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| features cs5231-3 500ma, 3.3v linear regulator with auxiliary control cs5231-3 description block diagram 1 1 1. no connect 2. v in 3. gnd 4. v out 5. auxdrv tab = gnd a company ? rev. 7/27/99 cherry semiconductor corporation 2000 south county trail, east greenwich, ri 02818 tel: (401)885-3600 fax: (401)885-5786 email: info@cherry-semi.com web site: www.cherry-semi.com the cs5231-3 combines a three-termi- nal linear regulator with circuitry con- trolling an external pfet transistor thus managing two input supplies. the part provides a 3.3v regulated output either from the main 5v sup- ply or a 3.3v auxiliary that switches on when the 5v supply is not present. this delivers constant, uninterrupted power to the load. the cs5231-3 meets intel?s ?instantly available? power requirements which follows from the ?advanced configuration and power interface? (acpi) stan- dards developed by intel, microsoft and toshiba. the cs5231-3 linear regulator pro- vides a fixed 3.3v output at 500ma with an overall accuracy of 2%. the internal npn-pnp composite pass transistor provides a low dropout voltage and requires less supply cur- rent than a straight pnp design. full protection with both current limit and thermal shutdown is provided. designed for low reverse current, the ic prevents excessive current from flowing from v out to either v in or ground when the regulator input volt- age is lower than the output voltage. the cs5231-3 can be used to provide power to an asic on a pci network interface card (nic). when the sys- tem enters a sleep state and the 5v input drops below 4.4v, the auxdrv control signal on the cs5231-3 is acti- vated turning on the external pfet. this switches the supply source from the 5v input to the 3.3v input through the pfet, guaranteeing a constant 3.3v output to the asic that is ?glitch free.? the cs5231-3 is available in two pack- age types: the 5-lead d 2 pak (to263) package and the 8-lead soic 4lead- fused (df) package. other applica- tions include desktop computers, power supplies with multiple input sources and pcmcia/pci interface cards. linear regulator 3.3v 2% output voltage 3ma quiescent current @ 500ma fast transient response current limit protection thermal shutdown with hysteresis 450a reverse output current system power management auxiliary supply control ?glitch free? transistion between two supplies ? + ? + internal bias bandgap reference thermal shutdown current limit v in 10k ? 50k ? auxdrv gnd v in uv comparator v ref error amp shutdown v out package options 5 lead d 2 pak 8 lead so narrow (internally fused leads) 1 nc gnd gnd v in auxdrv gnd gnd v out
electrical characteristics: 0c < t a < 70c, 0c < t j < 125c, 4.75v v cc < 6v, c out 10f with esr < 1 ? , i out = 10ma, u nless otherwise specified. parameter test conditions min typ max unit cs5231-3 2 absolute maximum ratings maximum operating junction temperature ........................................................................................ ..................................150c storage temperature range ...................................................................................................... ...............................-65c to +150c lead temperature soldering reflow (smd styles only) ...........................................................................................60 sec. max above 183c, 230c peak esd damage threshold (human body model)........................................................................................ ............................2kv pin symbol pin name v max v min i source i sink v in ic power input 14v -0.3v 100ma internally limited v out output voltage 6v -0.3v internally 100ma limited auxdrv auxiliary drive output 14v -0.3v 10ma 50ma gnd ic ground n/a n/a n/a n/a linear regulator output voltage 10ma < i out < 500ma 3.234 3.300 3.366 v -2% +2% line regulation i out = 10ma, 1 5 mv v in = 4.75v to 6v load regulation v in = 5v, 5 15 mv i out = 10ma to 500ma ground current i out = 10ma 2 3 ma i out = 500ma 3 6 ma reverse current v in = 0v, v out = 3.3v 0.45 1 ma current limit 0v < v out < 3.2v 0.55 0.85 1.2 a thermal shutdown note 1 150 180 210 c thermal shutdown hysteresis note 1 25 c auxiliary drive upper v in threshold increase v in until regulator turns on 4.35 4.5 4.65 v and auxdrv drives high lower v in threshold decrease v in until regulator turns off 4.25 4.4 4.55 v and auxdrv drives low v in threshold hysteresis 75 100 125 mv output low voltage i auxdrv = 100a, 0.1 0.4 v 1v < v in < 4.5v output low peak voltage increase v in from 0v to 1v. 0.65 0.9 v record peak auxdrv output voltage auxdrv current limit v auxdrv = 1v, 0.5 6 25 ma v in = 4.0v response time step v in from 5v to 4v, measure time 1 10 s for v auxdrv to drive low. note 1 pull-up/down resistance v in = 0v and v in > 4.7v 5 10 25 k ? note 1: guaranteed by design, not 100% production tested. thermal shutdown is 100% functionally tested at wafer probe. cs5231-3 package pin description package pin # pin symbol function 3 typical performance characteristics output voltage vs. junction temperature load regulation (mv) i out (a) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.0 0.2 0.4 125 c 27 c 0 c load regulation vs. i out over temperature line regulation vs. i out over temperature reverse current ( a) 390 380 370 360 0 20 40 60 80 100 120 junction temperature ( c) reverse current vs. junction temperature output voltage (v) 3.302 3.300 3.298 3.296 0 20 40 60 80 100 120 junction temperature ( c) i out = 10ma i out = 500ma line regulation ( v) i out (a) 80 70 60 50 40 0.0 0.2 0.4 27 c 0 c 125 c 4.75v theory of operation the cs5231-3 is a fixed 3.3v linear regulator that contains an auxiliary drive control feature. when v in is greater than the typical 4.5v threshold, the ic functions as a linear regu- lator. it provides up to 500ma of current to a load through a composite pnp-npn pass transistor. an output capacitor greater than 10f with equivalent series resistance less than 1 ? is required for compensation. more information is provided in the stability considerations section. the cs5231-3 provides an auxiliary drive feature that allows a load to remain powered even if the v in supply for the ic is absent. an external p-channel fet is the only additional component required to implement this function if an auxiliary power supply is available. the pfet gate is connected to the auxdrv lead. the pfet drain is connect- ed to the auxiliary power supply, and the pfet source is connected to the load. the polarity of this connection is very important, since the pfet body diode will be connect- ed between the load and the auxiliary supply. if the pfet is connected with its drain to the load and its source to the supply, the body diode will be forward-biased if the auxil- iary supply is turned off. this will result in the linear regu- lator providing current to everything on the auxiliary sup- ply rail. the auxdrv lead is internally connected to a 10k ? resistor and to a saturating npn transistor that acts as a switch. if the v in supply is off, the auxdrv output will connect the pfet gate to ground through the 10k ? resistor, and the pfet will conduct current to the load. as the v in supply begins to rise, the auxdrv lead will also rise until it reaches a typical voltage of about 650mv. the npn transistor connected to the auxdrv lead will saturate at this point, and the gate of the pfet will be pulled down to a typical voltage of about 100mv. the pfet will contin- ues to conduct current to the load. the v in supply voltage will continue to rise, but the linear regulator output is disabled until v in reaches a typical threshold of 4.5v. during this time, the load continues to be powered by the auxiliary driver. once the 4.5v v in threshold is reached, the saturating npn connected to the auxdrv lead turns off. the on-chip 10k ? pull-up resistor will pull the pfet gate up to v in , thus turning the pfet off. the linear regulator turns on at the same time. an external compensation capacitor is required for the linear regulator to be stable, and this capacitance also serves as a charge reservoir to minimize any ?glitching? that might result during the supply changeover. hysteresis is present in the auxdrv circuitry, requiring v in to drop by 100mv (typical) after the linear regulator is providing power to the load before the auxdrv circuitry can be re-enabled. cs5231-3 5 application information v in v out v auxdrv i out = startup 375ma figure 1. initial power-up, v aux not present r out = 8.8 ? . application circuit +5v pci c1 33 f v in gnd v out auxdrv cs5231-3 m1 +3.3v v aux c1 33 f c3 33 f asic v dd *indicates pfet body diode v in v out v auxdrv i out = 375ma v aux = 3.30v figure 2a. power-up, v aux = 3.30v. note the ?oscillatory performance? as the linear regulator charges the v out node. i out r ds(on) 130mv cs5231-3 6 stability considerations the output capacitor helps determine three main charac- teristics of a linear regulator: startup, transient response and stability. startup is affected because the output capacitor must be charged. at initial startup, the v in supply may not be pre- sent, and the output capacitor will be charged through the pfet. the pfet will initially provide current to the load through its body diode. the diode will act as a voltage fol- lower until sufficient voltage is present to turn the fet on. since most commercial power supplies have a fairly low ramp rate, charging through the body diode should effec- tively limit in-rush current to the capacitor. during normal operation, transient load current require- ments will be satisfied from the charge stored in the output capacitor until either the linear regulator or the auxiliary supply can respond. larger values of capacitance will improve transient response, but will also cost more. a lin- ear regulator will respond within microseconds, where an external power supply may take milliseconds to react. the output capacitance will provide the difference in current until this occurs. the result will be an instantaneous volt- age change at the output. this change is the product of the current change and the capacitor esr: application information: continued v in v out v auxdrv i out = 375ma v aux = 3.30 figure 3b. power-down, v aux = 3.135v. the difference in voltage is now i out r ds(on) plus the difference in supply voltages (3.30 -v aux ). v in v out v auxdrv i out = 375ma v aux = 3.465 v in v out v auxdrv i out = 375ma v aux = 3.135v v in v out v auxdrv i out = 375ma v aux = 3.135 figure 4a. power-up, v aux = 3.465v. i out r ds(on) is compensated by the higher value of v aux v in v out v auxdrv i out = 375ma v aux = 3.465 figure 2b. power-down, v aux = 3.30v. again, note ? v= i out r ds(on) 130mv. figure 3a. power-up, v aux = 3.135v. the ?oscillatory performance? mode lasts longer because the difference between v aux and 3.30 is greater. figure 4b. power-down, v aux = 3.465v. ? v out = ( ? i load ) (esr) this limitation directly affects load regulation. capacitor esr must be minimized if output voltage must be main- tained within tight tolerances. in such a case, it is often advisable to use a parallel network of different types of capacitors. for example, electrolytic capacitors provide high charge storage capacity in a small size, while tantalum capacitors have low esr. the parallel combination will result in a high capacity, low esr network. it is also impor- tant to physically locate the capacitance network close to the load, and to connect the network to the load with wide pc board traces to minimize the metal resistance. the cs5231-3 has been carefully designed to be stable for output capacitances greater than 10f with equivalent series resistance less than 1 ? . while careful board layout is important, the user should have a stable system if these constraints are met. a graph showing the region of stability for the cs5231-3 is included in the ?typical performance characteristics? section of this data sheet. input capacitors and the v in thresholds a capacitor placed on the v in pin will help to improve transient response. during a load transient, the input capacitor serves as a charge ?reservoir?, providing the needed extra current until the external power supply can respond. one of the consequences of providing this current is an instantaneous voltage drop at v in due to capacitor esr. the magnitude of the voltage change is again the product of the current change and the capacitor esr. it is very important to consider the maximum current step that can exist in the system. if the change in current is large enough, it is possible that the instantaneous voltage drop on v in will exceed the v in threshold hysteresis, and the ic will enter a mode of operation resembling an oscillation. as the part turns on, the output current i out will increase, reaching current limit during initial charging. increasing i out results in a drop at v in such that the shutdown threshold is reached. the part will turn off, and the load current will decrease. as i out decreases, v in will rise and the part will turn on, starting the cycle all over again. this oscillatory operation is most likely at initial startup when the output capacitance is not charged, and in cases where the ramp-up of the v in supply is slow. it may also occur during the power transition when the linear regulator turns on and the pfet turns off. a 15s delay exists between turn-on of the regulator and the auxdrv pin pulling the gate of the pfet high. this delay prevents ?chatter? during the power transitions. during this inter- val, the linear regulator will attempt to regulate the output voltage as 3.3v. if the output voltage is significantly below 3.3v, the ic will go into current limit while trying to raise v out . it is a short-lived phenomenon and is mentioned here to alert the user that the condition can exist. it is typi- cally not a problem in applications. careful choice of the pfet switch with respect to r ds(on) will minimize the volt- age drop which the output must charge through to return to a regulated state. more information is provided in the section on choosing the pfet switch. if required, using a few capacitors in parallel to increase the bulk charge storage and reduce the esr should give better performance than using a single input capacitor. short, straight connections between the power supply and v in lead along with careful layout of the pc board ground plane will reduce parasitic inductance effects. wide v in and v out traces will reduce resistive voltage drops. choosing the pfet switch the choice of the external pfet switch is based on two main considerations. first, the pfet should have a very low turn-on threshold. choosing a switch transistor with v gs(on) 1v ensures the pfet will be fully enhanced with only 3.3v of gate drive voltage. second, the switch transis- tor should be chosen to have a low r ds(on) to minimize the voltage drop due to current flow in the switch. the formu- la for calculating the maximum allowable on-resistance is r ds(on)(max) = where v aux(min) is the minimum value of the auxiliary supply voltage, v out(min) is the minimum allowable out- put voltage, i out(max) is the maximum output current and 1.5 is a ?fudge factor? to account for increases in r ds(on) due to temperature. output voltage sensing it is not possible to remotely sense the output voltage of the cs5231-3 since the feedback path to the error amplifier is not externally available. it is important to minimize volt- age drops due to metal resistance of high current pc board traces. such voltage drops can occur in both the supply traces and the return traces. the following board layout practices will help to minimize output voltage errors: always place the linear regulator as close to both load and output capacitors as possible. always use the widest possible traces to connect the lin- ear regulator to the capacitor network and to the load. connect the load to ground through the widest possible traces. connect the ic ground to the load ground trace at the point where it connects to the load. current limit the cs5231-3 has internal current limit protection. output current is limited to a typical value of 850ma, even under output short circuit conditions. if the load current drain exceeds the current limit value, the output voltage will be pulled down and will result in an out of regulation condi- tion. the ic does not contain circuitry to report this fault. thermal shutdown the cs5231-3 has internal temperature monitoring circuit- ry. the output is disabled if junction temperature of the ic reaches a typical value of 180c. thermal hysteresis is typi- v aux(min) ? v out(min) 1.5 i out(max) cs5231-3 7 application information: continued cally 25c and allows the ic to recover from a thermal fault without the need for an external reset signal. the monitoring circuitry is located near the composite pnp- npn output transistor, since this transistor is responsible for most of the on-chip power dissipation. the combina- tion of current limit and thermal shutdown will protect the ic from nearly any fault condition. reverse current protection during normal system operation, the auxiliary drive cir- cuitry will maintain voltage on the v out pin when v in is absent. ic reliability and system efficiency are improved by limiting the amount of reverse current that flows from v out to ground and from v out to v in . current flows from v out to ground through the feedback resistor divider that sets up the output voltage. this resistor can range in value from 6k ? to about 10k ? , and roughly 500a will flow in the typical case. current flow from v out to v in will be limited to leakage current after the ic shuts down. on-chip rc time constants are such that the output transistor should be turned off well before v in drops below the v out voltage. calculating power dissipation and heatsink requirements most linear regulators operate under conditions that result in high on-chip power dissipation. this results in high junction temperatures. since the ic has a thermal shut- down feature, ensuring the regulator will operate correctly under normal conditions is an important design considera- tion. some heatsinking will usually be required. thermal characteristics of an ic depend on four parame- ters: ambient temperature (t a in c), power dissipation (p d in watts), thermal resistance from the die to the ambi- ent air ( ja in c per watt) and junction temperature (t j in c). the maximum junction temperature is calculated from the formula below: t j(max) = t a(max) + ( ja ) (p d(max) ) maximum ambient temperature and power dissipation are determined by the design, while ja is dependent on the package manufacturer. the maximum junction tempera- ture for operation of the cs5231-3 within specification is 150c. the maximum power dissipation of a linear regula- tor is given as p d(max) = (v in(max) ? v out(min) ) (i load(max) ) + (v in (max) ) (i gnd(max) ) where i gnd(max) is the ic bias current. it is possible to change the effective value of ja by adding a heatsink to the design. a heatsink serves in some manner to raise the effective area of the package, thus improving the flow of heat from the package into the surrounding air. each material in the path of heat flow has its own charac- teristic thermal resistance, all measured in c per watt. the thermal resistances are summed to determine the total thermal resistance between the die junction and air. there are three components of interest: junction-to-case thermal resistance ( jc ), case-to-heatsink thermal resistance ( cs ) and heatsink-to-air thermal resistance ( sa ). the resulting equation for junction-to-air thermal resistance is ja = jc + cs + sa the values of jc for both packages of the cs5231-3 are provided in the packaging information section of this data sheet. the value of cs can be considered zero, since heat is conducted out of the d 2 pak package by the ic leads and the tab, and out of the soic package by its ic leads that are soldered directly to the pc board. modification of sa is the primary means of thermal man- agement. for surface mount components, this means mod- ifying the amount of trace metal that connects to the ic. the thermal capacity of pc board traces is dependent on how much copper area is used, whether or not the ic is in direct contact with the metal, whether or not the metal sur- face is coated with some type of sealant, and whether or not there is airflow across the pc board. the chart provid- ed below shows heatsinking capability of a square, single sided copper pc board trace. the area is given in square millimeters. it is assumed there is no airflow across the pc board. figure 5: thermal resistance capability of copper pc board metal traces typical d 2 pak pc board heatsink design a typical design of the pc board surface area needed for the d 2 pak package is shown on page 10. calculations were made assuming v in(max) =5.25v, v out(min) = 3.266v, i out(max) = 500ma, i gnd(max) = 5ma and t a = 70c. p d = (5.25v ? 3.266v) (0.5a) + (5.25v) (0.005a) = 1018mw maximum temperature rise ? t = t j(max) ? t a = 150c ? 70c = 80c. ja (worst case) = ? t/p d = 80c/1.018w = 78.56c/w first, we determine the need for heatsinking. if we assume the maximum ja = 50c/w for the d 2 pak, the maximum temperature rise is found to be ? t = (p d ) ( ja ) = (1.018w) (50c/w) = 50.9c this is less than the maximum specified operating junction temperature of 125c, and no heatsinking is required. since the d 2 pak has a large tab, mounting this part to the 70 60 50 40 30 20 10 0 0 2000 4000 6000 thermal resistance, c/w pc board trace area (mm 2 ) 8 cs5231-3 application information: continued pc board by soldering both tab and leads will provide superior performance with no pc board area penalty. typical 8 lead fused lead soic design we first determine the need for a heat sink for the 8 lead soic package at a load of 500ma. using the dissipation from the d 2 pak example of 1018mw and the ja of the soic package of 110c/w gives a temperature rise of 112c. adding this to an ambient temperature of 70c gives 182c junction temperature. this is an excessive tem- perature rise but it can be reduced by adding additional cooling in the form of added surface area of copper on the pcb. using the relationship of maximum temperature rise of ? t ja = t j(max) ? t a = 150c ? 70c = 80c. we calculate the thermal resistance allowed from junction to air: ja (worst case) = ? t ja /p d = 80c/1.018w = 79.6c/w. the thermal resistance from the die to the leads (case) is 25c/w. subtracting these two numbers gives the allow- able thermal resistance from case to ambient: ca = ja ? jc = 79.6c/w ? 25c/w = 54.6c/w the thermal resistance of this copper area will be 54.6c/w. we now look at figure 5 and find the pcb trace area that will be less than 54.5c/w. examination shows that 750mm 2 of copper will provide cooling for this part. this would be the soic part with the center 4 ground leads soldered to pads in the center of a copper area about 27mm 27mm. a lower dissipation or the addition of air- flow could result in a smaller required surface area. description the cs5231-3 application circuit has been implemented as shown in the following pages. the schematic, bill of mate- rials and printed circuit board artwork can be used to build the circuit. the design is very simple and consists of two capacitors, a p-channel fet and the cs5231-3. five turret pins are provided for connection of supplies, meters, oscil- loscope probes and loads. the cs5231-3 power supply management solution is implemented in an area less than 1.5 square inches. due to the simplicity of the design, out- put current must be derated if the cs5231-3 is operated at v in voltages greater than 7v. figure 6 provides the derat- ing curve on a maximum power dissipation if heatsink is added. operating at higher power dissipation without heatsink may result in a thermal shutdown condition. figure 6: demo board output current derating vs v in the v in connection the v in connection is denoted as such on the pc board. the maximum input voltage to the ic is 14v before dam- age to the ic is possible. however, the specification range for the ic is 4.75v < v in < 6v. the gnd connection the gnd connection ties the ic power return to two turret pins. the extra turret pin provides for connection of multi- ple instrument grounds to the demonstration board. the auxdrv connection the auxdrv lead of the cs5231-3 is connected to the gate of the external pfet. this connection is also brought to a turret pin to allow easy connection of an oscilloscope probe for viewing the auxdrv waveforms. the v aux connection the v aux turret pin provides a connection point between an external 3.3v supply and the pfet drain. the v out connection the v out connection is tied to the v out lead of the cs5231-3 and the pfet source. this point provides a con- venient point at which some type of lead may be applied. application circuit schematic c1 v in tp1 gnd tp2 tp3 tp5 tp6 auxdrv c2 v in gnd auxdrv v out cs5231-3 q1 tp4 +3.3v v aux u1 600 500 400 300 200 100 0 56 78 91011121314 v in (volts) i out (ma) application circuit characteristics cs5231-3 9 application circuit characteristics: continued 10 pc board layout artwork the pc board is a single layer copper design. the layout artwork is reproduced at actual size below. top copper layer top silk screen layer test descriptions the startup and supply transition waveforms shown in figures 1 through 4b were obtained using the application circuit board with a resistive load of 8.8 ? . this provides a dc load of 375ma when the regulated output voltage is 3.3v. a standard 2a bench supply was used to provide power to the application circuit. the transient response waveforms shown in the typical performance characteristics section were obtained by switching a 6.3 ? resistor across the output. temperature performance the graph below shows thermal performance for the cs5231-3 across the normal operating output current range. figure 7: package temperature vs load current (v in = 5v, t a =23 c) pfet r ds(on) performance the graph provided below show typical r ds(on) perfor- mance for the pfet. the data is provided as v ds vs i out for different values of v aux . figure 8: pfet vds vs i out 140 120 100 80 60 40 0 100 200 300 400 500 i out (ma) vds (mv) 160 20 0 v aux = 3.465v v aux = 3.135v v aux = 3.300v 50 45 40 35 30 25 0 50 100 150 200 250 300 350 400 450 500 load current (ma) package temperature (c) 20 55 aux.drv aux3.3v v out 3.3v gnd gnd v in 5v 2" 1.8" 2" 1.8" cs5231-3 11 application circuit bill of materials cs5231-3 refdes description part number manufacturer contact information c1, c2 33f, 16v tantalum capacitors tajd336k016 avx corp www.avxcorp.com 1-843-448-9411 q1 p-channel fet transistor mgsf1p02elt1 motorola www.mot-sps.com u1 linear regulator with auxiliary cs5231-3dps cherry semiconductor www.cherry-semi.com 1-800-272-3601 t1-t6 turret pins 40f6023 newark electronics www.newark.com 1-800-463-9275 12 thermal 5lead 8 lead so narrow data d 2 pak (internally fused leads) r jc typ 2.5 25 c/w r ja typ 10-50* 110 c/w *depending on thermal properties of substrate. r ja = r jc + r ca cherry semiconductor corporation reserves the right to make changes to the specifications without notice. please contact cherry semiconductor corporation for the latest available information. package dimensions in mm (inches) rev. 7/27/99 package specification package thermal data ordering information part number description CS5231-3GDP5 5 lead d 2 pak cs5231-3gdpr5 5 lead d 2 pak (tape & reel) cs5231-3gdf8 8 lead so narrow (internally fused leads) cs5231-3gdfr8 8 lead so narrow (internally fused leads) (tape & reel) ? 1999 cherry semiconductor corporation 5 lead d 2 pak (dp) 1.70 (.067) ref 0.10 (.004) 0.00 (.000) 10.31 (.406) 10.05 (.396) 0.91 (.036) 0.66 (.026) 1.40 (.055) 1.14 (.045) 4.57 (.180) 4.31 (.170) 1.68 (.066) 1.40 (.055) 2.74(.108) 2.49(.098) .254 (.010) ref 2.79 (.110) 2.29 (.090) 15.75 (.620) 14.73 (.580) 8.53 (.336) 8.28 (.326) surface mount narrow body (d); 150 mil wide 1.27 (.050) bsc 0.51 (.020) 0.33 (.013) 6.20 (.244) 5.80 (.228) 4.00 (.157) 3.80 (.150) 1.57 (.062) 1.37 (.054) d 0.25 (0.10) 0.10 (.004) 1.75 (.069) max 1.27 (.050) 0.40 (.016) ref: jedec ms-012 0.25 (.010) 0.19 (.008) d lead count metric english max min max min 8l so narrow 5.00 4.80 .197 .189 (internally fused leads) cs5231-3 |
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