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ddr3 sdram rdimm mt72jszs1g72pz - 8gb mt72jszs2g72pz - 16gb features ? ddr3 functionality and operations supported as defined in the component data sheet ? 240-pin, registered dual in-line memory module (rdimm) ? fast data transfer rates: pc3-12800, pc3-10600, pc3-8500, or pc3-6400 ? 8gb (1 gig x 72), 16gb (2 gig x 72) ? heat spreader ? v dd = 1.5v 0.075v ? v ddspd = +3.0v to +3.6v ? nominal and dynamic on-die termination (odt) for data and strobe signals ? quad rank, using 2gb and 4 gb twindie ? devices ? on-board i 2 c temperature sensor with integrated serial presence-detect (spd) eeprom ? 8 internal device banks ? fixed burst chop (bc) of 4 and burst length (bl) of 8 via the mode register set (mrs) ? gold edge contacts ? halogen-free ? fly-by topology ? terminated control, command, and address bus figure 1: 240-pin rdimm (r/c f) u1 u2 u3 u4 u5 u6 u7 u8 u9 u10 u11 u12 u13 u14 u15 u16 u17 u18 u19 u20 pcb height: 30.0mm (1.181in) options marking ? operating temperature 1 C commercial (0c t a +70c) none C industrial (C40c t a +85c) i ? package C 240-pin dimm (halogen-free) z ? frequency/cas latency C 1.25ns @ cl = 11 (ddr3-1600) -1g6 C 1.5ns @ cl = 9 (ddr3-1333) -1g4 C 1.5ns @ cl = 10 (ddr3-1333) 2 -1g3 C 1.87ns @ cl = 7 (ddr3-1066) -1g1 C 1.87ns @ cl = 8 (ddr3-1066) 2 -1g0 C 2.5ns @ cl = 5 (ddr3-800) 2 -80c C 2.5ns @ cl = 6 (ddr3-800) 2 -80b notes: 1. contact micron for industrial temperature module offerings. 2. not recommended for new designs. table 1: key timing parameters speed grade industry nomenclature data rate (mt/s) t rcd (ns) t rp (ns) t rc (ns) cl = 11 cl = 10 cl = 9 cl = 8 cl = 7 cl = 6 cl = 5 -1g6 pc3-12800 1600 1333 1333 1066 1066 800 667 13.125 13.125 48.125 -1g4 pc3-10600 C 1333 1333 1066 1066 800 667 13.125 13.125 49.125 -1g1 pc3-8500 C C C 1066 1066 800 667 13.125 13.125 50.625 -1g0 pc3-8500 C C C 1066 C 800 667 15 15 52.5 -80c pc3-6400 C C C C C 800 800 12.5 12.5 50 -80b pc3-6400 C C C C C 800 667 15 15 52.5 8gb, 16gb (x72, ecc, qr) 240-pin ddr3 sdram rdimm features pdf: 09005aef83a81483 rev. a 6/09 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice.
table 2: addressing parameter 8gb 16gb refresh count 8k 8k row address 16k a[13:0] 32k a[14:0] device bank address 8 ba[2:0] 8 ba[2:0] device configuration 2gb twindie (512 meg x 4) 4gb twindie (1 gig x 4) column address 2k a[11, 9:0] 2k a[11, 9:0] module rank address 4 s#[3:0] 4 s#[3:0] table 3: part numbers and timing parameters C 8gb modules base device: mt41j512m4thr, 1 2gb twindie ddr3 sdram part number 2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) mt72jszs1g72p(i)z-1g6__ 8gb 1 gig x 72 12.8 gb/s 1.25ns/1600 mt/s 11-11-11 mt72jszs1g72p(i)z-1g4__ 8gb 1 gig x 72 10.6 gb/s 1.5ns/1333 mt/s 9-9-9 mt72jszs1g72p(i)z-1g1__ 8gb 1 gig x 72 8.5 gb/s 1.87ns/1066 mt/s 7-7-7 mt72jszs1g72p(i)z-1g0__ 8gb 1 gig x 72 8.5 gb/s 1.87ns/1066 mt/s 8-8-8 mt72jszs1g72p(i)z-80c__ 8gb 1 gig x 72 6.4 gb/s 2.5ns/800 mt/s 5-5-5 mt72jszs1g72p(i)z-80b__ 8gb 1 gig x 72 6.4 gb/s 2.5ns/800 mt/s 6-6-6 table 4: part numbers and timing parameters C 16gb modules base device: mt41j1gm4thu, 1 4gb twindie ddr3 sdram part number 2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) mt72jszs2g72p(i)z-1g6__ 16gb 2 gig x 72 12.8 gb/s 1.25ns/1600 mt/s 11-11-11 mt72jszs2g72p(i)z-1g4__ 16gb 2 gig x 72 10.6 gb/s 1.5ns/1333 mt/s 9-9-9 mt72jszs2g72p(i)z-1g1__ 16gb 2 gig x 72 8.5 gb/s 1.87ns/1066 mt/s 7-7-7 mt72jszs2g72p(i)z-1g0__ 16gb 2 gig x 72 8.5 gb/s 1.87ns/1066 mt/s 8-8-8 mt72jszs2g72p(i)z-80c__ 16gb 2 gig x 72 6.4 gb/s 2.5ns/800 mt/s 5-5-5 mt72jszs2g72p(i)z-80b__ 16gb 2 gig x 72 6.4 gb/s 2.5ns/800 mt/s 6-6-6 notes: 1. the data sheet for the base device can be found on microns web site. 2. all part numbers end with a two-place code (not shown) that designates component and pcb revisions. consult factory for current revision codes. example: mt72jszs2g72pz-1g1 d1. 8gb, 16gb (x72, ecc, qr) 240-pin ddr3 sdram rdimm features pdf: 09005aef83a81483 rev. a 6/09 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
pin assignments and descriptions table 5: pin assignments 240-pin ddr3 rdimm front 240-pin ddr3 rdimm back pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1 v refdq 31 dq25 61 a2 91 dq41 121 v ss 151 v ss 181 a1 211 v ss 2 v ss 32 v ss 62 v dd 92 v ss 122 dq4 152 dqs12 182 v dd 212 dqs14 3 dq0 33 dqs3# 63 nf 93 dqs5# 123 dq5 153 dqs12# 183 v dd 213 dqs14# 4 dq1 34 dqs3 64 nf 94 dqs5 124 v ss 154 v ss 184 ck0 214 v ss 5 v ss 35 v ss 65 v dd 95 v ss 125 dqs9 155 dq30 185 ck0# 215 dq46 6 dqs0# 36 dq26 66 v dd 96 dq42 126 dqs9# 156 dq31 186 v dd 216 dq47 7 dqs0 37 dq27 67 v refca 97 dq43 127 v ss 157 v ss 187 event# 217 v ss 8 v ss 38 v ss 68 par_in 98 v ss 128 dq6 158 cb4 188 a0 218 dq52 9 dq2 39 cb0 69 v dd 99 dq48 129 dq7 159 cb5 189 v dd 219 dq53 10 dq3 40 cb1 70 a10 100 dq49 130 v ss 160 v ss 190 ba1 220 v ss 11 v ss 41 v ss 71 ba0 101 v ss 131 dq12 161 dqs17 191 v dd 221 dqs15 12 dq8 42 dqs8# 72 v dd 102 dqs6# 132 dq13 162 dqs17# 192 ras# 222 dqs15# 13 dq9 43 dqs8 73 we# 103 dqs6 133 v ss 163 v ss 193 s0# 223 v ss 14 v ss 44 v ss 74 cas# 104 v ss 134 dqs10 164 cb6 194 v dd 224 dq54 15 dqs1# 45 cb2 75 v dd 105 dq50 135 dqs10# 165 cb7 195 odt0 225 dq55 16 dqs1 46 cb3 76 s1# 106 dq51 136 v ss 166 v ss 196 a13 226 v ss 17 v ss 47 v ss 77 odt1 107 v ss 137 dq14 167 nu 197 v dd 227 dq60 18 dq10 48 v tt 78 v dd 108 dq56 138 dq15 168 reset# 198 nc 228 dq61 19 dq11 49 v tt 79 nc 109 dq57 139 v ss 169 cke1 199 v ss 229 v ss 20 v ss 50 cke0 80 v ss 110 v ss 140 dq20 170 v dd 200 dq36 230 dqs16 21 dq16 51 v dd 81 dq32 111 dqs7# 141 dq21 171 a15 201 dq37 231 dqs16# 22 dq17 52 ba2 82 dq33 112 dqs7 142 v ss 172 a14 202 v ss 232 v ss 23 v ss 53 err_out# 83 v ss 113 v ss 143 dqs11 173 vd dd 203 dqs13 233 dq62 24 dqs2# 54 v dd 84 dqs4# 114 dq58 144 dqs11# 174 a12 204 dqs13# 234 dq63 25 dqs2 55 a11 85 dqs4 115 dq59 145 v ss 175 a9 205 v ss 235 v ss 26 v ss 56 a7 86 v ss 116 v ss 146 dq22 176 v dd 206 dq38 236 v ddspd 27 dq18 57 v dd 87 dq34 117 sa0 147 dq23# 177 a8 207 dq39 237 sa1 28 dq19 58 a5 88 dq35 118 scl 148 v ss 178 a6 208 v ss 238 sda 29 v ss 59 a4 89 v ss 119 sa2 149 dq28 179 v dd 209 dq44 239 v ss 30 dq24 60 v dd 90 dq40 120 v tt 150 dq29 180 a3 210 dq45 240 v tt 8gb, 16gb (x72, ecc, qr) 240-pin ddr3 sdram rdimm pin assignments and descriptions pdf: 09005aef83a81483 rev. a 6/09 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 6: pin descriptions symbol type description a[15:0] input address inputs: provide the row address for activate commands, and the column ad- dress and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective bank. a10 is sampled during a precharge com- mand to determine whether the precharge applies to one bank (a10 low, bank selec- ted by ba[2:0]) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba. a12 is also used for bc4/bl8 identification as bl on-the-fly during cas commands. the address inputs also provide the op-code during the mode register com- mand set. a[13:0] addresses the 2gb ddr3 twindie devices. a[14:0] addresses the 4gb twindie devices. a15 is needed to calculate parity on the command/address bus. ba[2:0] input bank address inputs: ba[2:0] define the device bank to which an activate, read, write, or precharge command is being applied. ba[2:0] define which mode register (mr0, mr1, mr2, and mr3) is loaded during the load mode command. ba[1:0] are used as part of the parity calculation. ck0, ck0# input clock: ck and ck# are differential clock inputs. all control, command, and address input signals are sampled on the crossing of the positive edge of ck and the negative edge of ck#. cke[1:0] input clock enable: cke enables (registered high) and disables (registered low) internal circui- try and clocks on the dram. odt[1:0] input on-die termination: odt (registered high) enables termination resistance internal to the ddr3 sdram. when enabled, odt is only applied to the following pins: dq, dqs, dqs#, and dm. the odt input will be ignored if disabled via the load mode command. par_in input parity input: parity bit for the address, ras#, cas#, and we#. ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with s#) define the command being en- tered. reset# input (lvcmos) reset: reset# is an active low cmos input referenced to vss. the reset# input receiver is a cmos input defined as a rail-to-rail signal with dc high 0.8 v dd and dc low 0.2 v dd . s#[3:0] input chip select: s# enables (registered low) and disables (registered high) the command de- coder. sa[2:0] input presence-detect address inputs: these pins are used to configure the temperature sensor/ spd eeprom address range on the i 2 c bus. scl input serial clock for presence-detect: scl is used to synchronize communication to and from the temperature sensor/spd eeprom. cb[7:0] i/o check bits: data used for ecc. dq[63:0] i/o data input/output: bidirectional data bus. dqs[17:0], dqs#[17:0] i/o data strobe: dqs and dqs# are differential data strobes. output with read data. edge- aligned with read data. input with write data. center-aligned with write data. sda i/o serial data: sda is a bidirectional pin used to transfer addresses and data into and out of the temperature sensor/spd eeprom on the module on the i 2 c bus. err_out# output (open drain) parity error output: parity error found on the command and address bus. event# output (open drain) temperature event: the event# pin is asserted by the temperature sensor when critical temperature thresholds have been exceeded. v dd supply power supply: 1.5v 0.075v. 8gb, 16gb (x72, ecc, qr) 240-pin ddr3 sdram rdimm pin assignments and descriptions pdf: 09005aef83a81483 rev. a 6/09 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 6: pin descriptions (continued) symbol type description v ddspd supply serial eeprom positive power supply: +3.0v to +3.6v. the component v dd and v ddq are connected to the module v dd . v refca supply reference voltage: control, command, and address (v dd /2). v refdq supply reference voltage: dq, dm (v dd /2). v ss supply ground. v tt supply termination voltage: used for control, command, and address (v dd /2). nc C no connect: these pins are not connected on the module. nf C no function: connected within the module, but provides no functionality. nu C not used: these pins are not used in specific module configuration/operations. 8gb, 16gb (x72, ecc, qr) 240-pin ddr3 sdram rdimm pin assignments and descriptions pdf: 09005aef83a81483 rev. a 6/09 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
dq map table 7: component-to-module dq map component reference number component dq module dq module pin number component reference number component dq module dq module pin number u1 0 2 9 u2 0 10 18 1 0 3 1 8 12 2 3 10 2 11 19 3 1 4 3 9 13 u3 0 18 27 u4 0 26 36 1 16 21 1 24 30 2 19 28 2 27 37 3 17 22 3 25 31 u5 0 cb2 45 u8 0 34 87 1 cb0 39 1 32 81 2 cb3 46 2 35 88 3 cb1 40 3 33 82 u9 0 42 96 u10 0 50 105 1 40 90 1 48 99 2 43 97 2 51 106 3 41 91 3 49 100 u11 0 58 114 u12 0 5 123 1 56 108 1 6 128 2 59 115 2 4 122 3 57 109 3 7 129 u13 0 13 132 u14 0 21 141 1 14 137 1 22 146 2 12 131 2 20 140 3 15 138 3 23 147 u15 0 29 150 u16 0 cb5 159 1 30 155 1 cb6 164 2 28 149 2 cb4 158 3 31 156 3 cb7 165 u17 0 37 201 u18 0 45 210 1 38 206 1 46 215 2 36 200 2 44 209 3 39 207 3 47 216 u19 0 53 219 u20 0 61 228 1 54 224 1 62 233 2 52 218 2 60 227 3 55 225 3 63 234 8gb, 16gb (x72, ecc, qr) 240-pin ddr3 sdram rdimm dq map pdf: 09005aef83a81483 rev. a 6/09 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 7: component-to-module dq map (continued) component reference number component dq module dq module pin number component reference number component dq module dq module pin number u21 0 56 108 u22 0 48 99 1 58 114 1 50 105 2 57 109 2 49 100 3 59 115 3 51 106 u23 0 40 90 u24 0 32 81 1 42 96 1 34 87 2 41 91 2 33 82 3 43 97 3 35 88 u26 0 cb0 39 u27 0 24 30 1 cb2 45 1 26 36 2 cb1 40 2 25 31 3 cb3 46 3 27 37 u28 0 16 21 u29 0 8 12 1 18 27 1 10 18 2 17 22 2 9 13 3 19 28 3 11 19 u30 0 0 3 u31 0 62 233 1 2 9 1 61 228 2 1 4 2 63 234 3 3 10 3 60 227 u32 0 54 224 u33 0 46 215 1 53 219 1 45 210 2 55 225 2 47 216 3 52 218 3 44 209 u34 0 38 206 u35 0 cb6 164 1 37 201 1 cb5 159 2 39 207 2 cb7 165 3 36 200 3 cb4 158 u36 0 30 155 u37 0 22 146 1 29 150 1 21 141 2 31 156 2 23 147 3 28 149 3 20 140 u38 0 14 137 u39 0 6 128 1 13 132 1 5 123 2 15 138 2 7 129 3 12 131 3 4 122 8gb, 16gb (x72, ecc, qr) 240-pin ddr3 sdram rdimm dq map pdf: 09005aef83a81483 rev. a 6/09 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
functional block diagram figure 2: functional block diagram dq dq dq dq dm cs# dqs dqs# dq dq dq dq dm cs# dqs dqs# dq dq dq dq dm cs# dqs dqs# dq dq dq dq dm cs# dqs dqs# dq dq dq dq dm cs# dqs dqs# dq dq dq dq dm cs# dqs dqs# dq dq dq dq dm cs# dqs dqs# dq dq dq dq dm cs# dqs dqs# dq dq dq dq dm cs# dqs dqs# dq dq dq dq u39t dm cs# dqs dqs# dq dq dq dq u38t dm cs# dqs dqs# dq dq dq dq u37t dm cs# dqs dqs# dq dq dq dq u36t dm cs# dqs dqs# dq dq dq dq dm cs# dqs dqs# dq dq dq dq u33t dm cs# dqs dqs# dq dq dq dq u32t dm cs# dqs dqs# dq dq dq dq u31t dm cs# dqs dqs# dq dq dq dq u34t dm cs# dqs dqs# u35t dq dq dq dq dm cs# dqs dqs# dq dq dq dq dm cs# dqs dqs# dq dq dq dq dm cs# dqs dqs# dq dq dq dq dm cs# dqs dqs# dq dq dq dq dm cs# dqs dqs# dq dq dq dq dm cs# dqs dqs# dq dq dq dq dm cs# dqs dqs# dq dq dq dq dm cs# dqs dqs# dq dq dq dq dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq dq0 dq1 dq2 dq3 dq dq dq dq u1 t u1 b dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq dq4 dq5 dq6 dq7 dq dq dq dq u12t dm cs# dqs dqs# dqs0 dqs0# dqs9 dqs9# dm cs# dqs dqs# dq dq dq dq dq8 dq9 dq10 dq11 dq dq dq dq u2t u2b dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq dq12 dq13 dq14 dq15 dq dq dq dq u13t dm cs# dqs dqs# dqs1 dqs1# dqs10 dqs10# dm cs# dqs dqs# dq dq dq dq dq16 dq17 dq18 dq19 dq dq dq dq u3t u3b dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq dq20 dq21 dq22 dq23 dq dq dq dq u14t dm cs# dqs dqs# dqs2 dqs2# dqs11 dqs11# dm cs# dqs dqs# dq dq dq dq dq24 dq25 dq26 dq27 dq dq dq dq u4b u4t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq dq28 dq29 dq30 dq31 dq dq dq dq u15t dm cs# dqs dqs# dqs3 dqs3# dqs12 dqs12# dm cs# dqs dqs# dq dq dq dq dq dq dq dq dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq dq dq dq dq dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq dq32 dq33 dq34 dq35 dq dq dq dq u9t u9b dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq dq36 dq37 dq38 dq39 dq dq dq dq u18t dm cs# dqs dqs# dqs4 dqs4# dqs13 dqs13# dm cs# dqs dqs# dq dq dq dq dq40 dq41 dq42 dq43 dq dq dq dq u10t u10b dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq dq44 dq45 dq46 dq47 dq dq dq dq u19t dm cs# dqs dqs# dqs5 dqs5# dqs14 dqs14# dm cs# dqs dqs# dq dq dq dq dq48 dq49 dq50 dq51 dq dq dq dq u11t u11b dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq dq52 dq53 dq54 dq55 dq dq dq dq u20t dm cs# dqs dqs# dqs6 dqs6# dqs15 dqs15# dm cs# dqs dqs# dq dq dq dq dq56 dq57 dq58 dq59 dq dq dq dq u8t u8b dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq dq60 dq61 dq62 dq63 dq dq dq dq u17t dm cs# dqs dqs# dqs7 dqs7# dqs16 dqs16# v ss rs0# rs1# rs2# rs3# cb0 cb1 cb2 cb3 u5t u5b cb4 cb5 cb6 cb7 u16t dqs8 dqs8# dqs17 dqs17# dq dq dq dq u30b dm cs# dqs dqs# dq dq dq dq u29b dm cs# dqs dqs# dq dq dq dq u28b dm cs# dqs dqs# dq dq dq dq u27b dm cs# dqs dqs# dq dq dq dq dm cs# dqs dqs# dq dq dq dq u23b dm cs# dqs dqs# dq dq dq dq u22b dm cs# dqs dqs# dq dq dq dq u21b dm cs# dqs dqs# dq dq dq dq u24b dm cs# dqs dqs# u26b zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss r e g i s t e r a n d p l l s0# s1# s2# s3# ba[2:0] a[15:0] ras# cas# we# cke0 cke1 odt0 odt1 par_in reset# ck0 ck0# rs0#: rank 0 rs1#: rank 1 rs2#: rank 2 rs3#: rank 3 rba[2:0]: ddr3 sdram ra[13:0]: ddr3 sdram rras#: ddr3 sdram rcas#: ddr3 sdram rwe#: ddr3 sdram rcke0: rank 0, rank 2 rcke1: rank 1, rank 3 rodt0: rank 0, rank 2 rodt1: rank 1 and rank 3 tied to v ss at sdram err_out# u7, u25 v refca v ss ddr3 sdram ddr3 sdram v dd ddr3 sdram v ddspd t emperature sensor/spd eeprom v tt ddr3 sdram ddr3 sdram v refdq ck ck# ddr3 sdram ddr3 sdram rank 0: u1bCu11b, u12bCu20b rank 1: u1tCu11t, u12tCu20t rank 2: u21bCu30b, u31bCu39b rank 3: u21tCu30t, u31tCu39t rs#[3:0], rcke[1:0], ra[13:0], rras#, rcas#, rwe#, rodt[1:0], rba[2:0] ck ck# clock, command, control, and address clock line terminations: ddr3 sdram v tt ddr3 sdram v dd u6 a0 t emperature sensor/ spd eeprom a1 a2 sa0 sa1 sda scl evt event# u30 t u29t u28t u27t u23t u22t u21t u24t u26t u39b u38b u37b u36b u33b u32b u31b u34b u35b u12b u13b u14b u15b u18b u19b u20b u17b u16b sa2 note: 1. the zq ball on each ddr3 component is connected to an external 240 1% resistor that is tied to ground. it is used for the calibration of the components odt and output driver. 8gb, 16gb (x72, ecc, qr) 240-pin ddr3 sdram rdimm functional block diagram pdf: 09005aef83a81483 rev. a 6/09 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
general description ddr3 sdram modules are high-speed, cmos dynamic random access memory mod- ules that use internally configured 8-bank ddr3 sdram devices. ddr3 sdram mod- ules use ddr architecture to achieve high-speed operation. ddr3 architecture is essentially an 8 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr3 sdram module effectively consists of a single 8 n -bit-wide, one-clock-cycle data transfer at the internal dram core and eight corresponding n-bit-wide, one-half-clock-cycle data trans- fers at the i/o pins. ddr3 modules use two sets of differential signals: dqs, dqs# to capture data and ck and ck# to capture commands, addresses, and control signals. differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals. fly-by topology ddr3 modules use faster clock speeds than earlier ddr technologies, making signal quality more important than ever. for improved signal quality, the clock, control, com- mand, and address buses have been routed in a fly-by topology, where each clock, control, command, and address pin on each dram is connected to a single trace and terminated (rather than a tree structure, where the termination is off the module near the connector). inherent to fly-by topology, the timing skew between the clock and dqs signals can be easily accounted for by using the write-leveling feature of ddr3. registering clock driver operation registered ddr3 sdram modules use a registering clock driver device consisting of a register and a phase-lock loop (pll). the device complies with the jedec standard definition of the sste32882 registering clock driver with parity and quad chip se- lects for ddr3 rdimm applications. the register section of the registering clock driver latches command and address input signals on the rising clock edge. the pll section of the registering clock driver receives and redrives the differential clock signals (ck, ck#) to the ddr3 sdram devices. the register(s) and pll reduce clock, control, command, and address signals loading by iso- lating dram from the system controller. parity operations the registering clock driver can accept a parity bit from the systems memory control- ler, providing even parity for the control, command, and address bus. parity errors are flagged on the err_out# pin. systems not using parity are expected to function without issue if par_in and err_out# are left as no connects to the system. 8gb, 16gb (x72, ecc, qr) 240-pin ddr3 sdram rdimm general description pdf: 09005aef83a81483 rev. a 6/09 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
temperature sensor with serial presence-detect eeprom thermal sensor operations the temperature from the integrated thermal sensor is monitored and converts into a digital word via the i 2 c bus. system designers can use the user-programmable registers to create a custom temperature-sensing solution based on system requirements. pro- gramming and configuration details comply with jedec standard no. 21-c page 4.7-1 definition of the tse2002av, serial presence detect with temperature sensor. serial presence-detect eeprom operation ddr3 sdram modules incorporate serial presence-detect. the spd data is stored in a 256-byte eeprom. the first 128 bytes are programmed by micron to comply with je- dec standard jc-45 appendix x: serial presence detect (spd) for ddr3 sdram modules. these bytes identify module-specific timing parameters, configuration infor- mation, and physical attributes. user-specific information can be written into the remaining 128 bytes of storage. read/write operations between the system (master) and the eeprom (slave) device occur via an i 2 c bus. write protect (wp) is connected to v ss , permanently disabling hardware write protect. for further information please refer to micron technical note tn-04-42, "memory module serial presence-detect." 8gb, 16gb (x72, ecc, qr) 240-pin ddr3 sdram rdimm general description pdf: 09005aef83a81483 rev. a 6/09 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
electrical specifications stresses greater than those listed may cause permanent damage to the module. this is a stress rating only, and functional operation of the module at these or any other condi- tions outside those indicated in each devices data sheet is not implied. exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. table 8: absolute maximum ratings symbol parameter min max units v dd v dd supply voltage relative to v ss C0.4 +1.975 v v in , v out voltage on any pin relative to v ss C0.4 +1.975 v table 9: operating conditions symbol parameter min nom max units notes v dd v dd supply voltage 1.425 1.5 1.575 v i vtt termination reference current from v tt C600 C +600 ma v tt termination reference voltage (dc) C command/address bus 0.49 v dd - 20mv 0.5 v dd 0.51 v dd + 20mv v 1 i i input leakage current; any input 0v v in v dd ; v ref input 0v v in 0.95v (all other pins not under test = 0v) address inputs, ras#, cas#, we#, s#, cke, odt, ba, ck, ck# tbd tbd tbd a i oz output leakage current; 0v v out v dd ; dq and odt are disabled; odt is high dq, dqs, dqs# C20 0 +20 a i vref v ref supply leakage current; v refdq = v dd /2 or v refca = v dd /2 (all other pins not under test = 0v) C72 0 +72 a t a module ambient operating temperature commer- cial 0 C +70 c 2, 3 industrial C40 C +85 c t c ddr3 sdram component case operating temperature commer- cial 0 C +95 c 2, 3, 4 industrial C40 C +95 c notes: 1. v tt termination voltage in excess of the stated limit will adversely affect the command and address signals voltage margin and will reduce timing margins. 2. t a and t c are simultaneous requirements. 3. for further information, refer to technical note tn-00-08: thermal applications, available on microns web site. 4. the refresh rate is required to double when 85c < tc 95c. 8gb, 16gb (x72, ecc, qr) 240-pin ddr3 sdram rdimm electrical specifications pdf: 09005aef83a81483 rev. a 6/09 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
dram operating conditions recommended ac operating conditions are given in the ddr3 component data sheets. component specifications are available on microns web site. module speed grades cor- relate with component speed grades, as shown below. table 10: module and component speed grades ddr3 components may exceed the listed module speed grades; module may not be available in all listed speed grades module speed grade component speed grade -1g6 -125 -1g4 -15e -1g1 -187e -1g0 -187 -80c -25e -80b -25 design considerations simulations micron memory modules are designed to optimize signal integrity through carefully de- signed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. however, good signal integrity starts at the system level. mi- cron encourages designers to simulate the signal characteristics of the systems memo- ry bus to ensure adequate signal integrity of the entire memory system. power operating voltages are specified at the dram, not at the edge connector of the module. designers must account for any system voltage drops at anticipated power levels to en- sure the required supply voltage is maintained. i dd specifications table 11: ddr3 i cdd specifications and conditions C 8gb values are for the mt41j128m8 ddr3 sdram only and are computed from values specified in the 2gb twindie (512 meg x 4) component data sheet parameter com- bined symbol 1600 1333 1066 800 units operating current 0: one bank activate-to- precharge i cdd0 tbd 3222 2862 2592 ma operating current 1: one bank activate-to- read-to-precharge i cdd1 tbd 3582 3222 2952 ma precharge power-down current: slow exit i cdd2p tbd 864 864 864 ma precharge power-down current: fast exit i cdd2p tbd 1368 1278 1188 ma precharge quiet standby current i cdd2q tbd 2592 2340 2088 ma precharge standby current i cdd2n tbd 2862 2502 2322 ma 8gb, 16gb (x72, ecc, qr) 240-pin ddr3 sdram rdimm electrical specifications pdf: 09005aef83a81483 rev. a 6/09 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 11: ddr3 i cdd specifications and conditions C 8gb (continued) values are for the mt41j128m8 ddr3 sdram only and are computed from values specified in the 2gb twindie (512 meg x 4) component data sheet parameter com- bined symbol 1600 1333 1066 800 units precharge standby odt current i cdd2nt tbd 3222 2862 2592 ma active power-down current i cdd3p tbd 1368 1278 1188 ma active standby current i cdd3n tbd 2808 2538 2358 ma burst read operating current i cdd4r tbd 5292 4392 3762 ma burst write operating current i cdd4w tbd 5652 4932 4302 ma refresh current i cdd5b tbd 6012 5472 5022 ma self refresh temperature current: max t c = 85c i cdd6 tbd 432 432 432 ma self refresh temperature current (srt-enabled): max t c = 95c i cdd6et tbd 648 648 648 ma all banks interleaved read current i cdd7 tbd 7362 6012 5562 ma reset current i cdd8 tbd 1008 1008 1008 ma table 12: ddr3 i cdd specifications and conditions C 16gb values are for the mt41j1g4 ddr3 sdram only and are computed from the values specified in the 4gb twindie (1 gig x 4) component data sheet parameter com- bined symbol 1600 1333 1066 800 units operating current 0: one bank activate-to- precharge i cdd0 tbd 3132 2772 2412 ma operating current 1: one bank activate-to- read-to-precharge i cdd1 tbd 3582 3132 2772 ma precharge power-down current: slow exit i cdd2p tbd 864 864 864 ma precharge power-down current: fast exit i cdd2p tbd 1278 1188 1188 ma precharge quiet standby current i cdd2q tbd 2862 2502 2142 ma precharge standby current i cdd2n tbd 2772 2412 2052 ma precharge standby odt current i cdd2nt tbd 3222 2862 2412 ma active power-down current i cdd3p tbd 1458 1368 1278 ma active standby current i cdd3n tbd 3042 2592 2232 ma burst read operating current i cdd4r tbd 5112 4212 3402 ma burst write operating current i cdd4w tbd 5742 4842 3942 ma refresh current i cdd5b tbd 6282 5922 5382 ma self refresh temperature current: max t c = 85c i cdd6 tbd 648 648 648 ma self refresh temperature current (srt-enabled): max t c = 95c i cdd6et tbd 864 864 864 ma all banks interleaved read current i cdd7 tbd 7992 6732 6012 ma 8gb, 16gb (x72, ecc, qr) 240-pin ddr3 sdram rdimm electrical specifications pdf: 09005aef83a81483 rev. a 6/09 en 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 12: ddr3 i cdd specifications and conditions C 16gb (continued) values are for the mt41j1g4 ddr3 sdram only and are computed from the values specified in the 4gb twindie (1 gig x 4) component data sheet parameter com- bined symbol 1600 1333 1066 800 units reset current i cdd8 tbd 1008 1008 1008 ma 8gb, 16gb (x72, ecc, qr) 240-pin ddr3 sdram rdimm electrical specifications pdf: 09005aef83a81483 rev. a 6/09 en 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
registering clock driver specifications table 13: registering clock driver electrical characteristics sste32882 devices or equivalent symbol parameter pins min nom max units v dd dc supply voltage C 1.425 1.5 1.575 v v ref dc reference voltage C 0.49 v dd - 20mv 0.5 v dd 0.51 v dd + 20mv v v tt dc termination voltage C 0.49 v dd - 20mv 0.5 v dd 0.51 v dd + 20mv v v ih(ac) ac high-level input voltage control, command, address v ref + 175mv C v dd + 400mv v v il(ac) ac low-level input voltage control, command, address C0.4 C v ref - 175mv v v ih(dc) dc high-level input voltage control, command, address v ref + 100mv C v dd + 0.4 v v il(dc) dc low-level input voltage control, command, address C0.4 C v ref - 100mv v v ih(cmos) high-level input voltage reset#, mirror 0.65 v dd C v dd v v il(cmos) low-level input voltage reset#, mirror 0 C 0.35 v dd v v ix(ac) differential input cross point voltage range ck, ck#, fbin, fbin# 0.5 v dd - 175mv 0.5 v dd 0.5 v dd + 175mv v v id(ac) differential input voltage ck, ck# 350 C v dd + tbd mv i oh high-level output current err_out# C C tbd ma i ol low-level output current err_out# tbd C tbd ma note: 1. timing and switching specifications for the register listed are critical for proper opera- tion of the ddr3 sdram rdimms. these are meant to be a subset of the parameters for the specific device used on the module. 8gb, 16gb (x72, ecc, qr) 240-pin ddr3 sdram rdimm registering clock driver specifications pdf: 09005aef83a81483 rev. a 6/09 en 15 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
temperature sensor with serial presence-detect eeprom the temperature sensor continuously monitors the modules temperature and can be read back at any time over the i 2 c bus shared with the spd eeprom. table 14: temperature sensor with serial presence-detect eeprom operating conditions parameter/condition symbol min max units supply voltage v ddspd +3.0 +3.6 v supply current: v dd = 3.3v i dd C +2.0 ma input high voltage: logic 1; scl, sda v ih +1.45 v ddspd + 1 v input low voltage: logic 0; scl, sda v il C +0.55 v output low voltage: i out = 2.1ma v ol C +0.4 v input current i in C5.0 +5.0 a temperature sensing range C C40 +125 c temperature sensor accuracy (class b) C C1.0 +1.0 c table 15: sensor and eeprom serial interface timing parameter/condition symbol min max units time bus must be free before a new transition can start t buf 4.7 C s sda fall time t f 20 300 ns sda rise time t r C 1,000 ns data hold time t hd:dat 200 900 ns start condition hold time t h:sta 4.0 C s clock high period t high 4.0 50 s clock low period t low 4.7 C s scl clock frequency t scl 10 100 khz data setup time t su:dat 250 C ns start condition setup time t su:sta 4.7 C s stop condition setup time t su:sto 4.0 C s event# pin the temperature sensor also adds the event# pin (open drain). not used by the spd eeprom, event# is a temperature sensor output used to flag critical events that can be set up in the sensors configuration register. event# has three defined modes of operation: interrupt mode, compare mode, and critical temperature mode. the open-drain output of event# under the three separate operating modes is illustrated below. event thresholds are programmed in the 0x01 reg- ister using a hysteresis. the alarm window provides a comparison window, with upper and lower limits set in the alarm upper boundary register and the alarm lower boun- dary register, respectively. when the alarm window is enabled, event# will trigger whenever the temperature is outside the min or max values set by the user. 8gb, 16gb (x72, ecc, qr) 240-pin ddr3 sdram rdimm temperature sensor with serial presence-detect eeprom pdf: 09005aef83a81483 rev. a 6/09 en 16 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
the interrupt mode enables software to reset event# after a critical temperature thresh- old has been detected. threshold points are set in the configuration register by the user. this mode triggers the critical temperature limit and both the min and max of the tem- perature window. the compare mode is similar to the interrupt mode, except event# cannot be reset by the user and only returns to the logic high state when the temperature falls below the programmed thresholds. critical temperature mode triggers event# only when the temperature has exceeded the programmed critical trip point. when the critical trip point has been reached, the temperature sensor goes into comparator mode, and the critical event# cannot be cleared through software. sm bus slave subaddress decoding the temperature sensors physical address differs from the spd eeproms physical ad- dress: binary 0011 for a0, a1, a2, and rw#, where a2, a1, and a0 are the three slave subaddress pins and the rw# bit is the read/write flag. if the slave base address is fixed for the temperature sensor/spd eeprom, then the pins set the subaddress bits of the slave address, enabling the devices to be located any- where within the eight slave address locations. for example, they could be set from 30h to 3eh. 8gb, 16gb (x72, ecc, qr) 240-pin ddr3 sdram rdimm temperature sensor with serial presence-detect eeprom pdf: 09005aef83a81483 rev. a 6/09 en 17 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 3: event# pin functionality time temperature critical alarm window (max) alarm window (min) event# interrupt mode event# comparator mode event# critical temperature only mode clears event hysteresis affects these trip points table 16: temperature sensor registers name address power-on default pointer register not applicable undefined capability register 0x00 0x0001 configuration register 0x01 0x0000 alarm temperature upper boundary register 0x02 0x0000 alarm temperature lower boundary register 0x03 0x0000 critical temperature register 0x04 0x0000 temperature register 0x05 undefined pointer register the pointer register selects which of the 16-bit registers is being accessed in subsequent read and write operations. this register is a write-only register. 8gb, 16gb (x72, ecc, qr) 240-pin ddr3 sdram rdimm temperature sensor with serial presence-detect eeprom pdf: 09005aef83a81483 rev. a 6/09 en 18 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 17: pointer register bits 0C7 bit 7 6 5 4 3 2 1 0 0 0 0 0 register select register select register select register select table 18: pointer register bits 0C2 descriptions bit register 2 1 0 0 0 0 capability register 0 0 1 configuration register 0 1 0 alarm temperature upper boundary register 0 1 1 alarm temperature lower boundary register 1 0 0 critical temperature register 1 0 1 temperature register capability register the capability register indicates the features and functionality supported by the temper- ature sensor. this register is a read-only register. table 19: capability register (address: 0x00) bit 15 14 13 12 11 10 9 8 rfu rfu rfu rfu rfu rfu rfu rfu bit 7 6 5 4 3 2 1 0 rfu rfu rfu temperature resolution wider range precision has alarm and critical temperature table 20: capability register bit description bit description 0 basic capability 1: has alarm and critical trip point capabilities 1 accuracy 0: 2c over the active range and 3c over the monitor range 1: 1c over the active range and 2c over the monitor range 2 wider range 0: temperatures lower than 0c are clamped to a binary value of 0 1: temperatures below 0c can be read 8gb, 16gb (x72, ecc, qr) 240-pin ddr3 sdram rdimm temperature sensor with serial presence-detect eeprom pdf: 09005aef83a81483 rev. a 6/09 en 19 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 20: capability register bit description (continued) bit description 4:3 temperature resolution 00: 0.5c lsb 01: 0.25c lsb 10: 0.125c lsb 11: 0.0625c lsb 15:5 0: must be set to zero configuration register table 21: configuration register (address: 0x01) bit 15 14 13 12 11 10 9 8 rfu rfu rfu rfu rfu hysteresis shutdown mode bit 7 6 5 4 3 2 1 0 critical lock bit alarm lock bit clear event event output status event output control critical event only event polarity event mode table 22: configuration register bit descriptions bit description notes 0 event mode 0: comparator mode 1: interrupt mode event mode cannot be changed if either of the lock bits is set. 1 event# polarity 0: active low 1: active high event# polarity cannot be changed if either of the lock bits is set. 2 critical event only 0: event# trips on alarm or critical temperature event 1: event# trips only if critical temperature is reached 3 event output control 0: event output disabled 1: event output enabled 4 event status 0: event# has not been asserted by this device 1: event# is being asserted due to an alarm window or critical temperature condition this is a read-only field in the register. the event caus- ing the event can be determined from the read tem- perature register. 5 clear event 0: no effect 1: clears the event when the temperature sensor is in the interrupt mode 8gb, 16gb (x72, ecc, qr) 240-pin ddr3 sdram rdimm temperature sensor with serial presence-detect eeprom pdf: 09005aef83a81483 rev. a 6/09 en 20 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 22: configuration register bit descriptions (continued) bit description notes 6 alarm window lock bit 0: alarm trips are not locked and can be changed 1: alarm trips are locked and cannot be changed 7 critical trip lock bit 0: critical trip is not locked and can be changed 1: critical trip is locked and cannot be changed 8 shutdown mode 0: enabled 1: shutdown the shutdown mode is a power-saving mode that dis- ables the temperature sensor. 10:9 hysteresis enable 00: disable 01: enable at 1.5c 10: enable at 3c 11: enable at 6c when enabled, a hysteresis is applied to temperature movement around the trip points (see figure 4 (page 22)). as an example, if the hysteresis register is enabled to a delta of 6c, the preset trip points will toggle when the temperature reaches the program- med value. these values will reset when the tempera- ture drops below the trip points minus the set hysteresis level. in this case, this would be critical tem- perature minus 6c. the hysteresis is applied to both the above alarm win- dow and the below alarm window bits found in the read-only temperature register (see table 23 (page 22)). event# is also affected by this register. 8gb, 16gb (x72, ecc, qr) 240-pin ddr3 sdram rdimm temperature sensor with serial presence-detect eeprom pdf: 09005aef83a81483 rev. a 6/09 en 21 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
figure 4: hysteresis applied to temperature around trip points t h 1 t l 2 t h - hyst 3 t l - hyst below window bit above window bit notes: 1. t h is the value set in the alarm temperature upper boundary trip register. 2. t l is the value set in the alarm temperature lower boundary trip register. 3. hyst is the value set in the hysteresis bits of the configuration register. table 23: hysteresis applied to alarm window bits in the temperature register condition below alarm window bit above alarm window bit temperature gradient critical temperature temperature gradient critical temperature sets falling t l - hyst rising t h clears rising t l falling t h - hyst temperature format the temperature trip point registers and temperature readout register use a 2s comple- ment format to enable negative numbers. the least significant bit (lsb) is equal to 0.0625c or 0.25c, depending on which register is referenced. for example, assuming an lsb of 0.0625c: ? a value of 0x018c would equal 24.75c ? a value of 0x06c0 would equal 108c ? a value of 0x1e74 would equal C24.75c 8gb, 16gb (x72, ecc, qr) 240-pin ddr3 sdram rdimm temperature sensor with serial presence-detect eeprom pdf: 09005aef83a81483 rev. a 6/09 en 22 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
temperature trip point registers the upper and lower temperature boundary registers are used to set the maximum and minimum values of the alarm window. lsb for these registers is 0.25c. all rfu bits in the register will always report zero. table 24: alarm temperature lower boundary register (address: 0x02) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 msb lsb rfu rfu alarm window upper boundary temperature table 25: alarm temperature lower boundary register (address: 0x03) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 msb lsb rfu rfu alarm window lower boundary temperature critical temperature register the critical temperature register is used to set the maximum temperature above the alarm window. the lsb for this register is 0.25c. all rfu bits in the register will always report zero. table 26: critical temperature register (address: 0x04) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 msb lsb rfu rfu critical temperature trip point temperature register the temperature register is a read-only register that provides the current temperature detected by the temperature sensor. the lsb for this register is 0.0625c with a resolu- tion of 0.0625c. the most significant bit (msb) is 128c in the readout section of this register. the upper three bits of the register are used to monitor the trip points that are set in the previous three registers. 8gb, 16gb (x72, ecc, qr) 240-pin ddr3 sdram rdimm temperature sensor with serial presence-detect eeprom pdf: 09005aef83a81483 rev. a 6/09 en 23 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 27: temperature register (address: 0x05) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 above critical trip above alarm window below alarm window msb lsb temperature table 28: temperature register bit descriptions bit description 13 below alarm window 0: temperature is equal to or above the lower boundary 1: temperature is below alarm window 14 above alarm window 0: temperature is equal to or below the upper boundary 1: temperature is above alarm window 15 above critical trip point 0: temperature is below critical trip point 1: temperature is above critical trip point serial presence-detect data for the latest serial presence-detect data, refer to micron's spd page: www.micron.com/ spd . 8gb, 16gb (x72, ecc, qr) 240-pin ddr3 sdram rdimm temperature sensor with serial presence-detect eeprom pdf: 09005aef83a81483 rev. a 6/09 en 24 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
module dimensions figure 5: 240-pin ddr3 rdimm 30.5 (1.2) 29.85 (1.175) pin 1 17.3 (0.68) typ 2.5 (0.098) d (2x) 2.3 (0.091) typ 5.0 (0.197) typ 123.0 (4.84) typ 1.0 (0.039) typ 0.8 (0.031) typ 0.75 (0.03) r (8x) 0.76 (0.03) r pin 120 front view 133.50 (5.256) 133.20 (5.244) 47.0 (1.85) typ 71.0 (2.79) typ 9.5 (0.374) typ back view pin 240 pin 121 1.37 (0.054) 1.17 (0.046) 4.0 (0.157) max 2.2 (0.087) typ 1.45 (0.057) typ 3.05 (0.12) typ 54.68 (2.15) typ 3.0 (0.118) 4x typ 23.3 (0.92) typ 0.5 (0.02) r (4x) 0.9 (0.035) typ 1.0 (0.039) r (8x) 15.0 (0.59) typ (4x) u1 u2 u3 u4 u5 u6 u7 u8 u9 u10 u11 u12 u13 u14 u15 u16 u17 u18 u19 u20 u21 u22 u23 u24 u26 u27 u28 u29 u30 u31 u32 u33 u34 u35 u36 u37 u38 u39 3.1 (0.122) 2x typ 5.1 (0.2) typ 7.25 (0.285) max* with heat spreader u1 u2 u3 u4 u5 u6 u7 u8 u9 u10 u11 u12 u13 u14 u15 u16 u17 u18 u19 u20 u21 u22 u23 u24 u26 u27 u28 u29 u30 u31 u32 u33 u34 u35 u36 u37 u38 u39 1.37 (0.054) 1.17 (0.046) * at clips edge, max width is 8.32mm (0.328in) u25 u25 notes: 1. all dimensions are in millimeters (inches); max/min or typical (typ) where noted. 2. the dimensional diagram is for reference only. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. twindie is a trademark of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 8gb, 16gb (x72, ecc, qr) 240-pin ddr3 sdram rdimm module dimensions pdf: 09005aef83a81483 rev. a 6/09 en 25 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.

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