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? 2007 microchip technology inc. ds21483d-page 1 tc9400/9401/9402 features: voltage-to-frequency ? choice of linearity: - tc9401: 0.01% - tc9400: 0.05% - tc9402: 0.25% ? dc to 100 khz (f/v) or 1 hz to 100 khz (v/f) ? low power dissipation: 27 mw (typ.) ? single/dual supply operation: - +8v to +15v or 4v to 7.5v ? gain temperature stability: 25 ppm/c (typ.) ? programmable scale factor frequency-to-voltage ? operation: dc to 100 khz ? choice of linearity: - tc9401: 0.02% - tc9400: 0.05% - tc9402: 0.25% ? programmable scale factor applications: ? microprocessor data acquisition ? 13-bit analog-to-digital converters (adc) ? analog data transmission and recording ? phase locked loops ? frequency meters/tachometer ? motor control ? fm demodulation general description: the tc9400/9401/9402 are low-cost voltage-to-fre- quency (v/f) converters, utilizing low-power cmos technology. the converters accept a variable analog input signal and generate an output pulse train, whose frequency is linearly proportional to the input voltage. the devices can also be used as highly accurate frequency-to-voltage (f/v) converters, accepting virtually any input frequency waveform and providing a linearly proportional voltage output. a complete v/f or f/v sy stem only requires the addition of two capacitors, three resistors, and refer- ence voltage. package type 1 2 3 4 5 6 7 14 13 12 11 10 9 8 v dd nc amplifier out threshold detector freq/2 out output common pulse freq out i bias zero adj i in v ss v ref out gnd v ref 1 2 3 4 5 6 7 14 13 12 11 10 9 8 tc9400 tc9401 tc9402 14-pin plastic dip/cerdip 14-pin soic tc9400 tc9401 tc9402 nc = no internal connection v dd nc amplifier out threshold detector freq/2 out output common pulse freq out i bias zero adj i in v ss v ref out gnd v ref voltage-to-frequency / frequency-to-voltage converters
tc9400/9401/9402 ds21483d-page 2 ? 2007 microchip technology inc. functional block diagram i in i ref tc9400 r in integrator op amp integrator capacitor threshold detector one shot pulse output pulse/2 output 2 input voltage reference capacitor reference voltage
? 2007 microchip technology inc. ds21483d-page 3 tc9400/9401/9402 1.0 electrical characteristics absolute maximum ratings ? v dd ? v ss ......................................................................+18v i in ..................................................................................10 ma v out max ? v out common.................................................23v v ref ? v ss .....................................................................-1.5v storage temperature range.........................-65c to +150c operating temperature range: c device ...................................................... 0c to +70c e device....................................................-40c to +85c package dissipation (t a 70c): 8-pin cerdip ........................................................800 mw 8-pin plastic dip ..................................................730 mw 8-pin soic ...........................................................470 mw ? stresses above those listed under ?absolute maximum ratings? may cause permanent dam age to the device. these are stress ratings only and f unctional operation of the device at these or any other conditions above those indicated in the operation sections of the spec ifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. tc940x electrical specifications electrical characteristics: unless otherwise specified, v dd = +5v, v ss = -5v, v gnd = 0v, v ref = -5v, r bias = 100 k , full scale = 10 khz. t a = +25c, unless temperature range is specified (-40c to +85c for e dev ice, 0c to +70c for c device). parameter min typ max min typ max min typ max units test conditions voltage-to-frequency accuracy tc9400 tc9401 tc9402 linearity 10 khz ? 0.01 0.05 ? 0.004 0.01 ? 0.05 0.25 % full scale output deviation from straight line between normalized zero and full scale input linearity 100 khz ? 0.1 0.25 ? 0.04 0.08 ? 0.25 0.5 % full scale output deviation from straight line between normalized zero read- ing and full scale input gain temperature drift (note 1) ? 25 40 ? 25 40 ? 50 100 ppm/c full scale variation in gain a due to temperature change gain variance ? 10 ? ? 10 ? ? 10 ? % of nominal variation from ideal accuracy zero offset (note 2) ? 10 50 ? 10 50 ? 20 100 mv correction at zero adjust for zero output when input is zero zero temperature drift (note 1) ? 25 50 ? 25 50 ? 50 100 v/c variation in zero offset due to temperature change note 1: full temperature range; not tested. 2: i in = 0. 3: full temperature range, i out = 10 ma. 4: i out = 10 a. 5: threshold detect = 5v, amp out = 0v, full temperature range. 6: 10 hz to 100 khz; not tested. 7: 5 s minimum positive pulse width and 0.5 s minimum negative pulse width. 8: t r = t f = 20 ns. 9: r l 2k , tested @ 10 k . 10: full temperature range, v in = -0.1v.
tc9400/9401/9402 ds21483d-page 4 ? 2007 microchip technology inc. analog input i in full scale ? 10 ? ? 10 ? ? 10 ? a full scale analog input current to achieve specified accuracy i in over range ? ? 50 ? ? 50 ? ? 50 a over range current response time ? 2 ? ? 2 ? ? 2 ? cycle settling time to 0.1% full scale digital section tc9400 tc9401 tc9402 v sat @ i ol = 10ma ? 0.2 0.4 ? 0.2 0.4 ? 0.2 0.4 v logic ?0? output voltage (note 3) v out max ? v out common (note 4) ? ? 18 ? ? 18 ? ? 18 v voltage range between output and common pulse frequency output width ?3??3??3 ? s frequency-to-voltage supply current i dd quiescent (note 5) ? 1.5 6 ? 1.5 6 ? 3 10 ma current required from positive supply during operation i ss quiescent (note 5) ? -1.5 -6 ? -1.5 -6 ? -3 -10 ma current required from negative supply during operation v dd supply 4 ? 7.5 4 ? 7.5 4 ? 7.5 v operating range of positive supply v ss supply -4 ? -7.5 -4 ? -7.5 -4 ? -7.5 v operating range of negative supply reference voltage v ref ? v ss -2.5 ? ? -2.5 ? ? -2.5 ? ? v range of voltage reference input accuracy non-linearity (note 10) ? 0.02 0.05 ? 0.01 0.02 ? 0.05 0.25 % full scale deviation from ideal transfer function as a percentage full scale voltage input frequency range (notes 7 and 8) 10 ? 100k 10 ? 100k 10 ? 100k hz frequency range for specified non-linearity tc940x electrical spec ifications (continued) electrical characteristics: unless otherwise specified, v dd = +5v, v ss = -5v, v gnd = 0v, v ref = -5v, r bias = 100 k , full scale = 10 khz. t a = +25c, unless temperature range is specified (-40c to +85c for e device, 0c to +70c for c device). parameter min typ max min typ max min typ max units test conditions note 1: full temperature range; not tested. 2: i in = 0. 3: full temperature range, i out = 10 ma. 4: i out = 10 a. 5: threshold detect = 5v, amp out = 0v, full temperature range. 6: 10 hz to 100 khz; not tested. 7: 5 s minimum positive pulse width and 0.5 s minimum negative pulse width. 8: t r = t f = 20 ns. 9: r l 2k , tested @ 10 k . 10: full temperature range, v in = -0.1v.
? 2007 microchip technology inc. ds21483d-page 5 tc9400/9401/9402 frequency input positive excursion 0.4 ? v dd 0.4 ? v dd 0.4 ? v dd v voltage required to turn threshold detector on negative excursion -0.4 -2 -0.4 ? -2 -0.4 ? -2 v voltage required to turn threshold detector off minimum positive pulse width (note 8) ?5??5??5 ? s time between threshold crossings minimum negative pulse width (note 8) ? 0.5 ? ? 0.5 ? ? 0.5 ? s time between threshold crossings input impedance ? 10 ? ? 10 ? ? 10 m analog outputs tc9400 tc9401 tc9402 output voltage (note 9) ?v dd ? 1 ? ? v dd ? 1 ? ? v dd ? 1 ? v voltage range of op amp output for specified non-linearity output loading 2 ? ? 2 ? ? 2 ? ? k resistive loading at output of op amp supply current tc9400 tc9401 tc9402 i dd quiescent (note 10) ? 1.5 6 ? 1.5 6 ? 3 10 ma current required from positive supply during operation i ss quiescent (note 10) ? -1.5 -6 -1.5 -6 ? -3 -10 ma current required from negative supply during operation v dd supply 4 ? 7.5 4 ? 7.5 4 ? 7.5 v operating range of positive supply v ss supply -4 ? -7.5 -4 ? -7.5 -4 ? -7.5 v operating range of negative supply reference voltage v ref ? v ss -2.5 ? ? -2.5 ? ? -2.5 ? ? v range of voltage reference input tc940x electrical spec ifications (continued) electrical characteristics: unless otherwise specified, v dd = +5v, v ss = -5v, v gnd = 0v, v ref = -5v, r bias = 100 k , full scale = 10 khz. t a = +25c, unless temperature range is specified (-40c to +85c for e dev ice, 0c to +70c for c device). parameter min typ max min typ max min typ max units test conditions note 1: full temperature range; not tested. 2: i in = 0. 3: full temperature range, i out = 10 ma. 4: i out = 10 a. 5: threshold detect = 5v, amp out = 0v, full temperature range. 6: 10 hz to 100 khz; not tested. 7: 5 s minimum positive pulse width and 0.5 s minimum negative pulse width. 8: t r = t f = 20 ns. 9: r l 2k , tested @ 10 k . 10: full temperature range, v in = -0.1v.
tc9400/9401/9402 ds21483d-page 6 ? 2007 microchip technology inc. 2.0 pin descriptions the descriptions of the pins are listed in table 2-1 . table 2-1: pin function table 2.1 bias current (i bias ) an external resistor, connected to v ss , sets the bias point for the tc9400. specifications for the tc9400 are based on r bias = 100 k 10%, unless otherwise noted. increasing the maximum frequency of the tc9400 beyond 100 khz is limited by the pulse width of the pulse output (typically 3 s). reducing r bias will decrease the pulse width and increase the maximum operating frequency, but linearity errors will also increase. r bias can be reduced to 20 k , which will typically produce a maximum full scale frequency of 500 khz. 2.2 zero adjust this pin is the non-inverting input of the operational amplifier. the low frequency set point is determined by adjusting the voltage at this pin. 2.3 input current (i in ) the inverting input of the operational amplifier and the summing junction when connected in the v/f mode. an input current of 10 a is specified, but an over range current up to 50 a can be used without detrimental effect to the circuit operation. i in connects the summing junction of an operational amplifier. voltage sources cannot be attached directly, but must be buffered by external resistors. 2.4 voltage capacitor (v ref out) the charging current for c ref is supplied through this pin. when the op amp output reaches the threshold level, this pin is internally connected to the reference voltage and a charge, equal to v ref x c ref , is removed from the integrator capacitor. after about 3 sec, this pin is internally connected to the summing junction of the op amp to discharge c ref . break-before-make switch- ing ensures that the reference voltage is not directly applied to the summing junction. 2.5 voltage reference (v ref ) a reference voltage from either a precision source, or the v ss supply is applied to this pin. accuracy of the tc9400 is dependent on the voltage regulation and temperature characteristics of the reference circuitry. since the tc9400 is a charge balancing v/f converter, the reference current will be equal to the input current. for this reason, the dc impedance of the reference voltage source must be kept low enough to prevent linearity errors. for linearity of 0.01%, a reference impedance of 200 or less is recommended. a 0.1 f bypass capacitor should be connected from v ref to ground. pin no. symbol description 1i bias this pin sets bias current in the tc9400. connect to v ss through a 100 k resistor. 2 zero adj low frequency adjustment input. 3i in input current connection for the v/f converter. 4v ss negative power supply voltage connection, typically -5v. 5v ref out reference capacitor connection. 6 gnd analog ground. 7v ref voltage reference input, typically -5v. 8 pulse freq out frequency output. this open drain output will pulse low each time the freq. threshold detector limit is reached. the pul se rate is proportional to input voltage. 9output common source connection for the open drain output fets. 10 freq/2 out this open drain output is a square wave at one-half the frequency of the pulse output (pin 8). output transitions of this pin occur on the rising edge of pin 8. 11 threshold detector input to the threshold detector. this pi n is the frequency input during f/v operation. 12 amplifier out output of the integrator amplifier. 13 nc no internal connection. 14 v dd positive power supply connection, typically +5v.
? 2007 microchip technology inc. ds21483d-page 7 tc9400/9401/9402 2.6 pulse freq out this output is an open-drain n-channel fet, which provides a pulse waveform whose frequency is propor- tional to the input voltage. this output requires a pull- up resistor and interfaces directly with mos, cmos, and ttl logic (see figure 2-1 ). 2.7 output common the sources of both the freq/2 out and the pulse freq out are connected to this pin. an output level swing from the drain voltage to ground, or to the v ss supply, may be obtained by connecting this pin to the appropriate point. 2.8 freq/2 out this output is an open-drain n-channel fet, which provides a square-wave one-half the frequency of the pulse frequency output. the freq/2 out output will change state on the rising edge of pulse freq out. this output requires a pull- up resistor and interfaces directly with mos, cmos, and ttl logic. 2.9 threshold detector input in the v/f mode, this input is connected to the ampli- fier out output (pin 12) and triggers a 3 s pulse when the input voltage passes through its threshold. in the f/v mode, the input frequency is applied to this input. the nominal threshold of the detector is half way between the power supplies, or (v dd + v ss )/2 400 mv. the tc9400?s charge balancing v/f technique is not dependent on a precision comparator threshold, because the threshold only sets the lower limit of the op amp output. the op amp?s peak-to-peak output swing, which determines the frequency, is only influenced by external capacitors and by v ref . 2.10 amplifier out this pin is the output stage of the operational amplifier. during v/f operation, a negative going ramp signal is available at this pin. in the f/v mode, a voltage proportional to the frequency input is generated. figure 2-1: output waveforms. 3ms typ. 1/f f out f out /2 amp out v ref 0v c ref c int note 1: to adjust f min , set v in = 10 mv and adjust the 50 k offset for 10 hz output. 2: to adjust f max , set v in = 10v and adjust r in or v ref for 10 khz output. 3: to increase f outmax to 100 khz, change c ref to 2 pf and c int to 75 pf. 4: for high performance applications, use high stability components for r in , c ref . v ref (metal film resistors and glass capacitors). also, separate output ground (pin 9) from input ground (pin 6).
tc9400/9401/9402 ds21483d-page 8 ? 2007 microchip technology inc. 3.0 detailed description 3.1 voltage-to-frequency (v/f) circuit description the tc9400 v/f converter operates on the principal of charge balancing. the operation of the tc9400 is easily understood by referring to figure 3-1 . the input voltage (v in ) is converted to a current (i in ) by the input resistor. this current is then converted to a charge on the integrating capacitor and shows up as a linearly decreasing voltage at the output of the op amp. the lower limit of the output swing is set by the threshold detector, which causes the reference voltage to be applied to the reference capacitor for a time period long enough to charge the capacitor to the reference volt- age. this action reduces t he charge on the integrating capacitor by a fixed amount (q = c ref x v ref ), causing the op amp output to step up a finite amount. at the end of the charging period, c ref is shorted out. this dissipates the charge stored on the reference capacitor, so that when th e output again crosses zero, the system is ready to recycle. in this manner, the con- tinued discharging of the integrating capacitor by the input is balanced out by fixed charges from the refer- ence voltage. as the input voltage is increased, the number of reference pulses required to maintain balance increases, which causes the output frequency to also increase. since each charge increment is fixed, the increase in frequency with voltage is linear. in addition, the accuracy of the output pulse width does not directly affect the linearity of the v/f. the pulse must simply be long enough for full charge transfer to take place. the tc9400 contains a ?self-start? circuit to ensure the v/f converter always operates properly when power is first applied. in the event that, during power-on, the op amp output is below the threshold and c ref is already charged, a positive voltage step will not occur. the op amp output will continue to decrease until it crosses the -3.0v threshold of the ?self-start? comparator. when this happens, an internal resistor is connected to the op amp input, which forces the output to go positive until the tc9400 is in its normal operating mode. the tc9400 utilizes low-power cmos processing for low input bias and offset currents, with very low power dissipation. the open drain n-channel output fets provide high voltage and high current sink capability. figure 3-1: 10 hz to 10 khz v/f converter. ? + +5v + 5v 14 v dd + 5v r l 10 k r l 10 k 8 10 9 f out f out /2 11 3ms delay self- start 12 5 20 k 60 pf op amp c int 820 pf c ref 180 pf 12 pf r in 1m v in +5v -5v 50 k 510 k 10 k 3 1 offset adjust i in zero adjust 0v ?10v i bias v ss 4 -5v 2 output common v ref out r bias 100 k amp out tc9400 tc9401 tc9402 gnd 6 threshold detector threshold detect reference voltage (typically -5v) 2 v ref 7 -3v input
? 2007 microchip technology inc. ds21483d-page 9 tc9400/9401/9402 3.2 voltage-to-time measurements the tc9400 output can be measured in the time domain as well as the frequency domain. some micro- computers, for example, hav e extensive timing capabil- ity, but limited counter capability. also, the response time of a time domain measurement is only the period between two output pulses, while the frequency measurement must accumulate pulses during the entire counter time-base period. time measurements can be made from either the tc9400?s pulse freq out output, or from the freq/2 out output. the freq/2 out output changes state on the rising edge of pulse freq out, so freq/2 out is a symmetrical square wave at one-half the pulse output frequency. timing measure- ments can, therefore, be made between successive pulse freq out pulses, or while freq/2 out is high (or low).
tc9400/9401/9402 ds21483d-page 10 ? 2007 microchip technology inc. 4.0 voltage-to-frequency (v/f) converter design information 4.1 input/output relationships the output frequency (f out ) is related to the analog input voltage (v in ) by the transfer equation: equation 4-1: 4.2 external component selection 4.2.1 r in the value of this component is chosen to give a full scale input current of approximately 10 a: equation 4-2: equation 4-3: note that the value is an approximation and the exact relationship is defined by the transfer equation. in practice, the value of r in typically would be trimmed to obtain full scale frequency at v in full scale (see section 4.3 ?adjustment procedure? , adjustment procedure). metal film resistors with 1% tolerance or better are recommended for high accuracy applications because of their thermal stability and low noise generation. 4.2.2 c int the exact value is not crit ical but is related to c ref by the relationship: 3c ref c int 10c ref improved stability and linearity are obtained when c int 4c ref . low leakage types are recommended, although mica and ceramic devices can be used in applications where their temperature limits are not exceeded. locate as close as possible to pins 12 and 13. 4.2.3 c ref the exact value is not critical and may be used to trim the full scale frequency (see section 6.1 ?input/out- put relationships? , input/output relationships). glass film or air trimmer capacitors are recommended because of their stability and low leakage. locate as close as possible to pins 5 and 3 (see figure 4-1 ). figure 4-1: recommended c ref vs. v ref . 4.2.4 v dd , v ss power supplies of 5v are recommended. for high accuracy requirements, 0.05% line and load regulation and 0.1 f disc decoupling capacitors, located near the pins, are recommended. 4.3 adjustment procedure figure 3-1 shows a circuit for trimming the zero location. full scale may be trimmed by adjusting r in , v ref , or c ref . recommended procedure for a 10 khz full scale frequency is as follows: 1. set v in to 10 mv and trim the zero adjust circuit to obtain a 10 hz output frequency. 2. set v in to 10v and trim either r in , v ref , or c ref to obtain a 10 khz output frequency. if adjustments are performed in this order, there should be no interaction and they should not have to be repeated. 4.4 improved single supply v/f converter operation a tc9400, which operates from a single 12 to 15v variable power source, is shown in figure 4-2 . this circuit uses two zener diodes to set stable biasing levels for the tc9400. the zener diodes also provide the reference voltage, so the output impedance and temperature coefficient of t he zeners will directly affect power supply rejection and temperature performance. full scale adjustment is accomplished by trimming the input current. frequency out v in r in -------- 1 v ref () c ref () ------------------------------------ ? = v in full scale 10 a r in ? 10v 10 a r in ? = 1 m 500 400 300 200 100 0 -1 -2 -3 -4 -5 -6 -7 v ref (v) c ref (pf) +12pf 10 khz 100 khz v dd = +5v v ss = -5v r in = 1mw v in = +10v t a = +25c
? 2007 microchip technology inc. ds21483d-page 11 tc9400/9401/9402 trimming the reference voltage is not recommended for high accuracy applications unless an op amp is used as a buffer, because the tc9400 requires a low- impedance reference (see section 2.5 ?voltage ref- erence (vref)? , v ref pin description, for more infor- mation). the circuit of figure 4-2 will directly interface with cmos logic operating at 12v to 15v. ttl or 5v cmos logic can be accommodated by connecting the output pull-up resistors to the +5v supply. an optoisolator can also be used if an isolated output is required; also, see figure 4-3 . figure 4-2: voltage-to-frequency. r1 910 k r4 1f d2 5.1 vz r2 910 k r5 91 k rp offset 20 k 100 k d1 5.1 vz 0.1 f 100 k c ref c int 1.2 k +12 to +15v 10 10 k output frequency digital ground analog ground input voltage (0 to 10v) r3 gain tc9400 11 12 5 3 2 6 7 1 4 14 9 10 8 threshold detect amp out c ref i in zero adjust gnd v ref i bias output common f out /2 f out v dd v ss 100 k k component selection f/s freq. c ref c int 1 khz 2200 pf 4700 pf 10 khz 180 pf 470 pf 100 khz 27 pf 75 pf
tc9400/9401/9402 ds21483d-page 12 ? 2007 microchip technology inc. figure 4-3: fixed voltage ? single supply operation. v+ = 8v to 15v (fixed) 14 8 10 k 10 k f out f out /2 10 149 100 k 0v?10v i in 180 pf 820 pf 3 5 12 11 7 0.01 f 2 k 8.2 k 6 2 v2 r2 0.9 r1 0.2 r 1 r in 1m i in v ref tc9400 offset adjust gain adjust 5v 0.01 f v in v+ r 1 r 2 10v 1 m 10 k 12v 1.4 m 14 k 15v 2 m 20 k f out i in 1 v 2 v 7 ? () c ref () ----------------------------------------- - = i in v in v 2 ? () r in ------------------------- - v + v 2 ? () 0.9 r 1 0.2 r 1 + () -------------------------------------- - + =
? 2007 microchip technology inc. ds21483d-page 13 tc9400/9401/9402 5.0 frequency-to-voltage (f/v) circuit description when used as an f/v converter, the tc9400 generates an output voltage linearly proportional to the input frequency waveform. each zero crossing at the threshold detector?s input causes a precise amoun t of charge (q = c ref x v ref ) to be dispensed into the op amp?s summing junction. this charge, in turn, flows through the feedback resistor, generating voltage pu lses at the output of the op amp. a capacitor (c int ) across r int averages these pulses into a dc voltage, which is linearly proportional to the input frequency.
tc9400/9401/9402 ds21483d-page 14 ? 2007 microchip technology inc. 6.0 f/v converter design information 6.1 input/output relationships the output voltage is related to the input frequency (f in ) by the transfer equation: equation 6-1: the response time to a change in f in is equal to (r int c int ). the amount of ripple on v out is inversely proportional to c int and the input frequency. c int can be increased to lower the ripple. values of 1 f to 100 f are perfectly acceptable for low frequen- cies. when the tc9400 is used in the single supply mode, v ref is defined as the voltage difference between pin 7 and pin 2. 6.2 input voltage levels the input frequency is applied to the threshold detector input (pin 11). as discussed in the v/f circuit section of this data sheet, the threshold of pin 11 is approximately (v dd + v ss )/2 400 mv. pin 11?s input voltage range extends from v dd to about 2.5v below the threshold. if the voltage on pin 11 goes more than 2.5 volts below the threshold, the v/f mode start-up comparator will turn on and corrupt the output voltage. the threshold detector input has about 200 mv of hysteresis. in 5v applications, the input voltage levels for the tc9400 are 400 mv, minimum. if the frequency source being measured is unipolar, such as ttl or cmos operating from a +5v source, then an ac coupled level shifter should be used. one such circuit is shown in figure 6-1 (a). the level shifter circuit in figure 6-1 (b) can be used in single supply f/v applications. the resistor divider ensures that the input threshold will track the supply voltages. the diode clamp prevents the input from going far enough in the negative direction to turn on the start-up comparator. the diode?s forward voltage decreases by 2.1 mv/c, so for high ambient temperature operation, tw o diodes in series are recommended. figure 6-1: frequency input level shifter. v out = [v ref c ref r int ] f in +5v 14 64 +5v -5v v dd 1.0 11 33 k in914 v ss det tc9400 (a) 5v supply (b) single supply 0.01 f frequency input 0v gnd +8v to +15v 14 10 k 4 +5v v dd 1.0 11 33 k in914 v ss det tc9400 0.01 f frequency input 0v 0.1 f 10 k m m
? 2007 microchip technology inc. ds21483d-page 15 tc9400/9401/9402 figure 6-2: f/v single supply f/v converter. 6.3 input buffer f out and f out /2 are not used in the f/v mode. how- ever, these outputs may be useful for some applica- tions, such as a buffer to feed additional circuitry. then, f out will follow the input frequency waveform, except that f out will go high 3 s after f in goes high; f out /2 will be square wave with a frequency of one-half f out . if these outputs are not used, pins 8, 9 and 10 should be connected to ground (see figure 6-3 and figure 6-4 ). figure 6-3: f/v digital outputs. offset adjust 10 k .01 f 6.2v in914 33 k 100 k 500 k 0.1 f 100 k v+ = 10v to 15v 1 47 pf v out frequency input tc9400 6 10 k 2 11 1.0 4 14 12 3 5 gnd v ref out i in zero adjust v ref i bias amp out v dd v ss gnd 6 7 1.0 k v+ 1.0 k 0.01 f .001 f det note: the output is referenced to pin 6, which is at 6.2v (vz). for frequency meter applications, a 1 ma meter with a series scaling resi stor can be placed across pins 6 and 12. m m 0.5 ms min 5.0 ms min delay = 3 ms input f out f out /2
tc9400/9401/9402 ds21483d-page 16 ? 2007 microchip technology inc. figure 6-4: dc ? 10 khz converter. 6.4 output filtering the output of the tc9400 has a sawtooth ripple super- imposed on a dc level. the ripple will be rejected if the tc9400 output is converted to a digital value by an integrating analog-to-digital converter, such as the tc7107. the ripple can also be reduced by increasing the value of the integrating capacitor, although this will reduce the response time of the f/v converter. the sawtooth ripple on the output of an f/v can be eliminated without affecting the f/v?s response time by using the circuit in figure 6-1 . the circuit is a capacitance multiplier, where the output coupling capacitor is multiplied by the ac gain of the op amp. a moderately fast op amp, such as the tl071, should be used. figure 6-5: ripple filter. tc9400a tc9401a tc9402a +5v 14 v dd v+ v+ f out /2 f out output common 10 9 8 5 3 12 12 pf c ref 56 pf c int 1000 pf r int 1m 60 pf amp out v out v ss i bias 14 10 k 2.2 k 100 k 2k -5v +5v zero adjust 2 7 (typically -5v) v ref f in 11 threshold detector 3ms delay * * * *optional if buffer is needed offset adjust v ref out i in 42 ? + op amp + v ref see figure 7-1: frequency input level shifter 6 gnd threshold detect 1 47 pf v out tc9400 12 3 5 v ref out i in gnd amp out 6 .001 f + ? 1 3 2 .01 f 1m 0.1 f +5 7 6 4 -5 tl071 200 m m
? 2007 microchip technology inc. ds21483d-page 17 tc9400/9401/9402 7.0 f/v power-on reset in f/v mode, the tc9400 output voltage will occasion- ally be at its maximum value when power is first applied. this condition remains until the first pulse is applied to f in . in most frequency measurement applications, this is not a problem because proper operation begins as soon as the frequency input is applied. in some cases, however, the tc9400 output must be zero at power-on without a frequency input. in such cases, a capacitor connected from pin 11 to v dd will usually be sufficient to pulse the tc9400 and provide a power-on reset (see figure 7-1 (a) and (b)). where predictable power-on operation is critical, a more complicated circuit, such as figure 7-1 (b), may be required. figure 7-1: power-on operation/reset. v dd 14 11 1000 pf threshold detector 1k f in v dd 100 k 1f 3 4 8 6 f in 1 2 5 16 v cc b r c q v ss a clra cd4538 tc9400 (a) (b) to tc9400
tc9400/9401/9402 ds21483d-page 18 ? 2007 microchip technology inc. 8.0 package information 8.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part nu mber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e xxxxxxxxxxxxxx yywwnnn 14-lead cerdip xxxxxxxxxxxxxx 0731256 example: (front view) tc9400ejd 14-lead pdip xxxxxxxxxxxxxx xxxxxxxxxxxxxx yywwnnn example: (front view) 14-lead soic (.150?) xxxxxxxxxxx xxxxxxxxxxx yywwnnn example: (front view) y2026 example: (back view) y2026 example: (back view) tc9400 cpd ^^ 0731256 3 e tc9400 eod ^^ 0731256 example: (back view) 3 e y2026
? 2007 microchip technology inc. ds21483d-page 19 tc9400/9401/9402 14-lead ceramic dual in-line (jd) ? .300" body [cerdip] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. significant characteristic. 3. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units inches dimension limits min nom max number of pins n 14 pitch e .100 bsc top to seating plane a ? ? .200 standoff a1 .015 ? ? ceramic package height a2 .140 ? .175 shoulder to shoulder width e .290 ? .325 ceramic package width e1 .230 .288 .300 overall length d .740 .760 .780 tip to seating plane l .125 ? .200 lead thickness c .008 ? .015 upper lead width b1 .045 ? .065 lower lead width b .015 ? .023 overall row spacing e2 .320 ? .410 n e1 d 1 2 note 1 a a1 b1 b e l a2 e c e2 microchip technology drawing c04-002 b
tc9400/9401/9402 ds21483d-page 20 ? 2007 microchip technology inc. 14-lead plastic dual in-line (pd) ? 300 mil body [pdip] notes: 1. pin 1 visual index feature may vary, but must be located with the hatched area. 2. significant characteristic. 3. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010" per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units inches dimension limits min nom max number of pins n 14 pitch e .100 bsc top to seating plane a ? ? .210 molded package thickness a2 .115 .130 .195 base to seating plane a1 .015 ? ? shoulder to shoulder width e .290 .310 .325 molded package width e1 .240 .250 .280 overall length d .735 .750 .775 tip to seating plane l .115 .130 .150 lead thickness c .008 .010 .015 upper lead width b1 .045 .060 .070 lower lead width b .014 .018 .022 overall row spacing eb ? ? .430 n e1 d note 1 12 3 e c e b a2 l a a1 b1 b e microchip technology drawing c04-005b
? 2007 microchip technology inc. ds21483d-page 21 tc9400/9401/9402 14-lead plastic small outline (od) ? narrow, 3.90 mm body [soic] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. significant characteristic. 3. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15 mm per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 14 pitch e 1.27 bsc overall height a ? ? 1.75 molded package thickness a2 1.25 ? ? standoff a1 0.10 ? 0.25 overall width e 6.00 bsc molded package width e1 3.90 bsc overall length d 8.65 bsc chamfer (optional) h 0.25 ? 0.50 foot length l 0.40 ? 1.27 footprint l1 1.04 ref foot angle 0 ? 8 lead thickness c 0.17 ? 0.25 lead width b 0.31 ? 0.51 mold draft angle top 5 ? 15 mold draft angle bottom 5 ? 15 note 1 n d e e1 1 2 3 b e a a1 a2 l l1 c h h microchip technology drawing c04-065b
tc9400/9401/9402 ds21483d-page 22 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds21483d-page 23 tc9400/9401/9402 appendix a: revision history revision d (september 2007) the following is the list of modifications: 1. corrected figure 6-1. 2. added history section. 3. updated package marking information and package outline drawings 4. added product identific ation system section. revision c (may 2006) revision b (may 2002) revision a (april 2002) ? original release of this document.
tc9400/9401/9402 ds21483d-page 24 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds21483d-page 25 tc9400/9401/9402 product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . part no. x /xx package temperature range device device tc9400: voltage-to-frequency converter tc9401: voltage-to-frequency converter tc9402: voltage-to-frequency converter temperature range e = -40 c to +85 c (extended) c=0 c to +70 c (commercial) package jd = ceramic dual-inline (.300? body), 14-lead pd = plastic dual-inline (300 mil body), 14-lead od = plastic small outline (3.90 mm body), 14-lead od713 = plastic small outline (3.90 mm body), 14-lead tape and reel. examples: a) tc9400cod: 0 c to +70 c, 14ld soic package. b) tc9400cod713:0 c to +70 c, 14ld soic package, tape and reel c) TC9400CPD: 0 c to +70 c, 14ld pdip package. d) tc9400ejd: -40 c to +85 c, 14ld pdip package. a) tc9401cpd: 0 c to +70 c, 14ld pdip package. b) tc9401ejd: -40 c to +85 c, 14ld cerdip package. a) tc9402cpd: 0 c to +70 c, 14ld pdip package. b) tc9402ejd: -40 c to +85 c, 14ld cerdip package.
tc9400/9401/9402 ds21483d-page 26 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds21483d-page 27 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, micro id , mplab, pic, picmicro, picstart, pro mate, rfpic and smartshunt are registered trademarks of microc hip technology incorporated in the u.s.a. and other countries. amplab, filterlab, linear active thermistor, migratable memory, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip te chnology incorporated in the u.s.a. analog-for-the-digital age, a pplication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, real ice, rflab, select mode, smart serial, smarttel, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2007, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
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