View CXP87532Q_6901006.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

cmos 8-bit single chip microcomputer description the cxp87532/87540 is a cmos 8-bit micro- computer which consists of arithmetic coprocessor, a/d converter, serial interface, timer/counter, time base timer, vector interruption, high precision timing pattern generation circuit, pwm generator and the measuring circuit which measures signals of capstan fg, drum fg/pg, reel fg and other servo systems, as well as basic configurations like 8-bit cpu, rom, ram and i/o port. they are integrated into a single chip. also this ic provides power on reset function, sleep/stop function which enables to lower power consumption. features a wide instruction set (213 instructions) which covers various types of data ?16-bit operation multiplycation and division/boolean bit operation instructions minimum instruction cycle during operation 326ns/12.288mhz incorporated rom capacity 32k bytes (cxp87532) 40k bytes (cxp87540) incorporated ram capacity 1344 bytes peripheral functions ?arithmetic coprocessor multiplying with code, sum of products with code, high speed execution of many bits shift rotation operation ?a/d converter 8-bit, 8-channel, successive approximation system (conversion time 13s/12.288mhz) incorporated 3-stage fifo for a/d conversion data ?serial interface incorporated buffer ram for data (1 to 128 bytes auto transfer) 2-channel ?timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer ?high precision timing pattern generator ppg (11 pins) 32-stage programmable ?pwm output 12-bit, 2-channel (repeated frequency 48khz) 8-bit, 3-channel (repeated frequency 48khz) ?servo input control capstan fg, drum fg/pg, reel fg input ?frc capture unit incorporated 28-bit and 8-stage fifo interruption 12 factors, 12 vectors, multi-interruption possible standby mode sleep/stop package 100-pin plastic qfp/lqfp piggyback/evaluation cxp87500 100-pin ceramic qfp/lqfp structure silicon gate cmos ic ?1 e93820b16-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. cxp87532/87540 100 pin qfp (plastic) 100 pin lqfp (plastic)
?2 cxp87532/87540 6 spc700 cpu core co-processor prom 32k/40k bytes clock generator/ system control ram 1344 bytes prescaler/ time base timer frc capture unit fifo interrupt controller 8bit pwm generator 3ch 12bit pwm generator 2ch atf sync unit switching pulse genrator 8bit timer/counter 0 8bit timer 1 a/d converter fifo servo input control drum capstan reel serial interface unit ram nm1 pe1/int2 pe3/int1 pe0/int0 pe2/pwm0 pe3/pwm1 pe4/pwm2 pe5/pwm3 pe6/pwm4 pf0/an0 to pf7/an7 av dd av ref av ss pa4/atfs1 pa5/atfs3 pa7/atfs2 pk0/rfdt pk1/mclk pe7/swp pa6/area pg2/dref pg3/dpg pg4/dfg pg5/cfg pg6/rfg0 pg7/rfg1 pa3/prout pg0/exi0 pg1/exi1 si0 so0 ph2/si1 ph1/so1 pe1/ec pb0/ppo0 to pa2/ppo10 8 cs0 sck0 ph3/cs1 ph0/sck1 pa0 to pa7 port a pb0 to pb7 port b pc0 to pc7 port c pd0 to pd7 port d pe0 to pe1 pe2 to pe7 port e pf0 to pf7 port f pg0 to pg7 port g ph0 to ph3 ph4 to ph7 port h pi0 to pi7 port i pk0 to pk3 port k pj0 to pj7 port j programmable pattern generator ram v ss v dd mp xtal extal rst block diagram
3 cxp87532/87540 pin assignment 1 (top view) 100pin qfp a 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 73 74 81 82 83 84 75 76 77 78 88 87 86 85 79 89 90 10 0 99 98 97 96 95 94 91 92 93 1 80 pe6/pwm4 pe7/swp pk0/rfdt pk1/mclk pk2 pk3 pg0/exi0 pg1/exi1 pg2/dref pg3/dpg pg4/dfg pg5/cfg pg6/rfg0 pg7/rfg1 pf0/an0 pf1/an1 pf2/an2 pf3/an3 pf4/an4 pf5/an5 pf6/an6 pf7/an7 av dd av ref av ss sck0 so0 si0 cs0 ph0/sck1 pb5/ppo5 pb4/ppo4 pb3/ppo3 pb2/ppo2 pb1/ppo1 pb0/ppo0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pi7 pi6 pi5 pi4 pi3 pi2 pi1 pi0 pb6/ppo6 pb7/ppo7 pa0/ppo8 pa1/ppo9 pa2/ppo10 pa3/prout pa4/atfs1 pa5/atfs3 pa6/area pa7/atfs2 nc v dd v ss nmi pe0/int0 pe1/int2/ec pe2/pwm0 pe3/pwm1 pe4/pwm2 pe5/pwm3 pj7 pj6 pj5 pj4 pj3 pj2 pj1 pj0 mp rst v ss xtal extal ph7 ph6 ph5 ph4 ph3/int1/cs1 ph2/si1 ph1/so1 note) 1. nc (pin 90) is always connected to v dd . 2. v ss (pins 41 and 88) are both connected to gnd. 3. mp (pin 39) is always connected to v ss .
4 cxp87532/87540 pin assignment 2 (top view) 100pin lqfp aa aa 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 73 74 81 82 83 84 75 76 77 78 88 87 86 85 79 89 90 10 0 99 98 97 96 95 94 91 92 93 1 80 pe6/pwm4 pe7/swp pk0/rfdt pk1/mclk pk2 pk3 pg0/exi0 pg1/exi1 pg2/dref pg3/dpg pg4/dfg pg5/cfg pg6/rfg0 pg7/rfg1 pf0/an0 pf1/an1 pf2/an2 pf3/an3 pf4/an4 pf5/an5 pf6/an6 pf7/an7 av dd av ref av ss pb3/pbo3 pb2/ppo2 pb1/ppo1 pb0/ppo0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pi7 pi6 pi5 pb6/ppo6 pb7/ppo7 pa0/ppo8 pa1/ppo9 pa2/ppo10 pa3/prout pa4/atfs1 pa5/atfs3 pa6/area pa7/atfs2 nc v dd v ss nmi pe0/int0 pe1/ec/int2 pe2/pwm0 pe3/pwm1 pe4/pwm2 pe5/pwm3 pj2 pj1 pj0 mp rst v ss xtal extal ph7 ph6 ph5 ph4 ph3/int1/cs1 ph2/si1 ph1/so1 pj7 pj6 pj5 pj4 pj3 26 27 28 29 30 pi4 pi3 pi2 pi1 pi0 ph0/sck1 cs0 sck0 so0 si0 pb4/ppo4 pb5/ppo5 note) 1. nc (pin 88) is always connected to v dd . 2. v ss (pins 39 and 86) are both connected to gnd. 3. mp (pin 37) is always connected to v ss .
5 cxp87532/87540 (port c) 8-bit input/output port, enables to specify input/output by 4-bit unit. (8 pins) output/ real time output output/ monitor output output/ real time output i/o i/o input/input input/input/ input output/output output/output input/input input/input input/input input/input input/input input/input input/input input/input input/input (port b) 8-bit output port. data is gated with ppo by or-gate and they are output. (8 pins) (port d) 8-bit input/output port. lower 4 bits can be specified as input/output by bit unit and upper 4 bits can be specified as input/output by 4-bit unit. (8 pins) (port e) 8-bit port. lower 2 bits are input pins and upper 6 bits are output pins. (8 pins) external input pin 0. external input pin 1. drum reference signal input pin. drum pg input pin. drum fg input pin. capstan fg input pin. reel fg input pin. input pin to request external interruption. active when falling edge. pwm output pins (5 pins) swp output pin. programmable pattern generator (ppg) output (3 pins) and capstan servo control signal (1 pin). symbol i/o description pa0/ppo8 pa1/ppo9 pa2/ppo10 pa3/prout pa4/atfs1 pa5/atfs3 pa6/area pa7/atfs2 pb0/ppo0 to pb7/ppo7 pc0 to pc7 pd0 to pd7 pe0/int0 pe1/ec/int2 pe2/pwm0 to pe6/pwm4 pe7/swp pf0/an0 to pf7/an7 pg0/exi0 pg1/exi1 pg2/dref pg3/dpg pg4/dfg pg5/cfg pg6/rfg0 pg7/rfg1 (port a) 8-bit output port. data is gated with ppo (3 pins), monitor signal (4 pins) in relation to atf, control signal (1 pin) for capstan servo by or-gate and they are output. (8 pins) monitor output in relation to atf. (4 pins) programmable pattern generator (ppg) output. (8 pins) external event input pin for timer/counter. (port f) 8-bit input port. (8 pins) upper 4 bits serve as standby release input pin. (port g) 8-bit input port. (8 pins) analog input pins to a/d converter. (8 pins) pin description input pin to request external interruption. active when falling edge.
6 cxp87532/87540 symbol i/o description ph0/sck1 ph1/so1 ph2/si1 ph3/int1/ cs1 ph7 to ph4 pi0 to pi7 pj0 to pj7 pk0/rfdt pk1/mclk pk2, pk3 sck0 so0 si0 cs0 nmi extal xtal rst mp av dd av ref av ss v dd v ss input/i/o input/output input/input input/input/input output i/o i/o i/o/input i/o/input i/o i/o output input input input input output i/o input input serial clock input/output pin. serial data output pin. serial data input pin. chip select input pin to serial interface. serial clock input/output pin. serial data output pin. serial data input pin. chip select input pin to serial interface. non-maskable interrupt request pin. active during falling edge. connecting pin of crystal oscillator for system clock. when supplying the external clock, input the external clock to extal pin and set xtal pin to open. system reset pin of active l level. rst pin is input/output pin, which output l level by incorporated power on reset function when power on. (mask option) (port h) 4-bit input port. (4 pins) input pin to request external interruption. active when falling edge. (port h) 4-bit output port. n-ch open drain output of middle tension proof (12v) and large current (12ma). (4 pins) (port i) 8-bit input/output port, enables to specify input/output by 4-bit unit. (8 pins) (port j) 8-bit input/output port, enables to specify input/output by 4-bit unit. (8 pins) (port k) 4-bit input/output port, enables to specify input/ output by bit unit. (4 pins) playback data input pin. channel clock input pin. test mode pin. this pin is always connected to gnd. positive power supply pin of a/d converter. set the same voltage as v dd . reference voltage input pin of a/d converter. gnd pin of a/d converter. positive power supply pin. gnd pin. connect both v ss pins to gnd.
7 cxp87532/87540 i/o circuit formats for pins pin circuit format when reset port a port b port c port d port e hi-z hi-z hi-z hi-z pa0/ppo8 to pa2/ppo10 pa3/prout pa4/atfs1 pa5/atfs3 pa6/area pa7/atfs2 pb0/ppo0 to pb7/ppo7 16 pins pc0 to pc7 8 pins pd0 to pd7 8 pins pe0/int0 pe1/ec/ int2 2 pins aaaa aaaa aa aa ppo, prout, atfs1 to atfs3, area, data data bus output becomes active from high impedance by data writing to port register. port a or port b rd data bus rd (port d) aaaa aaaa aa port d direction aaaa aaaa port d data ip aa aa large current 12ma lower 4 bits are by bit unit and upper 4 bits are by 4- bit unit data bus rd (port c) aaaa aaaa aa port c direction aaaa aaaa port c data ip aa aa input protection circuit (every 4 bits) buffer aa a ip rd (port e) data bus schmitt input
8 cxp87532/87540 port e port e port f port g hi-z h level hi-z hi-z pe2/pwm0 pe3/pwm1 pe4/pwm2 pe5/pwm3 4 pins pe6/pwm4 pe7/swp 2 pins pf0/an0 to pf7/an7 8 pins pg0/exi0 pg1/exi1 pg2/dref pg3/dpg pg4/dfg pg5/cfg pg6/rfg0 pg7/rfg1 8 pins data bus rd (port e) aa aa aa aa aa aa pwm output mpx aaaa aaaa port/pwm output select aaaa port e data hi-z control data bus rd (port e) aaaa aaaa port/pwm, swp output select aa aa aa aa aa aa pwm, swp output mpx aaaa port e data aa aa a a ip input multiplexer a/d converter aaaa aaaa analog/digial input select rd (port f) data bus aa a ip rd (port g) data bus schmitt input servo input for pg0/exi0 to pg7/rfg1, ttl schmitt input can be selected with the mask option. pin circuit format when reset
9 cxp87532/87540 pin circuit format when reset port h port h port h port h hi-z hi-z hi-z open ph0/sck1 1 pin ph1/so1 1 pin ph2/si1 ph3/cs1/ int1 2 pins ph4 to ph7 4 pins sck1 output enable aa aa internal serial clock from si0 aa ip schmitt input data bus rd (port h) external serial clock to si0 so1 output enable aa aa so1 from si0 aa ip data bus rd (port h) aa a ip data bus schmitt input rd (port h) data bus rd (port h) aa aa aaaa aaaa port h data large current 12ma middle tension proof 12v
10 cxp87532/87540 port i port j port k hi-z hi-z hi-z when buffer amplifier input is selected, pulled up internally during standby. pi0 to pi7 8 pins pj0 to pj7 8 pins pk0/rfdt 1 pin data bus rd (port i) aaaa aaaa aa port i direction aaaa aaaa port i data ip aa aa input protection circuit (every 4 bits) buffer data bus rd (port j) aaaa aaaa aa port j direction aaaa aaaa port j data ip aa aa (every 4 bits) data bus rd (port k) aaaa aaaa aa port k direction aaaa aaaa port k data ip aa aa input protection circuit (every bit) servo input buffer amplifier input can be selected with the mask option. pin circuit format when reset
11 cxp87532/87540 pin circuit format when reset port k port k hi-z hi-z hi-z hi-z pk1/mclk 1 pin pk2 to pk3 2 pins cs0 si0 2 pins so0 1 pin hi-z sck0 1 pin data bus rd (port k) aaa aaa a a port k direction aaa aaa port k data ip aa aa input protection circuit (every bit) servo input ttl schmitt input can be selected with the mask option. data bus rd (port k) aaaa aaaa aa port k direction aaaa aaaa port k data ip aa aa (every bit) aa aa aa aa ip schmitt input to si0 so0 output enable aa aa so0 from si0 sck0 output enable a a internal serial clock from si0 a a ip schmitt input external serial clock to si0
12 cxp87532/87540 extal xtal oscillation 1 pin 2 pins rst 1 pin l level nmi hi-z aa aa aa aa ip aa aa extal xtal shows the circuit composition during oscillation. feedback resistor is removed during stop. aa aa schmitt input pull-up resistor from power on reset circuit (mask option) mask option op aa aa aa aa ip schmitt input interruption circuit pin circuit format when reset
13 cxp87532/87540 absolute maximum ratings (v ss = 0v reference) ? 1 av dd and v dd should be set to the same voltage. ? 2 v in and v out should not exceed v dd + 0.3v ? 3 the large current operation transistors are the n-ch transistors of the pd and ph4 to ph7. note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should better take place under the recommended operating conditions. exceeding those conditions may adversely affect the reliability of the lsi. power supply voltage input voltage output voltage middle tension proof output voltage high level output current high level total output current low level output current low level total output current operating temperature storage temperature allowable power dissipation v dd av dd av ss v in v out v outp i oh i oh i ol i olc i ol topr tstg p d mw 0.3 to +7.0 av ss to +7.0 ? 1 0.3 to +0.3 0.3 to +7.0 ? 2 0.3 to +7.0 ? 2 0.3 to +15.0 5 50 15 20 130 20 to +75 55 to +150 600 380 v v v v v ma ma ma ma ma ma c c ph pin total of entire output pins other than large current output pins : per pin large current port pin ? 3 : per pin total of entire output pins qfp package lqfp package item symbol ratings unit remarks
14 cxp87532/87540 recommended operating conditions (v ss = 0v reference) ? 1 av dd and v dd should be set to the same voltage. ? 2 normal input port (each pin of pc, pd, pf and ph1). ? 3 each pin of nmi, cs0, si0, sck0, rst, pe0/int0, pe1/ec/int2, ph0/sck1, ph2/si1, ph3/int1/cs1, pg and pk1/mclk (when cmos schmitt input is selected with mask option for pg, pk1/mclk). ? 4 each pin of pg and pk1/mclk (when ttl schmitt input is selected with mask option). ? 5 specified only during external clock input. analog voltage high level input voltage low level input voltage operating temperature 5.5 5.5 5.5 v dd v dd v dd v dd + 0.3 0.3v dd 0.2v dd 0.8 0.4 +75 v v v v v v v v v c v item symbol min. max. unit remarks 4.5 2.5 4.5 0.7v dd 0.8v dd 2.2 v dd 0.4 0 0 0 0.3 20 av dd v ih v ihs v ihts v ihex v il v ils v ilts v ilex topr guaranteed range during operation guaranteed data hold operation range during stop ? 1 ? 2 cmos schmitt input ? 3 ttl schmitt input ? 4 extal pin ? 5 ? 2 cmos schmitt input ? 3 ttl schmitt input ? 4 extal pin ? 5 v dd power supply voltage
15 cxp87532/87540 dc characteristics (ta = 20 to +75 c, v ss = 0v reference) ? 1 rst pin specifies only when the power on reset circuit is selected with mask option. ? 2 rst pin specifies the input current when the pull-up resistance is selected, and specifies leakage current when non-resistance is selected. ? 3 pk0 pin specifies only when the normal input circuit is selected with mask option. v dd = 4.5v, i oh = 0.5ma v dd = 4.5v, i oh = 1.2ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 12.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v il = 0.4v v dd = 5.5v v i = 0, 5.5v v dd = 5.5v v oh = 12v operating mode (1/2 dividing clock) 12.288mhz crystal oscillation (c 1 = c 2 = 12pf) entire output pins open sleep mode stop mode clock 1mhz 0v other than the measured pins high level output voltage 4.0 3.5 0.5 0.5 1.5 0.4 0.6 1.5 40 40 400 10 50 v v v v v a a a a a pd, ph4 to ph7 pa to pd, pe2 to pe7, ph0, ph1, so0, sck0 ph4 to ph7 (v ol only) rst ? 1 (v ol only) pi to pk extal rst ? 2 pa to pg ph0 to ph3, cs0, si0, so0, sck0, nmi, rst ? 2 pi to pk ? 3 ph4 to ph7 item symbol pin condition min. typ. max. unit other than v dd , v ss , av dd , and av ss pins v dd ma ma a pf 45 17 10 20 20 5 10 i loh i dd i ddsl i ddst c in v oh v ol i ihe i ile i ilr i iz low level output voltage input current i/o leakage current open drain output leakage current (n-ch tr off in state) current power supply input capacity
16 cxp87532/87540 ac characteristics (1) clock timing (ta = 20 to +75 c, v dd = 4.5 to 5.5v, v ss = 0v reference) ? 1 t sys indicates three values according to the contents of the clock control register (address : 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = 00 ), 4000/fc (upper 2 bits = 01 ), 16000/fc (upper 2 bits = 11 ) system clock frequency system clock input pulse width system clock input rising and falling times event count input clock pulse width event count input clock rising and falling times f c t xl , t xh t cr , t cf t eh , t el t er , t ef xtal extal extal extal ec ec 12.288 200 20 mhz ns ns ns ms item symbol pin condition min. max. unit fig. 1, fig. 2 fig. 1, fig. 2 external clock drive fig. 1, fig. 2 external clock drive fig. 3 fig. 3 1 36 t sys + 50 ? 1 aaaaa a aaa a aaaaa aaaaa a aaa a aaaaa crystal oscillation ceramic oscillation extal xtal external clock extal xtal c 1 c 2 fig. 2. clock applying condition fig. 1. clock timing extal t xh t xl t cf t cr 0.4v v dd 0.4v 1/fc fig. 3. event count clock timing ec t eh t el t ef t er 0.2v dd 0.8v dd 74hco4
17 cxp87532/87540 (2) serial transfer (ta = 20 to +75 c, v dd = 4.5 to 5.5v, v ss = 0v reference) note 1) t sys indicates three values according to the contents of the clock control register (address : 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = 00 ), 4000/fc (upper 2 bits = 01 ), 16000/fc (upper 2 bits = 11 ) note 2) the marks cs, sck, si and so respectivery mean pins of cs cs0, cs1, sck sck0, sck1, si si0, si1 and so so0, so1. note 3) the load of sck output mode and so output delay time is 50pf + 1ttl. cs sck delay time cs sck floating delay time cs so delay time cs so floating delay time cs high level width t sys + 200 2 t sys + 200 8000/fc t sys + 100 4000/fc 50 t sys + 100 200 2 t sys + 100 100 t sys + 200 t sys + 200 t sys + 200 t sys + 200 2 t sys + 200 100 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns item symbol pin condition min. max. unit chip select transfer mode (sck = output mode) chip select transfer mode (sck = output mode) chip select transfer mode chip select transfer mode chip select transfer mode input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode sck cycle time sck high and low level widths si input setup time (against sck ) si input hold time (against sck ) sck so delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso sck0, sck1 sck0, sck1 so0, so1 so0, so1 cs0, cs1 sck0, sck1 sck0, sck1 si0, si1 si0, si1 so0, so1
18 cxp87532/87540 fig. 4. serial transfer timing cs0 cs1 sck0 sck1 0.2v dd 0.8v dd t whcs t dcsk t dcskf 0.8v dd 0.2v dd 0.8v dd t kcy t kl t kh 0.8v dd 0.2v dd si0 si1 t sik input data t dcso t kso t dcsof output data 0.8v dd 0.2v dd so0 so1 t ksi
19 cxp87532/87540 (3) a/d converter characteristics (ta = 20 to +75 c, v dd = av dd = 4.5 to 5.5v, av ref = 4.0 to av dd , v ss = av ss = 0v reference) conversion time sampling time reference input voltage analog input voltage v zt ? 1 v ft ? 2 30 4970 t conv t samp v ref v ian i ref av ref an0 to an7 ta = 25 c v dd = av dd = 5.0v v ss = av ss = 0v operating mode sleep mode stop mode linearity error zero transition voltage resolution av ref current av ref i refs s s v v av dd av ref 1.0 ma 10 a 0.6 160/f c 12/f c av dd 0.5 0 item symbol pin condition min. typ. max. unit full scale transition voltage 10 4930 8 1 70 5010 bits lsb mv mv fig. 5. definitions of a/d converter terms analog input linearity error v ft v zt 00 h 01 h fe h ff h digital conversion value ? 1 v zt : indicates the value that digital conversion value changes from 00 h to 01 h and vice versa. ? 2 v ft : indicates the value that digital conversion value changes from fe h to ff h and vice versa.
20 cxp87532/87540 (4) interruption, reset input (ta = 20 to +75 c, v dd = 4.5 to 5.5v, v ss = 0v reference) (5) power on reset power on reset ? (ta = 20 to +75 c, v dd = 4.5 to 5.5v, v ss = 0v reference) external interruption high and low level widths reset input low level width int0 int1 int2 nmi rst 1 8/fc s s item symbol pin condition min. max. unit t ih t il t rsl power supply rising time power supply cut-off time t r t off v dd power on reset repetitive power on reset 0.05 1 50 ms ms item symbol pin condition min. max. unit fig. 6. interruption input timing fig. 7. rst input timing 0.2v dd 0.8v dd t ih t il t rsl 0.2v dd rst int0 int1 int2 nmi (falling edge) fig. 8. power on reset 0.2v 0.2v 4.5v v dd t r t off the power supply should rise smoothly. ? specifies only when power on reset function is selected.
21 cxp87532/87540 (6) others (ta = 20 to +75 c, v dd = 4.5 to 5.5v, v ss = 0v reference) ? 1 t mck indicates three values according to the contents of the atf control register (address : 01ee h ) bits 5 and 4 (mclk input control). t mck [ns] = t mch or t mcl (bits 5 and 4 = 00 ), 2 t mch or 2 t mcl (bits 5 and 4 = 01 ), 4 t mch or 4 t mcl (bits 5 and 4 = 10 ). rfdt input high and low level widths mclk input high and low level widths dref input high and low level widths dpg input high and low level widths dfg input high and low level widths cfg input high and low level widths rfg input high and low level widths exi input high and low level widths t rdh t rdl t mch t mcl t drh t drl t dph t dpl t dfh t dfl t cfh t cfl t rfh t rfl t eih t eil rfdt mclk dref dpg dfg cfg rfg0 rfg1 exi0 exi1 2.5 t mck ? 1 326/fc t sys + 200 t sys + 200 t sys + 200 t sys + 200 t sys + 200 t sys + 200 ns ns ns ns ns ns ns ns item symbol pin condition min. max. unit t sys = 2000/fc
22 cxp87532/87540 fig. 9. other timing rfdt t rdh t rdl mclk t mch t mcl dref t drh t drl dpg t dph t dpl dfg t dfh t dfl cfg t cfh t cfl rfg0 rfg1 t rfh t rfl exi0 exi1 t eih t eil
23 cxp87532/87540 ? 1 when buffer amplifier input circuit format of rfdt pin is selected with option. note) v app waveform indicates the range like fig. 11. when composed by circuits other than fig. 10. (when dc bias does not become v dd /2), it should not exceed v dd + 0.3 (v) and 0.3 (v) (v ss = 0v). (7) buffer amplifier function (ta = 20 to +75 c, v dd = 4.5 to 5.5v, v ss = 0v reference) buffer amplifier input voltage ? 1 (peak to peak value) v app rfdt when inputting 400khz sine wave on fig. 10 circuit. 2.0 v dd + 0.3 v item symbol pin condition min. max. unit fig. 10. c v app (refer to fig. 11.) c: 4700pf (5%) rfdt v dd v ss fig. 11. v app v dd /2
24 cxp87532/87540 supplement mask option table ? 1 on pg0/exi0 pin to pg7/rfg1 pin and pk1/mclk pin, the input circuit format of cmos schmitt or ttl schmitt can be selected to every pin. on pk0/rfdt pin, buffer amplifier or normal input circuit format can be selected. aaaaa a aaa a aaaaa extal xtal c 1 c 2 fig. 12. spc700 series recommended oscillation circuit model frequency f (mhz) c 1 , c 2 (pf) river eletec corporation hc-49/u-03 6.00 8.00 12.000 12 12 10 manufacturer reset pin pull-up resistor power on reset circuit input circuit format ? 1 non-existent non-existent cmos schmitt buffer amplifier item contents existent existent ttl schmitt normal input
25 cxp87532/87540 package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy package structure 23.9 0.4 qfp-100p-l01 100pin qfp (plastic) 20.0 0.1 + 0.4 0.15 0.05 + 0.1 15.8 0.4 17.9 0.4 14.0 0.1 + 0.4 2.75 0.15 + 0.35 a 0.65 m 0.13 qfp100-p-1420 1.7g 1 100 81 80 51 50 31 30 0.3 0.1 + 0.15 detail a 0 ? to 10 ? 0.8 0.2 (16.3) 0.15 0.1 0.05 + 0.2
26 cxp87532/87540 package outline unit: mm 100pin lqfp (plastic) 25 26 51 50 75 76 1 100 sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42 / copper alloy package structure detail a lqfp-100p-l01 p-lqfp100-14x14-0.5 16.0 0.2 14.0 0.1 0.5 b (0.22) a 1.5 ?0.1 + 0.2 0.5 0.2 (15.0) 0? to 10? 0.1 0.1 0.5 0.2 0.1 note: dimension " ? " does not include mold protrusion. 0.7g 0.13 m b = 0.18 ?0.03 ( 0.18 ) (0.127) + 0.08 0.127 ?0.02 + 0.05 detail b ? b 100pin lqfp (plastic) 25 26 51 50 75 76 1 100 sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42 / copper alloy package structure detail a lqfp-100p-l01 p-lqfp100-14x14-0.5 16.0 0.2 14.0 0.1 0.5 b (0.22) a 1.5 0.1 + 0.2 0.5 0.2 (15.0) 0 ? to 10 ? 0.1 0.1 0.5 0.2 0.1 note: dimension " ? " does not include mold protrusion. 0.7g 0.13 m b = 0.18 0.03 ( 0.18 ) (0.127) + 0.08 0.127 0.02 + 0.05 detail b ? b lead specifications item lead material copper alloy lead treatment sn-bi 2.5% lead treatment thickness 5-18 m spec. sony corporation

▲Up To Search▲

Price & Availability of CXP87532Q

	To Download CXP87532Q Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .