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2003.9.18 32 sh7709s group hardware manual renesas 32-bit risc microcomputer superh ? risc engine family/sh7700 series rev.5.00

renesas 32-bit risc microcomputer superh ? risc engine family/sh7700 series sh7709s group hardware manual rej09b0081-0500o
rev. 5.00, 09/03, page iv of xliv cautions keep safety first in your circuit designs! 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas technology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein.
rev. 5.00, 09/03, page v of xliv general precautions on handling of product 1. treatment of nc pins note: do not connect anything to the nc pins. the nc (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. if something is connected to the nc pins, the operation of the lsi is not guaranteed. 2. treatment of unused input pins note: fix all unused input pins to high or low level. generally, the input pins of cmos products are high-impedance input pins. if unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a pass- through current flows internally, and a malfunction may occur. 3. processing before initialization note: when power is first supplied, the product?s state is undefined. the states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. during the period where the states are undefined, the register settings and the output state of each pin are also undefined. design your system so that it does not malfunction because of processing while it is in this undefined state. for those products which have a reset function, reset the lsi immediately after the power supply has been turned on. 4. prohibition of access to undefined or reserved addresses note: access to undefined or reserved addresses is prohibited. the undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. do not access these registers; the system?s operation is not guaranteed if they are accessed.
rev. 5.00, 09/03, page vi of xliv configuration of this manual this manual comprises the following items: 1. general precautions on handling of product 2. configuration of this manual 3. preface 4. contents 5. overview 6. description of functional modules ? cpu and system-control modules ? on-chip peripheral modules the configuration of the functional description of each module differs according to the module. however, the generic style includes the following items: i) feature ii) input/output pin iii) register description iv) operation v) usage note when designing an application system that includes this lsi, take notes into account. each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. list of registers 8. electrical characteristics 9. appendix 10. main revisions and additions in this edition (only for revised versions) the list of revisions is a summary of points that have been revised or added to earlier versions. this does not include all of the revised contents. for details, see the actual locations in this manual. 11. index
rev. 5.00, 09/03, page vii of xliv preface this lsi is a microprocessor with the 32-bit sh-3 cpu as its core and peripheral functions necessary for configuring a user system. this lsi is built in with a variety of peripheral functions such as cache memory, memory management unit (mmu), interrupt controller, timer, three serial communication interfaces, real- time clock (rtc), use break controller (ubc), bus state controller (bsc) and i/o ports. this lsi can be used as a microcomputer for devices that require both high speed and low power consumption. target readers: this manual is designed for use by people who design application systems using the sh7709s. to use this manual, basic knowledge of electric circuits, logic circuits and microcomputers is required. purpose: this manual provides the information of the hardware functions and electrical characteristics of the sh7709s. the sh3, sh-3e, sh3-dsp programming manual contains detailed information of executable instructions. please read the programming manual together with this manual. how to use the book: ? to understand general functions ? read the manual from the beginning. the manual explains the cpu, system control functions, peripheral functions and electrical characteristics in that order. ? to understanding cpu functions ? refer to the separate sh3, sh-3e, sh3-dsp programming manual. explanatory note: bit sequence: upper bit at left, and lower bit at right list of related documents: the latest documents are available on our web site. please make sure that you have the latest version. (http://www.renesas.com/eng/) ? user manuals for sh7709s name of document document no. sh7709s group hardware manual this manual sh3, sh-3e, sh3-dsp programming manual ade-602-156
rev. 5.00, 09/03, page viii of xliv ? user manuals for development tools name of document document no. c/c++ compiler, assembler, optimizing linkage editor user?s manual ade-702-246 simulator/debugger user?s manual ade-702-186 embedded workshop user?s manual ade-702-201
rev. 5.0, 09/03, page ix of xliv list of items revised or added for this version section page description 1.2 block diagram figure 1.1 block diagram 6 aseram deleted from figure bridge external bus interface udi intc cpg/wdt i bus 2 aseram deleted from legend 2.5.1 processor states 53 description amended in the power-on reset state, the internal states of the cpu and the on-chip supporting module registers are initialized. in the manual reset state, the internal states of the cpu and registers of on-chip supporting modules other than the bus state controller (bsc) are initialized. refer to the register configurations in the relevant sections for further details. 5.4 memory-mapped cache 5.4.1 address array 113 description amended this operation is used to invalidate the address specification for a cache. write back will take place when the u bit of the entry that received a hit is 1. note that, when a 0 is written to the v bit, a 0 should always be written to the u bit of the same entry, too.
rev. 5.0, 09/03, page x of xliv section page description 5.4.3 examples of usage 115, 116 (1) invalidating a specific entry description amended a specific cache entry can be invalidated by accessing the allocated memory cache and writing a 0 to the entry?s u and v bits . the a bit is cleared to 0, and an address is specified for the entry address and the way. if the u bit of the way of the entry in question was set to 1, the entry is written back and the v and u bits specified by the write data are written to. in the following example, the write data is specified in r0 and the address is specified in r1. ;r0=h' 0000 0000 lru = h'000 ,u=0,v=0 ; r1 = h'f000 1080, way = 1, entry = h'08, a = 0 ; mov.l r0, @r1 to invalidate all entries and ways, write 0 to the following addresses. addresses f000 0000 f000 0010 f000 0020 : f000 3ff0 this involves a total of 1,024 writes. the above operation should be performed using a non-cacheable area. (2) invalidating a specific address newly added (3) reading data from a specific entry description amended ; r0 = h'f100 004c; data array access, entry = h'04, ; way = 0, longword address = 3 ; mov.l r0, @r1 ; longword 3 is read. 6.2.6 interrupt exception handling and priority table 6.4 interrupt exception handling sources and priority (irq mode) 127 ipr (bit numbers) for sci amended (before)iprb(3-0) (after)iprb (7-4) 6.3.6 interrupt request register 0 (irr0) 138 description amended when clearing an irq5r?irq0r bit to 0, read the bit while bit set to 1, and then write 0. in this case, 0 should be written only to the bits to be cleared and 1 to the other bits. the contents of the bits to which 1 is written do not change. 8.2.1 standby control register (stbcr) 184 description added bit 1?module standby 1 (mstp1) before switching the rtc to module standby, access at least one among the registers rtc, sci, and tmu.
rev. 5.0, 09/03, page xi of xliv section page description 8.3.3 precautions when using the sleep mode 187 newley added 8.5.1 transition to module standby function 191 note * 3 added to bit table note: 3. before putting the rtc into module standby status, first access one or more of the rtc, sci, and tmu registers. the rtc may then be put into module standby status. 9.3 clock operating modes table 9.4 available combinations of clock mode and frqcr values 210 2. under cautions amended the peripheral clock frequency should not be set higher than the frequency of the ckio pin, higher than 33.34 mhz. 9.5.1 changing the multiplication rate 213 description added 5.supply of the clock that has been set begins at wdt count overflow, and the processor begins operating again. the wdt stops after it overflows. when the following three conditions are all met, frqcr should not be changed while a dmac transfer is in progress. ? bits ifc2 to ifc0 are changed. ? stc2 to stc0 are not changed. ? the clock ratio of i (on-chip clock) to b (bus clock) after the change is other than 1:1. 9.8.2 changing the frequency 218, 219 description added 5.the counter stops at a value of h'00 or h'01. the stop value depends on the clock ratio. when the following three conditions are all met, frqcr should not be changed while a dmac transfer is in progress. ? bits ifc2 to ifc0 are changed. ? stc2 to stc0 are not changed. ? the clock ratio of i (on-chip clock) to b (bus clock) after the change is other than 1:1. 10.1.1 features 223 refresh function description deleted 10.2.5 individual memory control register (mcr) 246 description added bit 7?synchronous dram bank active (rasd): specifies whether synchronous dram is used in bank active mode or auto- precharge mode. set auto-precharge mode when areas 2 and 3 are both designated as synchronous dram space. the bank active mode should not be used unless the bus width for all areas is 32 bits.
rev. 5.0, 09/03, page xii of xliv section page description 10.2.13 mcs0 control register (mcscr0) 258 description added bit 6?cs2/cs0 select (cs2/0) only 0 should be used for the cs2/0 bit in mcscr0. either 0 or 1 may be used for mcscr1 to mcscr7. 10.3.4 synchronous dram interface 290 bank active description added ? .in bank active mode, too, all banks become inactive after a refresh cycle or after the bus is released as the result of bus arbitration. the bank active mode should not be used unless the bus width for all areas is 32 bits. 10.3.6 pcmcia interface figure 10.32 basic timing for pcmcia memory card interface 310 figure amended d15 to d0 ( write) 10.3.7 waits between access cycles figure 10.40 waits between access cycles 320 figure amended t 1 ckio a25 to a0 t 2 twait t 1 t 2 twait t 1 t 2 10.3.10 mcs[0] to mcs[7] pin control 323 description amended this enables 32-, 64-, 128-, or 256-mbit memory to be connected to area 0 or area 2. however, only cs2/0 = 0 (area 0) should be used for mcscr0. table 10.15 shows mcscr0?mcscr7 settings and mcs[0] ? mcs[7] assertion conditions. 11.6 usage notes 387 description added 13. dmac transfers should not be performed in the sleep mode under conditions other than when the clock ratio of i (on- chip clock) to b (bus clock) is 1:1. 14. when the following three conditions are all met, the frequency control register (frqcr) should not be changed while a dmac transfer is in progress. ? bits ifc2 to ifc0 are changed. ? stc2 to stc0 in frqcr are not changed. ? the clock ratio of i (on-chip clock) to b (bus clock) after the change is other than 1:1. 13.4.3 precautions when using rtc module standby 426 newly added
rev. 5.0, 09/03, page xiii of xliv section page description 16.4 scif interrupts 550 description amended when the tdfe flag in the serial status register (scssr) is set to 1, a txi interrupt request is generated. the dmac can be activated and data transfer performed when this interrupt is generated. when data exceeding the transmit trigger number is written to the transmit data register (scftdr) by the dmac, 1 is read from the tdfe flag, after which 0 is written to it to clear it. when the rdf flag in scssr is set to 1, an rxi interrupt request is generated. the dmac can be activated and data transfer performed when the rdf flag in scssr is set to 1. when receive data less than the receive trigger number is read from the receive data register (scfrdr) by the dmac, 1 is read from the rdf flag, after which 0 is written to it to clear it. description amended 1. scftdr writing and tdfe flag: however, if the number of data bytes written to scftdr is equal to or less than the transmit trigger number, the tdfe flag will be set to 1 again even after having been cleared to 0. tdfe clearing should therefore be carried out after data exceeding the specified transmit trigger number has been written to scftdr. 16.5 usage notes 551 2. scfrdr reading and rdf flag: however, if the number of data bytes in scfrdr exceeds the trigger number, the rdf flag will be set to 1 again even after having been cleared to 0. rdf should therefore be cleared to 0 after being read as 1 after all the receive data has been read. 19.13.2 sc port data register (scpdr) 610 title amended
rev. 5.0, 09/03, page xiv of xliv section page description 20.3 bus master interface figure 20.2 a/d data register access operation (reading h'aa40) 622 figure amended bus interface temp [h40] addrn l [h40] addrn h [haa] n = a to d cpu receives data haa upper byte read module internal data bus bus interface temp [h40] addrn l [h40] addrn h [haa] n = a to d cpu receives data h40 lower byte read module internal data bus 23.1 absolute maximum ratings table 23.1 absolute maximum ratings 657 caution added 2.until voltage is applied to all power supplies, a low level is input at the resetp pin, and ckio has operated for a maximum of 4 clock cycles, internal circuits remain unsettled, and so pin states are also undefined. the system design must ensure that these undefined states do not cause erroneous system operation. note that the resetp pin cannot receive a low level signal while a low level signal is being input to the ca pin. test conditions for in sleep mode amended item symbol min typ max unit test conditions icc ? 15 30 sleep mode * 1 iccq ? 10 20 * 1 : when there is no other external bus cycle other than the refresh cycle. vcc = 1.9 v vccq = 3.3 v b = 33mhz 23.2 dc characteristics table 23.2 dc characteristics 659, 662 note * added * if the irl and irls interrupts are used, the minimum is 1.9 v.
rev. 5.0, 09/03, page xv of xliv section page description 23.3.6 synchronous dram timing figure 23.31 synchronous dram burst read bus cycle (ras down, same row address, cas latency = 2) 690 tnop cycle deleted from figure a25 to a16 (high) t ad t ad t ad t casd2 t csd3 t rwd t dqmd t bsd t rdh2 t rds2 t rdh2 t rds2 t bsd t rasd2 t casd2 t dqmd t rwd t csd3 t ad t ad t ad tc1 tc2 tc3/td1 tc4/td2 td3 td4 ckio a12 or a10 a15 to a0 csn rd/ wr ras cas dqmxx d31 to d0 bs cke row address dackn t dakd1 t dakd1 column address read command
rev. 5.0, 09/03, page xvi of xliv section page description function information amended for v cc ?rtc, v cc ?pll1, v cc ? pll2, and v cc pin pin no. (fp-208c, fp-208e) pin no. (bp- 240a) i/o function v cc ? rtc 3 e2 power supply rtc oscillator power supply (2.0/1.9/1.8/1.7 v) v cc ? pll1 v cc ? pll2 145 150 f16, e17 power supply pll power supply (2.0/1.9/1.8/1.7 v) v cc 29, 81, 134, 154, 175 l3, l4, u11, t11, j17, j16, e18, c19, c12, d12 power supply internal power supply (2.0/1.9/1.8/1.7 v) a.2 pin specifications table a.2 pin specifications 723 a.3 treatment of unused pins 724 "when rtc is not used" and "when pll2 is not used" amended (before) (1.9/1.8v) (after) ( 2.0/1.9/1.8 /1.7v) a.4 pin states in access to each address space table a.3 pin states (ordinary memory/little endian) table a.4 pin states (ordinary memory/big endian) table a.5 pin states (burst rom/little endian) table a.6 pin states (burst rom/big endian) table a.9 pin states (pcmcia/little endian) table a.10 pin states (pcmcia/big endian) 726 to 738 note 2 amended note: 2. unused data pins should be switched to the port function, or pulled up.
rev. 5.00, 09/03, page xvii of xliv contents section 1 overview and pin functions .......................................................................... 1 1.1 sh7709s features ............................................................................................................ .1 1.2 block diagram ............................................................................................................... ... 6 1.3 pin description ............................................................................................................. ..... 7 1.3.1 pin assignment .................................................................................................... 7 1.3.2 pin function ......................................................................................................... 9 section 2 cpu ....................................................................................................................... 19 2.1 register configuration ...................................................................................................... 19 2.1.1 privileged mode and banks.................................................................................. 19 2.1.2 general registers ................................................................................................. 22 2.1.3 system registers .................................................................................................. 23 2.1.4 control registers.................................................................................................. 23 2.2 data formats ................................................................................................................ ..... 25 2.2.1 data format in registers...................................................................................... 25 2.2.2 data format in memory ....................................................................................... 25 2.3 instruction features ........................................................................................................ ... 26 2.3.1 execution environment........................................................................................ 26 2.3.2 addressing modes................................................................................................ 28 2.3.3 instruction formats............................................................................................... 32 2.4 instruction set............................................................................................................. ....... 35 2.4.1 instruction set classified by function.................................................................. 35 2.4.2 instruction code map........................................................................................... 50 2.5 processor states and processor modes.............................................................................. 53 2.5.1 processor states.................................................................................................... 53 2.5.2 processor modes .................................................................................................. 54 section 3 memory management unit (mmu) ............................................................ 55 3.1 overview .................................................................................................................... ....... 55 3.1.1 features ................................................................................................................ 55 3.1.2 role of mmu ....................................................................................................... 55 3.1.3 sh7709s mmu.................................................................................................... 58 3.1.4 register configuration ......................................................................................... 61 3.2 register description ........................................................................................................ .. 61 3.3 tlb functions............................................................................................................... .... 63 3.3.1 configuration of the tlb..................................................................................... 63 3.3.2 tlb indexing ....................................................................................................... 65 3.3.3 tlb address comparison.................................................................................... 66 3.3.4 page management information ............................................................................ 68
rev. 5.00, 09/03, page xviii of xliv 3.4 mmu functions ............................................................................................................... .69 3.4.1 mmu hardware management ............................................................................. 69 3.4.2 mmu software management............................................................................... 69 3.4.3 mmu instruction (ldtlb) ................................................................................. 70 3.4.4 avoiding synonym problems............................................................................... 72 3.5 mmu exceptions .............................................................................................................. 74 3.5.1 tlb miss exception ............................................................................................ 74 3.5.2 tlb protection violation exception.................................................................... 75 3.5.3 tlb invalid exception......................................................................................... 76 3.5.4 initial page write exception ................................................................................ 77 3.5.5 processing flow in event of mmu exception (same processing flow for address error) ................................................................................................ 79 3.6 configuration of memory-mapped tlb........................................................................... 80 3.6.1 address array ...................................................................................................... 80 3.6.2 data array............................................................................................................ 81 3.6.3 usage examples ................................................................................................... 83 3.7 usage note .................................................................................................................. ...... 83 section 4 exception handling .......................................................................................... 85 4.1 overview .................................................................................................................... ....... 85 4.1.1 features ................................................................................................................ 85 4.1.2 register configuration ......................................................................................... 85 4.2 exception handling function............................................................................................ 85 4.2.1 exception handling flow..................................................................................... 85 4.2.2 exception vector addresses................................................................................. 86 4.2.3 acceptance of exceptions .................................................................................... 88 4.2.4 exception codes................................................................................................... 90 4.2.5 exception request masks .................................................................................... 91 4.2.6 returning from exception handling .................................................................... 91 4.3 register descriptions....................................................................................................... .. 92 4.4 exception handling operation .......................................................................................... 93 4.4.1 reset..................................................................................................................... 93 4.4.2 interrupts .............................................................................................................. 93 4.4.3 general exceptions............................................................................................... 94 4.5 individual exception operations ....................................................................................... 94 4.5.1 resets ................................................................................................................... 9 4 4.5.2 general exceptions............................................................................................... 95 4.5.3 interrupts .............................................................................................................. 99 4.6 cautions.................................................................................................................... ......... 100 section 5 cache .................................................................................................................... 103 5.1 overview .................................................................................................................... ....... 103 5.1.1 features ................................................................................................................ 10 3
rev. 5.00, 09/03, page xix of xliv 5.1.2 cache structure .................................................................................................... 103 5.1.3 register configuration ......................................................................................... 105 5.2 register description ........................................................................................................ .. 105 5.2.1 cache control register (ccr)............................................................................. 105 5.2.2 cache control register 2 (ccr2)........................................................................ 106 5.3 cache operation ............................................................................................................. ... 109 5.3.1 searching the cache ............................................................................................. 109 5.3.2 read access ......................................................................................................... 111 5.3.3 prefetch operation................................................................................................ 111 5.3.4 write access ........................................................................................................ 111 5.3.5 write-back buffer................................................................................................ 111 5.3.6 coherency of cache and external memory.......................................................... 112 5.4 memory-mapped cache.................................................................................................... 112 5.4.1 address array ...................................................................................................... 112 5.4.2 data array............................................................................................................ 113 5.4.3 examples of usage............................................................................................... 115 section 6 interrupt controller (intc) ........................................................................... 117 6.1 overview .................................................................................................................... ....... 117 6.1.1 features ................................................................................................................ 11 7 6.1.2 block diagram ..................................................................................................... 118 6.1.3 pin configuration ................................................................................................. 119 6.1.4 register configuration ......................................................................................... 120 6.2 interrupt sources ........................................................................................................... .... 121 6.2.1 nmi interrupt ....................................................................................................... 121 6.2.2 irq interrupts ...................................................................................................... 121 6.2.3 irl interrupts....................................................................................................... 122 6.2.4 pint interrupts .................................................................................................... 124 6.2.5 on-chip peripheral module interrupts................................................................. 124 6.2.6 interrupt exception handling and priority ........................................................... 125 6.3 intc registers.............................................................................................................. .... 131 6.3.1 interrupt priority registers a to e (ipra?ipre) ................................................ 131 6.3.2 interrupt control register 0 (icr0) ..................................................................... 132 6.3.3 interrupt control register 1 (icr1) ..................................................................... 133 6.3.4 interrupt control register 2 (icr2) ..................................................................... 136 6.3.5 pint interrupt enable register (pinter) .......................................................... 137 6.3.6 interrupt request register 0 (irr0)..................................................................... 138 6.3.7 interrupt request register 1 (irr1)..................................................................... 140 6.3.8 interrupt request register 2 (irr2)..................................................................... 141 6.4 intc operation.............................................................................................................. ... 143 6.4.1 interrupt sequence................................................................................................ 143 6.4.2 multiple interrupts................................................................................................ 145 6.5 interrupt response time ................................................................................................... 14 5
rev. 5.00, 09/03, page xx of xliv section 7 user break controller ...................................................................................... 149 7.1 overview .................................................................................................................... ....... 149 7.1.1 features ................................................................................................................ 14 9 7.1.2 block diagram ..................................................................................................... 150 7.1.3 register configuration ......................................................................................... 151 7.2 register descriptions....................................................................................................... .. 152 7.2.1 break address register a (bara)...................................................................... 152 7.2.2 break address mask register a (bamra) ........................................................ 153 7.2.3 break bus cycle register a (bbra) .................................................................. 154 7.2.4 break address register b (barb)...................................................................... 156 7.2.5 break address mask register b (bamrb)......................................................... 157 7.2.6 break data register b (bdrb) ........................................................................... 158 7.2.7 break data mask register b (bdmrb) .............................................................. 159 7.2.8 break bus cycle register b (bbrb)................................................................... 160 7.2.9 break control register (brcr)........................................................................... 162 7.2.10 execution times break register (betr) ............................................................ 166 7.2.11 branch source register (brsr) .......................................................................... 167 7.2.12 branch destination register (brdr) .................................................................. 168 7.2.13 break asid register a (basra) ....................................................................... 169 7.2.14 break asid register b (basrb) ....................................................................... 169 7.3 operation description ....................................................................................................... 170 7.3.1 flow of the user break operation........................................................................ 170 7.3.2 break on instruction fetch cycle ......................................................................... 170 7.3.3 break by data access cycle ................................................................................ 171 7.3.4 sequential break .................................................................................................. 172 7.3.5 value of saved program counter......................................................................... 172 7.3.6 pc trace............................................................................................................... 173 7.3.7 usage examples ................................................................................................... 174 7.3.8 notes .................................................................................................................... 1 79 section 8 power-down modes ......................................................................................... 181 8.1 overview .................................................................................................................... ....... 181 8.1.1 power-down modes............................................................................................. 181 8.1.2 pin configuration ................................................................................................. 183 8.1.3 register configuration ......................................................................................... 183 8.2 register descriptions....................................................................................................... .. 183 8.2.1 standby control register (stbcr) ..................................................................... 183 8.2.2 standby control register 2 (stbcr2) ................................................................ 185 8.3 sleep mode.................................................................................................................. ...... 187 8.3.1 transition to sleep mode ..................................................................................... 187 8.3.2 canceling sleep mode.......................................................................................... 187 8.3.3 precautions when using the sleep mode ............................................................. 187 8.4 standby mode................................................................................................................ .... 188
rev. 5.00, 09/03, page xxi of xliv 8.4.1 transition to standby mode ................................................................................. 188 8.4.2 canceling standby mode ..................................................................................... 189 8.4.3 clock pause function........................................................................................... 190 8.5 module standby function ................................................................................................. 191 8.5.1 transition to module standby function............................................................... 191 8.5.2 clearing module standby function...................................................................... 191 8.6 timing of status pin changes...................................................................................... 192 8.6.1 timing for resets ................................................................................................. 192 8.6.2 timing for canceling standby ............................................................................. 194 8.6.3 timing for canceling sleep mode ....................................................................... 196 8.7 hardware standby mode................................................................................................... 199 8.7.1 transition to hardware standby mode ................................................................ 199 8.7.2 canceling hardware standby mode..................................................................... 199 8.7.3 hardware standby mode timing ......................................................................... 200 section 9 on-chip oscillation circuits ......................................................................... 203 9.1 overview .................................................................................................................... ....... 203 9.1.1 features ................................................................................................................ 20 3 9.2 overview of cpg ............................................................................................................. . 204 9.2.1 cpg block diagram............................................................................................. 204 9.2.2 cpg pin configuration ........................................................................................ 206 9.2.3 cpg register configuration................................................................................. 206 9.3 clock operating modes..................................................................................................... 20 7 9.4 register descriptions....................................................................................................... .. 211 9.4.1 frequency control register (frqcr) ................................................................. 211 9.5 changing the frequency.................................................................................................... 21 3 9.5.1 changing the multiplication rate ........................................................................ 213 9.5.2 changing the division ratio ................................................................................ 213 9.6 overview of wdt............................................................................................................. 214 9.6.1 block diagram of wdt ....................................................................................... 214 9.6.2 register configuration ......................................................................................... 214 9.7 wdt registers ............................................................................................................... ... 215 9.7.1 watchdog timer counter (wtcnt) ................................................................... 215 9.7.2 watchdog timer control/status register (wtcsr) ........................................... 215 9.7.3 notes on register access ..................................................................................... 217 9.8 using the wdt ............................................................................................................... .. 218 9.8.1 canceling standby................................................................................................ 218 9.8.2 changing the frequency....................................................................................... 218 9.8.3 using watchdog timer mode .............................................................................. 219 9.8.4 using interval timer mode.................................................................................. 219 9.9 notes on board design...................................................................................................... 2 20
rev. 5.00, 09/03, page xxii of xliv section 10 bus state controller (bsc) ......................................................................... 223 10.1 overview ................................................................................................................... ........ 223 10.1.1 features ................................................................................................................ 2 23 10.1.2 block diagram ..................................................................................................... 225 10.1.3 pin configuration ................................................................................................. 226 10.1.4 register configuration ......................................................................................... 228 10.1.5 area overview ..................................................................................................... 229 10.1.6 pcmcia support................................................................................................. 232 10.2 bsc registers.............................................................................................................. ...... 235 10.2.1 bus control register 1 (bcr1)............................................................................ 235 10.2.2 bus control register 2 (bcr2)............................................................................ 239 10.2.3 wait state control register 1 (wcr1) ................................................................ 240 10.2.4 wait state control register 2 (wcr2) ................................................................ 241 10.2.5 individual memory control register (mcr) ....................................................... 245 10.2.6 pcmcia control register (pcr) ........................................................................ 248 10.2.7 synchronous dram mode register (sdmr)..................................................... 252 10.2.8 refresh timer control/status register (rtcsr) ................................................ 253 10.2.9 refresh timer counter (rtcnt) ........................................................................ 255 10.2.10 refresh time constant register (rtcor).......................................................... 256 10.2.11 refresh count register (rfcr)........................................................................... 256 10.2.12 cautions on accessing refresh control related registers .................................. 257 10.2.13 mcs0 control register (mcscr0)..................................................................... 258 10.2.14 mcs1 control register (mcscr1)..................................................................... 259 10.2.15 mcs2 control register (mcscr2)..................................................................... 259 10.2.16 mcs3 control register (mcscr3)..................................................................... 259 10.2.17 mcs4 control register (mcscr4)..................................................................... 259 10.2.18 mcs5 control register (mcscr5)..................................................................... 259 10.2.19 mcs6 control register (mcscr6)..................................................................... 259 10.2.20 mcs7 control register (mcscr7)..................................................................... 259 10.3 bsc operation .............................................................................................................. .... 260 10.3.1 endian/access size and data alignment ............................................................. 260 10.3.2 description of areas............................................................................................. 265 10.3.3 basic interface...................................................................................................... 268 10.3.4 synchronous dram interface ............................................................................. 276 10.3.5 burst rom interface ............................................................................................ 304 10.3.6 pcmcia interface ............................................................................................... 307 10.3.7 waits between access cycles .............................................................................. 319 10.3.8 bus arbitration..................................................................................................... 320 10.3.9 bus pull-up .......................................................................................................... 321 10.3.10 mcs[0] to mcs[7] pin control ........................................................................... 323 section 11 direct memory access controller (dmac) .......................................... 327 11.1 overview ................................................................................................................... ........ 327
rev. 5.00, 09/03, page xxiii of xliv 11.1.1 features ................................................................................................................ 3 27 11.1.2 block diagram ..................................................................................................... 329 11.1.3 pin configuration ................................................................................................. 330 11.1.4 register configuration ......................................................................................... 331 11.2 register descriptions...................................................................................................... ... 333 11.2.1 dma source address registers 0?3 (sar0?sar3)........................................... 333 11.2.2 dma destination address registers 0?3 (dar0?dar3) .................................. 334 11.2.3 dma transfer count registers 0?3 (dmatcr0?dmatcr3) ......................... 335 11.2.4 dma channel control registers 0?3 (chcr0?chcr3) ................................... 336 11.2.5 dma operation register (dmaor) ................................................................... 343 11.3 operation.................................................................................................................. ......... 345 11.3.1 dma transfer flow............................................................................................. 345 11.3.2 dma transfer requests....................................................................................... 347 11.3.3 channel priority ................................................................................................... 349 11.3.4 dma transfer types ........................................................................................... 352 11.3.5 number of bus cycle states and dreq pin sampling timing........................... 363 11.3.6 source address reload function ......................................................................... 372 11.3.7 dma transfer ending conditions ....................................................................... 374 11.4 compare match timer (cmt) .......................................................................................... 376 11.4.1 overview .............................................................................................................. 376 11.4.2 register descriptions ........................................................................................... 377 11.4.3 operation.............................................................................................................. 38 0 11.4.4 compare match .................................................................................................... 381 11.5 examples of use............................................................................................................ .... 383 11.5.1 example of dma transfer between on-chip irda and external memory ........ 383 11.5.2 example of dma transfer between a/d converter and external memory........ 384 11.5.3 example of dma transfer between external memory and scif transmitter (indirect address on)........................................................................................... 385 11.6 usage notes................................................................................................................ ....... 387 section 12 timer (tmu) ................................................................................................... 389 12.1 overview ................................................................................................................... ........ 389 12.1.1 features ................................................................................................................ 3 89 12.1.2 block diagram ..................................................................................................... 390 12.1.3 pin configuration ................................................................................................. 391 12.1.4 register configuration ......................................................................................... 391 12.2 tmu registers .............................................................................................................. .... 392 12.2.1 timer output control register (tocr) .............................................................. 392 12.2.2 timer start register (tstr)................................................................................ 392 12.2.3 timer control registers (tcr)............................................................................ 393 12.2.4 timer constant registers (tcor)....................................................................... 397 12.2.5 timer counters (tcnt)....................................................................................... 397 12.2.6 input capture register (tcpr2) .......................................................................... 399
rev. 5.00, 09/03, page xxiv of xliv 12.3 tmu operation .............................................................................................................. ... 400 12.3.1 general operation ................................................................................................ 400 12.3.2 input capture function......................................................................................... 403 12.4 interrupts ................................................................................................................. .......... 404 12.4.1 status flag setting timing ................................................................................... 404 12.4.2 status flag clearing timing................................................................................. 405 12.4.3 interrupt sources and priorities ............................................................................ 405 12.5 usage notes................................................................................................................ ....... 406 12.5.1 writing to registers.............................................................................................. 406 12.5.2 reading registers................................................................................................. 406 section 13 realtime clock (rtc) .................................................................................. 407 13.1 overview ................................................................................................................... ........ 407 13.1.1 features ................................................................................................................ 4 07 13.1.2 block diagram ..................................................................................................... 408 13.1.3 pin configuration ................................................................................................. 409 13.1.4 rtc register configuration................................................................................. 410 13.2 rtc registers .............................................................................................................. ..... 411 13.2.1 64-hz counter (r64cnt).................................................................................... 411 13.2.2 second counter (rseccnt)............................................................................... 411 13.2.3 minute counter (rmincnt) .............................................................................. 412 13.2.4 hour counter (rhrcnt) .................................................................................... 412 13.2.5 day of week counter (rwkcnt)...................................................................... 413 13.2.6 date counter (rdaycnt).................................................................................. 414 13.2.7 month counter (rmoncnt).............................................................................. 414 13.2.8 year counter (ryrcnt) .................................................................................... 415 13.2.9 second alarm register (rsecar)...................................................................... 415 13.2.10 minute alarm register (rminar) ..................................................................... 416 13.2.11 hour alarm register (rhrar)........................................................................... 416 13.2.12 day of week alarm register (rwkar)............................................................. 417 13.2.13 date alarm register (rdayar) ........................................................................ 418 13.2.14 month alarm register (rmonar)..................................................................... 418 13.2.15 rtc control register 1 (rcr1) .......................................................................... 419 13.2.16 rtc control register 2 (rcr2) .......................................................................... 420 13.3 rtc operation .............................................................................................................. .... 422 13.3.1 initial settings of registers after power-on......................................................... 422 13.3.2 setting the time ................................................................................................... 422 13.3.3 reading the time ................................................................................................. 423 13.3.4 alarm function .................................................................................................... 424 13.3.5 crystal oscillator circuit...................................................................................... 425 13.4 usage notes................................................................................................................ ....... 426 13.4.1 register writing during rtc count .................................................................... 426 13.4.2 use of realtime clock (rtc) periodic interrupts ............................................... 426
rev. 5.00, 09/03, page xxv of xliv 13.4.3 precautions when using rtc module standby ................................................... 426 section 14 serial communication interface (sci) ..................................................... 427 14.1 overview ................................................................................................................... ........ 427 14.1.1 features ................................................................................................................ 4 27 14.1.2 block diagram ..................................................................................................... 428 14.1.3 pin configuration ................................................................................................. 431 14.1.4 register configuration ......................................................................................... 432 14.2 register descriptions...................................................................................................... ... 432 14.2.1 receive shift register (scrsr) .......................................................................... 432 14.2.2 receive data register (scrdr).......................................................................... 433 14.2.3 transmit shift register (sctsr)......................................................................... 433 14.2.4 transmit data register (sctdr) ........................................................................ 434 14.2.5 serial mode register (scsmr) ........................................................................... 434 14.2.6 serial control register (scscr) ......................................................................... 437 14.2.7 serial status register (scssr) ............................................................................ 440 14.2.8 sc port control register (scpcr)/sc port data register (scpdr) ................. 444 14.2.9 bit rate register (scbrr) .................................................................................. 446 14.3 operation.................................................................................................................. ......... 453 14.3.1 overview .............................................................................................................. 453 14.3.2 operation in asynchronous mode........................................................................ 455 14.3.3 multiprocessor communication ........................................................................... 465 14.3.4 synchronous operation ........................................................................................ 474 14.4 sci interrupts ............................................................................................................. ....... 484 14.5 usage notes................................................................................................................ ....... 485 section 15 smart card interface ...................................................................................... 489 15.1 overview ................................................................................................................... ........ 489 15.1.1 features ................................................................................................................ 4 89 15.1.2 block diagram ..................................................................................................... 490 15.1.3 pin configuration ................................................................................................. 491 15.1.4 smart card interface registers............................................................................. 491 15.2 register descriptions...................................................................................................... ... 492 15.2.1 smart card mode register (scscmr)................................................................ 492 15.2.2 serial status register (scssr) ............................................................................ 493 15.3 operation.................................................................................................................. ......... 494 15.3.1 overview .............................................................................................................. 494 15.3.2 pin connections.................................................................................................... 495 15.3.3 data format.......................................................................................................... 496 15.3.4 register settings................................................................................................... 497 15.3.5 clock .................................................................................................................... 498 15.3.6 data transmission and reception ........................................................................ 501 15.4 usage notes................................................................................................................ ....... 507
rev. 5.00, 09/03, page xxvi of xliv 15.4.1 receive data timing and receive margin in asynchronous mode .................... 507 15.4.2 retransmission (receive and transmit modes) ................................................... 509 section 16 serial communication interface with fifo (scif) ............................. 511 16.1 overview ................................................................................................................... ........ 511 16.1.1 features ................................................................................................................ 5 11 16.1.2 block diagram ..................................................................................................... 512 16.1.3 pin configuration ................................................................................................. 515 16.1.4 register configuration ......................................................................................... 516 16.2 register descriptions...................................................................................................... ... 517 16.2.1 receive shift register (scrsr) .......................................................................... 517 16.2.2 receive fifo data register (scfrdr).............................................................. 517 16.2.3 transmit shift register (sctsr)......................................................................... 517 16.2.4 transmit fifo data register (scftdr) ............................................................ 518 16.2.5 serial mode register (scsmr) ........................................................................... 518 16.2.6 serial control register (scscr) ......................................................................... 520 16.2.7 serial status register (scssr) ............................................................................ 522 16.2.8 bit rate register (scbrr) .................................................................................. 527 16.2.9 fifo control register (scfcr).......................................................................... 534 16.2.10 fifo data count register (scfdr) ................................................................... 536 16.3 operation.................................................................................................................. ......... 537 16.3.1 overview .............................................................................................................. 537 16.3.2 serial operation.................................................................................................... 538 16.4 scif interrupts ............................................................................................................ ...... 550 16.5 usage notes................................................................................................................ ....... 551 section 17 irda .................................................................................................................... 555 17.1 overview ................................................................................................................... ........ 555 17.1.1 features ................................................................................................................ 5 55 17.1.2 block diagram ..................................................................................................... 556 17.1.3 pin configuration ................................................................................................. 559 17.1.4 register configuration ......................................................................................... 560 17.2 register description ....................................................................................................... ... 561 17.2.1 serial mode register (scsmr) ........................................................................... 561 17.3 operation description ...................................................................................................... . 563 17.3.1 overview .............................................................................................................. 563 17.3.2 transmitting ......................................................................................................... 563 17.3.3 receiving.............................................................................................................. 56 4 section 18 pin function controller ................................................................................ 565 18.1 overview ................................................................................................................... ........ 565 18.2 register configuration ..................................................................................................... . 569 18.3 register descriptions...................................................................................................... ... 570
rev. 5.00, 09/03, page xxvii of xliv 18.3.1 port a control register (pacr).......................................................................... 570 18.3.2 port b control register (pbcr) .......................................................................... 571 18.3.3 port c control register (pccr) .......................................................................... 572 18.3.4 port d control register (pdcr).......................................................................... 573 18.3.5 port e control register (pecr)........................................................................... 574 18.3.6 port f control register (pfcr) ........................................................................... 575 18.3.7 port g control register (pgcr).......................................................................... 576 18.3.8 port h control register (phcr).......................................................................... 577 18.3.9 port j control register (pjcr) ............................................................................ 579 18.3.10 port k control register (pkcr).......................................................................... 580 18.3.11 port l control register (plcr)........................................................................... 581 18.3.12 sc port control register (scpcr)...................................................................... 582 section 19 i/o ports ............................................................................................................ 587 19.1 overview ................................................................................................................... ........ 587 19.2 port a ..................................................................................................................... ........... 587 19.2.1 register description ............................................................................................. 587 19.2.2 port a data register (padr) .............................................................................. 588 19.3 port b ..................................................................................................................... ........... 589 19.3.1 register description ............................................................................................. 589 19.3.2 port b data register (pbdr)............................................................................... 590 19.4 port c ..................................................................................................................... ........... 591 19.4.1 register description ............................................................................................. 591 19.4.2 port c data register (pcdr)............................................................................... 592 19.5 port d ..................................................................................................................... ........... 593 19.5.1 register description ............................................................................................. 593 19.5.2 port d data register (pddr) .............................................................................. 594 19.6 port e..................................................................................................................... ............ 595 19.6.1 register description ............................................................................................. 595 19.6.2 port e data register (pedr) ............................................................................... 596 19.7 port f..................................................................................................................... ............ 597 19.7.1 register description ............................................................................................. 597 19.7.2 port f data register (pfdr)................................................................................ 598 19.8 port g ..................................................................................................................... ........... 599 19.8.1 register description ............................................................................................. 599 19.8.2 port g data register (pgdr) .............................................................................. 600 19.9 port h ..................................................................................................................... ........... 601 19.9.1 register description ............................................................................................. 601 19.9.2 port h data register (phdr) .............................................................................. 602 19.10 port j.................................................................................................................... .............. 603 19.10.1 register description ............................................................................................. 603 19.10.2 port j data register (pjdr)................................................................................. 604 19.11 port k .................................................................................................................... ............ 605
rev. 5.00, 09/03, page xxviii of xliv 19.11.1 register description ............................................................................................. 605 19.11.2 port k data register (pkdr) .............................................................................. 606 19.12 port l.................................................................................................................... ............. 607 19.12.1 register description ............................................................................................. 607 19.12.2 port l data register (pldr) ............................................................................... 608 19.13 sc port ................................................................................................................... ........... 609 19.13.1 register description ............................................................................................. 609 19.13.2 sc port data register (scpdr) .......................................................................... 610 section 20 a/d converter ................................................................................................. 613 20.1 overview ................................................................................................................... ........ 613 20.1.1 features ................................................................................................................ 6 13 20.1.2 block diagram ..................................................................................................... 614 20.1.3 input pins.............................................................................................................. 6 15 20.1.4 register configuration ......................................................................................... 616 20.2 register descriptions...................................................................................................... ... 617 20.2.1 a/d data registers a to d (addra to addrd).............................................. 617 20.2.2 a/d control/status register (adcsr)................................................................ 618 20.2.3 a/d control register (adcr)............................................................................. 621 20.3 bus master interface....................................................................................................... ... 622 20.4 operation.................................................................................................................. ......... 623 20.4.1 single mode (multi = 0)................................................................................... 623 20.4.2 multi mode (multi = 1, scn = 0) .................................................................... 625 20.4.3 scan mode (multi = 1, scn = 1) ..................................................................... 627 20.4.4 input sampling and a/d conversion time.......................................................... 629 20.4.5 external trigger input timing ............................................................................. 630 20.5 interrupts ................................................................................................................. .......... 631 20.6 definitions of a/d conversion accuracy ......................................................................... 631 20.7 usage notes................................................................................................................ ....... 632 20.7.1 setting analog input voltage............................................................................... 632 20.7.2 processing of analog input pins .......................................................................... 632 20.7.3 access size and read data .................................................................................. 633 section 21 d/a converter ................................................................................................. 635 21.1 overview ................................................................................................................... ........ 635 21.1.1 features ................................................................................................................ 6 35 21.1.2 block diagram ..................................................................................................... 635 21.1.3 i/o pins................................................................................................................. 636 21.1.4 register configuration ......................................................................................... 636 21.2 register descriptions...................................................................................................... ... 637 21.2.1 d/a data registers 0 and 1 (dadr0/1) .............................................................. 637 21.2.2 d/a control register (dacr)............................................................................. 637 21.3 operation.................................................................................................................. ......... 639
rev. 5.00, 09/03, page xxix of xliv section 22 user debugging interface (udi) ............................................................... 641 22.1 overview ................................................................................................................... ........ 641 22.2 user debugging interface (udi)....................................................................................... 641 22.2.1 pin descriptions ................................................................................................... 641 22.2.2 block diagram ..................................................................................................... 642 22.3 register descriptions...................................................................................................... ... 642 22.3.1 bypass register (sdbpr).................................................................................... 643 22.3.2 instruction register (sdir).................................................................................. 643 22.3.3 boundary scan register (sdbsr)....................................................................... 644 22.4 udi operation.............................................................................................................. ..... 651 22.4.1 tap controller..................................................................................................... 651 22.4.2 reset configuration.............................................................................................. 652 22.4.3 udi reset............................................................................................................. 653 22.4.4 udi interrupt........................................................................................................ 653 22.4.5 bypass .................................................................................................................. 6 53 22.4.6 using udi to recover from sleep mode ............................................................. 653 22.5 boundary scan .............................................................................................................. .... 654 22.5.1 supported instructions.......................................................................................... 654 22.5.2 points for attention .............................................................................................. 655 22.6 usage notes................................................................................................................ ....... 655 22.7 advanced user debugger (aud) ..................................................................................... 655 section 23 electrical characteristics .............................................................................. 657 23.1 absolute maximum ratings.............................................................................................. 657 23.2 dc characteristics......................................................................................................... .... 659 23.3 ac characteristics......................................................................................................... .... 663 23.3.1 clock timing........................................................................................................ 664 23.3.2 control signal timing.......................................................................................... 670 23.3.3 ac bus timing .................................................................................................... 673 23.3.4 basic timing ........................................................................................................ 675 23.3.5 burst rom timing .............................................................................................. 678 23.3.6 synchronous dram timing ............................................................................... 681 23.3.7 pcmcia timing.................................................................................................. 699 23.3.8 peripheral module signal timing ........................................................................ 706 23.3.9 udi-related pin timing ...................................................................................... 709 23.3.10 ac characteristics measurement conditions....................................................... 711 23.3.11 delay time variation due to load capacitance.................................................. 712 23.4 a/d converter characteristics........................................................................................... 71 3 23.5 d/a converter characteristics........................................................................................... 713 appendix a pin functions ................................................................................................ 715 a.1 pin states .................................................................................................................. ......... 715 a.2 pin specifications .......................................................................................................... .... 719
rev. 5.00, 09/03, page xxx of xliv a.3 treatment of unused pins ................................................................................................. 724 a.4 pin states in access to each address space ..................................................................... 725 appendix b memory-mapped control registers ....................................................... 739 b.1 register address map ....................................................................................................... 7 39 b.2 register bits ............................................................................................................... ....... 745 appendix c product lineup ............................................................................................. 757 appendix d package dimensions ................................................................................... 758
rev. 5.00, 09/03, page xxxi of xliv figures figure 1.1 block diagram ..................................................................................................... 6 figure 1.2 pin assignment (fp-208c, fp-208e) .................................................................. 7 figure 1.3 pin assignment (bp-240a).................................................................................. 8 figure 2.1 user mode register configuration ...................................................................... 20 figure 2.2 privileged mode register configuration.............................................................. 21 figure 2.3 general registers ................................................................................................. 22 figure 2.4 system registers .................................................................................................. 23 figure 2.5 register set overview, control registers............................................................ 24 figure 2.6 longword ............................................................................................................. 25 figure 2.7 data format in memory ....................................................................................... 25 figure 2.8 processor state transitions................................................................................... 54 figure 3.1 mmu functions ................................................................................................... 57 figure 3.2 virtual address space mapping........................................................................... 59 figure 3.3 mmu register contents ...................................................................................... 62 figure 3.4 overall configuration of the tlb ........................................................................ 63 figure 3.5 virtual address and tlb structure...................................................................... 64 figure 3.6 tlb indexing (ix = 1) ......................................................................................... 65 figure 3.7 tlb indexing (ix = 0) ......................................................................................... 66 figure 3.8 objects of address comparison........................................................................... 67 figure 3.9 operation of ldtlb instruction.......................................................................... 71 figure 3.10 synonym problem ................................................................................................ 73 figure 3.11 mmu exception generation flowchart ............................................................... 78 figure 3.12 mmu exception signals in instruction fetch...................................................... 79 figure 3.13 mmu exception signals in data access ............................................................. 80 figure 3.14 specifying address and data for memory-mapped tlb access ........................ 82 figure 4.1 vector table......................................................................................................... 86 figure 4.2 example of acceptance order of general exceptions ......................................... 89 figure 4.3 bit configurations of expevt, intevt, intevt2, and tra registers......... 92 figure 5.1 cache structure .................................................................................................... 10 4 figure 5.2 ccr register configuration ................................................................................ 106 figure 5.3 ccr2 register configuration .............................................................................. 107 figure 5.4 cache search scheme (normal mode) ................................................................ 110 figure 5.5 write-back buffer configuration......................................................................... 112 figure 5.6 specifying address and data for memory-mapped cache access...................... 114 figure 6.1 block diagram of intc....................................................................................... 118 figure 6.2 example of irl interrupt connection.................................................................. 122 figure 6.3 interrupt operation flowchart.............................................................................. 144 figure 6.4 example of pipeline operations when irl interrupt is accepted ....................... 148 figure 7.1 block diagram of user break controller............................................................. 150 figure 8.1 canceling standby mode with stbcr.stby..................................................... 189 figure 8.2 power-on reset (clock modes 0, 1, 2, and 7) status output ......................... 192
rev. 5.00, 09/03, page xxxii of xliv figure 8.3 manual reset status output............................................................................ 193 figure 8.4 standby to interrupt status output.................................................................. 194 figure 8.5 standby to power-on reset status output...................................................... 195 figure 8.6 standby to manual reset status output.......................................................... 196 figure 8.7 sleep to interrupt status output ...................................................................... 196 figure 8.8 sleep to power-on reset status output.......................................................... 197 figure 8.9 sleep to manual reset status output.............................................................. 198 figure 8.10 hardware standby mode (when ca goes low in normal operation)............... 200 figure 8.11 hardware standby mode timing (when ca goes low during wdt operation on standby mode cancellation) ........................................................................... 201 figure 9.1 block diagram of clock pulse generator ............................................................ 204 figure 9.2 block diagram of wdt ....................................................................................... 214 figure 9.3 writing to wtcnt and wtcsr......................................................................... 217 figure 9.4 points for attention when using crystal resonator............................................. 220 figure 9.5 points for attention when using pll oscillator circuit ..................................... 221 figure 10.1 block diagram of bus state controller................................................................ 225 figure 10.2 correspondence between logical address space and physical address space .. 229 figure 10.3 physical space allocation .................................................................................... 231 figure 10.4 pcmcia space allocation .................................................................................. 232 figure 10.5 writing to rfcr, rtcsr, rtcnt, and rtcor............................................... 257 figure 10.6 basic timing of basic interface ........................................................................... 269 figure 10.7 example of 32-bit data-width static ram connection ..................................... 270 figure 10.8 example of 16-bit data-width static ram connection ..................................... 271 figure 10.9 example of 8-bit data-width static ram connection ....................................... 272 figure 10.10 basic interface wait timing (software wait only)............................................. 273 figure 10.11 basic interface wait state timing (wait state insertion by wait signal waitsel = 1)..................................................................................................... 275 figure 10.12 example of 64-mbit synchronous dram connection (32-bit bus width)........ 277 figure 10.13 example of 64-mbit synchronous dram connection (16-bit bus width)........ 278 figure 10.14 basic timing for synchronous dram burst read ............................................. 282 figure 10.15 synchronous dram burst read wait specification timing .............................. 283 figure 10.16 basic timing for synchronous dram single read............................................ 284 figure 10.17 basic timing for synchronous dram burst write ............................................ 286 figure 10.18 basic timing for synchronous dram single write........................................... 288 figure 10.19 burst read timing (no precharge)...................................................................... 291 figure 10.20 burst read timing (same row address) ............................................................ 292 figure 10.21 burst read timing (different row addresses) ................................................... 293 figure 10.22 burst write timing (no precharge) ..................................................................... 294 figure 10.23 burst write timing (same row address) ........................................................... 295 figure 10.24 burst write timing (different row addresses) .................................................. 296 figure 10.25 auto-refresh operation ....................................................................................... 298 figure 10.26 synchronous dram auto-refresh timing......................................................... 299 figure 10.27 synchronous dram self-refresh timing .......................................................... 301
rev. 5.00, 09/03, page xxxiii of xliv figure 10.28 synchronous dram mode write timing ........................................................... 303 figure 10.29 burst rom wait access timing ......................................................................... 305 figure 10.30 burst rom basic access timing ........................................................................ 306 figure 10.31 example of pcmcia interface ............................................................................ 308 figure 10.32 basic timing for pcmcia memory card interface ............................................ 310 figure 10.33 wait timing for pcmcia memory card interface ............................................. 311 figure 10.34 basic timing for pcmcia memory card interface burst access ...................... 312 figure 10.35 wait timing for pcmcia memory card interface burst access ....................... 313 figure 10.36 pcmcia space allocation .................................................................................. 314 figure 10.37 basic timing for pcmcia i/o card interface .................................................... 316 figure 10.38 wait timing for pcmcia i/o card interface ..................................................... 317 figure 10.39 dynamic bus sizing timing for pcmcia i/o card interface ............................ 318 figure 10.40 waits between access cycles .............................................................................. 320 figure 10.41 pull-up timing for pins a25 to a0 ..................................................................... 321 figure 10.42 pull-up timing for pins d31 to d0 (read cycle) ............................................... 322 figure 10.43 pull-up timing for pins d31 to d0 (write cycle) .............................................. 322 figure 11.1 block diagram of dmac .................................................................................... 329 figure 11.2 dmac transfer flowchart .................................................................................. 346 figure 11.3 round-robin mode.............................................................................................. 350 figure 11.4 changes in channel priority in round-robin mode............................................ 351 figure 11.5 operation of direct address mode in dual address mode ................................. 353 figure 11.6 example of dma transfer timing in the direct address mode in dual mode (transfer source: ordinary memory, transfer destination: ordinary memory). 354 figure 11.7 indirect address operation in dual address mode (when external memory space has a 16-bit width).................................................................................... 355 figure 11.8 example of transfer timing in the indirect address mode in dual address mode .................................................................................................................... 356 figure 11.9 data flow in single address mode...................................................................... 357 figure 11.10 example of dma transfer timing in single address mode .............................. 358 figure 11.11 example of dma transfer timing in single address mode (16-byte transfer, external memory space (ordinary memory) external device with dack) . 359 figure 11.12 example of dma transfer in cycle-steal mode................................................. 360 figure 11.13 example of transfer in burst mode..................................................................... 360 figure 11.14 bus state when multiple channels are operating............................................... 362 figure 11.15 cycle-steal mode, level input (cpu access: 2 cycles) ..................................... 365 figure 11.16 cycle-steal mode, level input (cpu access: 3 cycles) ..................................... 366 figure 11.17 cycle-steal mode, level input (cpu access: 2 cycles, dma rd access: 4 cycles)............................................................................................................... 367 figure 11.18 cycle-steal mode, level input (cpu access: 2 cycles, dreq input delayed). 368 figure 11.19 cycle-steal mode, edge input (cpu access: 2 cycles) ...................................... 369 figure 11.20 burst mode, level input ...................................................................................... 370 figure 11.21 burst mode, edge input ....................................................................................... 371 figure 11.22 source address reload function diagram........................................................... 372
rev. 5.00, 09/03, page xxxiv of xliv figure 11.23 timing chart of source address reload function............................................... 373 figure 11.24 block diagram of cmt ....................................................................................... 376 figure 11.25 counter operation ................................................................................................ 38 0 figure 11.26 count timing ....................................................................................................... 381 figure 11.27 cmf setting timing ............................................................................................ 382 figure 11.28 timing of cmf clearing by the cpu .................................................................. 382 figure 12.1 block diagram of tmu ....................................................................................... 390 figure 12.2 setting the count operation ................................................................................. 401 figure 12.3 auto-reload count operation.............................................................................. 402 figure 12.4 count timing when operating on internal clock ................................................ 402 figure 12.5 count timing when operating on external clock (both edges detected).......... 403 figure 12.6 count timing when operating on on-chip rtc clock...................................... 403 figure 12.7 operation timing when using input capture function (using tclk rising edge) .................................................................................................................... 404 figure 12.8 unf setting timing............................................................................................. 404 figure 12.9 status flag clearing timing................................................................................. 405 figure 13.1 block diagram of rtc ........................................................................................ 408 figure 13.2 setting the time ................................................................................................... 4 22 figure 13.3 reading the time ................................................................................................. 423 figure 13.4 using the alarm function .................................................................................... 424 figure 13.5 example of crystal oscillator circuit connection............................................... 425 figure 13.6 using periodic interrupt function ........................................................................ 426 figure 14.1 block diagram of sci.......................................................................................... 428 figure 14.2 scpt[1]/sck0 pin .............................................................................................. 429 figure 14.3 scpt[0]/txd0 pin............................................................................................... 430 figure 14.4 scpt[0]/rxd0 pin............................................................................................... 431 figure 14.5 example of data format in asynchronous communication (8-bit data with parity and two stop bits) ............................................................................ 455 figure 14.6 output clock and serial data timing (asynchronous mode) ............................. 457 figure 14.7 sample flowchart for sci initialization............................................................... 458 figure 14.8 sample flowchart for transmitting serial data................................................... 459 figure 14.9 example of sci transmit operation in asynchronous mode (8-bit data with parity and one stop bit) .............................................................................. 461 figure 14.10 sample flowchart for receiving serial data ....................................................... 462 figure 14.11 example of sci receive operation (8-bit data with parity and one stop bit) .. 465 figure 14.12 communication among processors using multiprocessor format (sending data h'aa to receiving processor a).................................................. 466 figure 14.13 sample flowchart for transmitting multiprocessor serial data.......................... 467 figure 14.14 example of sci multiprocessor transmit operation (8-bit data with multiprocessor bit and one stop bit) .................................................................. 468 figure 14.15 sample flowchart for receiving multiprocessor serial data .............................. 470 figure 14.16 example of sci receive operation (8-bit data with multiprocessor bit and one stop bit)........................................................................................................ 472
rev. 5.00, 09/03, page xxxv of xliv figure 14.17 data format in synchronous communication ..................................................... 474 figure 14.18 sample flowchart for sci initialization............................................................... 476 figure 14.19 sample flowchart for transmitting serial data................................................... 477 figure 14.20 example of sci transmit operation.................................................................... 478 figure 14.21 sample flowchart for receiving serial data ....................................................... 480 figure 14.22 example of sci receive operation...................................................................... 482 figure 14.23 sample flowchart for transmitting/receiving serial data.................................. 483 figure 14.24 receive data sampling timing in asynchronous mode ..................................... 486 figure 15.1 block diagram of smart card interface............................................................... 490 figure 15.2 pin connection diagram for smart card interface .............................................. 495 figure 15.3 data format for smart card interface.................................................................. 496 figure 15.4 waveform of start character................................................................................ 498 figure 15.5 initialization flowchart (example)....................................................................... 502 figure 15.6 transmission flowchart ....................................................................................... 504 figure 15.7 reception flowchart (example)........................................................................... 506 figure 15.8 receive data sampling timing in smart card mode .......................................... 508 figure 15.9 retransmission in sci receive mode .................................................................. 509 figure 15.10 retransmission in sci transmit mode ................................................................ 510 figure 16.1 block diagram of scif........................................................................................ 512 figure 16.2 scpt[5]/sck2 pin .............................................................................................. 513 figure 16.3 scpt[4]/txd2 pin............................................................................................... 514 figure 16.4 scpt[4]/rxd2 pin............................................................................................... 515 figure 16.5 sample flowchart for scif initialization ............................................................ 540 figure 16.6 sample flowchart for transmitting serial data................................................... 542 figure 16.7 example of transmit operation (8-bit data, parity, one stop bit)..................... 544 figure 16.8 example of operation using modem control ( cts )........................................... 544 figure 16.9 sample flowchart for receiving serial data ....................................................... 546 figure 16.10 sample flowchart for receiving serial data (cont)............................................. 547 figure 16.11 example of scif receive operation (8-bit data, parity, one stop bit)............. 549 figure 16.12 example of operation using modem control ( rts )........................................... 549 figure 16.13 receive data sampling timing in asynchronous mode ..................................... 552 figure 17.1 block diagram of irda........................................................................................ 556 figure 17.2 scpt[3]/sck1 pin .............................................................................................. 557 figure 17.3 scpt[2]/txd1 pin............................................................................................... 558 figure 17.4 scpt[2]/rxd1 pin............................................................................................... 559 figure 17.5 transmit/receive operation................................................................................. 564 figure 19.1 port a .............................................................................................................. ..... 587 figure 19.2 port b .............................................................................................................. ..... 589 figure 19.3 port c .............................................................................................................. ..... 591 figure 19.4 port d .............................................................................................................. ..... 593 figure 19.5 port e.............................................................................................................. ...... 595 figure 19.6 port f.............................................................................................................. ...... 597 figure 19.7 port g .............................................................................................................. ..... 599
rev. 5.00, 09/03, page xxxvi of xliv figure 19.8 port h .............................................................................................................. ..... 601 figure 19.9 port j .............................................................................................................. ...... 603 figure 19.10 port k ............................................................................................................. ...... 605 figure 19.11 port l............................................................................................................. ....... 607 figure 19.12 sc port ............................................................................................................ ..... 609 figure 20.1 block diagram of a/d converter ........................................................................ 614 figure 20.2 a/d data register access operation (reading h'aa40).................................... 622 figure 20.3 example of a/d converter operation (single mode, channel 1 selected) ......... 624 figure 20.4 example of a/d converter operation (multi mode, channels an0 to an2 selected)............................................................................................................... 626 figure 20.5 example of a/d converter operation (scan mode, channels an0 to an2 selected)............................................................................................................... 628 figure 20.6 a/d conversion timing....................................................................................... 629 figure 20.7 external trigger input timing ............................................................................. 630 figure 20.8 definitions of a/d conversion accuracy ............................................................ 632 figure 20.9 example of analog input protection circuit ........................................................ 633 figure 20.10 analog input pin equivalent circuit .................................................................... 633 figure 21.1 block diagram of d/a converter ........................................................................ 635 figure 21.2 example of d/a converter operation.................................................................. 639 figure 22.1 block diagram of udi ......................................................................................... 642 figure 22.2 tap controller state transitions ......................................................................... 651 figure 22.3 udi reset........................................................................................................... .. 653 figure 23.1 extal clock input timing ................................................................................ 665 figure 23.2 ckio clock input timing ................................................................................... 665 figure 23.3 ckio clock output timing................................................................................. 665 figure 23.4 power-on oscillation settling time ..................................................................... 666 figure 23.5 oscillation settling time at standby return (return by reset)........................... 666 figure 23.6 oscillation settling time at standby return (return by nmi)............................ 667 figure 23.7 oscillation settling time at standby return (return by irq4 to irq0, pint0/1, irl3 to irl0 )....................................................................................... 667 figure 23.8 pll synchronization settling time during standby recovery (reset or nmi).. 668 figure 23.9 pll synchronization settling time during standby recovery (irq/irl or pint0/pint1 interrupt)....................................................................................... 668 figure 23.10 pll synchronization settling time when frequency multiplication rate modified............................................................................................................... 669 figure 23.11 reset input timing............................................................................................... 67 1 figure 23.12 interrupt signal input timing............................................................................... 671 figure 23.13 irqout timing .................................................................................................. 671 figure 23.14 bus release timing.............................................................................................. 672 figure 23.15 pin drive timing at standby................................................................................ 672 figure 23.16 basic bus cycle (no wait) .................................................................................. 675 figure 23.17 basic bus cycle (one wait)................................................................................. 676 figure 23.18 basic bus cycle (external wait, waitsel = 1) ................................................ 677
rev. 5.00, 09/03, page xxxvii of xliv figure 23.19 burst rom bus cycle (no wait) ........................................................................ 678 figure 23.20 burst rom bus cycle (two waits) .................................................................... 679 figure 23.21 burst rom bus cycle (external wait, waitsel = 1) ...................................... 680 figure 23.22 synchronous dram read bus cycle (rcd = 0, cas latency = 1, tpc = 0) .. 681 figure 23.23 synchronous dram read bus cycle (rcd = 2, cas latency = 2, tpc = 1) .. 682 figure 23.24 synchronous dram read bus cycle (burst read (single read 4), rcd = 0, cas latency = 1, tpc = 1) ................................................................. 683 figure 23.25 synchronous dram read bus cycle (burst read (single read 4), rcd = 1, cas latency = 3, tpc = 0) ................................................................. 684 figure 23.26 synchronous dram write bus cycle (rcd = 0, tpc = 0, trwl = 0)............ 685 figure 23.27 synchronous dram write bus cycle (rcd = 2, tpc = 1, trwl = 1)............ 686 figure 23.28 synchronous dram write bus cycle (burst mode (single write 4), rcd = 0, tpc = 1, trwl = 0) ........................................................................... 687 figure 23.29 synchronous dram write bus cycle (burst mode (single write 4), rcd = 1, tpc = 0, trwl = 0) ........................................................................... 688 figure 23.30 synchronous dram burst read bus cycle (ras down, same row address, cas latency = 1).................................................................................. 689 figure 23.31 synchronous dram burst read bus cycle (ras down, same row address, cas latency = 2).................................................................................. 690 figure 23.32 synchronous dram burst read bus cycle (ras down, different row address, tpc = 0, rcd = 0, cas latency = 1).................................................. 691 figure 23.33 synchronous dram burst read bus cycle (ras down, different row address, tpc = 1, rcd = 0, cas latency = 1).................................................. 692 figure 23.34 synchronous dram burst write bus cycle (ras down, same row address) ............................................................................................................... 693 figure 23.35 synchronous dram burst write bus cycle (ras down, different row address, tpc = 0, rcd = 0) ............................................................................... 694 figure 23.36 synchronous dram burst write bus cycle (ras down, different row address, tpc = 1, rcd = 1) ............................................................................... 695 figure 23.37 synchronous dram auto-refresh timing (tras = 1, tpc = 1) ..................... 696 figure 23.38 synchronous dram self-refresh cycle (tras = 1, tpc = 1) ......................... 697 figure 23.39 synchronous dram mode register write cycle ............................................... 698 figure 23.40 pcmcia memory bus cycle (ted = 0, teh = 0, no wait) ............................. 699 figure 23.41 pcmcia memory bus cycle (ted = 2, teh = 1, one wait, external wait, waitsel = 1)..................................................................................................... 700 figure 23.42 pcmcia memory bus cycle (burst read, ted = 0, teh = 0, no wait).......... 701 figure 23.43 pcmcia memory bus cycle (burst read, ted = 1, teh = 1, two waits, burst pitch = 3, waitsel = 1)........................................................................... 702 figure 23.44 pcmcia i/o bus cycle (ted = 0, teh = 0, no wait)...................................... 703 figure 23.45 pcmcia i/o bus cycle (ted = 2, teh = 1, one wait, external wait, waitsel = 1)..................................................................................................... 704 figure 23.46 pcmcia i/o bus cycle (ted = 1, teh = 1, one wait, bus sizing, waitsel = 1)..................................................................................................... 705
rev. 5.00, 09/03, page xxxv iii of xliv figure 23.47 tclk input timing ............................................................................................. 707 figure 23.48 tclk clock input timing................................................................................... 707 figure 23.49 oscillation settling time at rtc crystal oscillator power-on............................ 707 figure 23.50 sck input clock timing ..................................................................................... 707 figure 23.51 sci i/o timing in clock synchronous mode ...................................................... 708 figure 23.52 i/o port timing .................................................................................................... 708 figure 23.53 dreq input timing............................................................................................. 708 figure 23.54 drak output timing.......................................................................................... 709 figure 23.55 tck input timing................................................................................................ 709 figure 23.56 trst input timing (reset hold)......................................................................... 710 figure 23.57 udi data transfer timing ................................................................................... 710 figure 23.58 asemd0 input timing........................................................................................ 710 figure 23.59 output load circuit.............................................................................................. 71 1 figure 23.60 load capacitance vs. delay time........................................................................ 712 figure d.1 package dimensions (fp-208c)........................................................................... 758 figure d.2 package dimensions (fp-208e)........................................................................... 759 figure d.3 package dimensions (bp-240a).......................................................................... 760
rev. 5.00, 09/03, page xxxix of xliv tables table 1.1 sh7709s features .................................................................................................. 2 table 1.2 characteristics....................................................................................................... .. 5 table 1.3 sh7709s pin function ........................................................................................... 9 table 2.1 initial register values ............................................................................................ 22 table 2.2 addressing modes and effective addresses........................................................... 28 table 2.3 instruction formats................................................................................................. 32 table 2.4 classification of instructions .................................................................................. 35 table 2.5 instruction code format ......................................................................................... 38 table 2.6 data transfer instructions ...................................................................................... 39 table 2.7 arithmetic instructions ........................................................................................... 41 table 2.8 logic operation instructions .................................................................................. 44 table 2.9 shift instructions.................................................................................................... .45 table 2.10 branch instructions................................................................................................. 4 6 table 2.11 system control instructions.................................................................................... 47 table 2.12 instruction code map ............................................................................................. 50 table 3.1 register configuration............................................................................................ 61 table 3.2 access states designated by d, c, and pr bits ..................................................... 68 table 4.1 register configuration............................................................................................ 85 table 4.2 exception event vectors ........................................................................................ 87 table 4.3 exception codes ..................................................................................................... 90 table 4.4 types of reset ........................................................................................................ 95 table 5.1 cache specifications............................................................................................... 103 table 5.2 lru and way replacement (when the cache lock function is not used) .............. 105 table 5.3 register configuration............................................................................................ 105 table 5.4 way replacement when pref instruction ended up in a cache miss ................. 107 table 5.5 way replacement when instructions except for pref instruction ended up in a cache miss....................................................................................................... 108 table 5.6 lru and way replacement (when w2lock=1) ................................................. 108 table 5.7 lru and way replacement (when w3lock=1) ................................................. 108 table 5.8 lru and way replacement (when w2lock=1 and w3lock=1)..................... 108 table 6.1 intc pins ............................................................................................................. .. 119 table 6.2 intc registers ....................................................................................................... 1 20 table 6.3 irl3 ? irl0 / irls3 ? irls0 pins and interrupt levels ............................................ 123 table 6.4 interrupt exception handling sources and priority (irq mode) ........................... 126 table 6.5 interrupt exception handling sources and priority (irl mode)............................ 128 table 6.6 interrupt levels and intevt codes...................................................................... 130 table 6.7 interrupt request sources and ipra?ipre............................................................ 131 table 6.8 interrupt response time......................................................................................... 146 table 7.1 register configuration............................................................................................ 151 table 7.2 data access cycle addresses and operand size comparison conditions............. 171 table 8.1 power-down modes ............................................................................................... 182
rev. 5.00, 09/03, page xl of xliv table 8.2 pin configuration.................................................................................................... 1 83 table 8.3 register configuration............................................................................................ 183 table 8.4 register states in standby mode ............................................................................ 188 table 9.1 cpg pins and functions ......................................................................................... 206 table 9.2 cpg register .......................................................................................................... 206 table 9.3 clock operating modes .......................................................................................... 207 table 9.4 available combinations of clock mode and frqcr values................................ 208 table 9.5 register configuration............................................................................................ 214 table 10.1 bsc pins............................................................................................................. .... 226 table 10.2 bsc registers........................................................................................................ . 228 table 10.3 physical address space map.................................................................................. 230 table 10.4 correspondence between external pins (md4 and md3) and memory size......... 231 table 10.5 pcmcia interface characteristics ......................................................................... 232 table 10.6 pcmcia support interface .................................................................................... 233 table 10.7 32-bit external device/big-endian access and data alignment .......................... 260 table 10.8 16-bit external device/big-endian access and data alignment .......................... 261 table 10.9 8-bit external device/big-endian access and data alignment ............................ 262 table 10.10 32-bit external device/little-endian access and data alignment........................ 263 table 10.11 16-bit external device/little-endian access and data alignment........................ 263 table 10.12 8-bit external device/little-endian access and data alignment.......................... 264 table 10.13 relationship between bus width, amx bits, and address multiplex output....... 279 table 10.14 example of correspondence between sh7709s and synchronous dram address pins (amx [3:0] = 0100 (32-bit bus width)).......................................... 281 table 10.15 mcscrx settings and mcs[x] assertion conditions (x: 0?7).............................. 324 table 11.1 dmac pins ............................................................................................................ 330 table 11.2 dmac registers .................................................................................................... 331 table 11.3 selecting external request modes with rs bits .................................................... 347 table 11.4 selecting on-chip peripheral module request modes with rs3-0 bits................ 348 table 11.5 supported dma transfers...................................................................................... 352 table 11.6 relationship between request modes and bus modes by dma transfer category ................................................................................................................. 361 table 11.7 register configuration............................................................................................ 377 table 11.8 transfer conditions and register settings for transfer between on-chip sci and external memory ............................................................................................. 383 table 11.9 transfer conditions and register settings for transfer between on-chip a/d converter and external memory ............................................................................ 384 table 11.10 values in dmac after end of fourth transfer ...................................................... 385 table 11.11 transfer conditions and register settings for transfer between external memory and scif transmitter............................................................................... 386 table 12.1 tmu pin.............................................................................................................. ... 391 table 12.2 tmu registers........................................................................................................ 391 table 12.3 tmu interrupt sources........................................................................................... 405 table 13.1 rtc pins............................................................................................................. .... 409
rev. 5.00, 09/03, page xli of xliv table 13.2 rtc registers........................................................................................................ . 410 table 13.3 day-of-week codes (rwkcnt) .......................................................................... 413 table 13.4 day-of-week codes (rwkar) ............................................................................. 417 table 13.5 recommended oscillator circuit constants (recommended values).................... 425 table 14.1 sci pins ............................................................................................................. .... 431 table 14.2 sci registers ........................................................................................................ .. 432 table 14.3 scsmr settings ..................................................................................................... 44 6 table 14.4 bit rates and scbrr settings in asynchronous mode......................................... 447 table 14.5 bit rates and scbrr settings in synchronous mode ........................................... 450 table 14.6 maximum bit rates for various frequencies with baud rate generator (asynchronous mode) ............................................................................................ 451 table 14.7 maximum bit rates with external clock input (asynchronous mode)................. 452 table 14.8 maximum bit rates with external clock input (synchronous mode) ................... 452 table 14.9 serial mode register settings and sci communication formats .......................... 454 table 14.10 scsmr and scscr settings and sci clock source selection............................. 454 table 14.11 serial communication formats (asynchronous mode) ......................................... 456 table 14.12 receive error conditions and sci operation......................................................... 464 table 14.13 sci interrupt sources ............................................................................................. 48 4 table 14.14 scssr status flags and transfer of receive data ................................................ 485 table 15.1 smart card interface pins ....................................................................................... 491 table 15.2 registers ............................................................................................................ ..... 491 table 15.3 register settings for smart card interface ............................................................. 497 table 15.4 relationship of n to cks1 and cks0..................................................................... 499 table 15.5 examples of bit rate b (bits/s) for scbrr settings (n = 0)................................. 499 table 15.6 examples of scbrr settings for bit rate b (bits/s) (n = 0)................................. 499 table 15.7 maximum bit rates for frequencies (smart card interface mode)....................... 500 table 15.8 register set values and sck pin ........................................................................... 500 table 15.9 smart card mode operating state and interrupt sources....................................... 507 table 16.1 scif pins............................................................................................................ .... 515 table 16.2 scif registers ....................................................................................................... . 516 table 16.3 scsmr settings ..................................................................................................... 52 8 table 16.4 bit rates and scbrr settings ............................................................................... 528 table 16.5 maximum bit rates for various frequencies with baud rate generator (asynchronous mode) ............................................................................................ 532 table 16.6 maximum bit rates with external clock input (asynchronous mode)................. 533 table 16.7 scsmr settings and scif communication formats ............................................ 537 table 16.8 scscr settings and scif clock source selection................................................ 538 table 16.9 serial communication formats .............................................................................. 538 table 16.10 scif interrupt sources ........................................................................................... 550 table 17.1 irda pins............................................................................................................ .... 559 table 17.2 irda registers ....................................................................................................... . 560 table 18.1 list of multiplexed pins ......................................................................................... 565 table 18.2 pin function controller registers........................................................................... 569
rev. 5.00, 09/03, page xlii of xliv table 19.1 port a register ...................................................................................................... . 587 table 19.2 port a data register (padr) read/write operations ........................................... 588 table 19.3 port b register...................................................................................................... .. 589 table 19.4 port b data register (pbdr) read/write operations ........................................... 590 table 19.5 port c register...................................................................................................... .. 591 table 19.6 port c data register (pcdr) read/write operations ........................................... 592 table 19.7 port d register ...................................................................................................... . 593 table 19.8 port d data register (pddr) read/write operations ........................................... 594 table 19.9 port e register...................................................................................................... .. 595 table 19.10 port e data register (pedr) read/write operations............................................ 596 table 19.11 port f register ..................................................................................................... ... 597 table 19.12 port f data register (pfdr) read/write operations ............................................ 598 table 19.13 port g register ..................................................................................................... .. 599 table 19.14 port g data register (pgdr) read/write operations ........................................... 600 table 19.15 port h register ..................................................................................................... .. 601 table 19.16 port h data register (phdr) read/write operations ........................................... 602 table 19.17 port j register..................................................................................................... .... 603 table 19.18 port j data register (pjdr) read/write operations.............................................. 604 table 19.19 port k register ..................................................................................................... .. 605 table 19.20 port k data register (pkdr) read/write operations ........................................... 606 table 19.21 port l register..................................................................................................... ... 607 table 19.22 port l data register (pldr) read/write operation ............................................. 608 table 19.23 sc port register .................................................................................................... . 609 table 19.24 read/write operation of the sc port data register (scpdr) .............................. 611 table 20.1 a/d converter pins................................................................................................. 61 5 table 20.2 a/d converter registers......................................................................................... 616 table 20.3 analog input channels and a/d data registers .................................................... 617 table 20.4 a/d conversion time (single mode)..................................................................... 630 table 20.5 analog input pin ratings........................................................................................ 634 table 20.6 relationship between access size and read data ................................................. 634 table 21.1 d/a converter pins................................................................................................. 63 6 table 21.2 d/a converter registers......................................................................................... 636 table 22.1 udi registers ........................................................................................................ . 643 table 22.2 udi commands ...................................................................................................... 644 table 22.3 pins of this lsi and boundary scan register bits.................................................. 645 table 22.4 reset configuration ................................................................................................ 65 2 table 23.1 absolute maximum ratings ................................................................................... 657 table 23.2 dc characteristics .................................................................................................. 6 59 table 23.3 permitted output current values............................................................................ 662 table 23.4 operating frequency range ................................................................................... 663 table 23.5 clock timing......................................................................................................... . 664 table 23.6 control signal timing ............................................................................................ 670 table 23.7 bus timing ........................................................................................................... .. 673
rev. 5.00, 09/03, page xliii of xliv table 23.8 peripheral module signal timing........................................................................... 706 table 23.9 udi-related pin timing......................................................................................... 709 table 23.10 a/d converter characteristics................................................................................ 713 table 23.11 d/a converter characteristics................................................................................ 713 table a.1 pin states during resets, power-down states, and bus-released state................. 715 table a.2 pin specifications ................................................................................................... 7 19 table a.3 pin states (ordinary memory/little endian).......................................................... 725 table a.4 pin states (ordinary memory/big endian)............................................................. 727 table a.5 pin states (burst rom/little endian) .................................................................... 729 table a.6 pin states (burst rom/big endian) ....................................................................... 731 table a.7 pin states (synchronous dram/little endian) ..................................................... 733 table a.8 pin states (synchronous dram/big endian) ........................................................ 734 table a.9 pin states (pcmcia/little endian)........................................................................ 735 table a.10 pin states (pcmcia/big endian) .......................................................................... 737 table b.1 memory-mapped control registers ....................................................................... 739 table b.2 register bits ......................................................................................................... .. 745 table c.1 sh7709s models.................................................................................................... 757
rev. 5.00, 09/03, page xliv of xliv
rev. 5.00, 09/03, page 1 of 760 section 1 overview and pin functions 1.1 sh7709s features this lsi is a single-chip risc microprocessor that integrates a renesas technology-original risc-type superh tm architecture cpu as its core that has an on-chip multiplier, cache memory, and a memory management unit (mmu) as well as peripheral functions required for system configuration such as a timer, a realtime clock, an interrupt controller, and a serial communication interface. this lsi includes data protection, virtual memory, and other functions provided by incorporating an mmu into a superh series microprocessor (sh-1 or sh-2). high-speed data transfers can be performed by an on-chip direct memory access controller (dmac) and an external memory access support function enables direct connection to different types of memory. the sh7709s microprocessor also supports an infrared communication function, an a/d converter, and a d/a converter. a powerful built-in power management function keeps power consumption low, even during high- speed operation. this lsi can run at six times the frequency of the system bus operating speed, making it optimum for electrical devices such as pdas that require both high speed and low power. the features of this lsi is listed in table 1.1. the specifications are shown in table 1.2. note: superh is a trademark of renesas technology, corp.
rev. 5.00, 09/03, page 2 of 760 table 1.1 sh7709s features item features cpu ? original renesas technology superh architecture ? object code level with sh-1, sh-2, and sh-3 series ? 32-bit internal data bus ? general-register files ? sixteen 32-bit general registers (eight 32-bit shadow registers) ? eight 32-bit control registers ? four 32-bit system registers ? risc-type instruction set ? instruction length: 16-bit fixed length for improved code efficiency ? load-store architecture ? delayed branch instructions ? instruction set based on c language ? instruction execution time: one instruction/cycle for basic instructions ? logical address space: 4 gbytes ? space identifier asid: 8 bits, 256 logical address space ? five-stage pipeline clock pulse generator (cpg) ? clock mode: an input clock can be selected from the external input (extal or ckio) or crystal oscillator. ? three types of clocks generated: ? cpu clock: 1?24 times the input clock, maximum 200 mhz ? bus clock: 1?4 times the input clock, maximum 66.67 mhz ? peripheral clock: 1/4?4 times the input clock, maximum 33.34 mhz ? power-down modes: ? sleep mode ? standby mode ? module standby mode ? one-channel watchdog timer memory management unit (mmu) ? 4 gbytes of address space, 256 address spaces (asid 8 bits) ? page unit sharing ? supports multiple page sizes: 1, 4 kbytes ? 128-entry, 4-way set associative tlb ? supports software selection of replacement method and random-replacement algorithms
rev. 5.00, 09/03, page 3 of 760 item features cache memory ? 16-kbyte cache, mixed instruction/data ? 256 entries, 4-way set associative, 16-byte block length ? write-back, write-through, lru replacement algorithm ? 1-stage write-back buffer ? maximum 2 ways of the cache can be locked interrupt controller (intc) ? 23 external interrupt pins (nmi, irq5?irq0, pint15 to pint0) ? on-chip peripheral interrupts: set priority levels for each module user break controller (ubc) ? 2 break channels ? addresses, data values, type of access, and data size can all be set as break conditions ? supports a sequential break function bus state controller (bsc) ? physical address space divided into six areas (area 0, areas 2 to 6), each a maximum of 64 mbytes, with the following features settable for each area: ? bus size (8, 16, or 32 bits) ? number of wait cycles (also supports a hardware wait function) ? setting the type of space enables direct connection to sram, synchronous dram, and burst rom ? supports pcmcia interface (2 channels) ? outputs chip select signal (cs0, cs2?cs6) for corresponding area ? synchronous dram refresh function ? programmable refresh interval ? support self-refresh mode ? synchronous dram burst access function ? usable as either big or little endian machine user-debugging interface (udi) ? e10a emulator support ? jtag-compliant ? realtime branch address trace ? 1-kb on-chip ram for fast emulation program execution timer (tmu) ? 3-channel auto-reload-type 32-bit timer ? input capture function ? 6 types of counter input clocks can be selected ? maximum resolution: 2 mhz realtime clock (rtc) ? built-in clock, calendar functions, and alarm functions ? on-chip 32-khz crystal oscillator circuit with a maximum resolution (interrupt cycle) of 1/256 second
rev. 5.00, 09/03, page 4 of 760 item features serial communi- cation interface 0 (sci0/sci) ? asynchronous mode or clock synchronous mode can be selected ? full-duplex communication ? supports smart card interface serial communi- cation interface 1 (sci1/irda) ? 16-byte fifo for transmission/reception ? dma can be transferred ? irda: interface based on 1.0 serial communi- cation interface 2 (sci2/scif) ? 16-byte fifo for transmission/reception ? dma can be transferred ? hardware flow control direct memory access controller (dmac) ? 4 channels ? burst mode and cycle-steal mode ? data transfer size: 8-/16-/32-bit and 16-byte i/o port ? twelve 8-bit ports a/d converter (adc) ? 10 bits 4 lsb, 8 channels ? conversion time: 16 s ? input range: 0?avcc (max. 3.6 v) d/a converter (dac) ? 8 bits 4 lsb, 2 channels ? conversion time: 10 s ? output range: 0?avcc (max. 3.6 v) product lineup power supply voltage abbr. i/o internal operating frequency model name package sh7709s 3.30.3 v 2.00.15 v * 200 mhz hd6417709shf200b 208-pin plastic hqfp (fp-208e) 1.90.15 v 167 mhz hd6417709sf167b 208-pin plastic lqfp (fp-208c) HD6417709SBP167B 240-pin csp (bp-240a) 1.8+0.25 v 1.8?0.15 v 133 mhz hd6417709sf133b 208-pin plastic lqfp (fp-208c) hd6417709sbp133b 240-pin csp (bp-240a) 1.7+0.25 v 1.7?0.15 v 100 mhz hd6417709sf100b 208-pin plastic lqfp (fp-208c) hd6417709sbp100b 240-pin csp (bp-240a) note: * 2.0 (+0.15, ?0.1) v when an irl or irls interrupt is used.
rev. 5.00, 09/03, page 5 of 760 table 1.2 characteristics item characteristics power supply voltage ? i/o: 3.3 0.3 v internal: 2.0 0.15 v (200 mhz model) * , 1.90.15 v (167 mhz model), 1.8 (+0.25, ?0.15) v (133 mhz model), 1.7(+0.25, ?0.15) v (100 mhz model) operating frequency ? internal frequency: maximum 200 mhz(200 mhz model), 167 mhz (167 mhz model) 133.34 mhz (133 mhz model), 100 mhz (100 mhz model); external frequency: maximum 66.67 mhz process ? 0.25-m cmos/5-layer metal note: * 2.0 (+0.15, ?0.1) v when an irl or irls interrupt is used.
rev. 5.00, 09/03, page 6 of 760 1.2 block diagram mmu tlb sh-3 cpu ubc sci tmu rtc irda scif adc dac aud bridge dmac cmt i/o port external bus interface bsc ccn cache udi intc cpg/wdt peripheral bus 1 peripheral bus 2 l bus i bus 1 i bus 2 legend: adc: aud: bsc: cache: ccn: cmt: cpg/wdt: cpu: dac: dmac: udi: a/d converter advanced user debugger bus state controller cache memory cache memory controller compare match timer clock pulse generator/watchdog timer central processing unit d/a converter direct memory access controller user debugging interface intc: irda: mmu: rtc: sci: scif: tlb: tmu: ubc: interrupt controller serial communicatiion interface (with irda) memory management unit realtime clock serial communication interface (with smart card interface) serial communication interface (with fifo) address translation buffer timer unit user break controller figure 1.1 block diagram
rev. 5.00, 09/03, page 7 of 760 1.3 pin description 1.3.1 pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 md1 md2 v cc -rtc xtal2 extal2 v ss -rtc nmi irq0/ irl0 /pth[0] irq1/ irl1 /pth[1] irq2/ irl2 /pth[2] irq3/ irl3 /pth[3] irq4/pth[4] d31/ptb[7] d30/ptb[6] d29/ptb[5] d28/ptb[4] d27/ptb[3] d26/ptb[2] v ss q d25/ptb[1] v cc q d24/ptb[0] d23/pta[7] d22/pta[6] d21/pta[5] d20/pta[4] v ss d19/pta[3] v cc d18/pta[2] d17/pta[1] d16/pta[0] v ss q d15 v cc q d14 d13 d12 d11 d10 d9 d8 d7 d6 v ss q d5 v cc q d4 d3 d2 d1 d0 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 extal xtal v cc v ss v ss audck/pth[6] v cc -pll2 cap2 v ss -pll2 v ss -pll1 cap1 v cc -pll1 md0 irls0 /ptf[0]/pint[8] irls1 /ptf[1]/pint[9] irls2 /ptf[2]/pint[10] irls3 /ptf[3]/pint[11] tck/ptf[4]/pint[12] tdi/ptf[5]/pint[13] tms/ptf[6]/pint[14] trst /ptf[7]/pint[15] audata[0]/ptg[0] v cc audata[1]/ptg[1] v ss audata[2]/ptg[2] audata[3]/ptg[3] ptg[4]/ckio2 asebrkak /ptg[5] asemd0 /ptg[6] iois16 /ptg[7] adtrg /pth[5] resetm wait breq back tdo/pte[0] pte[1] ras3u /pte[2] pte[3] pte[6] dack1/ptd[7] dack0/ptd[5] ptj[5] ptj[4] v cc q casu /ptj[3] v ss q casl /ptj[2] ptj[1] ras3l /ptj[0] cke/ptk[5] 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 status0/ptj[6] status1/ptj[7] tclk/pth[7] i rqout v ss q ckio v cc q txd0/scpt[0] sck0/scpt[1] txd1/scpt[2] sck1/scpt[3] txd2/scpt[4] sck2/scpt[5] rts2 /scpt[6] rxd0/scpt[0] rxd1/scpt[2] v ss rxd2/scpt[4] v cc cts2 /irq5/scpt[7] mcs[7] /ptc[7]/pint[7] mcs[6] /ptc[6]/pint[6] mcs[5] /ptc[5]/pint[5] mcs[4] /ptc[4]/pint[4] v ss q wakeup /ptd[3] v cc q resetout /ptd[2] mcs[3] /ptc[3]/pint[3] mcs[2] /ptc[2]/pint[2] mcs[1] /ptc[1]/pint[1] mcs[0] /ptc[0]/pint[0] drak0/ptd[1] drak1/ptd[0] dreq0 /ptd[4] dreq1 /ptd[6] resetp ca md3 md4 md5 av ss an[0]/ptl[0] an[1]/ptl[1] an[2]/ptl[2] an[3]/ptl[3] an[4]/ptl[4] an[5]/ptl[5] av cc an[6]/da[1]/ptl[6] an[7]/da[0]/ptl[7] av ss 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 ce2b /pte[5] ce2a /pte[4] cs6 / ce1b cs5/ce1a /ptk[3] cs4 /ptk[2] cs3 /ptk[1] cs2 /ptk[0] v cc q cs0 / mcs0 v ss q audsync /pte[7] rd/ wr we3 /dqmuu/iciowr/ptk[7] we2 /dqmul/iciord/ptk[6] we1 /domlu/we we0 /dqmll rd bs /ptk[4] a25 v cc q a24 v ss q a23 v cc a22 v ss a21 a20 a19 a18 a17 a16 a15 v cc q a14 v ss q a13 a12 a11 a10 a9 a8 a7 a6 a5 v cc q a4 v ss q a3 a2 a1 a0 sh7709s fp-208c fp-208e (top view) index mark figure 1.2 pin assignment (fp-208c, fp-208e)
rev. 5.00, 09/03, page 8 of 760 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 abcdefghjk lmnprtuvw abcdefghjk lmnprtuvw note: the pin area enclosed in broken lines is an inner view. sh7709s bp-240a (top view) figure 1.3 pin assignment (bp-240a)
rev. 5.00, 09/03, page 9 of 760 1.3.2 pin function table 1.3 sh7709s pin function number of pins fp-208c fp-208e bp-240a pin name i/o description 1 d2 md1 i clock mode setting 2 c2 md2 i clock mode setting 3 e2 vcc-rtc * 1 ? rtc power supply ( * 3 ) 4 d1 xtal2 o on-chip rtc crystal oscillator pin 5 d3 extal2 i on-chip rtc crystal oscillator pin * 6 6 e1 vss-rtc * 1 ? rtc power supply (0 v) 7 c3 nmi i nonmaskable interrupt request 8e3irq0/ irl0 /pth[0] i external interrupt request/input port h 9e4irq1/ irl1 /pth[1] i external interrupt request/input port h 10 f1 irq2/ irl2 /pth[2] i external interrupt request/input port h 11 f2 irq3/ irl3 /pth[3] i external interrupt request/input port h 12 f3 irq4/pth[4] i external interrupt request/input port h 13 f4 d31/ptb[7] i/o data bus / input/output port b 14 g1 d30/ptb[6] i/o data bus / input/output port b 15 g2 d29/ptb[5] i/o data bus / input/output port b 16 g3 d28/ptb[4] i/o data bus / input/output port b 17 g4 d27/ptb[3] i/o data bus / input/output port b 18 h1 d26/ptb[2] i/o data bus / input/output port b 19 h2 vssq ? input/output power supply (0 v) 20 h3 d25/ptb[1] i/o data bus / input/output port b 21 h4 vccq ? input/output power supply (3.3 v) 22 j1 d24/ptb[0] i/o data bus / input/output port b 23 j2 d23/pta[7] i/o data bus / input/output port a 24 j4 d22/pta[6] i/o data bus / input/output port a 25 j3 d21/pta[5] i/o data bus / input/output port a 26 k2 d20/pta[4] i/o data bus / input/output port a
rev. 5.00, 09/03, page 10 of 760 number of pins fp-208c fp-208e bp-240a pin name i/o description 27 k3 vss ? power supply (0 v) ? k4 vss ? power supply (0 v) 28 k1 d19/pta[3] i/o data bus / input/output port a 29 l3 vcc ? power supply (1.9 v/1.8 v * 3 ) ? l4 vcc ? power supply ( * 3 ) 30 l2 d18/pta[2] i/o data bus / input/output port a 31 l1 d17/pta[1] i/o data bus / input/output port a 32 m4 d16/pta[0] i/o data bus / input/output port a 33 m3 vssq ? input/output power supply (0 v) 34 m2 d15 i/o data bus 35 m1 vccq ? input/output power supply (3.3 v) 36 n4 d14 i/o data bus 37 n3 d13 i/o data bus 38 n2 d12 i/o data bus 39 n1 d11 i/o data bus 40 p4 d10 i/o data bus 41 p3 d9 i/o data bus 42 p2 d8 i/o data bus 43 p1 d7 i/o data bus 44 r4 d6 i/o data bus 45 r3 vssq ? input/output power supply (0 v) 46 t4 d5 i/o data bus 47 r1 vccq ? input/output power supply (3.3 v) 48 t3 d4 i/o data bus 49 t1 d3 i/o data bus 50 r2 d2 i/o data bus 51 u2 d1 i/o data bus 52 t2 d0 i/o data bus 53 v4 a0 o address bus 54 v3 a1 o address bus 55 v5 a2 o address bus 56 w4 a3 o address bus
rev. 5.00, 09/03, page 11 of 760 number of pins fp-208c fp-208e bp-240a pin name i/o description 57 u4 vssq ? input/output power supply (0 v) 58 w5 a4 o address bus 59 u3 vccq ? input/output power supply (3.3 v) 60 u5 a5 o address bus 61 t5 a6 o address bus 62 w6 a7 o address bus 63 v6 a8 o address bus 64 u6 a9 o address bus 65 t6 a10 o address bus 66 w7 a11 o address bus 67 v7 a12 o address bus 68 u7 a13 o address bus 69 t7 vssq ? input/output power supply (0 v) 70 w8 a14 o address bus 71 v8 vccq ? input/output power supply (3.3 v) 72 u8 a15 o address bus 73 t8 a16 o address bus 74 w9 a17 o address bus 75 v9 a18 o address bus 76 t9 a19 o address bus 77 u9 a20 o address bus 78 v10 a21 o address bus 79 u10 vss ? power supply (0 v) ? t10 vss o power supply (0 v) 80 w10 a22 o address bus 81 u11 vcc ? power supply ( * 3 ) ? t11 vcc ? power supply ( * 3 ) 82 v11 a23 o address bus 83 w11 vssq ? input/output power supply (0 v) 84 t12 a24 o address bus 85 u12 vccq ? input/output power supply (3.3 v) 86 v12 a25 o address bus
rev. 5.00, 09/03, page 12 of 760 number of pins fp-208c fp-208e bp-240a pin name i/o description 87 w12 bs /ptk[4] o / i/o bus cycle start signal / input/output port k 88 t13 rd o read strobe 89 u13 we0 /dqmll o d7?d0 select signal / dqm (sdram) 90 v13 we1 /dqmlu/ we o d15?d8 select signal / dqm (sdram) 91 w13 we2 /dqmul/ iciord / ptk[6] o / i/o d23?d16 select signal / dqm (sdram) / pcmcia i/o read / input/output port k 92 t14 we3 /dqmuu/ iciowr / ptk[7] o / i/o d31?d24 select signal / dqm (sdram) / pcmcia i/o write / input/output port k 93 u14 rd/ wr o read/write 94 v14 audsync /pte[7] o / i/o aud synchronous / input/output port e 95 w14 vssq ? input/output power supply (0 v) 96 t15 cs0 / mcs[0] o chip select 0/mask rom chip select 0 97 u15 vccq ? input/output power supply (3.3 v) 98 t16 cs2 /ptk[0] o / i/o chip select 2 / input/output port k 99 w15 cs3 /ptk[1] o / i/o chip select 3 / input/output port k 100 u16 cs4 /ptk[2] o / i/o chip select 4 / input/output port k 101 w16 cs5 / ce1a /ptk[3] o / i/o chip select 5/ce1 (area 5 pcmcia) / input/output port k 102 v15 cs6 / ce1b o chip select 6/ce1 (area 6 pcmcia) 103 v17 ce2a /pte[4] o / i/o ce2 (area 5 pcmcia) / input/output port e 104 v16 ce2b /pte[5] o / i/o ce2 (area 6 pcmcia) / input/output port e 105 t18 cke/ptk[5] o / i/o ck enable (sdram) / input/output port k
rev. 5.00, 09/03, page 13 of 760 number of pins fp-208c fp-208e bp-240a pin name i/o description 106 u18 ras3l /ptj[0] o / i/o lower 32 m / 64 mbytes address (sdram) ras / input/output port j 107 u19 ptj[1] o / i/o input/output port j * 5 108 r18 casl /ptj[2] o / i/o lower 32 m / 64 mbytes address (sdram) cas / input/output port j 109 t19 vssq ? input/output power supply (0 v) 110 t17 casu /ptj[3] o / i/o lower 32 mbytes address (sdram) cas / input/output port j 111 r19 vccq ? input/output power supply (3.3 v) 112 u17 ptj[4] i/o input/output port j 113 r17 ptj[5] i/o input/output port j 114 r16 dack0/ptd[5] o / i/o dma acknowledge 0 / input/output port d 115 p19 dack1/ptd[7] o / i/o dma acknowledge 1 / input/output port d 116 p18 pte[6] i/o input/output port e 117 p17 pte[3] i/o input/output port e 118 p16 ras3u /pte[2] o / i/o upper 32 mbytes address (sdram) ras / input/output port e 119 n19 pte[1] i/o input/output port e 120 n18 tdo/pte[0] o / i/o test data output / input/output port e 121 n17 back o bus acknowledge 122 n16 breq i bus request 123 m19 wait i hardware wait request 124 m18 resetm i manual reset request 125 m17 adtrg /pth[5] i analog trigger / input port h 126 m16 iois16 /ptg[7] i iois16 (pcmcia) / input port g 127 l19 asemd0 /ptg[6] i ase mode * 4 / input port g 128 l18 asebrkak /ptg[5] o/i ase break acknowledge / input port g 129 l16 ptg[4]/ck102 i input port g / clock output
rev. 5.00, 09/03, page 14 of 760 number of pins fp-208c fp-208e bp-240a pin name i/o description 130 l17 audata[3]/ptg[3] i/o / i aud data / input port g 131 k18 audata[2]/ptg[2] i/o/i aud data / input port g 132 k17 vss ? power supply (0 v) ? k16 vss ? power supply (0 v) 133 k19 audata[1]/ptg[1] i/o / i aud data / input port g 134 j17 vcc ? power supply ( * 3 ) ? j16 vcc ? power supply ( * 3 ) 135 j18 audata[0]/ptg[0] i/o / i aud data / input port g 136 j19 trst /ptf[7]/pint[15] i test reset / input port f / port interrupt 137 h16 tms/ptf[6]/pint[14] i test mode switch / input port f / port interrupt 138 h17 tdi/ptf[5]/pint[13] i test data input / input port f / port interrupt 139 h18 tck/ptf[4]/pnt[12] i test clock / input port f / port interrupt 140 h19 irls3 /ptf[3]/ pint[11] i external interrupt request / input port f / port interrupt 141 g16 irls2 /ptf[2]/ pint[10] i external interrupt request / input port f / port interrupt 142 g17 irls1 /ptf[1]/pint[9] i external interrupt request / input port f / port interrupt 143 g18 irls0 /ptf[0]/pint[8] i external interrupt request / input port f / port interrupt 144 g19 md0 i clock mode setting 145 f16 vcc-pll1 * 2 ? pll1 power supply ( * 3 ) 146 f17 cap1 ? pll1 external capacitance pin 147 f18 vss-pll1 * 2 ? pll1 power supply (0 v) 148 f19 vss-pll2 * 2 ? pll2 power supply (0 v) 149 e16 cap2 ? pll2 external capacitance pin 150 e17 vcc-pll2 * 2 ? pll2 power supply ( * 3 ) 151 d16 audck/pth[6] i aud clock / input port h 152 e19 vss ? power supply (0 v) 153 d17 vss ? power supply (0 v)
rev. 5.00, 09/03, page 15 of 760 number of pins fp-208c fp-208e bp-240a pin name i/o description ? d19 vss ? power supply (0 v) 154 e18 vcc ? power supply ( * 3 ) ? c19 vcc ? power supply ( * 3 ) 155 c18 xtal o clock oscillator pin 156 d18 extal i external clock / crystal oscillator pin 157 b16 status0/ptj[6] o / i/o processor status / input/output port j 158 b17 status1/ptj[7] o / i/o processor status / input/output port j 159 b15 tclk/pth[7] i/o tmu or rtc clock input/output / input/output port h 160 a16 irqout o interrupt request notification 161 c16 vssq ? input/output power supply (0 v) 162 a15 ckio i/o system clock input/output 163 c17 vccq ? power supply (3.3 v) 164 c15 txd0/scpt[0] o transmit data 0 / sci output port 165 d15 sck0/scpt[1] i/o serial clock 0 / sci input/output port 166 a14 txd1/scpt[2] o transmit data 1 / sci output port 167 b14 sck1/scpt[3] i/o serial clock 1 / sci input/output port 168 c14 txd2/scpt[4] o transmit data 2 / sci output port 169 d14 sck2/scpt[5] i/o serial clock 2 / sci input/output port 170 a13 rts2 /scpt[6] o / i/o transmit request 2 / sci input/output port 171 b13 rxd0/scpt[0] i transmit data 0 / sci output port 172 c13 rxd1/scpt[2] i transmit data 1 / sci output port 173 d13 vss ? power supply (0 v) ? a12 vss ? power supply (0 v) 174 b12 rxd2/scpt[4] i transmit data 2 / sci output port 175 c12 vcc ? power supply ( * 3 ) ? d12 vcc ? power supply ( * 3 )
rev. 5.00, 09/03, page 16 of 760 number of pins fp-208c fp-208e bp-240a pin name i/o description 176 a11 cts2 /irq5/scpt[7] i transmit clear 2 / external interrupt request / sci input port 177 b11 mcs[7] /ptc[7]/pint[7] o / i/o / i mask rom chip select / input/output port c / port interrupt 178 d11 mcs[6] /ptc[6]/pint[6] o / i/o / i mask rom chip select / input/output port c / port interrupt 179 c11 mcs[5] /ptc[5]/pint[5] o / i/o / i mask rom chip select / input/output port c / port interrupt 180 b10 mcs[4] /ptc[4]/pint[4] o / i/o / i mask rom chip select / input/output port c / port interrupt 181 c10 vssq ? input/output power supply (0 v) 182 d10 wakeup /ptd[3] o / i/o standby mode interrupt request notification / input/output port d 183 a10 vccq ? input/output power supply (3.3 v) 184 c9 resetout /ptd[2] o / i/o reset output / input/output port d 185 d9 mcs[3] /ptc[3]/pint[3] o / i/o / i mask rom chip select / input/output port c / port interrupt 186 b9 mcs[2] /ptc[2]/pint[2] o / i/o / i mask rom chip select / input/output port c / port interrupt 187 a9 mcs[1] /ptc[1]/pint[1] o / i/o / i mask rom chip select / input/output port c / port interrupt 188 d8 mcs[0] /ptc[0]/pint[0] o / i/o / i mask rom chip select / input/output port c / port interrupt 189 c8 drak0/ptd[1] o / i/o dma request acknowledge / input/output port d 190 b8 drak1/ptd[0] o / i/o dma request acknowledge / input/output port d 191 a8 dreq0 /ptd[4] i dma request / input port d 192 d7 dreq1 /ptd[6] i dma request / input port d 193 c7 resetp i power-on reset request 194 b7 ca i chip activate (hardware standby request signal) 195 a7 md3 i area 0 bus width setting 196 d6 md4 i area 0 bus width setting 197 c6 md5 i endian setting
rev. 5.00, 09/03, page 17 of 760 number of pins fp-208c fp-208e bp-240a pin name i/o description 198 b6 avss ? analog power supply (0 v) 199 a6 an[0]/ptl[0] i a/d converter input / input port l 200 d5 an[1]/ptl[1] i a/d converter input / input port l 201 c5 an[2]/ptl[2] i a/d converter input / input port l 202 d4 an[3]/ptl[3] i a/d converter input / input port l 203 a5 an[4]/ptl[4] i a/d converter input / input port l 204 c4 an[5]/ptl[5] i a/d converter input / input port l 205 a4 avcc ? analog power supply (3.3 v) 206 b5 an[6]/da[1]/ptl[6] i a/d converter input / d/a converter output / input port l 207 b3 an[7]/da[0]/ptl[7] i a/d converter input / d/a converter output / input port l 208 b4 avss ? analog power supply (0 v) notes: 1. must be connected to the power supply even when the rtc is not used. 2. except in hardware standby mode, all of the power supply pins must be connected to the system power supply. (supply power constantly.) in hardware standby mode, power must be supplied at least to v cc ?rtc and v ss ?rtc. if power is not being supplied to any of the power supply pins other than v cc ?rtc and v ss ?rtc, hold the ca pin low. 3. 2.0 v for the 200 mhz model, 1.9 v for the 167 mhz model, 1.8 v for the 133 mhz model, 1.7 v for the 100 mhz model. 4. when this lsi is used on the user system alone, without an emulator and the udi, hold this pin at high level. when this pin is low or open, resetp may be masked (see section 22, user debugging interface (udi)). 5. b2, b1, c1, u1, v1, w1, v2, w2, w3, w17, w18, w19, v18, v19, b19, a19, b18, a18, a17, a3, a2, and a1 are nc pins. do not connect anything to these pins. 6. if extal2 is not used, pull this pin up to the vcc-rtc level.
rev. 5.00, 09/03, page 18 of 760
rev. 5.00, 09/03, page 19 of 760 section 2 cpu 2.1 register configuration 2.1.1 privileged mode and banks processor modes: there are two processor modes: user mode and privileged mode. the sh7709s normally operates in user mode, and enters privileged mode when an exception occurs or an interrupt is accepted. there are three kinds of registers?general registers, system registers, and control registers?and the registers that can be accessed differ in the two processor modes. general registers: there are 16 general registers, designated r0 to r15. general registers r0 to r7 are banked registers which are switched by a processor mode change. in privileged mode, the register bank bit (rb) in the status register (sr) defines which banked register set is accessed as general registers, and which set is accessed only through the load control register (ldc) and store control register (stc) instructions. when the rb bit is 1, the 16 registers comprising bank1 general registers r0_bank1? r7_bank1 and non-banked general registers r8?r15 function as the general register set, with the 8 registers comprising bank0 general registers r0_bank0?r7_bank0 accessed only by the ldc/stc instructions. when the rb bit is 0, bank0 general registers r0_bank0?r7_bank0 and nonbanked general registers r8?r15 function as the general register set, with bank1 general registers r0_bank1? r7_bank1 accessed only by the ldc/stc instructions. in user mode, the 16 registers comprising bank 0 general registers r0_bank0?r7_bank0 and non-banked registers r8?r15 can be accessed as general registers r0?r15, and bank 1 general registers r0_bank1? r7_bank1 cannot be accessed. control registers: control registers comprise the global base register (gbr) and status register (sr) which can be accessed in both processor modes, and the saved status register (ssr), saved program counter (spc), and vector base register (vbr) which can only be accessed in privileged mode. some bits of the status register (such as the rb bit) can only be accessed in privileged mode. system registers: system registers comprise the multiply and accumulate registers (macl/mach), the procedure register (pr), and the program counter (pc). access to these registers does not depend on the processor mode. the register configuration in each mode is shown in figures 2.1 and 2.2. switching between user mode and privileged mode is controlled by the processor mode bit (md) in the status register.
rev. 5.00, 09/03, page 20 of 760 31 0 r0 _ bank0 * 1 * 2 r1 _ bank0 * 2 r2 _ bank0 * 2 r3 _ bank0 * 2 r4 _ bank0 * 2 r5 _ bank0 * 2 r6 _ bank0 * 2 r7 _ bank0 * 2 r8 r9 r10 r11 r12 r13 r14 r15 sr gbr mach macl pr pc user mode register configuration notes: 1. 2. r0 functions as an index register in the indexed register-indirect addressing mode and indexed gbr-indirect addressing mode. banked register. figure 2.1 user mode register configuration
rev. 5.00, 09/03, page 21 of 760 r0_bank1 * 1 * 2 r1_bank1 * 2 r2_bank1 * 2 r3_bank1 * 2 r4_bank1 * 2 r5_bank1 * 2 r6_bank1 * 2 r7_bank1 * 2 r8 r9 r10 r11 r12 r13 r14 r15 sr ssr pc spc gbr mach macl pr vbr 31 0 a. privileged mode register configuration (rb = 1) r0_bank0 * 1 * 3 r1_bank0 * 3 r2_bank0 * 3 r3_bank0 * 3 r4_bank0 * 3 r5_bank0 * 3 r6_bank0 * 3 r7_bank0 * 3 r0_bank0 * 1 * 3 r1_bank0 * 3 r2_bank0 * 3 r3_bank0 * 3 r4_bank0 * 3 r5_bank0 * 3 r6_bank0 * 3 r7_bank0 * 3 r8 r9 r10 r11 r12 r13 r14 r15 sr ssr pc spc gbr mach macl pr vbr 31 0 b. privileged mode register configuration (rb = 0) r0_bank1 * 1 * 2 r1_bank1 * 2 r2_bank1 * 2 r3_bank1 * 2 r4_bank1 * 2 r5_bank1 * 2 r6_bank1 * 2 r7_bank1 * 2 notes: 1. 2. 3. r0 functions as an index register in the indexed register-indirect addressing mode and indexed gbr- indirect addressing mode. banked register when the rb bit of the sr register is 1, the register can be accessed for general use. when the rb bit is 0, it can only be accessed with the ldc/stc instruction. banked register when the rb bit of the sr register is 0, the register can be accessed for general use. when the rb bit is 1, it can only be accessed with the ldc/stc instruction. figure 2.2 privileged mode register configuration
rev. 5.00, 09/03, page 22 of 760 register values after a reset are shown in table 2.1. table 2.1 initial register values type registers initial value * general registers r0 to r15 undefined control registers sr md bit = 1, rb bit = 1, bl bit = 1, i3?i0 = 1111 (h'f), reserved bits = 0, others undefined gbr, ssr, spc undefined vbr h'00000000 system registers mach, macl, pr undefined pc h'a0000000 note: * register values are initialized at power-on reset or manual reset. 2.1.2 general registers there are 16 general registers, designated r0 to r15 (figure 2.3). general registers r0 to r7 are banked registers, with a different r0?r7 register bank (r0_bank0?r7_bank0 or r0_bank1?r7_bank1) being accessed according to the processor mode. for details, see figures 2.1 and 2.2. the general register configuration is shown in figure 2.3. 31 0 r0 * 1 * 2 general registers notes: r0 functions as an index register in the indexed register-indirect addressing mode and indexed gbr-indirect addressing mode. in some instructions, only r0 can be used as the source register or destination register. r0 r7 are banked registers. in privileged mode, sr.rb specifies which banked registers are accessed as general registers (r0_bank0 ? r7_bank0 or r0_bank1 ? r7_bank1). 1. 2. r1 * 2 r2 * 2 r3 * 2 r4 * 2 r5 * 2 r6 * 2 r7 * 2 r8 r9 r10 r11 r12 r13 r14 r15 figure 2.3 general registers
rev. 5.00, 09/03, page 23 of 760 2.1.3 system registers system registers can be accessed by the lds and sts instructions. when an exception occurs, the contents of the program counter (pc) are saved in the saved program counter (spc). the spc contents are restored to the pc by the rte instruction used at the end of the exception handling. there are four system registers, as follows. ? multiply and accumulate high register (mach) ? multiply and accumulate low register (macl) ? procedure register (pr) ? program counter (pc) the system register configuration is shown in figure 2.4. 31 0 31 0 31 0 system registers multiply and accumulate high and low registers (mach/l) store the results of multiply-and-accumulate operations. procedure register (pr) stores the return address for exiting a subroutine procedure. program counter (pc) indicates the address four addresses (two instructions) ahead of the currently executing instruction. initialized to ha0000000 by a reset. pr pc mach macl figure 2.4 system registers 2.1.4 control registers control registers can be accessed in privileged mode using the ldc and stc instructions. the gbr register can also be accessed in user mode. there are five control registers, as follows: ? status register (sr) ? saved status register (ssr) ? saved program counter (spc) ? global base register (gbr) ? vector base register (vbr)
rev. 5.00, 09/03, page 24 of 760 ssr saved status register (ssr) stores current sr value at time of exception to indicate processor status in return to instruction stream from exception handler. saved program counter (spc) stores current pc value at time of exception to indicate return address at completion of exception handling. global base register (gbr) stores base address of gbr-indirect addressing mode. the gbr-indirect addressing mode is used for on-chip supporting module register area data transfers and logic operations. the gbr register can also be accessed in user mode. its contents are undefined after a reset. vector base register (vbr) stores base address of exception handling vector area. initialized to h0000000 by a reset. 31 0 spc 31 0 gbr 31 0 vbr 31 0 md bl m q 0 ?????????????????????? 0 i3 i2 i1 i0 0 0 s t status register (sr) 31 29 28 27 10 9 8 7 0 1 3 0rb 30 md: rb: bl: cl: m and q bits: i3 ? i0 bits: s bit: t bit: 0 bits: processor operation mode bit: indicates the processor operation mode as follows: md =1: privileged mode; md = 0: user mode md is set to 1 on generation of an exception or interrupt , and is initialized to 1 by a reset. register bank bit: determines the bank of general registers r0 r7 used in processing mode. rb = 1: r0_bank1 ? r7_bank1 and r8 ? r15 are general registers, and r0_bank0 ? r7_bank0 can be accessed by ldc/stc instructions. rb = 0: r0_bank0 ? r7_bank0 and r8 ? r15 are general registers, and r0_bank1 ? r7_bank1 can be accessed by ldc/stc instructions. rb is set to 1 on generation of an exception or interrupt , and is initialized to 1 by a reset. block bit bl = 1: exceptions and interrupts are suppressed. see section 4, exception handling, for details. bl = 0: exceptions and interrupts are accepted. bl is set to 1 on generation of an exception or interrupt , and is initialized to 1 by a reset. cache lock bit when set to 1, the cache lock function can be used. used by the div0s/u and div1 instructions. interrupt mask bits: 4-bit field indicating the interrupt request mask level. i3 ? i0 do not change to the interrupt acceptance level when an interrupt is generated. initialized to b1111 by a reset. used by the mac instruction. used by the movt, cmp/cond, tas, tst, bt, bf, sett, clrt, and dt instructions to indicate true (1) or false (0). used by the addv/c, subv/c, div0u/s, div1, negc, shar/l, shlr/l, rotr/l, and rotcr/l instructions to indicate a carry, borrow, overflow, or underflow. these bits always read 0, and the write value should always be 0. note: the m, q, s, and t bits can be set or cleared by special instructions in user mode. their values are undefined after a reset. all other bits can be read or written in privileged mode. 0 0 11 12 13 cl figure 2.5 register set overview, control registers
rev. 5.00, 09/03, page 25 of 760 2.2 data formats 2.2.1 data format in registers register operands are always longwords (32 bits, figure 2.6). when a memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. longword 31 0 figure 2.6 longword 2.2.2 data format in memory memory data formats are classified into bytes, words, and longwords. memory can be accessed in 8-bit byte, 16-bit word, or 32-bit longword form. a memory operand less than 32 bits in length is sign-extended before being stored in a register. a word operand must be accessed starting from a word boundary (even address of a 2-byte unit: address 2n), and a longword operand starting from a longword boundary (even address of a 4-byte unit: address 4n). an address error will result if this rule is not observed. a byte operand can be accessed from any address. big-endian or little-endian byte order can be selected for the data format. the endian mode should be set with the md5 external pin in a power-on reset. big-endian mode is selected when the md5 pin is low, and little-endian when high. the endian mode cannot be changed dynamically. bit positions are numbered left to right from most-significant to least-significant. thus, in a 32-bit longword, the leftmost bit, bit 31, is the most significant bit and the rightmost bit, bit 0, is the least significant bit. the data format in memory is shown in figure 2.7. longword longword 31 0 15 23 7 byte0 byte1 byte2 byte3 word1 big-endian mode word0 address a + 4 address a + 8 address a + 4 address a address a address a + 1 address a + 3 31 0 15 23 7 byte3 byte2 byte1 byte0 word0 little-endian mode word1 address a + 11 address a + 10 address a + 8 address a address a + 8 address a + 9 address a + 2 figure 2.7 data format in memory
rev. 5.00, 09/03, page 26 of 760 2.3 instruction features 2.3.1 execution environment data length: the sh7709s instruction set is implemented with fixed-length 16-bit wide instructions executed in a pipelined sequence with single-cycle execution for most instructions. all operations are executed in 32-bit longword units. memory can be accessed in 8-bit byte, 16-bit word, or 32-bit longword units, with byte or word units sign-extended into 32-bit longwords. literals are sign-extended in arithmetic operations (mov, add, and cmp/eq instructions) and zero-extended in logical operations (tst, and, or, and xor instructions). load/store architecture: the sh7709s features a load-store architecture in which basic operations are executed in registers. operations requiring memory access are executed in registers following register loading, except for bit-manipulation operations such as logical and functions, which are executed directly in memory. delayed branching: unconditional branching is implemented as delayed branch operations. pipeline disruptions due to branching are minimized by the execution of the instruction following the delayed branch instruction prior to branching. conditional branch instructions are of two kinds, delayed and normal. bra trget add r1, r0 ;add is executed prior to branching to trget
rev. 5.00, 09/03, page 27 of 760 t bit: the t bit in the status register (sr) is used to indicate the result of compare operations, and is read as a true/false condition determining if a conditional branch is taken or not. to improve processing speed, the t bit logic state is modified only by specific operations. an example of how the t bit may be used in a sequence of operations is shown below. add #1, r0 ;t bit not modified by add operation cmp/eq r1, r0 ;t bit set to 1 when r0 = 0 bt trget ;branch taken to trget when t bit = 1 (r0 = 0) literals: byte-length literals are inserted directly into the instruction code as immediate data. to maintain the 16-bit fixed-length instruction code, word or longword literals are stored in a table in main memory rather than inserted directly into the instruction code. the memory table is accessed by the mov instruction using pc-relative addressing with displacement, as follows: mov.w @(disp, pc), r0 absolute addresses: as with word and longword literals, absolute addresses must also be stored in a table in main memory. the value of the absolute address is transferred to a register and the operand access is specified by indexed register-indirect addressing, with the absolute address loaded (like word and longword immediate data) during instruction execution. 16-bit and 32-bit displacements: in the same way, 16-bit and 32-bit displacements also must be stored in a table in main memory. exactly like absolute addresses, the displacement value is transferred to a register and the operand access is specified by indexed register-indirect addressing, loading the displacement (like word and longword immediate data) during instruction execution.
rev. 5.00, 09/03, page 28 of 760 2.3.2 addressing modes addressing modes and effective address calculation methods are shown in table 2.2. table 2.2 addressing modes and effective addresses addressing mode instruction format effective address calculation method calculation formula register direct rn effective address is register rn. (operand is register rn contents.) ? register indirect @rn effective address is register rn contents. rn rn rn register indirect with post-increment @rn+ effective address is register rn contents. a constant is added to rn after instruction execution: 1 for a byte operand, 2 for a word operand, 4 for a longword operand. rn rn 1/2/4 + rn + 1/2/4 rn after instruction execution byte: rn + 1 rn word: rn + 2 rn longword: rn + 4 rn register indirect with pre-decrement @?rn effective address is register rn contents, decremented by a constant beforehand: 1 for a byte operand, 2 for a word operand, 4 for a longword operand. rn 1/2/4 rn ? 1/2/4 ? rn ? 1/2/4 byte: rn ? 1 rn word: rn ? 2 rn longword: rn ? 4 rn (instruction executed with rn after calculation)
rev. 5.00, 09/03, page 29 of 760 addressing mode instruction format effective address calculation method calculation formula register indirect with displacement @(disp:4, rn) effective address is register rn contents with 4-bit displacement disp added. after disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. rn 1/2/4 + disp (zero-extended) rn + disp 1/2/4 byte: rn + disp word: rn + disp 2 longword: rn + disp 4 indexed register indirect @(r0, rn) effective address is sum of register rn and r0 contents. rn r0 rn + r0 + rn + r0 gbr indirect with displacement @(disp:8, gbr) effective address is register gbr contents with 8-bit displacement disp added. after disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. gbr 1/2/4 + disp (zero-extended) gbr + disp 1/2/4 byte: gbr + disp word: gbr + disp 2 longword: gbr + disp 4 indexed gbr indirect @(r0, gbr) effective address is sum of register gbr and r0 contents. gbr r0 gbr + r0 + gbr + r0
rev. 5.00, 09/03, page 30 of 760 addressing mode instruction format effective address calculation method calculation formula pc-relative with displacement @(disp:8, pc) effective address is register pc contents with 8-bit displacement disp added. after disp is zero-extended, it is multiplied by 2 (word), or 4 (longword), according to the operand size. with a longword operand, the lower 2 bits of pc are masked. pc hfffffffc + 2/4 x & (for longword) disp (zero-extended) pc + disp 2 or pc&hfffffffc + disp 4 word: pc + disp 2 longword: pc & h'ffff fffc + disp 4 pc-relative disp:8 effective address is register pc contents with 8-bit displacement disp added after being sign-extended and multiplied by 2. pc 2 + disp (sign-extended) pc + disp 2 pc + disp 2 disp:12 effective address is register pc contents with 12-bit displacement disp added after being sign-extended and multiplied by 2. pc 2 + disp (sign-extended) pc + disp 2 pc + disp 2
rev. 5.00, 09/03, page 31 of 760 addressing mode instruction format effective address calculation method calculation formula pc-relative rn effective address is sum of register pc and rn contents. pc r0 + pc + r0 pc + rn immediate #imm:8 8-bit immediate data imm of tst, and, or, or xor instruction is zero-extended. ? #imm:8 8-bit immediate data imm of mov, add, or cmp/eq instruction is sign-extended. ? #imm:8 8-bit immediate data imm of trapa instruction is zero-extended and multiplied by 4. ? note: for the addressing modes below that use a displacement (disp), the assembler descriptions in this manual show the value before scaling ( 1, 2, or 4) is performed according to the operand size. this is done to clarify the operation of the ic. refer to the relevant assembler notation rules for the actual assembler descriptions. @ (disp:4, rn) ; register indirect with displacement @ (disp:8, rn) ; gbr indirect with displacement @ (disp:8, pc) ; pc-relative with displacement disp:8, disp:12; pc-relative
rev. 5.00, 09/03, page 32 of 760 2.3.3 instruction formats table 2.3 explains the meaning of instruction formats and source and destination operands. the meaning of the operands depends on the operation code. the following symbols are used. xxxx: operation code mmmm: source register nnnn: destination register iiii: immediate data dddd: displacement table 2.3 instruction formats instruction format source operand destination operand instruction example 0 format xxxx xxxx xxxx xxxx 15 0 ??nop n format xxxx xxxx xxxx nnnn 15 0 ? nnnn: register direct movt rn control register or system register nnnn: register direct sts mach,rn control register or system register nnnn: register indirect with pre-decrement stc.l sr,@?rn m format xxxx mmmm xxxx xxxx 15 0 mmmm: register direct control register or system register ldc rm,sr mmmm: register indirect with post- increment control register or system register ldc.l @rm+,sr mmmm: register indirect ?jmp@rm mmmm: pc- relative using rm ?brafrm
rev. 5.00, 09/03, page 33 of 760 instruction format source operand destination operand instruction example nm format nnnn xxxx xxxx 15 0 mmmm mmmm: register direct nnnn: register direct add rm,rn mmmm: register indirect nnnn: register indirect mov.l rm,@rn mmmm: register indirect with post- increment (multiply-and- accumulate operation) nnnn: * register indirect with post- increment (multiply-and- accumulate operation) mach,macl mac.w @rm+,@rn+ mmmm: register indirect with post- increment nnnn: register direct mov.l @rm+,rn mmmm: register direct nnnn: register indirect with pre-decrement mov.l rm,@?rn mmmm: register direct nnnn: indexed register indirect mov.l rm,@(r0,rn) md format xxxx dddd 15 0 mmmm xxxx mmmmdddd: register indirect with displacement r0 (register direct) mov.b @(disp,rm),r0 nd4 format dddd nnnn xxxx 15 0 xxxx r0 (register direct) nnnndddd: register indirect with displacement mov.b r0,@(disp,rn)
rev. 5.00, 09/03, page 34 of 760 instruction format source operand destination operand instruction example nmd format nnnn xxxx dddd 15 0 mmmm mmmm: register direct nnnndddd: register indirect with displacement mov.l rm,@(disp,rn) mmmmdddd: register indirect with displacement nnnn: register direct mov.l @(disp,rm),rn d format dddd xxxx 15 0 xxxx dddd dddddddd: gbr indirect with displacement r0 (register direct) mov.l @(disp,gbr),r 0 r0 (register direct) dddddddd: gbr indirect with displacement mov.l r0,@(disp,gbr ) dddddddd: pc-relative with displacement r0 (register direct) mova @(disp,pc),r0 dddddddd: pc-relative ?bflabel d12 format dddd xxxx 15 0 dddd dddd dddddddddddd: pc-relative ?bralabel (label = disp + pc) nd8 format dddd nnnn xxxx 15 0 dddd dddddddd: pc-relative with displacement nnnn: register direct mov.l @(disp,pc),rn i format i i i i xxxx 15 0 xxxx i i i i iiiiiiii: immediate indexed gbr indirect and.b #imm, @(r0,gbr) iiiiiiii: immediate r0 (register direct) and #imm,r0 iiiiiiii: immediate ? trapa #imm ni format nnnn i i i i xxxx 15 0 i i i i iiiiiiii: immediate nnnn: register direct add #imm,rn note: * in a multiply-and-accumulate instruction, nnnn is the source register.
rev. 5.00, 09/03, page 35 of 760 2.4 instruction set 2.4.1 instruction set classified by function the sh7709s instruction set includes 68 basic instruction types, as listed in table 2.4. table 2.4 classification of instructions classification types operation code function no. of instructions data transfer 5 mov data transfer 39 mova effective address transfer movt t bit transfer swap swap of upper and lower bytes xtrct extraction of middle of linked registers arithmetic 21 add binary addition 33 operations addc binary addition with carry addv binary addition with overflow check cmp/cond comparison div1 division div0s initialization of signed division div0u initialization of unsigned division dmuls signed double-precision multiplication dmulu unsigned double-precision multiplication dt decrement and test exts sign extension extu zero extension mac multiply-and-accumulate operation, double-precision multiply-and-accumulate operation
rev. 5.00, 09/03, page 36 of 760 classification types operation code function no. of instructions 21 mul double-precision multiplication (32 32 bits) 33 arithmetic operations (cont) muls signed multiplication (16 16 bits) mulu unsigned multiplication (16 16 bits) neg negation negc negation with borrow sub binary subtraction subc binary subtraction with borrow subv binary subtraction with underflow check 6 and logical and 14 logic operations not bit inversion or logical or tas memory test and bit set tst logical and and t bit set xor exclusive or shift 12 rotl one-bit left rotation 16 rotr one-bit right rotation rotcl one-bit left rotation with t bit rotcr one-bit right rotation with t bit shal one-bit arithmetic left shift shar one-bit arithmetic right shift shll one-bit logical left shift shlln n-bit logical left shift shlr one-bit logical right shift shlrn n-bit logical right shift shad dynamic arithmetic shift shld dynamic logical shift
rev. 5.00, 09/03, page 37 of 760 classification types operation code function no. of instructions branch 9 bf conditional branch, delayed conditional branch (t = 0) 11 bt conditional branch, delayed conditional branch (t = 1) bra unconditional branch braf unconditional branch bsr branch to subroutine procedure bsrf branch to subroutine procedure jmp unconditional branch jsr branch to subroutine procedure rts return from subroutine procedure system 15 clrmac mac register clear 75 control clrt clear t bit clrs clear s bit ldc load to control register lds load to system register ldtlb load pte to tlb nop no operation pref prefetch data to cache rte return from exception handling sets set s bit sett set t bit sleep shift to power-down mode stc store from control register sts store from system register trapa trap exception handling total: 68 188
rev. 5.00, 09/03, page 38 of 760 table 2.5 lists the sh7709s instruction code formats. table 2.5 instruction code format item format explanation instruction mnemonic op.sz src,dest op: operation code sz: size src: source dest: destination rm: source register rn: destination register imm: immediate data disp: displacement instruction code msb ? lsb mmmm: source register nnnn: destination register 0000: r0 0001: r1 ........... 1111: r15 iiii: immediate data dddd: displacement * operation summary , (xx) m/q/t & | ^ ~ <>n direction of transfer memory operand flag bits in sr logical and of each bit logical or of each bit exclusive or of each bit logical not of each bit n-bit shift privileged mode indicates whether privileged mode applies execution cycles value when no wait states are inserted the execution cycles listed in the table are minimums. the actual number of cycles may be increased in cases such as the followsing: 1. when contention occurs between instruction fetches and data access 2. when the destination register of the load instruction (memory register) and the register used by the next instruction are the same t bit value of t bit after instruction is executed ?: no change note: * scaling ( 1, 2, 4) is performed according to the instruction operand size.
rev. 5.00, 09/03, page 39 of 760 table 2.6 lists the sh7709s data transfer instructions table 2.6 data transfer instructions instruction operation code privileged mode cycles t bit mov #imm,rn imm sign extension rn 1110nnnniiiiiiii ?1? mov.w @(disp,pc),rn (disp 2 + pc) sign extension rn 1001nnnndddddddd ?1? mov.l @(disp,pc),rn (disp 4 + pc) rn 1101nnnndddddddd ?1? mov rm,rn rm rn 0110nnnnmmmm0011 ?1? mov.b rm,@rn rm (rn) 0010nnnnmmmm0000 ?1? mov.w rm,@rn rm (rn) 0010nnnnmmmm0001 ?1? mov.l rm,@rn rm (rn) 0010nnnnmmmm0010 ?1? mov.b @rm,rn (rm) sign extension rn 0110nnnnmmmm0000 ?1? mov.w @rm,rn (rm) sign extension rn 0110nnnnmmmm0001 ?1? mov.l @rm,rn (rm) rn 0110nnnnmmmm0010 ?1? mov.b rm,@ ? rn rn?1 rn, rm (rn) 0010nnnnmmmm0100 ?1? mov.w rm,@ ? rn rn?2 rn, rm (rn) 0010nnnnmmmm0101 ?1? mov.l rm,@ ? rn rn?4 rn, rm (rn) 0010nnnnmmmm0110 ?1? mov.b @rm+,rn (rm) sign extension rn, rm + 1 rm 0110nnnnmmmm0100 ?1? mov.w @rm+,rn (rm) sign extension rn, rm + 2 rm 0110nnnnmmmm0101 ?1? mov.l @rm+,rn (rm) rn,rm + 4 rm 0110nnnnmmmm0110 ?1? mov.b r0,@(disp,rn) r0 (disp + rn) 10000000nnnndddd ?1? mov.w r0,@(disp,rn) r0 (disp 2 + rn) 10000001nnnndddd ?1? mov.l rm,@(disp,rn) rm (disp 4 + rn) 0001nnnnmmmmdddd ?1? mov.b @(disp,rm),r0 (disp + rm) sign extension r0 10000100mmmmdddd ?1? mov.w @(disp,rm),r0 (disp 2 + rm) sign extension r0 10000101mmmmdddd ?1? mov.l @(disp,rm),rn (disp 4 + rm) rn 0101nnnnmmmmdddd ?1? mov.b rm,@(r0,rn) rm (r0 + rn) 0000nnnnmmmm0100 ?1?
rev. 5.00, 09/03, page 40 of 760 instruction operation code privileged mode cycles t bit mov.w rm,@(r0,rn) rm (r0 + rn) 0000nnnnmmmm0101 ?1? mov.l rm,@(r0,rn) rm (r0 + rn) 0000nnnnmmmm0110 ?1? mov.b @(r0,rm),rn (r0 + rm) sign extension rn 0000nnnnmmmm1100 ?1? mov.w @(r0,rm),rn (r0 + rm) sign extension rn 0000nnnnmmmm1101 ?1? mov.l @(r0,rm),rn (r0 + rm) rn 0000nnnnmmmm1110 ?1? mov.b r0,@(disp,gbr) r0 (disp + gbr) 11000000dddddddd ?1? mov.w r0,@(disp,gbr) r0 (disp 2 + gbr) 11000001dddddddd ?1? mov.l r0,@(disp,gbr) r0 (disp 4 + gbr) 11000010dddddddd ?1? mov.b @(disp,gbr),r0 (disp + gbr) sign extension r0 11000100dddddddd ?1? mov.w @(disp,gbr),r0 (disp 2 + gbr) sign extension r0 11000101dddddddd ?1? mov.l @(disp,gbr),r0 (disp 4 + gbr) r0 11000110dddddddd ?1? mova @(disp,pc),r0 disp 4 + pc r0 11000111dddddddd ?1? movt rn t rn 0000nnnn00101001 ?1? swap.b rm,rn rm swap the bottom two bytes rn 0110nnnnmmmm1000 ?1? swap.w rm,rn rm swap two consecutive words rn 0110nnnnmmmm1001 ?1? xtrct rm,rn rm: middle 32 bits of rn rn 0010nnnnmmmm1101 ?1?
rev. 5.00, 09/03, page 41 of 760 table 2.7 lists the sh7709s arithmetic instructions. table 2.7 arithmetic instructions instruction operation code privileged mode cycles t bit add rm,rn rn + rm rn 0011nnnnmmmm1100 ?1? add #imm,rn rn + imm rn 0111nnnniiiiiiii ?1? addc rm,rn rn + rm + t rn, carry t 0011nnnnmmmm1110 ? 1 carry addv rm,rn rn + rm rn, overflow t 0011nnnnmmmm1111 ? 1 overflow cmp/eq #imm,r0 if r0 = imm, 1 t 10001000iiiiiiii ? 1 comparison result cmp/eq rm,rn if rn = rm, 1 t 0011nnnnmmmm0000 ? 1 comparison result cmp/hs rm,rn if rn rm with unsigned data, 1 t 0011nnnnmmmm0010 ? 1 comparison result cmp/ge rm,rn if rn rm with signed data, 1 t 0011nnnnmmmm0011 ? 1 comparison result cmp/hi rm,rn if rn > rm with unsigned data, 1 t 0011nnnnmmmm0110 ? 1 comparison result cmp/gt rm,rn if rn > rm with signed data, 1 t 0011nnnnmmmm0111 ? 1 comparison result cmp/pz rn if rn 0, 1 t 0100nnnn00010001 ? 1 comparison result cmp/pl rn if rn > 0, 1 t 0100nnnn00010101 ? 1 comparison result cmp/str rm,rn if rn and rm have an equivalent byte, 1 t 0010nnnnmmmm1100 ? 1 comparison result div1 rm,rn single-step division (rn/rm) 0011nnnnmmmm0100 ? 1 calculation result div0s rm,rn msb of rn q, msb of rm m, m ^ q t 0010nnnnmmmm0111 ? 1 calculation result div0u 0 m/q/t 0000000000011001 ?10
rev. 5.00, 09/03, page 42 of 760 instruction operation code privileged mode cycles t bit dmuls.l rm,rn signed operation of rn rm mach, macl 32 32 64 bits 0011nnnnmmmm1101 ? 2(to 5) * ? dmulu.l rm,rn unsigned operation of rn rm mach, macl 32 32 64 bits 0011nnnnmmmm0101 ? 2(to 5) * ? dt rn rn ? 1 rn, if rn = 0, 1 t, else 0 t 0100nnnn00010000 ? 1 comparison result exts.b rm,rn a byte in rm is sign- extended rn 0110nnnnmmmm1110 ?1? exts.w rm,rn a word in rm is sign- extended rn 0110nnnnmmmm1111 ?1? extu.b rm,rn a byte in rm is zero- extended rn 0110nnnnmmmm1100 ?1? extu.w rm,rn a word in rm is zero- extended rn 0110nnnnmmmm1101 ?1? mac.l @rm+,@rn+ signed operation of (rn) (rm) + mac mac, rn + 4 rn, rm + 4 rm, 32 32 + 64 64 bits 0000nnnnmmmm1111 ? 2(to 5) * ? mac.w @rm+,@rn+ signed operation of (rn) (rm) + mac mac, rn + 2 rn, rm + 2 rm, 16 16 + 64 64 bits 0100nnnnmmmm1111 ? 2(to 5) * ? mul.l rm,rn rn rm macl, 32 32 32 bits 0000nnnnmmmm0111 ? 2(to 5) * ? muls.w rm,rn signed operation of rn rm macl, 16 16 32 bits 0010nnnnmmmm1111 ? 1(to 3) * ? mulu.w rm,rn unsigned operation of rn rm macl, 16 16 32 bits 0010nnnnmmmm1110 ? 1(to 3) * ?
rev. 5.00, 09/03, page 43 of 760 instruction operation code privileged mode cycles t bit neg rm,rn 0?rm rn 0110nnnnmmmm1011 ?1? negc rm,rn 0?rm?t rn, borrow t 0110nnnnmmmm1010 ?1borrow sub rm,rn rn?rm rn 0011nnnnmmmm1000 ?1? subc rm,rn rn?rm?t rn, borrow t 0011nnnnmmmm1010 ?1borrow subv rm,rn rn?rm rn, underflow t 0011nnnnmmmm1011 ? 1 underflow note: * the normal number of execution cycles is shown. the value in parentheses is the number of cycles required in case of contention with the preceding or following instruction.
rev. 5.00, 09/03, page 44 of 760 table 2.8 lists the sh7709s logic operation instructions. table 2.8 logic operation instructions instruction operation code privileged mode cycles t bit and rm,rn rn & rm rn 0010nnnnmmmm1001 ?1? and #imm,r0 r0 & imm r0 11001001iiiiiiii ?1? and.b #imm,@(r0,gbr) (r0 + gbr) & imm (r0 + gbr) 11001101iiiiiiii ?3? not rm,rn ~rm rn 0110nnnnmmmm0111 ?1? or rm,rn rn | rm rn 0010nnnnmmmm1011 ?1? or #imm,r0 r0 | imm r0 11001011iiiiiiii ?1? or.b #imm,@(r0,gbr) (r0 + gbr) | imm (r0 + gbr) 11001111iiiiiiii ?3? tas.b @rn if (rn) is 0, 1 t; 1 msb of (rn) 0100nnnn00011011 ?3test result tst rm,rn rn & rm; if the result is 0, 1 t 0010nnnnmmmm1000 ?1test result tst #imm,r0 r0 & imm; if the result is 0, 1 t 11001000iiiiiiii ?1test result tst.b #imm,@(r0,gbr) (r0 + gbr) & imm; if the result is 0, 1 t 11001100iiiiiiii ?3test result xor rm,rn rn ^ rm rn 0010nnnnmmmm1010 ?1? xor #imm,r0 r0 ^ imm r0 11001010iiiiiiii ?1? xor.b #imm,@(r0,gbr) (r0 + gbr) ^ imm (r0 + gbr) 11001110iiiiiiii ?3?
rev. 5.00, 09/03, page 45 of 760 table 2.9 lists the sh7709s shift instructions. table 2.9 shift instructions instruction operation code privileged mode cycles t bit rotl rn t rn msb 0100nnnn00000100 ?1msb rotr rn lsb rn t 0100nnnn00000101 ?1lsb rotcl rn t rn t 0100nnnn00100100 ?1msb rotcr rn t rn t 0100nnnn00100101 ?1lsb shad rm,rn rn 0: rn << rm rn rn < 0: rn >> rm [msb rn] 0100nnnnmmmm1100 ?1? shal rn t rn 0 0100nnnn00100000 ?1msb shar rn msb rn t 0100nnnn00100001 ?1lsb shld rm,rn rn 0: rn << rm rn rn < 0: rn >> rm [0 rn] 0100nnnnmmmm1101 ?1? shll rn t rn 0 0100nnnn00000000 ?1msb shlr rn 0 rn t 0100nnnn00000001 ?1lsb shll2 rn rn << 2 rn 0100nnnn00001000 ?1? shlr2 rn rn >> 2 rn 0100nnnn00001001 ?1? shll8 rn rn << 8 rn 0100nnnn00011000 ?1? shlr8 rn rn >> 8 rn 0100nnnn00011001 ?1? shll16 rn rn << 16 rn 0100nnnn00101000 ?1? shlr16 rn rn >> 16 rn 0100nnnn00101001 ?1?
rev. 5.00, 09/03, page 46 of 760 table 2.10 lists the sh7709s branch instructions. table 2.10 branch instructions instruction operation code privileged mode cycles t bit bf label if t = 0, disp 2 + pc pc; if t = 1, nop 10001011dddddddd ?3/1 * ? bf/s label delayed branch, if t = 0, disp 2 + pc pc; if t = 1, nop 10001111dddddddd ?2/1 * ? bt label if t = 1, disp 2 + pc pc; if t = 0, nop 10001001dddddddd ?3/1 * ? bt/s label delayed branch, if t = 1, disp 2 + pc pc; if t = 0, nop 10001101dddddddd ?2/1 * ? bra label delayed branch, disp 2 + pc pc 1010dddddddddddd ?2? braf rm delayed branch, rm + pc pc 0000mmmm00100011 ?2? bsr label delayed branch, pc pr, disp 2 + pc pc 1011dddddddddddd ?2? bsrf rm delayed branch, pc pr, rm + pc pc 0000mmmm00000011 ?2? jmp @rm delayed branch, rm pc 0100mmmm00101011 ?2? jsr @rm delayed branch, pc pr, rm pc 0100mmmm00001011 ?2? rts delayed branch, pr pc 0000000000001011 ?2? note: * one state when there is no branch.
rev. 5.00, 09/03, page 47 of 760 table 2.11 lists the sh7709s system control instructions. table 2.11 system control instructions instruction operation code privileged mode cycles t bit clrmac 0 mach, macl 0000000000101000 ?1? clrs 0 s 0000000001001000 ?1? clrt 0 t 0000000000001000 ?10 ldc rm,sr rm sr 0100mmmm00001110 5lsb ldc rm,gbr rm gbr 0100mmmm00011110 ?3? ldc rm,vbr rm vbr 0100mmmm00101110 3? ldc rm,ssr rm ssr 0100mmmm00111110 3? ldc rm,spc rm spc 0100mmmm01001110 3? ldc rm,r0_bank rm r0_bank 0100mmmm10001110 3? ldc rm,r1_bank rm r1_bank 0100mmmm10011110 3? ldc rm,r2_bank rm r2_bank 0100mmmm10101110 3? ldc rm,r3_bank rm r3_bank 0100mmmm10111110 3? ldc rm,r4_bank rm r4_bank 0100mmmm11001110 3? ldc rm,r5_bank rm r5_bank 0100mmmm11011110 3? ldc rm,r6_bank rm r6_bank 0100mmmm11101110 3? ldc rm,r7_bank rm r7_bank 0100mmmm11111110 3? ldc.l @rm+,sr (rm) sr, rm + 4 rm 0100mmmm00000111 7lsb ldc.l @rm+,gbr (rm) gbr, rm + 4 rm 0100mmmm00010111 ?5? ldc.l @rm+,vbr (rm) vbr, rm + 4 rm 0100mmmm00100111 5? ldc.l @rm+,ssr (rm) ssr, rm + 4 rm 0100mmmm00110111 5? ldc.l @rm+,spc (rm) spc, rm + 4 rm 0100mmmm01000111 5? ldc.l @rm+, r0_bank (rm) r0_bank, rm + 4 rm 0100mmmm10000111 5? ldc.l @rm+, r1_bank (rm) r1_bank, rm + 4 rm 0100mmmm10010111 5? ldc.l @rm+, r2_bank (rm) r2_bank, rm + 4 rm 0100mmmm10100111 5? ldc.l @rm+, r3_bank (rm) r3_bank, rm + 4 rm 0100mmmm10110111 5? ldc.l @rm+, r4_bank (rm) r4_bank, rm + 4 rm 0100mmmm11000111 5? ldc.l @rm+, r5_bank (rm) r5_bank, rm + 4 rm 0100mmmm11010111 5?
rev. 5.00, 09/03, page 48 of 760 instruction operation code privileged mode cycles t bit ldc.l @rm+, r6_bank (rm) r6_bank, rm + 4 rm 0100mmmm11100111 5? ldc.l @rm+, r7_bank (rm) r7_bank, rm + 4 rm 0100mmmm11110111 5? lds rm,mach rm mach 0100mmmm00001010 ?1? lds rm,macl rm macl 0100mmmm00011010 ?1? lds rm,pr rm pr 0100mmmm00101010 ?1? lds.l @rm+,mach (rm) mach, rm + 4 rm 0100mmmm00000110 ?1? lds.l @rm+,macl (rm) macl, rm + 4 rm 0100mmmm00010110 ?1? lds.l @rm+,pr (rm) pr, rm + 4 rm 0100mmmm00100110 ?1? ldtlb pteh/ptel tlb 0000000000111000 1? nop no operation 0000000000001001 ?1? pref @rm (rm) cache 0000mmmm10000011 ? 2? rte delayed branch, ssr sr, spc pc 0000000000101011 4? sets 1 s 0000000001011000 ?1? sett 1 t 0000000000011000 ?11 sleep sleep 0000000000011011 4 * ? stc sr,rn sr rn 0000nnnn00000010 1? stc gbr,rn gbr rn 0000nnnn00010010 ?1? stc vbr,rn vbr rn 0000nnnn00100010 1? stc ssr,rn ssr rn 0000nnnn00110010 1? stc spc,rn spc rn 0000nnnn01000010 1? stc r0_bank,rn r0_bank rn 0000nnnn10000010 1? stc r1_bank,rn r1_bank rn 0000nnnn10010010 1? stc r2_bank,rn r2_bank rn 0000nnnn10100010 1? stc r3_bank,rn r3_bank rn 0000nnnn10110010 1? stc r4_bank,rn r4_bank rn 0000nnnn11000010 1? stc r5_bank,rn r5_bank rn 0000nnnn11010010 1? stc r6_bank,rn r6_bank rn 0000nnnn11100010 1? stc r7_bank,rn r7_bank rn 0000nnnn11110010 1? stc.l sr,@ ? rn rn?4 rn, sr (rn) 0100nnnn00000011 2? stc.l gbr,@ ? rn rn?4 rn, gbr (rn) 0100nnnn00010011 ?2? stc.l vbr,@ ? rn rn?4 rn, vbr (rn) 0100nnnn00100011 2? note: * the number of cycles until the sleep state is entered.
rev. 5.00, 09/03, page 49 of 760 instruction operation code privileged mode cycles t bit stc.l ssr,@ ? rn rn?4 rn, ssr (rn) 0100nnnn00110011 2? stc.l spc,@ ? rn rn?4 rn, spc (rn) 0100nnnn01000011 2? stc.l r0_bank, @ ? rn rn?4 rn, r0_bank (rn) 0100nnnn10000011 2? stc.l r1_bank, @ ? rn rn?4 rn, r1_bank (rn) 0100nnnn10010011 2? stc.l r2_bank, @ ? rn rn?4 rn, r2_bank (rn) 0100nnnn10100011 2? stc.l r3_bank, @ ? rn rn?4 rn, r3_bank (rn) 0100nnnn10110011 2? stc.l r4_bank, @ ? rn rn?4 rn, r4_bank (rn) 0100nnnn11000011 2? stc.l r5_bank, @ ? rn rn?4 rn, r5_bank (rn) 0100nnnn11010011 2? stc.l r6_bank, @ ? rn rn?4 rn, r6_bank (rn) 0100nnnn11100011 2? stc.l r7_bank, @ ? rn rn?4 rn, r7_bank (rn) 0100nnnn11110011 2? sts mach,rn mach rn 0000nnnn00001010 ?1? sts macl,rn macl rn 0000nnnn00011010 ?1? sts pr,rn pr rn 0000nnnn00101010 ?1? sts.l mach,@ ? rn rn?4 rn, mach (rn) 0100nnnn00000010 ?1? sts.l macl,@ ? rn rn?4 rn, macl (rn) 0100nnnn00010010 ?1? sts.l pr,@ ? rn rn?4 rn, pr (rn) 0100nnnn00100010 ?1? trapa #imm pc spc, sr ssr, imm tra 11000011iiiiiiii ?8? notes: 1. the table shows the minimum number of execution cycles. the actual number of instruction execution cycles will increase in cases such as the following: ? when there is contention between an instruction fetch and data access ? when the destination register in a load (memory-to-register) instruction is also used by the next instruction 2. with the addressing modes using displacement (disp) listed below, the assembler descriptions in this manual show the value before scaling ( 1, 2, or 4) is performed. this is done to clarify the operation of the chip. for the actual assembler descriptions, refer to the individual assembler notation rules. @ (disp:4, rn) ; register-indirect with displacement @ (disp:8, rn) ; gbr-indirect with displacement @ (disp:8, pc) ; pc-relative with displacement disp:8, disp:12 ; pc-relative
rev. 5.00, 09/03, page 50 of 760 2.4.2 instruction code map table 2.12 shows the instruction code map. table 2.12 instruction code map instruction code fx: 0000 fx: 0001 fx: 0010 fx: 0011 to 1111 msb lsb md: 00 md: 01 md: 10 md: 11 0000 rn fx 0000 0000 rn fx 0001 0000 rn 00md 0010 stc sr,rn stc gbr,rn stc vbr,rn stc ssr,rn 0000 rn 01md 0010 stc spc,rn 0000 rn 10md 0010 stc r0_bank,rn stc r1_bank,rn stc r2_bank,rn stc r3_bank,rn 0000 rn 11md 0010 stc r4_bank,rn stc r5_bank,rn stc r6_bank,rn stc r7_bank,rn 0000 rm 00md 0011 bsrf rm braf rm 0000 rn 10md 0011 pref @rn 0000 rn rm 01md mov.b rm,@(r0,rn) mov.w rm,@(r0,rn) mov.l rm,@(r0,rn) mul.l rm,rn 0000 0000 00md 1000 clrt sett clrmac ldtlb 0000 0000 01md 1000 clrs sets 0000 0000 fx 1001 nop div0u 0000 0000 fx 1010 0000 0000 fx 1011 rts sleep rte 0000 rn fx 1000 0000 rn fx 1001 movt rn 0000 rn fx 1010 sts mach,rn sts macl,rn sts pr,rn 0000 rn fx 1011 0000 rn rm 11md mov.b @(r0,rm),rn mov.w @(r0,rm),rn mov.l @(r0,rm),rn mac.l @rm+,@rn+ 0001 rn rm disp mov.l rm,@(disp:4,rn) 0010 rn rm 00md mov.b rm,@rn mov.w rm,@rn mov.l rm,@rn 0010 rn rm 01md mov.b rm,@-rn mov.w rm,@-rn mov.l rm,@-rn div0s rm,rn 0010 rn rm 10md tst rm,rn and rm,rn xor rm,rn or rm,rn 0010 rn rm 11md cmp/str rm,rn xtrct rm,rn mulu.w rm,rn mulsw rm,rn 0011 rn rm 00md cmp/eq rm,rn cmp/hs rm,rn cmp/ge rm,rn 0011 rn rm 01md div1 rm,rn dmulu.lrm,rn cmp/hi rm,rn cmp/gt rm,rn 0011 rn rm 10md sub rm,rn subc rm,rn subv rm,rn 0011 rn rm 11md add rm,rn dmuls.l rm,rn addc rm,rn addv rm,rn
rev. 5.00, 09/03, page 51 of 760 instruction code fx: 0000 fx: 0001 fx: 0010 fx: 0011 to 1111 msb lsb md: 00 md: 01 md: 10 md: 11 0100 rn fx 0000 shll rn dt rn shal rn 0100 rn fx 0001 shlr rn cmp/pz rn shar rn 0100 rn fx 0010 sts.l mach,@-rn sts.l macl,@-rn sts.l pr,@-rn 0100 rn 00md 0011 stc.l sr,@-rn stc.l gbr,@-rn stc.l vbr,@-rn stc.l ssr,@-rn 0100 rn 01md 0011 stc.l spc,@-rn 0100 rn 10md 0011 stc.l r0_bank,@-rn stc.l r1_bank,@-rn stc.l r2_bank,@-rn stc.l r3_bank,@-rn 0100 rn 11md 0011 stc.l r4_bank,@-rn stc.l r5_bank,@-rn stc.l r6_bank,@-rn stc.l r7_bank,@-rn 0100 rn fx 0100 rotl rn rotcl rn 0100 rn fx 0101 rotr rn cmp/pl rn rotcr rn 0100 rm fx 0110 lds.l @rm+,mach lds.l @rm+,macl lds.l @rm+,pr 0100 rm 00md 0111 ldc.l @rm+,sr ldc.l @rm+,gbr ldc.l @rm+,vbr ldc.l @rm+,ssr 0100 rm 01md 0111 ldc.l @rm+,spc 0100 rm 10md 0111 ldc.l @rm+,r0_bank ldc.l @rm+,r1_bank ldc.l @rm+,r2_bank ldc.l @rm+,r3_bank 0100 rm 11md 0111 ldc.l @rm+,r4_bank ldc.l @rm+,r5_bank ldc.l @rm+,r6_bank ldc.l @rm+,r7_bank 0100 rn fx 1000 shll2 rn shll8 rn shll16 rn 0100 rn fx 1001 shlr2 rn shlr8 rn shlr16 rn 0100 rm fx 1010 lds rm,mach lds rm,macl lds rm,pr 0100 rm/ rn fx 1011 jsr @rm tas.b @rn jmp @rm 0100 rn rm 1100 shad rm,rn 0100 rn rm 1101 shld rm,rn 0100 rm 00md 1110 ldc rm,sr ldc rm,gbr ldc rm,vbr ldc rm,ssr 0100 rm 01md 1110 ldc rm,spc 0100 rm 10md 1110 ldc rm,r0_bank ldc rm,r1_bank ldc rm,r2_bank ldc rm,r3_bank 0100 rm 11md 1110 ldc rm,r4_bank ldc rm,r5_bank ldc rm,r6_bank ldc rm,r7_bank 0100 rn rm 1111 mac.w @rm+,@rn+ 0101 rn rm disp mov.l @(disp:4,rm),rn 0110 rn rm 00md mov.b @rm,rn mov.w @rm,rn mov.l @rm,rn mov rm,rn 0110 rn rm 01md mov.b @rm+,rn mov.w @rm+,rn mov.l @rm+,rn not rm,rn 0110 rn rm 10md swap.b rm,rn swap.w rm,rn negc rm,rn neg rm,rn 0110 rn rm 11md extu.b rm,rn extu.w rm,rn exts.b rm,rn exts.w rm,rn 0111 rn imm add #imm:8,rn
rev. 5.00, 09/03, page 52 of 760 instruction code fx: 0000 fx: 0001 fx: 0010 fx: 0011 to 1111 msb lsb md: 00 md: 01 md: 10 md: 11 1000 00md rn disp mov.b r0,@(disp:4,rn) mov.w r0,@(disp:4,rn) 1000 01md rm disp mov.b @(disp:4,rm),r0 mov.w @(disp:4,rm),r0 1000 10md imm/disp cmp/eq #imm:8,r0 bt label:8 bf label:8 1000 11md imm/disp bt/s label:8 bf/s label:8 1001 rn disp mov.w @(disp:8,pc),rn 1010 disp bra label:12 1011 disp bsr label:12 1100 00md imm/disp mov.b r0,@(disp:8,gbr) mov.w r0,@(disp:8,gbr) mov.l r0,@(disp:8,gbr) trapa #imm:8 1100 01md disp mov.b @(disp:8,gbr),r0 mov.w @(disp:8,gbr),r0 mov.l @(disp:8,gbr),r0 mova @(disp:8,pc),r0 1100 10md imm tst #imm:8,r0 and #imm:8,r0 xor #imm:8,r0 or #imm:8,r0 1100 11md imm tst.b #imm:8,@(r0,gbr) and.b #imm:8,@(r0,gbr) xor.b #imm:8,@(r0,gbr) or.b #imm:8,@(r0,gbr) 1101 rn disp mov.l @(disp:8,pc),rn 1110 rn imm mov #imm:8,rn 1111 ************ note: see the sh-3/sh-3e/sh3-dsp programming manual for details.
rev. 5.00, 09/03, page 53 of 760 2.5 processor states and processor modes 2.5.1 processor states the sh7709s has five processor states: the reset state, exception-handling state, bus-released state, program execution state, and power-down state. reset state: in this state the cpu is reset. the cpu enters the power-on reset state if the resetp pin is low, or the manual reset state if the resetm pin is low. see section 4, exception handling, for more information on resets. in the power-on reset state, the internal states of the cpu and the on-chip supporting module registers are initialized. in the manual reset state, the internal states of the cpu and registers of on- chip supporting modules other than the bus state controller (bsc) are initialized. refer to the register configurations in the relevant sections for further details. exception-handling state: this is a transient state during which the cpu?s processor state flow is altered by a reset, general exception, or interrupt exception handling. in the case of a reset, the cpu branches to address h'a0000000 and starts executing the user- coded exception handling program. in the case of a general exception or interrupt, the program counter (pc) contents are saved in the saved program counter (spc) and the status register (sr) contents are saved in the saved status register (ssr). the cpu branches to the start address of the user-coded exception service routine found from the sum of the contents of the vector base address and the vector offset. see section 4, exception processing, for more information on resets, general exceptions, and interrupts. program execution state: in this state the cpu executes program instructions in sequence. power-down state: in the power-down state, cpu operation halts and power consumption is reduced. there are two modes in the power-down state: sleep mode, and standby mode. see section 8, power-down modes, for more information. bus-released state: in this state the cpu has released the bus to a device that requested it. transitions between the states are shown in figure 2.8.
rev. 5.00, 09/03, page 54 of 760 from any state when resetp = 0 from any state but hardware standby mode when resetm = 0 note: * the hardware standby mode is entered when the ca pin goes low from any state. resetp = 1 resetm = 1 resetp = 0 ca = 1, resetp =0 power-on reset state manual reset state program execution state bus-released state sleep mode standby mode hardware standby mode * exception-handling state interrupt bus request bus request clearance exception interrupt end of exception transition processing bus request bus request clearance sleep instruction with stby bit set interrupt reset state power-down state sleep instruction with stby bit cleared bus request bus request clearance figure 2.8 processor state transitions 2.5.2 processor modes there are two processor modes: privileged mode and user mode. the processor mode is determined by the processor mode bit (md) in the status register (sr). user mode is selected when the md bit is 0, and privileged mode when the md bit is 1. when the reset state or exception state is entered, the md bit is set to 1. when exception handling ends, the md bit is cleared to 0 and user mode is entered. there are certain registers and bits which can only be accessed in privileged mode.
rev. 5.00, 09/03, page 55 of 760 section 3 memory management unit (mmu) 3.1 overview 3.1.1 features the sh7709s has an on-chip memory management unit (mmu) that implements address translation. the sh7709s features a resident translation look-aside buffer (tlb) that caches information for user-created address translation tables located in external memory. it enables high- speed translation of virtual addresses into physical addresses. address translation uses the paging system and supports two page sizes (1 kbytes and 4 kbytes). the access right to virtual address space can be set for privileged and user modes to provide memory protection. 3.1.2 role of mmu the mmu is a feature designed to make efficient use of physical memory. as shown in figure 3.1, if a process is smaller in size than the physical memory, the entire process can be mapped onto physical memory. however, if the process increases in size to the extent that it no longer fits into physical memory, it becomes necessary to partition the process and to map those parts requiring execution onto memory as occasion demands ((1)). having the process itself consider this mapping onto physical memory would impose a large burden on the process. to lighten this burden, the idea of virtual memory was born as a means of performing en bloc mapping onto physical memory ((2)). in a virtual memory system, substantially more virtual memory than physical memory is provided, and the process is mapped onto this virtual memory. thus a process only has to consider operation in virtual memory. mapping from virtual memory to physical memory is handled by the mmu. the mmu is normally controlled by the operating system, switching physical memory to allow the virtual memory required by a process to be mapped onto physical memory in a smooth fashion. switching of physical memory is carried out via secondary storage, etc. the virtual memory system that came into being in this way is particularly effective in a time- sharing system (tss) in which a number of processes are running simultaneously ((3)). if processes running in a tss had to take mapping onto virtual memory into consideration while running, it would not be possible to increase efficiency. virtual memory is thus used to reduce this load on the individual processes and so improve efficiency ((4)). in the virtual memory system, virtual memory is allocated to each process. the task of the mmu is to perform efficient mapping of these virtual memory areas onto physical memory. it also has a memory protection feature that prevents one process from inadvertently accessing another process?s physical memory. when address translation from virtual memory to physical memory is performed using the mmu, it may occur that the relevant translation information is not recorded in the mmu, with the result that one process may inadvertently access the virtual memory allocated to another process. in this
rev. 5.00, 09/03, page 56 of 760 case, the mmu will generate an exception, change the physical memory mapping, and record the new address translation information. although the functions of the mmu could also be implemented by software alone, the need for translation to be performed by software each time a process accesses physical memory would result in poor efficiency. for this reason, a buffer for address translation (translation look-aside buffer: tlb) is provided in hardware to hold frequently used address translation information. the tlb can be described as a cache for storing address translation information. unlike cache memory, however, if address translation fails, that is, if an exception is generated, switching of address translation information is normally performed by software. this makes it possible for memory management to be performed flexibly by software. the mmu has two methods of mapping from virtual memory to physical memory: a paging method using fixed-length address translation, and a segment method using variable-length address translation. with the paging method, the unit of translation is a fixed-size address space (usually of 1 to 64 kbytes) called a page. this lsi uses the paging method. in the following text, the sh7709s address space in virtual memory is referred to as virtual address space, and address space in physical memory as physical memory space.
rev. 5.00, 09/03, page 57 of 760 process 1 physical memory mmu (1) (2) (3) (4) process 1 physical memory process 1 virtual memory mmu physical memory process 1 process 2 process 3 physical memory process 1 process 2 process 3 virtual memory physical memory figure 3.1 mmu functions
rev. 5.00, 09/03, page 58 of 760 3.1.3 sh7709s mmu virtual address space: the sh7709s uses 32-bit virtual addresses to access a 4-gbyte virtual address space that is divided into several areas. address space mapping is shown in figure 3.2. ? privileged mode in privileged mode, there are five areas, p0?p4. the p0 and p3 areas are mapped onto physical address space in page units, in accordance with address translation table information. write- back or write-through can be selected for write access by means of a cache control register (ccr) setting. mapping of the p1 area is fixed in physical address space (h'00000000 to h'1fffffff). in the p1 area, setting a virtual address msb (bit 31) to 0 generates the corresponding physical address. p1 area accesses can be cached, and the cache control register (ccr) is set to indicate whether to cache or not. write-back or write-through mode can be selected. mapping of the p2 area is fixed in physical address space (h'00000000 to h'1fffffff). in the p2 area, setting the top three virtual address bits (bits 31, 30, and 29) to 0 generates the corresponding physical address. p2 area access cannot be cached. the p1 and p2 areas are not mapped by the address translation table, so the tlb is not used and no exceptions such as tlb misses occur. initialization of mmu control registers, exception handling routines, and the like should be located in the p1 and p2 areas. routines that require high-speed processing should be placed in the p1 area, since it can be cached. some peripheral module control registers are located in area 1 of the physical address space. when the physical address space is not used for address translation, these registers should be located in the p2 area. when address translation is to be used, set no caching. the p4 area is used for mapping peripheral module register addresses, etc. ? user mode in user mode, 2 gbytes of the virtual address space from h'00000000 to h'7fffffff (area u0) can be accessed. u0 is mapped onto physical address space in page units, in accordance with address translation table information.
rev. 5.00, 09/03, page 59 of 760 h80000000 ha0000000 hc0000000 he0000000 hffffffff 2-gbyte virtual space, cacheable (write-back/write-through) 2-gbyte virtual space, cacheable (write-back/write-through) address error h00000000 h00000000 h80000000 hffffffff area p0 area p1 area p2 area p3 area p4 area u0 privileged mode user mode 0.5-gbyte fixed physical space, cacheable (write-back/write-through) 0.5-gbyte fixed physical space, non-cacheable 0.5-gbyte virtual space, cacheable (write-back/write-through) 0.5-gbyte control space, non-cacheable figure 3.2 virtual address space mapping physical address space: the sh7709s supports a 32-bit physical address space, but the upper 3 bits are actually ignored and treated as a shadow. see section 10, bus state controller (bsc), for details. address translation: when the mmu is enabled, the virtual address space is divided into units called pages. physical addresses are translated in page units. address translation tables in external memory hold information such as the physical address that corresponds to the virtual address and memory protection codes. when an access to an area other than p4 occurs, if the accessed virtual address belongs to area p1 or p2 there is no tlb access and the physical address is uniquely defined. if it belongs to area p0, p3, or u0, the tlb is searched by virtual address and, if that virtual address is registered in the tlb, the access hits the tlb. the corresponding physical address and the page control information are read from the tlb and the physical address is determined.
rev. 5.00, 09/03, page 60 of 760 if the virtual address is not registered in the tlb, a tlb miss exception occurs and processing will shift to the tlb miss handler. in the tlb miss handler, the tlb address translation table in external memory is searched and the corresponding physical address and the page control information are registered in the tlb. after returning from the handler, the instruction that caused the tlb miss is re-executed. when the mmu is enabled, address translation information that results in a physical address space of h'80000000?h'ffffffff should not be registered in the tlb. when the mmu is disabled, the virtual address is used directly as the physical address. as the sh7709s supports a 29-bit address space as the physical address space, the top 3 bits of the physical address are ignored, and constitute a shadow space (see section 10, bus state controller (bsc)). for example, addresses h'00001000 in the p0 area, h'80001000 in the p1 area, h'a0001000 in the p2 area, and h'c0001000 in the p3 area are all mapped onto the same physical address. when access to these addresses is performed with the cache enabled, an address with the top 3 bits of the physical address masked to 0 is stored in the cache address array to ensure data congruity. single virtual memory mode and multiple virtual memory mode: there are two virtual memory modes: single virtual memory mode and multiple virtual memory mode. in single virtual memory mode, multiple processes run in parallel using the virtual address space exclusively and the physical address corresponding to a given virtual address is specified uniquely. in multiple virtual memory mode, multiple processes run in parallel sharing the virtual address space, so a given virtual address may be translated into different physical addresses depending on the process. single or multiple virtual mode is selected by a value set in the mmu control register (mmucr). in terms of operation, the only difference between single virtual memory mode and multiple virtual memory mode is in the tlb address comparison method (see section 3.3.3, tlb address comparison). address space identifier (asid): in multiple virtual memory mode, the address space identifier (asid) is used to differentiate between processes running in parallel and sharing virtual address space. the asid is 8 bits in length and can be set by software setting of the asid of the currently running process in the page table entry register high (pteh) within the mmu. when the process is switched using the asid, the tlb does not have to be purged. in single virtual memory mode, the asid is used to provide memory protection for processes running simultaneously and using the virtual address space exclusively (see section 3.4.2, mmu software management).
rev. 5.00, 09/03, page 61 of 760 3.1.4 register configuration a register that has an undefined initial value must be initialized by software. table 3.1 shows the configuration of the mmu control registers. table 3.1 register configuration name abbreviation r/w size initial value * 1 address page table entry register high pteh r/w longword undefined h'fffffff0 page table entry register low ptel r/w longword undefined h'fffffff4 translation table base register ttb r/w longword undefined h'fffffff8 tlb exception address register tea r/w longword undefined h'fffffffc mmu control register mmucr r/w longword * 2 h'ffffffe0 notes: 1. initialized by a power-on reset or manual reset. 2. sv bit: undefined other bits: 0 3.2 register description there are five registers for mmu processing. these registers are located in address space area p4 and can only be accessed from privileged mode by specifying the address. 1. the page table entry register high (pteh) register residing at address h'fffffff0, which consists of a virtual page number (vpn) and asid. the vpn set is the vpn of the virtual address at which the exception is generated in case of an mmu exception or address error exception. when the page size is 4 kbytes, the vpn is the upper 20 bits of the virtual address, but in this case the upper 22 bits of the virtual address are set. the vpn can also be modified by software. as the asid, software sets the number of the currently executing process. the vpn and asid are recorded in the tlb by the ldtlb instruction. 2. the page table entry register low (ptel) register residing at address h'fffffff4, and used to store the physical page number and page management information to be recorded in the tlb by the ldtlb instruction. the contents of this register are only modified in response to a software command. (refer to section 3.4.3, mmu instruction (ldtlb), and section 3.5, mmu exceptions.) 3. the translation table base register (ttb) residing at address h'fffffff8, which points to the base address of the current page table. the hardware does not set any value in ttb automatically. ttb is available to software for general purposes. 4. the tlb exception address register (tea) residing at address h'fffffffc, which stores the virtual address corresponding to a tlb or address error exception. this value remains valid until the next exception or interrupt.
rev. 5.00, 09/03, page 62 of 760 5. the mmu control register (mmucr) residing at address h'ffffffe0, which makes the mmu settings described in figure 3.3. any program that modifies mmucr should reside in the p1 or p2 area. the mmu registers are shown in figure 3.3. 31 7 vpn pteh ptel asid 0 ppn 000 0 10 31 29 28 31 ttb ttb 0 31 virtual address causing tlb-related or address error exception tea 0 mmucr 0 31 8 4 65 73210 sv rc 00 0 tfix at 0: reserved bits. always read as 0. writing is ignored. however, 0 should also be specified in a write to mmucr only. sv: single virtual memory mode bit. 0: multiple virtual memory mode 1: single virtual memory mode rc: a 2-bit random counter, automatically updated by hardware according to the following rules in the event of an mmu exception. when a tlb miss exception occurs, all tlb entry ways corresponding to the virtual address at which the exception occurred are checked, and if all ways are valid, 1 is added to rc; if there is one or more invalid way, they are set by priority from way 0, in the order: way 0, way 1, way 2, way 3. in the event of an mmu exception other than a tlb miss exception, the way which caused the exception is set in rc. tf: tlb flush bit. write 1 to flush the tlb (clear all valid bits of the tlb to 0). always reads 0. ix: index mode bit. when 0, vpn bits 16 - 12 are used as the tlb index number. when 1, the value obtained by ex-oring asid bits 4 - 0 in pteh and vpn bits 16 - 12 are used as the tlb index number. at: address translation bit. enables/disables the mmu. 0: mmu disabled 1: mmu enabled note: * refer to section 3.3, tlb functions. 643210 10 pr * sz * c * d * 8 9 7 v * 00 sh * 0 figure 3.3 mmu register contents
rev. 5.00, 09/03, page 63 of 760 3.3 tlb functions 3.3.1 configuration of the tlb the tlb caches address translation table information located in the external memory. the address translation table stores the physical page number translated from the virtual page number and the control information for the page, which is the unit of address translation. figure 3.4 shows the overall tlb configuration. the tlb is 4-way set associative with 128 entries. there are 32 entries for each way. figure 3.5 shows the configuration of virtual addresses and tlb entries. entry 1 address array data array entry 0 entry 1 entry 31 ways 0 - 3 ways 0 - 3 vpn(11 - 10) vpn(31 - 17) asid(7 - 0) v entry 0 entry 31 ppn(28 - 10) pr(1 - 0) sz c d sh figure 3.4 overall configuration of the tlb
rev. 5.00, 09/03, page 64 of 760 31 9 vpn virtual address (1-kbyte page) virtual address (4-kbyte page) tlb entry offset vpn vpn (31 17) vpn (11 10) asid v ppn d offset 0 10 31 11 0 (15) (2) (19) (8) sh (1) (1) c pr (2) sz (1) (1) (1) 12 vpn: virtual page number. top 22 bits of virtual address for a 1-kbyte page, or top 20 bits of virtual address for a 4-kbyte page. since vpn bits 16-12 are used as the index number, they are not stored in the tlb entry. asid: address space identifier. indicates the process that can access a virtual page. in single virtual memory mode and user mode, or in multiple virtual memory mode, if the sh bit is 0, the address is compared with the asid in pteh when address comparison is performed. sh: share status bit 0 = page not shared between processes 1 = page shared between processes sz: page-size bit 0 = 1-kbyte page 1 = 4-kbyte page v: valid bit. indicates whether entry is valid. 0 = invalid 1 = valid cleared to 0 by a power-on reset. not affected by a manual reset. ppn: physical page number. top 29 bits of physical address. ppn bits 11-10 are not used in case of a 4-kbyte page. attention must be paid to the synonym problem in case of a 1-kbyte page (see section 3.4.4, avoiding synonym problems). pr: set the most significant bit to 0. protection key field. 2-bit field encoded to define the access rights to the page. 00: reading only is possible in privileged mode. 01: reading/writing is possible in privileged mode. 10: reading only is possible in privileged/user mode. 11: reading/writing is possible in privileged/user mode. c: cacheable bit. indicates whether the page is cacheable. 0: non-cacheable 1: cacheable d: dirty bit. indicates whether the page has been written to. 0 = not written to 1 = written to legend: figure 3.5 virtual address and tlb structure
rev. 5.00, 09/03, page 65 of 760 3.3.2 tlb indexing the tlb uses a 4-way set associative scheme, so entries must be selected by index. vpn bits 16 to 12 and asid bits 4 to 0 in pteh are used as the index number regardless of the page size. the index number can be generated in two different ways depending on the setting of the ix bit in mmucr. 1. when ix = 0, vpn bits 16?12 alone are used as the index number 2. when ix = 1, vpn bits 16?12 are ex-ored with asid bits 4?0 to generate a 5-bit index number the second method is used to prevent lowered tlb efficiency that results when multiple processes run simultaneously in the same virtual address space (multiple virtual memory) and a specific entry is selected by generating an index number for each process. figures 3.6 and 3.7 show the indexing schemes. 31 16 11 12 17 0 31 0 pteh register virtual address vpn 0 asid 7 10 index asid(4 ? 0) exclusive-or ways 0 - 3 vpn(31 - 17)vpn(11 - 10) asid(7 - 0)v 0 31 address array data array ppn(28 - 10)pr(1 - 0)sz c d sh figure 3.6 tlb indexing (ix = 1)
rev. 5.00, 09/03, page 66 of 760 31 16 11 12 17 0 virtual address ways 0 - 3 vpn(31 - 17) vpn(11 - 10) asid(7 - 0) v 0 address array data array ppn(28 - 10) pr(1 - 0) sz c d sh index 31 figure 3.7 tlb indexing (ix = 0) 3.3.3 tlb address comparison the results of address comparison determine whether a specific virtual page number is registered in the tlb. the virtual page number of the virtual address that accesses external memory is compared to the virtual page number of the indexed tlb entry. the asid within the pteh is compared to the asid of the indexed tlb entry. all four ways are searched simultaneously. if the compared values match, and the indexed tlb entry is valid (v bit = 1), the hit is registered. it is necessary to have software ensure that tlb hits do not occur simultaneously in more than one way, as hardware operation is not guaranteed if this occurs. for example, if there are two identical tlb entries with the same vpn and a setting is made such that a tlb hit is made only by a process with asid = h'ff when one is in the shared state (sh = 1) and the other in the non-shared state (sh = 0), then if the asid in pteh is set to h'ff, there is a possibility of simultaneous tlb hits in both these ways. it is therefore necessary to ensure that this kind of setting is not made by software. the object compared varies depending on the page management information (sz, sh) in the tlb entry. it also varies depending on whether the system supports multiple virtual memory or single virtual memory. the page-size information determines whether vpn (11?10) is compared. vpn (11?10) is compared for 1-kbyte pages (sz = 0) but not for 4-kbyte pages (sz = 1).
rev. 5.00, 09/03, page 67 of 760 the sharing information (sh) determines whether the pteh.asid and the asid in the tlb entry are compared. asids are compared when there is no sharing between processes (sh = 0) but not when there is sharing (sh = 1). when single virtual memory is supported (mmucr.sv = 1) and privileged mode is engaged (sr.md = 1), all process resources can be accessed. this means that asids are not compared when single virtual memory is supported and privileged mode is engaged. the objects of address comparison are shown in figure 3.8. bits compared: vpn (31 ? 17) vpn (11 ? 10) sz = 0? yes no yes (1 kbyte) no (4 kbytes) bits compared: vpn (31 ? 17) bits compared: vpn (31 ? 17) vpn (11 ? 10) asid (7 ? 0) sz = 0? yes (1 kbyte) no (4 kbytes) bits compared: vpn (31 ? 17) asid (7 ? 0) sh = 1 or (sr.md = 1 and mmucr.sv = 1)? figure 3.8 objects of address comparison
rev. 5.00, 09/03, page 68 of 760 3.3.4 page management information in addition to the sh and sz bits, the page management information of tlb entries also includes d, c, and pr bits. the d bit of a tlb entry indicates whether the page is dirty (i.e., has been written to). if the d bit is 0, an attempt to write to the page results in an initial page write exception. for physical page swapping between secondary memory and main memory, for example, pages are controlled so that a dirty page is paged out of main memory only after that page is written back to secondary memory. the c bit in the entry indicates whether the referenced page resides in a cacheable or non- cacheable area of memory. when the control register in area 1 is mapped, set the c bit to 0. the pr field specifies the access rights for the page in privileged and user modes and is used to protect memory. attempts at nonpermitted accesses result in tlb protection violation exceptions. access states designated by the d, c, and pr bits are shown in table 3.2. table 3.2 access states designated by d, c, and pr bits privileged mode user mode reading writing reading writing d bit 0 permitted initial page write exception permitted initial page write exception 1 permitted permitted permitted permitted c bit 0 permitted (no caching) permitted (no caching) permitted (no caching) permitted (no caching) 1 permitted (with caching) permitted (with caching) permitted (with caching) permitted (with caching) pr bit 00 permitted tlb protection violation exception tlb protection violation exception tlb protection violation exception 01 permitted permitted tlb protection violation exception tlb protection violation exception 10 permitted tlb protection violation exception permitted tlb protection violation exception 11 permitted permitted permitted permitted
rev. 5.00, 09/03, page 69 of 760 3.4 mmu functions 3.4.1 mmu hardware management there are two kinds of mmu hardware management as follows: 1. the mmu decodes the virtual address accessed by a process and performs address translation by controlling the tlb in accordance with the mmucr settings. 2. in address translation, the mmu receives page management information from the tlb, and determines the mmu exception and whether the cache is to be accessed (using the c bit). for details of the determination method and the hardware processing, see section 3.5, mmu exceptions. 3.4.2 mmu software management there are three kinds of mmu software management, as follows. 1. mmu register setting. mmucr setting, in particular, should be performed in areas p1 and p2 for which address translation is not performed. also, since sv and ix bit changes constitute address translation system changes, in this case, tlb flushing should be performed by simultaneously writing 1 to the tf bit also. since mmu exceptions are not generated in the mmu disabled state with the at bit cleared to 0, use in the disabled state must be avoided with software that does not use the mmu. 2. tlb entry recording, deletion, and reading. tlb entry recording can be done in two ways by using the ldtlb instruction, or by writing directly to the memory-mapped tlb. for tlb entry deletion and reading, the memory allocation tlb can be accessed. see section 3.4.3, mmu instruction (ldtlb), for details of the ldtlb instruction, and section 3.6, configuration of memory-mapped tlb, for details of the memory-mapped tlb. 3. mmu exception processing. when an mmu exception is generated, it is handled on the basis of information set from the hardware side. see section 3.5, mmu exceptions, for details. when single virtual memory mode is used, it is possible to create a state in which physical memory access is enabled in the privileged mode only by clearing the share status bit (sh) to 0 to specify recording of all tlb entries. this strengthens inter-process memory protection, and enables special access levels to be created in the privileged mode only. recording a 1-kbyte page tlb entry may result in a synonym problem. see section 3.4.4, avoiding synonym problems.
rev. 5.00, 09/03, page 70 of 760 3.4.3 mmu instruction (ldtlb) the load tlb instruction (ldtlb) is used to record tlb entries. when the ix bit in mmucr is 0, the ldtlb instruction changes the tlb entry in the way specified by the rc bit in mmucr to the value specified by pteh and ptel, using vpn bits 16?12 specified in pteh as the index number. when the ix bit in mmucr is 1, the ex-or of vpn bits 16?12 specified in pteh and asid bits 4?0 in pteh are used as the index number. figure 3.9 shows the case where the ix bit in mmucr is 0. when an mmu exception occurs, the virtual page number of the virtual address that caused the exception is set in pteh by hardware. the way is set in the rc bit of mmucr for each exception (see figure 3.3). consequently, if the ldtlb instruction is issued after setting only ptel in the mmu exception handling routine, tlb entry recording is possible. any tlb entry can be updated by software rewriting of pteh and the rc bits in mmucr. as the ldtlb instruction changes address translation information, there is a risk of destroying address translation information if this instruction is issued in the p0, u0, or p3 area. make sure, therefore, that this instruction is issued in the p1 or p2 area. also, an instruction associated with an access to the p0, u0, or p3 area (such as the rte instruction) should be issued at least two instructions after the ldtlb instruction.
rev. 5.00, 09/03, page 71 of 760 vpn(31 - 17) vpn(11 - 10) asid(7 - 0) v vpn 0 asid vpn 0 sv 0 0 rc 0 tfix at ppn 0 000 v 0 pr sz c d sh 0 write ppn(28 - 10) pr(1 - 0) sz c d sh write data array address array way selection ways 0 to 3 31 9 0 mmucr index 31 17 12 10 8 0 pteh register 31 28 29 10 0 ptel register 0 31 figure 3.9 operation of ldtlb instruction
rev. 5.00, 09/03, page 72 of 760 3.4.4 avoiding synonym problems when a 1-kbyte page is recorded in a tlb entry, a synonym problem may arise. if a number of virtual addresses are mapped onto a single physical address, the same physical address data will be recorded in a number of cache entries, and it will not be possible to guarantee data congruity. the reason why this problem only occurs when using a 1-kbyte page is explained below with reference to figure 3.10. to achieve high-speed operation of the sh7709s cache, an index number is created using virtual address bits 11?4. when a 4-kbyte page is used, virtual address bits 11?4 are included in the offset, and since they are not subject to address translation, they are the same as physical address bits 11?4. in cache-based address comparison and recording in the address array, since the cache tag address is a physical address, physical address bits 28?10 are recorded. when a 1-kbyte page is used, also, a cache index number is created using virtual address bits 11-4. however, in case of a 1-kbyte page, virtual address bit (11, 10) is subject to address translation and therefore may not be the same as physical address bit (11, 10). consequently, the physical address is recorded in a different entry from that of the index number indicated by the physical address in the cache address array. for example, assume that, with 1-kbyte page tlb entries, tlb entries for which the following translation has been performed are recorded in two tlbs: virtual address 1 h'00000000 physical address h'00000400 virtual address 2 h'00000400 physical address h'00000400 virtual address 1 is recorded in cache entry h'00, and virtual address 2 in cache entry h'c0. since two virtual addresses are recorded in different cache entries despite the fact that the physical addresses are the same, memory inconsistency will occur as soon as a write is performed to either virtual address. therefore, when recording a 1-kbyte tlb entry, if the physical address is the same as a physical address already used in another tlb entry, it should be recorded in such a way that physical address bit (11, 10) is the same. note: in readiness for the future expansion of the superh risc engine family, we recommend that, when multiple sets of address translation information are mapped onto the same physical area of memory, you set the vpn numbers so that each vpn [20:10] is equal to the others. we also recommend that you do not map multiple sets of address-translation information that include 1- and 4-kbyte pages to a single physical area.
rev. 5.00, 09/03, page 73 of 760 when using a 4-kbyte page virtual address 31 vpn 0 12 11 10 offset physical address 31 ppn 0 offset virtual address (11 ? 4) physical address (28 ? 10) cache address array when using a 1-kbyte page virtual address 31 vpn 0 10 11 offset physical address 31 ppn 000 000 0 10 11 offset virtual address (11 ? 4) physical address (28 ? 10) cache address array 9 9 29 28 29 28 12 11 10 figure 3.10 synonym problem
rev. 5.00, 09/03, page 74 of 760 3.5 mmu exceptions there are four mmu exceptions: tlb miss, tlb protection violation, tlb invalid, and initial page write. 3.5.1 tlb miss exception a tlb miss results when the virtual address and the address array of the selected tlb entry are compared and no match is found. tlb miss exception processing includes both hardware and software operations. hardware operations: in a tlb miss, the sh7709s hardware executes a set of prescribed operations, as follows: 1. the vpn field of the virtual address causing the exception is written to the pteh register. 2. the virtual address causing the exception is written to the tea register. 3. either exception code h'040 for a load access, or h'060 for a store access, is written to the expevt register. 4. the pc value indicating the address of the instruction in which the exception occurred is written to the save program counter (spc). if the exception occurred in a delay slot, the pc value indicating the address of the related delayed branch instruction is written to the spc. 5. the contents of the status register (sr) at the time of the exception are written to the save status register (ssr). 6. the mode (md) bit in sr is set to 1 to place the sh7709s in the privileged mode. 7. the block (bl) bit in sr is set to 1 to mask any further exception requests. 8. the register bank (rb) bit in sr is set to 1. 9. the random counter (rc) field in the mmu control register (mmucr) is incremented by 1 when all ways are checked for the tlb entry corresponding to the logical address at which the exception occurred, and all ways are valid. if one or more ways are invalid, those ways are set in rc in prioritized order from way 0 through way 1, way 2, and way 3. 10. execution branches to the address obtained by adding the value of the vbr contents and h'00000400 to invoke the user-written tlb miss exception handler. software (tlb miss handler) operations: the software searches the page tables in external memory and allocates the required page table entry. upon retrieving the required page table entry, software must execute the following operations: 1. write the value of the physical page number (ppn) field and the protection key (pr), page size (sz), cacheable (c), dirty (d), share status (sh), and valid (v) bits of the page table entry recorded in the address translation table in the external memory into the ptel register in the sh7709s.
rev. 5.00, 09/03, page 75 of 760 2. if using software for way selection for entry replacement, write the desired value to the rc field in mmucr. 3. issue the ldtlb instruction to load the contents of pteh and ptel into the tlb. 4. issue the return from exception handler (rte) instruction to terminate the handler routine and return to the instruction stream. 3.5.2 tlb protection violation exception a tlb protection violation exception results when the virtual address and the address array of the selected tlb entry are compared and a valid entry is found to match, but the type of access is not permitted by the access rights specified in the pr field. tlb protection violation exception processing includes both hardware and software operations. hardware operations: in a tlb protection violation exception, the sh7709s hardware executes a set of prescribed operations, as follows: 1. the vpn field of the virtual address causing the exception is written to the pteh register. 2. the virtual address causing the exception is written to the tea register. 3. either exception code h'0a0 for a load access, or h'0c0 for a store access, is written to the expevt register. 4. the pc value indicating the address of the instruction in which the exception occurred is written into spc (if the exception occurred in a delay slot, the pc value indicating the address of the related delayed branch instruction is written into spc). 5. the contents of sr at the time of the exception are written to ssr. 6. the md bit in sr is set to 1 to place the sh7709s in the privileged mode. 7. the bl bit in sr is set to 1 to mask any further exception requests. 8. the register bank (rb) bit in sr is set to 1. 9. the way that generated the exception is set in the rc field in mmucr. 10. execution branches to the address obtained by adding the value of the vbr contents and h'00000100 to invoke the tlb protection violation exception handler. software (tlb protection violation handler) operations: software resolves the tlb protection violation and issues the rte (return from exception handler) instruction to terminate the handler and return to the instruction stream.
rev. 5.00, 09/03, page 76 of 760 3.5.3 tlb invalid exception a tlb invalid exception results when the virtual address is compared to a selected tlb entry address array and a match is found but the entry is not valid (the v bit is 0). tlb invalid exception processing includes both hardware and software operations. hardware operations: in a tlb invalid exception, the sh7709s hardware executes a set of prescribed operations, as follows: 1. the vpn number of the virtual address causing the exception is written to the pteh register. 2. the virtual address causing the exception is written to the tea register. 3. the way number causing the exception is written to rc in mmucr. 4. either exception code h'040 for a load access, or h'060 for a store access, is written to the expevt register. 5. the pc value indicating the address of the instruction in which the exception occurred is written to the spc. if the exception occurred in a delay slot, the pc value indicating the address of the delayed branch instruction is written to the spc. 6. the contents of sr at the time of the exception are written into ssr. 7. the mode (md) bit in sr is set to 1 to place the sh7709s in the privileged mode. 8. the block (bl) bit in sr is set to 1 to mask any further exception requests. 9. the register bank (rb) bit in sr is set to 1. 10. execution branches to the address obtained by adding the value of the vbr contents and h'00000100, and the tlb protection violation exception handler starts. software (tlb invalid exception handler) operations: the software searches the page tables in external memory and assigns the required page table entry. upon retrieving the required page table entry, software must execute the following operations: 1. write the values of the physical page number (ppn) field and the values of the protection key (pr), page size (sz), cacheable (c), dirty (d), share status (sh), and valid (v) bits of the page table entry recorded in the external memory to the ptel register. 2. if using software for way selection for entry replacement, write the desired value to the rc field in mmucr. 3. issue the ldtlb instruction to load the contents of pteh and ptel into the tlb. 4. issue the rte instruction to terminate the handler and return to the instruction stream. the rte instruction should be issued after two ldtlb instructions.
rev. 5.00, 09/03, page 77 of 760 3.5.4 initial page write exception an initial page write exception results in a write access when the virtual address and the address array of the selected tlb entry are compared and a valid entry with the appropriate access rights is found to match, but the d (dirty) bit of the entry is 0 (the page has not been written to). initial page write exception processing includes both hardware and software operations. hardware operations: in an initial page write exception, the sh7709s hardware executes a set of prescribed operations, as follows: 1. the vpn field of the virtual address causing the exception is written to the pteh register. 2. the virtual address causing the exception is written to the tea register. 3. exception code h'080 is written to the expevt register. 4. the pc value indicating the address of the instruction in which the exception occurred is written to the spc. if the exception occurred in a delay slot, the pc value indicating the address of the related delayed branch instruction is written to the spc. 5. the contents of sr at the time of the exception are written to ssr. 6. the md bit in sr is set to 1 to place the sh7709s in the privileged mode. 7. the bl bit in sr is set to 1 to mask any further exception requests. 8. the register bank (rb) bit in sr is set to 1. 9. the way that caused the exception is set in the rc field in mmucr. 10. execution branches to the address obtained by adding the value of the vbr contents and h'00000100 to invoke the user-written initial page write exception handler. software (initial page write handler) operations: the software must execute the following operations: 1. retrieve the required page table entry from external memory. 2. set the d bit of the page table entry in the external memory to 1. 3. write the value of the ppn field and the pr, sz, c, d, sh, and v bits of the page table entry in the external memory to the ptel register. 4. if using software for way selection for entry replacement, write the desired value to the rc field in mmucr. 5. issue the ldtlb instruction to load the contents of pteh and ptel into the tlb. 6. issue the rte instruction to terminate the handler and return to the instruction stream. the rte instruction should be issued after two ldtlb instructions. figure 3.11 shows the flowchart for mmu exceptions.
rev. 5.00, 09/03, page 78 of 760 start tlb miss exception initial page write exception pr check pr check yes sh = 0 and (mmucr.sv = 0 or sr.md = 0)? vpns and asids match? vpns match? no yes yes yes yes user or privileged? d = 1? c = 1? v = 1? no no user mode privileged mode no no tlb protection violation exception tlb protection violation cache access w 00/01 10 01/11 00/10 11 ww w rr rr r/w? r/w? r/w? r/w? tlb invalid exception memory access no (noncacheable) yes (cacheable) figure 3.11 mmu exception generation flowchart
rev. 5.00, 09/03, page 79 of 760 3.5.5 processing flow in event of mmu exception (same processing flow for address error) figure 3.12 shows the mmu exception signals in the instruction fetch mode. id ex ma wb id ex ma wb id ex ma wb nop nop ifid ex ma wb : exception source stage if id ex ma wb nop mmu exception handler handler transition processing = instruction fetch = instruction decode = instruction execution = memory access = write back = no operation if figure 3.12 mmu exception signals in instruction fetch
rev. 5.00, 09/03, page 80 of 760 figure 3.13 shows the mmu exception signals in the data access mode. ifid ex ifid ex ifid id ex ma wb id ex ma wb id ex ma wb nop nop ifid ex ma wb : exception source stage : stage cancellation for instruction that has begun execution if id ex ma wb nop = instruction fetch = instruction decode = instruction execution = memory access = write back = no operation mmu exception handler handler transition processing ma wb ma wb ex ma wb figure 3.13 mmu exception signals in data access 3.6 configuration of memory-mapped tlb to allow the management of tlb operations by software, the mov instruction can be used, in the privileged mode, to read and write tlb contents. the tlb is mapped to the p4 area of the virtual address space. the tlb address array (vpn, v bit, and asid) is mapped to h'f2000000 to h'f2ffffff, and the tlb data array (ppn, pr, sz, cd, s, and h bits) is mapped to h'f3000000 to h'f3ffffff. it is also possible to access the v bits in the address array from the data array. only longword access is possible, for both the address and data arrays. 3.6.1 address array the address array is mapped to h'f2000000 to h'f2ffffff. to access the address array, the 32- bit address field (for read/write access) and 32-bit data field (for write access) must be specified. the address field has the information that selects the entry to be accessed; the data field specifies the vpn, the v bit, and the asid to be written to the address array (figure 3.14 (1)).
rev. 5.00, 09/03, page 81 of 760 in the address field, specify vpn in bits 16-12 as the index address that selects the entry, w in bits 9-8 to select the way, and h'f2 in bits 31-24 to indicate access to the address array. selection of the index address depends on the mmucr.ix setting. the following 2 types of operations on the address array are possible. (1) address array read reads vpn, v bit, and asid from the entry that corresponds to the entry address and way that were specified in the address field. (2) address array write writes the data set in the data field to the entry that corresponds to the entry address and way that were specified in the address field. 3.6.2 data array the data array is assigned to h'f3000000 to h'f3ffffff. to access a data array, the 32-bit address field (for read/write operations), and 32-bit data field (for write operations) must be specified. these are specified in the general register. the address section specifies information for selecting the entry to be accessed; the data section specifies the longword data to be written to the data array (figure 3.14 (2)). in the address section, specify the entry address for selecting the entry (bits 16?12), w for selecting the way (bits 9?8: 00 is way 0, 01 is way 1, 10 is way 2, 11 is way 3), and h'f3 to indicate data array access (bits 31?24). the ix bit in mmucr indicates whether an ex-or is taken of the entry address and asid. both reading and writing use the longword of the data array specified by the index address and way number. the access size of the data array is fixed at longword.
rev. 5.00, 09/03, page 82 of 760 vpn 31 23 11110010 * * 16 (1) tlb address array access read access w 0 * vpn * 31 23 24 24 17 17 17 11110010 * ** * 16 write access read/write access w 60 * * 0 vpn 31 23 24 11110011 000 * * 16 17 address field w 0 * * 31 29 28 data field 10 ppn 8 976543210 x v xx vpn 31 16 data field (2) tlb data array access 12 10 11 8 97 12 10 11 8 97 12 10 11 8 97 12 10 11 8 97 6 * 0 0 asid 0v vpn 0 0 17 vpn 16 12 10 11 vpn 31 asid 8 97 0 * v d c sh pr sz vpn: v: w: virtual page number valid bit way (00: way 0, 01: way 1, 10: way 2, 11: way 3) asid: : address space identifier dont care bit ppn: pr: c: sh: vpn: x: w: physical page number protection key field cacheable bit share status bit virtual page number 0 for read, don t care bit for write way (00: way 0, 01: way 1, 10: way 2, 11: way 3) v: sz: d: : valid bit page-size bit dirty bit dont care bit address field data field address field * * * * * * * figure 3.14 specifying address and data for memory-mapped tlb access
rev. 5.00, 09/03, page 83 of 760 3.6.3 usage examples invalidating specific entries: specific tlb entries can be invalidated by writing 0 to the entry?s v bit. when the a bit is 1, the vpn and asid specified by the write data is compared to the vpn and asid within the tlb entry selected by the entry address and data is written to the matching way. if no match is found, there is no operation. r0 specifies the write data and r1 specifies the address. ; r0=h'1547 381c r1=h'f201 3000 ; mmucr.ix=0 ; vpn(31?17)=b'0001 0101 0100 011 vpn(11?10)=b'10 asid=b'0001 1100 ; corresponding entry association is made from the entry selected by ; the vpn(16?12)=b'1 0011 index, the v bit of the hit way is cleared to ; 0,achieving invalidation. mov.l r0,@r1 reading the data of a specific entry: this example reads the data section of a specific tlb entry. the bit order indicated in the data field in figure 3.14 (2) is read. r0 specifies the address and the data section of a selected entry is read to r1. ;r1 = h'f300 4300 vpn(16-12)=b'00100 way 3 mov.l @r0,r1 3.7 usage note the operations listed below must only be performed when the tlb is disabled or in the p1 or p2 area. any subsequent operation that accesses the p0, p3, or u0 area must take place two or more instructions after any of the below operations. 1. change sr.md or sr.bl 2. execute the ldtlb instruction 3. write to the memory-mapped tlb 4. change mmucr.
rev. 5.00, 09/03, page 84 of 760
rev. 5.00, 09/03, page 85 of 760 section 4 exception handling 4.1 overview 4.1.1 features exception handling is separate from normal program processing, and is performed by a routine separate from the normal program. in response to an exception handling request due to abnormal termination of the executing instruction, control is passed to a user-written exception handler. however, in response to an interrupt request, normal program execution continues until the end of the executing instruction. here, all exceptions other than resets and interrupts will be called general exceptions. there are thus three types of exceptions: resets, general exceptions, and interrupts. 4.1.2 register configuration table 4.1 lists the registers used for exception handling. a register with an undefined initial value should be initialized by software. table 4.1 register configuration register abbr. r/w size initial value address trapa exception register tra r/w longword undefined h'ffffffd0 exception event register expevt r/w longword power-on reset: h'000 manual reset: h'020 * 1 h'ffffffd4 interrupt event register intevt r/w longword undefined h'ffffffd8 interrupt event register2 intevt2 r longword undefined h'04000000 (h'a4000000) * 2 notes: 1. h'000 is set in a power-on reset, and h'020 in a manual reset. 2. when address translation by the mmu does not apply, the address in parentheses should be used. 4.2 exception handling function 4.2.1 exception handling flow in exception handling, the contents of the program counter (pc) and status register (sr) are saved in the saved program counter (spc) and saved status register (ssr), respectively, and execution of the exception handler is invoked from a vector address. the return from exception handler (rte) instruction is issued by the exception handler routine on completion of the routine, restoring the
rev. 5.00, 09/03, page 86 of 760 contents of pc and sr to return to the processor state at the point of interruption and the address where the exception occurred. a basic exception handling sequence consists of the following operations: 1. the contents of pc and sr are saved in spc and ssr, respectively. 2. the block (bl) bit in sr is set to 1, masking any subsequent exceptions. 3. the mode (md) bit in sr is set to 1 to place the sh7709s in privileged mode. 4. the register bank (rb) bit in sr is set to 1. 5. an exception code identifying the exception event is written to bits 11?0 of the exception event (expevt) or interrupt event (intevt or intevt2) register. 6. instruction execution jumps to the designated exception vector address to invoke the handler routine. 4.2.2 exception vector addresses the reset vector address is fixed at h'a0000000. the other three events are assigned offsets from the vector base address by software. translation look-aside buffer (tlb) miss exceptions have an offset from the vector base address of h'00000400. the vector address offset for general exception events other than tlb miss exceptions is h'00000100. the interrupt vector address offset is h'00000600. the vector base address is loaded into the vector base register (vbr) by software. the vector base address should reside in p1 or p2 fixed physical address space. figure 4.1 shows the relationship between the vector base address, the vector offset, and the vector table. vbr (vector base address) + vector offset ha000 0000 vector table figure 4.1 vector table in table 4.2, exceptions and their vector addresses are listed by exception type, instruction completion state, relative acceptance priority, relative order of occurrence within an instruction execution sequence and vector address for exceptions and their vector addresses.
rev. 5.00, 09/03, page 87 of 760 table 4.2 exception event vectors exception type current instruction exception event priority * 1 exception order vector address vector offset reset aborted power-on reset 1 ? h'a00000000 ? manual reset 1 ? h'a00000000 ? udi reset 1 ? h'a00000000 ? aborted and retried cpu address error (instruction access) 2 1 ? h'00000100 general exception events tlb miss 2 2 ? h'00000400 tlb invalid (instruction access) 2 3 ? h'00000100 tlb protection violation (instruction access) 2 4 ? h'00000100 general illegal instruction exception 2 5 ? h'00000100 illegal slot instruction exception 2 5 ? h'00000100 cpu address error (data access) 2 6 ? h'00000100 tlb miss (data access not in repeat loop) 2 7 ? h'00000400 tlb invalid (data access) 2 8 ? h'00000100 tlb protection violation (data access) 2 9 ? h'00000100 initial page write 2 10 ? h'00000100 completed unconditional trap (trapa instruction) 2 5 ? h'00000100 user breakpoint trap 2 n * 2 ? h'00000100 dma address error 2 ? ? h'00000100 completed nonmaskable interrupt 3 ? ? h'00000600 general interrupt requests external hardware interrupt 4 * 3 ? ? h'00000600 udi interrupt 4 * 3 ? ? h'00000600 notes: 1. priorities are indicated from high to low, 1 being the highest and 4 the lowest. 2. the user defines the break point traps. 1 is a break point before instruction execution and 11 is a break point after instruction execution. for an operand break point, use 11. 3. use software to specify relative priorities of external hardware interrupts and peripheral module interrupts (see section 6, interrupt controller (intc)).
rev. 5.00, 09/03, page 88 of 760 4.2.3 acceptance of exceptions processor resets and interrupts are asynchronous events unrelated to the instruction stream. all exception events are prioritized to establish an acceptance order whenever two or more exception events occur simultaneously. all general exception events occur in a relative order in the execution sequence of an instruction (i.e. execution order), but are handled at priority level 2 in instruction-stream order (i.e. program order), where an exception detected in a preceding instruction is accepted prior to an exception detected in a subsequent instruction. three general exception events (reserved instruction code exception, unconditional trap, and slot illegal instruction exception) are detected in the decode stage (id stage) of different instructions and are mutually exclusive events in the instruction pipeline. they have the same execution priority. figure 4.2 shows the order of general exception acceptance.
rev. 5.00, 09/03, page 89 of 760 if instruction n id ex ma tlb miss (data access) wb if instruction n + 1 instruction n + 2 id ex ma tlb miss (instruction access) wb if id ex ma rie (reserved instruction exception) wb pipeline sequence: tlb miss (instruction n) re-execution of instruction n 1 2 3 tlb miss (instruction n + 1) re-execution of instruction n + 1 rie (instruction n + 2) if id ex ma wb = instruction fetch = instruction decode = instruction execution = memory access = write back handling order: program order: tlb miss (instruction n+1) tlb miss (instruction n) and general illegal instruction exception (instruction n + 2) = simultaneous detection detection order: figure 4.2 example of acceptance order of general exceptions all exceptions other than a reset are detected in the pipeline id stage, and accepted at instruction boundaries. however, an exception is not accepted between a delayed branch instruction and the delay slot. a re-execution type exception detected in a delay slot is accepted before execution of the delayed branch instruction. a completion type exception detected in a delayed branch
rev. 5.00, 09/03, page 90 of 760 instruction or delay slot is accepted after execution of the delayed branch instruction. the delay slot here refers either to the next instruction after a delayed unconditional branch instruction or to the next instruction when a delayed conditional branch instruction is true. 4.2.4 exception codes table 4.3 lists the exception codes written to the expevt register (for reset or general exceptions) or the intevt and intevt2 registers (for general interrupt requests) to identify each specific exception event. table 4.3 exception codes exception type exception event exception code reset power-on reset h'000 manual reset h'020 udi reset h'000 general exception events tlb miss/invalid (read) h'040 tlb miss/invalid (write) h'060 initial page write h'080 tlb protection violation (read) h'0a0 tlb protection violation (write) h'0c0 cpu address error (read) h'0e0 cpu address error (write) h'100 unconditional trap (trapa instruction) h'160 illegal general instruction exception h'180 illegal slot instruction exception h'1a0 user breakpoint trap h'1e0 dma address error h'5c0 general interrupt requests nonmaskable interrupt h'1c0 udi interrupt h'5e0 external hardware interrupts: irl3?irl0 = 0000 h'200 irl3?irl0 = 0001 h'220
rev. 5.00, 09/03, page 91 of 760 exception type exception event exception code general interrupt requests external hardware interrupts (cont): (cont) irl3?irl0 = 0010 h'240 irl3?irl0 = 0011 h'260 irl3?irl0 = 0100 h'280 irl3?irl0 = 0101 h'2a0 irl3?irl0 = 0110 h'2c0 irl3?irl0 = 0111 h'2e0 irl3?irl0 = 1000 h'300 irl3?irl0 = 1001 h'320 irl3?irl0 = 1010 h'340 irl3?irl0 = 1011 h'360 irl3?irl0 = 1100 h'380 irl3?irl0 = 1101 h'3a0 irl3?irl0 = 1110 h'3c0 4.2.5 exception request masks when the bl bit in sr is 0, exceptions and interrupts are accepted. if a general exception event occurs when the bl bit in sr is 1, the cpu?s internal registers are set to their post-reset state, other module registers retain their contents prior to the general exception, and a branch is made to the same address (h'a0000000) as for a reset. if a general interrupt occurs when bl = 1, the request is masked (held pending) and not accepted until the bl bit is cleared to 0 by software. for reentrant exception handling, spc and ssr must be saved and the bl bit in sr cleared to 0. 4.2.6 returning from exception handling the rte instruction is used to return from exception handling. when rte is executed, the spc value is set in pc, and the ssr value in sr, and the return from exception handling is performed by branching to the spc address. if spc and ssr have been saved in external memory, set the bl bit in sr to 1, then restore spc and ssr, and issue an rte instruction.
rev. 5.00, 09/03, page 92 of 760 4.3 register descriptions there are four registers related to exception handling. these are peripheral module registers, and therefore reside in area p4. they can be accessed by specifying the address in privileged mode only. 1. the exception event register (expevt) resides at address h'ffffffd4, and contains a 12-bit exception code. the exception code set in expevt is that for a reset or general exception event. the exception code is set automatically by hardware when an exception occurs. expevt can also be modified by software. 2. the interrupt event register (intevt) resides at address h'ffffffd8, and contains a 12-bit interrupt exception code or a code indicating the interrupt priority. which is set when an interrupt occurs depends on the interrupt source (see tables 6.4 and 6.5). the exception code or interrupt priority code is set automatically by hardware when an exception occurs. intevt can also be modified by software. 3. interrupt event register 2 (intevt2) resides at address h'04000000, and contains a 12-bit exception code. the exception code set in intevt2 is that for an interrupt request. the exception code is set automatically by hardware when an exception occurs. 4. the trapa exception register (tra) resides at address h'ffffffd0, and contains 8-bit immediate data (imm) for the trapa instruction. tra is set automatically by hardware when a trapa instruction is executed. tra can also be modified by software. the bit configurations of the expevt, intevt, intevt2, and tra registers are shown in figure 4.3. 31 0 0 exception code imm 00 11 0 expevt, intevt, and intevt2 registers 8-bit immediate data in trapa instruction imm: 0: reserved bits, always read as 0 31 00 920 tra register figure 4.3 bit configurations of expevt, intevt, intevt2, and tra registers
rev. 5.00, 09/03, page 93 of 760 4.4 exception handling operation 4.4.1 reset the reset sequence is used to power up or restart the sh7709s from the initialization state. the resetp and resetm signals are sampled every clock cycle, and in the case of a power-on reset, all processing being executed (excluding the rtc) is suspended, all unfinished events are canceled, and reset processing is executed immediately. in the case of a manual reset, however, reset processing is executed after completion of any memory access being executed. the reset sequence consists of the following operations: 1. the md bit in sr is set to 1 to place the sh7709s in privileged mode. 2. the bl bit in sr is set to 1, masking any subsequent exceptions (except the nmi interrupt when the blmsk bit is 1). 3. the rb bit in sr is set to 1. 4. an encoded value of h'000 in a power-on reset or h'020 in a manual reset is written to bits 11? 0 of the expevt register to identify the exception event. 5. instruction execution jumps to the user-written exception handler at address h'a0000000. 4.4.2 interrupts an interrupt handling request is accepted on completion of the current instruction. the interrupt acceptance sequence consists of the following operations: 1. the contents of pc and sr are saved to spc and ssr, respectively. 2. the bl bit in sr is set to 1, masking any subsequent exceptions (except the nmi interrupt when the blmsk bit is 1). 3. the md bit in sr is set to 1 to place the sh7709s in privileged mode. 4. the rb bit in sr is set to 1. 5. an encoded value identifying the exception event is written to bits 11?0 of the intevt and intevt2 registers. 6. instruction execution jumps to the vector location designated by the sum of the value of the contents of the vector base register (vbr) and h'00000600 to invoke the exception handler.
rev. 5.00, 09/03, page 94 of 760 4.4.3 general exceptions when the sh7709s encounters any exception condition other than a reset or interrupt request, it executes the following operations: 1. the contents of pc and sr are saved to spc and ssr, respectively. 2. the bl bit in sr is set to 1, masking any subsequent exceptions (except the nmi interrupt when the blmsk bit is 1). 3. the md bit in sr is set to 1 to place the sh7709s in privileged mode. 4. the rb bit in sr is set to 1. 5. instruction execution jumps to the vector location designated by either the sum of the vector base address and offset h'00000400 in the vector table in a tlb miss trap, or by the sum of the vector base address and offset h'00000100 for exceptions other than tlb miss traps, to invoke the exception handler. 4.5 individual exception operations this section describes the conditions for specific exception handling, and this lsi operations. 4.5.1 resets ? power-on reset ? conditions: resetp low ? operations: expevt set to h'000, vbr and sr initialized, branch to pc = h'a0000000. initialization sets the vbr register to h'0000000. in sr, the md, rb and bl bits are set to 1 and the interrupt mask bits (i3 to i0) are set to b'1111. the cpu and on-chip peripheral modules are initialized. see the register descriptions in the relevant sections for details. a power-on reset must always be performed when powering on. a low level is output from the resetout pin, and a high level is output from the status0 and status1 pins. ? manual reset ? conditions: resetm low ? operations: expevt set to h'020, vbr and sr initialized, branch to pc = h'a0000000. initialization sets the vbr register to h'0000000. in sr, the md, rb, and bl bits are set to 1 and the interrupt mask bits (i3 to i0) are set to b'1111. the cpu and on-chip peripheral modules are initialized. see the register descriptions in the relevant sections for details. a low level is output from the resetout pin, and a high level is output from the status0 and status1 pins.
rev. 5.00, 09/03, page 95 of 760 ? udi reset ? conditions: udi reset command input (see section 22.4.3, udi reset) ? operations: expevt set to h'000, vbr and sr initialized, branch to pc = h'a0000000. initialization sets the vbr register to h'0000000. in sr, the md, rb and bl bits are set to 1 and the interrupt mask bits (i3 to i0) are set to b'1111. the cpu and on-chip peripheral modules are initialized. see the register descriptions in the relevant sections for details. table 4.4 types of reset internal state type conditions for transition to reset state cpu on-chip peripheral modules power-on reset resetp = low initialized (see register configuration in relevant sections) manual reset resetm = low initialized udi reset udi reset command input initialized 4.5.2 general exceptions ? tlb miss exception ? conditions: comparison of tlb addresses shows no address match. ? operations: the virtual address (32 bits) that caused the exception is set in tea and the corresponding virtual page number (22 bits) is set in pteh (31?10). the asid of pteh indicates the asid at the time the exception occurred. if all ways are valid, 1 is added to the rc bit in mmucr. if there is one or more invalid way, they are set by priority starting with way 0. pc and sr of the instruction that generated the exception are saved to spc and ssr, respectively. if the exception occurred during a read, h'040 is set in expevt; if the exception occurred during a write, h'060 is set in expevt. the bl, md and rb bits in sr are set to 1 and a branch occurs to pc = vbr + h'0400. to speed up tlb miss processing, the offset differs from other exceptions.
rev. 5.00, 09/03, page 96 of 760 ? tlb invalid exception ? conditions: comparison of tlb addresses shows address match but the tlb entry valid bit (v) is 0. ? operations: the virtual address (32 bits) that caused the exception is set in tea and the corresponding virtual page number (22 bits) is set in pteh (31?10). the asid of pteh indicates the asid at the time the exception occurred. the way that generated the exception is set in the rc bits in mmucr. pc and sr of the instruction that generated the exception are saved to spc and ssr, respectively. if the exception occurred during a read, h'040 is set in expevt; if the exception occurred during a write, h'060 is set in expevt. the bl, md, and rb bits in sr are set to 1 and a branch occurs to pc = vbr + h'0100. ? initial page write exception ? conditions: a hit occurred to the tlb for a store access, but the tlb entry data bit (d) is 0. this occurs for initial writes to the page registered by the load. ? operations: the virtual address (32 bits) that caused the exception is set in tea and the corresponding virtual page number (22 bits) is set in pteh (31?10). the asid of pteh indicates the asid at the time the exception occurred. the way that generated the exception is set in the rc bit in mmucr. pc and sr of the instruction that generated the exception are saved to spc and ssr, respectively. h'080 is set in expevt. the bl, md, and rb bits in sr are set to 1 and a branch occurs to pc = vbr + h'0100. ? tlb protection exception ? conditions: when a hit access violates the tlb protection information (pr bits) shown below: pr privileged mode user mode 00 only read enabled no access 01 read/write enabled no access 10 only read enabled only read enabled 11 read/write enabled read/write enabled ? operations: the virtual address (32 bits) that caused the exception is set in tea and the corresponding virtual page number (22 bits) is set in pteh (31?10). the asid of pteh indicates the asid at the time the exception occurred. the way that generated the exception is set in the rc bits in mmucr. pc and sr of the instruction that generated the exception are saved to spc and ssr, respectively. if the exception occurred during a read, h'0a0 is set in expevt; if the exception occurred during a write, h'0c0 is set in expevt. the bl, md, and rb bits in sr are set to 1 and a branch occurs to pc = vbr + h'0100.
rev. 5.00, 09/03, page 97 of 760 ? cpu address error ? conditions: a. instruction fetch from odd address (4n + 1, 4n + 3) b. word data accessed from addresses other than word boundaries (4n + 1, 4n + 3) c. longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n + 3) d. virtual space accessed in user mode in the area h'80000000 to h'ffffffff ? operations: the virtual address (32 bits) that caused the exception is set in tea. pc and sr of the instruction that generated the exception are saved to spc and ssr, respectively. if the exception occurred during a read, h'0e0 is set in expevt; if the exception occurred during a write, h'100 is set in expevt. the bl, md, and rb bits in sr are set to 1 and a branch occurs to pc = vbr + h'0100. see section 3.5.5, processing flow in event of mmu exception, for more information. ? unconditional trap ? conditions: trapa instruction executed ? operations: the exception is a processing-completion type, so pc of the instruction after the trapa instruction is saved to spc. sr from the time when the trapa instruction was executing is saved to ssr. the 8-bit immediate value in the trapa instruction is quadrupled and set in tra (9?0). h'160 is set in expevt. the bl, md, and rb bits in sr are set to 1 and a branch occurs to pc = vbr + h'0100. ? illegal general instruction exception ? conditions: a. when undefined code not in a delay slot is decoded delay branch instructions: jmp, jsr, bra, braf, bsr, bsrf, rts, rte, bt/s, bf/s undefined instruction: h'fxxx b. when a privileged instruction not in a delay slot is decoded in user mode privileged instructions: ldc, stc, rte, ldtlb, sleep; instructions that access gbr with ldc/stc are not privileged instructions and therefore do not apply. ? operations: pc and sr of the instruction that generated this instruction are saved to spc and ssr, respectively. h'180 is set in expevt. the bl, md, and rb bits in sr are set to 1 and a branch occurs to pc = vbr + h'100. when an undefined code other than h'fxxx is decoded, operation cannot be guaranteed.
rev. 5.00, 09/03, page 98 of 760 ? illegal slot instruction ? conditions: a. when undefined code in a delay slot is decoded delay branch instructions: jmp, jsr, bra, braf, bsr, bsrf, rts, rte, bt/s, bf/s b. when an instruction that rewrites pc in a delay slot is decoded instructions that rewrite pc: jmp, jsr, bra, braf, bsr, bsrf, rts, rte, bt, bf, bt/s, bf/s, trapa, ldc rm, sr, ldc.l @rm+, sr c. when a privileged instruction in a delay slot is decoded in user mode privileged instructions: ldc, stc, rte, ldtlb, sleep; instructions that access gbr with ldc/stc are not privileged instructions and therefore do not apply. ? operations: pc of the immediately preceding delay branch instruction is saved to spc. sr of the instruction that generated the exception is saved to ssr. h'1a0 is set in expevt. the bl, md, and rb bits in sr are set to 1 and a branch occurs to pc = vbr + h'0100. when an undefined instruction other than h'fxxx is decoded, operation cannot be guaranteed. ? user break point trap ? conditions: when a break condition set in the user break controller is satisfied ? operations: when a post-execution break occurs, pc of the instruction immediately after the instruction that set the break point is set in spc. if a pre-execution break occurs, pc of the instruction that set the break point is set in spc. sr when the break occurs is set in ssr. h'1e0 is set in expevt. the bl, md, and rb bits in sr are set to 1 and a branch occurs to pc = vbr + h'0100. see section 7, user break controller, for more information. ? dma address error ? conditions: a. word data accessed from addresses other than word boundaries (4n + 1, 4n + 3) b. longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n + 3) ? operations: pc of the instruction immediately after the instruction executed before the exception occurs is saved to spc. sr when the exception occurs is saved to ssr. h'5c0 is set in expevt. the bl, md, and rb bits in sr are set to 1 and a branch occurs to pc = vbr + h'0100.
rev. 5.00, 09/03, page 99 of 760 4.5.3 interrupts 1. nmi ? conditions: nmi pin edge detection ? operations: pc after the instruction that receives the interrupt is saved to spc, and sr at the point the interrupt is accepted is saved to ssr. h'01c0 is set to intevt and intevt2. the bl, md, and rb bits of the sr are set to 1 and a branch occurs to pc = vbr + h'0600. this interrupt is not masked by sr.imask and is accepted with top priority when the bl bit in sr is 0. when the bl bit is 1, the interrupt is masked. see section 6, interrupt controller (intc), for more information. 2. irl interrupts ? conditions: the value of the interrupt mask bits in sr is lower than the irl3?irl0 level and the bl bit in sr is 0. the interrupt is accepted at an instruction boundary. ? operations: the pc value after the instruction at which the interrupt is accepted is saved to spc. sr at the time the interrupt is accepted is saved to ssr. the code corresponding to the irl3?irl0 level is set in intevt and intevt2. the corresponding code is given as h'200 + [irl3?irl0] h'20. see table 6.5, for the corresponding codes. the bl, md, and rb bits in sr are set to 1 and a branch occurs to vbr + h'0600. the received level is not set in sr.imask. see section 6, interrupt controller (intc), for more information. 3. irq pin interrupts ? conditions: the irq pin is asserted, sr.imask is lower than the irq priority level, and the bl bit in sr is 0. the interrupt is accepted at an instruction boundary. ? operations: the pc value after the instruction at which the interrupt is accepted is saved to spc. sr at the point the interrupt is accepted is saved to ssr. the code corresponding to the interrupt source is set in intevt and intevt2. the bl, md, and rb bits in sr are set to 1 and a branch occurs to vbr + h'0600. the received level is not set in the interrupt mask bits in sr. see section 6, interrupt controller (intc), for more information. 4. pint pin interrupts ? conditions: the pint pin is asserted, the interrupt mask bits in sr. is lower than the pint priority level, and the bl bit in sr is 0. the interrupt is accepted at an instruction boundary. ? operations: the pc value after the instruction at which the interrupt is accepted is saved to spc. sr at the point the interrupt is accepted is saved to ssr. the code corresponding to the interrupt source is set in intevt and intevt2. the bl, md, and rb bits of sr are set to 1 and a branch occurs to vbr + h'0600. the received level is not set in the interrupt mask bits in sr. see section 6, interrupt controller (intc), for more information.
rev. 5.00, 09/03, page 100 of 760 5. on-chip peripheral interrupts ? conditions: the interrupt mask bits in sr are lower than the on-chip module (tmu, rtc, sci, irda, scif, a/d, dmac, wdt, ref) interrupt level and the bl bit in sr is 0. the interrupt is accepted at an instruction boundary. ? operations: the pc value after the instruction at which the interrupt is accepted is saved to spc. sr at the point the interrupt is accepted is saved to ssr. the code corresponding to the interrupt source is set in intevt and intevt2. the bl, md, and rb bits in sr are set to 1 and a branch occurs to vbr + h'0600. see section 6, interrupt controller (intc), for more information. 6. udi interrupt ? conditions: an udi interrupt command is input (see section 22.4.4, udi interrupt), sr.imask is lower than 15, and the bl bit in sr is 0. the interrupt is accepted at an instruction boundary. ? operations: the pc value after the instruction that accepts the interrupt is saved to spc. sr at the point the interrupt is accepted is saved to ssr. h'5e0 is set to intevt and intevt2. the bl, md, and rb bits in sr are set to 1 and a branch occurs to vbr + h'0600. see section 6, interrupt controller (intc), for more information. 4.6 cautions ? return from exception handling ? check the bl bit in sr with software. when spc and ssr have been saved to external memory, set the bl bit in sr to 1 before restoring them. ? issue an rte instruction, which sets spc in pc and ssr in sr, and causes a branch to the spc address, and return from exception handling. ? operation when exception or interrupt occurs while sr.bl = 1 ? interrupt: acceptance is suppressed until the bl bit in sr is cleared to 0. if there is an interrupt request and the reception conditions are satisfied, the interrupt is accepted after the execution of the instruction that clears the bl bit in sr to 0. in sleep or standby mode, however, the interrupt will be accepted even when the bl bit in sr is 1. ? exception: no user break point trap will occur even when the break conditions are met. when one of the other exceptions occurs, a branch is made to the fixed address of the reset (h'a0000000). in this case, the values of the expevt, spc, and ssr registers are undefined. differently from general reset processing, the resetout pin is not asserted, and reset status is output from the status0 and status1 pins.
rev. 5.00, 09/03, page 101 of 760 ? spc when exception occurs: the pc saved to spc when an exception occurs is as shown below: ? re-executing-type exceptions: pc of the instruction that caused the exception is set in spc and re-executed after return from exception handling. if the exception occurred in a delay slot, however, pc of the immediately prior delayed branch instruction is set in spc. if the condition of the conditional delayed branch instruction is not satisfied, the delay slot pc is set in spc. ? completed-type exceptions and interrupts: pc of the instruction after the one that caused the exception is set in spc. if the exception was caused by a conditional delayed branch instruction, however, the branch destination pc is set in spc. if the condition of the conditional delayed branch instruction is not satisfied, the delay slot pc is set in spc. ? initial register values after reset ? undefined registers r0_bank0/1?r7_bank0/1, r8?r15, gbr, spc, ssr, mach, macl, pr ? initialized registers vbr = h'00000000 sr.md = 1, sr.bl = 1, sr.rb = 1, sr.i3?sr.i0 = h'f. other sr bits are undefined. pc = h'a0000000 ? ensure that an exception is not generated at an rte instruction delay slot, as operation is not guaranteed in this case. ? when the bl bit in the sr register is set to 1, ensure that a tlb-related exception or address error does not occur at an ldc instruction that updates the sr register and the following instruction. this will be identified as the occurrence of multiple exceptions, and may initiate reset processing.
rev. 5.00, 09/03, page 102 of 760
rev. 5.00, 09/03, page 103 of 760 section 5 cache 5.1 overview 5.1.1 features the cache specifications are listed in table 5.1. table 5.1 cache specifications parameter specification capacity 16 kbytes structure instruction/data mixed, 4-way set associative locking way 2 and way 3 are lockable line size 16 bytes number of entries 256 entries/way write system p0, p1, p3, u0: write-back/write-through selectable replacement method least-recently-used (lru) algorithm 5.1.2 cache structure the cache mixes data and instructions and uses a 4-way set associative system. it is composed of four ways (banks), each of which is divided into an address section and a data section. each of the address and data sections is divided into 256 entries. the data section of the entry is called a line. each line consists of 16 bytes (4 bytes 4). the data capacity per way is 4 kbytes (16 bytes 256 entries), with a total of 16 kbytes in the cache as a whole (4 ways). figure 5.1 shows the cache structure.
rev. 5.00, 09/03, page 104 of 760 24 (1 + 1 + 22) bits 128 (32 4) bits 6 bits lw0 ? lw3: longword data 0 ? 3 entry 0 entry 1 entry 255 0 1 255 0 1 255 v u tag address lw0 lw1 lw2 lw3 address array (ways 0 ? 3) data array (ways 0 ? 3) lru . . . . . . . . . . . . . . . . . . figure 5.1 cache structure address array: the v bit indicates whether the entry data is valid. when the v bit is 1, data is valid; when 0, data is not valid. the u bit indicates whether the entry has been written to in write- back mode. when the u bit is 1, the entry has been written to; when 0, it has not. the address tag holds the physical address used in the external memory access. it is composed of 22 bits (address bits 31?10) used for comparison during cache searches. in the sh7709s, the top three of 32 physical address bits are used as shadow bits (see section 10, bus state controller (bsc)), and therefore in a normal replace operation the top three bits of the tag address are cleared to 0. the v and u bits are initialized to 0 by a power-on reset, but are not initialized by a manual reset. the tag address is not initialized by either a power-on or manual reset. data array: holds a 16-byte instruction or data. entries are registered in the cache in line units (16 bytes). the data array is not initialized by a power-on or manual reset. lru: with the 4-way set associative system, up to four instructions or data with the same entry address (address bits 11?4) can be registered in the cache. when an entry is registered, the lru shows which of the four ways it is recorded in. there are six lru bits, controlled by hardware. a least-recently-used (lru) algorithm is used to select the way. the way that is to be replaced on a cache miss is determined by the 6-bit lru. table 5.2 shows the correspondence between the lru bits and the way to be replaced when the cache-lock function is not used (when the cache-lock function is used, refer to section 5.2.2, cache control register 2 (ccr2)). if a bit pattern other than those listed in table 5.2 is set in the lru bits by software, the cache will not function correctly. when modifying the lru bits by software, set one of the patterns listed in table 5.2.
rev. 5.00, 09/03, page 105 of 760 the lru bits are initialized to 000000 by a power-on reset, but are not initialized by a manual reset. table 5.2 lru and way replacement (when the cache lock function is not used) lru (5?0) way to be replaced 000000, 000100, 010100, 100000, 110000, 110100 3 000001, 000011, 001011, 100001, 101001, 101011 2 000110, 000111, 001111, 010110, 011110, 011111 1 111000, 111001, 111011, 111100, 111110, 111111 0 5.1.3 register configuration table 5.3 shows details of the cache control register. table 5.3 register configuration register abbr. r/w initial value address access size cache control register ccr r/w h'00000000 h'ffffffec 32-bit cache control register 2 ccr2 r/w h'00000000 h'040000b0 (h?a40000b0) * 32-bit note: * when address translation by the mmu does not apply, the address in parentheses should be used. 5.2 register description 5.2.1 cache control register (ccr) the cache is enabled or disabled using the ce bit of the cache control register (ccr). ccr also has a cf bit (which invalidates all cache entries), and a wt and cb bits (which select either write- through mode or write-back mode). programs that change the contents of the ccr register should be placed in address space that is not cached. when updating the contents of the ccr register, always set bits 4 to 0. figure 5.2 shows the configuration of the ccr register.
rev. 5.00, 09/03, page 106 of 760 ce wt cf cb 0 1 2 3 4 5 6 31 ??? ?? ?? ? ? : reserved bits. always 0 when reading. data written here is also always 0. cf: cache flush bit. writing 1 flushes all cache entries (clears the v, u, and lru bits of all cache entries to 0). always reads 0. write-back to external memory is not performed when the cache is flushed. cb: write-back/write-through switchover bit. indicates the cache s operating mode for area p1. 1 = write-back mode, 0 = write-through mode. wt: write-through bit. indicates the cache s operating mode for area p0, u0, and p3. 1 = write-through mode, 0 = write-back mode. ce: cache enable bit. indicates whether the cache function is used. 1 = cache used, 0 = cache not used. figure 5.2 ccr register configuration 5.2.2 cache control register 2 (ccr2) ccr2 is used to control the cache-lock function and is valid only in cache locking mode. cache locking mode means that the cache lock bit (bit 12) in sr (status register) is set to 1. the cache- lock function is invalid in non-cache locking mode (the cache-lock bit is 0). when a prefetch instruction (pref) is executed in cache locking mode and a cache miss occurs, one line size of data pointed to by rn is brought to cache according to the setting of bits 9 and 8 (w3load and w3lock) and bits 1 and 0 (w2load and w2lock) in ccr2. table 5.4 shows the relationship between the bit setting and way to be replaced when a prefetch instruction is executed. when a prefetch instruction is executed and there is a cache hit, new data is not fetched and an entry which has already been valid is retained. for example, when the cache-lock, w3load, and w3lock bits are set to 1 and a prefetch instruction is executed while one line size of data pointed to by rn is already in way 0, a cache hit occurs and data is not fetched to way 3. when cache is accessed by means of instructions except for a prefetch instruction in cache locking mode, a way that is replaced by the w3lock and w2lock bits is restricted. table 5.5 shows the relationship between the bit setting of ccr2 and way to be replaced. the program which modifies the contents of ccr2 must be placed in an address space which does not cache. figure 5.3 shows the configuration of ccr2. ccr2 is a write-only register; if read, an undefined value will be returned.
rev. 5.00, 09/03, page 107 of 760 31 9 8 7 2 1 0 w2 load w3 lock w3 load w2 lock w2lock: way 2 lock bit. w2load: way 2 load bit. when w2lock = 1 & w2load = 1 & sr, cl = 1, the prefetched data will always be loaded into way2. in all other conditions the prefetched data will be loaded into the way pointed by lru. w3lock: way 3 lock bit. w3load: way 3 load bit. when w3lock = 1 & w3load = 1 & sr, cl = 1, the prefetched data will always be loaded into way3. in all other conditions the prefetched data will be loaded into the way pointed by lru. note: w2load and w3load should not be set to high at the same time. : reserved bits. figure 5.3 ccr2 register configuration whenever ccr2 bit 8 (w3lock) or bit 0 (w2lock) is high the cache is locked. the locked data will not be overwritten unless w3lock bit and w2lock bit are reset or the pref condition during dsp mode matched. during cache locking mode, the lru in table 5.2 will be replaced by tables 5.4 to 5.8. table 5.4 way replacement when pref instruction ended up in a cache miss dsp bit w3load w3lock w2load w2lock way to be replaced 0 **** depends on lru (table 5.2) 1 * 0 * 0 depends on lru (table 5.2) 1 * 0 0 1 depends on lru (table 5.6) 101 * 0 depends on lru (table 5.7) 1 0 1 0 1 depends on lru (table 5.8) 10 * 11way 2 1110 * way 3 * : don't care do not set as w3load=1 and also w2load=1
rev. 5.00, 09/03, page 108 of 760 table 5.5 way replacement when instructions except for pref instruction ended up in a cache miss dsp bit w3load w3lock w2load w2lock way to be replaced 0 **** depends on lru (table 5.2) 1 * 0 * 0 depends on lru (table 5.2) 1 * 0 * 1 depends on lru (table 5.6) 1 * 1 * 0 depends on lru (table 5.7) 1 * 1 * 1 depends on lru (table 5.8) * : don't care do not set as w3load=1 and also w2load=1 table 5.6 lru and way replacement (when w2lock=1) lru (5?0) way to be replaced 000000, 000001, 000100, 010100, 100000, 100001, 110000, 110100 3 000011, 000110, 000111, 001011, 001111, 010110, 011110, 011111 1 101001, 101011, 111000, 111001, 111011, 111100, 111110, 111111 0 table 5.7 lru and way replacement (when w3lock=1) lru (5?0) way to be replaced 000000, 000001, 000011, 001011, 100000, 100001, 101001, 101011 2 000100, 000110, 000111, 001111, 010100, 010110, 011110, 011111 1 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 0 table 5.8 lru and way replacement (when w2lock=1 and w3lock=1) lru (5?0) way to be replaced 000000, 000001, 000011, 000100, 000110, 000111, 001011, 001111, 010100, 010110, 011110, 011111 1 100000, 100001, 101001, 101011, 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 0
rev. 5.00, 09/03, page 109 of 760 5.3 cache operation 5.3.1 searching the cache if the cache is enabled, whenever instructions or data in memory are accessed the cache will be searched to see if the desired instruction or data is in the cache. figure 5.4 illustrates the method by which the cache is searched. the cache is a physical cache and holds physical addresses in its address section. entries are selected using bits 11?4 of the address (virtual) of the access to memory and the address tag of that entry is read. in parallel to reading of the address tag, the virtual address is translated to a physical address in the mmu. the physical address after translation and the physical address read from the address section are compared. the address comparison uses all four ways. when the comparison shows a match and the selected entry is valid (v = 1), a cache hit occurs. when the comparison does not show a match or the selected entry is not valid (v = 0), a cache miss occurs. figure 5.4 shows a hit on way 1.
rev. 5.00, 09/03, page 110 of 760 0 1 255 v u tag address lw0 lw1 lw2 lw3 ways 0 ? 3 ways 0 ? 3 31 12 11 4 3 2 1 0 virtual address cmp0 cmp1 cmp2 cmp3 physical address cmp0: comparison circuit 0 cmp1: comparison circuit 1 cmp2: comparison circuit 2 cmp3: comparison circuit 3 hit signal 1 entry selection longword (lw) selection mmu figure 5.4 cache search scheme (normal mode)
rev. 5.00, 09/03, page 111 of 760 5.3.2 read access read hit: in a read access, instructions and data are transferred from the cache to the cpu. the transfer unit is 32 bits. the lru is updated. read miss: an external bus cycle starts and the entry is updated. the way replaced is the one least recently used. entries are updated in 16-byte units. when the desired instruction or data that caused the miss is loaded from external memory to the cache, the instruction or data is transferred to the cpu in parallel with being loaded to the cache. when it is loaded in the cache, the u bit is cleared to 0 and the v bit is set to 1. 5.3.3 prefetch operation prefetch hit: the lru will be updated to correctly indicate the latest way to have been hit. other contents of the cache will remain unchanged. neither instructions nor data are transferred to the cpu. prefetch miss: neither instructions nor data are transferred to the cpu, and way replacement takes place as shown in table 5.4. all other action is the same as for a read miss. 5.3.4 write access write hit: in a write access in the write-back mode, the data is written to the cache and the u bit of the entry written is set to 1. writing occurs only to the cache; no external memory write cycle is issued. in the write-through mode, the data is written to the cache and an external memory write cycle is issued. write miss: in the write-back mode, an external write cycle starts when a write miss occurs, and the entry is updated. the way to be replaced is shown in table 5.5. when the u bit of the entry to be replaced is 1, the cache fill cycle starts after the entry is transferred to the write-back buffer. the write-back unit is 16 bytes. data is written to the cache and the u bit is set to 1. after the cache completes its fill cycle, the write-back buffer writes back the entry to the memory. in the write-through mode, no write to cache occurs in a write miss; the write is only to the external memory. 5.3.5 write-back buffer when the u bit of the entry to be replaced in the write-back mode is 1, it must be written back to the external memory. to increase performance, the entry to be replaced is first transferred to the write-back buffer and fetching of new entries to the cache takes priority over writing back to the external memory. during the write back cycles, the cache can be accessed. the write-back buffer can hold one line of the cache data (16 bytes) and its physical address. figure 5.5 shows the configuration of the write-back buffer.
rev. 5.00, 09/03, page 112 of 760 longword 0 longword 1 longword 2 longword 3 pa (31 ? 4) pa (31 ? 4): longword 0 ? 3: physical address written to external memory the line of cache data to be written to external memory figure 5.5 write-back buffer configuration 5.3.6 coherency of cache and external memory use software to ensure coherency between the cache and the external memory. when memory shared by this lsi and another device is placed in an address space to be cached, the memory allocation cache is manipulated if necessary and a write back should be performed by invalidating the entry. this is also applied to memory shared by the cpu and dmac in this lsi. 5.4 memory-mapped cache to allow software management of the cache, cache contents can be read and written by means of mov instructions in the privileged mode. the cache is mapped onto the p4 area in virtual address space. the address array is mapped onto addresses h'f0000000 to h'f0ffffff, and the data array onto addresses h'f1000000 to h'f1ffffff. only longword can be used as the access size for the address array and data array, and instruction fetches cannot be performed. 5.4.1 address array the address array is mapped to h'f0000000 to h'f0ffffff. the 32-bit address field (for read/write accessed) and 32-bit data field (for write access) must be specified to access an element of the address array. the address field specifies information that selects the entry to be accessed; the data field specifies the tag address, v bit, u bit, and lru bits to be written to the address array (figure 5.6 (1)). in the address field, specify the entry's address in bits 11-4 to select the entry, w in bits 13-12 to select the way, the a bit (bit 3) to specify an associative operation, and h'f0 in bits 31-24 to indicate access to the address array. settings for the w bits (13-12) are as follows: 00 is way 0, 01 is way 1, 10 is way 2, and 11 is way 3. in the data field, specify the tag address in bits 31-10, lru in bits 9-4, u bit in bit 1, and v bit in bit 0. the upper 3 bits (bit 31-29) of the tag address must always be 0.
rev. 5.00, 09/03, page 113 of 760 the following three operations on the address array are possible. (1) address array read reads the tag address, lru, u bit, and v bit from the entry that corresponds to the entry address and w`ay that were specified in the address field. no associative operation will be performed, regardless of the value of the associative bit (the a bit). (2) address array write (without associative operation) writes the tag address, lru, u bit, and v bit specified in the data field to the entry that corresponds to the entry address and way that were specified in the address field. the associative bit (a bit) of the address field must be set to 0. an attempt to write to a cache line for which both the u bit and v bit are set results in a write-back for that cache line. the tag address, lru, u bit, and v bit specified in the data field are then written. note that, when a 0 is written to the v bit, a 0 should always be written to the u bit of the same entry, too. (3) address array write (with associative operation) the associative bit (a bit) in the address field indicates whether the addresses are compared during writing. with the a bit set to 1, all 4 ways for the entry specified in the address field will be compared to the tag address specified in the data field for a match. the values of the u bit and v bit specified in the data field will be written to the way that has a hit. however, the tag address and the lru will not be changed. if no way receives a hit, writing does not take place and the result is no operation. this operation is used to invalidate the address specification for a cache. write back will take place when the u bit of the entry that received a hit is 1. note that, when a 0 is written to the v bit, a 0 should always be written to the u bit of the same entry, too. 5.4.2 data array the address array is mapped to h'f1000000 to h'f1ffffff. to access an element of the data array, the 32-bit address field (for read/write access) and 32-bit data field (for write access) must be specified. the address field specifies the information that selects the entry to be accessed; the data field specifies the longword data to be written to the data array. in the address field, specify the entry's address in bits 11-4, l in bits 3-2 to indicate the longword's position within a line (which consists of 16 bytes), w in bits 13-12 to select the way, and h'f1 in bits 31-24 to indicate access to the data array. the l bits (3-2) specification is in the following form: 00 is longword 0, 01 is longword 1, 10 is longword 2, and 11 is longword 3. settings for the w bits (13-12) are as follows: 00 is way 0, 01 is way 1, 10 is way 2, and 11 is way 3. since access is not allowed crossing longword boundaries, always set 00 in bits 1-0 of the address field.
rev. 5.00, 09/03, page 114 of 760 the following two operations on the data array are possible. note that these operations will not change the information in the address array. (1) data array read reads the data at the position selected by the l bits (3-2) of the address field from the entry that corresponds to the entry address and way that were specified in the address field. (2) data array write writes the longword data set in the data field into the entry that corresponds to the entry address and way that were specified in the address field. the longword data will be written to the entry at the position selected by the l bits (3-2) of the address field. 1. address array access address specification read access write access data specification (both read and write accesses) 2. data array access (both read and write accesses) address specification 31 24 23 14 13 12 11 4 3 0 1111 0000 2 2 2 2 2 2 w entry address 31 24 23 14 13 12 11 4 3 0 1111 0000 w entry address 2 a 31 30 29 10 4 3 0 lru 2 x 000 x 9 address tag (28 ? 10) uv 1 31 24 23 14 13 12 11 4 3 0 1111 0001 w entry address 0 0 1 2 l data specification 31 0 longword x: 0 for read, dont care for write 2 : dont care bit 0 2 figure 5.6 specifying address and data for memory-mapped cache access
rev. 5.00, 09/03, page 115 of 760 5.4.3 examples of usage (1) invalidating a specific entry a specific cache entry can be invalidated by accessing the allocated memory cache and writing a 0 to the entry?s u and v bits. the a bit is cleared to 0, and an address is specified for the entry address and the way. if the u bit of the way of the entry in question was set to 1, the entry is written back and the v and u bits specified by the write data are written to. in the following example, the write data is specified in r0 and the address is specified in r1. ; r0 = h'0000 0000 lru = h'000 ,u=0,v=0 ; r1 = h'f000 1080, way = 1, entry = h'08 ,a=0 ; mov.l r0, @r1 to invalidate all entries and ways, write 0 to the following addresses. addresses f000 0000 f000 0010 f000 0020 : f000 3ff0 this involves a total of 1,024 writes. the above operation should be performed using a non-cacheable area. (2) invalidating a specific address a specific address can be invalidated by writing a 0 to the entry?s u and v bits. when the a bit is 1, the tag address specified by the write data is compared to the tag address within the cache selected by the entry address. if the tag addresses match, data is written to the memory at that address. if no match is found, no operation is carried out. if the entry?s u bit is 1 at that time, the entry is written back. ; r0 = h'0110 0010; tag address = b'0000 0001 0001 0000 0000 00 ,u=0, v=0 ; r1 = h'f000 0088; address array access, entry = h'08 ,a=1 ; mov.l r0, @r1
rev. 5.00, 09/03, page 116 of 760 in the following example, an address (32-bit) to be purged is specified in r0. mov.l #h'00000ff0, r1 ; and r0, r1 ; the entry address is fetched. mov.l #h'f0000008, r2 ; or r1, r2 ; the start is set to h'f0 and the a bit to 1. mov.l #h'1ffffc00, r3 ; and r0, r3 ; the tag address is fetched .u=v=0. mov.l r3, @r2 ; associative purge. the above operation should be performed using a non-cacheable area. (3) reading data from a specific entry this example reads the data section of a specific entry. the longword in the data field of the data array in figure 5.6 is read to the register. ; r0 = h'f100 004c; data array access, entry = h'04, ; way = 0, longword address = 3 ; mov.l r0, @r1 ; longword 3 is read.
rev. 5.00, 09/03, page 117 of 760 section 6 interrupt controller (intc) 6.1 overview the interrupt controller (intc) ascertains the priority of interrupt sources and controls interrupt requests to the cpu. the intc registers set the order of priority of each interrupt, allowing the user to process interrupt requests according to the user-set priority. 6.1.1 features the intc has the following features: ? 16 levels of interrupt priority can be set: by setting the five interrupt-priority registers, the priorities of on-chip peripheral module, irq, and pint interrupts can be selected from 16 levels for individual request sources. ? nmi noise canceler function: an nmi input-level bit indicates the nmi pin state. by reading this bit in the interrupt exception service routine, the pin state can be checked, enabling it to be used as a noise canceler. ? external devices can be notified that an interrupt has been received ( irqout ): when the sh7709s has released the bus, the external bus master can be notified that an external interrupt, an on-chip peripheral module interrupt, or a memory refresh request has occurred, enabling the bus to be requested.
rev. 5.00, 09/03, page 118 of 760 6.1.2 block diagram figure 6.1 shows a block diagram of the intc. ref irda dmac icr input/output control com- parator priority identifier 3 4 6 16 interrupt request sr ipra ipre irl3 irl0 nmi irq0 irq5 pint0 pint15 irqout : timer unit : realtime clock unit : serial communication interface : serial communication interface (with irda) : serial communication interface (with fifo) : watchdog timer : refresh requests in the bus state controller : interrupt control register : interrupt priority registers a ? e : status register : direct memory access controller : analog-to-digital converter : user-debugging interface legend tmu rtc sci irda scif wdt ref icr ipra ipre sr dmac adc udi (interrupt request) scif tmu (interrupt request) (interrupt request/ ipr cpu internal bus bus interface 2 1 0 (interrupt request) (interrupt request) rtc wdt (interrupt request) (interrupt request) irls3 irls0 4 sci (interrupt request) adc (interrupt request) intc udi (interrupt request) refresh request) figure 6.1 block diagram of intc
rev. 5.00, 09/03, page 119 of 760 6.1.3 pin configuration table 6.1 shows the intc pin configuration. table 6.1 intc pins name abbreviation i/o description nonmaskable interrupt input pin nmi i input of interrupt request signal, not maskable by the interrupt mask bits in sr. interrupt input pins irq5?irq0 irl3 ? irl0 irls3 - irls0 i input of interrupt request signals, maskable by the interrupt mask bits in sr. port interrupt input pins pint0?pint15 i input of port interrupt request signals, maskable by the interrupt mask bits in sr. bus request output pin irqout o output of signal that notifies external devices that an interrupt source or memory refresh has occurred
rev. 5.00, 09/03, page 120 of 760 6.1.4 register configuration the intc has the 12 registers listed in table 6.2. table 6.2 intc registers name abbr. r/w initial value * 1 address access size interrupt control register 0 icr0 r/w * 2 h'fffffee0 16 interrupt control register 1 icr1 r/w h'0000 h'04000010 (h'a4000010) * 3 16 interrupt control register 2 icr2 r/w h'0000 h'04000012 (h'a4000012) * 3 16 pint interrupt enable register pinter r/w h'0000 h'04000014 (h'a4000014) * 3 16 interrupt priority register a ipra r/w h'0000 h'fffffee2 16 interrupt priority register b iprb r/w h'0000 h'fffffee4 16 interrupt priority register c iprc r/w h'0000 h'04000016 (h'a4000016) * 3 16 interrupt priority register d iprd r/w h'0000 h'04000018 (h'a4000018) * 3 16 interrupt priority register e ipre r/w h'0000 h'0400001a (h'a400001a) * 3 16 interrupt request register 0 irr0 r/w h'00 h'04000004 (h'a4000004) * 3 8 interrupt request register 1 irr1 r h'00 h'04000006 (h'a4000006) * 3 8 interrupt request register 2 irr2 r h'00 h'04000008 (h'a4000008) * 3 8 notes: 1. initialized by a power-on or manual reset. 2. h'8000 when the nmi pin is high, h'0000 when the nmi pin is low. 3. when address translation by the mmu does not apply, the address in parentheses should be used.
rev. 5.00, 09/03, page 121 of 760 6.2 interrupt sources there are five types of interrupt sources: nmi, irq, irl,pint, and on-chip peripheral modules. each interrupt has a priority level (0?16), with 0 the lowest and 16 the highest. priority level 0 masks an interrupt. 6.2.1 nmi interrupt the nmi interrupt has the highest priority level of 16. when the blmsk bit in the interrupt control register (icr1) is 1 or the bl bit in the status register (sr) is 0, nmi interrupts are accepted when the mai bit in the icr1 register is 0. nmi interrupts are edge-detected. in sleep or standby mode, the interrupt is accepted regardless of the bl setting. the nmi edge select bit (nmie) in the interrupt control register 0 (icr0) is used to select either rising or falling edge detection. when the nmie bit in the icr0 register is changed, an nmi interrupt is not detected for 20 cycles after changing icr0. nmie to avoid a false detection of nmi. nmi interrupt exception handling does not affect the interrupt mask level bits (i3?i0) in the status register (sr). when the bl bit is land the blmsk bit in the icr1 register is set to 1 and only nmi interrupts are accepted, the spc register and ssr register are updated by the nmi interrupt handler, making it impossible to return to the original processing from exception handling initiated prior to the nmi interrupt. use should therefore be restricted to cases where return is not necessary. it is possible to wake the chip up from the standby state with an nmi interrupt (except when the mai bit in the icr1 register is set to 1). 6.2.2 irq interrupts irq interrupts are input by level or edge from pins irq0?irq5. the priority level can be set by interrupt priority registers c?d (iprc?iprd) in a range from 0 to 15. when using edge-sensing for irq interrupts, clear the interrupt source by having software read 1 from the corresponding bit in irr0, then write 0 to the bit. when the icr1 register is rewritten, irq interrupts may be mistakenly detected, depending on the pin states. to prevent this, rewrite the register while interrupts are masked, then release the mask after clearing the illegal interrupt by writing 0 to interrupt request register 0 (irr0). edge input interrupt detection requires input of a pulse width of more than two cycles on a peripheral clock (p ) basis. the interrupt mask bits (i3?i0) in the status register (sr) are not affected by irq interrupt handling.
rev. 5.00, 09/03, page 122 of 760 interrupts irq4?irq0 can wake the chip up from the standby state when the relevant interrupt level is higher than the setting of i3?i0 in the sr register (but only when the rtc 32-khz oscillator is used). if the irq edge is input immediately before the cpu enters the standby mode (during the period between when the cpu executes a sleep instruction and when status0 becomes high level), the interrupt may not be detected. however, the interrupt will be accepted correctly if the irq edge is re-input after the cpu has entered the standby mode (when status0 is high level). in addition, the interrupt may not be detected if the irq edge is input during frequency change processing (wdt count). 6.2.3 irl interrupts irl interrupts are input by level at pins irl3 ? irl0 and irls3 ? irls0 . irls3 ? irls0 are enabled when the irqlvl bit and irlsen bit in interrupt control register 1 (icr1) are both 1. the priority level is the higher level indicated by pins irl3 ? irl0 and irls3 ? irls0 . an irl3 ? irl0 / irls3 ? irls0 value of 0 (0000) indicates the highest-level interrupt request (interrupt priority level 15). a value of 15 (1111) indicates no interrupt request (interrupt priority level 0). figure 6.2 shows an example of irl interrupt connection. table 6.3 shows irl / irls pins and interrupt levels. interrupt request priority encoder irl3 to irl0 4 sh7709s irl3 to irl0 interrupt request priority encoder irls3 to irls0 4 irls3 to irls0 figure 6.2 example of irl interrupt connection
rev. 5.00, 09/03, page 123 of 760 table 6.3 irl3 irl3 irl3 irl3 ? irl0 irl0 irl0 irl0 / irls3 irls3 irls3 irls3 ? irls0 irls0 irls0 irls0 pins and interrupt levels irl3/ irl3/ irl3/ irl3/ irls3 irls3 irls3 irls3 irl2/ irl2/ irl2/ irl2/ irls2 irls2 irls2 irls2 irl1/ irl1/ irl1/ irl1/ irls1 irls1 irls1 irls1 irl0/ irl0/ irl0/ irl0/ irls0 irls0 irls0 irls0 interrupt priority level interrupt request 0 0 0 0 15 level 15 interrupt request 0 0 0 1 14 level 14 interrupt request 0 0 1 0 13 level 13 interrupt request 0 0 1 1 12 level 12 interrupt request 0 1 0 0 11 level 11 interrupt request 0 1 0 1 10 level 10 interrupt request 0 1 1 0 9 level 9 interrupt request 0 1 1 1 8 level 8 interrupt request 1 0 0 0 7 level 7 interrupt request 1 0 0 1 6 level 6 interrupt request 1 0 1 0 5 level 5 interrupt request 1 0 1 1 4 level 4 interrupt request 1 1 0 0 3 level 3 interrupt request 1 1 0 1 2 level 2 interrupt request 1 1 1 0 1 level 1 interrupt request 1 1 1 1 0 no interrupt request a noise-cancellation feature is built in, and the irl interrupt is not detected unless the levels sampled at every peripheral module clock cycle remain unchanged for two consecutive cycles, so that no transient level on the irl / irls pin change is detected. in standby mode, as the peripheral clock is stopped, noise cancellation is performed using the 32-khz clock for the rtc instead. therefore when the rtc is not used, interruption by means of irl interrupts cannot be performed in standby mode. the priority level of the irl interrupt must not be lowered until the interrupt is accepted and interrupt handling starts. correct operation cannot be guaranteed if the level is not maintained. however, the priority level can be changed to a higher one. the interrupt mask bits (i3?i0) in the status register (sr) are not affected by irl / irls interrupt handling. when the interrupt level of the irl interrupt is higher than the level set by the i3-i0 bits in the sr, the irl interrupt can be used to recover from standby mode (however, this only applies when the rtc is used for 32-khz oscillator).
rev. 5.00, 09/03, page 124 of 760 6.2.4 pint interrupts pint interrupts are input by level from pins pint0?pint15. the priority level can be set by interrupt priority register d (iprd) in a range from 0 to 15, in groups of pint0?pint7 and pint8?pint15. the pint0/1 interrupt level should be held until the interrupt is accepted and interrupt handling is started. correct operation cannot be guaranteed if the level is not maintained. the interrupt mask bits (i3?i0) in the status register (sr) are not affected by pint interrupt handling. pint0/1 interrupts can wake the chip up from the standby state when the relevant interrupt level is higher than the setting of i3?i0 in the sr register (but only when the rtc 32-khz oscillator is used). 6.2.5 on-chip peripheral module interrupts on-chip peripheral module interrupts are generated by the following ten modules: ? timer unit (tmu) ? realtime clock (rtc) ? serial communication interfaces (sci, irda, scif) ? bus state controller (bsc) ? watchdog timer (wdt) ? direct memory access controller (dmac) ? analog-to-digital converter (adc) ? user-debugging interface (udi) not every interrupt source is assigned a different interrupt vector. sources are reflected in the interrupt event registers (intevt and intevt2). it is easy to identify sources by using the value of the intevt or intevt2 register as a branch offset. a priority level (from 0 to 15) can be set for each module except udi by writing to interrupt priority registers a, b, and e (ipra, iprb, and ipre). the priority level of the udi interrupt is 15 (fixed). the interrupt mask bits (i3?i0) in the status register are not affected by on-chip peripheral module interrupt handling. tmu and rtc interrupts can wake the chip up from the standby state when the relevant interrupt level is higher than the setting of i3?i0 in the sr register (but only when the rtc 32-khz oscillator is used).
rev. 5.00, 09/03, page 125 of 760 6.2.6 interrupt exception handling and priority tables 6.4 and 6.5 list the codes for the interrupt event registers (intevt and intevt2), and the order of interrupt priority. each interrupt source is assigned a unique code. the start address of the interrupt service routine is common to each interrupt source. this is why, for instance, the value of intevt or intevt2 is used as offset at the start of the interrupt service routine and branched to in order to identify the interrupt source. the priority of the on-chip peripheral module, irq, and pint interrupts is set within priority levels 0?15 as required by using interrupt priority registers a?e (ipra?ipre). the priority of the on-chip peripheral module, irq, and pint interrupts is set to 0 by a reset. when the priorities of multiple interrupt sources are set to the same level and such interrupts are generated simultaneously, they are handled according to the default order shown in tables 6.4 and 6.5.
rev. 5.00, 09/03, page 126 of 760 table 6.4 interrupt exception handling sources and priority (irq mode) interrupt source intevt code (intevt2 code) interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority nmi h'1c0 (h'1c0) 16 ? ? high udi h'5e0 (h'5e0) 15 ? ? irq irq0 h'200?3c0 * (h'600) 0?15 (0) iprc (3?0) ? irq1 h'200?3c0 * (h'620) 0?15 (0) iprc (7?4) ? irq2 h'200?3c0 * (h'640) 0?15 (0) iprc (11?8) ? irq3 h'200?3c0 * (h'660) 0?15 (0) iprc (15?12) ? irq4 h'200?3c0 * (h'680) 0?15 (0) iprd (3?0) ? irq5 h'200?3c0 * (h'6a0) 0?15 (0) iprd (7?4) ? pint pint0?7 h'200?3c0 * (h'700) 0?15 (0) iprd (15?12) ? pint8?15 h'200?3c0 * (h'720) 0?15 (0) iprd (11?8) ? dmac dei0 h'200?3c0 * (h'800) 0?15 (0) ipre (15?12) high dei1 h'200?3c0 * (h'820) dei2 h'200?3c0 * (h'840) dei3 h'200?3c0 * (h'860) low irda eri1 h'200?3c0 * (h'880) 0?15 (0) ipre (11?8) high rxi1 h'200?3c0 * (h'8a0) bri1 h'200?3c0 * (h'8c0) txi1 h'200?3c0 * (h'8e0) low scif eri2 h'200?3c0 * (h'900) 0?15 (0) ipre (7?4) high rxi2 h'200?3c0 * (h'920) bri2 h'200?3c0 * (h'940) txi2 h'200?3c0 * (h'960) low adc adi h'200?3c0 * (h'980) 0?15 (0) ipre (3?0) ? tmu0 tuni0 h'400 (h'400) 0?15 (0) ipra (15?12) ? tmu1 tuni1 h'420 (h'420) 0?15 (0) ipra (11?8) ? tmu2 tuni2 h'440 (h'440) 0?15 (0) ipra (7?4) high ticpi2 h'460 (h'460) low low
rev. 5.00, 09/03, page 127 of 760 interrupt source intevt code (intevt2 code) interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority rtc ati h'480 (h'480) 0?15 (0) ipra (3?0) high high pri h'4a0 (h'4a0) cui h'4c0 (h'4c0) low sci eri h'4e0 (h'4e0) 0?15 (0) iprb (7?4) high rxi h'500 (h'500) txi h'520 (h'520) tei h'540 (h'540) low wdt iti h'560 (h'560) 0?15 (0) iprb (15?12) ? ref rcmi h'580 (h'580) 0?15 (0) iprb (11?8) high rovi h'5a0 (h'5a0) low low note: * the code corresponding to an interrupt level shown in table 6.6 is set.
rev. 5.00, 09/03, page 128 of 760 table 6.5 interrupt exception handling sources and priority (irl mode) interrupt source intevt code (intevt2 code) interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority nmi h'1c0 (h'1c0) 16 ? ? high udi h'5e0 (h'5e0) 15 ? ? irl irl(3:0) * 2 = 0000 h'200 (h'200) 15 ? ? irl(3:0) * 2 = 0001 h'220 (h'220) 14 ? ? irl(3:0) * 2 = 0010 h'240 (h'240) 13 ? ? irl(3:0) * 2 = 0011 h'260 (h'260) 12 ? ? irl(3:0) * 2 = 0100 h'280 (h'280) 11 ? ? irl(3:0) * 2 = 0101 h'2a0 (h'2a0) 10 ? ? irl(3:0) * 2 = 0110 h'2c0 (h'2c0) 9 ? ? irl(3:0) * 2 = 0111 h'2e0 (h'2e0) 8 ? ? irl(3:0) * 2 = 1000 h'300 (h'300) 7 ? ? irl(3:0) * 2 = 1001 h'320 (h'320) 6 ? ? irl(3:0) * 2 = 1010 h'340 (h'340) 5 ? ? irl(3:0) * 2 = 1011 h'360 (h'360) 4 ? ? irl(3:0) * 2 = 1100 h'380 (h'380) 3 ? ? irl(3:0) * 2 = 1101 h'3a0 (h'3a0) 2 ? ? irl(3:0) * 2 = 1110 h'3c0 (h'3c0) 1 ? ? irq irq4 h'200?3c0 * 1 (h'680) 0?15 (0) iprd (3?0) ? irq5 h'200?3c0 * 1 (h'6a0) 0?15 (0) iprd (7?4) ? pint pint0?7 h'200?3c0 * 1 (h'700) 0?15 (0) iprd (15?12) ? pint8?15 h'200?3c0 * 1 (h'720) 0?15 (0) iprd (11?8) ? dmac dei0 h'200?3c0 * 1 (h'800) 0?15 (0) ipre (15?12) high dei1 h'200?3c0 * 1 (h'820) dei2 h'200?3c0 * 1 (h'840) dei3 h'200?3c0 * 1 (h'860) low irda eri1 h'200?3c0 * 1 (h'880) 0?15 (0) ipre (11?8) high rxi1 h'200?3c0 * 1 (h'8a0) bri1 h'200?3c0 * 1 (h'8c0) txi1 h'200?3c0 * 1 (h'8e0) low low
rev. 5.00, 09/03, page 129 of 760 interrupt source intevt code (intevt2 code) interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority scif eri2 h'200?3c0 * 1 (h'900) 0?15 (0) ipre (7?4) high high rxi2 h'200?3c0 * 1 (h'920) bri2 h'200?3c0 * 1 (h'940) txi2 h'200?3c0 * 1 (h'960) low adc adi h'200?3c0 * 1 (h'980) 0?15 (0) ipre (3?0) ? tmu0 tuni0 h'400 (h'400) 0?15 (0) ipra (15?12) ? tmu1 tuni1 h'420 (h'420) 0?15 (0) ipra (11?8) ? tmu2 tuni2 h'440 (h'440) 0?15 (0) ipra (7?4) high ticpi2 h'460 (h'460) low rtc ati h'480 (h'480) 0?15 (0) ipra (3?0) high pri h'4a0 (h'4a0) cui h'4c0 (h'4c0) low sci eri h'4e0 (h'4e0) 0?15 (0) iprb (7?4) high rxi h'500 (h'500) txi h'520 (h'520) tei h'540 (h'540) low wdt iti h'560 (h'560) 0?15 (0) iprb (15?12) ? ref rcmi h'580 (h'580) 0?15 (0) iprb (11?8) high rovi h'5a0 (h'5a0) low low notes: 1. the code corresponding to an interrupt level shown in table 6.6 is set. 2. when irls3 ? irls0 are enabled, irl is the higher level of irl3 ? irl0 and irls3 ? irls0 .
rev. 5.00, 09/03, page 130 of 760 table 6.6 interrupt levels and intevt codes interrupt level intevt code 15 h'200 14 h'220 13 h'240 12 h'260 11 h'280 10 h'2a0 9h'2c0 8h'2e0 7 h'300 6 h'320 5 h'340 4 h'360 3 h'380 2h'3a0 1h'3c0
rev. 5.00, 09/03, page 131 of 760 6.3 intc registers 6.3.1 interrupt priority registers a to e (ipra?ipre) interrupt priority registers a to e (ipra to ipre) are 16-bit readable/writable registers in which priority levels from 0 to 15 are set for on-chip peripheral module, irq, and pint interrupts. these registers are initialized to h'0000 by a power-on reset or manual reset, but are not initialized in standby mode. bit: 15 14 13 12 11 10 9 8 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w table 6.7 lists the relationship between the interrupt sources and the ipra?ipre bits. table 6.7 interrupt request sources and ipra?ipre register bits 15 to 12 bits 11 to 8 bits 7 to 4 bits 3 to 0 ipra tmu0 tmu1 tmu2 rtc iprb wdt ref sci0 reserved * iprc irq3 irq2 irq1 irq0 iprd pint0 to pint7 pint8 to pint15 irq5 irq4 ipre dmac irda scif adc note: * always read as 0. only 0 should be written. as shown in table 6.7, on-chip peripheral module, irq, or pint interrupts are assigned to four 4- bit groups in each register. these 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0) are set with values from h'0 (0000) to h'f (1111). setting h'0 means priority level 0 (masking is requested); h'f is priority level 15 (the highest level). a reset initializes ipra?ipre to h'0000.
rev. 5.00, 09/03, page 132 of 760 6.3.2 interrupt control register 0 (icr0) icr0 is a register that sets the input signal detection mode of external interrupt input pin nmi, and indicates the input signal level at the nmi pin. this register is initialized to h'0000 or h'8000 by a power-on reset or manual reset, but is not initialized in standby mode. bit: 15 14 13 12 11 10 9 8 nmil??????nmie initial value: 0/1 * 0000000 r/w:rrrrrrrr/w bit:76543210 ???????? initial value:00000000 r/w:rrrrrrrr note: * 1 when nmi input is high, 0 when nmi input is low. bit 15?nmi input level (nmil): sets the level of the signal input at the nmi pin. this bit can be read to determine the nmi pin level. this bit cannot be modified. bit 15: nmil description 0 nmi input level is low 1 nmi input level is high bit 8?nmi edge select (nmie): selects whether the falling or rising edge of the interrupt request signal at the nmi pin is detected. bit 8: nmie description 0 interrupt request is detected on falling edge of nmi input 1 interrupt request is detected on rising edge of nmi input bits 14 to 9 and 7 to 0?reserved: these bits are always read as 0. the write value should always be 0.
rev. 5.00, 09/03, page 133 of 760 6.3.3 interrupt control register 1 (icr1) icr1 is a 16-bit register that specifies the detection mode for external interrupt input pins irq0 to irq5 individually: rising edge, falling edge, or low level. this register is initialized to h'4000 by a power-on reset or manual reset, but is not initialized in standby mode. bit: 15 14 13 12 11 10 9 8 mai irqlvl blmsk irlsen irq51s irq50s irq41s irq40s initial value:01000000 r/w: r/w r/w r/w rw r/w r/w r/w r/w bit:76543210 irq31s irq30s irq21s irq20s irq11s irq10s irq01s irq00s initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit 15?mask all interrupts (mai): when set to 1, all interrupt requests are masked while a low level is being input to the nmi pin. masks nmi interrupts in standby mode. bit 15: mai description 0 all interrupt requests are not masked when nmi pin is low level (initial value) 1 all interrupt requests are masked when nmi pin is low level bit 14?interrupt request level detect (irqlvl): selects whether the irq3?irq0 pins are used as four independent interrupt pins or as 15-level interrupt pins encoded as irl3 ? irl0 . bit 14: irqlvl description 0 used as four independent interrupt request pins irq3?irq0 1 used as 15-level interrupt pins encoded as irl3 ? irl0 (initial value) bit 13?bl bit mask (blmsk): specifies whether nmi interrupts are masked when the bl bit in the sr register is 1. bit 13: blmsk description 0 nmi interrupts are masked when bl bit is 1 (initial value) 1 nmi interrupts are accepted regardless of bl bit setting
rev. 5.00, 09/03, page 134 of 760 bit 12? irls irls irls irls enable (irlsen): enables pins irls3 ? irls0 . this bit is valid only when the irqlvl bit is 1. bit 12: irlsen description 0pins irls3 ? irls0 disabled (initial value) 1pins irls3 ? irls0 enabled bits 11 and 10?irq5 sense select (irq51s, irq50s): select whether the interrupt signal to the irq5 pin is detected at the rising edge, at the falling edge, or at the low level. bit 11: irq51s bit 10: irq50s description 0 0 an interrupt request is detected at irq5 input falling edge (initial value) 1 an interrupt request is detected at irq5 input rising edge 1 0 an interrupt request is detected at irq5 input low level 1 reserved bits 9 and 8?irq4 sense select (irq41s, irq40s): select whether the interrupt signal to the irq4 pin is detected at the rising edge, at the falling edge, or at the low level. bit 9: irq41s bit 8: irq40s description 0 0 an interrupt request is detected at irq4 input falling edge (initial value) 1 an interrupt request is detected at irq4 input rising edge 1 0 an interrupt request is detected at irq4 input low level 1 reserved bits 7 and 6?irq3 sense select (irq31s, irq30s): select whether the interrupt signal to the irq3 pin is detected at the rising edge, at the falling edge, or at the low level. bit 7: irq31s bit 6: irq30s description 0 0 an interrupt request is detected at irq3 input falling edge (initial value) 1 an interrupt request is detected at irq3 input rising edge 1 0 an interrupt request is detected at irq3 input low level 1 reserved
rev. 5.00, 09/03, page 135 of 760 bits 5 and 4?irq2 sense select (irq21s, irq20s): select whether the interrupt signal to the irq2 pin is detected at the rising edge, at the falling edge, or at the low level. bit 5: irq21s bit 4: irq20s description 0 0 an interrupt request is detected at irq2 input falling edge (initial value) 1 an interrupt request is detected at irq2 input rising edge 1 0 an interrupt request is detected at irq2 input low level 1 reserved bits 3 and 2?irq1 sense select (irq11s, irq10s): select whether the interrupt signal to the irq1 pin is detected at the rising edge, at the falling edge, or at the low level. bit 3: irq11s bit 2: irq10s description 0 0 an interrupt request is detected at irq1 input falling edge (initial value) 1 an interrupt request is detected at irq1 input rising edge 1 0 an interrupt request is detected at irq1 input low level 1 reserved bits 1 and 0?irq0 sense select (irq01s, irq00s): select whether the interrupt signal to the irq0 pin is detected at the rising edge, at the falling edge, or at the low level. bit 1: irq01s bit 0: irq00s description 0 0 an interrupt request is detected at irq0 input falling edge (initial value) 1 an interrupt request is detected at irq0 input rising edge 1 0 an interrupt request is detected at irq0 input low level 1 reserved
rev. 5.00, 09/03, page 136 of 760 6.3.4 interrupt control register 2 (icr2) icr2 is a 16-bit readable/writable register that sets the detection mode for external interrupt input pins pint0 to pint15. this register is initialized to h'0000 by a power-on reset or manual reset, but is not initialized in standby mode. bit: 15 14 13 12 11 10 9 8 pint15s pint14s pint13s pint14s pint11s pint10s pint9s pint8s initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 pint7s pint6s pint5s pint4s pint3s pint2s pint1s pint0s initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 0?pint15 to pint0 sense select (pint15s to pint0s): select whether interrupt request signals to pint15 to pint0 are detected at the low level or high level. bits 15?0: pint15s to pint0s description 0 interrupt requests are detected at low level input to the pint pin (initial value) 1 interrupt requests are detected at high level input to the pint pin
rev. 5.00, 09/03, page 137 of 760 6.3.5 pint interrupt enable register (pinter) pinter is a 16-bit readable/writable register that enables interrupt requests input to external interrupt input pins pint0 to pint15. this register is initialized to h'0000 by a power-on reset or manual reset, but is not initialized in standby mode. bit: 15 14 13 12 11 10 9 8 pint15e pint14e pint13e pint12e pint11e pint10e pint9e pint8e initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 pint7e pint6e pint5e pint4e pint3e pint2e pint1e pint0e initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 0?pint15 to pint0 interrupt enable (pint15e to pint0e): enable or diable interrupt request input to pins pint15 to pint0. bits 15?0: pint15e to pint0e description 0 pint input interrupt requests disabled (initial value) 1 pint input interrupt requests enabled when all or some of pins pint0?pint15 are not used for interrupt input, bits corresponding to pins not used as interrupt request pins should be cleared to 0.
rev. 5.00, 09/03, page 138 of 760 6.3.6 interrupt request register 0 (irr0) irr0 is an 8-bit register that indicates interrupt requests from external input pins irq0 to irq5 and pint0 to pint15. this register is initialized to h'00 by a power-on reset or manual reset, but is not initialized in standby mode. bit:76543210 pint0r pint1r irq5r irq4r irq3r irq2r irq1r irq0r initial value:00000000 r/w: r r r/w r/w r/w r/w r/w r/w when clearing an irq5r?irq0r bit to 0, read the bit while bit set to 1, and then write 0. in this case, 0 should be written only to the bits to be cleared and 1 to the other bits. the contents of the bits to which 1 is written do not change. bit 7?pint0 to pint7 interrupt request (pint0r): indicates whether there is interrupt request input to pins pint0 to pint7. bit 7: pint0r description 0 no interrupt request to pins pint0 to pint7 (initial value) 1 interrupt to pins pint0 to pint7 bit 6?pint8 to pint15 interrupt request (pint1r): indicates whether there is interrupt request input to pins pint8 to pint15. bit 6: pint1r description 0 no interrupt request input to pins pint8 to pint15 (initial value) 1 interrupt request input to pins pint8 to pint15 bit 5?irq5 interrupt request (irq5r): indicates whether there is interrupt request input to the irq5 pin. when edge detection mode is set for irq5, an interrupt request is cleared by clearing the irq5r bit. bit 5: irq5r description 0 no interrupt request input to irq5 pin (initial value) 1 interrupt request input to irq5 pin
rev. 5.00, 09/03, page 139 of 760 bit 4?irq4 interrupt request (irq4r): indicates whether there is interrupt request input to the irq4 pin. when edge detection mode is set for irq4, an interrupt request is cleared by clearing the irq4r bit. bit 4: irq4r description 0 no interrupt request input to irq4 pin (initial value) 1 interrupt request input to irq4 pin bit 3?irq3 interrupt request (irq3r): indicates whether there is interrupt request input to the irq3 pin. when edge detection mode is set for irq3, an interrupt request is cleared by clearing the irq3r bit. bit 3: irq3r description 0 no interrupt request input to irq3 pin (initial value) 1 interrupt request input to irq3 pin bit 2?irq2 interrupt request (irq2r): indicates whether there is interrupt request input to the irq2 pin. when edge detection mode is set for irq2, an interrupt request is cleared by clearing the irq2r bit. bit 2: irq2r description 0 no interrupt request input to irq2 pin (initial value) 1 interrupt request input to irq2 pin bit 1?irq1 interrupt request (irq1r): indicates whether there is interrupt request input to the irq1 pin. when edge detection mode is set for irq1, an interrupt request is cleared by clearing the irq1r bit. bit 1: irq1r description 0 no interrupt request input to irq1 pin (initial value) 1 interrupt request input to irq1 pin bit 0?irq0 interrupt request (irq0r): indicates whether there is interrupt request input to the irq0 pin. when edge detection mode is set for irq0, an interrupt request is cleared by clearing the irq0r bit. bit 0: irq0r description 0 no interrupt request input to irq0 pin (initial value) 1 interrupt request input to irq0 pin
rev. 5.00, 09/03, page 140 of 760 6.3.7 interrupt request register 1 (irr1) irr1 is an 8-bit read-only register that indicates whether dmac or irda interrupt requests have been generated. this register is initialized to h'00 by a power-on reset or manual reset, but is not initialized in standby mode. bit:76543210 txi1r bri1r rxi1r eri1r dei3r dei2r dei1r dei0r initial value:00000000 r/w:rrrrrrrr bit 7?txi1 interrupt request (txi1r): indicates whether a txi1 (irda) interrupt request has been generated. bit 7: txi1 description 0 txi1 interrupt request not generated (initial value) 1 txi1 interrupt request generated bit 6?bri1 interrupt request (bri1r): indicates whether a bri1 (irda) interrupt request has been generated. bit 6: bri1r description 0 bri1 interrupt request not generated (initial value) 1 bri1 interrupt request generated bit 5?rxi1 interrupt request (rxi1r): indicates whether an rxi1 (irda) interrupt request has been generated. bit 5: rxi1r description 0 rxi1 interrupt request not generated (initial value) 1 rxi1 interrupt request generated bit 4?eri1 interrupt request (eri1r): indicates whether an eri1 (irda) interrupt request has been generated. bit 4: eri1r description 0 eri1 interrupt request not generated (initial value) 1 eri1 interrupt request generated
rev. 5.00, 09/03, page 141 of 760 bit 3?dei3 interrupt request (dei3r): indicates whether a dei3 (dmac) interrupt request has been generated. bit 3: dei3r description 0 dei3 interrupt request not generated (initial value) 1 dei3 interrupt request generated bit 2?dei2 interrupt request (dei2r): indicates whether a dei2 (dmac) interrupt request has been generated. bit 2: dei2r description 0 dei2 interrupt request not generated (initial value) 1 dei2 interrupt request generated bit 1?dei1 interrupt request (dei1r): indicates whether a dei1 (dmac) interrupt request has been generated. bit 1: dei1r description 0 dei1 interrupt request not generated (initial value) 1 dei1 interrupt request generated bit 0?dei0 interrupt request (dei0r): indicates whether a dei0 (dmac) interrupt request has been generated. bit 0: dei0r description 0 dei0 interrupt request not generated (initial value) 1 dei0 interrupt request generated 6.3.8 interrupt request register 2 (irr2) irr2 is an 8-bit read-only register that indicates whether an a/d converter or scif interrupt request has been generated. this register is initialized to h'00 by a power-on reset or manual reset, but is not initialized in standby mode. bit:76543210 ? ? ? adir txi2r bri2r rxi2r eri2r initial value:00000000 r/w:rrrrrrrr
rev. 5.00, 09/03, page 142 of 760 bits 7 to 5?reserved: these bits are always read as 0. the write value should always be 0. bit 4?adi interrupt request (adir): indicates whether an adi (adc) interrupt request has been generated. b it 4: adir description 0 adi interrupt request not generated (initial value) 1 adi interrupt request generated bit 3?txi2 interrupt request (txi2r): indicates whether a txi2 (scif) interrupt request has been generated. bit 3: txi2r description 0 txi2 interrupt request not generated (initial value) 1 txi2 interrupt request generated bit 2?bri2 interrupt request (bri2r): indicates whether a bri2 (scif) interrupt request has been generated. bit 2: bri2r description 0 bri2 interrupt request not generated (initial value) 1 bri2 interrupt request generated bit 1?rxi2 interrupt request (rxi2r): indicates whether an rxi2 (scif) interrupt request has been generated. bit 1: rxi2r description 0 rxi2 interrupt request not generated (initial value) 1 rxi2 interrupt request generated bit 0?eri2 interrupt request (eri2r): indicates whether an eri2 (scif) interrupt request has been generated. bit 0: eri2r description 0 eri2 interrupt request not generated (initial value) 1 eri2 interrupt request generated
rev. 5.00, 09/03, page 143 of 760 6.4 intc operation 6.4.1 interrupt sequence the sequence of interrupt operations is described below. figure 6.3 is a flowchart of the operations. 1. the interrupt request sources send interrupt request signals to the interrupt controller. 2. the interrupt controller selects the highest-priority interrupt from the interrupt requests sent, following the priority levels set in interrupt priority registers a to e (ipra to ipre). lower priority interrupts are held pending. if two of these interrupts have the same priority level or if multiple interrupts occur within a single module, the interrupt with the highest default priority or the highest priority within its ipr setting unit (as indicated in tables 6.4 and 6.5) is selected. 3. the priority level of the interrupt selected by the interrupt controller is compared with the interrupt mask bits (i3?i0) in the status register (sr) of the cpu. if the request priority level is higher than the level in bits i3?i0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the cpu. when the interrupt controller receives an interrupt, a low level is output from the irqout pin. 4. detection timing: the intc operates, and notifies the cpu of interrupt requests, in synchronization with the peripheral clock (p ). the cpu receives an interrupt at a break in instructions. 5. the interrupt source code is set in the interrupt event registers (intevt and intevt2). 6. the status register (sr) and program counter (pc) are saved to ssr and spc, respectively. 7. the block bit (bl), mode bit (md), and register bank bit (rb) in sr are set to 1. 8. the cpu jumps to the start address of the interrupt handler (the sum of the value set in the vector base register (vbr) and h'00000600). this jump is not a delayed branch. the interrupt handler may branch with the intevt and intevt2 register value as its offset in order to identify the interrupt source. this enables it to branch to the handling routine for the individual interrupt source. notes: 1. the interrupt mask bits (i3?i0) in the status register (sr) are not changed by acceptance of an interrupt in the sh7709s. 2. irqout outputs a low level until the interrupt request is cleared. however, if the interrupt source is masked by an interrupt mask bit, the irqout pin returns to the high level. the level is output without regard to the bl bit. 3. the interrupt source flag should be cleared in the interrupt handler. to ensure that an interrupt request that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, then wait for the interval shown in table 6.8 (time for priority decision and sr mask bit comparison) before clearing the bl bit or executing an rte instruction.
rev. 5.00, 09/03, page 144 of 760 no yes yes yes yes yes yes yes no no no no no level 15 interrupt? i3 ? i0: interrupt mask bits in status register (sr) program execution state icr1.mai = 1? interrupt generated? nmi = low? sr.bl= 0 or sleep mode? yes yes yes yes yes yes no no no no no no no icr1.blmsk = 1? nmi? nmi? irqout = low set interrupt cause in intevt, intevt2 save sr to ssr; save pc to spc set bl/md/rb bits in sr to 1 branch to exception handler i3 ? i0 level 14 or lower? level 14 interrupt? i3 ? i0 level 13 or lower? level 1 interrupt? i3 ? i0 level 0? figure 6.3 interrupt operation flowchart
rev. 5.00, 09/03, page 145 of 760 6.4.2 multiple interrupts when handling multiple interrupts, an interrupt handler should include the following procedures: 1. branch to a specific interrupt handler corresponding to a code set in intevt and intevt2. the code in intevt and intevt2 can be used as a branch-offset for branching to the specific handler. 2. clear the cause of the interrupt in each specific handler. 3. save ssr and spc to memory. 4. clear the bl bit in sr, and set the accepted interrupt level in the interrupt mask bits in sr. 5. handle the interrupt. 6. execute the rte instruction. when these procedures are followed in order, an interrupt of higher priority than the one being handled can be accepted after clearing bl in step 4. figure 6.3 shows a sample interrupt operation flowchart. 6.5 interrupt response time the time from generation of an interrupt request until interrupt exception handling is performed and fetching of the first instruction of the exception handler is started (the interrupt response time) is shown in table 6.8. figure 6.4 shows an example of pipeline operation when an irl interrupt is accepted. when sr.bl is 1, interrupt exception handling is masked, and is kept waiting until completion of an instruction that clears bl to 0.
rev. 5.00, 09/03, page 146 of 760 table 6.8 interrupt response time number of states item nmi irq pint peripheral modules notes 0.5 icyc + 1.5 pcyc * 5 time for priority decision and sr mask bit comparison 0.5 icyc + 0.5 bcyc + 0.5 pcyc 0.5 icyc + 1 bcyc + 4.5 pcyc * 4 0.5 icyc + 3.5 pcyc 0.5 icyc + 3 pcyc * 6 wait time until end of sequence being executed by cpu x ( 0) icyc x ( 0) icyc x ( 0) icyc x ( 0) icyc interrupt exception handling is kept waiting until the executing instruc- tion ends. if the number of instruc- tion execution states is s * 1 , the maximum wait time is: x = s ? 1. however, if bl is set to 1 by instru- ction execution or by an exception, interrupt exception handling is deferred until completion of an instruction that clears bl to 0. if the following instruction masks interrupt exception handling, the handling may be further deferred. time from interrupt exception handling (save of sr and pc) until fetch of first instruction of exception handler is started 5 icyc 5 icyc 5 icyc 5 icyc
rev. 5.00, 09/03, page 147 of 760 number of states item nmi irq pint peripheral modules notes response time total (5.5 + x) icyc + 1.5 pcyc * 5 (5.5 + x) icyc + 0.5 bcyc + 0.5 pcyc (5.5 + x) icyc + 1 bcyc + 4.5 pcyc * 4 (5.5 + x) icyc + 3.5 pcyc * 5 (5.5 + x) icyc + 3 pcyc * 6 minimum case * 2 7.5 16.5 12.5 8.5 * 5 /11.5 * 6 at 60-mhz (ckio = 30) operation: 0.13?0.28 s maximum case * 3 8.5 + s 26.5 + s 18.5 + s 10.5 + s * 5 16.5 + s * 6 at 60-mhz (ckio = 15) operation: 0.26?0.56 s (in case of operand cache-hit) at 60-mhz (ckio = 15) operation: 0.29?0.59 s (when external memory access is performed with wait = 0) icyc: duration of one cycle of internal clock supplied to cpu. bcyc: duration of one ckio cycle. pcyc: duration of one cycle of peripheral clock supplied to peripheral modules. notes: 1. s also includes the memory access wait time. the processing requiring the maximum execution time is ldc.l @rm+, sr. when the memory access is a cache-hit, this requires seven instruction execution cycles. when the external access is performed, the corresponding number of cycles must be added. there are also instructions that perform two external memory accesses; if the external memory access is slow, the number of instruction execution cycles will increase accordingly. 2. the internal clock:ckio:peripheral clock ratio is 2:1:1. 3. the internal clock:ckio:peripheral clock ratio is 4:1:1. 4. irq mode 5. modules: tmu, rtc, sci, wdt, refc 6. modules: dmac, adc, irda, scif
rev. 5.00, 09/03, page 148 of 760 interrupt acceptance irl 0.5 icyc + 0.5 bcyc + 2 pcyc instruction (instruction replaced by interrupt exception handling) if id ex ex ex ex if if id ex 5 icyc start of interrupt handling if: instruction fetch: instruction is fetched from memory in which program is stored. id: instruction decode: fetched instruction is decoded. ex: instruction execution: data operation and address calculation are performed. overrun fetch first instruction of interrupt handler figure 6.4 example of pipeline operations when irl interrupt is accepted
rev. 5.00, 09/03, page 149 of 760 section 7 user break controller 7.1 overview the user break controller (ubc) provides functions that simplify program debugging. this function makes it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. break conditions that can be set in the ubc are instruction fetch or data read/write, data size, data content, address value, and stop timing during instruction fetches. 7.1.1 features the user break controller has the following features: ? the following break comparison conditions can be set. number of break channels: two channels (channels a and b) user break can be requested as either the independent or sequential condition on channels a and b (sequential break setting: channel a and, then channel b match with logical and, but not in the same bus cycle). address (compares 40 bits comprised of a 32-bit logical address prefixed with an asid address. comparison bits are maskable in 32-bit units, user can easily program it to mask addresses at bottom 12 bits (4-k page), bottom 10 bits (1-k page), or any size of page, etc. one of two address buses (cpu address bus (lab), cache address bus (iab)) can be selected. ? data (only on channel b, 32-bit maskable) ? one of the two data buses (cpu data bus (ldb), cache data bus (idb)) can be selected. ? bus master: cpu cycle or dmac cycle ? bus cycle: instruction fetch or data access ? read/write ? operand size: byte, word, or longword ? user break is generated upon satisfying break conditions. a user-designed user-break condition exception processing routine can be run. ? in an instruction fetch cycle, it can be selected that a break is set before or after an instruction is executed. ? maximum repeat times for the break condition: 2 12 ? 1 times. ? eight pairs of branch source/destination buffers.
rev. 5.00, 09/03, page 150 of 760 7.1.2 block diagram figure 7.1 shows a block diagram of the ubc. bbra bara bamra basra asid comparator cpu state signals iab lab mdb access comparator address comparator channel a asid comparator access comparator address comparator data comparator pc trace control channel b bbrb betr barb bamrb basrb bdrb bdmrb brsr brdr brcr user break request ubc location ccn location ldb/idb/ xdb/ydb access control legend bbra: break bus cycle register a bara: break address register a bamra: break address mask register a basra: break asid register a bbrb: break bus cycle register b barb: break address register b bamrb: break address mask register b basrb: break asid register b bdrb: break data register b bdmrb: break data mask register b betr: break execution times register brsr: branch source register brdr: branch destination register brcr: break control register figure 7.1 block diagram of user break controller
rev. 5.00, 09/03, page 151 of 760 7.1.3 register configuration table 7.1 register configuration name abbr. r/w initial value * 1 address access size location break address register a bara r/w h'00000000 h'ffffffb0 32 ubc break address mask register a bamra r/w h'00000000 h'ffffffb4 32 ubc break bus cycle register a bbra r/w h'0000 h'ffffffb8 16 ubc break address register b barb r/w h'00000000 h'ffffffa0 32 ubc break address mask register b bamrb r/w h'00000000 h'ffffffa4 32 ubc break bus cycle register b bbrb r/w h'0000 h'ffffffa8 16 ubc break data register b bdrb r/w h'00000000 h'ffffff90 32 ubc break data mask register b bdmrb r/w h'00000000 h'ffffff94 32 ubc break control register brcr r/w h'00000000 h'ffffff98 32 ubc execution count break register betr r/w h'0000 h'ffffff9c 16 ubc branch source register brsr r undefined * 2 h'ffffffac 32 ubc branch destination register brdr r undefined * 2 h'ffffffbc 32 ubc break asid register a basra r/w undefined h'ffffffe4 16 ccn break asid register b basrb r/w undefined h'ffffffe8 16 ccn notes: 1. initialized by power-on reset. values held in standby state and undefined by manual resets. 2. bit 31 of brsr and brdr (valid flag) is initialized by power-on resets. but other bits are not initialized.
rev. 5.00, 09/03, page 152 of 760 7.2 register descriptions 7.2.1 break address register a (bara) bara is a 32-bit read/write register. bara specifies the address used as a break condition in channel a. a power-on reset initializes bara to h'00000000. bit: 31 30 29 28 27 26 25 24 baa31 baa30 baa29 baa28 baa27 baa26 baa25 baa24 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 baa23 baa22 baa21 baa20 baa19 baa18 baa17 baa16 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 baa15 baa14 baa13 baa12 baa11 baa10 baa9 baa8 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 baa7 baa6 baa5 baa4 baa3 baa2 baa1 baa0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 31 to 0?break address a31 to a0 (baa31 to baa0): stores the address on the lab or iab specifying break conditions of channel a.
rev. 5.00, 09/03, page 153 of 760 7.2.2 break address mask register a (bamra) bamra is a 32-bit read/write register. bamra specifies bits masked in the break address specified by bara. a power-on reset initializes bamra to h'00000000. bit: 31 30 29 28 27 26 25 24 bama31 bama30 bama29 bama28 bama27 bama26 bama25 bama24 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 bama23 bama22 bama21 bama20 bama19 bama18 bama17 bama16 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 bama15 bama14 bama13 bama12 bama11 bama10 bama9 bama8 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 bama7 bama6 bama5 bama4 bama3 bama2 bama1 bama0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 31 to 0?break address mask register a31 to a0 (bama31 to bama0): specifies bits masked in the channel a break address bits specified by bara (baa31?baa0). bits 31 to 0: baman description 0 break address bit baan of channel a is included in the break condition (initial value) 1 break address bit baan of channel a is masked and is not included in the break condition n = 31 to 0
rev. 5.00, 09/03, page 154 of 760 7.2.3 break bus cycle register a (bbra) break bus cycle register a (bbra) is a 16-bit read/write register, which specifies (1) cpu cycle or dmac cycle, (2) instruction fetch or data access, (3) read or write, and (4) operand size in the break conditions of channel a. a power-on reset initializes bbra to h'0000. bit: 15 14 13 12 11 10 9 8 ???????? initial value:00000000 r/w:rrrrrrrr bit:76543210 cda1 cda0 ida1 ida0 rwa1 rwa0 sza1 sza0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 8?reserved: these bits are always read as 0. the write value should always be 0. bits 7 and 6?cpu cycle/dmac cycle select a (cda1, cda0): selects the cpu cycle or dmac cycle as the bus cycle of the channel a break condition. bit 7: cda1 bit 6: cda0 description 0 0 condition comparison is not performed (initial value) * 1 the break condition is the cpu cycle 1 0 the break condition is the dmac cycle * : don?t care bits 5 and 4?instruction fetch/data access select a (ida1, ida0): selects the instruction fetch cycle or data access cycle as the bus cycle of the channel a break condition. bit 5: ida1 bit 4: ida0 description 0 0 condition comparison is not performed (initial value) 1 the break condition is the instruction fetch cycle 1 0 the break condition is the data access cycle 1 the break condition is the instruction fetch cycle or data access cycle
rev. 5.00, 09/03, page 155 of 760 bits 3 and 2?read/write select a (rwa1, rwa0): selects the read cycle or write cycle as the bus cycle of the channel a break condition. bit 3: rwa1 bit 2: rwa0 description 0 0 condition comparison is not performed (initial value) 1 the break condition is the read cycle 1 0 the break condition is the write cycle 1 the break condition is the read cycle or write cycle bits 1 and 0?operand size select a (sza1, sza0): selects the operand size of the bus cycle for the channel a break condition. bit 1: sza1 bit 0: sza0 description 0 0 the break condition does not include operand size (initial value) 1 the break condition is byte access 1 0 the break condition is word access 1 the break condition is longword access
rev. 5.00, 09/03, page 156 of 760 7.2.4 break address register b (barb) barb is a 32-bit read/write register. barb specifies the address used as a break condition in channel b. a power-on reset initializes barb to h'00000000. bit: 31 30 29 28 27 26 25 24 bab31 bab30 bab29 bab28 bab27 bab26 bab25 bab24 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 bab23 bab22 bab21 bab20 bab19 bab18 bab17 bab16 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 bab15 bab14 bab13 bab12 bab11 bab10 bab9 bab8 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 bab7 bab6 bab5 bab4 bab3 bab2 bab1 bab0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
rev. 5.00, 09/03, page 157 of 760 7.2.5 break address mask register b (bamrb) bamrb is a 32-bit read/write register. bamrb specifies bits masked in the break address specified by barb. a power-on reset initializes bamrb to h'00000000. bit: 31 30 29 28 27 26 25 24 bamb31 bamb30 bamb29 bamb28 bamb27 bamb26 bamb25 bamb24 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 bamb23 bamb22 bamb21 bamb20 bamb19 bamb18 bamb17 bamb16 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 bamb15 bamb14 bamb13 bamb12 bamb11 bamb10 bamb9 bamb8 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 bamb7 bamb6 bamb5 bamb4 bamb3 bamb2 bamb1 bamb0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 31 to 0?break address mask register b31 to b0 (bamb31 to bamb0): specifies bits masked in the channel b break address bits specified by barb (bab31?bab0). bits 31 to 0: bambn description 0 break address babn of channel b is included in the break condition (initial value) 1 break address babn of channel b is masked and is not included in the break condition n = 31 to 0
rev. 5.00, 09/03, page 158 of 760 7.2.6 break data register b (bdrb) bdrb is a 32-bit read/write register. a power-on reset initializes bdrb to h'00000000. bit: 31 30 29 28 27 26 25 24 bdb31 bdb30 bdb29 bdb28 bdb27 bdb26 bdb25 bdb24 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 bdb23 bdb22 bdb21 bdb20 bdb19 bdb18 bdb17 bdb16 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 bdb15 bdb14 bdb13 bdb12 bdb11 bdb10 bdb9 bdb8 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 bdb7 bdb6 bdb5 bdb4 bdb3 bdb2 bdb1 bdb0 initial value:00000000
rev. 5.00, 09/03, page 159 of 760 7.2.7 break data mask register b (bdmrb) bdmrb is a 32-bit read/write register. bdmrb specifies bits masked in the break data specified by bdrb. a power-on reset initializes bdmrb to h'00000000. bit: 31 30 29 28 27 26 25 24 bdmb31 bdmb30 bdmb29 bdmb28 bdmb27 bdmb26 bdmb25 bdmb24 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 bdmb23 bdmb22 bdmb21 bdmb20 bdmb19 bdmb18 bdmb17 bdmb16 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 bdmb15 bdmb14 bdmb13 bdmb12 bdmb11 bdmb10 bdmb9 bdmb8 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 bdmb7 bdmb6 bdmb5 bdmb4 bdmb3 bdmb2 bdmb1 bdmb0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 31 to 0?break data mask register b31 to b0 (bdmb31 to bdmb0): specifies bits in the channel b break data bits specified by bdrb (bdb31?bdb0). bits 31 to 0: bdmbn description 0 break data bdbn of channel b is included in the break condition (initial value) 1 break data bdbn of channel b is masked and is not included in the break condition n = 31 to 0 notes: 1. specify an operand size when including the value of the data bus in the break condition. 2. when a byte size is specified as a break condition, the same-byte data must be set in bits 15 to 8 and bits 7 to 0 in bdrb for the break data.
rev. 5.00, 09/03, page 160 of 760 7.2.8 break bus cycle register b (bbrb) break bus cycle register b (bbrb) is a 16-bit read/write register, which specifies, (1) cpu cycle or dmac cycle, (2) instruction fetch or data access, (3) read/write, and (4) operand size in the break conditions of channel b. a power-on reset initializes bbrb to h'0000. bit: 15 14 13 12 11 10 9 8 ???????? initial value:00000000 r/w:rrrrrrrr bit:76543210 cdb1 cdb0 idb1 idb0 rwb1 rwb0 szb1 szb0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 8?reserved: these bits are always read as 0. these bits are always read as 0. bits 7 and 6?cpu cycle/dmac cycle select b (cdb1, cdb0): select the cpu cycle or dmac cycle as the bus cycle of the channel b break condition. bit 7: cdb1 bit 6: cdb0 description 0 0 condition comparison is not performed (initial value) * 1 the break condition is the cpu cycle 1 0 the break condition is the dmac cycle * : don?t care bits 5 and 4?instruction fetch/data access select b (idb1, idb0): select the instruction fetch cycle or data access cycle as the bus cycle of the channel b break condition. bit 5: idb1 bit 4: idb0 description 0 0 condition comparison is not performed (initial value) 1 the break condition is the instruction fetch cycle 1 0 the break condition is the data access cycle 1 the break condition is the instruction fetch cycle or data access cycle
rev. 5.00, 09/03, page 161 of 760 bits 3 and 2?read/write select b (rwb1, rwb0): select the read cycle or write cycle as the bus cycle of the channel b break condition. bit 3: rwb1 bit 2: rwb0 description 0 0 condition comparison is not performed (initial value) 1 the break condition is the read cycle 1 0 the break condition is the write cycle 1 the break condition is the read cycle or write cycle bits 1 and 0?operand size select b (szb1, szb0): select the operand size of the bus cycle for the channel b break condition. bit 1: szb1 bit 0: szb0 description 0 0 the break condition does not include operand size (initial value) 1 the break condition is byte access 1 0 the break condition is word access 1 the break condition is longword access
rev. 5.00, 09/03, page 162 of 760 7.2.9 break control register (brcr) brcr sets the following conditions: 1. channels a and b are used in two independent channels condition or under the sequential condition. 2. a break is set before or after instruction execution. 3. a break is set by the number of execution times. 4. determine whether to include data bus on channel b in comparison conditions. 5. enable pc trace. 6. enable the asid check. the break control register (brcr) is a 32-bit read/write register that has break conditions match flags and bits for setting a variety of break conditions. a power-on reset initializes brcr to h'00000000. bit: 31 30 29 28 27 26 25 24 ???????? initial value:00000000 r/w:rrrrrrrr bit: 23 22 21 20 19 18 17 16 ??basmabasmb???? initial value:00000000 r/w:rrr/wr/wrrrr bit: 15 14 13 12 11 10 9 8 scmfca scmfcb scmfda scmfdb pcte pcba ? ? initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r r bit:76543210 dbeb pcbb ? ? seq ? ? etbe initial value:00000000 r/w: r/w r/w r r r/w r r r/w bits 31 to 22?reserved: these bits are always read as 0. the write value should always be 0.
rev. 5.00, 09/03, page 163 of 760 bit 21?break asid mask a (basma): specifies whether the bits of the channel a break asid7-asid0 (basa7 to basa0) set in basra are masked or not. bit 21: basma description 0 all basra bits are included in break condition, asid is checked (initial value) 1 no basra bits are included in break condition, asid is not checked bit 20?break asid mask b (basmb): specifies whether the bits of channel b break asid7- asid0 (basb7 to basb0) set in basrb are masked or not. bit 20: basmb description 0 all basrb bits are included in break condition, asid is checked (initial value) 1 no basrb bits are included in break condition, asid is not checked bits 19 to 16?reserved: these bits are always read as 0. the write value should always be 0. bit 15?cpu condition match flag a (scmfca): when the cpu bus cycle condition in the break conditions set for channel a is satisfied, this flag is set to 1 (not cleared to 0). in order to clear this flag, write 0 into this bit. bit 15: scmfca description 0 the cpu cycle condition for channel a does not match (initial value) 1 the cpu cycle condition for channel a matches bit 14?cpu condition match flag b (scmfcb): when the cpu bus cycle condition in the break conditions set for channel b is satisfied, this flag is set to 1 (not cleared to 0). in order to clear this flag, write 0 into this bit. bit 14: scmfcb description 0 the cpu cycle condition for channel b does not match (initial value) 1 the cpu cycle condition for channel b matches
rev. 5.00, 09/03, page 164 of 760 bit 13?dmac condition match flag a (scmfda): when the on-chip dmac bus cycle condition in the break conditions set for channel a is satisfied, this flag is set to 1 (not cleared to 0). in order to clear this flag, write 0 into this bit. bit 13: scmfda description 0 the dmac cycle condition for channel a does not match (initial value) 1 the dmac cycle condition for channel a matches bit 12?dmac condition match flag b (scmfdb): when the on-chip dmac bus cycle condition in the break conditions set for channel b is satisfied, this flag is set to 1 (not cleared to 0). in order to clear this flag, write 0 into this bit. bit 12: scmfdb description 0 the dmac cycle condition for channel b does not match (initial value) 1 the dmac cycle condition for channel b matches bit 11?pc trace enable (pcte): enables pc trace. bit 11: pcte description 0 disables pc trace (initial value) 1 enables pc trace bit 10?pc break select a (pcba): selects the break timing of the instruction fetch cycle for channel a as before or after instruction execution. bit 10: pcba description 0 pc break of channel a is set before instruction execution (initial value) 1 pc break of channel a is set after instruction execution bits 9 and 8?reserved: these bits are always read as 0. the write value should always be 0. bit 7?data break enable b (dbeb): selects whether or not the data bus condition is included in the break condition of channel b. bit 7: dbeb description 0 no data bus condition is included in the condition of channel b (initial value) 1 the data bus condition is included in the condition of channel b
rev. 5.00, 09/03, page 165 of 760 bit 6?pc break select b (pcbb): selects the break timing of the instruction fetch cycle for channel b as before or after instruction execution. bit 6: pcbb description 0 pc break of channel b is set before instruction execution (initial value) 1 pc break of channel b is set after instruction execution bits 5 and 4?reserved: these bits are always read as 0. the write value should always be 0. bit 3?sequence condition select (seq): selects two conditions of channels a and b as independent or sequential. bit 3: seq description 0 channels a and b are compared under the independent condition (initial value) 1 channels a and b are compared under the sequential condition (channel a, then channel b) bits 2 and 1?reserved: these bits are always read as 0. the write value should always be 0. bit 0?the number of execution times break enable (etbe): enable the execution-times break condition only on channel b. if this bit is 1 (break enable), a user break is issued when the number of break conditions matches with the number of execution times that is specified by the betr register. bit 0: etbe description 0 the execution-times break condition is masked on channel b (initial value) 1 the execution-times break condition is enabled on channel b
rev. 5.00, 09/03, page 166 of 760 7.2.10 execution times break register (betr) when the execution-times break condition of channel b is enabled, this register specifies the number of execution times to make the break. the maximum number is 2 12 ? 1 times. a power-on reset initializes betr to h'0000. when a break condition is satisfied, it decreases the betr. a break is issued when the break condition is satisfied after the betr becomes h'0001. bits 15-12 are always read as 0 and 0 should always be written in these bits. bit: 15 14 13 12 11 10 9 8 ???? initial value:00000000 r/w:rrrrr/wr/wr/wr/w bit:76543210 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
rev. 5.00, 09/03, page 167 of 760 7.2.11 branch source register (brsr) brsr is a 32-bit read register. brsr stores the last fetched address before branch and the pointer (3 bits) which indicates the number of cycles from fetch to execution for the last executed instruction. brsr has the flag bit that is set to 1 when branch occurs. this flag bit is cleared to 0, when brsr is read and also initialized by power-on resets or manual resets. other bits are not initialized by reset. eight brsr registers have queue structure and a stored register is shifted every branch. bit: 31 30 29 28 27 26 25 24 svf pid2 pid1 pid0 bsa27 bsa26 bsa25 bsa24 initial value: 0 ******* r/w:rrrrrrrr bit: 23 22 21 20 19 18 17 16 bsa23 bsa22 bsa21 bsa20 bsa19 bsa18 bsa17 bsa16 initial value: ******** r/w:rrrrrrrr bit: 15 14 13 12 11 10 9 8 bsa15 bsa14 bsa13 bsa12 bsa11 bsa10 bsa9 bsa8 initial value: ******** r/w:rrrrrrrr bit:76543210 bsa7 bsa6 bsa5 bsa4 bsa3 bsa2 bsa1 bsa0 initial value: ******** r/w:rrrrrrrr note: * undefined value bit 31?brsr valid flag (svf): indicates whether the address and the pointer by which the branch source address can be calculated. when a branch source address is fetched, this flag is set to 1. this flag is cleared to 0 in reading brsr. bit 31: svf description 0 the value of brsr register is invalid 1 the value of brsr register is valid
rev. 5.00, 09/03, page 168 of 760 bits 30 to 28?instruction decode pointer (pid2 to pid0): pid is a 3-bit binary pointer (0?7). these bits indicate the instruction buffer number which stores the last executed instruction before branch. bits 30 to 28: pid description even pid indicates the instruction buffer number. odd pid+2 indicates the instruction buffer number bits 27 to 0?branch source address (bsa27 to bsa0): these bits store the last fetched address before branch. 7.2.12 branch destination register (brdr) brdr is a 32-bit read register. brdr stores the branch destination fetch address. brdr has the flag bit that is set to 1 when branch occurs. this flag bit is cleared to 0, when brdr is read and also initialized by power-on resets or manual resets. other bits are not initialized by resets. eight brdr registers have queue structure and a stored register is shifted every branch. bit: 31 30 29 28 27 26 25 24 dvf ? ? ? bda27 bda26 bda25 bda24 initial value: 0 ******* r/w:rrrrrrrr bit: 23 22 21 20 19 18 17 16 bda23 bda22 bda21 bda20 bda19 bda18 bda17 bda16 initial value: ******** r/w:rrrrrrrr bit: 15 14 13 12 11 10 9 8 bda15 bda14 bda13 bda12 bda11 bda10 bda9 bda8 initial value: ******** r/w:rrrrrrrr bit:76543210 bda7 bda6 bda5 bda4 bda3 bda2 bda1 bda0 initial value: ******** r/w:rrrrrrrr note: * undefined value
rev. 5.00, 09/03, page 169 of 760 bit 31?brdr valid flag (dvf): indicates whether a branch destination address is stored. when a branch destination address is fetched, this flag is set to 1. this flag is set to 0 in reading brdr. bit 31: dvf description 0 the value of brdr register is invalid 1 the value of brdr register is valid bits 30 to 28?reserved: these bits are always read as 0. the write value should always be 0. bits 27 to 0?branch destination address (bda27 to bda0): these bits store the first fetched address after branch. 7.2.13 break asid register a (basra) break asid register a (basra) is an 8-bit read/write register that specifies the asid that serves as the break condition for channel a. it is not initialized by resets. bit:76543210 basa7 basa6 basa5 basa4 basa3 basa2 basa1 basa0 initial value: ******** r/w: r/w r/w r/w r/w r/w r/w r/w r/w note: * undefined value bits 7 to 0?break asid a7 to 0 (basa7 to basa0): these bits store the asid (bits 7 to 0) that is the channel a break condition. 7.2.14 break asid register b (basrb) break asid register b (basrb) is an 8-bit read/write register that specifies the asid that serves as the break condition for channel b. it is not initialized by resets. bit:76543210 basb7 basb6 basb5 basb4 basb3 basb2 basb1 basb0 initial value: ******** r/w: r/w r/w r/w r/w r/w r/w r/w r/w note: * undefined value bits 7 to 0?break asid a7 to 0 (basb7 to basb0): these bits store the asid (bits 7 to 0) that is the channel b break condition.
rev. 5.00, 09/03, page 170 of 760 7.3 operation description 7.3.1 flow of the user break operation the flow from setting of break conditions to user break exception processing is described below: 1. the break addresses and the corresponding asids are loaded in the break address registers (bara and barb) and break asid registers (basra and basrb). the masked addresses are set in the break address mask registers (bamra and bamrb). the break data is set in the break data register (bdrb). the masked data is set in the break data mask register (bdmrb). the breaking bus conditions are set in the break bus cycle registers (bbra and bbrb). three groups of the bbra and bbrb (cpu cycle/dmac cycle select, instruction fetch/data access select, and read/write select) are each set. no user break will be generated if even one of these groups is set with 00. the respective conditions are set in the bits of the brcr. 2. when the break conditions are satisfied, the ubc sends a user break request to the interrupt controller. the break type will be sent to cpu indicating the instruction fetch, pre/post instruction break, data access break. when conditions match up, the cpu condition match flags (scmfca and scmfcb) and dmac condition match flags (scmfda and scmfdb) for the respective channels are set. 3. the appropriate condition match flags (scmfca, scmfda, scmfcb, and scmfdb) can be used to check if the set conditions match or not. the matching of the conditions sets flags, but they are not reset. 0 must first be written to them before they can be used again. 4. there is a chance that the data access break and its following instruction fetch break occur around the same time, there will be only one break request to the cpu, but these two break channel match flags could be both set. 7.3.2 break on instruction fetch cycle 1. when cpu/instruction fetch/read/word or longword is set in the break bus cycle registers (bbra/bbrb), the break condition becomes the cpu instruction fetch cycle. whether it then breaks before or after the execution of the instruction can then be selected with the pcba/pcbb bits of the break control register (brcr) for the appropriate channel. 2. an instruction set for a break before execution breaks when it is confirmed that the instruction has been fetched and will be executed. this means this feature cannot be used on instructions fetched by overrun (instructions fetched at a branch or during an interrupt transition, but not to be executed). when this kind of break is set for the delay slot of a delay branch instruction, the break is generated prior to execution of the instruction that then first accepts the break. meanwhile, the break set for pre-instruction-break on delay slot instruction and post- instruction-break on sleep instruction are also prohibited.
rev. 5.00, 09/03, page 171 of 760 3. when the condition is specified to be occurred after execution, the instruction set with the break condition is executed and then the break is generated prior to the execution of the next instruction. as with pre-execution breaks, this cannot be used with overrun fetch instructions. when this kind of break is set for a delay branch instruction, the break is generated at the instruction that then first accepts the break. 4. when an instruction fetch cycle is set for channel b, break data register b (bdrb) is ignored. there is thus no need to set break data for the break of the instruction fetch cycle. 7.3.3 break by data access cycle 1. the memory cycles in which cpu data access breaks occur are from instructions. 2. the relationship between the data access cycle address and the comparison condition for operand size are listed in table 7.2: table 7.2 data access cycle addresses and operand size comparison conditions access size address compared longword compares break address register bits 31?2 to address bus bits 31?2 word compares break address register bits 31?1 to address bus bits 31?1 byte compares break address register bits 31?0 to address bus bits 31?0 this means that when address h'00001003 is set without specifying the size condition, for example, the bus cycle in which the break condition is satisfied is as follows (where other conditions are met). longword access at h'00001000 word access at h'00001002 byte access at h'00001003 3. when the data value is included in the break conditions on b channel: when the data value is included in the break conditions, either longword, word, or byte is specified as the operand size of the break bus cycle registers (bbra and bbrb). when data values are included in break conditions, a break is generated when the address conditions and data conditions both match. to specify byte data for this case, set the same data in two bytes at bits 15?8 and bits 7?0 of the break data register b (bdrb) and break data mask register b (bdmrb). when word or byte is set, bits 31?16 of bdrb and bdmrb are ignored. 4. when the dmac data access is included in the break condition: when the address is included in the break condition on dmac data access, the operand size of the break bus cycle registers (bbra and bbrb) should be byte, word or no specified operand size. when the data value is included, select either byte or word.
rev. 5.00, 09/03, page 172 of 760 7.3.4 sequential break 1. by specifying seq in brcr is set to 1, the sequential break is issued when channel b break condition matches after channel a break condition matches. a user break is ignored even if channel b break condition matches before channel a break condition matches. when channels a and b condition match at the same time, the sequential break is not issued. 2. in sequential break specification, a logical bus or internal bus can be selected and the execution times break condition can be also specified. for example, when the execution times break condition is specified, the break condition is satisfied at channel b condition match with betr = h'0001 after channel a condition match. 7.3.5 value of saved program counter the pc when a break occurs is saved to the spc in user breaks. the pc value saved is as follows depending on the type of break. 1. when instruction fetch (before instruction execution) is specified as a break condition: the value of the program counter (pc) saved is the address of the instruction that matches the break condition. the fetched instruction is not executed, and a break occurs before it. 2. when instruction fetch (after instruction execution) is specified as a break condition: the pc value saved is the address of the instruction to be executed following the instruction in which the break condition matches. the fetched instruction is executed, and a break occurs before the execution of the next instruction. 3. when data access (address only) is specified as a break condition: the pc value is the address of the instruction to be executed following the instruction that matched the break condition. the instruction that matched the condition is executed and the break occurs before the next instruction is executed. 4. when data access (address + data) is specified as a break condition: the pc value is the start address of the instruction that follows the instruction already executed when break processing started up. when a data value is added to the break conditions, the place where the break will occur cannot be specified exactly. the break will occur before the execution of an instruction fetched around the data access where the break occurred.
rev. 5.00, 09/03, page 173 of 760 7.3.6 pc trace 1. setting pcte in brcr to 1 enables pc traces. when branch (branch instruction, repeat, and interrupt) is generated, the address from which the branch source address can be calculated and the branch destination address are stored in brsr and brdr, respectively. the branch address and the pointer, which corresponds to the branch, are included in brsr. 2. the branch address before branch occurs can be calculated from the address and the pointer stored in brsr. the expression from bsa (the address in brsr), pid (the pointer in brsr), and ia (the instruction address before branch occurs) is as follows: ia = bsa ? 2 * pid. notes are needed when an interrupt (a branch) is issued before the branch destination instruction is executed. in case of the next figure, the instruction ?exec? executed immediately before branch is calculated by ia = bsa ? 2 * pid. however, when branch ?branch? has delay slot and the destination address is 4n + 2 address, the address ?dest? which is specified by branch instruction is stored in brsr (dest = bsa). therefore, as ia = bsa ? 2 * pid is not applied to this case, this pid is invalid. the case where bsa is 4n + 2 boundary is applied only to this case and then some cases are classified as follows: exec:branch dest dest:instr (not executed) interrupt int: interrupt routine if the pid value is odd, instruction buffer indicates pid+2 buffer. however, these expressions in this table are accounted for it. therefore, the true branch source address is calculated with bsa and pid values stored in brsr. 3. the branch address before branch occurrence, ia, has different values due to some kinds of branch. a. branch instruction the branch instruction address b. interrupt the last instruction executed before interrupt the top address of interrupt routine is stored in brdr. 4. brsr and brdr have eight pairs of queue structures. the top of queues is read first when the address stored in the pc trace register is read. brsr and brdr share the read pointer. read brsr and brdr in order, the queue only shifts after brdr is read. when reading brdr, longword access should be used. also, the pc trace has a trace pointer, which initially points to the bottom of the queues. the first pair of branch addresses will be stored at the bottom of the queues, then push up when next pairs come into the queues. the trace pointer will points to the next branch address to be executed, unless it got push out of the queues. when the branch address has been executed, the trace pointer will shift down to next pair of addresses, until it
rev. 5.00, 09/03, page 174 of 760 reaches the bottom of the queues. after switching the pcte bit (in brcr) off and on, the values in the queues are invalid. the read pointer stay at the position before pcte is switched, but the trace pointer restart at the bottom of the queues. 7.3.7 usage examples break condition specified to a cpu instruction fetch cycle 1. register specifications bara = h'00000404, bamra = h'00000000, bbra = h'0054, barb = h'00008010, bamrb = h'00000006, bbrb = h'0054, bdrb = h'00000000, bdmrb = h'00000000, brcr = h' 00300400 specified conditions: channel a/channel b independent mode ?channel a address: h'00000404, address mask: h'00000000 bus cycle: cpu/instruction fetch (after instruction execution)/read (operand size is not included in the condition) no asid check is included ?channel b address: h'00008010, address mask: h'00000006 data: h'00000000, data mask: h'00000000 bus cycle: cpu/instruction fetch (before instruction execution)/read (operand size is not included in the condition) no asid check is included a user break occurs after an instruction of address h'00000404 is executed or before instructions of adresses h'00008010 to h'00008016 are executed.
rev. 5.00, 09/03, page 175 of 760 2. register specifications bara = h'00037226, bamra = h'00000000, bbra = h'0056, barb = h'0003722e, bamrb = h'00000000, bbrb = h'0056, bdrb = h'00000000, bdmrb = h'00000000, brcr = h' 00000008, basra = h'80, basrb = h'70 specified conditions: channel a/channel b sequence mode ?channel a address: h'00037226, address mask: h'00000000, asid = h'80 bus cycle: cpu/instruction fetch (before instruction execution)/read/word ?channel b address: h'0003722e, address mask: h'00000000, asid = h'70 data: h'00000000, data mask: h'00000000 bus cycle: cpu/instruction fetch (before instruction execution)/read/word an instruction with asid = h'80 and address h'00037226 is executed, and a user break occurs before an instruction with asid = h'70 and address h'0003722e is executed. 3. register specifications bara = h'00027128, bamra = h'00000000, bbra = h'005a, barb = h'00031415, bamrb = h'00000000, bbrb = h'0054, bdrb = h'00000000, bdmrb = h'00000000, brcr = h' 00300000 specified conditions: channel a/channel b independent mode ?channel a address: h'00027128, address mask: h'00000000 bus cycle: cpu/instruction fetch (before instruction execution)/write/word no asid check is included ?channel b address: h'00031415, address mask: h'00000000 data: h'00000000, data mask: h'00000000 bus cycle: cpu/instruction fetch (before instruction execution)/read (operand size is not included in the condition) no asid check is included on channel a, no user break occurs since instruction fetch is not a write cycle. on channel b, no user break occurs since instruction fetch is performed for an even address.
rev. 5.00, 09/03, page 176 of 760 4. register specifications bara = h'00037226, bamra = h'00000000, bbra = h'005a, barb = h'0003722e, bamrb = h'00000000, bbrb = h'0056, bdrb = h'00000000, bdmrb = h'00000000, brcr = h' 00000008, basra = h'80, basrb = h'70 specified conditions: channel a/channel b sequence mode ?channel a address: h'00037226, address mask: h'00000000, asid: h'80 bus cycle: cpu/instruction fetch (before instruction execution)/write/word ?channel b address: h'0003722e, address mask: h'00000000, asid: h'70 data: h'00000000, data mask: h'00000000 bus cycle: cpu/instruction fetch (before instruction execution)/read/word since instruction fetch is not a write cycle on channel a, a sequence condition does not match. therefore, no user break occurs. 5. register specifications bara = h'00000500, bamra = h'00000000, bbra = h'0057, barb = h'00001000, bamrb = h'00000000, bbrb = h'0057, bdrb = h'00000000, bdmrb = h'00000000, brcr = h' 00300001, betr = h'0005 specified conditions: channel a/channel b independent mode ?channel a address: h'00000500, address mask: h'00000000 bus cycle: cpu/instruction fetch (before instruction execution)/read/longword ?channel b address: h'00001000, address mask: h'00000000 data: h'00000000, data mask: h'00000000 bus cycle: cpu/instruction fetch (before instruction execution)/read/longword the number of execution-times break enable (5 times) on channel a, a user break occurs before an instruction of address h'00000500 is executed. on channel b, a user break occurs before the fifth instruction execution after instructions of address h'00001000 are executed four times.
rev. 5.00, 09/03, page 177 of 760 6. register specifications bara = h'00008404, bamra = h'00000fff, bbra = h'0054, barb = h'00008010, bamrb = h'00000006, bbrb = h'0054, bdrb = h'00000000, bdmrb = h'00000000, brcr = h' 00000400, basra = h'80, basrb = h'70 specified conditions: channel a/channel b independent mode ?channel a address: h'00008404, address mask: h'00000fff, asid: h'80 bus cycle: cpu/instruction fetch (after instruction execution)/read (operand size is not included in the condition) ?channel b address: h'00008010, address mask: h'00000006, asid: h'70 data: h'00000000, data mask: h'00000000 bus cycle: cpu/instruction fetch (before instruction execution)/read (operand size is not included in the condition) a user break occurs after an instruction with asid = h'80 and address h'00008000 to h'00008ffe is executed or before instructions with asid = h'70 and addresses h'00008010 to h'00008016 are executed. break condition specified to a cpu data access cycle 1. register specifications bara = h'00123456, bamra = h'00000000, bbra = h'0064, barb = h'000abcde, bamrb = h'000000ff, bbrb = h'006a, bdrb = h'0000a512, bdmrb = h'00000000, brcr = h' 00000080, basra = h'80, basrb = h'70 specified conditions: channel a/channel b independent mode ?channel a address: h'00123456, address mask: h'00000000 bus cycle: cpu/data access/read (operand size is not included in the condition) ?channel b address: h'000abcde, address mask: h'000000ff, asid: h'70 data: h'0000a512, data mask: h'00000000 bus cycle: cpu/data access/write/word on channel a, a user break occurs with asid = h'80 during longword read to address h'00123454, word read to address h'00123456, or byte read to address h'00123456. on channel b, a user break occurs with asid = h'70 when word h'a512 is written in addresses h'000abc00 to h'000abcfe.
rev. 5.00, 09/03, page 178 of 760 break condition specified to a dmac data access cycle 1. register specifications: bara = h'00314156, bamra = h'00000000, bbra = h'0094, barb = h'00055555, bamrb = h'00000000, bbrb = h'00a9, bdrb = h'00000078, bdmrb = h'0000000f, brcr = h' 00000080, basra = h'80, basrb = h'70 specified conditions: channel a/channel b independent mode ?channel a address: h'00314156, address mask: h'00000000, asid: h'80 bus cycle: dmac/instruction fetch/read (operand size is not included in the condition) ?channel b address: h'00055555, address mask: h'00000000, asid: h'70 data: h'00000078, data mask: h'0000000f bus cycle: dmac/data access/write/byte on channel a, no user break occurs since instruction fetch is not performed in dmac cycles. on channel b, a user break occurs with asid = h'70 when the dmac writes byte h'7* in address h'00055555.
rev. 5.00, 09/03, page 179 of 760 7.3.8 notes 1. only cpu can read/write ubc registers. 2. ubc cannot monitor cpu and dmac access in the same channel. 3. notes in specification of sequential break are described below: a. a condition match occurs when b-channel match occurs in a bus cycle after an a-channel match occurs in another bus cycle in sequential break setting. therefore, no condition match occurs even if a bus cycle, in which an a-channel match and a channel b match occur simultaneously, is set. b. since the cpu has a pipeline configuration, the pipeline determines the order of an instruction fetch cycle and a memory cycle. therefore, when a channel condition matches in the order of bus cycles, a sequential condition is satisfied. c. when the bus cycle condition for channel a is specified as a break before execution (pcba = 0 in brcr) and an instruction fetch cycle (in bbra), the attention is as follows. a break is issued and condition match flags in brcr are set to 1, when the bus cycle conditions both for channels a and b match simultaneously. 4. the change of a ubc register value is executed in ma (memory access) stage. therefore, even if the break condition matches in the instruction fetch address following the instruction in which the pre-execution break is specified as the break condition, no break occurs. in order to know the timing ubc register is changed, read the last written register. instructions after then are valid for the newly written register value. 5. the branch instruction should not be executed as soon as pc trace register brsr and brdr are read. 6. when pc breaks and tlb exceptions or errors occur in the same instruction. the priority is as follows: a. break and instruction fetch exceptions: instruction fetch exception occurs first. b. break before execution and operand exception: break before execution occurs first. c. break after execution and operand exception: operand exception occurs first.
rev. 5.00, 09/03, page 180 of 760
rev. 5.00, 09/03, page 181 of 760 section 8 power-down modes 8.1 overview in the power-down modes, all cpu and some on-chip peripheral module functions are halted. this lowers power consumption. 8.1.1 power-down modes the sh7709s has the following power-down modes and function: 1. sleep mode 2. standby mode 3. module standby function (tmu, rtc, sci, ubc, dmac, dac, adc, scif, and irda on- chip peripheral modules) 4. hardware standby mode table 8.1 shows the transition conditions for entering the modes from the program execution state, as well as the cpu and peripheral module states in each mode and the procedures for canceling each mode.
rev. 5.00, 09/03, page 182 of 760 table 8.1 power-down modes state mode transition conditions cpg cpu cpu reg- ister on-chip memory on-chip peripheral modules pins external memory canceling procedure sleep mode execute sleep instruction with stby bit cleared to 0 in stbcr runs halts held held run held refresh 1. interrupt 2. reset standby mode execute sleep instruction with stby bit set to 1 in stbcr halts halts held held halt * 1 held self- refresh 1. interrupt 2. reset module standby function set mstp bit to 1 in stbcr runs runs or halts held held specified module halts * 2 refresh 1. clear mstp bit to 0 2. reset hardware standby mode drive ca pin low halts halts held held halt * 3 held self- refresh power-on reset notes: 1. the rtc still runs if the start bit in rcr2 is set to 1 (see section 13, realtime clock (rtc)). the tmu still runs when output of the rtc is used as input to its counter (see section 12, timer (tmu)). 2. depends on the on-chip peripheral module. tmu external pin: held sci external pin: reset 3. the rtc still runs if the start bit in rcr2 is set to 1. the tmu does not run.
rev. 5.00, 09/03, page 183 of 760 8.1.2 pin configuration table 8.2 lists the pins used for the power-down modes. table 8.2 pin configuration pin name abbreviation i/o description processing state 1 status1 o operating state of the processor. processing state 0 status0 hh: reset, hl: sleep mode, lh: standby mode, ll: normal operation wakeup from standby mode wakeup o active-low assertion after accepting wakeup interrupt in standby mode until returning to normal operation with wdt overflow note: h: high level; l: low level 8.1.3 register configuration table 8.3 shows the control register configuration for the power-down modes. table 8.3 register configuration name abbreviation r/w initial value access size address standby control register stbcr r/w h'00 * h'ffffff82 8 standby control register 2 stbcr2 r/w h'00 * h'ffffff88 8 note: * initialized by a power-on reset. this value is not initialized by a manual reset; the current value is retained. 8.2 register descriptions 8.2.1 standby control register (stbcr) the standby control register (stbcr) is an 8-bit readable/writable register that sets the power- down mode. stbcr is initialized to h'00 by a power-on reset. bit:76543210 stby ? ? stbxtl ? mstp2 mstp1 mstp0 initial value:00000000 r/w: r/w r r r/w r r/w r/w r/w
rev. 5.00, 09/03, page 184 of 760 bit 7?standby (stby): specifies transition to standby mode. bit 7: stby description 0 executing sleep instruction puts chip into sleep mode (initial value) 1 executing sleep instruction puts chip into standby mode bits 6, 5, and 3?reserved: these bits are always read as 0. the write value should always be 0. bit 4?standby crystal (stbxtl): specifies halting or operating of the clock pulse generator in standby mode. bit 4: stbxtl description 0 clock pulse generator is halted in standby mode (initial value) 1 clock pulse generator is operates in standby mode bit 2?module standby 2 (mstp2): specifies halting of the clock supply to the timer unit tmu (an on-chip peripheral module). when the mstp2 bit is set to 1, the supply of the clock to the tmu is halted. bit 2: mstp2 description 0 tmu runs (initial value) 1 clock supply to tmu is halted bit 1?module standby 1 (mstp1): specifies halting of the clock supply to the realtime clock rtc (an on-chip peripheral module). when the mstp1 bit is set to 1, the supply of the clock to the rtc is halted. when the clock halts, all rtc registers become inaccessible, but the counter keeps running. bit 1: mstp1 description 0 rtc runs (initial value) 1 clock supply to rtc is halted before switching the rtc to module standby, access at least one among the registers rtc, sci, and tmu.
rev. 5.00, 09/03, page 185 of 760 bit 0?module standby 0 (mstp0): specifies halting of the clock supply to the serial communication interface sci (an on-chip peripheral module). when the mstp0 bit is set to 1, the supply of the clock to the sci is halted. bit 0: mstp0 description 0 sci operates (initial value) 1 clock supply to sci is halted 8.2.2 standby control register 2 (stbcr2) the standby control register 2 (stbcr2) is a readable/writable 8-bit register that sets the power- down mode. stbcr2 is initialized to h'00 by a power-on reset. bit:76543210 ? mdchg mstp8 mstp7 mstp6 mstp5 mstp4 mstp3 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit 7?reserved: the write value set in the program should always be 1. bit 6?pin md5 to md0 control (mdchg): specifies whether or not pins md5 to md0 are changed in standby mode. when this bit is set to 1, the md5 to md0 pin values are latched when returning from standby mode by means of a reset or interrupt. bit 6: mdchg description 0 pins md5 to md0 are not changed in standby mode (initial value) 1 pins md5 to md0 are changed in standby mode bit 5? module stop 8 (mstp8): specifies halting of the clock supply to the user break controller ubc (an on-chip peripheral module). when the mstp8 bit is set to 1, the supply of the clock to the ubc is halted. bit 5: mstp8 description 0 ubc runs (initial value) 1 clock supply to ubc is halted
rev. 5.00, 09/03, page 186 of 760 bit 4?module stop 7 (mstp7): specifies halting of the clock supply to the dmac (an on-chip peripheral module). when the mstp7 bit is set to 1, the supply of the clock to the dmac is halted. bit 4: mstp7 description 0 dmac runs (initial value) 1 clock supply to dmac halted bit 3?module stop 6 (mstp6): specifies halting of the clock supply to the dac (an on-chip peripheral module). when the mstp6 bit is set to 1, the supply of the clock to the dac is halted. bit 3: mstp6 description 0 dac runs (initial value) 1 clock supply to dac halted bit 2?module stop 5 (mstp5): specifies halting of the clock supply to the adc (an on-chip peripheral module). when the mstp5 bit is set to 1, the supply of the clock to the adc is halted and all registers are initialized. bit 2: mstp5 description 0 adc runs (initial value) 1 clock supply to adc halted and all registers initialized bit 1?module stop 4 (mstp4): specifies halting of the clock supply to the sci2 (scif) serial communication interface with fifo (an on-chip peripheral module). when the mstp1 bit is set to 1, the supply of the clock to sci2 (scif) is halted. bit 1: mstp4 description 0 sci2 (scif) runs (initial value) 1 clock supply to sci2 (scif) halted bit 0?module stop 3 (mstp3): specifies halting of the clock supply to the sci1 (irda) infrared data association interface with fifo (an on-chip peripheral module). when the mstp3 bit is set to 1, the supply of the clock to sci1 (irda) is halted. bit 0: mstp3 description 0 sci1(irda) runs (initial value) 1 clock supply to sci1(irda) halted
rev. 5.00, 09/03, page 187 of 760 8.3 sleep mode 8.3.1 transition to sleep mode executing the sleep instruction when the stby bit in stbcr is 0 causes a transition from the program execution state to sleep mode. although the cpu halts immediately after executing the sleep instruction, the contents of its internal registers remain unchanged. the on-chip peripheral modules continue to run in sleep mode and the clock continues to be output to the ckio and ckio2 pins. in sleep mode, the status1 pin is set high and the status0 pin low. 8.3.2 canceling sleep mode sleep mode is canceled by an interrupt (nmi, irq, irl, on-chip peripheral module, pint) or reset. interrupts are accepted in sleep mode even when the bl bit in the sr register is 1. if necessary, save spc and ssr to the stack before executing the sleep instruction. canceling with an interrupt: when an nmi, irq, irl or on-chip peripheral module interrupt occurs, sleep mode is canceled and interrupt exception handling is executed. a code indicating the interrupt source is set in the intevt and intevt2 registers. canceling with a reset: sleep mode is canceled by a power-on reset or a manual reset. 8.3.3 precautions when using the sleep mode dmac transfers should not be performed in the sleep mode under conditions other than when the clock ratio of i (on-chip clock) to b (bus clock) is 1:1.
rev. 5.00, 09/03, page 188 of 760 8.4 standby mode 8.4.1 transition to standby mode to enter standby mode, set the stby bit to 1 in stbcr, then execute the sleep instruction. the chip switches from the program execution state to standby mode. in standby mode, power consumption is greatly reduced by halting not only the cpu, but the clock and on-chip peripheral modules as well. the clock output from the ckio and ckio2 pins also halts. cpu and cache register contents are held, but some on-chip peripheral modules are initialized. table 8.4 lists the states of registers in standby mode. table 8.4 register states in standby mode module registers initialized registers retaining data interrupt controller (intc) ? all registers on-chip clock pulse generator (osc) ? all registers user break controller (ubc) ? all registers bus state controller (bsc) ? all registers timer unit (tmu) tstr register registers other than tstr realtime clock (rtc) ? all registers a/d converter (adc) all registers ? d/a converter (dac) ? all registers the procedure for moving to standby mode is as follows: 1. clear the tme bit in the wdt?s timer control register (wtcsr) to 0 to stop the wdt. clear the wdt?s timer counter (wtcnt) to 0 and the cks2?cks0 bits in the wtcsr register to appropriate values to secure the specified oscillation settling time. 2. after the stby bit in the stbcr register is set to 1, a sleep instruction is executed. 3. standby mode is entered and the clocks within the chip are halted. the status1 pin output goes low and the status0 pin output goes high.
rev. 5.00, 09/03, page 189 of 760 8.4.2 canceling standby mode standby mode is canceled by an interrupt (nmi, irq, irl, pint, or on-chip peripheral module) or a reset. canceling with an interrupt: the on-chip wdt can be used for hot starts. when the chip detects an nmi, irl, irq, pint * 1 , or on-chip peripheral module (except interval timer) * 2 interrupt, the clock will be supplied to the entire chip and standby mode canceled after the time set in the wdt?s timer control/status register has elapsed. the status1 and status0 pins both go low. interrupt handling then begins and a code indicating the interrupt source is set in the intevt and intevt2 registers. after the branch to the interrupt handling routine, clear the stby bit in the stbcr register. wtcnt stops automatically. if the stby bit is not cleared, wtcnt continues operation and a transition is made to standby mode * 3 when it reaches h'80. this function prevents the data from being destroyed due to a rise in voltage with an unstable power supply, etc. interrupts are accepted in standby mode even when the bl bit in the sr register is 1. if necessary, save spc and ssr to the stack before executing the sleep instruction. immediately after an interrupt is detected, the phase of the ckio pin clock output may be unstable, until the processor starts interrupt handling. (the canceling condition is that the irl3?irl0 level is higher than the mask level in the i3?i0 bits in the sr register.) notes: 1. when the rtc is being used, standby mode can be canceled using irl3?irl0, irq4? irq0, or pint0/1. 2. standby mode can be canceled with an rtc or tmu (only when running on the rtc clock) interrupt. 3. this standby mode can be canceled only by a power-on reset. wtcnt value hff h80 time interrupt request wdt overflow and branch to interrupt handling routine crystal oscillator settling time and pll synchronization time clear bit stbcr.stby before wtcnt reaches h80. when stbcr.stby is cleared, wtcnt halts automatically. figure 8.1 canceling standby mode with stbcr.stby
rev. 5.00, 09/03, page 190 of 760 canceling with a reset: standby mode is canceled by a reset (power-on or manual). keep the reset pin low until the clock oscillation settles. the internal clock will continue to be output to the ckio and ckio2 pins. 8.4.3 clock pause function in standby mode, the clock input from the extal pin or ckio pin can be halted and the frequency can be changed. this function is used as follows: 1. enter standby mode using the appropriate procedures. 2. once standby mode is entered and the clock stopped within the chip, the status1 pin output is low and the status0 pin output is high. 3. once the status1 pin goes low and the status0 pin goes high, the input clock is stopped or the frequency is changed. 4. when the frequency is changed, an nmi, irl, irq, pint, or on-chip peripheral module (except interval timer) interrupt is input after the change. when the clock is stopped, the same interrupts are input after the clock is applied. 5. after the time set in the wdt has elapsed, the clock starts being applied internally within the chip, the status1 and status0 pins both go low, and operation resumes from interrupt exception handling.
rev. 5.00, 09/03, page 191 of 760 8.5 module standby function 8.5.1 transition to module standby function setting the standby control register mstp8?mstp0 bits to 1 halts the supply of clocks to the corresponding on-chip peripheral modules. this function can be used to reduce the power consumption in normal mode and sleep mode. the module standby function holds the state prior to halting the external pins of the on-chip peripheral modules. tmu external pins hold their state prior to the halt. sci external pins go to the reset state. with a few exceptions, all registers hold their values. bit value description mstp8 0 ubc runs 1 supply of clock to ubc halted mstp7 0 dmac runs 1 supply of clock to dmac halted mstp6 0 dac runs 1 supply of clock to dac halted mstp5 0 adc runs 1 supply of clock to adc halted, and all registers initialized mstp4 0 scif runs 1 supply of clock to scif halted mstp3 0 irda runs 1 supply of clock to irda halted mstp2 0 tmu runs 1 supply of clock to tmu halted. registers initialized * 1 mstp1 0 rtc runs 1 supply of clock to rtc halted. register access prohibited * 2 * 3 mstp0 0 sci runs 1 supply of clock to sci halted notes: 1. the registers initialized are the same as in standby mode (see table 8.4). 2. the counter runs. 3. before switching the rtc to module standby, access at least one among the registers rtc, sci, and tmu. 8.5.2 clearing module standby function the module standby function can be cleared by clearing the mstpslp0 and mstp8?mstp0 bits to 0, or by a power-on reset or manual reset.
rev. 5.00, 09/03, page 192 of 760 8.6 timing of status pin changes the timing of status1 and status0 pin changes is shown in figures 8.1 to 8.8. 8.6.1 timing for resets power-on reset ckio, ckio2 * 4 resetp status normal * 2 normal * 2 reset * 1 pll settling time 0 to 5 bcyc * 3 0 to 30 bcyc * 3 resetout notes: 1. reset: hh (status1 high, status0 high) 2. normal: ll (status1 low, status0 low) 3. bcyc: bus clock cycle 4. the ckio2 output is available only in clock modes 0, 1, and 2. figure 8.2 power-on reset (clock modes 0, 1, 2, and 7) status output
rev. 5.00, 09/03, page 193 of 760 manual reset ckio, ckio2 * 5 resetm status normal * 3 normal * 3 reset * 2 0 bcyc or more * 4 0 to 30 bcyc * 4 resetout notes: 1. in a manual reset, status becomes hh (reset) and the internal reset begins after waiting for the executing bus cycle to end. 2. reset: hh (status1 high, status0 high) 3. normal: ll (status1 low, status0 low) 4. bcyc: bus clock cycle 5. the ckio2 output is available only in clock modes 0, 1, and 2. figure 8.3 manual reset status output
rev. 5.00, 09/03, page 194 of 760 8.6.2 timing for canceling standby standby to interrupt ckio, ckio2 * 3 status normal * 2 normal * 2 wdt count oscillation stops standby * 1 interrupt request wdt overflow wakeup notes: 1. standby: lh (status1 low, status0 high) 2. normal: ll (status1 low, status0 low) 3. the ckio2 output is available only in clock modes 0, 1, and 2. figure 8.4 standby to interrupt status output
rev. 5.00, 09/03, page 195 of 760 standby to power-on reset ckio, ckio2 * 7 status normal * 5 normal * 5 oscillation stops standby * 4 0 to 10 bcyc * 6 0 to 30 bcyc * 6 reset reset * 3 resetp * 1 * 2 notes: 1. when standby mode is cleared with a power-on reset, the wdt does not count. keep resetp low during the pll s oscillation settling time. 2. undefined 3. reset: hh (status1 high, status0 high) 4. standby: lh (status1 low, status0 high) 5. normal: ll (status1 low, status0 low) 6. bcyc: bus clock cycle 7. the ckio2 output is available only in clock modes 0, 1, and 2. figure 8.5 standby to power-on reset status output
rev. 5.00, 09/03, page 196 of 760 standby to manual reset ckio, ckio2 * 6 status normal * 4 normal * 4 oscillation stops standby * 3 reset * 2 0 to 20 bcyc * 5 reset resetm * 1 notes: 1. when standby mode is cleared with a manual reset, the wdt does not count. keep resetm low during the pll s oscillation settling time. 2. reset: hh (status1 high, status0 high) 3. standby: lh (status1 low, status0 high) 4. normal: ll (status1 low, status0 low) 5. bcyc: bus clock cycle 6. the ckio2 output is available only in clock modes 0, 1, and 2. figure 8.6 standby to manual reset status output 8.6.3 timing for canceling sleep mode sleep to interrupt ckio, ckio2 * 3 status normal * 2 normal * 2 sleep * 1 interrupt request notes: 1. sleep: hl (status1 high, status0 low) 2. normal: ll (status1 low, status0 low) 3. the ckio2 output is available only in clock modes 0, 1, and 2. figure 8.7 sleep to interrupt status output
rev. 5.00, 09/03, page 197 of 760 sleep to power-on reset ckio, ckio2 * 7 status normal * 5 normal * 5 sleep * 4 0 to 10 bcyc * 6 0 to 30 bcyc * 6 reset reset * 3 * 2 resetp * 1 notes: 1. when the pll1 s multiplication ratio is changed by a power-on reset, keep resetp low during the pll s oscillation settling time. 2. undefined 3. reset: hh (status1 high, status0 high) 4. sleep: hl (status1 high, status0 low) 5. normal: ll (status1 low, status0 low) 6. bcyc: bus clock cycle 7. the ckio2 output is available only in clock modes 0, 1, and 2. figure 8.8 sleep to power-on reset status output
rev. 5.00, 09/03, page 198 of 760 sleep to manual reset ckio, ckio2 * 6 0 to 80 bcyc * 5 0 to 30 bcyc * 5 reset status normal * 4 normal * 4 sleep * 3 reset * 2 resetm * 1 notes: 1. keep resetm low until status becomes reset. 2. reset: hh (status1 high, status0 high) 3. sleep: hl (status1 high, status0 low) 4. normal: ll (status1 low, status0 low) 5. bcyc: bus clock cycle 6. the ckio2 output is available only in clock modes 0, 1, and 2. figure 8.9 sleep to manual reset status output
rev. 5.00, 09/03, page 199 of 760 8.7 hardware standby mode 8.7.1 transition to hardware standby mode driving the ca pin low causes a transition to hardware standby mode. in hardware standby mode, all modules except those operating on an rtc clock are halted, as in the standby mode entered on execution of a sleep instruction ((software) standby mode). hardware standby mode differs from (software) standby mode as follows. 1. interrupts and manual resets are not accepted. 2. the tmu does not operate. operation when a low-level signal is input at the ca pin depends on the cpg state, as follows. 1. in standby mode the clock remains stopped and the chip enters the hardware standby state. acceptance of interrupts and manual resets is disabled, tclk output is fixed low, and the tmu halts. 2. during wdt operation when standby mode is canceled by an interrupt the chip enters hardware standby mode after standby mode is canceled and the cpu resumes operation. 3. in sleep mode the chip enters hardware standby mode after sleep mode is canceled and the cpu resumes operation. hold the ca pin low in hardware standby mode. 8.7.2 canceling hardware standby mode hardware standby mode can only be canceled by a power-on reset. when the ca pin is driven high while the resetp pin is low, clock oscillation is started. hold the resetp pin low until clock oscillation stabilizes. when the resetp pin is driven high, the cpu begins power-on reset processing. operation is not guaranteed in the event of an interrupt or manual reset.
rev. 5.00, 09/03, page 200 of 760 8.7.3 hardware standby mode timing figures 8.10 and 8.11 show examples of pin timing in hardware standby mode. the ca pin is sampled using extal2 (32.768 khz), and a hardware standby request is only recognized when the pin is low for two consecutive clock cycles. the ca pin must be held low while the chip is in hardware standby mode. clock oscillation starts when the ca pin is driven high after the resetp pin is driven low. normal * 3 status ca ckio, ckio2 * 6 standby * 2 reset * 1 resetp undefined rcyc: extal2 (32.768 khz) cycle 2 rcyc or more * 5 0 ? 10bcyc * 4 notes: 1. reset: hh (status1 high, status0 high) 2. standby: lh (status1 low, status0 high) 3. normal: ll (status1 low, status0 low) 4. bcyc: bus clock cycle 5. rcyc: extal2 (32.768 khz) cycle 6. the ckio2 output is available only in clock modes 0, 1, and 2. figure 8.10 hardware standby mode (when ca goes low in normal operation)
rev. 5.00, 09/03, page 201 of 760 normal * 3 status ca ckio, ckio2 * 6 standby * 2 reset * 1 resetp undefined 2 rcyc or more * 5 0 ? 10 bcyc * 4 standby wdt operation notes: 1. reset: hh (status1 high, status0 high) 2. standby: lh (status1 low, status0 high) 3. normal: ll (status1 low, status0 low) 4. bcyc: bus clock cycle 5. rcyc: extal2 (32.768 khz) cycle 6. the ckio2 output is available only in clock modes 0, 1, and 2. figure 8.11 hardware standby mode timing (when ca goes low during wdt operation on standby mode cancellation)
rev. 5.00, 09/03, page 202 of 760
rev. 5.00, 09/03, page 203 of 760 section 9 on-chip oscillation circuits 9.1 overview the on-chip oscillation circuits consist of a clock pulse generator (cpg) block and a watchdog timer (wdt) block. the wdt is a single-channel timer that counts the clock settling time and is used when clearing standby mode and temporary standbys, such as frequency changes. it can also be used as an ordinary watchdog timer or interval timer. 9.1.1 features the cpg has the following features: ? four clock modes: selection of four clock modes for different frequency ranges, power consumption, direct crystal input, and external clock input. ? three clocks generated independently: an internal clock for the cpu, cache, and tlb (i ); a peripheral clock (p ) for the on-chip peripheral modules; and a bus clock (ckio) for the external bus interface. ? frequency change function: internal and peripheral clock frequencies can be changed independently using the pll circuit and divider circuit within the cpg. frequencies are changed by software using frequency control register (frqcr) settings. ? power-down mode control: the clock can be stopped for sleep mode and standby mode and specific modules can be stopped using the module standby function. the wdt has the following features: ? can be used to ensure the clock settling time: use the wdt to cancel standby mode and the temporary standbys which occur when the clock frequency is changed. ? can switch between watchdog timer mode and interval timer mode. ? generates internal resets in watchdog timer mode: internal resets occur after counter overflow. selection of power-on reset or manual reset. ? generates interrupts in interval timer mode: internal timer interrupts occur after counter overflow. ? selection of eight counter input clocks. eight clocks ( 1 to 1/4096) can be obtained by dividing the peripheral clock.
rev. 5.00, 09/03, page 204 of 760 9.2 overview of cpg 9.2.1 cpg block diagram a block diagram of the on-chip clock pulse generator is shown in figure 9.1. cap1 ckio cycle = bcyc cap2 xtal extal md2 md1 md0 frqcr internal bus bus interface stbcr pll circuit 1 ( 1, 2, 3, 4, 6) divider 1 internal clock (i ) cycle = icyc peripheral clock (p ) cycle = pcyc standby control divider 2 clock pulse generator pll circuit 2 ( 1, 4) crystal oscillator cpg control unit clock frequency control circuit standby control circuit 1 1/2 1/3 1/4 1/6 1 1/2 1/3 1/4 1/6 legend frqcr: frequency control register stbcr: standby control register figure 9.1 block diagram of clock pulse generator
rev. 5.00, 09/03, page 205 of 760 the clock pulse generator blocks function as follows: 1. pll circuit 1: pll circuit 1 doubles, triples, quadruples, sextuples, or leaves unchanged the input clock frequency from the ckio pin. the multiplication rate is set by the frequency control register. when this is done, the phase of the leading edge of the internal clock is controlled so that it will agree with the phase of the leading edge of the ckio pin. 2. pll circuit 2: pll circuit 2 leaves unchanged or quadruples the frequency of the crystal oscillator or the input clock frequency from the extal pin. the multiplication ratio is fixed by the clock operation mode. the clock operation mode is set by pins md0, md1, and md2. see table 9.3 for more information on clock operation modes. 3. crystal oscillator: this oscillator is used when a crystal oscillator element is connected to the xtal and extal pins. it operates according to the clock operating mode setting. 4. divider 1: divider 1 generates a clock at the operating frequency used by the internal clock. the operating frequency can be 1, 1/2, 1/3, 1/4 or 1/6 times the output frequency of pll circuit 1, as long as it is not lower than the ckio pin clock frequency. the division ratio is set in the frequency control register. 5. divider 2: divider 2 generates a clock at the operating frequency used by the peripheral clock. the operating frequency can be 1, 1/2, 1/3, 1/4 or 1/6 times the output frequency of pll circuit 1 or the ckio pin clock frequency, as long as it is not higher than the ckio pin clock frequency. the division ratio is set in the frequency control register. 6. clock frequency control circuit: the clock frequency control circuit controls the clock frequency using the md pins and the frequency control register. 7. standby control circuit: the standby control circuit controls the state of the clock pulse generator and other modules during clock switching and sleep/standby modes. 8. frequency control register: the frequency control register has control bits assigned for the following functions: the frequency multiplication ratio of pll 1, and the frequency division ratio of the internal clock and the peripheral clock. 9. standby control register: the standby control register has bits for controlling the power-down modes. see section 8, power-down modes, for more information.
rev. 5.00, 09/03, page 206 of 760 9.2.2 cpg pin configuration table 9.1 lists the cpg pins and their functions. table 9.1 cpg pins and functions pin name symbol i/o description md0 i set the clock operating mode md1 i mode control pins md2 i xtal o connects a crystal oscillator crystal i/o pins (clock input pins) extal i connects a crystal oscillator. also used to input an external clock clock i/o pin ckio i/o inputs or outputs an external clock cap1 i connects capacitor for pll circuit 1 operation (recommended value 470 pf) capacitor connection pins for pll cap2 i connects capacitor for pll circuit 2 operation (recommended value 470 pf) 9.2.3 cpg register configuration table 9.2 shows the cpg register configuration. table 9.2 cpg register register name abbreviation r/w initial value address access size frequency control register frqcr r/w h'0102 h'ffffff80 16
rev. 5.00, 09/03, page 207 of 760 9.3 clock operating modes table 9.3 shows the relationship between the mode control pin (md2?md0) combinations and the clock operating modes. table 9.4 shows the usable frequency ranges in the clock operating modes. table 9.3 clock operating modes pin values clock i/o mode md2 md1 md0 source output pll2 on/off pll1 on/off divider 1 input divider 2 input ckio frequency 0 0 0 0 extal ckio on, multi- plication ratio: 1 on pll1 output pll1 (extal) 1 0 0 1 extal ckio on, multi- plication ratio: 4 on pll1 output pll1 (extal) 4 2 010 crystal oscillator ckio on, multi- plication ratio: 4 on pll1 output pll1 (crystal) 4 7 1 1 1 ckio ? off on pll1 output pll1 (ckio) ? except above value reserved mode 0: an external clock is input from the extal pin and undergoes waveform shaping by pll circuit 2 before being supplied inside the chip. pll circuit 1 is constantly on. an input clock frequency of 25 mhz to 66.67 mhz can be used, and the ckio frequency range is 25 mhz to 66.67 mhz. mode 1: an external clock is input from the extal pin and its frequency is multiplied by 4 by pll circuit 2 before being supplied inside the chip, allowing a low-frequency external clock to be used. an input clock frequency of 6.25 mhz to 16.67 mhz can be used, and the ckio frequency range is 25 mhz to 66.67 mhz. mode 2: the on-chip crystal oscillator operates, with the oscillation frequency being multiplied by 4 by pll circuit 2 before being supplied inside the chip, allowing a low crystal frequency to be used. a crystal oscillation frequency of 6.25 mhz to 16.67 mhz can be used, and the ckio frequency range is 25 mhz to 66.67 mhz.
rev. 5.00, 09/03, page 208 of 760 mode 7: in this mode, the ckio pin is an input, an external clock is input to this pin, and undergoes waveform shaping, and also frequency multiplication according to the setting, by pll circuit 1 before being supplied to the chip. in modes 0 to 2, the system clock is generated from the output of the chip?s ckio pin. consequently, if a large number of ics are operating on the clock cycle, the ckio pin load will be large. this mode, however, assumes a comparatively large-scale system. if a large number of ics are operating on the clock cycle, a clock generator with a number of low-skew clock outputs can be provided, so that the ics can operate synchronously by distributing the clocks to each one. as pll circuit 1 compensates for fluctuations in the ckio pin load, this mode is suitable for connection of synchronous dram. table 9.4 available combinations of clock mode and frqcr values clock mode frqcr pll1 pll2 clock rate * (i:b:p) input frequency range ckio frequency range 0 h'0100 on ( 1) on ( 1) 1:1:1 25 mhz to 33.34 mhz 25 mhz to 33.34 mhz h'0101 on ( 1) on ( 1) 1:1:1/2 25 mhz to 66.67 mhz 25 mhz to 66.67 mhz h'0102 on ( 1) on ( 1) 1:1:1/4 25 mhz to 66.67 mhz 25 mhz to 66.67 mhz h'0111 on ( 2) on ( 1) 2:1:1 25 mhz to 33.34 mhz 25 mhz to 33.34 mhz h'0112 on ( 2) on ( 1) 2:1:1/2 25 mhz to 66.67 mhz 25 mhz to 66.67 mhz h'0115 on ( 2) on ( 1) 1:1:1 25 mhz to 33.34 mhz 25 mhz to 33.34 mhz h'0116 on ( 2) on ( 1) 1:1:1/2 25 mhz to 66.67 mhz 25 mhz to 66.67 mhz h'0122 on ( 4) on ( 1) 4:1:1 25 mhz to 33.34 mhz 25 mhz to 33.34 mhz h'0126 on ( 4) on ( 1) 2:1:1 25 mhz to 33.34 mhz 25 mhz to 33.34 mhz h'012a on ( 4) on ( 1) 1:1:1 25 mhz to 33.34 mhz 25 mhz to 33.34 mhz h'a100 on ( 3) on ( 1) 3:1:1 25 mhz to 33.34 mhz 25 mhz to 33.34 mhz h'a101 on ( 3) on ( 1) 3:1:1/2 25 mhz to 66.67 mhz 25 mhz to 66.67 mhz h'e100 on ( 3) on ( 1) 1:1:1 25 mhz to 33.34 mhz 25 mhz to 33.34 mhz h'e101 on ( 3) on ( 1) 1:1:1/2 25 mhz to 66.67 mhz 25 mhz to 66.67 mhz h'a111 on ( 6) on ( 1) 6:1:1 25 mhz to 33.34 mhz 25 mhz to 33.34 mhz
rev. 5.00, 09/03, page 209 of 760 clock mode frqcr pll1 pll2 clock rate * (i:b:p) input frequency range ckio frequency range 1, 2 h'0100 on ( 1) on ( 4) 4:4:4 6.25 mhz to 8.34 mhz 25 mhz to 33.34 mhz h'0101 on ( 1) on ( 4) 4:4:2 6.25 mhz to 16.67 mhz 25 mhz to 66.67 mhz h'0102 on ( 1) on ( 4) 4:4:1 6.25 mhz to 16.67 mhz 25 mhz to 66.67 mhz h'0111 on ( 2) on ( 4) 8:4:4 6.25 mhz to 8.34 mhz 25 mhz to 33.34 mhz h'0112 on ( 2) on ( 4) 8:4:2 6.25 mhz to 16.67 mhz 25 mhz to 66.67 mhz h'0115 on ( 2) on ( 4) 4:4:4 6.25 mhz to 8.34 mhz 25 mhz to 33.34 mhz h'0116 on ( 2) on ( 4) 4:4:2 6.25 mhz to 16.67 mhz 25 mhz to 66.67 mhz h'0122 on ( 4) on ( 4) 16:4:4 6.25 mhz to 8.34 mhz 25 mhz to 33.34 mhz h'0126 on ( 4) on ( 4) 8:4:4 6.25 mhz to 8.34 mhz 25 mhz to 33.34 mhz h'012a on ( 4) on ( 4) 4:4:4 6.25 mhz to 8.34 mhz 25 mhz to 33.34 mhz h'a100 on ( 3) on ( 4) 12:4:4 6.25 mhz to 8.34 mhz 25 mhz to 33.34 mhz h'a101 on ( 3) on ( 4) 12:4:2 6.25 mhz to 16.67 mhz 25 mhz to 66.67 mhz h'e100 on ( 3) on ( 4) 4:4:4 6.25 mhz to 8.34 mhz 25 mhz to 33.34 mhz h'e101 on ( 3) on ( 4) 4:4:2 6.25 mhz to 16.67 mhz 25 mhz to 66.67 mhz h'a111 on ( 6) on ( 4) 24:4:4 6.25 mhz to 8.34 mhz 25 mhz to 33.34 mhz 7 h'0100 on ( 1) off 1:1:1 25 mhz to 33.34 mhz 25 mhz to 33.34 mhz h'0101 on ( 1) off 1:1:1/2 25 mhz to 66.67 mhz 25 mhz to 66.67 mhz h'0102 on ( 1) off 1:1:1/4 25 mhz to 66.67 mhz 25 mhz to 66.67 mhz h'0111 on ( 2) off 2:1:1 25 mhz to 33.34 mhz 25 mhz to 33.34 mhz h'0112 on ( 2) off 2:1:1/2 25 mhz to 66.67 mhz 25 mhz to 66.67 mhz h'0115 on ( 2) off 1:1:1 25 mhz to 33.34 mhz 25 mhz to 33.34 mhz h'0116 on ( 2) off 1:1:1/2 25 mhz to 66.67 mhz 25 mhz to 66.67 mhz h'0122 on ( 4) off 4:1:1 25 mhz to 33.34 mhz 25 mhz to 33.34 mhz h'0126 on ( 4) off 2:1:1 25 mhz to 33.34 mhz 25 mhz to 33.34 mhz h'012a on ( 4) off 1:1:1 25 mhz to 33.34 mhz 25 mhz to 33.34 mhz h'a100 on ( 3) off 3:1:1 25 mhz to 33.34 mhz 25 mhz to 33.34 mhz h'a101 on ( 3) off 3:1:1/2 25 mhz to 66.67 mhz 25 mhz to 66.67 mhz h'e100 on ( 3) off 1:1:1 25 mhz to 33.34 mhz 25 mhz to 33.34 mhz h'e101 on ( 3) off 1:1:1/2 25 mhz to 66.67 mhz 25 mhz to 66.67 mhz h'a111 on ( 6) off 6:1:1 25 mhz to 33.34 mhz 25 mhz to 33.34 mhz do not set values other than those in the table above in the frqcr register. note: * taking input clock as 1.
rev. 5.00, 09/03, page 210 of 760 cautions: 1. the frequency of the internal clock (i ) becomes: ? the product of the frequency of the ckio pin, the frequency multiplication ratio of pll circuit 1, and the division ratio of divider 1. ? do not set the internal clock frequency lower than the ckio pin frequency. 2. the frequency of the peripheral clock (p ) becomes: ? the product of the frequency of the ckio pin, the frequency multiplication ratio of pll circuit 1, and the division ratio of divider 2. ? the peripheral clock frequency should not be set higher than the frequency of the ckio pin, higher than 33.34 mhz. 3. the output frequency of pll circuit 1 is the product of the ckio frequency and the multiplication ratio of pll circuit 1. 4. 1, 2, 3, 4, or 6 can be used as the multiplication ratio of pll circuit 1. 1, 1/2, 1/ 3, 1/4, and 1/6 can be selected as the division ratios of dividers 1 and 2. set the rate in the frequency control register. the on/off state of pll circuit 2 is determined by the mode.
rev. 5.00, 09/03, page 211 of 760 9.4 register descriptions 9.4.1 frequency control register (frqcr) the frequency control register (frqcr) is a 16-bit readable/writable register used to specify the frequency multiplication ratio of pll circuit 1 and the frequency division ratio of the internal clock and the peripheral clock. only word access can be used on the frqcr register. frqcr is initialized to h'0102 by a power-on reset, but retains its value in a manual reset and in standby mode. frqcr: bit: 15 14 13 12 11 10 9 8 stc2ifc2pfc2????? initial value:00000001 r/w:r/wr/wr/wrrrrr bit:76543210 ? ? stc1 stc0 ifc1 ifc0 pfc1 pfc0 initial value:00000010 r/w: r r r/w r/w r/w r/w r/w r/w bits 15, 5, and 4?frequency multiplication ratio (stc): these bits specify the frequency multiplication ratio of pll circuit 1. bit 15: stc2 bit 5: stc1 bit 4: stc0 description 000 1 (initial value) 001 2 100 3 010 4 101 6 except above value reserved
rev. 5.00, 09/03, page 212 of 760 bits 14, 3, and 2?internal clock frequency division ratio (ifc): these bits specify the frequency division ratio of the internal clock with respect to the output frequency of pll circuit 1. bit 14: ifc2 bit 3: ifc1 bit 2: ifc0 description 000 1 (initial value) 001 1/2 100 1/3 010 1/4 except above value reserved (setting prohibited) note: do not set the internal clock frequency lower than the ckio pin frequency. bits 13, 1, and 0?peripheral clock frequency division ratio (pfc): these bits specify the division ratio of the peripheral clock frequency with respect to the frequency of the output frequency of pll circuit 1 or the frequency of the ckio pin. bit 13: pfc2 bit 1: pfc1 bit 0: pfc0 description 000 1 001 1/2 100 1/3 010 1/4 (initial value) 101 1/6 except above value reserved (setting prohibited) note: do not set the peripheral clock frequency higher than the ckio pin frequency. bits 12 to 9, 7, and 6?reserved: these bits are always read as 0. the write value should always be 0. bit 8?reserved: this bit is always read as 1. the write value should always be 1.
rev. 5.00, 09/03, page 213 of 760 9.5 changing the frequency the frequency of the internal clock and peripheral clock can be changed either by changing the multiplication ratio of pll circuit 1 or by changing the division ratios of dividers 1 and 2. all of these are controlled by software through the frequency control register. the methods are described below. to the frqcr register, do not set values other than those given in table 9.4. 9.5.1 changing the multiplication rate a pll settling time is required when the multiplication rate of pll circuit 1 is changed. the on- chip wdt counts the settling time. 1. in the initial state, the multiplication rate of pll circuit 1 is 1. 2. set a value that will become the specified oscillation settling time in the wdt and stop the wdt. the following must be set: wtcsr register tme bit = 0: wdt stops wtcsr register cks2?cks0 bits: division ratio of wdt count clock wtcnt counter: initial counter value 3. set the desired value in the stc2 to stc0 bits. the division ratio can also be set in the ifc2? ifc0 bits and pfc2?pfc0 bits. 4. the processor pauses internally and the wdt starts incrementing. in clock modes 0?2 and 7, the internal and peripheral clocks both stop. (except for the peripheral clock supplied to the wdt) 5. supply of the clock that has been set begins at wdt count overflow, and the processor begins operating again. the wdt stops after it overflows. when the following three conditions are all met, frqcr should not be changed while a dmac transfer is in progress. ? bits ifc2 to ifc0 are changed. ? stc2 to stc0 are not changed. ? the clock ratio of i (on-chip clock) to b (bus clock) after the change is other than 1:1. 9.5.2 changing the division ratio the wdt will not count unless the multiplication ratio is changed simultaneously. 1. in the initial state, ifc2?ifc0 = 000 and pfc2?pfc0 = 010. 2. set the ifc2, ifc1, ifc0, pfc2, pfc1, and pfc0 bits to the new division ratio. the values that can be set are limited by the clock mode and the multiplication ratio of pll circuit 1. note that if the wrong value is set, the processor will malfunction. 3. the clock is immediately supplied at the new division ratio.
rev. 5.00, 09/03, page 214 of 760 9.6 overview of wdt 9.6.1 block diagram of wdt figure 9.2 shows a block diagram of the wdt. wtcsr standby control bus interface wtcnt divider clock selector clock standby mode peripheral clock standby cancellation reset control clock selection wdt overflow internal reset request interrupt control interrupt request wtcsr: wtcnt: legend watchdog timer control/status register watchdog timer counter figure 9.2 block diagram of wdt 9.6.2 register configuration the wdt has two registers that select the clock, switch the timer mode, and perform other functions. table 9.5 shows the wdt registers. table 9.5 register configuration name abbreviation r/w initial value address access size watchdog timer counter wtcnt r/w * h'00 h'ffffff84 r: 8; w: 16 * watchdog timer control/status register wtcsr r/w * h'00 h'ffffff86 r: 8; w: 16 * note: * write with word access. write with h'5a and h'a5, respectively, in the upper byte. byte or longword writes are not possible. read with byte access.
rev. 5.00, 09/03, page 215 of 760 9.7 wdt registers 9.7.1 watchdog timer counter (wtcnt) the watchdog timer counter (wtcnt) is an 8-bit readable/writable counter that increments on the selected clock. wtcnt differs from other registers in that it is more difficult to write to. see section 9.7.3, notes on register access, for details. when an overflow occurs, it generates a reset in watchdog timer mode and an interrupt in interval time mode. its address is h'ffffff84. the wtcnt counter is initialized to h'00 only by a power-on reset through the resetp pin. use word access to write to the wtcnt counter, with h'5a in the upper byte. use byte access to read wtcnt. bit:76543210 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 9.7.2 watchdog timer control/status register (wtcsr) the watchdog timer control/status register (wtcsr) is an 8-bit readable/writable register composed of bits to select the clock used for the count, bits to select the timer mode, and overflow flags. wtcsr differs from other registers in that it is more difficult to write to. see section 9.7.3, notes on register access, for details. its address is h'ffffff86. the wtcsr register is initialized to h'00 only by a power-on reset through the resetp pin. when a wdt overflow causes an internal reset, wtcsr retains its value. when used to count the clock settling time for canceling a standby, it retains its value after counter overflow. use word access to write to the wtcsr counter, with h'a5 in the upper byte. use byte access to read wtcsr. bit:76543210 tme wt/ it rsts wovf iovf cks2 cks1 cks0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit 7?timer enable (tme): starts and stops timer operation. clear this bit to 0 when using the wdt in standby mode or when changing the clock frequency. bit 7: tme description 0 timer disabled: count-up stops and wtcnt value is retained (initial value) 1 timer enabled
rev. 5.00, 09/03, page 216 of 760 bit 6?timer mode select (wt/ it it it it ): selects whether to use the wdt as a watchdog timer or an interval timer. bit 6: wt/ it it it it description 0 used as interval timer (initial value) 1 used as watchdog timer note: if wt/ it is modified when the wdt is running, the up-count may not be performed correctly. bit 5?reset select (rsts): selects the type of reset when wtcnt overflows in watchdog timer mode. in interval timer mode, this setting is ignored. bit 5: rsts description 0 power-on reset (initial value) 1 manual reset note: resetout is output. bit 4?watchdog timer overflow (wovf): indicates that the wtcnt has overflowed in watchdog timer mode. this bit is not set in interval timer mode. bit 4: wovf description 0 no overflow (initial value) 1 wtcnt has overflowed in watchdog timer mode bit 3?interval timer overflow (iovf): indicates that wtcnt has overflowed in interval timer mode. this bit is not set in watchdog timer mode. bit 3: iovf description 0 no overflow (initial value) 1 wtcnt has overflowed in interval timer mode bits 2 to 0?clock select 2 to 0 (cks2 to cks0): these bits select the clock to be used for the wtcnt count from the eight types obtainable by dividing the peripheral clock. the overflow period in the table is the value when the peripheral clock (p ) is 15 mhz.
rev. 5.00, 09/03, page 217 of 760 bit 2: cks2 bit 1: cks1 bit 0: cks0 clock division ratio overflow period (when p = 15 mhz) 0001(initial value)17 s 1 1/4 68 s 101/16 273 s 1 1/32 546 s 1001/64 1.09 ms 1 1/256 4.36 ms 1 0 1/1024 17.48 ms 1 1/4096 69.91 ms note: if bits cks2?cks0 are modified when the wdt is running, the up-count may not be performed correctly. ensure that these bits are modified only when the wdt is not running. 9.7.3 notes on register access the watchdog timer counter (wtcnt) and watchdog timer control/status register (wtcsr) are more difficult to write to than other registers. the procedure for writing to these registers is given below. writing to wtcnt and wtcsr: these registers must be written to using a word transfer instruction. they cannot be written to with a byte or longword transfer instruction. when writing to wtcnt, set the upper byte to h'5a and transfer the lower byte as the write data, as shown in figure 9.3. when writing to wtcsr, set the upper byte to h'a5 and transfer the lower byte as the write data. this transfer procedure writes the lower byte data to wtcnt or wtcsr. 15 8 7 0 h5a write data address: hffffff84 wtcnt write 15 8 7 0 ha5 write data address: hffffff86 wtcsr write figure 9.3 writing to wtcnt and wtcsr
rev. 5.00, 09/03, page 218 of 760 9.8 using the wdt 9.8.1 canceling standby the wdt can be used to cancel standby mode with an nmi or other interrupt. the procedure is described below. (the wdt does not run when a reset is used for canceling, so keep the reset pin low until the clock stabilizes.) 1. before transitioning to standby mode, always clear the tme bit in wtcsr to 0. when the tme bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. set the type of count clock used in the cks2?cks0 bits in wtcsr and the initial values for the counter in the wtcnt counter. these values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. switch to standby mode by executing a sleep instruction to stop the clock. 4. the wdt starts counting by detecting the edge change of the nmi signal or detecting interrupts. 5. when the wdt count overflows, the cpg starts supplying the clock and the processor resumes operation. the wovf flag in wtcsr is not set when this happens. 6. since the wdt continues counting from h'00, set the stby bit in the stbcr register to 0 in the interrupt handling routine and this will stop the wdt. when the stby bit remains at 1, the sh7709s again enters standby mode when the wdt has counted up to h'80. this standby mode can be canceled by a power-on reset. 9.8.2 changing the frequency to change the frequency used by the pll, use the wdt. when changing the frequency only by switching the divider, do not use the wdt. 1. before changing the frequency, always clear the tme bit in wtcsr to 0. when the tme bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. set the type of count clock used in the cks2?cks0 bits of wtcsr and the initial values for the counter in the wtcnt counter. these values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. when the frequency control register (frqcr) is written to, the clock stops and the processor enters standby mode temporarily. the wdt starts counting. 4. when the wdt count overflows, the cpg resumes supplying the clock and the processor resumes operation. the wovf flag in wtcsr is not set when this happens. 5. the counter stops at a value of h'00 or h'01. the stop value depends on the clock ratio.
rev. 5.00, 09/03, page 219 of 760 when the following three conditions are all met, frqcr should not be changed while a dmac transfer is in progress. ? bits ifc2 to ifc0 are changed. ? stc2 to stc0 are not changed. ? the clock ratio of i (on-chip clock) to b (bus clock) after the change is other than 1:1. 9.8.3 using watchdog timer mode 1. set the wt/ it bit in the wtcsr register to 1, set the reset type in the rsts bit, set the type of count clock in the cks2?cks0 bits, and set the initial value of the counter in the wtcnt counter. 2. set the tme bit in wtcsr to 1 to start the count in watchdog timer mode. 3. while operating in watchdog timer mode, rewrite the counter periodically to h'00 to prevent the counter from overflowing. 4. when the counter overflows, the wdt sets the wovf flag in wtcsr to 1 and generates the type of reset specified by the rsts bit. the counter then resumes counting. when a reset is generated, a low level is output at the resetout pin, and a high level at the status0 and status1 pins. the output period is approximately 1 count clock cycle in the case of a power- on reset, and approximately 5 peripheral clock cycles in the case of a manual reset. 9.8.4 using interval timer mode when operating in interval timer mode, interval timer interrupts are generated at every overflow of the counter. this enables interrupts to be generated at set periods. 1. clear the wt/ it bit in the wtcsr register to 0, set the type of count clock in the cks2? cks0 bits, and set the initial value of the counter in the wtcnt counter. 2. set the tme bit in wtcsr to 1 to start the count in interval timer mode. 3. when the counter overflows, the wdt sets the iovf flag in wtcsr to 1 and an interval timer interrupt request is sent to the intc. the counter then resumes counting.
rev. 5.00, 09/03, page 220 of 760 9.9 notes on board design when using an external crystal resonator: place the crystal resonator, capacitors cl1 and cl2 close to the extal and xtal pins. to prevent induction from interfering with correct oscillation, use a common grounding point for the capacitors connected to the resonator, and do not locate a wiring pattern near these components. note: the values for cl1 and cl2 should be determined after consultation with the crystal manufacturer. xtal extal sh7709s cl2 cl1 avoid crossing signal lines figure 9.4 points for attention when using crystal resonator decoupling capacitors: insert a laminated ceramic capacitor of 0.1 to 1 f as a passive capacitor for each v ss /v cc pair. mount the passive capacitors close to the sh7709s power supply pins, and use components with a frequency characteristic suitable for the chip?s operating frequency, as well as a suitable capacitance value. digital system v ss /v cc pairs: 19-21, 27-29, 33-35, 45-47, 57-59, 69-71, 79-81, 83-85, 95-97, 109- 111, 132-134, 153-154, 161-163, 173-175, 181-183, 205-208 on-chip oscillator v ss /v cc pairs: 3-6, 145-147, 148-150 note: the pin numbers above apply to lqfp and hqfp packages. when using a pll oscillator circuit: keep the wiring from the pll v cc and v ss connection pattern to the power supply pins short, and make the pattern width large, to minimize the inductance component. ground the oscillation stabilization capacitors c1 and c2 to v ss (pll1) and v ss (pll2), respectively. place c1 and c2 close to the cap1 and cap2 pins and do not locate a wiring pattern in the vicinity. in clock mode 7, connect the extal pin to v cc or v ss and leave the xtal pin open.
rev. 5.00, 09/03, page 221 of 760 cap2 v cc (pll2) v cc (pll1) v cc c1 = 470 pf c2 = 470 pf v ss cap1 v ss (pll2) v ss (pll1) avoid crossing signal lines power supply reference values c2 c1 figure 9.5 points for attention when using pll oscillator circuit
rev. 5.00, 09/03, page 222 of 760
rev. 5.00, 09/03, page 223 of 760 section 10 bus state controller (bsc) 10.1 overview the bus state controller (bsc) divides physical address space and output control signals for various types of memory and bus interface specifications. bsc functions enable the chip to link directly with synchronous dram, sram, rom, and other memory storage devices without an external circuit. the bsc also allows direct connection to pcmcia interfaces, simplifying system design and allowing high-speed data transfers in a compact system. 10.1.1 features the bsc has the following features: ? physical address space is divided into six areas ? a maximum 64 mbytes for each of the six areas, 0, 2?6 ? area bus width can be selected by register (area 0 is set by external pin) ? wait states can be inserted using the wait pin ? wait state insertion can be controlled through software. register settings can be used to specify the insertion of 1?10 cycles independently for each area (1?38 cycles for areas 5 and 6 and the pcmcia interface only) ? the type of memory connected can be specified for each area, and control signals are output for direct memory connection ? wait cycles are automatically inserted to avoid data bus conflict for continuous memory accesses to different areas or writes directly following reads in the same area ? direct interface to synchronous dram ? multiplexes row/column addresses according to synchronous dram capacity ? supports burst operation ? supports bank active mode ? has both auto-refresh and self-refresh functions ? controls timing of synchronous dram direct-connection control signals according to register setting ? burst rom interface ? insertion of wait states controllable through software ? register setting control of burst transfers ? pcmcia direct-connection interface ? insertion of wait states controllable through software ? bus sizing function for i/o bus width (only in little-endian mode)
rev. 5.00, 09/03, page 224 of 760 ? short refresh cycle control ? the overflow interrupt function of the refresh counter enables the refresh function immediately after a self-refresh operation using low power-consumption dram ? the refresh counter can be used as an interval timer ? outputs an interrupt request signal using the compare-match function ? outputs an interrupt request signal when the refresh counter overflows
rev. 5.00, 09/03, page 225 of 760 10.1.2 block diagram figure 10.1 shows a block diagram of the bus state controller. wcr1 wcr2 bcr1 module bus mcr bsc rfcr rtcnt comparator refresh controller peripheral bus internal bus interrupt controller memory controller area controller wait controller wait cs0 , cs6 to cs2 , ce2a , ce2b mcs0 to mcs7 bs rd rd/ wr we3 to we0 rasxx casx cke iciord , iciowr iois16 wcr: bcr: mcr: pcr: legend bus interface rtcsr rtcor bcr2 pcr mcscrn wait state control register bus control register memory control register pcmcia control register rfcr: rtcnt: rtcor: rtcsr: mcscrn: refresh count register refresh timer count register refresh time constant register refresh timer control/status register mcsn control register (n = 0 - 7) figure 10.1 block diagram of bus state controller
rev. 5.00, 09/03, page 226 of 760 10.1.3 pin configuration table 10.1 shows the bsc pin configuration. table 10.1 bsc pins pin name signal i/o description address bus a25?a0 o address output data bus d15?d0 i/o data i/o d31?d16 i/o data i/o when using 32-bit bus width bus cycle start bs o shows start of bus cycle. during burst transfers, asserted every data cycle. chip select 0, 2?4 cs0 , cs2 ? cs4 o chip select signals to indicate area being accessed. chip select 5, 6 cs5 / ce1a , cs6 / ce1b o chip select signals to indicate area being accessed. cs5 / ce1a and cs6 / ce1b can also be used as ce1a and ce1b of pcmcia. pcmcia card select ce2a , ce2b o ce2a and ce2b signals when pcmcia is used read/write rd/ wr o data bus direction indication signal. pcmcia write indication signal. row address strobe 3l ras3l o when synchronous dram is used, ras3l for lower 32-mbyte address and 64-mbyte address. row address strobe 3u ras3u o when synchronous dram is used, ras3u for upper 32-mbyte address. column address strobe casl o when synchronous dram is used, casl signal for lower 32-mbyte address and 64-mbyte address. column address strobe lh casu o when synchronous dram is used, casu signal for upper 32-mbyte address. data enable 0 we0 /dqmll o when memory other than synchronous dram is used, d7?d0 write strobe signal. when synchronous dram is used, selects d7?d0. data enable 1 we1 /dqmlu/ we o when memory other than synchronous dram and pcmcia is used, d15?d8 write strobe signal. when synchronous dram is used, selects d15?d8. when pcmcia is used, strobe signal indicating write cycle. data enable 2 we2 /dqmul/ iciord o when memory other than synchronous dram and pcmcia is used, d23?d16 write strobe signal. when synchronous dram is used, selects d23? d16. when pcmcia is used, strobe signal indicating i/o read.
rev. 5.00, 09/03, page 227 of 760 pin name signal i/o description data enable 3 we3 /dqmuu/ iciowr o when memory other than synchronous dram and pcmcia is used, d31?d24 write strobe signal. when synchronous dram is used, selects d31? d24. when pcmcia is used, strobe signal indicating i/o write. read rd o strobe signal indicating read cycle wait wait i wait state request signal clock enable cke o clock enable control signal for synchronous dram iois16 iois16 i signal indicating pcmcia 16-bit i/o. valid only in little-endian mode. bus release request breq i bus release request signal bus release acknowledgment back o bus release acknowledge signal mask rom chip select mcs[0] ? mcs[7] o chip select signal for mask rom connected to area 0 or 2.
rev. 5.00, 09/03, page 228 of 760 10.1.4 register configuration the bsc has 21 registers (table 10.2). synchronous dram also has a built-in synchronous dram mode register. these registers control direct connection interfaces to memory, wait states, and refreshes devices. table 10.2 bsc registers name abbr. r/w initial value * address bus width bus control register 1 bcr1 r/w h'0000 h'ffffff60 16 bus control register 2 bcr2 r/w h'3ff0 h'ffffff62 16 wait state control register 1 wcr1 r/w h'3ff3 h'ffffff64 16 wait state control register 2 wcr2 r/w h'ffff h'ffffff66 16 individual memory control register mcr r/w h'0000 h'ffffff68 16 pcmcia control register pcr r/w h'0000 h'ffffff6c 16 refresh timer control/status register rtcsr r/w h'0000 h'ffffff6e 16 refresh timer counter rtcnt r/w h'0000 h'ffffff70 16 refresh time constant register rtcor r/w h'0000 h'ffffff72 16 refresh count register rfcr r/w h'0000 h'ffffff74 16 synchronous dram mode register, area 2 sdmr w ? h'ffffd000? h'ffffdfff 8 synchronous dram mode register, area 3 h'ffffe000? h'ffffefff mcs0 control register mcscr0 r/w h'0000 h'ffffff50 16 mcs1 control register mcscr1 r/w h'0000 h'ffffff52 16 mcs2 control register mcscr2 r/w h'0000 h'ffffff54 16 mcs3 control register mcscr3 r/w h'0000 h'ffffff56 16 mcs4 control register mcscr4 r/w h'0000 h'ffffff58 16 mcs5 control register mcscr5 r/w h'0000 h'ffffff5a 16 mcs6 control register mcscr6 r/w h'0000 h'ffffff5c 16 mcs7 control register mcscr7 r/w h'0000 h'ffffff5e 16 notes: for details, see section 10.2.7, synchronous dram mode register (sdmr). * initialized by a power-on reset.
rev. 5.00, 09/03, page 229 of 760 10.1.5 area overview space allocation: in the architecture of the sh7709s, both logical spaces and physical spaces have 32-bit address spaces. the logical space is divided into five areas by the value of the upper bits of the address. the physical space is divided into eight areas. logical space can be allocated to physical space using a memory management unit (mmu). for details, refer to section 3, memory management unit (mmu), which describes area allocation for physical space. as shown in table 10.3, the sh7709s can be connected directly to six memory/pcmcia interface areas, and it outputs chip select signals ( cs0 , cs2 ? cs6 , ce2a , ce2b ) for each of them. cs0 is asserted during area 0 access; cs6 is asserted during area 6 access. when pcmcia interface is selected in area 5 or 6, in addition to cs5 / cs6 , ce2a / ce2b are asserted for the corresponding bytes accessed. area 0 (cs0) internal i/o area 2 (cs2) area 3 (cs3) area 4 (cs4) area 5 (cs5) area 6 (cs6) h00000000 h20000000 h40000000 h60000000 h80000000 ha0000000 hc0000000 he0000000 h00000000 h04000000 h08000000 h0c000000 h10000000 h14000000 h18000000 reserved area physical address space logical address space p0, u0 p1 p2 p3 p4 note: for logical address spaces p0 and p3, when the memory management unit (mmu) is on, it can optionally generate a physical address for the logical address. this diagram can be applied when the mmu is off, and when the mmu is on and each physical address corresponding to a logical address is equal except for the upper three bits. when translating logical addresses to arbitrary physical addresses, refer to table 10.3. figure 10.2 correspondence between logical address space and physical address space
rev. 5.00, 09/03, page 230 of 760 table 10.3 physical address space map area connectable memory physical address capacity access size 0 h'00000000 to h'03ffffff 64 mbytes 8, 16, 32 * 2 ordinary memory * 1 , burst rom h'00000000 + h'20000000 n to h'03ffffff + h'20000000 n shadow n = 1?6 1 h'04000000 to h'07ffffff 64 mbytes 8, 16, 32 * 3 internal i/o registers * 7 h'04000000 + h'20000000 n to h'07ffffff + h'20000000 n shadow n = 1?6 2 h'08000000 to h'0bffffff 64 mbytes 8, 16, 32 * 3 * 4 ordinary memory * 1 , synchronous dram h'08000000 + h'20000000 n to h'0bffffff + h'20000000 n shadow n = 1?6 3 h'0c000000 to h'0fffffff 64 mbytes 8, 16, 32 * 3 * 4 ordinary memory * 1 , synchronous dram h'0c000000 + h'20000000 n to h'0fffffff + h'20000000 n shadow n = 1?6 4 h'10000000 to h'13ffffff 64 mbytes 8, 16, 32 * 3 ordinary memory * 1 h'10000000 + h'20000000 n to h'13ffffff + h'20000000 n shadow n = 1?6 5 h'14000000 to h'15ffffff 32 mbytes 8, 16, 32 * 3 * 5 h'16000000 to h'17ffffff 32 mbytes ordinary memory * 1 , pcmcia, burst rom ordinary memory, burst rom h'14000000 + h'20000000 n to h'17ffffff + h'20000000 n shadow n = 1?6 6 h'18000000 to h'19ffffff 32 mbytes 8, 16, 32 * 3 * 5 h'1a000000 to h'1bffffff ordinary memory * 1 , pcmcia, burst rom h'18000000 + h'20000000 n to h'1bffffff + h'20000000 n shadow n = 1?6 7 * 6 reserved area h'1c000000 + h'20000000 n to h'1fffffff + h'20000000 n n = 0?7 notes: 1. memory with interface such as sram or rom. 2. use external pin to specify memory bus width. 3. use register to specify memory bus width. 4. with synchronous dram interfaces, bus width must be 16 or 32 bits. 5. with pcmcia interface, bus width must be 8 or 16 bits. 6. do not access the reserved area. if the reserved area is accessed, correct operation cannot be guaranteed. 7. when the control register in area 1 is not used for address translation by the mmu, set the first three bits of the logical address to 101 for allocation to the p2 space.
rev. 5.00, 09/03, page 231 of 760 area 0: h00000000 area 1: h04000000 area 2: h08000000 area 3: h0c000000 area 4: h10000000 area 5: h14000000 the pcmcia interface is shared by the memory and i/o card the pcmcia interface is shared by the memory and i/o card area 6: h18000000 ordinary memory/ burst rom internal i/o ordinary memory/ synchronous dram ordinary memory/ synchronous dram ordinary memory ordinary memory/ burst rom/pcmcia ordinary memory/ burst rom/pcmcia figure 10.3 physical space allocation memory bus width: the memory bus width in the sh7709s can be set for each area. in area 0, external pins can be used to select byte (8 bits), word (16 bits), or longword (32 bits) on power-on reset. the correspondence between the external pins (md4 and md3) and the memory size is shown in table below. table 10.4 correspondence between external pins (md4 and md3) and memory size md4 md3 memory size 0 0 reserved (do not set) 0 1 8 bits 1 0 16 bits 1 1 32 bits for areas 2?6, byte, word, and longword can be chosen for the bus width using bus control register 2 (bcr2) whenever ordinary memory, rom, or burst rom are used. when the synchronous dram interface is used, word or longword can be chosen as the bus width. when the pcmcia interface is used, set the bus width to byte or word. when synchronous dram is connected to both area 2 and area 3, set the same bus width for areas 2 and 3. when using the port function, set each of the bus widths to byte or word for all areas. for more information, see section 10.2.2, bus control register 2 (bcr2).
rev. 5.00, 09/03, page 232 of 760 shadow space: areas 0 and 2?6 are decoded by physical addresses a28?a26, which correspond to areas 000 to 110. address bits 31?29 are ignored. this means that the range of area 0 addresses, for example, is h'00000000 to h'03ffffff, and its corresponding shadow space is the address space obtained by adding to it h'20000000 n (n = 1?6). the address range for area 7, which is on-chip i/o space, is h'1c000000 to h'1fffffff. the address space h'1c000000 + h'20000000 n?h'1fffffff + h'20000000 n (n = 0?7) corresponding to the area 7 shadow space is reserved, and must not be used. 10.1.6 pcmcia support the sh7709s supports pcmcia standard interface specifications in physical space areas 5 and 6. the interfaces supported are basically the ?ic memory card interface? and ?i/o card interface? stipulated in jeida specifications ver. 4.2 (pcmcia2.1). table 10.5 pcmcia interface characteristics item feature access random access data bus 8/16 bits memory type mask rom, otprom, eprom, eeprom, flash memory, sram memory capacity maximum 32 mbytes i/o space capacity maximum 32 mbytes other features dynamic bus sizing of i/o bus width * the pcmcia interface can be accessed from the address translation area or non-address translation area. note: * dynamic bus sizing of the i/o bus width is supported only in little-endian mode. common memory/attribute memory area 5: h14000000 area 5: h16000000 common memory/attribute memory area 6: h18000000 i/o space i/o space area 6: h1a000000 figure 10.4 pcmcia space allocation
rev. 5.00, 09/03, page 233 of 760 table 10.6 pcmcia support interface ic memory card interface i/o card interface pin signal i/o function signal i/o function sh7709s pin 1 gnd ? ground gnd ? ground ? 2 d3 i/o data d3 i/o data d3 3 d4 i/o data d4 i/o data d4 4 d5 i/o data d5 i/o data d5 5 d6 i/o data d6 i/o data d6 6 d7 i/o data d7 i/o data d7 7 ce1 i card enable ce1 i card enable ce1a or ce1b 8 a10 i address a10 i address a10 9 oe i output enable oe i output enable rd 10 a11 i address a11 i address a11 11 a9 i address a9 i address a9 12 a8 i address a8 i address a8 13 a13 i address a13 i address a13 14 a14 i address a14 i address a14 15 we / pgm i write enable we / pgm i write enable we 16 rdy/ bsy o ready/busy ireq o ready/busy ? 17 v cc operation power v cc operation power ? 18 vpp1 program power vpp1 program/ peripheral power ? 19 a16 i address a16 i address a16 20 a15 i address a15 i address a15 21 a12 i address a12 i address a12 22 a7 i address a7 i address a7 23 a6 i address a6 i address a6 24 a5 i address a5 i address a5 25 a4 i address a4 i address a4 26 a3 i address a3 i address a3 27 a2 i address a2 i address a2 28 a1 i address a1 i address a1 29 a0 i address a0 i address a0 30 d0 i/o data d0 i/o data d0
rev. 5.00, 09/03, page 234 of 760 ic memory card interface i/o card interface pin signal i/o function signal i/o function sh7709s pin 31 d1 i/o data d1 i/o data d1 32 d2 i/o data d2 i/o data d2 33 wp o write protect iois16 o 16-bit i/o port iois16 34 gnd ground gnd ground ? 35 gnd ground gnd ground ? 36 cd1 o card detection cd1 o card detection ? 37 d11 i/o data d11 i/o data d11 38 d12 i/o data d12 i/o data d12 39 d13 i/o data d13 i/o data d13 40 d14 i/o data d14 i/o data d14 41 d15 i/o data d15 i/o data d15 42 ce2 i card enable ce2 i card enable ce2a or ce2b 43 vs1 i voltage sense 1 vs1 i voltage sense 1 ? 44 rfu reserved iord i i/o read iciord 45 rfu reserved iowr i i/o write iciowr 46 a17 i address a17 i address a17 47 a18 i address a18 i address a18 48 a19 i address a19 i address a19 49 a20 i address a20 i address a20 50 a21 i address a21 i address a21 51 v cc power supply v cc power supply ? 52 vpp2 program power vpp2 program/ peripheral power ? 53 a22 i address a22 i address a22 54 a23 i address a23 i address a23 55 a24 i address a24 i address a24 56 a25 i address a25 i address a25 57 vs2 i voltage sense 2 vs2 i voltage sense 2 ? 58 reset i reset reset i reset ? 59 wait o wait request wait o wait request ? 60 rfu reserved inpack o input acknowledge ?
rev. 5.00, 09/03, page 235 of 760 ic memory card interface i/o card interface pin signal i/o function signal i/o function sh7709s pin 61 reg i attribute memory space select reg i attribute memory space select ? 62 bvd2 o battery voltage detection spkr o digital voice signal ? 63 bvd1 o battery voltage detection stschg o card state change ? 64 d8 i/o data d8 i/o data d8 65 d9 i/o data d9 i/o data d9 66 d10 i/o data d10 i/o data d10 67 cd2 o card detection cd2 o card detection ? 68 gnd ground gnd ground ? 10.2 bsc registers 10.2.1 bus control register 1 (bcr1) bus control register 1 (bcr1) is a 16-bit readable/writable register that sets the functions and bus cycle state for each area. it is initialized to h'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. do not access external memory outside area 0 until bcr1 register initialization is complete. bit: 15 14 13 12 11 10 9 8 pula puld hizmem hizcnt endian a0bst1 a0bst0 a5bst1 initial value: 0 0 0 0 0/1 * 000 r/w: r/w r/w r/w r/w r r/w r/w r/w bit:76543210 a5bst0 a6bst1 a6bst0 dram tp2 dram tp1 dram tp0 a5 pcm a6 pcm initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w note: * samples the value of the external pin (md5) designating the endian in a power-on reset.
rev. 5.00, 09/03, page 236 of 760 bit 15?pin a25 to a0 pull-up (pula): specifies whether or not pins a25 to a0 are pulled up for 4 cycles immediately after back is asserted. bit 15: pula description 0 not pulled up (initial value) 1 pulled up bit 14?pin d31 to d0 pull-up (puld): specifies whether or not pins d31 to d0 are pulled up when not in use. bit 14: puld description 0 not pulled up (initial value) 1 pulled up bit 13?hi-z memory control (hizmem): specifies the state of a25?a0, bs , cs , rd/ wr , we /dqm, rd , ce2a , ce2b and drak0/1 in standby mode. bit 13: hizmem description 0 a25?a0, bs, cs, rd/wr, we/dqm, rd, ce2a, ce2b and drak0/1 are hi-z in standby mode (initial value) 1 a25?a0, bs, cs, rd/wr, we/dqm, rd, ce2a, ce2b and drak0/1 are high in standby mode bit 12?high-z control (hizcnt): specifies the state of the ras and cas signals in standby mode and when the bus is released. bit 12: hizcnt description 0 ras and cas signals are high-impedance (high-z) in standby mode and when bus is released (initial value) 1 ras and cas signals are driven in standby mode and when bus is released bit 11?endian flag (endian): samples the value of the external pin designating the endian in a power-on reset. the endian for all physical spaces is decided by this bit, which is read-only. bit 11: endian description 0 (on reset) endian setting external pin (md5) is low. indicates the sh7709s is set as big-endian 1 (on reset) endian setting external pin (md5) is high. indicates the sh7709s is set as little-endian
rev. 5.00, 09/03, page 237 of 760 bits 10 and 9?area 0 burst rom control (a0bst1, a0bst0): specify whether to use burst rom in physical space area 0. when burst rom is used, these bits set the number of burst transfers. bit 10: a0bst1 bit 9: a0bst0 description 0 0 access area 0 accessed as ordinary memory (initial value) 1 access area 0 accessed as burst rom (4 consecutive accesses). can be used when bus width is 8, 16, or 32. 1 0 access area 0 accessed as burst rom (8 consecutive accesses). can be used when bus width is 8 or 16. should not be specified when bus width is 16 or 32. 1 access area 0 accessed as burst rom (16 consecutive accesses). can be used only when bus width is 8. should not be specified when bus width is 16 or 32. bits 8 and 7?area 5 burst enable (a5bst1, a5bst0): specify whether to use burst rom and pcmcia burst mode in physical space area 5. when burst rom and pcmcia burst mode are used, these bits set the number of burst transfers. bit 8: a5bst1 bit 7: a5bst0 description 0 0 access area 5 accessed as ordinary memory (initial value) 1 burst access of area 5 (4 consecutive accesses). can be used when bus width is 8, 16, or 32. 1 0 burst access of area 5 (8 consecutive accesses). can be used when bus width is 8 or 16. should not be specified when bus width is 32. 1 burst access of area 5 (16 consecutive accesses). can be used only when bus width is 8. should not be specified when bus width is 16 or 32. bits 6 and 5?area 6 burst enable (a6bst1, a6bst0): specify whether to use burst rom and pcmcia burst mode in physical space area 6. when burst rom and pcmcia burst mode are used, these bits set the number of burst transfers.
rev. 5.00, 09/03, page 238 of 760 bit 6: a6bst1 bit 5: a6bst0 description 0 0 access area 6 accessed as ordinary memory (initial value) 1 burst access of area 6 (4 consecutive accesses). can be used when bus width is 8, 16, or 32. 1 0 burst access of area 6 (8 consecutive accesses). can be used when bus width is 8 or 16. should not be specified when bus width is 32. 1 burst access of area 6 (16 consecutive accesses). can be used only when bus width is 8. should not be specified when bus width is 16 or 32. bits 4 to 2?area 2, area 3 memory type (dramtp2, dramtp1, dramtp0): designate the types of memory connected to physical space areas 2 and 3. ordinary memory, such as rom, sram, or flash rom, can be directly connected. synchronous dram can also be directly connected. bit 4: dramtp2 bit 3: dramtp1 bit 2: dramtp0 description 000areas 2 and 3 are ordinary memory (initial value) 1 reserved (setting prohibited) 1 0 area 2: ordinary memory; area 3: synchronous dram * 2 1 areas 2 and 3 are synchronous dram * 1 * 2 100reserved (setting prohibited) 1 reserved (setting prohibited) 1 0 reserved (setting prohibited) 1 reserved (setting prohibited) notes: 1. when selecting this mode, set the same bus width for area 2 and area 3. 2. do not access synchronous dram when clock ratio i :b = 1:1 bit 1?area 5 bus type (a5pcm): designates whether to access physical space area 5 as pcmcia space. bit 1: a5pcm description 0 physical space area 5 accessed as ordinary memory (initial value) 1 physical space area 5 accessed as pcmcia space
rev. 5.00, 09/03, page 239 of 760 bit 0?area 6 bus type (a6pcm): designates whether to access physical space area 6 as pcmcia space. bit 0: a6pcm description 0 physical space area 6 accessed as ordinary memory (initial value) 1 physical space area 6 accessed as pcmcia space 10.2.2 bus control register 2 (bcr2) bus control register 2 (bcr2) is a 16-bit readable/writable register that selects the bus size of each area and whether an 8-bit port is used or not. it is initialized to h'3ff0 by a power-on reset, but is not initialized by a manual reset or in standby mode. do not access external memory outside area 0 until bcr2 register initialization is complete. bit: 15 14 13 12 11 10 9 8 ? ? a6sz1 a6sz0 a5sz1 a5sz0 a4sz1 a4sz0 initial value:00111111 r/w: r r r/w r/w r/w r/w r/w r/w bit:76543210 a3sz1a3sz0a2sz1a2sz0???? initial value:11110000 r/w:r/wr/wr/wr/wrrrr bits 15, 14, 3, 2, 1, and 0?reserved: these bits are always read as 0. the write value should always be 0. bits 2n + 1, 2n?area n (2?6) bus size specification (ansz1, ansz0): specify the bus size of physical space area n (n = 2 to 6).
rev. 5.00, 09/03, page 240 of 760 bit 2n + 1: ansz1 bit 2n: ansz0 port a / b description 0 0 not used reserved (setting prohibited) 1 byte (8-bit) size 1 0 word (16-bit) size 1 longword (32-bit) size 0 0 used reserved (setting prohibited) 1 byte (8-bit) size 1 0 word (16-bit) size 1 reserved (setting prohibited) 10.2.3 wait state control register 1 (wcr1) wait state control register 1 (wcr1) is a 16-bit readable/writable register that specifies the number of idle (wait) state cycles inserted for each area. for some memories, data bus drive may not be turned off quickly even when the read signal from the external device is turned off. this can result in conflicts between data buses when consecutive memory accesses are to different memories or when a write immediately follows a memory read. this lsi automatically inserts the number of idle states set in wcr1 in those cases. wcr1 is initialized to h'3ff3 by a power-on reset. it is not initialized by a manual reset or in standby mode, and retains its contents. bit: 15 14 13 12 11 10 9 8 waitse l ? a6iw1 a6iw0 a5iw1 a5iw0 a4iw1 a4iw0 initial value:00111111 r/w: r/w r r/w r/w r/w r/w r/w r/w bit:76543210 a3iw1 a3iw0 a2iw1 a2iw0 ? ? a0iw1 a0iw0 initial value:11110011 r/w: r/w r/w r/w r/w r r r/w r/w
rev. 5.00, 09/03, page 241 of 760 bit 15?wait sampling timing select (waitsel): specifies the wait signal sampling timing. bit 15: waitsel description 0 setting to 1 when using the wait signal * (initial value) 1 sampled wait signal at fall of ckio note: * operation is not guaranteed if wait is asserted while weitsel = 0. bits 14, 3, and 2 ?reserved: these bits are always read as 0. the write value should always be 0. bits 2n + 1, 2n?area n (6?2, 0) intercycle idle specification (aniw1, aniw0): specify the number of idles inserted between bus cycles when switching between physical space area n (6?2, 0) and another space or between a read access and a write access in the same physical space. bit 2n + 1: aniw1 bit 2n: aniw0 description 0 0 1 idle cycle inserted 1 1 idle cycle inserted 1 0 2 idle cycles inserted 1 3 idle cycles inserted (initial value) 10.2.4 wait state control register 2 (wcr2) wait state control register 2 (wcr2) is a 16-bit readable/writable register that specifies the number of wait state cycles inserted for each area. it also specifies the data access pitch for burst memory accesses. this allows direct connection of even low-speed memories without an external circuit. wcr2 is initialized to h'ffff by a power-on reset. it is not initialized by a manual reset or in standby mode. bit: 15 14 13 12 11 10 9 8 a6 w2 a6 w1 a6 w0 a5 w2 a5 w1 a5 w0 a4 w2 a4 w1 initial value:11111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 a4 w0 a3 w1 a3 w0 a2 w1 a2 w0 a0 w2 a0 w1 a0 w0 initial value:11111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
rev. 5.00, 09/03, page 242 of 760 bits 15 to 13?area 6 wait control (a6w2, a6w1, a6w0): specify the number of wait states inserted in physical space area 6. also specify the number of states for burst transfer. description first cycle burst cycle (excluding first cycle) bit 15: a6w2 bit 14: a6w1 bit 13: a6w0 inserted wait states wait wait wait wait pin number of states per data transfer wait wait wait wait pin 0 0 0 0 disabled 2 enabled 1 1 enabled 2 enabled 1 0 2 enabled 3 enabled 1 3 enabled 4 enabled 1 0 0 4 enabled 4 enabled 1 6 enabled 6 enabled 1 0 8 enabled 8 enabled 110 (initial value) enabled 10 enabled bits 12 to 10?area 5 wait control (a5w2, a5w1, a5w0): specify the number of wait states inserted in physical space area 5. also specify the number of states for burst transfer. description first cycle burst cycle (excluding first cycle) bit 12: a5w2 bit 11: a5w1 bit 10: a5w0 inserted wait states wait wait wait wait pin number of states per data transfer wait wait wait wait pin 0 0 0 0 disabled 2 enabled 1 1 enabled 2 enabled 1 0 2 enabled 3 enabled 1 3 enabled 4 enabled 1 0 0 4 enabled 4 enabled 1 6 enabled 6 enabled 1 0 8 enabled 8 enabled 110 (initial value) enabled 10 enabled
rev. 5.00, 09/03, page 243 of 760 bits 9 to 7?area 4 wait control (a4w2, a4w1, a4w0): specify the number of wait states inserted in physical space area 4. description bit 9: a4w2 bit 8: a4w1 bit 7: a4w0 inserted wait state wait wait wait wait pin 0000 ignored 1 1 enabled 1 0 2 enabled 1 3 enabled 1004 e nabled 1 6 enabled 1 0 8 enabled 1 10 enabled (initial value) bits 6 and 5?area 3 wait control (a3w1, a3w0): specify the number of wait states inserted in physical space area 3. ? for ordinary memory description bit 6: a3w1 bit 5: a3w0 inserted wait states wait wait wait wait pin 0 0 0 ignored 11 enabled 1 0 2 enabled 1 3 enabled (initial value) ? for synchronous dram description bit 6: a3w1 bit 5: a3w0 synchronous dram: cas latency 00 1 11 10 2 1 3 (initial value)
rev. 5.00, 09/03, page 244 of 760 bits 4 and 3?area 2 wait control (a2w1, a2w0): specify the number of wait states inserted in physical space area 2. ? for ordinary memory description bit 4: a2w0 bit 3: a2w0 inserted wait states wait wait wait wait pin 0 0 0 ignored 11 enabled 1 0 2 enabled 1 3 enabled (initial value) ? for synchronous dram description bit 4: a2w1 bit 3: a2w0 synchronous dram: cas latency 001 11 102 1 3 (initial value) bits 2 to 0?area 0 wait control (a0w2, a0w1, a0w0): specify the number of wait states inserted in physical space area 0. also specify the burst pitch for burst transfer. description first cycle burst cycle (excluding first cycle) bit 2: a0w2 bit 1: a0w1 bit 0: a0w0 inserted wait states wait wait wait wait pin number of states per data transfer wait wait wait wait pin 00 0 0 ignored 2 enabled 1 1 enabled 2 enabled 1 0 2 enabled 3 enabled 1 3 enabled 4 enabled 1 0 0 4 enabled 4 enabled 1 6 enabled 6 enabled 1 0 8 enabled 8 enabled 110 (initial value) enabled 10 enabled
rev. 5.00, 09/03, page 245 of 760 10.2.5 individual memory control register (mcr) the individual memory control register (mcr) is a 16-bit readable/writable register that specifies ras and cas timing for synchronous dram (areas 2 and 3), specifies address multiplexing, and controls refresh. this enables direct connection of synchronous dram without external circuits. mcr is initialized to h'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. bits tpc1?tpc0, rcd1?rcd0, trwl1?trwl0, tras1?tras0, rasd, and amx3?amx0 are written to in the initialization after a power-on reset and should not then be modified again. when rfsh and rmode are written to, write the same values to the other bits. when using synchronous dram, do not access areas 2 and 3 until this register is initialized. bit: 15 14 13 12 11 10 9 8 tpc1 tpc0 rcd1 rcd0 trwl1 trwl0 tras1 tras0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 rasd amx3 amx2 amx1 amx0 rfsh rmode ? initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r bits 15 and 14?ras precharge time (tpc1, tpc0): when synchronous dram interface is selected as connected memory, they set the minimum number of cycles until output of the next bank-active command after precharge. however, the number of cycles input immediately after the issue of an all-bank-precharge command (pall) in the case of an auto-refresh or a precharge command (pre) in the bank active mode is one fewer than the normal value. tpc1 should not be set to 0 and tpc0 to 1 in the bank active mode. description bit 15: tpc1 bit 14: tpc0 normal operation immediately after precharge command * immediately after self-refresh 0 0 1 cycle (initial value) 0 cycle (initial value) 2 cycles (initial value) 1 2 cycles 1 cycle 5 cycles 1 0 3 cycles 2 cycles 8 cycles 1 4 cycles 3 cycles 11 cycles note: * immediately after all-bank-precharge (pall) in the case of an auto-refresh or precharge (pre) in the bank active mode.
rev. 5.00, 09/03, page 246 of 760 bits 13 and 12?ras?cas delay (rcd1, rcd0): when synchronous dram interface is selected as connected memory, these bits set the bank active read/write command delay time. bit 13: rcd1 bit 12: rcd0 description 0 0 1 cycle (initial value) 1 2 cycles 1 0 3 cycles 1 4 cycles bits 11 and 10?write-precharge delay (trwl1, trwl0): set the synchronous dram write-precharge delay time. this designates the time between the end of a write cycle and the next bank-active command. this setting is valid only when synchronous dram is connected. after the write cycle, the next bank-active command is not issued for the period tpc + trwl. bit 11: trwl1 bit 10: trwl0 description 0 0 1 cycle (initial value) 1 2 cycles 1 0 3 cycles 1 reserved (setting prohibited) bits 9 and 8? cas cas cas cas -before- ras ras ras ras refresh ras ras ras ras assert time (tras1, tras0): when synchronous dram interface is selected, no bank-active command is issued during the period tpc + tras after an auto-refresh command. bit 9: tras1 bit 8: tras0 description 0 0 2 cycles (initial value) 1 3 cycles 1 0 4 cycles 1 5 cycles bit 7?synchronous dram bank active (rasd): specifies whether synchronous dram is used in bank active mode or auto-precharge mode. set auto-precharge mode when areas 2 and 3 are both designated as synchronous dram space. bit 7: rasd description 0 auto-precharge mode (initial value) 1 bank active mode the bank active mode should not be used unless the bus width for all areas is 32 bits.
rev. 5.00, 09/03, page 247 of 760 bits 6 to 3?address multiplex (amx3, amx2, amx1, amx0): specify address multiplexing for synchronous dram. for synchronous dram interface: bit6: amx3 bit5: amx2 bit 4: amx1 bit 3: amx0 description 1101the row address begins with a10 (the a10 value is output at a1 when the row address is output. 4m 16-bit 4-bank products) 1 0 the row address begins with a11 (the a11 value is output at a1 when the row address is output. 8m 16-bit 4-bank products) * 1 0100the row address begins with a9 (the a9 value is output at a1 when the row address is output. 1m 16-bit 4-bank products) 1 the row address begins with a10 (the a10 value is output at a1 when the row address is output. 2m 8-bit 4-bank products, 2m 16-bit 4-bank products) 1 1 the row address begins with a9 (the a9 value is output at a1 when the row address is output. 512k 32-bit 4-bank products) * 2 0000begin synchronous dram access after setting amx3 to 0 = *1** (initial value) except above value reserved (setting prohibited) notes: 1. can only be set when using a 16-bit bus width. 2. can only be set when using a 32-bit bus width. bit 2?refresh control (rfsh): the rfsh bit determines whether or not synchronous dram refresh operations are is performed. if the refresh function is not used, the timer for generation of periodic refresh requests can also be used as an interval timer. bit 2: rfsh description 0 no refresh (initial value) 1refresh
rev. 5.00, 09/03, page 248 of 760 bit 1?refresh mode (rmode): selects whether to perform an ordinary refresh or a self- refresh when the rfsh bit is 1. when the rfsh bit is 1 and this bit is 0, an auto-refresh is performed on synchronous dram at the period set by refresh-related registers rtcnt, rtcor, and rtcsr. when a refresh request occurs during an external bus cycle, the refresh cycle is performed after the bus cycle ends. when the rfsh bit is 1 and this bit is also 1, the synchronous dram will wait for the end of any executing external bus cycle before going into a self-refresh. all refresh requests to memory that is in the self-refresh state are ignored. bit 1: rmode description 0 auto refresh (rfsh must be 1) (initial value) 1 self-refresh (rfsh must be 1) bit 0?reserved: this bit is always read as 0. the write value should always be 0. 10.2.6 pcmcia control register (pcr) the pcmcia control register (pcr) is a 16-bit readable/writable register that specifies the assertion and negation timing of the oe and we signals for the pcmcia interface connected to areas 5 and 6. the oe and we signal assertion width is set by the wait control bits in the wcr2 register. pcr is initialized to h'0000 by a power-on reset, but is not initialized, and retains its contents, in a manual reset and in standby mode. bit: 15 14 13 12 11 10 9 8 a6w3 a5w3 ? ? a5ted2 a6ted2 a5teh2 a6teh2 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 a5ted1 a5ted0 a6ted1 a6ted0 a5teh1 a5teh0 a6teh1 a6teh0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
rev. 5.00, 09/03, page 249 of 760 bit 15?area 6 wait control (a6w3): specifies the number of inserted wait states for area 6 combined with bits a6w2?a6w0 in wcr2. also specifies the number of transfer states in burst transfer. clear this bit to 0 when area 6 is not set to pcmcia. first cycle burst cycle a6w3 a6w2 a6w1 a6w0 inserted wait states wait wait wait wait pin number of states per one-data transfer wait wait wait wait pin 00000 ignored2 enabled 00011 enabled2 enabled 00102 enabled3 enabled 00113 enabled4 enabled 01004 enabled5 enabled 01016 enabled7 enabled 01108 enabled9 enabled 011110 (initial value) enabled 11 enabled 1 0 0 0 12 enabled 13 enabled 1 0 0 1 14 enabled 15 enabled 1 0 1 0 18 enabled 19 enabled 1 0 1 1 22 enabled 23 enabled 1 1 0 0 26 enabled 27 enabled 1 1 0 1 30 enabled 31 enabled 1 1 1 0 34 enabled 35 enabled 1 1 1 1 38 enabled 39 enabled bit 14?area 5 wait control (a5w3): specifies the number of inserted wait states for area 5 combined with bits a5w2?a5w0 in wcr2. also specifies the number of transfer states in burst transfer. clear this bit to 0 when area 5 is not set to pcmcia. the relationship between the set value and the number of waits is the same as for a6w3. bits 13 and 12?reserved: these bits are always read as 0. the write value should always be 0.
rev. 5.00, 09/03, page 250 of 760 bits 11, 7, and 6?area 5 address oe oe oe oe / we we we we assert delay (a5ted2, a5ted1, a5ted0): specify the delay time from address output to oe / we assertion for the pcmcia interface connected to area 5. bit 11: a5ted2 bit 7: a5ted1 bit 6: a5ted0 description 0000.5-cycle delay (initial value) 1 1.5-cycle delay 102.5-cycle delay 1 3.5-cycle delay 1004.5-cycle delay 1 5.5-cycle delay 106.5-cycle delay 1 7.5-cycle delay bits 10, 5, and 4?area 6 address oe oe oe oe / we we we we assert delay (a6ted2, a6ted1, a6ted0): the a6ted bits specify the delay time from address output to oe / we assertion for the pcmcia interface connected to area 6. bit 10: a6ted2 bit 5: a6ted1 bit 4: a6ted0 description 0000.5-cycle delay (initial value) 1 1.5-cycle delay 102.5-cycle delay 1 3.5-cycle delay 1004.5-cycle delay 1 5.5-cycle delay 106.5-cycle delay 1 7.5-cycle delay
rev. 5.00, 09/03, page 251 of 760 bits 9, 3, and 2?area 5 oe oe oe oe / we we we we negate address delay (a5teh2, a5teh1, a5teh0): specify the address hold delay time from oe / we negation for the pcmcia interface connected to area 5. bit 9: a5teh2 bit 3: a5teh1 bit 2: a5teh0 description 0000.5-cycle delay (initial value) 1 1.5-cycle delay 102.5-cycle delay 1 3.5-cycle delay 1004.5-cycle delay 1 5.5-cycle delay 106.5-cycle delay 1 7.5-cycle delay bits 8, 1, and 0?area 6 oe oe oe oe / we we we we negate address delay (a6teh2, a6teh1, a6teh0): specify the address hold delay time from oe / we negation for the pcmcia interface connected to area 6. bit 8: a6teh2 bit 1: a6teh1 bit 0: a6teh0 description 0000.5-cycle delay (initial value) 1 1.5-cycle delay 102.5-cycle delay 1 3.5-cycle delay 1004.5-cycle delay 1 5.5-cycle delay 106.5-cycle delay 1 7.5-cycle delay
rev. 5.00, 09/03, page 252 of 760 10.2.7 synchronous dram mode register (sdmr) the synchronous dram mode register (sdmr) is an 8-bit write-only register that is written to via the synchronous dram address bus. it sets synchronous dram mode for areas 2 and 3. sdmr must be set before accessing the synchronous dram. writes to the synchronous dram mode register use the address bus rather than the data bus. if the value to be set is x and the sdmr address is y, the value x is written in the synchronous dram mode register by writing in address x + y. since, with a 32-bit bus width, a0 of the synchronous dram is connected to a2 of the chip and a1 of the synchronous dram is connected to a3 of the chip, the value actually written to the synchronous dram is the x value shifted two bits right. with a 16-bit bus width, the value written is the x value shifted one bit right. for example, with a 32-bit bus width, when h'0230 is written to the sdmr register of area 2, random data is written to the address h'ffffd000 (address y) + h'08c0 (value x), or h'ffffd8c0. as a result, h'0230 is written to the sdmr register. the range for value x is h'0000 to h'0ffc. when h'0230 is written to the sdmr register of area 3, random data is written to the address h'ffffe000 (address y) + h'08c0 (value x), or h'ffffe8c0. as a result, h'0230 is written to the sdmr register. the range for value x is h'0000 to h'0ffc. bit: 31 12 11 10 9 8 sdmr address ???? initial value: ? ...................... ????? r/w: ? ...................... ? w * w * ww bit:76543210 ???????? initial value:???????? r/w:wwwwww?? note: * depending on the type of synchronous dram.
rev. 5.00, 09/03, page 253 of 760 10.2.8 refresh timer control/status register (rtcsr) the refresh timer control/status register (rtcsr) is a 16-bit readable/writable register that specifies the refresh cycle, whether to generate an interrupt, and the cycle of that interrupt. it is initialized to h'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. make the rtcor setting before setting bits cks2 to cks0 in rtcsr. note: the method of writing to rtcsr differs from that for general registers to ensure that rtcsr is not rewritten incorrectly. use a word transfer instruction to set the upper byte as b'10100101 and the lower byte as the write data. for details, see section 10.2.12, cautions on accessing refresh control related registers. bit: 15 14 13 12 11 10 9 8 ???????? initial value:00000000 r/w:rrrrrrrr bit:76543210 cmf cmie cks2 cks1 cks0 ovf ovie lmts initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 8?reserved: these bits are always read as 0. the write value should always be 0. bit 7?compare match flag (cmf): indicates that the values of rtcnt and rtcor match. bit 7: cmf description 0 the values of rtcnt and rtcor do not match (initial value) clearing condition: when a refresh is performed after 0 has been written to cmf and rfsh = 1 and rmode = 0 (to perform a cbr refresh) 1 the values of rtcnt and rtcor match setting condition: rtcnt = rtcor * note: * contents do not change when 1 is written to cmf. bit 6?compare match interrupt enable (cmie): enables or disables an interrupt request caused when cmf in rtcsr is set to 1. do not set this bit to 1 when using auto-refresh. bit 6: cmie description 0 interrupt request by cmf is disabled (initial value) 1 interrupt request by cmf is enabled
rev. 5.00, 09/03, page 254 of 760 bits 5 to 3?clock select bits (cks2 to cks0): select the clock input to rtcnt. the source clock is the external bus clock (ckio). the rtcnt count clock is ckio divided by the specified ratio. rtcor must be set before setting cks2-cks0. description bit 5: cks2 bit 4: cks1 bit 3: cks0 normal external bus clock 000clock input disabled 1 bus clock (ckio)/4 1 0 ckio/16 1ckio/64 100ckio/256 1 ckio/1024 1 0 ckio/2048 1 ckio/4096 bit 2?refresh count overflow flag (ovf): indicates when the number of refresh requests indicated in the refresh count register (rfcr) exceeds the limit set in the lmts bit in rtcsr. bit 2: ovf description 0 rfcr has not exceeded the count limit value set in lmts (initial value) clearing condition: when 0 is written to ovf 1 rfcr has exceeded the count limit value set in lmts setting condition: when the rfcr value has exceeded the count limit value set in lmts * note: * contents do not change when 1 is written to ovf. bit 1?refresh count overflow interrupt enable (ovie): selects whether to suppress generation of interrupt requests by the ovf bit in rtcsr when ovf is set to 1. bit 1: ovie description 0 interrupt request by ovf is disabled (initial value) 1 interrupt request by ovf is enabled
rev. 5.00, 09/03, page 255 of 760 bit 0?refresh count overflow limit select (lmts): indicates the count limit value to be compared to the number of refreshes indicated in the refresh count register (rfcr). when the value in rfcr overflows the value specified by lmts, the ovf flag is set. bit 0: lmts description 0 count limit value is 1024 (initial value) 1 count limit value is 512 10.2.9 refresh timer counter (rtcnt) rtcnt is a 16-bit register containing a readable/writable 8-bit counter that counts up on an input clock. the clock select bits (cks2?cks0) in rtcsr select the input clock. when rtcnt matches rtcor, the cmf bit in rtcsr is set and rtcnt is cleared. rtcnt is initialized to h'00 by a power-on reset, but continues incrementing after a manual reset. it is not initialized in standby mode, but holds its contents. note: the method of writing to rtcnt differs from that for general registers to ensure that rtcnt is not rewritten incorrectly. use a word transfer instruction to set the upper byte as b'10100101 and the lower byte as the write data. for details, see section 10.2.12, cautions on accessing refresh control related registers. bit: 15 14 13 12 11 10 9 8 initial value:00000000 r/w:???????? bit:76543210 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
rev. 5.00, 09/03, page 256 of 760 10.2.10 refresh time constant register (rtcor) the refresh time constant register (rtcor) specifies the upper-limit value of rtcnt. the values of rtcor and rtcnt (lower 8 bits) are constantly compared. when the values match, the compare match flag (cmf) in rtcsr is set and rtcnt is cleared to 0. when the refresh bit (rfsh) in the individual memory control register (mcr) is set to 1 and the refresh mode is set to auto refresh, a memory refresh cycle occurs when the cmf bit is set. rtcor is a readable/writable register. rtcor is initialized to h'00 by a power-on reset. it is not initialized by a manual reset or in standby mode, but holds its contents. make the rtcor setting before setting bits cks2 to cks0 in rtcsr. note: the method of writing to rtcor differs from that for general registers to ensure that rtcor is not rewritten incorrectly. use a word transfer instruction to set the upper byte as b'10100101 and the lower byte as the write data. for details, see section 10.2.12, cautions on accessing refresh control related registers. bit: 15 14 13 12 11 10 9 8 initial value:00000000 r/w:???????? bit:76543210 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 10.2.11 refresh count register (rfcr) the refresh count register (rfcr) counts the number of refreshing. when rfcr exceeds the count limit value set in the lmts bit in rtcsr, the ovf bit in rtcsr is set and rfcr is cleared. rfcr is a 10-bit readable/writable counter. rfcr is initialized to h'0000 by a power-on reset. rfcr continues incrementing in a manual reset. it is not initialized by in standby mode, but holds its contents. note: the method of writing to rfcr differs from that for general registers to ensure that rfcr is not rewritten incorrectly. use a word transfer instruction to set the six bits starting from the msb in the upper byte as b'101001, and the remaining bits as the write data. for details, see section 10.2.12, cautions on accessing refresh control related registers.
rev. 5.00, 09/03, page 257 of 760 bit: 15 14 13 12 11 10 9 8 initial value:00000000 r/w:??????r/wr/w bit:76543210 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 10.2.12 cautions on accessing refresh control related registers rfcr, rtcsr, rtcnt, and rtcor require that a specific code be appended to the data when it is written to prevent data from being mistakenly overwritten by program overruns or other write operations (figure 10.5). perform reads and writes using the following methods: 1. when writing to rfcr, rtcsr, rtcnt, and rtcor, use only word transfer instructions. byte transfer instructions cannot be used. when writing to rtcnt, rtcsr, or rtcor, place b'10100101 in the upper byte and the write data in the lower byte. when writing to rfcr, place b'101001 in the upper 6 bits and the write data in the remaining bits, as shown in figure 10.5. 2. when reading from rfcr, rtcsr, rtcnt, and rtcor, carry out reads with a 16-bit width. 0 is read from undefined bits. 15 10 8 rtcsr, rtcnt, rtcor 0 rfcr 7 100101 15 10 10 0 9 1 0 0 1 write data write data figure 10.5 writing to rfcr, rtcsr, rtcnt, and rtcor
rev. 5.00, 09/03, page 258 of 760 10.2.13 mcs0 control register (mcscr0) the mcs0 control register (mcscr0) is a 16-bit readable/writable register that specifies the mcs[0] pin output conditions. mcscr0 is initialized to h'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. as the mcs[0] pin is multiplexed as the ptc0 pin, when using the pin as mcs[0] , bits pc0md[1:0] in the pccr register should be set to 00 (other function). bit: 15 14 13 12 11 10 9 8 ???????? initial value:00000000 r/w:rrrrrrrr bit:76543210 ? cs2/0 cap1 cap0 a25 a24 a23 a22 initial value:00000000 r/w: r r/w r/w r/w r/w r/w r/w r/w bits 15 to 7?reserved: these bits are always read as 0. the write value should always be 0. bit 6?cs2/cs0 select (cs2/0): selects whether an area 2 or area 0 address is to be decoded. bit 6: cs2/0 description 0 area 0 is selected 1 area 2 is selected only 0 should be used for the cs2/0 bit in mcscr0. either 0 or 1 may be used for mcscr1 to mcscr7. bits 5 and 4?connected memory size specification (cap1, cap0) bit 5: cap1 bit 4: cap0 description 0 0 32-mbit memory is connected 0 1 64-mbit memory is connected 1 0 128-mbit memory is connected 1 1 256-mbit memory is connected bits 3 to 0?start address specification (a25, a24, a23, a22): these bits specify the start address of the memory area for which mcs[0] is asserted.
rev. 5.00, 09/03, page 259 of 760 10.2.14 mcs1 control register (mcscr1) the mcs1 control register (mcscr1) specifies the mcs[1] pin output conditions. the bit configuration and functions are the same as those of mcscr0. 10.2.15 mcs2 control register (mcscr2) the mcs2 control register (mcscr2) specifies the mcs[2] pin output conditions. the bit configuration and functions are the same as those of mcscr0. 10.2.16 mcs3 control register (mcscr3) the mcs3 control register (mcscr3) specifies the mcs[3] pin output conditions. the bit configuration and functions are the same as those of mcscr0. 10.2.17 mcs4 control register (mcscr4) the mcs4 control register (mcscr4) specifies the mcs[4] pin output conditions. the bit configuration and functions are the same as those of mcscr0. 10.2.18 mcs5 control register (mcscr5) the mcs5 control register (mcscr5) specifies the mcs[5] pin output conditions. the bit configuration and functions are the same as those of mcscr0. 10.2.19 mcs6 control register (mcscr6) the mcs6 control register (mcscr6) specifies the mcs[6] pin output conditions. the bit configuration and functions are the same as those of mcscr0. 10.2.20 mcs7 control register (mcscr7) the mcs7 control register (mcscr7) specifies the mcs[7] pin output conditions. the bit configuration and functions are the same as those of mcscr0.
rev. 5.00, 09/03, page 260 of 760 10.3 bsc operation 10.3.1 endian/access size and data alignment the sh7709s supports both big endian, in which the 0 address is the most significant byte in the byte data, and little endian, in which the 0 address is the least significant byte. switching between the two is designated by an external pin (md5 pin) at the time of a power-on reset. after a power- on reset, big endian is engaged when md5 is low; little endian is engaged when md5 is high. three data bus widths are available for ordinary memory (byte, word, longword) and two data bus widths (word and longword) for synchronous dram. for the pcmcia interface, choose from byte and word. this means data alignment is done by matching the device?s data width and endian. the access unit must also be matched to the device?s bus width. this also means that when longword data is read from a byte-width device, four read operations must be performed. in the sh7709s, data alignment and conversion of data length is performed automatically between the respective interfaces. tables 10.7 to 10.12 show the relationship between endian, device data width, and access unit. table 10.7 32-bit external device/big-endian access and data alignment data bus strobe signals operation d31?d24 d23?d16 d15?d8 d7?d0 we3 we3 we3 we3 , dqmuu we2 we2 we2 we2 , dqmul we1 we1 we1 we1 , dqmlu we0 we0 we0 we0 , dqmll byte access at 0 data 7?0 ? ??asserted byte access at 1 ?data 7?0 ?? asserted byte access at 2 ??data 7?0 ?asserted byte access at 3 ???data 7?0 asserted word access at 0 data 15?8 data 7?0 ? ? asserted asserted word access at 2 ??data 15?8 data 7?0 asserted asserted longword access at 0 data 31?24 data 23?16 data 15?8 data 7?0 asserted asserted asserted asserted
rev. 5.00, 09/03, page 261 of 760 table 10.8 16-bit external device/big-endian access and data alignment data bus strobe signals operation d31? d24 d23? d16 d15?d8 d7?d0 we3 we3 we3 we3 , dqmuu we2 we2 we2 we2 , dqmul we1 we1 we1 we1 , dqmlu we0 we0 we0 we0 , dqmll byte access at 0 ? ? data 7?0 ?asserted? byte access at 1 ? ? ? data 7?0 asserted byte access at 2 ? ? data 7?0 ?asserted? byte access at 3 ? ? ? data 7?0 asserted word access at 0 ? ? data 15?8 data 7?0 asserted asserted word access at 2 ? ? data 15?8 data 7?0 asserted asserted 1st time at 0 ??data 31?24 data 23?16 asserted asserted longword access at 0 2nd time at 2 ??data 15?8 data 7?0 asserted asserted
rev. 5.00, 09/03, page 262 of 760 table 10.9 8-bit external device/big-endian access and data alignment data bus strobe signals operation d31? d24 d23? d16 d15? d8 d7?d0 we3 we3 we3 we3 , dqmuu we2 we2 we2 we2 , dqmul we1 we1 we1 we1 , dqmlu we0 we0 we0 we0 , dqmll byte access at 0 ? ? ? data 7?0 asserted byte access at 1 ? ? ? data 7?0 asserted byte access at 2 ? ? ? data 7?0 asserted byte access at 3 ? ? ? data 7?0 asserted word access at 0 1st time at 0 ?? ?data 15?8 asserted 2nd time at 1 ?? ?data 7?0 asserted word access at 2 1st time at 2 ?? ?data 15?8 asserted 2nd time at 3 ?? ?data 7?0 asserted longword access at 0 1st time at 0 ?? ?data 31?24 asserted 2nd time at 1 ?? ?data 23?16 asserted 3rd time at 2 ?? ?data 15?8 asserted 4th time at 3 ?? ?data 7?0 asserted
rev. 5.00, 09/03, page 263 of 760 table 10.10 32-bit external device/little-endian access and data alignment data bus strobe signals operation d31?d24 d23?d16 d15?d8 d7?d0 we3 we3 we3 we3 , dqmuu we2 we2 we2 we2 , dqmul we1 we1 we1 we1 , dqmlu we0 we0 we0 we0 , dqmll byte access at 0 ???data 7?0 asserted byte access at 1 ??data 7?0 ?asserted byte access at 2 ?data 7?0 ?? asserted byte access at 3 data 7?0 ???asserted word access at 0 ??data 15?8 data 7?0 asserted asserted word access at 2 data 15?8 data 7?0 ? ? asserted asserted longword access at 0 data 31?24 data 23?16 data 15?8 data 7?0 asserted asserted asserted asserted table 10.11 16-bit external device/little-endian access and data alignment data bus strobe signals operation d31? d24 d23? d16 d15?d8 d7?d0 we3 we3 we3 we3 , dqmuu we2 we2 we2 we2 , dqmul we1 we1 we1 we1 , dqmlu we0 we0 we0 we0 , dqmll byte access at 0 ? ? ? data 7?0 asserted byte access at 1 ? ? data 7?0 ?asserted byte access at 2 ? ? ? data 7?0 asserted byte access at 3 ? ? data 7?0 ?asserted word access at 0 ? ? data 15?8 data 7?0 asserted asserted word access at 2 ? ? data 15?8 data 7?0 asserted asserted 1st time at 0 ??data 15?8 data 7?0 asserted asserted longword access at 0 2nd time at 2 ??data 31?24 data 23?16 asserted asserted
rev. 5.00, 09/03, page 264 of 760 table 10.12 8-bit external device/little-endian access and data alignment data bus strobe signals operation d31? d24 d23? d16 d15?d8 d7?d0 we3 we3 we3 we3 , dqmuu we2 we2 we2 we2 , dqmul we1 we1 we1 we1 , dqmlu we0 we0 we0 we0 , dqmll byte access at 0 ? ? ? data 7?0 asserted byte access at 1 ? ? ? data 7?0 asserted byte access at 2 ? ? ? data 7?0 asserted byte access at 3 ? ? ? data 7?0 asserted word access at 0 1st time at 0 ???data 7?0 asserted 2nd time at 1 ???data 15?8 asserted word access at 2 1st time at 2 ???data 7?0 asserted 2nd time at 3 ???data 15?8 asserted longword access at 0 1st time at 0 ???data 7?0 asserted 2nd time at 1 ???data 15?8 asserted 3rd time at 2 ???data 23?16 asserted 4th time at 3 ???data 31?24 asserted
rev. 5.00, 09/03, page 265 of 760 10.3.2 description of areas area 0: area 0 physical address bits a28?a26 are 000. address bits a31?a29 are ignored and the address range is h'00000000 + h'20000000 n ? h'03ffffff + h'20000000 n (n = 0?6 and n = 1?6 are the shadow spaces). ordinary memories such as sram, rom, and burst rom can be connected to this space. byte, word, or longword can be selected as the bus width using external pins md3 and md4. when the area 0 space is accessed, the cs0 signal is asserted. the rd signal that can be used as oe and the we0 ? we3 signals for write control are also asserted. the number of bus cycles is selected between 0 and 10 wait cycles using the a0w2?a0w0 bits in wcr2. when the burst function is used, the bus cycle pitch of the burst cycle is determined within a range of 2?10 according to the number of waits. area 1: area 1 physical address bits a28?a26 are 001. address bits a31?a29 are ignored and the address range is h'04000000 + h'20000000 n ? h'07ffffff + h'20000000 n (n = 0?6 and n = 1?6 are the shadow spaces). area 1 is the area specifically for internal peripheral modules. external memories cannot be connected. control registers of the peripheral modules shown below are mapped to this area 1. their addresses are physical addresses, to which logical addresses can be mapped when the mmu is enabled: dmac, port, irda, scif, adc, dac, intc (except intevt, ipra, iprb) these registers must be set not to be cached by using software. area 2: area 2 physical address bits a28?a26 are 010. address bits a31?a29 are ignored and the address range is h'08000000 + h'20000000 n ? h'0bffffff + h'20000000 n (n = 0?6 and n = 1?6 are the shadow spaces). ordinary memories such as sram and rom, as well as synchronous dram, can be connected to this space. byte, word, or longword can be selected as the bus width using bits a2sz1 and a2sz0 in bcr2 for ordinary memory. when the area 2 space is accessed, the cs2 signal is asserted. when ordinary memories are connected, the rd signal that can be used as oe and the we0 ? we3 signals for write control are also asserted and the number of bus cycles is selected between 0 and 3 wait cycles using bits a2w1 and a2w0 bits in wcr2. only when ordinary memories are connected, any way can be inserted in each bus cycle by means of the external wait pin ( wait ). when synchronous dram is connected, the ras3u and ras3l signals, casu and casl signals, rd/ wr signal, and byte control signals dqmhh, dqmhl, dqmlh, and dqmll are all asserted and addresses multiplexed. control of ras3u , ras3l , casu , casl , data timing, and address multiplexing is set with mcr.
rev. 5.00, 09/03, page 266 of 760 area 3: area 3 physical address bits a28?a26 are 011. address bits a31?a29 are ignored and the address range is h'0c000000 + h'20000000 n ? h'0fffffff + h'20000000 n (n = 0?6 and n = 1?6 are the shadow spaces). ordinary memories such as sram and rom, as well as synchronous dram, can be connected to this space. byte, word or longword can be selected as the bus width using bits a3sz1 and a3sz0 bits in bcr2 for ordinary memory. when area 3 space is accessed, cs3 is asserted. when ordinary memories are connected, the rd signal that can be used as oe and the we0 ? we3 signals for write control are asserted and the number of bus cycles is selected between 0 and 3 wait cycles using the a3w1 and a3w0 bits in wcr2. when synchronous dram is connected, the ras3u and ras3l signals, casu and casl signals, rd/ wr signal, and byte control signals dqmhh, dqmhl, dqmlh, and dqmll are all asserted and addresses multiplexed. area 4: area 4 physical address bits a28?a26 are 100. address bits a31?a29 are ignored and the address range is h'10000000 + h'20000000 n ? h'13ffffff + h'20000000 n (n = 0?6 and n = 1?6 are the shadow spaces). only ordinary memories such as sram and rom can be connected to this space. byte, word, or longword can be selected as the bus width using bits a4sz1 and a4sz0 in bcr2. when the area 4 space is accessed, the cs4 signal is asserted. the rd signal that can be used as oe and the we0 ? we3 signals for write control are also asserted. the number of bus cycles is selected between 0 and 10 wait cycles using the a4w2?a4w0 bits in wcr2. any wait can be inserted in each bus cycle by means of the external wait pin ( wait ). area 5: area 5 physical address bits a28?a26 are 101. address bits a31?a29 are ignored and the address range is the 64 mbytes at h'14000000 + h'20000000 n ? h'17ffffff + h'20000000 n (n = 0?6 and n = 1?6 are the shadow spaces). ordinary memories such as sram and rom as well as burst rom and pcmcia interfaces can be connected to this space. when the pcmcia interface is used, the ic memory card interface address range comprises the 32 mbytes at h'14000000 + h'20000000 n to h'15ffffff + h'20000000 n (n = 0?6 and n = 1?6 are the shadow spaces), and the i/o card interface address range comprises the 32 mbytes at h'16000000 + h'20000000 n to h'17ffffff + h'20000000 n (n = 0?6 and n = 1?6 are the shadow spaces). for ordinary memory and burst rom, byte, word, or longword can be selected as the bus width using bits a5sz1 and a5sz0 in bcr2. for the pcmcia interface, byte or word can be selected as the bus width using bits a5sz1 and a5sz0 bits in bcr2.
rev. 5.00, 09/03, page 267 of 760 when the area 5 space is accessed and ordinary memory is connected, the cs5 signal is asserted. the rd signal that can be used as oe and the we0 ? we3 signals for write control are also asserted. when the pcmcia interface is used, the ce1a signal, ce2a signal, rd signal as oe signal, and we1 signal are asserted. the number of bus cycles is selected between 0 and 10 wait cycles using the a5w2?a5w0 bits in wcr2. with the pcmcia interface, from 0 to 38 wait cycles can be selected using the a5w2? a5w0 bits in wcr2 and the a5w3 bit in pcr. in addition, any number of waits can be inserted in each bus cycle by means of the external wait pin ( wait ). when a burst function is used, the bus cycle pitch of the burst cycle is determined within a range of 2?11 (2?39 for the pcmcia interface) according to the number of waits. the setup and hold times of address/ cs5 for the read/write strobe signals can be set in the range 0.5?7.5 using bits a5ted2?a5ted0 and a5teh2?a5teh0 in the pcr register. area 6: area 6 physical address bits a28?a26 are 110. address bits a31?a29 are ignored and the address range is the 64 mbytes at h'18000000 + h'20000000 n ? h'1bffffff + h'20000000 n (n = 0?6 and n = 1?6 are the shadow spaces). ordinary memories such as sram and rom as well as burst rom and pcmcia interfaces can be connected to this space. when the pcmcia interface is used, the ic memory card interface address range is 32 mbytes at h'18000000 + h'20000000 n ? h'19ffffff + h'20000000 n and the i/o card interface address range is 32 mbytes at h'1a000000 + h'20000000 n ? h'1bffffff + h'20000000 n (n = 0?6 and n = 1?6 are the shadow spaces). for ordinary memory and burst rom, byte, word, or longword can be selected as the bus width using bits a6sz1 and a6sz0 in bcr2. for the pcmcia interface, byte or word can be selected as the bus width using bits a6sz1 and a6sz0 in bcr2. when the area 6 space is accessed and ordinary memory is connected, the cs6 signal is asserted. the rd signal that can be used as oe and the we0 ? we3 signals for write control are also asserted. when the pcmcia interface is used, the ce1b signal, ce2b signal, rd signal as oe signal, and we , iciord , and iciowr signals are asserted. the number of bus cycles is selected between 0 and 10 wait cycles using the a6w2?a6w0 bits in wcr2. with the pcmcia interface, from 0 to 38 wait cycles can be selected using the a6w2? a6w0 bits in wcr2 and the a6w3 bit in pcr. in addition, any number of waits can be inserted in each bus cycle by means of the external wait pin ( wait ). the bus cycle pitch of the burst cycle is determined within a range of 2?11 (2?39 for the pcmcia interface) according to the number of waits. the address/ cs6 setup and hold times for the read/write strobe signals can be set in the range 0.5?7.5 using bits a6ted2?a6ted0 and a6teh2?a6teh0 in the pcr register.
rev. 5.00, 09/03, page 268 of 760 10.3.3 basic interface basic timing: the basic interface of the sh7709s uses strobe signal output in consideration of the fact that mainly static ram will be directly connected. figure 10.6 shows the basic timing of normal space accesses. a no-wait normal access is completed in two cycles. the bs signal is asserted for one cycle to indicate the start of a bus cycle. the csn signal is negated on the t2 clock falling edge to secure the negation period. therefore, in case of access at minimum pitch, there is a half-cycle negation period. there is no access size specification when reading. the correct access start address is output in the least significant bit of the address, but since there is no access size specification, 32 bits are always read in case of a 32-bit device, and 16 bits in case of a 16-bit device. when writing, only the we signal for the byte to be written is asserted. for details, see section 10.3.1, endian/access size and data alignment. read/write for cache fill or write-back follows the set bus width and transfers a total of 16 bytes continuously. the bus is not released during this transfer. for cache misses that occur during byte or word operand accesses or branching to odd word boundaries, the fill is always performed by longword accesses on the chip-external interface. write-through-area write access and non- cacheable read/write access are based on the actual address size.
rev. 5.00, 09/03, page 269 of 760 t 1 ckio a25 to a0 csn rd/wr rd d31 to d0 wen d31 to d0 bs t 2 read write figure 10.6 basic timing of basic interface
rev. 5.00, 09/03, page 270 of 760 figures 10.7, 10.8, and 10.9 show examples of connection to 32, 16, and 8-bit data-width static ram, respectively. ???? ???? ???? ???? ???? a16 a0 cs oe i/o7 i/o0 we ???? ???? ???? ???? a18 a2 csn rd d31 d24 we3 d23 d16 we2 d15 d8 we1 d7 d0 we0 sh7709s 128k 8-bit sram ???? a16 a0 cs oe i/o7 i/o0 we ???? ???? ???? ???? a16 a0 cs oe i/o7 i/o0 we ???? ???? ???? ???? a16 a0 cs oe i/o7 i/o0 we ???? ???? ???? ???? ???? figure 10.7 example of 32-bit data-width static ram connection
rev. 5.00, 09/03, page 271 of 760 a16 a0 cs oe i/o7 i/o0 we ???? ???? ???? ???? a17 a1 csn rd d15 d8 we1 d7 d0 we0 sh7709s 128k 8-bit sram ???? a16 a0 cs oe i/o7 i/o0 we ???? ???? ???? ???? ???? ???? ???? figure 10.8 example of 16-bit data-width static ram connection
rev. 5.00, 09/03, page 272 of 760 a16 a0 csn rd d7 d0 we0 sh7709s 128k 8-bit sram ???? a16 a0 cs oe i/o7 i/o0 we ???? ???? ???? ???? ???? ???? ???? figure 10.9 example of 8-bit data-width static ram connection
rev. 5.00, 09/03, page 273 of 760 wait state control: wait state insertion on the basic interface can be controlled by the wcr2 settings. if the wcr2 wait specification bits corresponding to a particular area are not zero, a software wait is inserted in accordance with that specification. for details, see section 10.2.4, wait state control register 2 (wcr2). the specified number of tw cycles are inserted as wait cycles using the basic interface wait timing shown in figure 10.10. t 1 ckio a25 to a0 csn rd/ wr rd d31 to d0 wen d31 to d0 bs tw t 2 read write figure 10.10 basic interface wait timing (software wait only)
rev. 5.00, 09/03, page 274 of 760 when software wait insertion is specified by wcr2, the external wait input wait signal is also sampled. wait pin sampling is shown in figure 10.11. a 2-cycle wait is specified as a software wait. sampling is performed at the transition from the tw state to the t 2 state; therefore, if the wait signal has no effect if asserted in the t 1 cycle or the first tw cycle. when the waitsel bit in the wcr1 register is set to 1, the wait signal is sampled at the falling edge of the clock. if the setup time and hold times with respect to the falling edge of the clock are not satisfied, the value sampled at the next falling edge is used. however, the wait signal is ignored in the following three cases: ? a write to external address space in dual address mode with 16-byte dma transfer ? transfer from an external device with dack to external address space in single address mode with 16-byte dma transfer ? cache write-back access
rev. 5.00, 09/03, page 275 of 760 t 1 ckio a25 to a0 csn rd/ wr rd d31 to d0 wen d31 to d0 wait tw tw tw t 2 read write bs wait states inserted by wait signal figure 10.11 basic interface wait state timing (wait state insertion by wait wait wait wait signal waitsel = 1)
rev. 5.00, 09/03, page 276 of 760 10.3.4 synchronous dram interface synchronous dram direct connection: since synchronous dram can be selected by the cs signal, physical space areas 2 and 3 can be connected using ras and other control signals in common. if the memory type bits (dramtp2?0) in bcr1 are set to 010, area 2 is ordinary memory space and area 3 is synchronous dram space; if set to 011, areas 2 and 3 are both synchronous dram space. note, however, that synchronous dram must not be accessed when clock ratio i :b = 1:1. with the sh7709s, burst length 1 burst read/single write mode is supported as the synchronous dram operating mode. a data bus width of 16 or 32 bits can be selected. a 16-bit burst transfer is performed in a cache fill/write-back cycle, and only one access is performed in a write-through area write or a non-cacheable area read/write. the control signals for direct connection of synchronous dram are ras3l , ras3u , casl , casu , rd/ wr , cs2 or cs3 , dqmuu, dqmul, dqmlu, dqmll, and cke. all the signals other than cs2 and cs3 are common to all areas, and signals other than cke are valid and fetched to the synchronous dram only when cs2 or cs3 is asserted. synchronous dram can therefore be connected in parallel to a number of areas. cke is negated (low) only when self-refreshing is performed, and is always asserted (high) at other times. in the refresh cycle and mode-register write cycle, ras3u and ras3l or casu and casl are output. commands for synchronous dram are specified by ras3l , ras3u , casl , casu , rd/ wr , and special address signals. the commands are nop, auto-refresh (ref), self-refresh (self), precharge all banks (pall), row address strobe bank active (actv), read (read), read with precharge (reada), write (writ), write with precharge (writa), and mode register write (mrs). byte specification is performed by dqmuu, dqmul, dqmlu, and dqmll. a read/write is performed for the byte for which the corresponding dqm is low. in big-endian mode, dqmuu specifies an access to address 4n, and dqmll specifies an access to address 4n + 3. in little- endian mode, dqmuu specifies an access to address 4n + 3, and dqmll specifies an access to address 4n. figures 10.12 and 10.13 show examples of the connection of two 1m 16-bit 4-bank synchronous drams and one 1m 16-bit 4-bank synchronous dram, respectively.
rev. 5.00, 09/03, page 277 of 760 a15 a2 cki0 cke csn ras3x casx rd/ wr d31 d16 dqmuu dqmul d15 d0 dqmlu dqmll sh7709s 64m synchronous dram (1m 16-bit 4-bank) ???? a13 a0 clk cke cs ras cas we dq15 dq0 dqmu dqml ???? ???? ???? a13 a0 clk cke cs ras cas we dq15 dq0 dqmu dqml ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? note : "x" is u or l figure 10.12 example of 64-mbit synchronous dram connection (32-bit bus width)
rev. 5.00, 09/03, page 278 of 760 sh7709s 64m synchronous dram (1m 16 bit 4 bank) a14 a13 a12 a1 ckio cke csn ras3x casx rd/ wr d15 d0 dqmlu dqmll a13 a12 a11 a0 clk cke cs ras cas we dq15 dq0 dqmu dqml ??? ??? ??? ??? ??? ??? ??? ??? figure 10.13 example of 64-mbit synchronous dram connection (16-bit bus width) address multiplexing: synchronous dram can be connected without external multiplexing circuitry in accordance with the address multiplex specification bits amx2-amx0 in mcr. table 10.13 shows the relationship between the address multiplex specification bits and the bits output at the address pins. a25?a17 and a0 are not multiplexed; the original values are always output at these pins. when a0, the lsb of the synchronous dram address, is connected to the sh7709s, it performs longword address specification. connection should therefore be made in the following order: with a 32-bit bus width, connect pin a0 of the synchronous dram to pin a2 of the sh7709s, then connect pin a1 to pin a3; with a 16-bit bus width, connect pin a0 of the synchronous dram to pin a1 of the sh7709s, then connect pin a1 to pin a2.
rev. 5.00, 09/03, page 279 of 760 table 10.13 relationship between bus width, amx bits, and address multiplex output setting external address pins bus width memory type amx 3 amx 2 amx 1 amx 0 output timing a1 to a8 a9 a10 a11 a12 a13 a14 a15 a16 32 bits 4m 16bits 4banks * 1 1101column address a1 to a8 a9 a10 a11 l/h * 3 a13 a23 a24 * 4 a25 * 4 row address a10 to a17 a18 a19 a20 a21 a22 a23 a24 * 4 a25 * 4 2m 16bits 4banks * 2 0101column address a1 to a8 a9 a10 a11 l/h * 3 a13 a23 * 4 a24 * 4 row address a10 to a17 a18 a19 a20 a21 a22 a23 * 4 a24 * 4 1m 16bits 4banks * 2 0100column address a1 to a8 a9 a10 a11 l/h * 3 a13 a22 * 4 a23 * 4 row address a9 to a16 a17 a18 a19 a20 a21 a22 * 4 a23 * 4 2m 8bits 4banks * 2 0101column address a1 to a8 a9 a10 a11 l/h * 3 a13 a23 * 4 a24 * 4 row address a10 to a17 a18 a19 a20 a21 a22 a23 * 4 a24 * 4 512k 32bits 4banks * 2 0111column address a1 to a8 a9 a10 a11 l/h * 3 a21 * 4 a22 * 4 a15 row address a9 to a16 a17 a18 a19 a20 a21 * 4 a22 * 4 a23 16 bits 8m 16bits 4banks * 1 1110column address a1 to a8 a9 a10 l/h * 3 a12 a23 a24 * 4 a25 * 4 row address a11 to a18 a19 a20 a21 a22 a23 a24 * 4 a25 * 4 4m 16bits 4banks * 2 1101column address a1 to a8 a9 a10 l/h * 3 a12 a22 a23 * 4 a24 * 4 row address a10 to a17 a18 a19 a20 a21 a22 a23 * 4 a24 * 4
rev. 5.00, 09/03, page 280 of 760 setting external address pins bus width memory type amx 3 amx 2 amx 1 amx 0 output timing a1 to a8 a9 a10 a11 a12 a13 a14 a15 a16 2m 16bits 4banks * 2 0101column address a1 to a8 a9 a10 l/h * 3 a12 a22 * 4 a23 * 4 a24 row address a10 to a17 a18 a19 a20 a21 a22 * 4 a23 * 4 a24 1m 16bits 4banks * 2 0100column address a1 to a8 a9 a10 l/h * 3 a12 a21 * 4 a22 * 4 a15 row address a 9 to a16 a17 a18 a19 a20 a21 * 4 a22 * 4 a23 2m 8bits 4banks * 2 0101column address a1 to a8 a9 a10 l/h * 3 a12 a22 * 4 a23 * 4 a24 row address a10 to a17 a18 a19 a20 a21 a22 * 4 a23 * 4 a24 notes: 1. only ral3l or casl is output. 2. when addresses are upper 32 mbytes, ras3u or casu is output. when addresses are lower 32 mbytes, ras3l or casl is output. 3. l/h is a bit used in the command specification; it is fixed at l or h according to the access mode. 4. bank address specification
rev. 5.00, 09/03, page 281 of 760 table 10.14 example of correspondence between sh7709s and synchronous dram address pins (amx [3:0] = 0100 (32-bit bus width)) sh7709s address pin synchronous dram address pin ras cycle cas cycle function a15 a23 a23 a13(ba1) a14 a22 a22 a12(ba0) bank select bank address a13 a21 a13 a11 address a12 a20 l/h a10 address precharge setting a11 a19 a11 a9 a10 a18 a10 a8 a9 a17 a9 a7 a8 a16 a8 a6 a7 a15 a7 a5 a6 a14 a6 a4 a5 a13 a5 a3 a4 a12 a4 a2 a3 a11 a3 a1 a2 a10 a2 a0 address a1 a9 a1 not used a0 a0 a0 not used burst read: in the example in figure 10.15 it is assumed that four 2m 8-bit synchronous drams are connected and a 32-bit data width is used, and the burst length is 1. following the tr cycle in which actv command output is performed, a read command is issued in the tc1, tc2, and tc3 cycles, and a reada command in the tc4 cycle, and the read data is accepted at the rising edge of the external command clock (ckio) from cycle td1 to cycle td4. the tpc cycle is used to wait for completion of auto-precharge based on the reada command inside the synchronous dram; no new access command can be issued to the same bank during this cycle, but access to synchronous dram for another area is possible. in the sh7709s, the number of tpc cycles is determined by the tpc bit specification in mcr, and commands cannot be issued for the same synchronous dram during this interval. the example in figure 10.14 shows the basic cycle. to connect low-speed synchronous dram, the cycle can be extended by setting wcr2 and mcr bits. the number of cycles from the actv command output cycle, tr, to the read command output cycle, tc1, can be specified by the rcd bits in mcr, with values of 0 to 3 specifying 1 to 4 cycles, respectively. in case of 2 or more cycles, a trw cycle, in which an nop command is issued for the synchronous dram, is inserted between the tr cycle and the tc cycle. the number of cycles from read and reada command output cycles tc1-tc4 to the first read data latch cycle, td1, can be specified as 1 to 3 cycles
rev. 5.00, 09/03, page 282 of 760 independently for areas 2 and 3 by means of bits a2w1 and a2w0 or a3w1 and a3w0 in wcr2. this number of cycles corresponds to the number of synchronous dram cas latency cycles. ckio a25 to a16, a13 a12 a15, a14, a11 to a0 cs2 or cs3 ras3x casx rd/ wr dqmxx d31 to d0 bs tr tc1 tc2/td1 tc3/td2 tc4/td3 td4 tpc figure 10.14 basic timing for synchronous dram burst read
rev. 5.00, 09/03, page 283 of 760 figure 10.15 shows the burst read timing when rcd is set to 1, a3w1 and a3w0 are set to 10, and tpc is set to 1. the bs cycle, which is asserted for one cycle at the start of a bus cycle for normal access space, is asserted in each of cycles td1?td4 in a synchronous dram cycle. when a burst read is performed, the address is updated each time cas is asserted. as the unit of burst transfer is 16 bytes, address updating is performed for a3 and a2 only (when the bus width is 16 bits, address updating is performed for a3, a2, and a1). the order of access is as follows: in a fill operation in the event of a cache miss, the missed data is read first, then 16-byte boundary data including the missed data is read in wraparound mode. ckio a25 to a16, a13 a12 a15, a14, a11 to a0 cs2 or cs3 ras3x casx rd/ wr dqmxx d31 to d0 bs tr tc1 tc2 tc3/td1 tc4/td2 td3 tpc trw td4 figure 10.15 synchronous dram burst read wait specification timing
rev. 5.00, 09/03, page 284 of 760 single read: figure 10.16 shows the timing when a single address read is performed. as the burst length is set to 1 in synchronous dram burst read/single write mode, only the required data is output. consequently, no unnecessary bus cycles are generated even when a cache-through area is accessed. ckio a25 to a16, a13 a12 a15, a14, a11 to a0 cs2 or cs3 ras3x casx rd/ wr dqmxx d31 to d0 bs tr tc1 td1 tpc figure 10.16 basic timing for synchronous dram single read
rev. 5.00, 09/03, page 285 of 760 burst write: the timing chart for a burst write is shown in figure 10.17. in the sh7709s, a burst write occurs only in the event of cache write-back or 16-byte dmac transfer. in a burst write operation, following the tr cycle in which actv command output is performed, a writ command is issued in the tc1, tc2, and tc3 cycles, and a writa command that performs auto- precharge is issued in the tc4 cycle. in the write cycle, the write data is output at the same time as the write command. in case of the write with auto-precharge command, precharging of the relevant bank is performed in the synchronous dram after completion of the write command, and therefore no command can be issued for the same bank until precharging is completed. consequently, in addition to the precharge wait cycle, tpc, used in a read access, cycle trwl is also added as a wait interval until precharging is started following the write command. issuance of a new command for the same bank is deferred during this interval. the number of trwl cycles can be specified by the trwl bits in mcr.
rev. 5.00, 09/03, page 286 of 760 ckio csn rd/ wr ras3x casx dqmxx d31 to d0 (read) bs tr tc1 tc2 tc3 tc4 (trwl) (tpc) address upper bits a12, a11, a10 or a9 address lower bits figure 10.17 basic timing for synchronous dram burst write
rev. 5.00, 09/03, page 287 of 760 single write: the basic timing chart for write access is shown in figure 10.18. in a single write operation, following the tr cycle in which actv command output is performed, a writa command that performs auto-precharge is issued in the tc1 cycle. in the write cycle, the write data is output at the same time as the write command. in case of the write with auto-precharge command, precharging of the relevant bank is performed in the synchronous dram after completion of the write command, and therefore no command can be issued for the same bank until precharging is completed. consequently, in addition to the precharge wait cycle, tpc, used in a read access, cycle trwl is also added as a wait interval until precharging is started following the write command. issuance of a new command for the same bank is deferred during this interval. the number of trwl cycles can be specified by the trwl bits in mcr.
rev. 5.00, 09/03, page 288 of 760 ckio csn rd/ wr ras3x casx dqmxx d31 to d0 bs address upper bits a12 or a10 address lower bits cke tr tc1 (trwl) (tpc) figure 10.18 basic timing for synchronous dram single write
rev. 5.00, 09/03, page 289 of 760 bank active: the synchronous dram bank function is used to support high-speed accesses to the same row address. when the rasd bit in mcr is 1, read/write command accesses are performed using commands without auto-precharge (read, writ). in this case, precharging is not performed when the access ends. when accessing the same row address in the same bank, it is possible to issue the read or writ command immediately, without issuing an actv command, in the same way as in the ras down state in dram fast page mode. as synchronous dram is internally divided into two or four banks, it is possible to activate one row address in each bank. if the next access is to a different row address, a pre command is first issued to precharge the relevant bank, then when precharging is completed, the access is performed by issuing an actv command followed by a read or writ command. if this is followed by an access to a different row address, the access time will be longer because of the precharging performed after the access request is issued. in a write, when auto-precharge is performed, a command cannot be issued for a period of trwl + tpc cycles after issuance of the writa command. when bank active mode is used, read or writ commands can be issued successively if the row address is the same. the number of cycles can thus be reduced by trwl + tpc cycles for each write. the number of cycles between issuance of the precharge command and the row address strobe command is determined by the tpc bits in mcr. whether faster execution speed is achieved by use of bank active mode or by use of basic access is determined by the probability of accessing the same row address (p1), and the average number of cycles from completion of one access to the next access (ta). if ta is greater than tpc, the delay due to the precharge wait when writing is imperceptible. in this case, the access speed for bank active mode and basic access is determined by the number of cycles from the start of access to issuance of the read/write command: (tpc + trcd) (1 ? p1) and trcd, respectively. there is a limit on tras, the time for placing each bank in the active state. if there is no guarantee that there will not be a cache hit and another row address will be accessed within the period in which this value is maintained by program execution, it is necessary to set auto-refresh and set the refresh cycle to no more than the maximum value of tras. in this way, it is possible to observe the restrictions on the maximum active state time for each bank. if auto-refresh is not used, measures must be taken in the program to ensure that the banks do not remain active for longer than the prescribed time. a burst read cycle without auto-precharge is shown in figure 10.19, a burst read cycle for the same row address in figure 10.20, and a burst read cycle for different row addresses in figure 10.21. similarly, a burst write cycle without auto-precharge is shown in figure 10.22, a burst write cycle for the same row address in figure 10.23, and a burst write cycle for different row addresses in figure 10.24.
rev. 5.00, 09/03, page 290 of 760 a tnop cycle, in which no operation is performed, is inserted before the tc cycle in which the read command is issued in figure 10.20, but when synchronous dram is read, there is a two- cycle latency for the dqmxx signal that performs the byte specification. if the tc cycle were performed immediately, without inserting a tnop cycle, it would not be possible to perform the dqmxx signal specification for td1 cycle data output. this is the reason for inserting the tnop cycle. if the cas latency is two cycles or longer, tnop cycle insertion is not performed, since the timing requirements will be met even if the dqmxx signal is set after the tc cycle. when bank active mode is set, if only accesses to the respective banks in the area 3 space are considered, as long as accesses to the same row address continue, the operation starts with the cycle in figure 10.19 or 10.22, followed by repetition of the cycle in figure 10.20 or 10.23. an access to a different area 3 space during this time has no effect. if there is an access to a different row address in the bank active state, after this is detected the bus cycle in figure 10.21 or 10.24 is executed instead of that in figure 10.20 or 10.23. in bank active mode, too, all banks become inactive after a refresh cycle or after the bus is released as the result of bus arbitration. the bank active mode should not be used unless the bus width for all areas is 32 bits.
rev. 5.00, 09/03, page 291 of 760 ckio a25 to a16, a13 (a25 to a16, a11) a12 (a10) a15, a14, a11 to a0 (a15 to a12, a9 to a0) cs2 or cs3 ras3x casx rd/ wr dqmxx d31 to d0 bs tr tc1 tc2/td1 tc3/td2 tc4/td3 td4 figure 10.19 burst read timing (no precharge)
rev. 5.00, 09/03, page 292 of 760 ckio a25 to a16, a13 (a25 to a16, a11) a12 (a10) a15, a14, a11 to a0 (a15 to a12, a9 to a0) cs2 or cs3 ras3x casx rd/ wr dqmxx d31 to d0 bs tnop tc1 tc2/td1 tc3/td2 tc4/td3 td4 figure 10.20 burst read timing (same row address)
rev. 5.00, 09/03, page 293 of 760 ckio a25 to a16, a13 (a25 to a16, a11) a12 (a10) a15, a14, a11 to a0 (a15 to a12, a9 to a0) cs2 or cs3 ras3x casx rd/ wr dqmxx d31 to d0 bs tp tr tc1 tc2/td1 tc3/td2 tc4/td3 td4 figure 10.21 burst read timing (different row addresses)
rev. 5.00, 09/03, page 294 of 760 ckio a25 to a16, a13 (a25 to a16, a11) a12 (a10) a15, a14, a11 to a0 (a15 to a12, a9 to a0) cs2 or cs3 ras3x casx rd/ wr dqmxx d31 to d0 bs tr tc1 tc2 tc3 tc4 figure 10.22 burst write timing (no precharge)
rev. 5.00, 09/03, page 295 of 760 ckio a25 to a16, a13 (a25 to a16, a11) a12 (a10) a15, a14, a11 to a0 (a15 to a12, a9 to a0) cs2 or cs3 ras3x casx rd/ wr dqmxx d31 to d0 bs tc1 tc2 tc3 tc4 figure 10.23 burst write timing (same row address)
rev. 5.00, 09/03, page 296 of 760 ckio a25 to a16, a13 (a25 to a16, a11) a12 (a10) a15, a14, a11 to a0 (a15 to a12, a9 to a0) cs2 or cs3 ras3x casx rd/ wr dqmxx d31 to d0 bs tp tr tc1 tc2 tc3 td4 figure 10.24 burst write timing (different row addresses)
rev. 5.00, 09/03, page 297 of 760 refreshing: the bus state controller is provided with a function for controlling synchronous dram refreshing. auto-refreshing can be performed by clearing the rmode bit to 0 and setting the rfsh bit to 1 in mcr. if synchronous dram is not accessed for a long period, self-refresh mode, in which the power consumption for data retention is low, can be activated by setting both the rmode bit and the rfsh bit to 1. ? auto-refreshing refreshing is performed at intervals determined by the input clock selected by bits cks2-0 in rtcsr, and the value set in rtcor. the value of bits cks2-0 in rtcor should be set so as to satisfy the refresh interval stipulation for the synchronous dram used. first make the settings for rtcor, rtcnt, and the rmode and rfsh bits in mcr, then make the cks2- cks0 setting. when the clock is selected by cks2-cks0, rtcnt starts counting up from the value at that time. the rtcnt value is constantly compared with the rtcor value, and if the two values are the same, a refresh request is generated and an auto-refresh is performed. at the same time, rtcnt is cleared to zero and the count-up is restarted. figure 10.25 shows the auto-refresh cycle timing. all-bank precharging is performed in the tp cycle, then an ref command is issued in the trr cycle following the interval specified by the tpc bits in mcr. after the trr cycle, new command output cannot be performed for the duration of the number of cycles specified by the tras bits in mcr plus the number of cycles specified by the tpc bits in mcr. the tras and tpc bits must be set so as to satisfy the synchronous dram refresh cycle time stipulation (active/active command delay time). auto-refreshing is performed in normal operation, in sleep mode, and in case of a manual reset.
rev. 5.00, 09/03, page 298 of 760 rtcor value rtcnt h00000000 rtcsr.cks(2 to 0) cmf external bus cmf flag cleared by start of refresh cycle = 000 1 000 rtcnt cleared to 0 when rtcnt = rtcor auto-refresh cycle time figure 10.25 auto-refresh operation
rev. 5.00, 09/03, page 299 of 760 tp trr trrw trrw ckio cke csn ras3u , ras3l casu , casl rd/ wr figure 10.26 synchronous dram auto-refresh timing
rev. 5.00, 09/03, page 300 of 760 ? self-refreshing self-refresh mode is a kind of standby mode in which the refresh timing and refresh addresses are generated within the synchronous dram. self-refreshing is activated by setting both the rmode bit and the rfsh bit to 1. the self-refresh state is maintained while the cke signal is low. synchronous dram cannot be accessed while in the self-refresh state. self-refresh mode is cleared by clearing the rmode bit to 0. after self-refresh mode has been cleared, command issuance is disabled for the number of cycles specified by the tpc bits in mcr. self-refresh timing is shown in figure 10.27. settings must be made so that self-refresh clearing and data retention are performed correctly, and auto-refreshing is performed at the correct intervals. when self-refreshing is activated from the state in which auto-refreshing is set, or when exiting standby mode other than through a power-on reset, auto-refreshing is restarted if rfsh is set to 1 and rmode is cleared to 0 when self-refresh mode is cleared. if the transition from clearing of self-refresh mode to the start of auto-refreshing takes time, this time should be taken into consideration when setting the initial value of rtcnt. making the rtcnt value 1 less than the rtcor value will enable refreshing to be started immediately. after self-refreshing has been set, the self-refresh state continues even if the chip standby state is entered using the sh7709s?s standby function, and is maintained even after recovery from standby mode other than through a power-on reset. in case of a power-on reset, the bus state controller?s registers are initialized, and therefore the self-refresh state is cleared. self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in case of a manual reset. when using synchronous dram, use the following procedure to initiate self-refreshing. 1. clear the refresh control bit to 0. 2. write h'00 to the rtcnt register. 3. set the refresh control bit and refresh mode bit to 1.
rev. 5.00, 09/03, page 301 of 760 trs1 ckio rd/wr csn ras3u, ras3l casu, casl cke (trs2) (trs2) trs3 (tpc) (tpc) tp figure 10.27 synchronous dram self-refresh timing ? relationship between refresh requests and bus cycle requests if a refresh request is generated during execution of a bus cycle, execution of the refresh is deferred until the bus cycle is completed. if a refresh request occurs when the bus has been released by the bus arbiter, refresh execution is deferred until the bus is acquired. if a match between rtcnt and rtcor occurs while a refresh is waiting to be executed, so that a new refresh request is generated, the previous refresh request is eliminated. in order for refreshing to be performed normally, care must be taken to ensure that no bus cycle or bus right occurs that is longer than the refresh interval. when a refresh request is generated, the irqout pin is asserted (driven low). therefore, normal refreshing can be performed by having the irqout pin monitored by a bus master other than the sh7709s requesting the bus, or the bus arbiter, and returning the bus to the sh7709s. when refreshing is started, and if no other interrupt request has been generated, the irqout pin is negated (driven high).
rev. 5.00, 09/03, page 302 of 760 power-on sequence: in order to use synchronous dram, mode setting must first be performed after powering on. to perform synchronous dram initialization correctly, the bus state controller registers must first be set, followed by a write to the synchronous dram mode register. in synchronous dram mode register setting, the address signal value at that time is latched by a combination of the ras , cas , and rd/ wr signals. if the value to be set is x, the bus state controller provides for value x to be written to the synchronous dram mode register by performing a write to address h'ffffd000 + x for area 2 synchronous dram, and to address h'ffffe000 + x for area 3 synchronous dram. in this operation the data is ignored, but the mode write is performed as a byte-size access. to set burst read/single write, cas latency 1 to 3, wrap type = sequential, and burst length 1 supported by the sh7709s, arbitrary data is written in a byte-size access to the following addresses. with 32-bit bus width: area 2 area 3 cas latency 1 ffffd840 ffffe840 cas latency 2 ffffd880 ffffe880 cas latency 3 ffffd8c0 ffffe8c0 with 16-bit bus width: area 2 area 3 cas latency 1 ffffd420 ffffe420 cas latency 2 ffffd440 ffffe440 cas latency 3 ffffd460 ffffe460 mode register setting timing is shown in figure 10.28. as a result of the write to address h'ffffd000 + x or h'ffffe000 + x, a precharge all banks (pall) command is first issued in the trp1 cycle, then a mode register write command is issued in the tmw1 cycle. address signals, when the mode-register write command is issued, are as follows: 32-bit bus width: a15?a9 = 0000100 (burst read and single write) a8?a6 = cas latency a5 = 0 (burst type = sequential) a4?a2 = 000 (burst length 1) 16-bit bus width: a14?a8 = 0000100 (burst read and single write) a7?a5 = cas latency a4 = 0 (burst type = sequential) a3?a1 = 000 (burst length 1)
rev. 5.00, 09/03, page 303 of 760 before mode register setting, a 100 s idle time (depending on the memory manufacturer) must be guaranteed after powering on requested by the synchronous dram. if the reset signal pulse width is greater than this idle time, there is no problem in performing mode register setting immediately. the number of dummy auto-refresh cycles specified by the manufacturer (usually 8) or more must be executed. this is usually achieved automatically while various kinds of initialization are being performed after auto-refresh setting, but a way of carrying this out more dependably is to set a short refresh request generation interval just while these dummy cycles are being executed. with simple read or write access, the address counter in the synchronous dram used for auto- refreshing is not initialized, and so the cycle must always be an auto-refresh cycle. ckio a11 a12 or a10 a9 to a2 csn rd/ wr ras3u or ras3l casu or casl d31 to d0 cke t rp1 t rp2 t rp3 t rp4 t mw1 t mw2 t mw3 t mw4 (high) a15 to a13 or a15 to a12 figure 10.28 synchronous dram mode write timing
rev. 5.00, 09/03, page 304 of 760 10.3.5 burst rom interface setting bits a0bst1?0, a5bst1?0, and a6bst1?0 in bcr1 to a non-zero value allows burst rom to be connected to areas 0, 5, and 6. the burst rom interface provides high-speed access to rom that has a nibble access function. the timing for nibble access to burst rom is shown in figure 10.29. two wait cycles are set. basically, access is performed in the same way as for normal space, but when the first cycle ends the cs0 signal is not negated, and only the address is changed before the next access is executed. when 8-bit rom is connected, the number of consecutive accesses can be set as 4, 8, or 16 by bits a0bst1?0, a5bst1?0, or a6bst1?0. when 16-bit rom is connected, 4 or 8 can be set in the same way. when 32-bit rom is connected, only 4 can be set. wait pin sampling is performed in the first access if one or more wait states are set, and is always performed in the second and subsequent accesses. the second and subsequent access cycles also comprise two cycles when a burst rom setting is made and the wait specification is 0. the timing in this case is shown in figure 10.30. however, the wait signal is ignored in the following three cases: ? a write to external address space in dual address mode with 16-byte dma transfer ? transfer from an external device with dack to external address space in single address mode with 16-byte dma transfer ? cache write-back access
rev. 5.00, 09/03, page 305 of 760 t 1 t w t w t b2 t b1 t w t b2 ckio a25 to a4 a3 to a0 csn rd/ wr rd d31 to d0 bs wait t 2 note: for a write cycle, a basic bus cycle (write cycle) is performed. t b1 figure 10.29 burst rom wait access timing
rev. 5.00, 09/03, page 306 of 760 t 1 t b2 t b1 t b2 t b1 t b2 t b1 t 2 ckio a25 to a4 a3 to a0 csn rd/ wr rd d31 to d0 bs wait note: for a write cycle, a basic bus cycle (write cycle) is performed. figure 10.30 burst rom basic access timing
rev. 5.00, 09/03, page 307 of 760 10.3.6 pcmcia interface in the sh7709s, setting the a5pcm bit in bcr1 to 1 makes the bus interface for physical space area 5 an ic memory card and i/o card interface as stipulated in jeida version 4.2 (pcmcia2.1). setting the a6pcm bit to 1 makes the bus interface for physical space area 6 an ic memory card and i/o card interface as stipulated in jeida version 4.2. when the pcmcia interface is used, a bus size of 8 or 16 bits can be set by bits a5sz1 and a5sz0, or a6sz1 and a6sz0, in bcr2. figure 10.31 shows an example of pcmcia card connection to the sh7709s. to enable active insertion of the pcmcia cards (i.e. insertion or removal while system power is being supplied), a 3-state buffer must be connected between the sh7709s?s bus interface and the pcmcia cards. as operation in big-endian mode is not explicitly stipulated in the jeida/pcmcia specifications, the pcmcia interface for the sh7709s in big-endian mode is stipulated independently. however, the wait signal is ignored in the following three cases: ? a write to external address space in dual address mode with 16-byte dma transfer ? transfer from an external device with dack to external address space in single address mode with 16-byte dma transfer ? cache write-back access
rev. 5.00, 09/03, page 308 of 760 a24 to a0 d15 to d0 rd/wr ce1b/(cs6) ce1a/(cs5) rd we1 iciord iciowr wait iois16 sh7709s a25 to a0 d15 to d0 ce2 oe we/pgm (iord) (iowr) wait (iois16) cd1, cd2 ce1 pc card (memory/io) g g g dir dir g d7 to d0 d15 to d8 a25 to a0 d15 to d0 ce2 oe we/pgm wait cd1, cd2 ce1 pc card (memory/io) g g g dir dir g d7 to d0 d15 to d8 ce2b ce2a output port card detection circuit card detection circuit figure 10.31 example of pcmcia interface
rev. 5.00, 09/03, page 309 of 760 memory card interface basic timing: figure 10.32 shows the basic timing for the pcmcia ic memory card interface. when physical space areas 5 and 6 are designated as pcmcia interface areas, bus accesses are automatically performed as ic memory card interface accesses. with a high external bus frequency (ckio), the setup and hold times for the address (a24?a0), card enable ( cs5 , ce2a , cs6 , ce2b ), and write data (d15?d0) in a write cycle, become insufficient with respect to rd and wr (the we pin in the sh7709s). the sh7709s provides for this by enabling setup and hold times to be set for physical space areas 5 and 6 in the pcr register. also, software waits by means of a wcr2 register setting and hardware waits by means of the wait pin can be inserted in the same way as for the basic interface. figure 10.33 shows the pcmcia memory bus wait timing.
rev. 5.00, 09/03, page 310 of 760 ckio tpcm1 tpcm2 a25 to a0 cexx rd/ wr d15 to d0 (read) d15 to d0 (write) rd (read) we (write) bs figure 10.32 basic timing for pcmcia memory card interface
rev. 5.00, 09/03, page 311 of 760 ckio tpcm0 a25 to a0 rd/ wr cexx rd (read) d15 to d0 (read) d15 to d0 (write) we (write) bs wait tpcm0w tpcm1 tpcm1w tpcm1w tpcm2 tpcm2w figure 10.33 wait timing for pcmcia memory card interface
rev. 5.00, 09/03, page 312 of 760 memory card interface burst timing: in the sh7709s, when the ic memory card interface is selected, page mode burst access mode can be used, for read access only, by setting bits a5bst1 and a5bst0 in bcr1 for physical space area 5, or bits a6bst1 and a6bst0 in bcr1 for area 6. this burst access mode is not stipulated in jeida version 4.2 (pcmcia2.1), but allows high- speed data access using rom provided with a burst mode, etc. burst access mode timing is shown in figures 10.34 and 10.35. ckio tpcm1 a25 to a4 cexx a3 to a0 rd/ wr rd (read) d15 to d0 (read) bs tpcm2 tpcm1 tpcm2 tpcm1 tpcm2 tpcm1 tpcm2 figure 10.34 basic timing for pcmcia memory card interface burst access
rev. 5.00, 09/03, page 313 of 760 ckio tpcm0 a25 to a4 cexx a3 to a0 rd/wr rd (read) d15 to d0 (read) bs wait tpcm1 tpcm1w tpcm1w tpcm1w tpcm2 tpcm1 tpcm1w tpcm2 tpcm2w figure 10.35 wait timing for pcmcia memory card interface burst access
rev. 5.00, 09/03, page 314 of 760 when the entire 32-mbyte memory space is used as ic memory card interface space, the common memory/attribute memory switching signal reg is generated using a port, etc. if 16 mbytes or less of memory space is sufficient, using 16 mbytes of memory space as common memory space and 16 mbytes as attribute memory space enables the a24 pin to be used for the reg signal. i/o space i/o space i/o space area 5: h14000000 area 5: h16000000 area 6: h18000000 area 6: h1a000000 area 5: h14000000 area 5: h15000000 area 5: h16000000 h17000000 area 6: h18000000 area 6: h19000000 area 6: h1a000000 h1b000000 attribute memory common memory attribute memory common memory i/o space up to 16-mbyte capacity (reg = a24) 32-mbyte capacity (reg = i/o port) common memory/ attribute memory common memory/ attribute memory figure 10.36 pcmcia space allocation
rev. 5.00, 09/03, page 315 of 760 i/o card interface timing: figures 10.37 and 10.38 show the timing for the pcmcia i/o card interface. switching between the i/o card interface and the ic memory card interface is performed according to the accessed address. when pcmcia is designed for physical space area 5, the bus access is automatically performed as an i/o card interface access when a physical address from h'16000000 to h'17ffffff is accessed. when pcmcia is designated for physical space area 6, the bus access is automatically performed as an i/o card interface access when a physical address from h'1a000000 to h'1bffffff is accessed. when accessing a pcmcia i/o card, the access should be performed using a non-cacheable area in virtual space (p2 or p3 space) or an area specified as non-cacheable by the mmu. when an i/o card interface access is made to a pcmcia card in little-endian mode, dynamic sizing of the i/o bus width is possible using the iois16 pin. when a 16-bit bus width is set for are 5 or area 6, if the iois16 signal is high during a word-size i/o bus cycle, the i/o port is recognized as being 8 bits in width. in this case, a data access for only 8 bits is performed in the i/o bus cycle being executed, followed automatically by a data access for the remaining 8 bits. figure 10.39 shows the basic timing for dynamic bus sizing. in big-endian mode, the iois16 signal is not supported, and should be fixed low.
rev. 5.00, 09/03, page 316 of 760 ckio tpci1 tpci2 a25 to a0 rd/ wr cexx iciord (read) d15 to d0 (read) iciowr (write) d15 to d0 (write) bs figure 10.37 basic timing for pcmcia i/o card interface
rev. 5.00, 09/03, page 317 of 760 ckio a25 to a0 rd/ wr cexx iciord (read) iciowr (write) d15 to d0 (read) d15 to d0 (write) bs wait iois16 tpci0 tpci0w tpci1 tpci1w tpci1w tpci2 tpci2w figure 10.38 wait timing for pcmcia i/o card interface
rev. 5.00, 09/03, page 318 of 760 ckio tpci0 a25 to a1 cexx a0 rd/ wr iciord (read) d15 to d0 (read) iciowr (write) d15 to d0 (write) bs wait iois16 tpci1 tpci1w tpci2 tpci1 tpci1w tpci2 tpci2w figure 10.39 dynamic bus sizing timing for pcmcia i/o card interface
rev. 5.00, 09/03, page 319 of 760 10.3.7 waits between access cycles a problem associated with higher external memory bus operating frequencies is that data buffer turn-off on completion of a read from a low-speed device may be too slow, causing a collision with data in the next access. this results in lower reliability or incorrect operation. to avoid this problem, a data collision prevention feature has been provided. this memorizes the preceding access area and the kind of read/write. if there is a possibility of a bus collision when the next access is started, a wait cycle is inserted before the access cycle thus preventing a data collision. there are two cases in which a wait cycle is inserted: when an access is followed by an access to a different area, and when a read access is followed by a write access from the sh7709s. when the sh7709s performs consecutive write cycles, the data transfer direction is fixed (from the sh7709s to other memory) and there is no problem. with read accesses to the same area, in principle, data is output from the same data buffer, and wait cycle insertion is not performed. bits aniw1 and aniw0 (n = 0, 2?6) in wcr1 specify the number of idle cycles to be inserted between access cycles when a physical space area access is followed by an access to another area, or when the sh7709s performs a write access after a read access to physical space area n. if there is originally space between accesses, the number of idle cycles inserted is the specified number of idle cycles minus the number of empty cycles. waits are not inserted between accesses when bus arbitration is performed, since empty cycles are inserted for arbitration purposes.
rev. 5.00, 09/03, page 320 of 760 t 1 ckio csm csn a25 to a0 bs rd/ wr rd d31 to d0 t 2 twait t 1 t 2 twait t 1 t 2 area m read area m inter-access wait specification area n inter-access wait specification area n space read area n space write figure 10.40 waits between access cycles 10.3.8 bus arbitration when a bus release request ( breq ) is asserted from an external device, buses are released after the bus cycle being executed is completed and a bus grant signal ( back ) is output . the bus is not released during burst transfers for cache fills or write-back, or tas instruction execution between the read cycle and write cycle. bus arbitration is not executed in multiple bus cycles that are generated when the data bus width is shorter than the access size; i.e. in the bus cycles when longword access is executed for the 8-bit memory. at the negation of breq , back is negated and bus use is restarted . see appendix a.1, pin states, for the pin states when the bus is released. the sh7709s sometimes needs to retrieve a bus it has released. for example, when memory generates a refresh request or an interrupt request internally, the sh7709s must perform the appropriate processing. the sh7709s has a bus request signal ( irqout ) for this purpose. when it must retrieve the bus, it asserts the irqout signal. devices asserting an external bus release request receive the assertion of the irqout signal and negate the breq signal to release the bus. the sh7709s retrieves the bus and carries out the processing.
rev. 5.00, 09/03, page 321 of 760 irqout irqout irqout irqout pin assertion conditions: ? when a memory refresh request has been generated but the refresh cycle has not yet begun ? when an interrupt is generated with an interrupt request level higher than the setting of the interrupt mask bits (i3?i0) in the status register (sr). (this does not depend on the sr.bl bit.) 10.3.9 bus pull-up with the sh7709s, address pin pull-up can be performed when the bus is released by setting the pula bit in bcr1 to 1. the address pins are pulled up for a 4-clock period after back is asserted. figure 10.41 shows the address pin pull-up timing. similarly, data pin pull-up can be performed by setting the puld bit in bcr1 to 1. the data pins should be pulled up when the data bus is not in use. the data pin pull-up timing for a read cycle is shown in figure 10.42, and the timing for a write cycle in figure 10.43. hi-z pull-up ckio a25 to a0 back figure 10.41 pull-up timing for pins a25 to a0
rev. 5.00, 09/03, page 322 of 760 pull-up ckio d31 to d0 rd csn pull-up figure 10.42 pull-up timing for pins d31 to d0 (read cycle) pull-up ckio d31 to d0 wen csn pull-up figure 10.43 pull-up timing for pins d31 to d0 (write cycle)
rev. 5.00, 09/03, page 323 of 760 10.3.10 mcs[0] mcs[0] mcs[0] mcs[0] to mcs[7] mcs[7] mcs[7] mcs[7] pin control the sh7709s is provided with pins mcs[0] ? mcs[7] as dedicated cs pins for the rom connected to area 0 or 2. assertion of mcs[0] ? mcs[7] is controlled by settings in mcscr0? mcscr7. this enables 32-, 64-, 128-, or 256-mbit memory to be connected to area 0 or area 2. however, only cs2/0 = 0 (area 0) should be used for mcscr0. table 10.15 shows mcscr0? mcscr7 settings and mcs[0] ? mcs[7] assertion conditions. as the mcs[0] ? mcs[7] pins are multiplexed as the ptc0?ptc7 pins, when using these pins as mcs[0] ? mcs[7] , the corresponding bits in the pccr register should be set to ?other function.? when cs2/0 = 0 in the mcscr0 and when the ptc0 pin is switched to mcs[0] (when pcomd1?pcomd0 are set to ?other function?), the cs0 pin is also switched to mcs[0] . as port register writes operate on the peripheral clock, they take time compared with instruction execution by the cpu operating on the high-speed internal clock. therefore, if an instruction that accesses mcs[1] to mcs[7] is located several instructions after an instruction that switches port c to mcs , the switch from ptc[n] to mcsn and from cs0 to mcs[0] may not be performed correctly. to prevent this problem, the following switching procedure should be used. ? when the program runs with cache on (1) to switch port c to mcs , set the corresponding bits in the pccr register to 00 ("other function"). (2) read the pccr register and check whether the set value is read. repeat until the set value is read. (3) perform a dummy read from non-cacheable cs0 space (e.g. address h'a0000000). this will result in an access to the cs0 space, and immediately afterward, cs0 will be switched to mcs[0] , and port c[n] will be switched to mcs[n] . (4) access can now be made to the mcs[1] to mcs[7] spaces. ? when the program runs in mcs[0] space with cache off (1) set the pccr register as in (1) above. (2) place at least three nop instructions after the instruction in (1). as a result, when the pccr register is rewritten, an access to the cs0 space will be generated, and immediately afterward, cs0 will be switched to mcs[0] , and port c[n] will be switched to mcs[n] . (3) access can now be made to the mcs[1] to mcs[7] spaces.
rev. 5.00, 09/03, page 324 of 760 table 10.15 mcscrx settings and mcs[x] mcs[x] mcs[x] mcs[x] assertion conditions (x: 0?7) mcscrx settings mcs[x] mcs[x] mcs[x] mcs[x] assertion conditions cs2/0 cap1 cap0 a25 a24 a23 a22 cs0 cs0 cs0 cs0 cs2 cs2 cs2 cs2 address bus a [25:0] notes 0110???lhh' 0000000 to h'1ffffff 256-mbit rom 1 ? ? ? l h h'2000000 to h'3ffffff 1 0 0 0 ? ? l h h'0000000 to h'0ffffff 128-mbit rom 0 1 ? ? l h h'1000000 to h'1ffffff 1 0 ? ? l h h'2000000 to h'2ffffff 1 1 ? ? l h h'3000000 to h'3ffffff 0 1 0 0 0 ? l h h'0000000 to h'07fffff 64-mbit rom 0 0 1 ? l h h'0800000 to h'0ffffff 0 1 0 ? l h h'1000000 to h'17fffff 0 1 1 ? l h h'1800000 to h'1ffffff 1 0 0 ? l h h'2000000 to h'27fffff 1 0 1 ? l h h'2800000 to h'2ffffff 1 1 0 ? l h h'3000000 to h'37fffff 1 1 1 ? l h h'3800000 to h'3ffffff 0 0 0 0 0 0 l h h'0000000 to h'03fffff 32-mbit rom 0 0 0 1 l h h'0400000 to h'07fffff 0 0 1 0 l h h'0800000 to h'0bfffff 0 0 1 1 l h h'0c00000 to h'0ffffff 0 1 0 0 l h h'1000000 to h'13fffff 0 1 0 1 l h h'1400000 to h'17fffff 0 1 1 0 l h h'1800000 to h'1bfffff 0 1 1 1 l h h'1c00000 to h'1ffffff 1 0 0 0 l h h'2000000 to h'23fffff 1 0 0 1 l h h'2400000 to h'27fffff 1 0 1 0 l h h'2800000 to h'2bfffff 1 0 1 1 l h h'2c00000 to h'2ffffff 1 1 0 0 l h h'3000000 to h'33fffff 1 1 0 1 l h h'3400000 to h'37fffff 1 1 1 0 l h h'3800000 to h'3bfffff 1 1 1 1 l h h'3c00000 to h'3ffffff
rev. 5.00, 09/03, page 325 of 760 mcscrx settings mcs[x] mcs[x] mcs[x] mcs[x] assertion conditions cs2/0 cap1 cap0 a25 a24 a23 a22 cs0 cs0 cs0 cs0 cs2 cs2 cs2 cs2 address bus a[25:0] notes 1110???hlh' 0000000 to h'1ffffff 256-mbit rom 1 ? ? ? h l h'2000000 to h'3ffffff 1 0 0 0 ? ? h l h'0000000 to h'0ffffff 128-mbit rom 0 1 ? ? h l h'1000000 to h'1ffffff 1 0 ? ? h l h'2000000 to h'2ffffff 1 1 ? ? h l h'3000000 to h'3ffffff 0 1 0 0 0 ? h l h'0000000 to h'07fffff 64-mbit rom 0 0 1 ? h l h'0800000 to h'0ffffff 0 1 0 ? h l h'1000000 to h'17fffff 0 1 1 ? h l h'1800000 to h'1ffffff 1 0 0 ? h l h'2000000 to h'27fffff 1 0 1 ? h l h'2800000 to h'2ffffff 1 1 0 ? h l h'3000000 to h'37fffff 1 1 1 ? h l h'3800000 to h'3ffffff 0 0 0 0 0 0 h l h'0000000 to h'03fffff 32-mbit rom 0 0 0 1 h l h'0400000 to h'07fffff 0 0 1 0 h l h'0800000 to h'0bfffff 0 0 1 1 h l h'0c00000 to h'0ffffff 0 1 0 0 h l h'1000000 to h'13fffff 0 1 0 1 h l h'1400000 to h'17fffff 0 1 1 0 h l h'1800000 to h'1bfffff 0 1 1 1 h l h'1c00000 to h'1ffffff 1 0 0 0 h l h'2000000 to h'23fffff 1 0 0 1 h l h'2400000 to h'27fffff 1 0 1 0 h l h'2800000 to h'2bfffff 1 0 1 1 h l h'2c00000 to h'2ffffff 1 1 0 0 h l h'3000000 to h'33fffff 1 1 0 1 h l h'3400000 to h'37fffff 1 1 1 0 h l h'3800000 to h'3bfffff 1 1 1 1 h l h'3c00000 to h'3ffffff
rev. 5.00, 09/03, page 326 of 760
rev. 5.00, 09/03, page 327 of 760 section 11 direct memory access controller (dmac) 11.1 overview the sh7709s includes a four-channel direct memory access controller (dmac). the dmac can be used in place of the cpu to perform high-speed transfers between external devices that have dack (transfer request acknowledge signal), external memory, memory-mapped external devices, and on-chip peripheral modules (irda, scif, a/d converter, and d/a converter). using the dmac reduces the burden on the cpu and increases overall operating efficiency. 11.1.1 features the dmac has the following features. ? four channels ? 4-gb address space in the architecture ? 16-byte transfer (in 16-byte transfer, four 32-bit reads are executed, followed by four 32-bit writes.) ? choice of 8-bit, 16-bit, 32-bit, or 16-byte transfer data length ? 16 mbytes (16,777,216 transfers) ? address mode: dual address mode and single address mode are supported. in addition, direct address transfer mode or indirect address transfer mode can be selected. ? dual address mode transfer: both the transfer source and transfer destination are accessed by address. dual address mode has direct address transfer mode and indirect address transfer mode. direct address transfer mode: the values specified in the dmac registers indicates the transfer source and transfer destination. two bus cycles are required for one data transfer. indirect address transfer mode: data is transferred with the address stored prior to the address specified in the transfer source address in the dmac. other operations are the same as those of direct address transfer mode. this function is only available in channel 3. four bus cycles are required for one data transfer. ? single address mode transfer: either the transfer source or transfer destination peripheral device is accessed (selected) by means of the dack signal, and the other device is accessed by address. one transfer unit of data is transferred in one bus cycle. ? channel functions: the transfer mode that can be specified depends on the channel: ? channel 0: external request can be accepted. ? channel 1: external request can be accepted. ? channel 2: this channel has a source address reload function, which reloads a source address every four transfers.
rev. 5.00, 09/03, page 328 of 760 ? channel 3: in this channel, direct address mode or indirect address transfer mode can be specified. ? reload function: the value that was specified in the source address register can be automatically reloaded every four dma transfers. this function is only available in channel 2. ? transfer requests ? external request (from two dreq pins (channels 0 and 1 only). dreq can be detected either by the falling edge or by low level.) ? on-chip module request (requests from on-chip peripheral modules such as serial communications interface (irda and scif), a/d converter (a/d) and a timer (cmt). this request can be accepted in all the channels.) ? auto request (the transfer request is generated automatically within the dmac.) ? selectable bus modes: cycle-steal mode or burst mode ? selectable channel priority levels: fixed mode: the channel priority is fixed. round-robin mode: the priority of the channel in which the execution request was accepted is made the lowest. ? interrupt request: an interrupt request to the cpu can be generated after the specified number of transfers.
rev. 5.00, 09/03, page 329 of 760 11.1.2 block diagram figure 11.1 shows a block diagram of the dmac. peripheral bus internal bus dreq0 , dreq1 iteration control sarn dmac module register control start-up control request priority control bus interface bus state controller on-chip peripheral module darn dmatcrn chcrn dmaor irda, scif a/d converter cmt dein external ram external rom external i/o (memory mapped) external i/o (with acknowledge) dack0 , dack1 drak0, drak1 legend dmaor: sarn: darn: dmatcrn: chcrn: dein: n = 0 to 3 dmac operation register dmac source address register dmac destination address register dmac transfer count register dmac channel control register dma transfer-end interrupt request to cpu figure 11.1 block diagram of dmac
rev. 5.00, 09/03, page 330 of 760 11.1.3 pin configuration table 11.1 shows the dmac pins. table 11.1 dmac pins channel name symbol i/o function 0 dma transfer request dreq0 i dma transfer request input from external device to channel 0 dma transfer request acceptance dack0 o strobe output to an external i/o upon dma transfer request from external device to channel 0 dma request acknowledge drak0 o output showing that dreq0 has been accepted 1 dma transfer request dreq1 i dma transfer request input from external device to channel 1 dma transfer request acceptance dack1 o strobe output to an external i/o upon dma transfer request from external device to channel 1 dma request acknowledge drak1 o output showing that dreq1 has been accepted
rev. 5.00, 09/03, page 331 of 760 11.1.4 register configuration table 11.2 summarizes the dmac registers. the dmac has a total of 17 registers: each channel has four registers, and one overall dmac control register. table 11.2 dmac registers channel name abbrevi- ation r/w initial value address register size access size 0 dma source address register 0 sar0 r/w undefined h'04000020 (h'a4000020) * 4 32 16, 32 * 2 dma destination address register 0 dar0 r/w undefined h'04000024 (h'a4000024) * 4 32 16, 32 * 2 dma transfer count register 0 dmatcr0 r/w undefined h'04000028 (h'a4000028) * 4 24 16, 32 * 3 dma channel control register 0 chcr0 r/w * 1 h'00000000 h'0400002c (h'a400002c) * 4 32 8, 16, 32 * 2 1 dma source address register 1 sar1 r/w undefined h'04000030 (h'a4000030) * 4 32 16, 32 * 2 dma destination address register 1 dar1 r/w undefined h'04000034 (h'a4000034) * 4 32 16, 32 * 2 dma transfer count register 1 dmatcr1 r/w undefined h'04000038 (h'a4000038) * 4 24 16, 32 * 3 dma channel control register 1 chcr1 r/w * 1 h'00000000 h'0400003c (h'a400003c) * 4 32 8, 16, 32 * 2 2 dma source address register 2 sar2 r/w undefined h'04000040 (h'a4000040) * 4 32 16, 32 * 2 dma destination address register 2 dar2 r/w undefined h'04000044 (h'a4000044) * 4 32 16, 32 * 2 dma transfer count register 2 dmatcr2 r/w undefined h'04000048 (h'a4000048) * 4 24 16, 32 * 3 dma channel control register 2 chcr2 r/w * 1 h'00000000 h'0400004c (h'a400004c) * 4 32 8, 16, 32 * 2
rev. 5.00, 09/03, page 332 of 760 channel name abbrevi- ation r/w initial value address register size access size 3 dma source address register 3 sar3 r/w undefined h'04000050 (h'a4000050) * 4 32 16, 32 * 2 dma destination address register 3 dar3 r/w undefined h'04000054 (h'a4000054) * 4 32 16, 32 * 2 dma transfer count register 3 dmatcr3 r/w undefined h'04000058 (h'a4000058) * 4 24 16, 32 * 3 dma channel control register 3 chcr3 r/w * 1 h'00000000 h'0400005c (h'a400005c) * 4 32 8, 16, 32 * 2 shared dma operation register dmaor r/w * 1 h'0000 h'04000060 (h'a4000060) * 4 16 8, 16 * 2 notes: these registers are located in area 1 of physical space. therefore, when the cache is on, either access these registers from the p2 area of logical space or else make an appropriate setting using the mmu so that these registers are not cached. 1. only 0 can be written to bit 1 of chcr0 to chcr3, and bits 1 and 2 of dmaor to clear the flag after 1 is read. 2. if 16-bit access is used on sar0 to sar3, dar0 to dar3, and chcr0 to chcr3, the value in the 16 bits that were not accessed is retained. 3. dmatcr comprises the 24 bits from bit 0 to bit 23. the upper 8 bits, bits 24 to 31, cannot be written with 1 and are always read as 0. 4. when address translation by the mmu does not apply, the address in parentheses should be used.
rev. 5.00, 09/03, page 333 of 760 11.2 register descriptions 11.2.1 dma source address registers 0?3 (sar0?sar3) dma source address registers 0?3 (sar0?sar3) are 32-bit readable/writable registers that specify the source address of a dma transfer. during a dma transfer, these registers indicate the next source address. to transfer data in 16 bits or in 32 bits, specify a 16-bit or 32-bit address boundary address. when transferring data in 16-byte units, a 16-byte boundary (address 16n) must be set for the source address value. operation is not guaranteed if other addresses are specified. an undefined value will be returned in a reset. the previous value is retained in standby mode. bit: 31 30 29 28 27 26 25 24 initial value:???????? r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 ? 0 ? initial value: ? ? ? ? ? ? r/w: r/w r/w r/w r/w ? r/w
rev. 5.00, 09/03, page 334 of 760 11.2.2 dma destination address registers 0?3 (dar0?dar3) dma destination address registers 0?3 (dar0?dar3) are 32-bit readable/writable registers that specify the destination address of a dma transfer. these registers include a count function, and during a dma transfer, these registers indicate the next destination address. to transfer data in 16-bit or 32-bit units, make sure to specify a destination address with a 16-byte boundary (16n address). an undefined value will be returned in a reset. the previous value is retained in standby mode. bit: 31 30 29 28 27 26 25 24 initial value:???????? r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 ? 0 ? initial value: ? ? ? ? ? ? r/w: r/w r/w r/w r/w ? r/w
rev. 5.00, 09/03, page 335 of 760 11.2.3 dma transfer count registers 0?3 (dmatcr0?dmatcr3) dma transfer count registers 0?3 (dmatcr0?dmatcr3) are 24-bit readable/writable registers that specify the dma transfer count (bytes, words, or longwords). the number of transfers is 1 when the setting is h'000001, and 16,777,216 (the maximum) when h'000000 is set. during a dma transfer, these registers indicate the remaining number of transfers. in 16-byte transfer, one 16-byte transfer (128 bits) is counted as one. writing to upper eight bits in dmatcr is invalid; 0s are read if these bits are read. the write value should always be 0. an undefined value will be returned in a reset. the previous value is retained in standby mode. bit: 31 30 29 28 27 26 25 24 initial value:???????? r/w:rrrrrrrr bit: 23 22 21 20 ... 0 ... initial value:???? ... ? r/w: r/w r/w r/w r/w ... r/w
rev. 5.00, 09/03, page 336 of 760 11.2.4 dma channel control registers 0?3 (chcr0?chcr3) dma channel control registers 0?3 (chcr0?chcr3) are 32-bit readable/writable registers that specify the operation mode, transfer method, etc., for each channel. bit 20 is only used in chcr3; it is not used in chcr0 to chcr2. consequently, writing to this bit is invalid in chcr0 to chcr2; 0 is read if this bit is read. bit 19 is only used in chcr2; it is not used in chcr0, chcr1, and chcr3. consequently, writing to this bit is invalid in chcr0, chcr1, and chcr3; 0 is read if this bit is read. bits 6 and 16 to 18 are only used in chcr0 and chcr1; they are not used in chcr2 and chcr3. consequently, writing to these bits is invalid in chcr2 and chcr3; 0s are read if these bits are read. these register values are initialized to 0 in a reset. the previous value is retained in standby mode. bit: 31 ... 21 20 19 18 17 16 ? ... ? di ro rl am al initial value:0...000000 r/w: r ... r (r/w) * 2 (r/w) * 2 (r/w) * 2 (r/w) * 2 (r/w) * 2 bit: 15 14 13 12 11 10 9 8 dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 ?dstmts1ts0ietede initial value:00000000 r/w: r (r/w) * 2 r/w r/w r/w r/w r/(w) * 1 r/w notes: 1. only 0 can be written to the te bit after 1 is read. 2. the di, ro, rl, am, al, and ds bits are not included in some channels.
rev. 5.00, 09/03, page 337 of 760 bits 31 to 21?reserved: these bits are always read as 0. the write value should always be 0. bit 20?direct/indirect selection (di): selects direct address mode or indirect address mode in channel 3. this bit is only valid in chcr3. writing to this bit is invalid in chcr0 to chcr2; 0 is read if this bit is read. the write value should always be 0. when using 16-byte transfer, direct address mode must be specified. operation is not guaranteed if indirect address mode is specified. bit 20: di description 0 direct address mode operation for channel 3 (initial value) 1 indirect address mode operation for channel 3 bit 19?source address reload bit (ro): selects whether the source address initial value is reloaded in channel 2. this bit is only valid in chcr2. writing to this bit is invalid in chcr0, chcr1, and chcr3; 0 is read if this bit is read. the write value should always be 0. when using 16-byte transfer, this bit must be cleared to 0, specifying non-reloading. operation is not guaranteed if reloading is specified. bit 19: ro description 0 source address is not reloaded (initial value) 1 source address is reloaded bit 18?request check level bit (rl): specifies whether drak ( dreq acknowledge) signal output is active-high or active-low. this bit is only valid in chcr0 and chcr1. writing to this bit is invalid in chcr2 and chcr3; 0 is read if this bit is read. the write value should always be 0. bit 18: rl description 0 active-low drak output (initial value) 1 active-high drak output
rev. 5.00, 09/03, page 338 of 760 bit 17?acknowledge mode bit (am): specifies whether dack is output in the data read cycle or in the data write cycle in dual address mode. dack is always output in single address mode, regardless of this bit specification. this bit is only valid in chcr0 and chcr1. writing to this bit is invalid in chcr2 and chcr3; 0 is read if this bit is read. the write value should always be 0. bit 17: am description 0 dack output in read cycle (initial value) 1 dack output in write cycle bit 16?acknowledge level (al): specifies whether dack (acknowledge) signal output is active-high or active-low. this bit is only valid in chcr0 and chcr1. writing to this bit is invalid in chcr2 and chcr3; 0 is read if this bit is read. the write value should always be 0. bit 16: al description 0 active-low dack output (initial value) 1 active-high dack output bits 15 and 14?destination address mode bits 1 and 0 (dm1, dm0): select whether the dma destination address is incremented, decremented, or left fixed. bit 15: dm1 bit 14: dm0 description 0 0 fixed destination address (initial value) 0 1 destination address is incremented (+1 in 8-bit transfer, +2 in 16-bit transfer, +4 in 32-bit transfer, +16 in 16-byte transfer) 1 0 destination address is decremented (?1 in 8-bit transfer, ?2 in 16-bit transfer, ?4 in 32-bit transfer; illegal setting in 16-byte transfer) 1 1 setting prohibited
rev. 5.00, 09/03, page 339 of 760 bits 13 and 12?source address mode bits 1 and 0 (sm1, sm0): select whether the dma source address is incremented, decremented, or left fixed. bit 13: sm1 bit 12: sm0 description 0 0 fixed source address (initial value) 0 1 source address is incremented (+1 in 8-bit transfer, +2 in 16- bit transfer, +4 in 32-bit transfer, +16 in 16-byte transfer) 1 0 source address is decremented (?1 in 8-bit transfer, ?2 in 16- bit transfer, ?4 in 32-bit transfer; illegal setting in 16-byte transfer) 1 1 setting prohibited if the transfer source is specified by indirect address, specify the address holding the value of the address in which the data to be transferred is stored (i.e. the indirect address) in source address register 3 (sar3). specification of sar3 incrementing or decrementing in indirect address mode depends on the sm1 and sm0 settings. in this case, however, the sar3 increment or decrement value is +4, ?4, or fixed at 0, regardless of the transfer data size specified in ts1 and ts0.
rev. 5.00, 09/03, page 340 of 760 bits 11 to 8?resource select bits 3 to 0 (rs3 to rs0): specify which transfer requests will be sent to the dmac. bit 11: rs3 bit 10: rs2 bit 9: rs1 bit 8: rs0 description 0000external request * , dual address mode (initial value) 0 0 0 1 setting prohibited 0 0 1 0 external request / single address mode external address space external device with dack 0 0 1 1 external request / single address mode external device with dack external address space 0100auto request 0 1 0 1 setting prohibited 0 1 1 0 setting prohibited 0 1 1 1 setting prohibited 1 0 0 0 setting prohibited 1 0 0 1 setting prohibited 1010irda transmission 1011irda reception 1100scif transmission 1101scif reception 1110a/d converter 1111cmt notes: when using 16-byte transfer, the following settings must not be made: 1010 irda transmission 1011 irda reception 1100 scif transmission 1101 scif reception 1110 a/d converter 1111 cmt operation is not guaranteed if these settings are made. * external request specification is valid only in channels 0 and 1. none of the request sources can be selected in channels 2 and 3.
rev. 5.00, 09/03, page 341 of 760 bit 6? dreq dreq dreq dreq select bit (ds): selects low-level or falling-edge detection as the sampling method for the dreq pin used in external request mode. this bit is only valid in chcr0 and chcr1. writing to this bit is invalid in chcr2 and chcr3; 0 is read if this bit is read. the write value should always be 0. in channels 0 and 1, if an on-chip peripheral module is specified as a transfer request source or an auto-request is specified, the specification of this bit is ignored and falling-edge detection is fixed except in an auto-request. bit 6: ds description 0 dreq detected by low level (initial value) 1 dreq detected at falling edge bit 5?transmit mode (tm): specifies the bus mode when transferring data. bit 5: tm description 0 cycle-steal mode (initial value) 1 burst mode bits 4 and 3?transmit size bits 1 and 0 (ts1, ts0): specify the size of data to be transferred. bit 4: ts1 bit 3: ts0 description 0 0 byte size (8 bits) (initial value) 0 1 word size (16 bits) 1 0 longword size (32 bits) 1 1 16-byte unit (4 longword transfers) bit 2?interrupt enable bit (ie): if this bit is set to 1, an interrupt is requested on completion of the number of data transfers specified in dmatcr (i.e. when te = 1). bit 2: ie description 0 interrupt request is not generated on completion of data transfers specified in dmatcr (initial value) 1 interrupt request is generated on completion of data transfers specified in dmatcr
rev. 5.00, 09/03, page 342 of 760 bit 1?transfer end bit (te): set to 1 on completion of the number of data transfers specified in dmatcr. at this time, if the ie bit is set to 1, an interrupt request is generated. if data transfer ends due to an nmi interrupt, a dmac address error, or clearing of the de bit or the dme bit in dmaor before this bit is set to 1, this bit will not be set to 1. even if the de bit is set to 1 while this bit is set to 1, transfer is not enabled. bit 1: te description 0 data transfers specified in dmatcr not completed (initial value) clearing conditions: writing 0 to te after reading te = 1 power-on reset, manual reset 1 data transfers specified in dmatcr completed bit 0?dmac enable bit (de): enables operation of the corresponding channel. bit 0: de description 0 channel operation disabled (initial value) 1 channel operation enabled if an auto-request is specified (rs3 to rs0), transfer starts when this bit is set to 1. in an external request or an internal module request, transfer starts when a transfer request is generated after this bit is set to 1. clearing this bit during transfer terminates the transfer. even if the de bit is set, transfer is not enabled if the te bit is 1, the dme bit in dmaor is 0, or the nmif or ae bit in dmaor is 1.
rev. 5.00, 09/03, page 343 of 760 11.2.5 dma operation register (dmaor) the dma operation register (dmaor) is a 16-bit readable/writable register that controls the dmac transfer mode. these register values are initialized to 0 in a reset. the previous value is retained in standby mode. bit: 15 14 13 12 11 10 9 8 ??????pr1pr0 initial value:00000000 r/w:rrrrrrr/wr/w bit:76543210 ?????aenmifdme initial value:00000000 r/w:rrrrrr/(w) * r/(w) * r/w note: * only 0 can be written to the ae and nmif bits after 1 is read. bits 15 to 10?reserved: these bits are always read as 0. the write value should always be 0. bits 9 and 8?priority mode bits 1 and 0 (pr1, pr0): select the priority level between channels when there are simultaneous transfer requests for multiple channels. bit 9: pr1 bit 8: pr0 description 0 0 ch0 > ch1 > ch2 > ch3 (initial value) 0 1 ch0 > ch2 > ch3 > ch1 1 0 ch2 > ch0 > ch1 > ch3 1 1 round-robin bits 7 to 3?reserved: these bits are always read as 0. the write value should always be 0.
rev. 5.00, 09/03, page 344 of 760 bit 2?address error flag bit (ae): indicates that an address error occurred by the dmac. if this bit is set during data transfer, transfers on all channels are suspended. the cpu cannot write 1 to this bit. this bit can only be cleared by writing 0 after reading 1. bit 2: ae description 0 no dmac address error; dma transfer is enabled (initial value) clearing conditions: writing 0 to ae after reading ae = 1 power-on reset, manual reset 1 dmac address error; dma transfer is disabled this bit is set by occurrence of a dmac address error bit 1?nmi flag bit (nmif): indicates that an nmi is input. this bit is set regardless of whether the dmac is in the operating or halted state. the cpu cannot write 1 to this bit. only 0 can be written to clear this bit after 1 is read. bit 1: nmif description 0 no nmi input; dma transfer is enabled (initial value) clearing conditions: writing 0 to nmif after reading nmif = 1 power-on reset, manual reset 1 nmi input; dma transfer is disabled this bit is set by occurrence of an nmi interrupt bit 0?dma master enable bit (dme): enables or disables the dmac on all channels. if the dme bit and the de bit corresponding to each channel in chcr are set to 1, transfer is enabled on the corresponding channel. if this bit is cleared during transfer, transfer on all the channels will be terminated. even if the dme bit is set, transfer is not enabled if the te bit is 1 or the de bit is 0 in chcr, or the nmif or ae bit is 1 in dmaor. bit 0: dme description 0 dma transfer disabled on all channels (initial value) 1 dma transfer enabled on all channels
rev. 5.00, 09/03, page 345 of 760 11.3 operation when there is a dma transfer request, the dmac starts the transfer according to the predetermined channel priority order; when the transfer end conditions are satisfied, it ends the transfer. transfers can be requested in three modes: auto-request, external request, and on-chip module request. the dual address mode has direct address transfer mode and indirect address transfer mode. burst mode or cycle-steal mode can be selected as the bus mode. 11.3.1 dma transfer flow after the dma source address register (sar), dma destination address register (dar), dma transfer count register (dmatcr), dma channel control register (chcr), and dma operation register (dmaor) are set, the dmac transfers data according to the following procedure: 1. checks to see if transfer is enabled (de = 1, dme = 1, te = 0, ae = 0, nmif = 0) 2. when a transfer request comes and transfer is enabled, the dmac transfers 1 transfer unit of data (according to the ts0 and ts1 settings). for an auto-request, the transfer begins automatically when the de bit and dme bit are set to 1. the dmatcr value will be decremented for each transfer. the actual transfer flows vary by address mode and bus mode. 3. when the specified number of transfers have been completed (when dmatcr reaches 0), the transfer ends normally. if the ie bit in chcr is set to 1 at this time, a dei interrupt is sent to the cpu. 4. when an address error occurs by the dmac or an nmi interrupt is generated, the transfer is aborted. figure 11.2 is a flowchart of this procedure.
rev. 5.00, 09/03, page 346 of 760 normal end ae = 1 or nmif = 1 or de = 0 or dme = 0? bus mode, transfer request mode, dreq detection selection system initial settings (sar, dar, dmatcr, chcr, dmaor) transfer (1 transfer unit); dmatcr ? 1 ? dmatcr, sar and dar updated dei interrupt request (when ie = 1) no yes no yes no yes yes no yes no p 3 p 2 start transfer aborted dmatcr = 0? transfer request? p 1 de, dme = 1 and ae, nmif, te = 0? does ae = 1 or nmif = 1 or de = 0 or dme = 0? transfer end notes: 1. in auto-request mode, transfer begins when ae, nmif, and te are both 0 and the de and dme bits are set to 1. 2. dreq = level detection in burst mode (external request) or cycle-steal mode. 3. dreq = edge detection in burst mode (external request), or auto-request mode in burst mode. figure 11.2 dmac transfer flowchart
rev. 5.00, 09/03, page 347 of 760 11.3.2 dma transfer requests dma transfer requests are basically generated in either the data transfer source or destination, but they can also be generated by devices and on-chip peripheral modules that are neither the source nor the destination. transfers can be requested in three modes: auto-request, external request, and on-chip module request. the request mode is selected in the rs3?rs0 bits of dma channel control registers 0?3 (chcr0?chcr3). auto-request mode: when there is no transfer request signal from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, the auto-request mode allows the dmac to automatically generate a transfer request signal internally. when the de bit of chcr0?chcr3 and the dme bit of dmaor are set to 1, the transfer begins so long as the te bit of chcr0?chcr3 and the nmif and ae bits of dmaor are 0. external request mode: in this mode a transfer is performed in response to the request signal ( dreq ) of an external device. choose one of the modes shown in table 11.3 according to the application system. when this mode is selected, if dma transfer is enabled (de = 1, dme = 1, te = 0, ae = 0, nmif = 0), a transfer is performed upon a request at the dreq input. choose dreq detection by either a falling edge or low level of the signal input with the ds bit in chcr0 and chcr1 (ds = 0 for level detection, ds = 1 for edge detection). the source of the transfer request does not have to be the data transfer source or destination. table 11.3 selecting external request modes with rs bits rs3 rs2 rs1 rs0 address mode source destination 0000dual address mode any * any * 1 0 single address mode external memory, memory-mapped external device external device with dack 1 external device with dack external memory, memory-mapped external device note: * external memory, memory-mapped external device, on-chip memory, on-chip peripheral module (this applies only to irda, scif, a/d converter, d/a converter, and i/o ports.) on-chip module request mode: in this mode a transfer is performed in response to a transfer request signal (interrupt request signal) of an on-chip module. this mode cannot be set in case of 16-byte transfer. these are six transfer request signals: the receive-data-full interrupts (rxi) and the transmit-data-empty interrupts (txi) from two serial communication interfaces (irda, scif), the a/d conversion end interrupt (adi) of the a/d converter, and the compare match timer interrupt (cmi) of the cmt (table 11.4). when this mode is selected, if dma transfer is enabled (de = 1, dme = 1, te = 0, ae = 0, nmif = 0), a transfer is performed upon input of a transfer
rev. 5.00, 09/03, page 348 of 760 request signal. the source of the transfer request does not have to be the data transfer source or destination. when rxi is set as the transfer request, however, the transfer source must be the sci's receive data register (rdr). likewise, when txi is set as the transfer request, the transfer source must be the sci's transmit data register (tdr). if the transfer requester is the a/d converter, the data transfer source must be the a/d data register (addr). table 11.4 selecting on-chip peripheral module request modes with rs3-0 bits rs3 rs2 rs1 rs0 dma transfer request source dma transfer request signal source desti- nation bus mode 1010irda transmitter txi1 (irda transmit-data-empty interrupt transfer request) any * tdr1 cycle-steal 1011irda receiver rxi1 (irda receive-data-full interrupt transfer request) rdr1 any * cycle-steal 1100scif transmitter txi2 (scif transmit-data-empty interrupt transfer request) any * tdr2 cycle-steal 1101scif receiver rxi2 (scif receive-data-full interrupt transfer request) rdr1 any * cycle-steal 1110a/d converter adi (a/d conversion end interrupt) addr any * cycle-steal 1111cmt cmi (compare match timer interrupt) any * any * burst/ cycle-steal addr: a/d data register of a/d converter note: * external memory, memory-mapped external device, on-chip peripheral module (this applies only to irda, scif, a/d converter, d/a converter, and i/o ports.) when outputting transfer requests from on-chip peripheral modules, the appropriate interrupt enable bits must be set to output the interrupt signals. if the interrupt request signal of the on-chip peripheral module is used as a dma transfer request signal, an interrupt is not sent to the cpu. the dma transfer request signals in table 11.4 are automatically discontinued when the corresponding dma transfer is performed. if cycle-steal mode is being employed, they are withdrawn at the first transfer; if burst mode is being used, they are discontinued at the last transfer.
rev. 5.00, 09/03, page 349 of 760 11.3.3 channel priority when the dmac receives simultaneous transfer requests on two or more channels, it selects a channel according to a predetermined priority order. two modes (fixed mode and round-robin mode) are selected by priority bits pr1 and pr0 in the dma operation register (dmaor). fixed mode: in these modes, the priority order of the channels remain fixed. there are three kinds of fixed modes as follows: ch0 > ch1 > ch2 > ch3 ch0 > ch2 > ch3 > ch1 ch2 > ch0 > ch1 > ch3 these are selected by the pr1 and pr0 bits in dmaor. round-robin mode: each time one word, byte, or longword is transferred on one channel, the priority order is rotated. the channel on which the transfer was just finished rotates to the bottom of the priority order. the round-robin mode operation is shown in figure 11.3. the priority of the round-robin mode is ch0 > ch1 > ch2 > ch3 immediately after reset.
rev. 5.00, 09/03, page 350 of 760 ch1 > ch2 > ch3 > ch0 ch0 > ch1 > ch2 > ch3 ch2 > ch3 > ch0 > ch1 ch0 > ch1 > ch2 > ch3 ch2 > ch3 > ch0 > ch1 ch0 > ch1 > ch2 > ch3 ch0 > ch1 > ch2 > ch3 ch3 > ch0 > ch1 > ch2 ch0 > ch1 > ch2 > ch3 (1) when channel 0 transfers initial priority order initial priority order initial priority order priority order after transfer priority order after transfer priority order does not change. channel 2 becomes lowest- priority. the priority of channels 0 and 1, which were higher than channel 2, are also shifted. if immediately after there is a request to transfer channel 1 only, channel 1 becomes lowest-priority and the priority of channels 3 and 0, which were higher than channel 1, is also shifted. channel 1 becomes lowest- priority. the priority of channel 0, which was higher than channel 1, is also shifted. channel 0 becomes lowest- priority. priority order after transfer priority order after transfer priority order after transfer post-transfer priority order when there is an immediate transfer request to channel 1 only (2) when channel 1 transfers (3) when channel 2 transfers (4) when channel 3 transfers figure 11.3 round-robin mode
rev. 5.00, 09/03, page 351 of 760 figure 11.4 shows how the priority order changes when channel 0 and channel 3 transfers are requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. the dmac operates as follows: 1. transfer requests are generated simultaneously for channels 0 and 3. 2. channel 0 has a higher priority than channel 3, so the channel 0 transfer begins first (channel 3 waits for transfer). 3. a channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both waiting) 4. when the channel 0 transfer ends, channel 0 becomes lowest-priority. 5. at this point, channel 1 has a higher priority than channel 3, so the channel 1 transfer begins (channel 3 waits for transfer). 6. when the channel 1 transfer ends, channel 1 becomes lowest-priority. 7. the channel 3 transfer begins. 8. when the channel 3 transfer ends, channels 3 and 2 shift downward in priority so that channel 3 becomes the lowest-priority. transfer request waiting channel(s) dmac operation channel priority (1) channels 0 and 3 (3) channel 1 0 > 1 > 2 > 3 (2) channel 0 transfer start (4) channel 0 transfer ends (5) channel 1 transfer starts (6) channel 1 transfer ends (7) channel 3 transfer starts (8) channel 3 transfer ends 1 > 2 > 3 > 0 2 > 3 > 0 > 1 0 > 1 > 2 > 3 priority order changes priority order changes priority order changes none 3 3 1,3 figure 11.4 changes in channel priority in round-robin mode
rev. 5.00, 09/03, page 352 of 760 11.3.4 dma transfer types the dmac supports the transfers shown in table 11.5. dual address mode has a direct address mode and indirect address mode. in direct address mode, an output address value is the data transfer target address; in indirect address mode, the value stored in the output address, not the output address value itself, is the data transfer target address. data transfer timing depends on the bus mode, which may be cycle-steal mode or burst mode. table 11.5 supported dma transfers destination source external device with dack external memory memory- mapped external device on-chip peripheral module external device with dack not available dual, single dual, single not available external memory dual, single dual dual dual memory-mapped external device dual, single dual dual dual on-chip peripheral module not available dual dual dual notes: 1. dual: dual address mode 2. single: single address mode 3. dual address mode includes direct address mode and indirect address mode. 4. 16-byte transfer is not available for on-chip peripheral modules. address modes: ? dual address mode in dual address mode, both the transfer source and destination are accessed (selectable) by an address. the source and destination can be located externally or internally. dual address mode has (1) a direct address transfer mode and (2) an indirect address transfer mode.
rev. 5.00, 09/03, page 353 of 760 (1) in direct address transfer mode, dma transfer requires two bus cycles because data is read from the transfer source in a data read cycle and written to the transfer destination in a data write cycle. at this time, transfer data is temporarily stored in the dmac. in the transfer between external memories as shown in figure 11.5, data is read to the dmac from one external memory in a data read cycle, and then that data is written to the other external memory in a write cycle. figure 11.6 shows an example of the timing at this time. data buffer address bus data bus address bus data bus memory transfer source module transfer destination module memory transfer source module transfer destination module sar dar data buffer sar dar the sar value is an address, data is read from the transfer source module, and the data is temporarily stored in the dmac. first bus cycle second bus cycle the dar value is an address, and the value stored in the data buffer in the dmac is written to the transfer destination module. dmac dmac figure 11.5 operation of direct address mode in dual address mode
rev. 5.00, 09/03, page 354 of 760 (1st cycle) (2nd cycle) data read cycle data write cycle transfer source address transfer destination address ckio a25 to a0 csn d31 to d0 rd wen dackn note: in transfer between external memories, with dack output in the read cycle, dack output timing is the same as that of csn . figure 11.6 example of dma transfer timing in the direct address mode in dual mode (transfer source: ordinary memory, transfer destination: ordinary memory) (2) in indirect address transfer mode, the address of memory in which data to be transferred is stored is specified in the transfer source address register (sar3) in the dmac. consequently, in this mode, the address value specified in the transfer source address register in the dmac is read first. this value is temporarily stored in the dmac. next, the read value is output as an address, and the value stored in that address is stored in the dmac again. then, the value read afterwards is written to the address specified in the transfer destination address; this completes one dma transfer. 16-byte transfer is not possible. figure 11.7 shows an example. in this example, the transfer destination, the transfer source, and the storage destination of the indirect address are 16-bit external memories, and transfer data is 16 or 8 bits. figure 11.8 shows an example of the transfer timing.
rev. 5.00, 09/03, page 355 of 760 memory transfer source module transfer destination module sar3 dar3 data buffer temporary buffer d m a c when the value in sar3 is an address, the memory data is read and the value is stored in the temporary buffer. the value to be read must be 32 bits since it is used for the address. if data bus connected to an external memory space is 16 bits wide, two bus cycles are necessary. memory transfer source module data bus address bus transfer destination module sar3 dar3 data buffer temporary buffer d m a c memory transfer source module data bus address bus transfer destination module sar3 dar3 data buffer temporary buffer d m a c first and second bus cycles when the value in the temporary buffer is an address, the data is read from the transfer source module to the data buffer. third bus cycle fourth bus cycle when the value in sar3 is an address, the value in the data buffer is written to the transfer source module. note: this example shows memory, the transfer source module, and the transfer destination module; in practice, any module can be connected in the addressing space. data bus address bus figure 11.7 indirect address operation in dual address mode (when external memory space has a 16-bit width)
rev. 5.00, 09/03, page 356 of 760 transfer source address (h) transfer source address (l) indirect address nop transfer destination address indirect address (h) indirect address (l) transfer data transfer data transfer data transfer data transfer data transfer source address p 1 transfer source address p 2 indirect address nop indirect address address read cycle (1st) (2nd) (3rd) nop cycle data read cycle (4th) data write cycle ckio a25 to a0 csn d31 to d0 internal address bus internal data bus dmac indirect address buffer dmac data buffer rd wen notes: 1. 2. the internal address bus value does not change, and is controlled by the port. the dmac does not fetch the value until 32-bit data is output to the internal data bus. external memory space ? external memory space (external memory is 16-bit width) figure 11.8 example of transfer timing in the indirect address mode in dual address mode
rev. 5.00, 09/03, page 357 of 760 ? single address mode in single address mode, either the transfer source or transfer destination peripheral device is accessed (selected) by means of the dack signal, and the other device is accessed by address. in this mode, the dmac performs one dma transfer in one bus cycle, accessing one of the external devices by outputting the dack transfer request acknowledge signal to it, and at the same time outputting an address to the other device involved in the transfer. for example, in the case of transfer between external memory and an external device with dack shown in figure 11.9, when the external device outputs data to the data bus, that data is written to the external memory in the same bus cycle. dmac sh7709s dack dreq external address bus external data bus external memory external device with dack data flow figure 11.9 data flow in single address mode two kinds of transfer are possible in single address mode: (1) transfer between an external device with dack and a memory-mapped external device, and (2) transfer between an external device with dack and external memory. in both cases, only the external request signal ( dreq ) is used for transfer requests. figures 11.10 and 11.11 show examples of dma transfer timing in single address mode.
rev. 5.00, 09/03, page 358 of 760 address output to external memory space data output from external device with dack dack signal (active-low) to external device with dack write strobe signal to external memory space address output to external memory space data output from external memory space dack signal (active-low) to external device with dack read strobe signal to external memory space (a) external device with dack external memory space (ordinary memory) (b) external memory space (ordinary memory) external device with dack ckio a25 to a0 d31 to d0 dackn csn we bs ckio a25 to a0 d31 to d0 dackn csn rd bs figure 11.10 example of dma transfer timing in single address mode
rev. 5.00, 09/03, page 359 of 760 ckio a25 to a0 d31 to d0 rd wen dackn csn transfer source address +4 +8 +12 figure 11.11 example of dma transfer timing in single address mode (16-byte transfer, external memory space (ordinary memory) external device with dack) bus modes: there are two bus modes: cycle-steal and burst. select the mode in the tm bits of chcr0?chcr3. ? cycle-steal mode in cycle-steal mode, the bus is given to another bus master after a one-transfer-unit (byte, word, longword, or 16-byte unit) dmac. when another transfer request occurs, the bus is obtained from the other bus master and transfer is performed for one transfer unit. when that transfer ends, the bus is passed to the other bus master. this is repeated until the transfer end conditions are satisfied. in the cycle-steal mode, transfer areas are not affected regardless of the transfer request source, transfer source, and transfer destination settings. figure 11.12 shows an example of dma transfer timing in cycle-steal mode. transfer conditions shown in the figure are: dual address mode dreq level detection
rev. 5.00, 09/03, page 360 of 760 cpu cpu cpu dmac dmac cpu dmac dmac cpu cpu dreq bus cycle bus returned to cpu read write write read figure 11.12 example of dma transfer in cycle-steal mode ? burst mode once the bus is obtained, the transfer is performed continuously until the transfer end condition is satisfied. in external request mode with low level detection of the dreq pin, however, when the dreq pin is driven high, the bus passes to the other bus master after the dmac transfer request that has already been accepted ends, even if the transfer end conditions have not been satisfied. burst mode cannot be used when a serial communication interface (irda, sci), or a/d converter is the transfer request source. figure 11.13 shows an example of burst mode timing. cpu cpu cpu dmac dmac dmac dmac dmac dmac cpu dreq bus cycle read read read write write write figure 11.13 example of transfer in burst mode
rev. 5.00, 09/03, page 361 of 760 relationship between request modes and bus modes by dma transfer category: table 11.6 shows the relationship between request modes and bus modes by dma transfer category. table 11.6 relationship between request modes and bus modes by dma transfer category address mode transfer category request mode bus mode transfer size (bits) usable channels dual external device with dack and external memory external b/c 8/16/32/128 0,1 external device with dack and memory-mapped external device external b/c 8/16/32/128 0, 1 external memory and external memory all * 1 b/c 8/16/32/128 0?3 * 5 external memory and memory- mapped external device all * 1 b/c 8/16/32/128 0?3 * 5 memory-mapped external device and memory-mapped external device all * 1 b/c 8/16/32/128 0?3 * 5 external memory and on-chip peripheral module all * 2 b/c * 3 8/16/32 * 4 0?3 * 5 memory-mapped external device and on-chip peripheral module all * 2 b/c * 3 8/16/32 * 4 0?3 * 5 on-chip peripheral module and on- chip peripheral module all * 2 b/c * 3 8/16/32 * 4 0?3 * 5 single external device with dack and external memory external b/c 8/16/32/128 0, 1 external device with dack and memory-mapped external device external b/c 8/16/32/128 0, 1 b: burst, c: cycle-steal notes: 1. external requests, auto requests and on-chip peripheral module (cmt) requests are all available. 2. external requests, auto requests and on-chip peripheral module requests are all available. when the irda, scif, or a/d converter is also the transfer request source, however, the transfer destination or transfer source must be the irda, scif, or a/d converter, respectively. 3. if the transfer request source is the irda, scif, or a/d converter only cycle-steal mode is available. 4. the access size permitted when the transfer destination or source is an on-chip peripheral module register. 5. if the transfer request is an external request, only channels 0 and 1 are available.
rev. 5.00, 09/03, page 362 of 760 bus mode and channel priority order: when, for example, channel 1 is transferring in burst mode and there is a transfer request to channel 0, which has higher priority, the channel 0 transfer will begin immediately. at this time, if the priority is set in the fixed mode (ch0 > ch1), the channel 1 transfer will continue when the channel 0 transfer has completely finished, even if channel 0 is operating in cycle-steal mode or burst mode. if the priority is set in round-robin mode, channel 1 will begin operating again after channel 0 completes the transfer of one transfer unit, even if channel 0 is in cycle-steal mode or burst mode. the bus will then switch between the two in the order channel 1, channel 0, channel 1, channel 0. even if the priority is set in fixed mode or in round-robin mode, the bus will not be given to the cpu since channel 1 is in burst mode. this example is illustrated in figure 11.14. cpu dmac ch1 dmac ch1 dmac ch0 dmac ch1 dmac ch0 dmac ch1 dmac ch1 cpu ch0 ch1 ch0 round-robin mode in dmac ch0 and ch1 dmac ch1 burst mode cpu cpu priority: round-robin mode ch0: cycle-steal mode ch1: burst mode dmac ch1 burst mode figure 11.14 bus state when multiple channels are operating
rev. 5.00, 09/03, page 363 of 760 11.3.5 number of bus cycle states and dreq dreq dreq dreq pin sampling timing number of bus cycle states: when the dmac is the bus master, the number of bus cycle states is controlled by the bus state controller (bsc) in the same way as when the cpu is the bus master. for details, see section 10, bus state controller (bsc). dreq dreq dreq dreq pin sampling timing: in external request mode, the dreq pin is sampled by clock pulse (ckio) falling edge or low level detection. when dreq input is detected, a dmac bus cycle is generated and dma transfer performed, at the earliest, three states later. the second and subsequent dreq sampling operations are started two cycles after the first sample. operation ? cycle-steal mode in cycle-steal mode, the dreq sampling timing is the same regardless of whether level or edge detection is used. for example, in figure 11.15 (cycle-steal mode, level input), dmac transfer begins, at the earliest, three cycles after the first sampling is performed. the second sampling is started two cycles after the first. if dreq is not detected at this time, sampling is performed in each subsequent cycle. thus, dreq sampling is performed one step in advance. the third sampling operation is not performed until the idle cycle following the end of the first dma transfer. the above conditions are the same whatever the number of cpu transfer cycles, as shown in figure 11.16. the above conditions are also the same whatever the number of dma transfer cycles, as shown in figure 11.17. dack is output in a read in the example in figure 11.15, and in a write in the example in figure 11.16. in both cases, dack is output for the same duration as csn . figure 11.18 shows an example in which sampling is executed in all subsequent cycles when dreq cannot be detected.
rev. 5.00, 09/03, page 364 of 760 ? burst mode, level detection in the case of burst mode with level detection, the dreq sampling timing is the same as in cycle-steal mode. for example, in figure 11.20, dmac transfer begins, at the earliest, three cycles after the first sampling is performed. the second sampling is started two cycles after the first. subsequent sampling operations are performed in the idle cycle following the end of the dma transfer cycle. in burst mode, also, the dack output period is the same as in cycle-steal mode. ? burst mode, edge detection in the case of burst mode with edge detection, dreq sampling is only performed once. for example, in figure 11.21, dmac transfer begins, at the earliest, three cycles after the first sampling is performed. after this, dmac transfer is executed continuously until the number of data transfers set in the dmatcr register have been completed. dreq is not sampled during this time. to restart dmac after it has been suspended by an nmi, first clear nmif, then input an edge request again. in burst mode, also, the dack output period is the same as in cycle-steal mode.
rev. 5.00, 09/03, page 365 of 760 ckio drak dreq dack bus cycle dmac(r) cpu dmac(w) dmac(r) cpu dmac(w) 1st sampling 2nd sampling 3rd sampling figure 11.15 cycle-steal mode, level input (cpu access: 2 cycles)
rev. 5.00, 09/03, page 366 of 760 cpu cpu ckio drak dreq dack dmac(r) dmac(w) dmac(r) 1st sampling 2nd sampling 3rd sampling bus cycle figure 11.16 cycle-steal mode, level input (cpu access: 3 cycles)
rev. 5.00, 09/03, page 367 of 760 ckio drak (high output) bus cycle dreq dack (rd output) dmac(w) cpu dmac(w) dmac(r) cpu 1st sampling 2nd sampling 3rd sampling figure 11.17 cycle-steal mode, level input (cpu access: 2 cycles, dma rd access: 4 cycles)
rev. 5.00, 09/03, page 368 of 760 ckio drak bus cycle dreq dack (rd output) cpu cpu dmac(w) dmac(r) dmac(w) dmac(r) cpu 3rd sampling is performed, but since dreq is high, per-cycle sampling starts 2nd sampling is performed, but since dreq is high, per-cycle sampling starts 1st sampling2nd sampling 3rd sampling figure 11.18 cycle-steal mode, level input (cpu access: 2 cycles, dreq dreq dreq dreq input delayed)
rev. 5.00, 09/03, page 369 of 760 ckio drak bus cycle dreq dack (rd output) cpu cpu dmac(w) dmac(r) dmac(w) dmac(r) cpu high high high high 3rd sampling is performed, but since there is no dreq falling edge, per-cycle sampling starts 2nd sampling is performed, but since there is no dreq falling edge, per-cycle sampling starts 1st sampling 2nd sampling 3rd sampling note: when a dreq falling edge is detected, dreq must be high for at least one cycle before the sampling point. figure 11.19 cycle-steal mode, edge input (cpu access: 2 cycles)
rev. 5.00, 09/03, page 370 of 760 ckio drak dreq dack bus cycle dmac(r) dmac(w) dmac(r) dmac(w) dmac(r) cpu 1st sampling 2nd sampling 3rd sampling figure 11.20 burst mode, level input
rev. 5.00, 09/03, page 371 of 760 ckio drak dreq dack bus cycle cpu dmac(r) dmac(w) dmac(r) dmac(w) dmac(r) 1st sampling figure 11.21 burst mode, edge input
rev. 5.00, 09/03, page 372 of 760 11.3.6 source address reload function channel 2 includes a reload function, in which the value is returned to the value set in the source address register (sar2) every four transfers by setting the ro bit in chcr2 to 1. 16-byte transfer cannot be used. figure 11.22 shows this operation. figure 11.23 shows a timing chart for the source address reload function under the following conditions: burst mode, auto-request, 16-bit transfer data size, sar2 incremented, dar2 fixed, reload function on, and use of channel 2 only. sar2 (initial value) dmac transfer request dmac control reload control 4 time count chcr2 dmatcr2 sar2 ro bit = 1 count signal reload signal reload signal address bus figure 11.22 source address reload function diagram
rev. 5.00, 09/03, page 373 of 760 ck internal address bus internal data bus sar2 dar2 dar2 dar2 dar2 sar2+2 sar2+4 sar2+6 sar2 sar2 data sar2+2 data sar2+4 data sar2+6 data first transfer on channel 2 second transfer third transfer fourth transfer fifth transfer sar2 output dar2 output sar2+2 output dar2 output sar2+4 output dar2 output sar2+6 output dar2 output sar2 reload sar2 output dar2 output figure 11.23 timing chart of source address reload function the reload function can be executed with a transfer data size of 8, 16, or 32 bits. dmatcr2, which specifies the transfer count, decrements 1 each time a transfer ends regardless of whether the reload function is on or off. consequently, a multiple of four must be specified in dmatcr2 when the reload function is on. operation is not guaranteed if other values are specified. the counter that counts the execution of four transfers for the address reload function is reset by clearing the dme bit in dmaor or the de bit in chcr2, by setting the transfer end flag (te bit in chcr2), by dmac address error, and by nmi input, as well as by a reset, but the sar2, dar2, and dmatcr2 registers are not reset. therefore, if these sources are generated, there will be a mix of an initialized counter and uninitialized registers in the dmac, and a malfunction will be caused by restarting the dmac in that state. consequently, if one of these sources other than setting of the te bit occurs during use of the address reload function, set sar2, dar2, and dmatcr2 again.
rev. 5.00, 09/03, page 374 of 760 11.3.7 dma transfer ending conditions the dma transfer ending conditions are different for ending on an individual channel and ending on all channels together. at the end of transfer, the following conditions are applied except in the case where the value set in the dma transfer count register (dmatcr) reaches 0. (a) cycle-steal mode (external request, internal request, and auto-request) when the transfer ending conditions are satisfied, dmac transfer request acceptance is suspended. the dmac stops operating after completing the number of transfers that it has accepted until the ending conditions are satisfied. in cycle-steal mode, the operation is the same regardless of whether the transfer request is detected by level or edge. (b) burst mode, edge detection (external request, internal request, and auto-request) the timing from the point where the ending conditions are satisfied to the point where the dmac stops operating is the same as in cycle-steal mode. with edge detection in burst mode, though only one transfer request is generated to start the dmac, stop request sampling is performed at the same timing as transfer request sampling in cycle-steal mode. as a result, the period when a stop request is not sampled is regarded as the period when a transfer request is generated, and after performing the dma transfer for this period, the dmac stops operating. (c) burst mode, level detection (external request) same as in (a). (d) bus timing when transfer is suspended transfer is suspended when one transfer ends. even if transfer ending conditions are satisfied during a read in direct address transfer in dual address mode, the subsequent write process is executed, and after the transfer in (a) to (c) above has been executed, dmac operation is suspended. individual channel ending conditions: there are two ending conditions. a transfer ends when the value of the channel?s dma transfer count register (dmatcr) is 0, or when the de bit in the channel?s chcr register is cleared to 0. ? when dmatcr is 0: when the dmatcr value becomes 0 and the corresponding channel's dma transfer ends, the transfer end flag bit (te) is set in chcr. if the ie (interrupt enable) bit has been set, a dmac interrupt (dei) request is sent to the cpu. this transfer ending does not apply to (a) to (d) described above. ? when de in chcr is 0: software can halt a dma transfer by clearing the de bit in the channel?s chcr register. the te bit is not set when this happens. this transfer ending applies to (a) to (d) described above.
rev. 5.00, 09/03, page 375 of 760 conditions for ending on all channels simultaneously: transfers on all channels end (1) when the ae or nmif (nmi flag) bit is set to 1 in dmaor, or (2) when the dme bit in dmaor is cleared to 0. ? transfer ending when the nmif bit is set to 1 in dmaor: when an nmi interrupt occurs, the ae or nmif bit is set to 1 in dmaor and all channels stop their transfers according to the conditions in (a) to (d) described above, and pass the bus to an other bus master. consequently, even if the ae or nmi bit is set to 1 during transfer, sar, dar, dmatcr are updated. the te bit is not set. to resume transfer after nmi interrupt exception handling, clear the nmif bit to 0. at this time, if there are channels that should not be restarted, clear the corresponding de bit in chcr. ? transfer ending when dme is cleared to 0 in dmaor: clearing the dme bit to 0 in dmaor forcibly aborts transfer on all channels. the te bit is not set. all channels abort their transfer according to the conditions in (a) to (d) in section 11.3.7, dma transfer ending conditions, as in nmi interrupt generation. in this case, the values in sar, dar, and dmatcr are also updated.
rev. 5.00, 09/03, page 376 of 760 11.4 compare match timer (cmt) 11.4.1 overview the dmac has an on-chip compare match timer (cmt) to generate dma transfer requests. the cmt has a 16-bit counter. features the cmt has the following features: ? four types of counter input clock can be selected ? one of four internal clocks (p /4, p /8, p /16, p /64) can be selected. ? generates a dma transfer request when compare match occurs. block diagram figure 11.24 shows a block diagram of the cmt. internal bus bus interface control circuit clock selection cmstr cmcsr0 cmcor0 comparator cmcnt0 module bus cmt p /4 p /8 p /16 p /64 cmstr: cmcsr0: cmcor0: cmcnt0: compare match timer start register compare match timer control/status register 0 compare match timer constant register 0 compare match timer counter 0 figure 11.24 block diagram of cmt
rev. 5.00, 09/03, page 377 of 760 register configuration table 11.7 summarizes the cmt register configuration. table 11.7 register configuration name abbreviation r/w initial value address access size (bits) compare match timer start register cmstr r/(w) h'0000 h'04000070 (h'a4000070) * 2 8, 16, 32 compare match timer control/status register 0 cmcsr0 r/(w) * 1 h'0000 h'04000072 (h'a4000072) * 2 8, 16, 32 compare match counter 0 cmcnt0 r/w h'0000 h'04000074 (h'a4000074) * 2 8, 16, 32 compare match constant register 0 cmcor0 r/w h'ffff h'04000076 (h'a4000076) * 2 8, 16, 32 notes: 1. the only value that can be written to the cmf bit in cmcsr0 is 0 to clear the flag. 2. when address translation by the mmu does not apply, the address in parentheses should be used. 11.4.2 register descriptions compare match timer start register (cmstr) the compare match timer start register (cmstr) is a 16-bit register that selects whether compare match counter 0 (cmcnt0) is operated or halted. it is initialized to h'0000 by a reset, but retains its previous value in standby mode. bit: 15 14 13 12 11 10 9 8 ???????? initial value:00000000 r/w:rrrrrrrr bit:76543210 ???????str0 initial value:00000000 r/w:rrrrrrr/wr/w bits 15 to 2?reserved: these bits are always read as 0. the write value should alway be 0. bit 1?reserved: this bit can be read or written. the write value should always be 0.
rev. 5.00, 09/03, page 378 of 760 bit 0?count start 0 (str0): selects whether to operate or halt cmcnt0. bit 0: str0 description 0 cmcnt0 count operation halted (initial value) 1 cmcnt0 count operation compare match timer control/status register 0 (cmcsr0) the compare match timer control/status register 0 (cmcsr0) is a 16-bit register that indicates the occurrence of compare matches, sets the enable/disable status of interrupts, and establishes the clock used for incrementation. it is initialized to h'0000 by a reset, but retains its previous value in standby mode. bit: 15 14 13 12 11 10 9 8 ???????? initial value:00000000 r/w:rrrrrrrr bit:76543210 cmf?????cks1cks0 initial value:00000000 r/w: r/(w) * r/wrrrrr/wr/w note: * the only value that can be written is 0 to clear the flag. bits 15 to 8 and 5 to 2?reserved: these bits are always read as 0. the write value should always be 0. bit 7?compare match flag (cmf): indicates whether or not the compare match timer counter 0 (cmcnt0) and compare match timer constant 0 (cmcor0) values match. bit 7: cmf description 0 cmcnt0 and cmcor0 values do not match (initial value) clearing condition: write 0 to cmf after reading cmf = 1 1 cmcnt0 and cmcor0 values match
rev. 5.00, 09/03, page 379 of 760 bit 6?reserved: this bit can be read or written. the wite value should always be 0. bits 1 and 0?clock select 1 and 0 (cks1, cks0): select the clock input to cmcnt from among the four internal clocks obtained by dividing the system clock (p ). when the str bit in cmstr is set to 1, cmcnt0 begins incrementing on the clock selected by cks1 and cks0. bit 1: cks1 bit 0: cks0 description 00p /4 (initial value) 1p /8 1 0 p /16 1p /64 compare match counter 0 (cmcnt0) compare match counter 0 (cmcnt0) is a 16-bit register used as an up-counter. when an internal clock is selected with the cks1 and cks0 bits in the cmcsr0 register and the str bit in cmstr is set to 1, cmcnt0 begins incrementing on that clock. when the cmcnt0 value matches that of compare match constant register 0 (cmcor0), cmcnt0 is cleared to h'0000 and the cmf flag in cmcsr0 is set to 1. cmcnt0 is initialized to h'0000 by a reset, but retains its previous value in standby mode. bit: 15 14 13 12 11 10 9 8 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
rev. 5.00, 09/03, page 380 of 760 compare match constant register 0 (cmcor0) compare match constant register 0 (cmcor0) is a 16-bit register that sets the cmcnt0 compare match period. cmcor0 is initialized to h'ffff by a reset, but retains its previous value in standby mode. bit: 15 14 13 12 11 10 9 8 initial value:11111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 initial value:11111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 11.4.3 operation period count operation when an internal clock is selected with the cks1 and cks0 bits in the cmcsr0 register and the str bit in cmstr is set to 1, cmcnt0 begins incrementing on the selected clock. when the cmcnt counter value matches that of cmcor0, the cmcnt0 counter is cleared to h'0000 and the cmf flag in the cmcsr0 register is set to 1. the cmcnt0 counter begins counting up again from h'0000. figure 11.25 shows the compare match counter operation. counter cleared by cmcor0 compare match cmcnt0 value cmcor0 h0000 time figure 11.25 counter operation
rev. 5.00, 09/03, page 381 of 760 cmcnt0 count timing one of four clocks (p /4, p /8, p /16, p /64) obtained by dividing the p clock can be selected with the cks1 and cks0 bits in cmcsr0. figure 11.26 shows the timing. n+1 ck internal clock cmcnt0 input clock cmcnt0 n-1 n figure 11.26 count timing 11.4.4 compare match compare match flag setting timing the cmf bit in the cmcsr0 register is set to 1 by the compare match signal generated when the cmcor0 register and the cmcnt0 counter match. the compare match signal is generated in the final state of the match (timing at which the cmcnt0 counter matching count value is updated). consequently, after the cmcor0 register and the cmcnt0 counter match, a compare match signal will not be generated until a cmcnt0 counter input clock occurs. figure 11.27 shows the cmf bit setting timing.
rev. 5.00, 09/03, page 382 of 760 ck cmcor0 cmcnt0 input clock compare match signal cmf cmi cmcnt0 n n 0 figure 11.27 cmf setting timing compare match flag clearing timing the cmf bit in the cmcsr0 register is cleared by writing 0 to it after reading 1. figure 11.28 shows the timing when the cmf bit is cleared by the cpu. ck cmf cmcsr0 write cycle t 1 t 2 figure 11.28 timing of cmf clearing by the cpu
rev. 5.00, 09/03, page 383 of 760 11.5 examples of use 11.5.1 example of dma transfer between on-chip irda and external memory in this example, receive data of the on-chip irda is transferred to external memory using dmac channel 3. table 11.8 shows the transfer conditions and register settings. in addition, it is recommended that the trigger for the number of receive fifo data bytes in irda be set to 1 (rtrg1 = rtrg0 = 0 in scfcr). table 11.8 transfer conditions and register settings for transfer between on-chip sci and external memory transfer conditions register setting transfer source: rdr1 of on-chip irda sar3 h'0400014a transfer destination: external memory dar3 h'00400000 number of transfers: 64 dmatcr3 h'00000040 transfer source address: fixed chcr3 h'00004b05 transfer destination address: incremented transfer request source: irda (rxi1) bus mode: cycle-steal transfer unit: byte interrupt request generated at end of transfer channel priority order: 0 > 2 > 3 > 1 dmaor h'0101
rev. 5.00, 09/03, page 384 of 760 11.5.2 example of dma transfer between a/d converter and external memory in this example, dma transfer is performed between the on-chip a/d converter (transfer source) and the external memory (transfer destination) with the address reload function on. table 11.9 shows the transfer conditions and register settings. table 11.9 transfer conditions and register settings for transfer between on-chip a/d converter and external memory transfer conditions register setting transfer source: on-chip a/d converter sar2 h'04000080 transfer destination: internal memory dar2 h'00400000 number of transfers: 128 (reloading 32 times) dmatcr2 h'00000080 transfer source address: incremented chcr2 h'00089e35 transfer destination address: decremented transfer request source: a/d converter bus mode: burst transfer unit: longword interrupt request generated at end of transfer channel priority order: 0 > 2 > 3 > 1 dmaor h'0101 when the address reload function is on, the value set in sar returns to the initially set value every four transfers. in this example, when a transfer request is generated from the a/d converter, byte data is read from the register at address h'04000080 in the a/d converter, and is written to external memory address h'00400000. since longword data has been transferred, the values in sar and dar are h'04000084 and h'003ffffc, respectively. the bus is kept and data transfers are performed successively because this transfer is in burst mode. after four transfers end, fifth and sixth transfers are performed if the address reload function is off, and the value in sar is incremented from h'0400008c to h'04000090, h'04000094 if the address reload function is on, dma transfer stops after the fourth transfer ends, and the bus request signal to the cpu is cleared. at this time, the value stored in sar is not incremented from h'0400008c to h'04000090, but returns to the initially set value, h'04000080. the value in dar continues to be decremented regardless of whether the address reload function is on or off.
rev. 5.00, 09/03, page 385 of 760 as a result, the values in the dmac are as shown in table 11.10 when the fourth transfer ends, depending on whether the address reload function is on or off. table 11.10 values in dmac after end of fourth transfer items address reload on address reload off sar h'04000080 h'04000090 dar h'003ffffc h'003ffffc dmatcr h'0000007c h'0000007c bus right released held dmac operation stops keeps operating interrupt not generated not generated transfer request source flag clearing executed not executed notes: 1. an interrupt is generated regardless of whether the address reload function is on or off, if transfers are executed until the value in dmatcr reaches 0 and the ie bit in chcr has been set to 1. 2. the transfer request source flag is cleared regardless of whether the address reload function is on or off, if transfers are executed until the value in dmatcr reaches 0. 3. specify burst mode when using the address reload function. this function may not be correctly executed in cycle-steal mode. 4. set a multiple of four in dmatcr when using the address reload function. this function may not be correctly executed if other values are specified. 11.5.3 example of dma transfer between external memory and scif transmitter (indirect address on) in this example, dma transfer is performed between the external memory specified by indirect address (transfer source) and the scif transmitter (transfer destination) using dmac channel 3. table 11.11 shows the transfer conditions and register settings. in addition, the trigger for the number of transmit fifo data bytes is set to 1 (ttrg1 = ttrg0 = 1 in scfcr).
rev. 5.00, 09/03, page 386 of 760 table 11.11 transfer conditions and register settings for transfer between external memory and scif transmitter transfer conditions register setting transfer source: external memory sar3 h'00400000 value stored in address h'00400000 ? h'00450000 value stored in address h'04500000 ? h'55 transfer destination: on-chip scif tdr2 dar3 h'04000156 number of transfers: 10 dmatcr3 h'0000000a transfer source address: incremented chcr3 h'00011c01 transfer destination address: fixed transfer request source: scif (txi2) bus mode: cycle-steal transfer unit: byte no interrupt request generated at end of transfer channel priority order: 0 > 1 > 2 > 3 dmaor h'0001 if the indirect address is on, data stored in the address set in sar is not used as transfer source data. in the indirect address, after the value stored in the address set in sar is read, that read value is used as an address again, and the value stored in that address is read and stored in the address set in dar. in the example shown in table 11.11, when an scif transfer request is generated, the dmac reads the value in address h'00400000 set in sar3. since the value h'00450000 is stored in that address, the dmac reads the value h'00450000. next, the dmac uses that read value as an address again, and reads the value h'55 stored in that address. then, the dmac writes the value h'55 to address h'04000156 set in dar3; this completes one indirect address transfer. in the indirect address, when data is read first from the address set in sar3, the data transfer size is always longword regardless of the settings of the ts0 and ts1 bits that specify the transfer data size. however, whether the transfer source address is fixed, incremented, or decremented is specified by the sm0 and sm1 bits. therefore, in this example, though the transfer data size is specified as byte, the value in sar3 is h'00400004 when one transfer ends. write operations are the same as in normal dual address transfer.
rev. 5.00, 09/03, page 387 of 760 11.6 usage notes 1. the dma channel control registers (chcr0?chcr3) can be accessed with any data size. the dma operation register (dmaor) must be accessed by byte (8 bits) or word (16 bits); other registers must be accessed by word (16 bits) or longword (32 bits). 2. before rewriting the rs0?rs3 bits in chcr0?chcr3, first clear the de bit to 0 (when rewriting chcr with a byte address, be sure to set the de bit to 0 in advance). 3. even if an nmi interrupt is input when the dmac is not operating, the nmif bit in dmaor will be set. 4. before entering standby mode, the dme bit in dmaor must be cleared to 0 and the transfers accepted by the dmac completed. 5. the on-chip peripherals which the dmac can access are the irda, scif, a/d converter, d/a converter, and i/o ports. do not access other peripherals with the dmac. 6. when starting up the dmac, set chcr or dmaor last. normal operation is not guaranteed if settings for another register are made last. 7. even if the maximum number of transfers are performed in the same channel after the dmatcr count reaches 0 and dma transfer ends normally, write 0 to dmatcr. otherwise, normal dma transfer may not be performed. 8. when using the address reload function, specify burst mode as the transfer mode. in cycle-steal mode, normal dma transfer may not be performed. 9. when using the address reload function, set a multiple of four in dmatcr. normal operation is not guaranteed if other values are specified. 10. when detecting an external request at the falling edge, keep the external request pin high when setting the dmac. 11. do not access the space from h'4000062 to h'400006f, which is not used in the dmac. accessing this space may cause malfunctions. 12. the wait signal is ignored in the case of a write to external address space in dual address mode with 16-byte transfer, or transfer from an external device with dack to external address space in signal address mode with 16-byte transfer. 13. dmac transfers should not be performed in the sleep mode under conditions other than when the clock ratio of i (on-chip clock) to b (bus clock) is 1:1. 14. when the following three conditions are all met, the frequency control register (frqcr) should not be changed while a dmac transfer is in progress. ? bits ifc2 to ifc0 are changed. ? stc2 to stc0 in frqcr are not changed. ? the clock ratio of i (on-chip clock) to b (bus clock) after the change is other than 1:1.
rev. 5.00, 09/03, page 388 of 760
rev. 5.00, 09/03, page 389 of 760 section 12 timer (tmu) 12.1 overview the sh7709s has a three-channel (channels 0 to 2) 32-bit timer unit (tmu). 12.1.1 features the tmu has the following features: ? each channel is provided with an auto-reload 32-bit down counter. ? channel 2 is provided with an input capture function. ? all channels are provided with 32-bit constant registers and 32-bit down counters that can be read or written to at any time. ? all channels generate interrupt requests when the 32-bit down counter underflows (h'00000000 h'ffffffff). ? allows selection between 6 counter input clocks: external clock (tclk), on-chip rtc output clock (16 khz), p /4, p /16, p /64, p /256. (p is the internal clock for peripheral modules.) see section 9, on-chip oscillation circuits, for more information on the clock pulse generator. ? all channels can operate when the sh7709s is in standby mode: when the rtc output clock is being used as the counter input clock, the sh7709s is still able to count in standby mode. ? synchronized read: tcnt is a sequentially changing 32-bit register. since the peripheral module used has an internal bus width of 16 bits, a time lag can occur between the time when the upper 16 bits and lower 16 bits are read. to correct the discrepancy in the counter read value caused by this time lag, a synchronization circuit is built into the tcnt so that the entire 32-bit data in the tcnt can be read at once. ? the maximum operating frequency of the 32-bit counter is 2 mhz on all channels: operate the sh7709s so that the clock input to the timer counters of each channel (obtained by dividing the external clock and internal clock with the prescaler) does not exceed the maximum operating frequency.
rev. 5.00, 09/03, page 390 of 760 12.1.2 block diagram figure 12.1 shows a block diagram of the tmu. tocr prescaler tstr tcr0 tcnt0 module bus internal bus tcor0 tcr1 tcnt1 tcor1 counter controller tclk p rtcclk tuni0 bus interface ch. 0 interrupt controller interrupt controller interrupt controller counter controller counter controller tuni1 tuni2 ticpi2 tcr2 tcpr2 tcnt2 tcor2 tmu ch. 1 ch. 2 clock controller tocr: tstr: tcr: legend timer output control register timer start register tcnt: tcor: tcpr2: 32-bit timer counter 32-bit timer constant register 32-bit input capture register timer control register figure 12.1 block diagram of tmu
rev. 5.00, 09/03, page 391 of 760 12.1.3 pin configuration table 12.1 shows the pin configuration of the tmu. table 12.1 tmu pin channel pin i/o description clock input/clock output tclk i/o external clock input pin/input capture control input pin/realtime clock (rtc) output pin 12.1.4 register configuration table 12.2 shows the tmu register configuration. table 12.2 tmu registers channel register abbre- viation r/w initial value * address access size common timer output control register tocr r/w h'00 h'fffffe90 8 timer start register tstr r/w h'00 h'fffffe92 8 0 timer constant register 0 tcor0 r/w h'ffffffff h'fffffe94 32 timer counter 0 tcnt0 r/w h'ffffffff h'fffffe98 32 timer control register 0 tcr0 r/w h'0000 h'fffffe9c 16 1 timer constant register 1 tcor1 r/w h'ffffffff h'fffffea0 32 timer counter 1 tcnt1 r/w h'ffffffff h'fffffea4 32 timer control register 1 tcr1 r/w h'0000 h'fffffea8 16 2 timer constant register 2 tcor2 r/w h'ffffffff h'fffffeac 32 timer counter 2 tcnt2 r/w h'ffffffff h'fffffeb0 32 timer control register 2 tcr2 r/w h'0000 h'fffffeb4 16 input capture register 2 tcpr2 r undefined h'fffffeb8 32 note: * initialized by power-on resets or manual resets.
rev. 5.00, 09/03, page 392 of 760 12.2 tmu registers 12.2.1 timer output control register (tocr) tocr is an 8-bit readable/writable register that selects whether to use the external tclk pin as an external clock or an input capture control usage input pin, or an output pin for the on-chip rtc output clock. tocr is initialized to h'00 by a power-on reset or manual reset, but is not initialized in standby mode. bit:76543210 ???????tcoe initial value:00000000 r/w:rrrrrrrr/w bits 7 to 1?reserved: these bits are always read as 0. the write value should always be 0. bit 0?timer clock pin control (tcoe): selects use of the timer clock pin (tclk) as an external clock output pin or input pin for input capture control for the on-chip timer, or as an output pin for the on-chip rtc output clock. since the tclk pin is multiplexed as the pth7 pin, when the pin is used as tclk, bits ph7md1 and ph7md0 in the phcr register should be set to 00 (the "other function" setting). bit 0: tcoe description 0 timer clock pin (tclk) used as external clock input or input capture control input pin for the on-chip timer (initial value) 1 timer clock pin (tclk) used as output pin for on-chip rtc output clock 12.2.2 timer start register (tstr) tstr is an 8-bit readable/writable register that selects whether to run or halt the timer counters (tcnt) for channels 0?2. tstr is initialized to h'00 by a power-on reset or manual reset, but is not initialized in standby mode when the input clock selected for the channel is the on-chip rtc clock (rtcclk). only when an external clock (tclk) or the peripheral clock (p ) is used as the input clock, it is initialized in standby mode when the multiplication ratio of pll circuit 1 is changed or when the mstp2 bit in stbcr is set to 1. bit:76543210 ?????str2str1str0 initial value:00000000 r/w:rrrrrr/wr/wr/w
rev. 5.00, 09/03, page 393 of 760 bits 7 to 3?reserved: these bits are always read as 0. the write value should always be 0. bit 2?counter start 2 (str2): selects whether to run or halt timer counter 2 (tcnt2). bit 2: str2 description 0 tcnt2 count halted (initial value) 1 tcnt2 counts bit 1?counter start 1 (str1): selects whether to run or halt timer counter 1 (tcnt1). bit 1: str1 description 0 tcnt1 count halted (initial value) 1 tcnt1 counts bit 0?counter start 0 (str0): selects whether to run or halt timer counter 0 (tcnt0). bit 0: str0 description 0 tcnt0 count halted (initial value) 1 tcnt0 counts 12.2.3 timer control registers (tcr) the timer control registers (tcr) control the timer counters (tcnt) and interrupts. the tmu has three tcr registers, one for each channel. the tcr registers are 16-bit readable/writable registers that control the issuance of interrupts when the flag indicating timer counter (tcnt) underflow has been set to 1, and also carry out counter clock selection. when the external clock has been selected, they also select its edge. additionally, tcr2 controls the channel 2 input capture function and the issuance of interrupts during input capture. the tcr registers are initialized to h'0000 by a power-on reset and manual reset, but are not initialized in standby mode and retain their contents.
rev. 5.00, 09/03, page 394 of 760 channels 0 and 1 tcr bit configuration: bit: 15 14 13 12 11 10 9 8 ???????unf initial value:00000000 r/w:rrrrrrrr/w bit:76543210 ? ? unie ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 initial value:00000000 r/w: r r r/w r/w r/w r/w r/w r/w channel 2 tcr bit configuration: bit: 15 14 13 12 11 10 9 8 ??????icpfunf initial value:00000000 r/w:rrrrrrr/wr/w bit:76543210 icpe1 icpe0 unie ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 10, 9 (except tcr2), 7, and 6 (except tcr2)?reserved: these bits are always read as 0. the write value should always be 0. bit 9?input capture interrupt flag (icpf): a function of channel 2 only: the flag is set when input capture is requested via the tclk pin. bit 9: icpf description 0 no input capture request has been issued clearing condition: when 0 is written to icpf (initial value) 1 input capture has been requested via the tclk pin setting condition: when input capture is requested via the tclk pin * note: * contents do not change when 1 is written to icpf.
rev. 5.00, 09/03, page 395 of 760 bit 8?underflow flag (unf): status flag that indicates occurrence of a tcnt underflow. bit 8: unf description 0 tcnt has not underflowed clearing condition: when 0 is written to unf (initial value) 1 tcnt has underflowed setting condition: when tcnt underflows * note: * contents do not change when 1 is written to unf. bits 7 and 6?input capture control (icpe1, icpe0): a function of channel 2 only: determines whether the input capture function can be used, and when used, whether or not to enable interrupts. when using this input capture function it is necessary to set the tclk pin to input mode with the tcoe bit in the tocr register. additionally, use the ckeg bit to designate use of either the rising or falling edge of the tclk pin to set the value in tcnt2 in the input capture register (tcpr2). bit 7: icpe1 bit 6: icpe0 description 0 0 input capture function is not used (initial value) 1 reserved (setting prohibited) 1 0 input capture function is used. interrupt due to icpf (ticpi2) is not enabled 1 input capture function is used. interrupt due to icpf (ticpi2) is enabled bit 5?underflow interrupt control (unie): controls enabling of interrupt generation when the status flag (unf) indicating tcnt underflow has been set to 1. bit 5: unie description 0 interrupt due to unf (tuni) is not enabled (initial value) 1 interrupt due to unf (tuni) is enabled
rev. 5.00, 09/03, page 396 of 760 bits 4 and 3?clock edge 1 and 0 (ckeg1, ckeg0): select the external clock edge when the external clock is selected, or when the input capture function is used. bit 4: ckeg1 bit 3: ckeg0 description 0 0 count/capture register set on rising edge (initial value) 1 count/capture register set on falling edge 1 x count/capture register set on both rising and falling edge note: x means 0, 1, or ?don?t care?. bits 2 to 0?timer prescaler 2 to 0 (tpsc2 to tpsc0): select the tcnt count clock. bit 2: tpsc2 bit 1: tpsc1 bit 0: tpsc0 description 0 0 0 internal clock: count on p /4 (initial value) 1 internal clock: count on p / 16 1 0 internal clock: count on p /64 1 internal clock: count on p /256 1 0 0 internal clock: count on clock output of on-chip rtc (rtc clk) 1 count on tclk pin input 1 0 reserved (setting prohibited) 1 reserved (setting prohibited)
rev. 5.00, 09/03, page 397 of 760 12.2.4 timer constant registers (tcor) the tmu has three tcor registers, one for each channel. tcor specifies the value for setting in tcnt when a tcnt count-down results in an under flow. tcor is a 32-bit readable/writable register. tcor is initialized to h'ffffffff by a power-on reset or manual reset, but is not initialized, and retains its contents, in standby mode. bit: 31 30 29 28 27 26 25 24 initial value:11111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 initial value:11111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 initial value:11111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 initial value:11111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 12.2.5 timer counters (tcnt) the timer counters are 32-bit readable/writable registers. the tmu has three timer counters, one for each channel. tcnt counts down upon input of a clock. the clock input is selected using the tpsc2 ? tpsc0 bits in the timer control register (tcr). when a tcnt count-down results in an underflow (h'00000000 h'ffffffff), the underflow flag (unf) in the timer control register (tcr) of the relevant channel is set. the tcor value is simultaneously set in tcnt itself and the count-down continues from that value.
rev. 5.00, 09/03, page 398 of 760 because the internal bus for the sh7709s on-chip peripheral modules is 16 bits wide, a time lag can occur between the time when the upper 16 bits and lower 16 bits are read. since tcnt counts sequentially, this time lag can create discrepancies between the data in the upper and lower halves. to correct the discrepancy, a buffer register is connected to tcnt so that the upper and lower halves are not read separately. the entire 32-bit data in tcnt can thus be read at once. tcnt is initialized to h'ffffffff by a power-on reset or manual reset, but is not initialized, and retains its contents, in standby mode. bit: 31 30 29 28 27 26 25 24 initial value:11111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 initial value:11111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 initial value:11111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 initial value:11111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
rev. 5.00, 09/03, page 399 of 760 12.2.6 input capture register (tcpr2) input capture register 2 (tcpr2) is a read-only 32-bit register provided only in timer 2. control of tcpr2 setting conditions due to the tclk pin is affected by the input capture function bits (icpe1/icpe0 and ckeg1/ckeg0) in tcr2. when a tcpr2 setting indication due to the tclk pin occurs, the value of tcnt2 is copied into tcpr2. tcnt2 is not initialized by a power-on reset or manual reset, but is not initialized, and retains its contents, or in standby mode. bit: 31 30 29 28 27 26 25 24 initial value:???????? r/w:rrrrrrrr bit: 23 22 21 20 19 18 17 16 initial value:???????? r/w:rrrrrrrr bit: 15 14 13 12 11 10 9 8 initial value:???????? r/w:rrrrrrrr bit:76543210 initial value:???????? r/w:rrrrrrrr
rev. 5.00, 09/03, page 400 of 760 12.3 tmu operation each of three channels has a 32-bit timer counter (tcnt) and a 32-bit timer constant register (tcor). tcnt counts down. the auto-reload function enables cycle counting and counting by external events. channel 2 has an input capture function. 12.3.1 general operation when the str0 ? str2 bits in the timer start register (tstr) are set to 1, the corresponding timer counter (tcnt) starts counting. when a tcnt underflows, the unf flag of the corresponding timer control register (tcr) is set. at this time, if the unie bit in tcr is 1, an interrupt request is sent to the cpu. also at this time, the value is copied from tcor to tcnt and the down-count operation is continued. the count operation is set as follows (figure 12.2): 1. select the counter clock with the tpsc2?tpsc0 bits in the timer control register (tcr). if the external clock is selected, set the tclk pin to input mode with the toce bit in tocr, and select its edge with the ckeg1 and ckeg0 bits in tcr. 2. use the unie bit in tcr to set whether to generate an interrupt when tcnt underflows. 3. when using the input capture function, set the icpe bits in tcr, including the choice of whether or not to use the interrupt function (channel 2 only). 4. set a value in the timer constant register (tcor) (the cycle is the set value plus 1). 5. set the initial value in the timer counter (tcnt). 6. set the str bit in the timer start register (tstr) to 1 to start operation.
rev. 5.00, 09/03, page 401 of 760 select operation select counter clock set underflow interrupt generation set timer constant register initialize timer counter start counting (1) (2) (4) (5) (6) set interrupt generation when using input capture function (3) note: when an interrupt has been generated, clear the flag in the interrupt handler that caused it. if interrupts are enabled without clearing the flag, another interrupt will be generated. figure 12.2 setting the count operation
rev. 5.00, 09/03, page 402 of 760 auto-reload count operation: figure 12.3 shows the tcnt auto-reload operation. tcnt value tcor h00000000 str0 ? str2 unf tcor value set to tcnt during underflow time figure 12.3 auto-reload count operation tcnt count timing: ? internal clock operation: set the tpsc2?tpsc0 bits in tcr to select whether peripheral module clock p or one of the four internal clocks created by dividing it is used (p /4, p /16, p /64, p /256). figure 12.4 shows the timing. p internal clock tcnt input clock tcnt n + 1 n n ? 1 figure 12.4 count timing when operating on internal clock
rev. 5.00, 09/03, page 403 of 760 ? external clock operation: set the tpsc2?tpsc0 bits in tcr to select the external clock (tclk) as the timer clock. use the ckeg1 and ckeg0 bits in tcr to select the detection edge. rising, falling, or both edges may be selected. the pulse width of the external clock must be at least 1.5 peripheral module clock cycles for single edges or 2.5 peripheral module clock cycles for both edges. a shorter pulse width will result in accurate operation. figure 12.5 shows the timing for both-edge detection. p external clock input pin (tclk) tcnt input clock tcnt n + 1 n n ? 1 figure 12.5 count timing when operating on external clock (both edges detected) ? on-chip rtc clock operation: set the tpsc2?tpsc0 bits in tcr to select the on-chip rtc clock as the timer clock. figure 12.6 shows the timing. rtc output clock tcnt tcnt input clock n + 1 n n ? 1 figure 12.6 count timing when operating on on-chip rtc clock 12.3.2 input capture function channel 2 has an input capture function (figure 12.7). when using the input capture function, set the tclk pin to input mode with the tcoe bit in the timer output control register (tocr) and set the timer operation clock to internal clock or on-chip rtc clock with the tpcs2?tpcs0 bits in the timer control register (tcr2). also, designate use of the input capture function and whether to generate interrupts on input capture with the ipce1?ipce0 bits in tcr2, and designate the use of either the rising or falling edge of the tclk pin to set the timer counter (tcnt2) value into the input capture register (tcpr2) with the ckeg1?ckeg0 bits in tcr2. the input capture function cannot be used in standby mode.
rev. 5.00, 09/03, page 404 of 760 tcnt value tcor h00000000 tclk tcpr2 set tcnt value icpi tcor value set to tcnt during underflow time figure 12.7 operation timing when using input capture function (using tclk rising edge) 12.4 interrupts there are two sources of tmu interrupts: underflow interrupts (tuni) and interrupts when using the input capture function (ticpi2). 12.4.1 status flag setting timing unf is set to 1 when the tcnt underflows. figure 12.8 shows the timing. p tcnt underflow signal unf tuni tcor value h00000000 figure 12.8 unf setting timing
rev. 5.00, 09/03, page 405 of 760 12.4.2 status flag clearing timing the status flag can be cleared by writing 0 from the cpu. figure 12.9 shows the timing. p peripheral address bus unf, icpf tcr address t 1 t 2 tcr write cycle t 3 figure 12.9 status flag clearing timing 12.4.3 interrupt sources and priorities the tmu produces underflow interrupts for each channel. when the interrupt request flag and interrupt enable bit are both set to 1, an interrupt is requested. codes are set in the interrupt event registers (intevt, intevt2) for these interrupts and interrupt handling occurs according to the codes. the relative priorities of channels can be changed using the interrupt controller (see section 4, exception handling, and section 6, interrupt controller (intc)). table 12.3 lists tmu interrupt sources. table 12.3 tmu interrupt sources channel interrupt source description priority 0 tuni0 underflow interrupt 0 high 1 tuni1 underflow interrupt 1 2 tuni2 underflow interrupt 2 2 ticpi2 input capture interrupt 2 low
rev. 5.00, 09/03, page 406 of 760 12.5 usage notes 12.5.1 writing to registers synchronization processing is not performed for timer counting during register writes. when writing to registers, always clear the appropriate start bits for the channel (str2?str0) in the timer start register (tstr) to halt timer counting. 12.5.2 reading registers synchronization processing is performed for timer counting during register reads. when timer counting and register read processing are performed simultaneously, the register value before tcnt counting down (with synchronization processing) is read.
rev. 5.00, 09/03, page 407 of 760 section 13 realtime clock (rtc) 13.1 overview the sh7709s has a realtime clock (rtc) with its own 32.768-khz crystal oscillator. 13.1.1 features ? clock and calendar functions (bcd display): seconds, minutes, hours, date, day of the week, month, and year ? 1-hz to 64-hz timer (binary display) ? start/stop function ? 30-second adjust function ? alarm interrupt: frame comparison of seconds, minutes, hours, date, day of the week, and month can be used as conditions for the alarm interrupt ? cyclic interrupts: the interrupt cycle may be 1/256 second, 1/64 second, 1/16 second, 1/4 second, 1/2 second, 1 second, or 2 seconds ? carry interrupt: a carry interrupt indicates when a carry occurs during a counter read ? automatic leap year correction
rev. 5.00, 09/03, page 408 of 760 13.1.2 block diagram figure 13.1 shows a block diagram of the rtc. module bus rtc internal bus interrupt control circuit prescaler ( 2) rtcclk bus interface carry detection circuit ati pri cui legend r64cnt: 64 hz counter rseccnt: second counter rmincnt: minute counter rhrcnt: hour counter rwkcnt: day-of-week counter rdaycnt: day counter rmoncnt: month counter ryrcnt: year counter rsecar: second alarm register rminar: minute alarm register rhrar: hour alarm register rwkar: day-of-week alarm register rdayar: day alarm register rmonar: month alarm register rcr1: rtc control register 1 rcr2: rtc control register 2 r64cnt reset rseccnt rmincnt rhrcnt rwkcnt 16.384 khz rdaycnt rmoncnt ryrcnt comparator rsecar rminar rhrar rwkar rdayar rcr1 rcr2 30- second adj extal2 32.768 khz 128 hz xtal2 externally connected circuit oscillator circuit prescaler ( 128) rmonar figure 13.1 block diagram of rtc
rev. 5.00, 09/03, page 409 of 760 13.1.3 pin configuration table 13.1 shows the rtc pin configuration. table 13.1 rtc pins pin signal name i/o description rtc oscillator crystal pin extal2 i connects crystal to rtc oscillator * 2 rtc oscillator crystal pin xtal2 o connects crystal to rtc oscillator * 2 clock input/clock output tclk i/o external clock input pin/input capture control input pin/realtime clock (rtc) output pin (shared by tmu) dedicated power-supply pin for rtc vcc?rtc ? dedicated power-supply pin for rtc * 1 dedicated gnd pin for rtc vss?rtc ? dedicated gnd pin for rtc * 1 notes: 1. except in hardware standby mode, power must be supplied to all power supply pins, including these, even when only the rtc is used (including standby mode). 2. when the rtc is not used, pull extal2 up (to vcc) and make no connection for xtal2.
rev. 5.00, 09/03, page 410 of 760 13.1.4 rtc register configuration table 13.2 shows the rtc register configuration. table 13.2 rtc registers name abbreviation r/w initial value address access size 64-hz counter r64cnt r undefined h'fffffec0 8 second counter rseccnt r/w undefined h'fffffec2 8 minute counter rmincnt r/w undefined h'fffffec4 8 hour counter rhrcnt r/w undefined h'fffffec6 8 day of week counter rwkcnt r/w undefined h'fffffec8 8 date counter rdaycnt r/w undefined h'fffffeca 8 month counter rmoncnt r/w undefined h'fffffecc 8 year counter ryrcnt r/w undefined h'fffffece 8 second alarm register rsecar r/w undefined * h'fffffed0 8 minute alarm register rminar r/w undefined * h'fffffed2 8 hour alarm register rhrar r/w undefined * h'fffffed4 8 day of week alarm register rwkar r/w undefined * h'fffffed6 8 date alarm register rdayar r/w undefined * h'fffffed8 8 month alarm register rmonar r/w undefined * h'fffffeda 8 rtc control register 1 rcr1 r/w h'00 h'fffffedc 8 rtc control register 2 rcr2 r/w h'09 h'fffffede 8 note: * only the enb bits of each register are initialized.
rev. 5.00, 09/03, page 411 of 760 13.2 rtc registers 13.2.1 64-hz counter (r64cnt) the 64-hz counter (r64cnt) is an 8-bit read-only register that indicates the states of the rtc divider circuit, rtc prescaler, and r64cnt between 64 hz and 1 hz. r64cnt is initialized to h'00 by setting the reset bit in rtc control register 2 (rcr2) or the adj bit in rcr2 to 1. r64cnt is not initialized by a power-on reset or manual reset, or in standby mode. bit 7 is always read as 0. bit:76543210 ? 1hz 2hz 4hz 8hz 16hz 32hz 64hz initial value:0 ??????? r/w:rrrrrrrr 13.2.2 second counter (rseccnt) the second counter (rseccnt) is an 8-bit readable/writable register used for setting/counting in the bcd-coded second section of the rtc. the count operation is performed by a carry for each second of the 64 - hz counter. the range that can be set is 00 ? 59 (decimal). errant operation will result if any other value is set. carry out write processing after halting the count operation with the start bit in rcr2. rseccnt is not initialized by a power-on reset or manual reset, or in standby mode. bit:76543210 ? 10 seconds 1 second initial value:0 ??????? r/w: r r/w r/w r/w r/w r/w r/w r/w
rev. 5.00, 09/03, page 412 of 760 13.2.3 minute counter (rmincnt) the minute counter (rmincnt) is an 8-bit readable/writable register used for setting/counting in the bcd-coded minute section of the rtc. the count operation is performed by a carry for each minute of the second counter. the range that can be set is 00?59 (decimal). errant operation will result if any other value is set. carry out write processing after halting the count operation with the start bit in rcr2. rmincnt is not initialized by a power-on reset or manual reset, or in standby mode. bit:76543210 ? 10 minutes 1 minute initial value:0 ??????? r/w: r r/w r/w r/w r/w r/w r/w r/w 13.2.4 hour counter (rhrcnt) the hour counter (rhrcnt) is an 8-bit readable/writable register used for setting/counting in the bcd-coded hour section of the rtc. the count operation is performed by a carry for each 1 hour of the minute counter. the range that can be set is 00 ? 23 (decimal). errant operation will result if any other value is set. carry out write processing after halting the count operation with the start bit in rcr2 or using a carry flag as shown in figure 13.2. rhrcnt is not initialized by a power-on reset or manual reset, or in standby mode. bit:76543210 ? ? 10 hours 1 hour initial value:0 0 ?????? r/w: r r r/w r/w r/w r/w r/w r/w
rev. 5.00, 09/03, page 413 of 760 13.2.5 day of week counter (rwkcnt) the day of week counter (rwkcnt) is an 8-bit readable/writable register used for setting/counting in the bcd-coded day of week section of the rtc. the count operation is performed by a carry for each day of the date counter. the range that can be set is 0 ? 6 (decimal). errant operation will result if any other value is set. carry out write processing after halting the count operation with the start bit in rcr2. rwkcnt is not initialized by a power-on reset or manual reset, or in standby mode. bit:76543210 ????? day of week initial value: 0 0 0 0 0 ? ? ? r/w:rrrrrr/wr/wr/w days of the week are coded as shown in table 13.3. table 13.3 day-of-week codes (rwkcnt) day of week code sunday 0 monday 1 tuesday 2 wednesday 3 thursday 4 friday 5 saturday 6
rev. 5.00, 09/03, page 414 of 760 13.2.6 date counter (rdaycnt) the date counter (rdaycnt) is an 8-bit readable/writable register used for setting/counting in the bcd-coded date section of the rtc. the count operation is performed by a carry for each day of the hour counter. the range that can be set is 01 ? 31 (decimal). errant operation will result if any other value is set. carry out write processing after halting the count operation with the start bit in rcr2. rdaycnt is not initialized by a power-on reset or manual reset, or in standby mode. the rdaycnt range that can be set changes with each month and in leap years. please confirm the correct setting. bit:76543210 ? ? 10 days 1 day initial value:0 0 ?????? r/w: r r r/w r/w r/w r/w r/w r/w 13.2.7 month counter (rmoncnt) the month counter (rmoncnt) is an 8-bit readable/writable register used for setting/counting in the bcd-coded month section of the rtc. the count operation is performed by a carry for each month of the date counter. the range that can be set is 00 ? 12 (decimal). errant operation will result if any other value is set. carry out write processing after halting the count operation with the start bit in rcr2. rmoncnt is not initialized by a power-on reset or manual reset, or in standby mode. bit:76543210 ???10 months 1 month initial value:0 0 0 ????? r/w: r r r r/w r/w r/w r/w r/w
rev. 5.00, 09/03, page 415 of 760 13.2.8 year counter (ryrcnt) the year counter (ryrcnt) is an 8-bit readable/writable register used for setting/counting in the bcd-coded year section of the rtc. the least significant 2 digits of the western calendar year are displayed. the count operation is performed by a carry for each year of the month counter. the range that can be set is 00 ? 99 (decimal). errant operation will result if any other value is set. carry out write processing after halting the count operation with the start bit in rcr2. ryrcnt is not initialized by a power-on reset or manual reset, or in standby mode. leap years are recognized by dividing the year counter value by 4 and obtaining a fractional result of 0. the year counter value: 00 is included in leap years. bit:76543210 10 years 1 year initial value:???????? r/w: r/w r/w r/w r/w r/w r/w r/w r/w 13.2.9 second alarm register (rsecar) the second alarm register (rsecar) is an 8-bit readable/writable register, and an alarm register corresponding to the bcd-coded second section counter rseccnt of the rtc. when the enb bit is set to 1, a comparison with the rseccnt value is performed. from among the rsecar/rminar/rhrar/rwkar/rdayar/rmonar registers, the counter and alarm register comparison is performed only on those with enb bits set to 1, and if each of those coincide, an rtc alarm interrupt is generated. the range that can be set is 00 ? 59 (decimal) + enb bit. errant operation will result if any other value is set. the enb bit in rsecar is initialized to 0 by a power-on reset. the remaining rsecar fields are not initialized and retain their contents by a manual reset, or in standby mode. bit:76543210 enb 10 seconds 1 second initial value:0 ??????? r/w: r/w r/w r/w r/w r/w r/w r/w r/w
rev. 5.00, 09/03, page 416 of 760 13.2.10 minute alarm register (rminar) the minute alarm register (rminar) is an 8-bit readable/writable register, and an alarm register corresponding to the bcd-coded minute section counter rmincnt of the rtc. when the enb bit is set to 1, a comparison with the rmincnt value is performed. from among the rsecar/rminar/rhrar/rwkar/rdayar/rmonar registers, the counter and alarm register comparison is performed only on those with enb bits set to 1, and if each of those coincide, an rtc alarm interrupt is generated. the range that can be set is 00 ? 59 (decimal) + enb bit. errant operation will result if any other value is set. the enb bit in rminar is initialized by a power-on reset. the remaining rminar fields are not initialized and retain their contents by a manual reset, or in standby mode. bit:76543210 enb 10 minutes 1 minute initial value:0 ??????? r/w: r/w r/w r/w r/w r/w r/w r/w r/w 13.2.11 hour alarm register (rhrar) the hour alarm register (rhrar) is an 8-bit readable/writable register, and an alarm register corresponding to the bcd-coded hour section counter rhrcnt of the rtc. when the enb bit is set to 1, a comparison with the rhrcnt value is performed. from among the rsecar/rminar/rhrar/rwkar/rdayar/rmonar registers, the counter and alarm register comparison is performed only on those with enb bits set to 1, and if each of those coincide, an rtc alarm interrupt is generated. the range that can be set is 00 ? 23 (decimal) + enb bit. errant operation will result if any other value is set. the enb bit in rhrar is initialized by a power-on reset. the remaining rhrar fields are not initialized and retain their contents by a manual reset, or in standby mode. bit:76543210 enb ? 10 hours 1 hour initial value:0 0 ?????? r/w: r/w r r/w r/w r/w r/w r/w r/w
rev. 5.00, 09/03, page 417 of 760 13.2.12 day of week alarm register (rwkar) the day of week alarm register (rwkar) is an 8-bit readable/writable register, and an alarm register corresponding to the bcd-coded day of week section counter rwkcnt of the rtc. when the enb bit is set to 1, a comparison with the rwkcnt value is performed. from among the rsecar/rminar/rhrar/rwkar/rdayar/rmonar registers, the counter and alarm register comparison is performed only on those with enb bits set to 1, and if each of those coincide, an rtc alarm interrupt is generated. the range that can be set is 0 ? 6 (decimal) + enb bit. errant operation will result if any other value is set. the enb bit in rwkar is initialized by a power-on reset. the remaining rwkar fields are not initialized and retain their contents by a manual reset, or in standby mode. bit:76543210 enb???? day of week initial value: 0 0 0 0 0 ? ? ? r/w:r/wrrrrr/wr/wr/w days of the week are coded as shown in table 13.4. table 13.4 day-of-week codes (rwkar) day of week code sunday 0 monday 1 tuesday 2 wednesday 3 thursday 4 friday 5 saturday 6
rev. 5.00, 09/03, page 418 of 760 13.2.13 date alarm register (rdayar) the date alarm register (rdayar) is an 8-bit readable/writable register, and an alarm register corresponding to the bcd-coded date section counter rdaycnt of the rtc. when the enb bit is set to 1, a comparison with the rdaycnt value is performed. from among the registers rsecar, rminar, rhrar, rwkar, rdayar, rmonar, the counter and alarm register comparison is performed only on those with enb bits set to 1, and if each of those coincide, an rtc alarm interrupt is generated. the range that can be set is 01 ? 31 (decimal) + enb bit. errant operation will result if any other value is set. the rdaycnt range that can be set changes with some months and in leap years. please confirm the correct setting. the enb bit in rdayar is initialized by a power-on reset. the remaining rdayar fields are not initialized and retain their contents by a manual reset, or in standby mode. bit:76543210 enb ? 10 days 1 day initial value:0 0 ?????? r/w: r/w r r/w r/w r/w r/w r/w r/w 13.2.14 month alarm register (rmonar) the month alarm register (rmonar) is an 8-bit readable/writable register, and an alarm register corresponding to the bcd-coded month section counter rmoncnt of the rtc. when the enb bit is set to 1, a comparison with the rmoncnt value is performed. from among the registers rsecar, rminar, rhrar, rwkar, rdayar, rmonar, the counter and alarm register comparison is performed only on those with enb bits set to 1, and if each of those coincide, an rtc alarm interrupt is generated. the range that can be set is 01 ? 12 (decimal) + enb bit. errant operation will result if any other value is set. the enb bit in rmonar is initialized by a power-on reset. the remaining rmonar fields are not initialized and retain their contents by a manual reset, or in standby mode. bit:76543210 enb ? ? 10 months 1 month initial value:0 0 0 ????? r/w: r/w r r r/w r/w r/w r/w r/w
rev. 5.00, 09/03, page 419 of 760 13.2.15 rtc control register 1 (rcr1) the rtc control register 1 (rcr1) is an 8-bit readable/writable register that affects carry flags and alarm flags. it also selects whether to generate interrupts for each flag. because flags are sometimes set after an operand read, do not use this register in read-modify-write processing. rcr1 is initialized to h'00 by a power-on reset or a manual reset. in a manual reset, all bits are initialized to h'00 except for the cf flag, which is undefined. when using the cf flag, it must be initialized beforehand. this register is not initialized in standby mode. bit:76543210 cf ? ? cie aie ? ? af initial value:00000000 r/w: r/w r r r/w r/w r r r/w bit 7 ? carry flag (cf): status flag that indicates that a carry has occurred. setting cf to 1 indicates reading of a counter register value has occurred when (1) the second counter is carried or (2) the 64-hz counter is carried. a count register value read at this time cannot be guaranteed; another read is required. bit 7: cf description 0 no count up of r64cnt or rseccnt clearing condition: when 0 is written to cf (initial value) 1 count up of r64cnt or rseccnt setting condition: when 1 is written to cf bits 6, 5, 2, and 1 ? reserved: these bits are always read as 0. the write value should always be 0. bit 4 ? carry interrupt enable flag (cie): when the carry flag (cf) is set to 1, the cie bit enables interrupts. bit 4: cie description 0 a carry interrupt is not generated when the cf flag is set to 1 (initial value) 1 a carry interrupt is generated when the cf flag is set to 1
rev. 5.00, 09/03, page 420 of 760 bit 3 ? alarm interrupt enable flag (aie): when the alarm flag (af) is set to 1, the aie bit allows interrupts. bit 3: aie description 0 an alarm interrupt is not generated when the af flag is set to 1 (initial value) 1 an alarm interrupt is generated when the af flag is set to 1 bit 0 ? alarm flag (af): the af flag is set to 1 when the alarm time set in an alarm register (only registers with enb bit set to 1) matches the clock and calendar time. this flag is cleared to 0 when 0 is written, but holds its previous value when 1 is written. bit 0: af description 0 clock/calendar and alarm register have not matched since last reset to 0 clearing condition: when 0 is written to af (initial value) 1 setting condition: clock/calendar and alarm register have matched (only registers with enb set) * note: * contents do not change when 1 is written to af. 13.2.16 rtc control register 2 (rcr2) the rtc control register 2 (rcr2) is an 8-bit readable/writable register for periodic interrupt control, 30-second adjustment adj, divider circuit reset, and rtc count start/stop control. it is initialized to h'09 by a power-on reset. it is initialized except for rtcen and start by a manual reset. it is not initialized, and retains its contents, in standby mode. bit:76543210 pef pes2 pes1 pes0 rtcen adj reset start initial value:00001001 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit 7 ? periodic interrupt flag (pef): indicates interrupt generation with the period designated by the pes bits. when set to 1, pef generates periodic interrupts. bit 7: pef description 0 interrupts not generated with the period designated by the pes bits clearing condition: when 0 is written to pef (initial value) 1 interrupts generated with the period designated by the pes bits setting condition: when 1 is written to pef
rev. 5.00, 09/03, page 421 of 760 bits 6 to 4?periodic interrupt flags (pes2-pes0): specify the periodic interrupt. bit 6: pes2 bit 5: pes1 bit 4: pes0 description 0 0 0 no periodic interrupts generated (initial value) 1 periodic interrupt generated every 1/256 second 1 0 periodic interrupt generated every 1/64 second 1 periodic interrupt generated every 1/16 second 1 0 0 periodic interrupt generated every 1/4 second 1 periodic interrupt generated every 1/2 second 1 0 periodic interrupt generated every 1 second 1 periodic interrupt generated every 2 seconds bit 3 ? rtcen: controls the operation of the crystal oscillator for the rtc. bit 3: rtcen description 0 crystal oscillator for rtc is halted 1 crystal oscillator for rtc runs (initial value) bit 2 ? 30 second adjustment (adj): when 1 is written to the adj bit, times of 29 seconds or less will be rounded to 00 seconds and 30 seconds or more to 1 minute. the divider circuit, rtc prescaler, and r64cnt will be simultaneously reset. this bit is always read as 0. the maximum duration between when the adj bit is set to 1 and when the new setting is reflected in the readout value from the seconds counter (rseccnt) is approximately 91.6 s (when a 32.768 khz quartz oscillator is connected to the extal2 pin). bit 2: adj description 0 runs normally (initial value) 1 (write) 30-second adjustment bit 1 ? reset (reset): when 1 is written, initializes the divider circuit (rtc prescaler and r64cnt). this bit is always read as 0. bit 1: reset description 0 runs normally (initial value) 1 (write) divider circuit is reset
rev. 5.00, 09/03, page 422 of 760 bit 0 ? start bit (start): halts and restarts the counter (clock). bit 0: start description 0 second/minute/hour/day/week/month/year counter halts 1 second/minute/hour/day/week/month/year counter runs normally (initial value) note: the 64-hz counter always runs unless stopped with the rtcen bit. 13.3 rtc operation 13.3.1 initial settings of registers after power-on all the registers should be set after the power is turned on. 13.3.2 setting the time figure 13.2 shows how to set the time when the clock is stopped. this works when the entire calendar or clock is to be set. programming can be easily performed. write 1 to reset and 0 to start in the rcr2 register order is irrelevant write 1 to start in the rcr2 register set seconds, minutes, hour, day, day of the week, month and year stop clock, reset divider circuit to reset the divider circuit (rtc prescaler and r64cnt) and set the counter start clock figure 13.2 setting the time
rev. 5.00, 09/03, page 423 of 760 13.3.3 reading the time figure 13.3 shows how to read the time. if a carry occurs while reading the time, the correct time will not be obtained, so it must be read again. part (a) in figure 13.3 shows the method of reading the time without using interrupts; part (b) in figure 13.3 shows the method using carry interrupts. to keep programming simple, method (a) should normally be used. write 0 to cf in rcr1 note: set af to 1 so that alarm flag is not cleared. clear cie in rcr1 to 0 read rcr1 and check cf write 0 to cie in rcr1 carry flag = 1? no yes clear the carry flag disable the carry interrupt read counter register write 1 to cie in rcr1, and write 0 to cf in rcr1 note: set af in rcr1 to 1 so that alarm flag is not cleared. interrupt generated? no yes enable the carry interrupt clear the carry flag disable the carry interrupt read counter register to read the time without using interrupts b. to use interrupts a. figure 13.3 reading the time
rev. 5.00, 09/03, page 424 of 760 13.3.4 alarm function figure 13.4 shows how to use the alarm function. alarms can be generated using seconds, minutes, hours, day of the week, date, month, or any combination of these. set the enb bit (bit 7) to 1 in the register to which the alarm applies, and then set the alarm time in the lower bits. clear the enb bit to 0 in registers to which the alarm does not apply. when the clock and alarm times match, 1 is set in the af bit (bit 0) in rcr1. alarm detection can be checked by reading this bit, but normally it is done by interrupt. if 1 is placed in the aie bit (bit 3) in rcr1, an interrupt is generated when an alarm occurs. disable interrupts for preventing error interrupts (clear the aie bit in rcr1 to 0). then write 1 to the aie bit in rcr1. clock running set alarm time set whether to use alarm interrupt always reset, since the flag may have been set while the alarm time was being set (clear the af bit in rcr1 to 0). clear alarm flag monitor alarm time (wait for interrupt or check alarm flag) figure 13.4 using the alarm function
rev. 5.00, 09/03, page 425 of 760 13.3.5 crystal oscillator circuit crystal oscillator circuit constants (recommended values) are shown in table 13.5, and the rtc crystal oscillator circuit in figure 13.5. table 13.5 recommended oscillator circuit constants (recommended values) fosc cin cout 32.768 khz 10 to 22 pf 10 to 22 pf sh7709s extal2 xtal2 xtal c in c out r f r d notes: 1. select either the c in or c out side for the frequency adjustment variable capacitor according to requirements such as frequency range, degree of stability, etc. 2. built-in resistance value r f (typ value) = 10 m ? , r d (typ value) = 400 k ? 3. c in and c out values include floating capacitance due to the wiring. take care when using a ground plane. 4. the crystal oscillation settling time depends on the mounted circuit constants, floating capacitance, etc., and should be decided after consultation with the crystal resonator manufacturer. 5. place the crystal resonator and load capacitors c in and c out as close as possible to the chip. (correct oscillation may not be possible if there is externally induced noise in the extal2 and xtal2 pins.) 6. ensure that the crystal resonator connection pin (extal2, xtal2) wiring is routed as far away as possible from other power lines (except gnd) and signal lines. figure 13.5 example of crystal oscillator circuit connection
rev. 5.00, 09/03, page 426 of 760 13.4 usage notes 13.4.1 register writing during rtc count the following rtc registers cannot be written to during an rtc count (while bit 0 = 1 in rcr2). rseccnt, rmincnt, rhrcnt, rdaycnt, rwkcnt, rmoncnt, ryrcnt the rtc count must be halted before writing to any of the above registers. 13.4.2 use of realtime clock (rtc) periodic interrupts the method of using the periodic interrupt function is shown in figure 13.6. a periodic interrupt can be generated periodically at the interval set by the periodic interrupt enable flag (pes) in rtc control register 2 (rcr2). when the time set by the periodic interrupt enable flag (pes) has elapsed, the periodic interrupt flag (pef) is set to 1. the periodic interrupt flag (pef) is cleared to 0 upon periodic interrupt generation when the periodic interrupt enable flag (pes) is set. periodic interrupt generation can be confirmed by reading this bit, but normally the interrupt function is used. set pes, and clear pef to 0, in rcr2 clear pef to 0 set pes, clear pef elapse of time set by pes clear pef figure 13.6 using periodic interrupt function 13.4.3 precautions when using rtc module standby before switching the rtc to module standby, access at least one among the registers rtc, sci, and tmu.
rev. 5.00, 09/03, page 427 of 760 section 14 serial communication interface (sci) 14.1 overview the sh7709s has an on-chip serial communication interface (sci) that supports both asynchronous and clock synchronous serial communication. it also has a multiprocessor communication function for serial communication among two or more processors. the sci supports a smart card interface, which is a serial communication feature for ic card interfaces that conforms to the iso/iec standard 7816-3 for identification cards. see section 15, smart card interface, for more information. 14.1.1 features selection of asynchronous or synchronous as the serial communication mode. ? asynchronous mode: ? serial data communication is synchronized by start-stop in character units. the sci can communicate with a universal asynchronous receiver/transmitter (uart), an asynchronous communication interface adapter (acia), or any other communications chip that employs a standard asynchronous serial system. it can also communicate with two or more other processors using the multiprocessor communication function. there are 12 selectable serial data communication formats. ? data length: 7 or 8 bits ? stop bit length: 1 or 2 bits ? parity: even, odd, or none ? multiprocessor bit: 1 or 0 ? receive error detection: parity, overrun, and framing errors ? break detection: by reading the rxd level directly from the sc port data register (scpdr) when a framing error occurs ? synchronous mode: ? serial data communication is synchronized with a clock signal. the sci can communicate with other chips having a synchronous communication function. there is one serial data communication format. ? data length: 8 bits ? receive error detection: overrun errors ? full duplex communication: the transmitting and receiving sections are independent, so the sci can transmit and receive simultaneously. both sections use double buffering, so continuous data transfer is possible in both the transmit and receive directions. ? on-chip baud rate generator with selectable bit rates
rev. 5.00, 09/03, page 428 of 760 ? internal or external transmit/receive clock source: from either baud rate generator (internal) or sck pin (external) ? four types of interrupts: transmit-data-empty, transmit-end, receive-data-full, and receive- error interrupts are requested independently. ? when the sci is not in use, it can be stopped by halting the clock supplied to it, saving power. 14.1.2 block diagram figure 14.1 shows a block diagram of the sci. rxd txd sck sci scbrr scssr scscr sctsr scrdr scrsr scsmr scpcr scpdr parity generation parity check clock external clock module data bus internal data bus p p /4 p /16 p /64 txi tei rxi eri bus interface baud rate generator transmit/ receive control scrsr: scrdr: sctsr: sctdr: scsmr: legend receive shift register receive data register transmit shift register transmit data register serial mode register scscr: scssr: scbrr: scpdr: scpcr: serial control register serial status register bit rate register sc port data register sc port control register sctdr figure 14.1 block diagram of sci
rev. 5.00, 09/03, page 429 of 760 figures 14.2, 14.3, and 14.4 show block diagrams of the sci i/o port pins. scif pin i/o and data control is performed by bits 11 to 8 of scpcr and bits 5 and 4 of scpdr. for details, see section 14.2.8, sc port control register (scpcr)/sc port data register (scpdr). internal data bus output enable clock input enable sci serial clock output serial clock input r scp1md0 pcrw reset c q q d r scp1md1 pcrw reset c qd r scp1dt1 pdrw reset scpt[1]/sck0 c d pdrw: scpdr write pdrr: pcrw: scpdr read scpcr write pdrr * note: * legend when reading the sck0 pin, clear the c/ a bit in scsmr and the cke1 and cke0 bits in scscr to 0, and set the scp1md1 bit in scpcr to 1 (see section 14.2.8, sc port control register (scpcr)/sc port data register (scpdr)). figure 14.2 scpt[1]/sck0 pin
rev. 5.00, 09/03, page 430 of 760 internal data bus output enable sci serial transmission output r scp0md0 pcrw reset c q q d r scp0md1 pcrw reset c qd r scp0dt1 pdrw reset scpt[0]/txd0 c d pcrw: pdrw: scpcr write scpdr write legend figure 14.3 scpt[0]/txd0 pin
rev. 5.00, 09/03, page 431 of 760 sci serial receive data internal data bus pdrr * scpt[0]/rxd0 pdrr: pdr read note: * when reading the rxd0 pin, set the re bit in scscr to 1. legend figure 14.4 scpt[0]/rxd0 pin 14.1.3 pin configuration the sci has the serial pins summarized in table 14.1. table 14.1 sci pins pin name abbreviation i/o function serial clock pin sck0 i/o clock i/o receive data pin rxd0 input receive data input transmit data pin txd0 output transmit data output note: these pins are made to function as serial pins by performing sci operation settings with the te, re, ckei, and cke0 bits in scscr and the c/ a bit in scsmr. break state transmission and detection can be performed by means of the sci?s scsptr register.
rev. 5.00, 09/03, page 432 of 760 14.1.4 register configuration table 14.2 summarizes the sci internal registers. these registers select the communication mode (asynchronous or synchronous), specify the data format and bit rate, and control the transmitter and receiver sections. table 14.2 sci registers name abbreviation r/w initial value address access size serial mode register scsmr r/w h'00 h'fffffe80 8 bit rate register scbrr r/w h'ff h'fffffe82 8 serial control register scscr r/w h'00 h'fffffe84 8 transmit data register sctdr r/w h'ff h'fffffe86 8 serial status register scssr r/(w) * h'84 h'fffffe88 8 receive data register scrdr r h'00 h'fffffe8a 8 sc port data register scpdr r/w h'00 h'04000136 (h'a4000136) * 2 8 sc port control register scpcr r/w h'a888 h'04000116 (h'a4000116) * 2 16 notes: these registers are located in area 1 of physical space. therefore, when the cache is on, either access these registers from the p2 area of logical space or else make an appropriate setting using the mmu so that these registers are not cached. 1. the only value that can be written is 0 to clear the flags. 2. when address translation by the mmu does not apply, the address in parentheses should be used. 14.2 register descriptions 14.2.1 receive shift register (scrsr) the receive shift register (scrsr) receives serial data. data input at the rxd pin is loaded into scrsr in the order received, lsb (bit 0) first, converting the data to parallel form. when one byte has been received, it is automatically transferred to scrdr. the cpu cannot read or write to scrsr directly. bit:76543210 r/w:????????
rev. 5.00, 09/03, page 433 of 760 14.2.2 receive data register (scrdr) the receive data register (scrdr) stores serial receive data. the sci completes the reception of one byte of serial data by moving the received data from the receive shift register (scrsr) into scrdr for storage. scrsr is then ready to receive the next data. this double buffering allows the sci to receive data continuously. the cpu can read but not write to scrdr. scrdr is initialized to h'00 by a reset and in standby or module standby mode. bit:76543210 initial value:00000000 r/w:rrrrrrrr 14.2.3 transmit shift register (sctsr) the transmit shift register (sctsr) transmits serial data. the sci loads transmit data from the transmit data register (sctdr) into sctsr, then transmits the data serially from the txd pin, lsb (bit 0) first. after transmitting one-byte data, the sci automatically loads the next transmit data from sctdr into sctsr and starts transmitting again. if the tdre bit in scssr is 1, however, the sci does not load the sctdr contents into sctsr. the cpu cannot read or write to sctsr directly. bit:76543210 r/w:????????
rev. 5.00, 09/03, page 434 of 760 14.2.4 transmit data register (sctdr) the transmit data register (sctdr) is an 8-bit register that stores data for serial transmission. when the sci detects that the transmit shift register (sctsr) is empty, it moves transmit data written in sctdr into sctsr and starts serial transmission. continuous serial transmission is possible by writing the next transmit data in sctdr during serial transmission from sctsr. the cpu can always read and write to sctdr. sctdr is initialized to h'ff by a reset and in standby or module standby mode. bit:76543210 initial value:11111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 14.2.5 serial mode register (scsmr) the serial mode register (scsmr) is an 8-bit register that specifies the sci serial communication format and selects the clock source for the baud rate generator. the cpu can always read and write to scsmr. scsmr is initialized to h'00 by a reset and in standby or module standby mode. bit:76543210 c/ a chr pe o/ e stop mp cks1 cks0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit 7?communication mode (c/ a a a a ): selects whether the sci operates in asynchronous or synchronous mode. bit 7: c/ a a a a description 0 asynchronous mode (initial value) 1 synchronous mode
rev. 5.00, 09/03, page 435 of 760 bit 6?character length (chr): selects 7-bit or 8-bit data in asynchronous mode. in the synchronous mode, the data length is always eight bits, regardless of the chr setting. bit 6: chr description 0 8-bit data (initial value) 1 7-bit data * note: * when 7-bit data is selected, the msb (bit 7) of the transmit data register (sctdr) is not transmitted. bit 5?parity enable (pe): selects whether to add a parity bit to transmit data and to check the parity of receive data, in asynchronous mode. in synchronous mode, a parity bit is neither added nor checked, regardless of the pe setting. bit 5: pe description 0 parity bit not added or checked (initial value) 1 parity bit added and checked * note: * when pe is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (o/ e ) setting. receive data parity is checked according to the even/odd (o/ e ) mode setting. bit 4?parity mode (o/ e e e e ): selects even or odd parity when parity bits are added and checked. the o/ e setting is used only in asynchronous mode and only when the parity enable bit (pe) is set to 1 to enable parity addition and checking. the o/ e setting is ignored in synchronous mode, or in asynchronous mode when parity addition and checking is disabled. bit 4: o/ e e e e description 0 even parity * 1 (initial value) 1 odd parity * 2 notes: 1. if even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 2. if odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined.
rev. 5.00, 09/03, page 436 of 760 bit 3?stop bit length (stop): selects one or two bits as the stop bit length in asynchronous mode. this setting is used only in asynchronous mode. it is ignored in synchronous mode because no stop bits are added. when receiving, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. bit 3: stop description 0 one stop bit * 1 (initial value) 1 two stop bits * 2 notes: 1. when transmitting, a single 1-bit is added at the end of each transmitted character. 2. when transmitting, two 1-bits are added at the end of each transmitted character. bit 2?multiprocessor mode (mp): selects multiprocessor format. when multiprocessor format is selected, settings of the parity enable (pe) and parity mode (o/ e ) bits are ignored. the mp bit setting is used only in asynchronous mode; it is ignored in synchronous mode. for the multiprocessor communication function, see section 14.3.3, multiprocessor communication. bit 2: mp description 0 multiprocessor function disabled (initial value) 1 multiprocessor format selected bits 1 and 0?clock select 1 and 0 (cks1, cks0): select the internal clock source of the on- chip baud rate generator. four clock sources are available. p , p /4, p /16 and p /64 can be set according to the setting of the cks1 and cks0 bits. for further information on the clock source, bit rate register settings, and baud rate, see section 14.2.9, bit rate register (scbrr). bit 1: cks1 bit 0: cks0 description 00p (initial value) 1p /4 10p /16 1p /64 note: p : peripheral clock
rev. 5.00, 09/03, page 437 of 760 14.2.6 serial control register (scscr) the serial control register (scscr) operates the sci transmitter/receiver, selects the serial clock output in asynchronous mode, enables/disables interrupt requests, and selects the transmit/receive clock source. the cpu can always read and write to scscr. scscr is initialized to h'00 by a reset and in standby or module standby mode. bit:76543210 tie rie te re mpie teie cke1 cke0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit 7?transmit interrupt enable (tie): enables or disables the transmit-data-empty interrupt (txi) requested when the transmit data register empty bit (tdre) in the serial status register (scssr) is set to 1 due to transfer of serial transmit data from sctdr to sctsr. bit 7: tie description 0 transmit-data-empty interrupt request (txi) is disabled * (initial value) 1 transmit-data-empty interrupt request (txi) is enabled note: * the txi interrupt request can be cleared by reading tdre after it has been set to 1, then clearing tdre to 0, or by clearing tie to 0. bit 6?receive interrupt enable (rie): enables or disables the receive-data-full interrupt (rxi) requested when the receive data register full bit (rdrf) in the serial status register (scssr) is set to 1 due to transfer of serial receive data from scrsr to scrdr. it also enables or disables receive-error interrupt (eri) requests. bit 6: rie description 0 receive-data-full interrupt (rxi) and receive-error interrupt (eri) requests are disabled * (initial value) 1 receive-data-full interrupt (rxi) and receive-error interrupt (eri) requests are enabled note: * rxi and eri interrupt requests can be cleared by reading the rdrf flag or error flag (fer, per, or orer) after it has been set to 1, then clearing the flag to 0, or by clearing rie to 0.
rev. 5.00, 09/03, page 438 of 760 bit 5?transmit enable (te): enables or disables the sci serial transmitter. bit 5: te description 0 transmitter disabled * 1 (initial value) 1 transmitter enabled * 2 notes: 1. the transmit data register empty bit (tdre) in the serial status register (scssr) is fixed at 1. 2. serial transmission starts when the transmit data register empty (tdre) bit in the serial status register (scssr) is cleared to 0 after writing of transmit data into the sctdr. select the transmit format in scsmr before setting te to 1. bit 4?receive enable (re): enables or disables the sci serial receiver. bit 4: re description 0 receiver disabled * 1 (initial value) 1 receiver enabled * 2 notes: 1. clearing re to 0 does not affect the receive flags (rdrf, fer, per, orer). these flags retain their previous values. 2. serial reception starts when a start bit is detected in asynchronous mode, or synchronous clock input is detected in synchronous mode. select the receive format in scsmr before setting re to 1. bit 3?multiprocessor interrupt enable (mpie): enables or disables multiprocessor interrupts. the mpie setting is used only in asynchronous mode, and only if the multiprocessor mode bit (mp) in the serial mode register (scsmr) is set to 1 during reception. the mpie setting is ignored in synchronous mode or when the mp bit is cleared to 0. bit 3: mpie description 0 multiprocessor interrupts are disabled (normal receive operation) (initial value) [clearing conditions] (1) mpe is cleared to 0 when mpie is cleared to 0. (2) the multiprocessor bit (mpb) is set to 1 in receive data. 1 multiprocessor interrupts are enabled * receive-data-full interrupt requests (rxi), receive-error interrupt requests (eri), and setting of the rdrf, fer, and orer status flags in the serial status register (scssr) are disabled until data with a multiprocessor bit of 1 is received. note: * the sci does not transfer receive data from scrsr to scrdr, does not detect receive errors, and does not set the rdrf, fer, and orer flags in the serial status register (scssr). when it receives data that includes mpb = 1, the scssr?s mpb flag is set to 1, and the sci automatically clears mpie to 0, generates rxi and eri interrupts (if the tie and rie bits in the scscr are set to 1), and allows the fer and orer bits to be set.
rev. 5.00, 09/03, page 439 of 760 bit 2?transmit-end interrupt enable (teie): enables or disables the transmit-end interrupt (tei) requested if sctdr does not contain new transmit data when the msb is transmitted. bit 2: teie description 0 transmit-end interrupt (tei) requests are disabled * (initial value) 1 transmit-end interrupt (tei) requests are enabled * note: * the tei request can be cleared by reading the tdre bit in the serial status register (scssr) after it has been set to 1, then clearing tdre to 0 and clearing the transmit end (tend) bit to 0, or by clearing the teie bit to 0. bits 1 and 0?clock enable 1 and 0 (cke1, cke0): select the sci clock source and enable or disable clock output from the sck pin. depending on the combination of cke1 and cke0, the sck pin can be used for serial clock output or serial clock input. the cke0 setting is valid only in asynchronous mode, and only when the sci is internally clocked (cke1 = 0). the cke0 setting is ignored in synchronous mode, or when an external clock source is selected (cke1 = 1). before selecting the sci operating mode in the serial mode register (scsmr), set cke1 and cke0. for further details on selection of the sci clock source, see table 14.10 in section 14.3, operation. bit 1: cke1 bit 0: cke0 description 0 0 asynchronous mode internal clock, sck pin used for input pin (input signal is ignored) (initial value) synchronous mode internal clock, sck pin used for synchronous clock output (initial value) 1 asynchronous mode internal clock, sck pin used for clock output * 1 synchronous mode internal clock, sck pin used for synchronous clock output 1 0 asynchronous mode external clock, sck pin used for clock input * 2 synchronous mode external clock, sck pin used for synchronous clock input 1 asynchronous mode external clock, sck pin used for clock input * 2 synchronous mode external clock, sck pin used for synchronous clock input notes: 1. the output clock frequency is the same as the bit rate. 2. the input clock frequency is 16 times the bit rate.
rev. 5.00, 09/03, page 440 of 760 14.2.7 serial status register (scssr) the serial status register (scssr) is an 8-bit register containing multiprocessor bit values, and status flags that indicate the sci operating state. the cpu can always read and write to scssr, but cannot write 1 to the status flags (tdre, rdrf, orer, per, and fer). these flags can be cleared to 0 only if they have first been read (after being set to 1). bits 2 (tend) and 1 (mpb) are read-only bits that cannot be written. scssr is initialized to h'84 by a reset and in standby or module standby mode. bit:76543210 tdre rdrf orer fer per tend mpb mpbt initial value:10000100 r/w: r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * rrr/w note: * the only value that can be written is 0 to clear the flag. bit 7?transmit data register empty (tdre): indicates that the sci has loaded transmit data from sctdr into sctsr and new serial transmit data can be written in sctdr. bit 7: tdre description 0 sctdr contains valid transmit data [clearing condition] tdre is cleared to 0 when software reads tdre after it has been set to 1. 1 sctdr does not contain valid transmit data (initial value) [setting conditions] (1) tdre is set to 1 when the chip is reset or enters standby mode. (2) the te bit in the serial control register (scscr) is cleared to 0. (3) sctdr contents are loaded into sctsr, so new data can be written in sctdr.
rev. 5.00, 09/03, page 441 of 760 bit 6?receive data register full (rdrf): indicates that scrdr contains received data. bit 6: rdrf description 0 scrdr does not contain valid receive data (initial value) [clearing conditions] (1) rdrf is cleared to 0 when the chip is reset or enters standby mode. (2) software reads rdrf after it has been set to 1, then writes 0 in rdrf. 1 scrdr contains valid receive data [setting condition] rdrf is set to 1 when serial data is received normally and transferred from scrsr to scrdr. note: scrdr and rdrf are not affected by detection of receive errors or by clearing of the re bit to 0 in the serial control register. they retain their previous contents. if rdrf is still set to 1 when reception of the next data ends, an overrun error (orer) occurs and the receive data is lost. bit 5?overrun error (orer): indicates that data reception aborted due to an overrun error. bit 5: orer description 0 receiving is in progress or has ended normally * 1 (initial value) [clearing conditions] (1) orer is cleared to 0 when the chip is reset or enters standby mode. (2) when software reads orer after it has been set to 1, then writes 0 to orer. 1 a receive overrun error occurred * 2 [setting condition] orer is set to 1 if reception of the next serial data ends when rdrf is set to 1. notes: 1. clearing the re bit to 0 in the serial control register does not affect the orer bit, which retains its previous value. 2. scrdr continues to hold the data received before the overrun error, so subsequent receive data is lost. serial receiving cannot continue while orer is set to 1. in synchronous mode, serial transmitting is also disabled.
rev. 5.00, 09/03, page 442 of 760 bit 4?framing error (fer): indicates that data reception aborted due to a framing error in asynchronous mode. bit 4: fer description 0 receiving is in progress or has ended normally * 1 (initial value) [clearing conditions] (1) fer is cleared to 0 when the chip is reset or enters standby mode. (2) when software reads fer after it has been set to 1, then writes 0 to fer. 1 a receive framing error occurred [setting condition] fer is set to 1 if the stop bit at the end of receive data is checked and found to be 0. * 2 notes: 1. clearing the re bit to 0 in the serial control register does not affect the fer bit, which retains its previous value. 2. when the stop bit length is two bits, only the first bit is checked. the second stop bit is not checked. when a framing error occurs, the sci transfers the receive data into scrdr but does not set rdrf. serial receiving cannot continue while fer is set to 1. in synchronous mode, serial transmitting is also disabled. bit 3?parity error (per): indicates that data reception (with parity) aborted due to a parity error in asynchronous mode. bit 3: per description 0 receiving is in progress or has ended normally * 1 (initial value) [clearing conditions] (1) per is cleared to 0 when the chip is reset or enters standby mode. (2) when software reads per after it has been set to 1, then writes 0 to per. 1 a receive parity error occurred * 2 [setting condition] per is set to 1 if the number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of the parity mode bit (o/ e ) in the serial mode register (scsmr). notes: 1. clearing the re bit to 0 in the serial control register does not affect the per bit, which retains its previous value. 2. when a parity error occurs, the sci transfers the receive data into scrdr but does not set rdrf. serial receiving cannot continue while per is set to 1. in synchronous mode, serial transmitting is also disabled.
rev. 5.00, 09/03, page 443 of 760 bit 2?transmit end (tend): indicates that when the last bit of a serial character was transmitted, sctdr did not contain valid data, so transmission has ended. tend is a read-only bit and cannot be written to. bit 2: tend description 0 transmission is in progress [clearing condition] tend is cleared to 0 when software reads tdre after it has been set to 1, then writes 0 to tdre. 1 end of transmission (initial value) [setting conditions] (1) tend is set to 1 when the chip is reset or enters standby mode. (2) when te is cleared to 0 in the serial control register (scscr). (3) if tdre is 1 when the last bit of a one-byte serial character is transmitted. bit 1?multiprocessor bit (mpb): stores the value of the multiprocessor bit in receive data when a multiprocessor format is selected for receiving in asynchronous mode. mpb is a read-only bit and cannot be written to. bit 1: mpb description 0 multiprocessor bit value in receive data is 0 * (initial value) 1 multiprocessor bit value in receive data is 1 note: * if re is cleared to 0 when a multiprocessor format is selected, mpb retains its previous value. bit 0?multiprocessor bit transfer (mpbt): stores the value of the multiprocessor bit added to transmit data when a multiprocessor format is selected for transmitting in asynchronous mode. the mpbt setting is ignored in synchronous mode, when a multiprocessor format is not selected, or when the sci is not transmitting. bit 0: mpbt description 0 multiprocessor bit value in transmit data is 0 (initial value) 1 multiprocessor bit value in transmit data is 1
rev. 5.00, 09/03, page 444 of 760 14.2.8 sc port control register (scpcr)/sc port data register (scpdr) the sc port control register (scpcr) and sc port data register (scpdr) control i/o and data for the port pins multiplexed with the serial communication interface (sci) pins. scpcr settings are used to perform i/o control, to enable data written in scpdr to be output to the txd pin, and input data to be read from the rxd pin, and to control serial transmission/reception breaks. it is also possible to read data on the sck pin, and write output data. scpcr bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scp7 md1 scp7 md0 scp6 md1 scp6 md0 scp5 md1 scp5 md0 scp4 md1 scp4 md0 scp3 md1 scp3 md0 scp2 md1 scp2 md0 scp1 md1 scp1 md0 scp0 md1 scp0 md0 initial value:1010100010001000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w scpdr bit:76543210 scp7dt scp6dt scp5dt scp4dt scp3dt scp2dt scp1dt scp0dt initial value:00000000 r/w: r r/w r/w r/w r/w r/w r/w r/w sci pin i/o and data control are performed by bits 3?0 of scpcr and bits 1 and 0 of scpdr. scpcr bits 3 and 2?serial clock port i/o (scp1md1, scp1md0): specify serial port sck pin i/o. when the sck pin is actually used as a port i/o pin, clear the c/ a bit in scsmr and bits cke1 and cke0 in scscr to 0. bit 3: scp1md1 bit 2: scp1md0 description 0 0 scp1dt bit value is not output to sck pin 0 1 scp1dt bit value is output to sck pin 1 0 sck pin value is read from scp1dt bit 1 1 (initial values: 1 and 0)
rev. 5.00, 09/03, page 445 of 760 scpdr bit 1?serial clock port data (scp1dt): specifies the serial port sck pin i/o data. input or output is specified by the scp1md1 and scp1md0 bits. in output mode, the value of the scp1dt bit is output to the sck pin. bit 1: scp1dt description 0 i/o data is low (initial value) 1 i/o data is high scpcr bits 1 and 0?serial port break i/o (scp0md1, scp0md0): specify the serial port txd pin output condition. when the txd pin is actually used as a port output pin and outputs the value set with the scp0dt bit, clear the te bit in scscr to 0. bit 1: scp0md1 bit 0: scp0md0 description 0 0 scp0dt bit value is not output to txd pin (initial value) 0 1 scp0dt bit value is output to txd pin scpdr bit 0?serial port break data (scp0dt): specifies the serial port rxd pin input data and txd pin output data. the txd pin output condition is specified by the scp0md1 and scp0md0 bits. when the txd pin is set to output mode, the value of the scp0dt bit is output to the txd pin. the rxd pin value is read from the scp0dt bit regardless of the values of the scp0md1 and scp0md0 bits, if re in scscr is set to 1. the initial value of this bit after a power-on reset is undefined. bit 0: scp0dt description 0 i/o data is low (initial value) 1 i/o data is high block diagrams of the sci i/o port pins are shown in figures 14.2, 14.3, and 14.4.
rev. 5.00, 09/03, page 446 of 760 14.2.9 bit rate register (scbrr) the bit rate register (scbrr) is an 8-bit register that, together with the baud rate generator clock source selected by the cks1 and cks0 bits in the serial mode register (scsmr), determines the serial transmit/receive bit rate. the cpu can always read and write to scbrr. scbrr is initialized to h'ff by a reset, and in module standby or standby mode. each channel has independent baud rate generator control, so different values can be set in two channels. bit:76543210 initial value:11111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the scbrr setting is calculated as follows: asynchronous mode: n = p 64 2 2n ? 1 b 10 6 ? 1 synchronous mode: n = p 8 2 2n ? 1 b 10 6 ? 1 b: bit rate (bits/s) n: scbrr setting for baud rate generator (0 n 255) p : operating frequency for peripheral modules (mhz) n: baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n, see table 14.3.) table 14.3 scsmr settings scsmr settings n clock source cks1 cks0 0p 00 1p /4 0 1 2p /16 1 0 3p /64 1 1 note: the bit rate error in asynchronous is given by the following formula: error ( % ) = ( p 10 6 (n + 1) b 64 2 2n ? 1 ) 100
rev. 5.00, 09/03, page 447 of 760 table 14.4 lists examples of scbrr settings in asynchronous mode, and table 14.5 lists examples of scbrr settings in synchronous mode. table 14.4 bit rates and scbrr settings in asynchronous mode p (mhz) 2 2.097152 2.4576 bit rate (bits/s) n n error ( % % % % ) n n error ( % % % % ) n n error ( % % % % ) 110 1 141 0.03 1 148 ?0.04 1 174 ?0.26 150 1 103 0.16 1 108 0.21 1 127 0.00 300 0 207 0.16 0 217 0.21 0 255 0.00 600 0 103 0.16 0 108 0.21 0 127 0.00 1200 0 51 0.16 0 54 ?0.70 0 63 0.00 2400 0 25 0.16 0 26 1.14 0 31 0.00 4800 0 12 0.16 0 13 ?2.48 0 15 0.00 9600 0 6 ?6.99 0 6 ?2.48 0 7 0.00 19200 0 2 8.51 0 2 13.78 0 3 0.00 31250 0 1 0.00 0 1 4.86 0 1 22.88 38400 0 1 ?18.62 0 1 ?14.67 0 1 0.00 p (mhz) 3 3.6864 4 bit rate (bits/s) n n error ( % % % % ) n n error ( % % % % ) n n error ( % % % % ) 110 1 212 0.03 2 64 0.70 2 70 0.03 150 1 155 0.16 1 191 0.00 1 207 0.16 300 1 77 0.16 1 95 0.00 1 103 0.16 600 0 155 0.16 0 191 0.00 0 207 0.16 1200 0 77 0.16 0 95 0.00 0 103 0.16 2400 0 38 0.16 0 47 0.00 0 51 0.16 4800 0 19 ?2.34 0 23 0.00 0 25 0.16 9600 0 9 ?2.34 0 11 0.00 0 12 0.16 19200 0 4 ?2.34 0 5 0.00 0 6 ?6.99 31250 0 2 0.00 ? ? ? 0 3 0.00 38400 ? ? ? 0 2 0.00 0 2 8.51
rev. 5.00, 09/03, page 448 of 760 p (mhz) 4.9152 5 6 bit rate (bits/s) n n error ( % % % % ) n n error ( % % % % ) n n error ( % % % % ) 110 2 86 0.31 2 88 ?0.25 2 106 ?0.44 150 1 255 0.00 2 64 0.16 2 77 0.16 300 1 127 0.00 1 129 0.16 1 155 0.16 600 0 255 0.00 1 64 0.16 1 77 0.16 1200 0 127 0.00 0 129 0.16 0 155 0.16 2400 0 63 0.00 0 64 0.16 0 77 0.16 4800 0 31 0.00 0 32 ?1.36 0 38 0.16 9600 0 15 0.00 0 15 1.73 0 19 ?2.34 19200 0 7 0.00 0 7 1.73 0 9 ?2.34 31250 0 4 ?1.70 0 4 0.00 0 5 0.00 38400 0 3 0.00 0 3 1.73 0 4 ?2.34 p (mhz) 6.144 7.3728 8 bit rate (bits/s) n n error ( % % % % ) n n error ( % % % % ) n n error ( % % % % ) 110 2 108 0.08 2 130 ?0.07 2 141 0.03 150 2 79 0.00 2 95 0.00 2 103 0.16 300 1 159 0.00 1 191 0.00 1 207 0.16 600 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 2.40 0 6 5.33 0 7 0.00 38400 0 4 0.00 0 5 0.00 0 6 ?6.99
rev. 5.00, 09/03, page 449 of 760 p (mhz) 14.7456 16 19.6608 20 bit rate (bits/s) n n error ( % % % % )n n error ( % % % % )n n error ( % % % % )n n error ( % % % % ) 110 3 64 0.70 3 70 0.03 3 86 0.31 3 88 ?0.25 150 2 191 0.00 2 207 0.16 2 255 0.00 3 64 0.16 300 2 95 0.00 2 103 0.16 2 127 0.00 2 129 0.16 600 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 1200 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 2400 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 4800 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 9600 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 19200 0 23 0.00 0 25 0.16 0 31 0.00 0 32 ?1.36 31250 0 14 ?1.70 0 15 0.00 0 19 ?1.70 0 19 0.00 38400 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 p (mhz) 24 24.576 28.7 30 bit rate (bits/s) n n error ( % % % % )n n error ( % % % % )n n error ( % % % % )n n error ( % % % % ) 110 3 106 ?0.44 3 108 0.08 3 126 0.31 3 132 0.13 150 3 77 0.16 3 79 0.00 3 92 0.46 3 97 ?0.35 300 2 155 0.16 2 159 0.00 2 186 ?0.08 2 194 0.16 600 2 77 0.16 2 79 0.00 2 92 0.46 2 97 ?0.35 1200 1 155 0.16 1 159 0.00 1 186 ?0.08 1 194 0.16 2400 1 77 0.16 1 79 0.00 1 92 0.46 1 97 ?0.35 4800 0 155 0.16 0 159 0.00 0 186 ?0.08 0 194 ?1.36 9600 0 77 0.16 0 79 0.00 0 92 0.46 0 97 ?0.35 19200 0 38 0.16 0 39 0.00 0 46 ?0.61 0 48 ?0.35 31250 0 23 0.00 0 24 ?1.70 0 28 ?1.03 0 29 0.00 38400 0 19 ?2.34 0 19 0.00 0 22 1.55 0 23 1.73
rev. 5.00, 09/03, page 450 of 760 table 14.5 bit rates and scbrr settings in synchronous mode p (mhz) 4 8 16 28.7 30 bit rate (bits/s) n n n n n n n n n n 110 ?????????? 250 2 249 3 124 3 249 ? ? ? ? 500 2 124 2 249 3 124 3 223 3 233 1k 1 249 2 124 2 249 3 111 3 116 2.5k 1 99 1 199 2 99 2 178 2 187 5k 0 199 1 99 1 199 2 89 2 93 10k 0 99 0 199 1 99 1 178 1 187 25k 0 390 790159171174 50k 0 19 0 39 0 79 0 143 0 149 100k 09019039071074 250k 0307015??029 500k 010307??014 1m 0 0 * 0 1 0 3 ???? 2m 0 0 * 0 1 ???? notes: settings with an error of 1 % or less are recommended. blank: no setting possible ?: setting possible, but error occurs * : continuous transmit/receive operation not possible
rev. 5.00, 09/03, page 451 of 760 table 14.6 indicates the maximum bit rates in asynchronous mode when the baud rate generator is used. tables 14.7 and 14.8 list the maximum rates for external clock input. table 14.6 maximum bit rates for various frequencies with baud rate generator (asynchronous mode) settings p (mhz) maximum bit rate (bits/s) n n 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 8 250000 0 0 9.8304 307200 0 0 12 375000 0 0 14.7456 460800 0 0 16 500000 0 0 19.6608 614400 0 0 20 625000 0 0 24 750000 0 0 24.576 768000 0 0 28.7 896875 0 0 30 937500 0 0
rev. 5.00, 09/03, page 452 of 760 table 14.7 maximum bit rates with external clock input (asynchronous mode) p (mhz) external input clock (mhz) maximum bit rate (bits/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 8 2.0000 125000 9.8304 2.4576 153600 12 3.0000 187500 14.7456 3.6864 230400 16 4.0000 250000 19.6608 4.9152 307200 20 5.0000 312500 24 6.0000 375000 24.576 6.1440 384000 28.7 7.1750 448436 30 7.5000 468750 table 14.8 maximum bit rates with external clock input (synchronous mode) p (mhz) external input clock (mhz) maximum bit rate (bits/s) 8 1.3333 1333333.3 16 2.6667 2666666.7 24 4.0000 4000000.0 28.7 4.7833 4783333.3 30 5.0000 5000000.0
rev. 5.00, 09/03, page 453 of 760 14.3 operation 14.3.1 overview for serial communication, the sci has an asynchronous mode in which characters are synchronized individually, and a synchronous mode in which communication is synchronized with clock pulses. asynchronous/synchronous mode and the transmission format are selected in the serial mode register (scsmr), as shown in table 14.9. the sci clock source is selected by the combination of the c/ a bit in the serial mode register (scsmr) and the cke1 and cke0 bits in the serial control register (scscr), as shown in table 14.10. asynchronous mode: ? data length is selectable: 7 or 8 bits. ? parity and multiprocessor bits are selectable. so is the stop bit length (1 or 2 bits). the combination of the preceding selections constitutes the communication format and character length. ? in receiving, it is possible to detect framing errors (fer), parity errors (per), overrun errors (orer) and breaks. ? an internal or external clock can be selected as the sci clock source. ? when an internal clock is selected, the sci operates using the on-chip baud rate generator, and can output a serial clock signal with a frequency matching the bit rate. ? when an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (the on-chip baud rate generator is not used.) synchronous mode: ? the transmission/reception format has a fixed 8-bit data length. ? in receiving, it is possible to detect overrun errors (orer). ? an internal or external clock can be selected as the sci clock source. ? when an internal clock is selected, the sci operates using the on-chip baud rate generator, and outputs a serial clock signal to external devices. ? when an external clock is selected, the sci operates on the input serial clock. the on-chip baud rate generator is not used.
rev. 5.00, 09/03, page 454 of 760 table 14.9 serial mode register settings and sci communication formats scsmr settings sci communication format bit 7 c/ a a a a bit 6 chr bit 5 pe bit 2 mp bit 3 stop mode data length parity bit multipro- cessor bit stop bit length 0 0 0 0 0 asynchronous 8-bit not set not set 1 bit 12 bits 10 set 1 bit 12 bits 1 0 0 7-bit not set 1 bit 12 bits 10 set 1 bit 12 bits 0 * 1 0 8-bit not set set 1 bit * 12 bits 1 * 0 7-bit 1 bit * 1 asynchronous (multiprocessor format) 2 bits 1 **** synchronous 8-bit not set none note: asterisks ( * ) indicate don?t care bits. table 14.10 scsmr and scscr settings and sci clock source selection scsmr scscr settings sci transmit/receive clock bit 7 c/ a a a a bit 1 cke1 bit 0 cke0 mode clock source sck pin function 0 0 0 internal sci does not use the sck pin 1 outputs a clock with frequency matching the bit rate 10 external 1 asynchronous mode inputs a clock with frequency 16 times the bit rate 1 0 0 internal outputs the synchronous clock 1 1 0 external inputs the synchronous clock 1 synchronous mode
rev. 5.00, 09/03, page 455 of 760 14.3.2 operation in asynchronous mode in asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. serial communication is synchronized one character at a time. the transmitting and receiving sections of the sci are independent, so full duplex communication is possible. the transmitter and receiver are both double buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. figure 14.5 shows the general format of asynchronous serial communication. in asynchronous serial communication, the communication line is normally held in the mark (high) state. the sci monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. one serial character consists of a start bit (low), data (lsb first; starting from the lowerest bit), parity bit (high or low), and stop bit (high), in that order. when receiving in asynchronous mode, the sci synchronizes at the falling edge of the start bit. the sci samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. receive data is latched at the center of each bit. 0d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 1 1 0/1 1 1 (lsb) (msb) serial data start bit 1 bit transmit/receive data 7 or 8 bits one unit of communication data (character or frame) idle (mark) state parity bit stop bit 1 or no bit 1 or 2 bits figure 14.5 example of data format in asynchronous communication (8-bit data with parity and two stop bits)
rev. 5.00, 09/03, page 456 of 760 transmit/receive formats: table 14.11 lists the 12 communication formats that can be selected in asynchronous mode. the format is selected by settings in the serial mode register (scsmr). table 14.11 serial communication formats (asynchronous mode) scsmr bits serial transmit/receive format and frame length chrpempstop1 23456789 10 11 12 0 0 0 0 start 8-bit data stop 0 0 0 1 start 8-bit data stop stop 0 1 0 0 start 8-bit data p stop 0 1 0 1 start 8-bit data p stop stop 1 0 0 0 start 7-bit data stop 1 0 0 1 start 7-bit data stop stop 1 1 0 0 start 7-bit data p stop 1 1 0 1 start 7-bit data p stop stop 0 ? 1 0 start 8-bit data mpb stop 0 ? 1 1 start 8-bit data mpb stop stop 1 ? 1 0 start 7-bit data mpb stop 1 ? 1 1 start 7-bit data mpb stop stop notes: ? : don?t care bits start: start bit stop: stop bit p: parity bit mpb: multiprocessor bit clock: an internal clock generated by the on-chip baud rate generator or an external clock input from the sck pin can be selected as the sci transmit/receive clock. the clock source is selected by the c/ a bit in the serial mode register (scsmr) and bits cke1 and cke0 in the serial control register (scscr) (table 14.10). when an external clock is input at the sck pin, it must have a frequency equal to 16 times the desired bit rate.
rev. 5.00, 09/03, page 457 of 760 when the sci operates on an internal clock, it can output a clock signal at the sck pin. the frequency of this output clock is equal to the bit rate. the phase is aligned as in figure 14.6 so that the rising edge of the clock occurs at the center of each transmit data bit. 0 d0 d1 d2 d3 d4d5 d6 d7 0/1 1 1 1 frame figure 14.6 output clock and serial data timing (asynchronous mode) transmitting and receiving data (sci initialization (asynchronous mode)): before transmitting or receiving, clear the te and re bits to 0 in the serial control register (scscr), then initialize the sci as follows. when changing the operation mode or communication format, always clear the te and re bits to 0 before following the procedure given below. clearing te to 0 sets tdre to 1 and initializes the transmit shift register (sctsr). clearing re to 0, however, does not initialize the rdrf, per, fer, and orer flags or receive data register (scrdr), which retain their previous contents. when an external clock is used, the clock should not be stopped during initialization or subsequent operation. sci operation becomes unreliable if the clock is stopped. figure 14.7 shows a sample flowchart for initializing the sci. the procedure for initializing the sci is: 1. select the clock source in the serial control register (scscr). leave rie, tie, teie, mpie, te, and re cleared to 0. if clock output is selected in asynchronous mode, clock output starts immediately after the setting is made in scscr. 2. select the communication format in the serial mode register (scsmr). 3. write the value corresponding to the bit rate in the bit rate register (scbrr) (not necessary if an external clock is used). 4. wait for at least the interval required to transmit or receive one bit, then set te or re in the serial control register (scscr) to 1. also set rie, tie, teie, and mpie as necessary. setting te or re enables the sci to use the txd or rxd pin. the initial state is the mark state when transmitting, or the idle state (waiting for a start bit) when receiving.
rev. 5.00, 09/03, page 458 of 760 initialization clear te and re bits in scscr to 0 select communication format in scsmr set value in scbrr set cke1 and cke0 bits in scscr (te and re bits are 0) wait set te and re bits in scscr to 1 and set rie, tie, teie, and mpie bits has a 1-bit interval elapsed? end no yes (1) (2) (3) (4) note: numbers in parentheses refer to steps in the preceding procedure description. figure 14.7 sample flowchart for sci initialization transmitting serial data (asynchronous mode): figure 14.8 shows a sample flowchart for transmitting serial data. the procedure for transmitting serial data is: 1. sci status check and transmit data write: read the serial status register (scssr), check that the tdre bit is 1, then write transmit data in the transmit data register (sctdr) and clear tdre to 0. 2. to continue transmitting serial data: read the tdre bit to check whether it is safe to write (if it reads 1); if so, write data in sctdr, then clear tdre to 0. 3. to output a break at the end of serial transmission: set the port sc data register (scpdr) and port sc control register (scpcr), then clear the te bit to 0 in the serial control register (scscr). for scpcr and scpdr settings, see section 14.2.8, sc port control register (scpcr)/sc port data register (scpdr).
rev. 5.00, 09/03, page 459 of 760 tdre = 1? write transmit data to sctdr and clear tdre bit in scssr to 0 all data transmitted? yes tend = 1? read tend bit in scssr break output? yes clear te bit in scscr to 0 end of transmission yes read tdre bit in scssr no no yes no no (1) (2) (3) start of transmission set scpdr and scpcr note: numbers in parentheses refer to steps in the preceding procedure description. figure 14.8 sample flowchart for transmitting serial data
rev. 5.00, 09/03, page 460 of 760 in transmitting serial data, the sci operates as follows: 1. the sci monitors the tdre bit in scssr. when tdre is cleared to 0, the sci recognizes that the transmit data register (sctdr) contains new data, and loads this data from sctdr into the transmit shift register (sctsr). 2. after loading the data from sctdr into sctsr, the sci sets the tdre bit to 1 and starts transmitting. if the transmit-data-empty interrupt enable bit (tie) is set to 1 in scscr, the sci requests a transmit-data-empty interrupt (txi) at this time. serial transmit data is transmitted in the following order from the txd pin: a. start bit: one 0 bit is output. b. transmit data: seven or eight bits of data are output, lsb first. c. parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit is output. formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. d. stop bit: one or two 1-bits (stop bits) are output. e. marking: output of 1-bits continues until the start bit of the next transmit data. 3. the sci checks the tdre bit when it outputs the stop bit. if tdre is 0, the sci loads new data from sctdr into sctsr, outputs the stop bit, then begins serial transmission of the next frame. if tdre is 1, the sci sets the tend bit to 1 in scssr, outputs the stop bit, then continues output of 1-bits (marking). if the transmit-end interrupt enable bit (teie) in scscr is set to 1, a transmit-end interrupt (tei) is requested.
rev. 5.00, 09/03, page 461 of 760 figure 14.9 shows an example of sci transmit operation in asynchronous mode. 01 1 1 0/1 0 1 tdre tend parity bit parity bit serial data start bit data stop bit start bit data stop bit idle (mark) state txi interrupt request generated tei interrupt request generated txi interrupt handler writes data to sctdr and clears tdre bit to 0 1 frame d 0 d 1 d 7 d 0 d 1 d 7 0/1 txi interrupt request generated figure 14.9 example of sci transmit operation in asynchronous mode (8-bit data with parity and one stop bit) receiving serial data (asynchronous mode): figure 14.10 shows a sample flowchart for receiving serial data. the procedure for receiving serial data after enabling the sci for reception is: 1. receive error handling and break detection: if a receive error occurs, read the orer, per and fer bits in scssr to identify the error. after executing the necessary error handling, clear orer, per and fer to 0. receiving cannot resume if orer, per or fer remains set to 1. when a framing error occurs, the rxd pin can be read to detect the break state. 2. sci status check and receive-data read: read the serial status register (scssr), check that rdrf is set to 1, then read receive data from the receive data register (scrdr) and clear rdrf to 0. the rxi interrupt can also be used to determine if the rdrf bit has changed from 0 to 1. 3. to continue receiving serial data: read the rdrf and scrdr bits and clear rdrf to 0 before the stop bit of the current frame is received.
rev. 5.00, 09/03, page 462 of 760 start of reception read orer, per, and fer bits in scssr all data received? end of reception no yes per fer orer = 1? rdrf = 1? yes yes clear re bit in scscr to 0 no no read rdrf bit in scssr error handling read receive data from scrdr and clear rdrf bit in scssr to 0 (1) (2) (3) note: numbers in parentheses refer to steps in the preceding procedure description. figure 14.10 sample flowchart for receiving serial data
rev. 5.00, 09/03, page 463 of 760 error handling orer = 1? overrun error handling fer = 1? yes break? no framing error handling per = 1? yes parity error handling clear orer, per, and fer bits in scssr to 0 end no no no yes yes clear re bit in scscr to 0 figure 14.10 sample flowchart for receiving serial data (cont)
rev. 5.00, 09/03, page 464 of 760 in receiving, the sci operates as follows: 1. the sci monitors the communication line. when it detects a start bit (0), the sci synchronizes internally and starts receiving. 2. receive data is shifted into scrsr in order from the lsb to the msb. 3. the parity bit and stop bit are received. after receiving these bits, the sci makes the following checks: a. parity check: the number of 1s in the receive data must match the even or odd parity setting of the o/ e bit in scsmr. b. stop bit check: the stop bit value must be 1. if there are two stop bits, only the first stop bit is checked. c. status check: rdrf must be 0 so that receive data can be loaded from scrsr into scrdr. if these checks all pass, the sci sets rdrf to 1 and stores the received data in scrdr. if one of the checks fails (receive error), the sci operates as indicated in table 14.12. note: when a receive error flag is set, further receiving is disabled. the rdrf bit is not set to 1. be sure to clear the error flags. 4. after setting rdrf to 1, if the receive-data-full interrupt enable bit (rie) is set to 1 in scscr, the sci requests a receive-data-full interrupt (rxi). if one of the error flags (orer, per, or fer) is set to 1 and the receive-data-full interrupt enable bit (rie) in scscr is also set to 1, the sci requests a receive-error interrupt (eri). table 14.12 receive error conditions and sci operation receive error abbreviation condition data transfer overrun error orer receiving of next data ends while rdrf is still set to 1 in scssr receive data not transferred from scrsr into scrdr framing error fer stop bit is 0 receive data transferred from scrsr into scrdr parity error per parity of receive data differs from even/odd parity setting in scsmr receive data transferred from scrsr into scrdr
rev. 5.00, 09/03, page 465 of 760 figure 14.11 shows an example of sci receive operation in asynchronous mode. rdrf fer eri interrupt request generated by framing error 1 frame rxi interrupt handler reads data and clears rdrf bit to 0 rxi interrupt request generated 01 1 1 0/1 0 1 parity bit parity bit serial data start bit data stop bit start bit data stop bit idle (mark) state d 0 d 1 d 7 d 0 d 1 d 7 0/1 figure 14.11 example of sci receive operation (8-bit data with parity and one stop bit) 14.3.3 multiprocessor communication the multiprocessor communication function enables several processors to share a single serial communication line. the processors communicate in asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). in multiprocessor communication, each receiving processor is addressed by a unique id. a serial communication cycle consists of an id-sending cycle that identifies the receiving processor, and a data-sending cycle. the multiprocessor bit distinguishes id-sending cycles from data-sending cycles. the transmitting processor starts by sending the id of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. when they receive data with the multiprocessor bit set to 1, receiving processors compare the data with their ids. the receiving processor with a matching id continues to receive further incoming data. processors with ids not matching the received data skip further incoming data until they again receive data with the multiprocessor bit set to 1. multiple processors can send and receive data in this way. figure 14.12 shows an example of communication among processors using the multiprocessor format.
rev. 5.00, 09/03, page 466 of 760 receiving station a (id = 01) (id = 02) (id = 03) (id = 04) receiving station b receiving station c serial communication line h01 haa (mpb = 0) (mpb = 1) id transmit cycle: specifies receiving station serial data transmitting station receiving station d data transmit cycle: data transmission to receiving station specified by id mpb: multiprocessor bit figure 14.12 communication among processors using multiprocessor format (sending data h'aa to receiving processor a) communication formats: four formats are available. parity-bit settings are ignored when the multiprocessor format is selected. for details see table 14.11. clock: see the description in the asynchronous mode section. transmitting multiprocessor serial data: figure 14.13 shows a sample flowchart for transmitting multiprocessor serial data. the procedure for transmitting multiprocessor serial data is: 1. sci status check and transmit data write: read the serial status register (scssr), check that the tdre bit is 1, then write transmit data in the transmit data register (sctdr). also set mpbt (multiprocessor bit transfer) to 0 or 1 in scssr. finally, clear tdre to 0. 2. to continue transmitting serial data: read the tdre bit to check whether it is safe to write (if it reads 1); if so, write data in sctdr, then clear tdre to 0. 3. to output a break at the end of serial transmission: set the port sc data register (scpdr) and port sc control register (scpcr), then clear the te bit to 0 in the serial control register (scscr). for scpcr and scpdr settings, see section 14.2.8, sc port control register (scpcr)/sc port data register (scpdr).
rev. 5.00, 09/03, page 467 of 760 tdre = 1? write transmit data to sctdr and set mpbt bit in scssr transmission ended? yes tend = 1? read tend bit in scssr clear tdre bit to 0 break output? yes clear te bit scscr to 0 end of transmission yes read tdre bit in scssr no no yes no no (1) (2) (3) start of transmission set scpdr and scpcr note: numbers in parentheses refer to steps in the preceding procedure description. figure 14.13 sample flowchart for transmitting multiprocessor serial data
rev. 5.00, 09/03, page 468 of 760 in transmitting serial data, the sci operates as follows: 1. the sci monitors the tdre bit in scssr. when tdre is cleared to 0 the sci recognizes that the transmit data register (sctdr) contains new data, and transfers this data from sctdr into the transmit shift register (sctsr). 2. after loading the data from sctdr into sctsr, the sci sets the tdre bit to 1 and starts transmitting. if the transmit-data-empty interrupt enable bit (tie) in scscr is set to 1, the sci requests a transmit-data-empty interrupt (txi) at this time. serial transmit data is transmitted in the following order from the txd pin: a. start bit: one 0-bit is output. b. transmit data: seven or eight bits are output, lsb first. c. multiprocessor bit: one multiprocessor bit (mpbt value) is output. d. stop bit: one or two 1-bits (stop bits) are output. e. marking: output of 1-bits continues until the start bit of the next transmit data. 3. the sci checks the tdre bit when it outputs the stop bit. if tdre is 0, the sci transfers data from sctdr into sctsr, outputs the stop bit, then begins serial transmission of the next frame. if tdre is 1, the sci sets the tend bit in scssr to 1, outputs the stop bit, then continues output of 1 bits in the mark state. if the transmit-end interrupt enable bit (teie) in scscr is set to 1, a transmit-end interrupt (tei) is requested at this time. figure 14.14 shows sci transmission with a multiprocessor format. tdre tend txi interrupt request generated tei interrupt request generated writes data to tdr with the txi interrupt processing routine and clears tdre bit to 0 1 frame 01 1 1 0/1 0 1 multi- processor bit serial data start bit data stop bit start bit data stop bit idle (mark) state d 0 d 1 d 7 d 0 d 1 d 7 0/1 multi- processor bit txi interrupt request generated figure 14.14 example of sci multiprocessor transmit operation (8-bit data with multiprocessor bit and one stop bit)
rev. 5.00, 09/03, page 469 of 760 receiving multiprocessor serial data: figure 14.15 shows a sample flowchart for receiving multiprocessor serial data. the procedure for receiving multiprocessor serial data is: 1. id receive cycle: set the mpie bit in the serial control register (scscr) to 1. 2. sci status check and compare to id reception: read the serial status register (scssr), check that rdrf is set to 1, then read data from the receive data register (scrdr) and compare with the processor?s own id. if the id does not match the receive data, set mpie to 1 again and clear rdrf to 0. if the id matches the receive data, clear rdrf to 0. 3. sci status check and data receiving: read scssr, check that rdrf is set to 1, then read data from the receive data register (scrdr). 4. receive error handling and break detection: if a receive error occurs, read the orer and fer bits in scssr to identify the error. after executing the necessary error handling, clear both orer and fer to 0. receiving cannot resume if orer or fer remain set to 1. when a framing error occurs, the rxd pin can be read to detect the break state.
rev. 5.00, 09/03, page 470 of 760 rdrf = 1? fer = 1 or orer = 1? rdrf = 1? all data received? no end of reception yes set mpie bit in scscr to 1 read rdrf bit in scssr clear re bit in scscr to 0 no no read orer and fer bits in scssr fer = 1 or orer = 1? read rdrf bit in scssr read receive data from scrdr is id the stations id? yes read orer and fer bits in sscsr no error handling yes yes yes no start of reception no yes read receive data from scrdr (1) (2) (4) (3) note: numbers in parentheses refer to steps in the preceding procedure description. figure 14.15 sample flowchart for receiving multiprocessor serial data
rev. 5.00, 09/03, page 471 of 760 orer = 1? break? yes framing error handling yes error handling overrun error handling yes fer = 1? clear orer and fer bits in scssr to 0 end no no no clear re bit in scscr to 0 figure 14.15 sample flowchart for receiving multiprocessor serial data (cont)
rev. 5.00, 09/03, page 472 of 760 figure 14.16 shows an example of sci receive operation using a multiprocessor format. rdrf mpie rdr value id1 rxi interrupt request (multiprocessor interrupt) generated, mpie = 0 example: own id does not match data rxi interrupt handler reads rdr data and clears rdrf bit to 0 id is not stations id, so mpie bit is set to 1 again no rxi interrupt generated; rdr state is maintained 01 1 1 10 1 stop bit mpb serial data start bit data (id1) data (data 1) start bit mpb stop bit idle (mark) state d 0 d 1 d 7 d 0 d 1 d 7 0 figure 14.16 example of sci receive operation (8-bit data with multiprocessor bit and one stop bit)
rev. 5.00, 09/03, page 473 of 760 rdrf mpie rdr value example: own id matches data id1 id2 data2 01 1 1 10 1 mpb mpb serial data start bit data (id2) data (data 2) stop bit start bit stop bit idle (mark) state d 0 d 1 d 7 d 0 d 1 d 7 0 rxi interrupt request (multiprocessor interrupt) generated, mpie = 0 rxi interrupt handler reads rdr data and clears rdrf bit to 0 id is that of station, so reception continues unchanged and data is received by rxi interrupt handler mpie bit set to 1 again figure 14.16 example of sci receive operation (cont) (8-bit data with multiprocessor bit and one stop bit)
rev. 5.00, 09/03, page 474 of 760 14.3.4 synchronous operation in synchronous mode, the sci transmits and receives data in synchronization with clock pulses. this mode is suitable for high-speed serial communication. the sci transmitter and receiver are independent, so full-duplex communication is possible while sharing the same clock. the transmitter and receiver are also double buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. figure 14.17 shows the general format in synchronous serial communication. bit 0 dont care dont care bit 1 bit 2 bit 3 bit 4bit 5 bit 6 bit 7 lsb msb serial clock serial data ** one unit of communication data (character or frame) note: * high except in continuous transmitting or receiving figure 14.17 data format in synchronous communication in synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. data is guaranteed valid at the rising edge of the serial clock. in each character, the serial data bits are transmitted in order from the lsb (first) to the msb (last). after output of the msb, the communication line remains in the state of the msb. in synchronous mode, the sci transmits or receives data by synchronizing with the falling edge of the serial clock. communication format: the data length is fixed at eight bits. no parity bit or multiprocessor bit can be added.
rev. 5.00, 09/03, page 475 of 760 clock: an internal clock generated by the on-chip baud rate generator or an external clock input from the sck pin can be selected as the sci transmit/receive clock. the clock source is selected by the c/ a bit in the serial mode register (scsmr) and bits cke1 and cke0 in the serial control register (scscr). see table 14.10. when the sci operates on an internal clock, it outputs the clock signal at the sck pin. eight clock pulses are output per transmitted or received character. when the sci is not transmitting or receiving, the clock signal remains in the high state. when only receiving, the sci receives in 2- character units, so a 16-pulse serial clock is output. to receive in 1-character units, select an external clock source. transmitting and receiving data sci initialization (synchronous mode): before transmitting, receiving, or changing the mode or communication format, the software must clear the te and re bits to 0 in the serial control register (scscr), then initialize the sci. clearing te to 0 sets tdre to 1 and initializes the transmit shift register (sctsr). clearing re to 0, however, does not initialize the rdrf, per, fer, and orer flags and receive data register (scrdr), which retain their previous contents. figure 14.18 shows a sample flowchart for initializing the sci. the procedure for initializing the sci is: 1. select the clock source in the serial control register (scscr). leave rie, tie, teie, mpie, te and re cleared to 0. 2. select transmit/receive format in the serial mode register (scsmr). 3. write the value corresponding to the bit rate in the bit rate register (scbrr) (not necessary if an external clock is used). 4. wait for at least the interval required to transmit or receive one bit, then set te or re in the serial control register (scscr) to 1. also set rie, tie, teie and mpie. setting te and re allows use of the txd and rxd pins.
rev. 5.00, 09/03, page 476 of 760 initialization clear te and re bits in scscr to 0 (1) has a 1-bit period elapsed? set te and re bits in scscr to 1 and set rie, tie, teie, and mpie bits set transmit/receive format in scsmr yes no set value in scbrr set rie, tie, teie, mpie, cke1, and cke0 bits in scscr (te and re are 0) end wait (2) (3) (4) note: numbers in parentheses refer to steps in the preceding procedure description. figure 14.18 sample flowchart for sci initialization transmitting serial data (synchronous mode): figure 14.19 shows a sample flowchart for transmitting serial data. the procedure for transmitting serial data is: 1. sci status check and transmit data write: read the serial status register (scssr), check that the tdre bit is 1, then write transmit data in the transmit data register (sctdr) and clear tdre to 0. 2. to continue transmitting serial data: read the tdre bit to check whether it is safe to write (if it reads 1); if so, write data in sctdr, then clear tdre to 0.
rev. 5.00, 09/03, page 477 of 760 start of transmission read tdre bit in scssr all data transmitted? yes no end of transmission (1) (2) tdre = 1? write transmit data to sctdr and clear tdre bit in scssr to 0 yes no read tend bit in scssr tend = 1? yes no clear te bit in scscr to 0 note: numbers in parentheses refer to steps in the preceding procedure description. figure 14.19 sample flowchart for transmitting serial data
rev. 5.00, 09/03, page 478 of 760 in transmitting serial data, the sci operates as follows: 1. the sci monitors the tdre bit in scssr. when tdre is cleared to 0 the sci recognizes that the transmit data register (sctdr) contains new data and loads this data from sctdr into the transmit shift register (sctsr). 2. after loading the data from sctdr into sctsr, the sci sets the tdre bit to 1 and starts transmitting. if the transmit-data-empty interrupt enable bit (tie) in scscr is set to 1, the sci requests a transmit-data-empty interrupt (txi) at this time. if clock output mode is selected, the sci outputs eight synchronous clock pulses. if an external clock source is selected, the sci outputs data in synchronization with the input clock. data is output from the txd pin in order from the lsb (bit 0) to the msb (bit 7). 3. the sci checks the tdre bit when it outputs the msb (bit 7). if tdre is 0, the sci loads data from sctdr into sctsr, then begins serial transmission of the next frame. if tdre is 1, the sci sets the tend bit in scssr to 1, transmits the msb, then holds the transmit data pin (txd) in the msb state. if the transmit-end interrupt enable bit (teie) in scscr is set to 1, a transmit-end interrupt (tei) is requested at this time. 4. after the end of serial transmission, the sck pin is held in the high state. figure 14.20 shows an example of sci transmit operation. bit 0 bit 1 bit 7 bit 0 bit 1 bit 6 serial clock serial data transfer direction bit 7 txi interrupt handler writes data to tdr and clears tdre bit to 0 1 frame tdre tend lsb msb txi interrupt request generated txi interrupt request generated tei interrupt request generated figure 14.20 example of sci transmit operation
rev. 5.00, 09/03, page 479 of 760 receiving serial data (synchronous mode): figure 14.21 shows a sample flowchart for receiving serial data. when switching from asynchronous mode to synchronous mode, make sure that orer, per, and fer are cleared to 0. if per or fer is set to 1, the rdrf bit will not be set and both transmitting and receiving will be disabled. the procedure for receiving serial data is: 1. receive error handling: if a receive error occurs, read the orer bit in scssr to identify the error. after executing the necessary error handling, clear orer to 0. transmitting/receiving cannot resume if orer remains set to 1. 2. sci status check and receive data read: read the serial status register (scssr), check that rdrf is set to 1, then read receive data from the receive data register (scrdr) and clear rdrf to 0. the rxi interrupt can also be used to determine if the rdrf bit has changed from 0 to 1. 3. to continue receiving serial data: read scrdr, and clear rdrf to 0 before the msb (bit 7) of the current frame is received.
rev. 5.00, 09/03, page 480 of 760 read orer bit in scssr all data received? end of reception no yes orer = 1? rdrf = 1? yes clear re bit in scscr to 0 no no read rdrf bit in scssr (3) (2) yes error handling (1) read receive data from scrdr and clear rdrf bit in scssr to 0 start of reception note: numbers in parentheses refer to steps in the preceding procedure description. figure 14.21 sample flowchart for receiving serial data
rev. 5.00, 09/03, page 481 of 760 error handling end orer = 1? no clear orer bit in scssr to 0 yes overrun error handling figure 14.21 sample flowchart for receiving serial data (cont) in receiving, the sci operates as follows: 1. the sci synchronizes with serial clock input or output and initializes internally. 2. receive data is shifted into scrsr in order from the lsb to the msb. after receiving the data, the sci checks that rdrf is 0 so that receive data can be loaded from scrsr into scrdr. if this check is passed, the sci sets rdrf to 1 and stores the received data in scrdr. if the check is not passed (receive error), the sci operates as indicated in table 14.12. this state prevents further transmission or reception. while receiving, the rdrf bit is not set to 1. be sure to clear the error flag. 3. after setting rdrf to 1, if the receive-data-full interrupt enable bit (rie) is set to 1 in scscr, the sci requests a receive-data-full interrupt (rxi). if the orer bit is set to 1 and the receive-data-full interrupt enable bit (rie) in scscr is also set to 1, the sci requests a receive-error interrupt (eri). figure 14.22 shows an example of sci receive operation.
rev. 5.00, 09/03, page 482 of 760 bit 7 bit 0 bit 7 bit 0 bit 1 bit 6 serial clock serial data transfer direction bit 7 rxi interrupt handler reads data and clears rdrf bit to 0 1 frame rxi interrupt request generated rxi interrupt request generated eri interrupt request generated by overrun error rdrf orer figure 14.22 example of sci receive operation transmitting and receiving serial data simultaneously (synchronous mode): figure 14.23 shows a sample flowchart for transmitting and receiving serial data simultaneously. the procedure for setting the sci to transmit and receive serial data simultaneously is: 1. sci status check and transmit data write: read the serial status register (scssr), check that the tdre bit is 1, then write transmit data in the transmit data register (sctdr) and clear tdre to 0. the txi interrupt can also be used to determine if the tdre bit has changed from 0 to 1. 2. receive error handling: if a receive error occurs, read the orer bit in scssr to identify the error. after executing the necessary error handling, clear orer to 0. transmitting/receiving cannot resume if orer remains set to 1. 3. sci status check and receive data read: read the serial status register (scssr), check that rdrf is set to 1, then read receive data from the receive data register (scrdr) and clear rdrf to 0. the rxi interrupt can also be used to determine if the rdrf bit has changed from 0 to 1. 4. to continue transmitting and receiving serial data: read the rdrf bit and scrdr, and clear rdrf to 0 before the msb (bit 7) of the current frame is received. also read the tdre bit to check whether it is safe to write (if it reads 1); if so, write data in sctdr, then clear tdre to 0 before the msb (bit 7) of the current frame is transmitted.
rev. 5.00, 09/03, page 483 of 760 start of transmission/reception read tdre bit in scssr all data transmitted/received? end of transmission/reception (1) no yes tdre = 1? write transmit data to sctdr and clear tdre bit in scssr to 0 rdrf = 1? no yes yes no read orer bit in scssr error processing (2) orer = 1? no read rdrf bit in scssr (4) yes (3) read receive data from scrdr and clear rdrf bit in scssr to 0 clear te and re bits in scscr to 0 notes: 1. 2. numbers in parentheses refer to steps in the preceding procedure description. in switching from transmitting or receiving to simultaneous transmitting and receiving, clear both te and re to 0, then set both te and re to 1 simultaneously. figure 14.23 sample flowchart for transmitting/receiving serial data
rev. 5.00, 09/03, page 484 of 760 14.4 sci interrupts the sci has four interrupt sources transmit-end (tei), receive-error (eri), receive-data-full (rxi), and transmit-data-empty (txi). table 14.13 lists the interrupt sources and indicates their priority. these interrupts can be enabled and disabled by the tie, rie, and teie bits in the serial control register (scscr). each interrupt request is sent separately to the interrupt controller. txi is requested when the tdre bit in scssr is set to 1. rxi is requested when the rdrf bit in scssr is set to 1. eri is requested when the orer, per, or fer bit in scssr is set to 1. tei is requested when the tend bit in scssr is set to 1. where the txi interrupt indicates that transmit data writing is enabled, the tei interrupt indicates that the transmit operation is complete. table 14.13 sci interrupt sources interrupt source description priority when reset is cleared eri receive error (orer, per, or fer) high rxi receive data full (rdrf) txi transmit data empty (tdre) tei transmit end (tend) low see section 4, exception handling, for priorities and the relationship to non-sci interrupts.
rev. 5.00, 09/03, page 485 of 760 14.5 usage notes note the following points when using the sci. sctdr writing and tdre flag: the tdre bit in the serial status register (scssr) is a status flag indicating loading of transmit data from sctdr into sctsr. the sci sets tdre to 1 when it transfers data from sctdr to sctsr. data can be written to sctdr regardless of the tdre bit state. if new data is written in sctdr when tdre is 0, however, the old data stored in sctdr will be lost because the data has not yet been transferred to sctsr. before writing transmit data to sctdr, be sure to check that tdre is set to 1. simultaneous multiple receive errors: table 14.14 indicates the state of scssr status flags when multiple receive errors occur simultaneously. when an overrun error occurs, the scrsr contents cannot be transferred to scrdr, so receive data is lost. table 14.14 scssr status flags and transfer of receive data scssr status flags receive error status rdrf orer fer per receive data transfe r scrsr scrdr overrun error 1 1 0 0 x framing error 0 0 1 0 o parity error 0 0 0 1 o overrun error + framing error 1 1 1 0 x overrun error + parity error 1 1 0 1 x framing error + parity error 0 0 1 1 o overrun error + framing error + parity error 1 1 1 1 x x: receive data is not transferred from scrsr to scrdr. o: receive data is transferred from scrsr to scrdr. break detection and processing: break signals can be detected by reading the rxd pin directly when a framing error (fer) is detected. in the break state, the input from the rxd pin consists of all 0s, so fer is set and the parity error flag (per) may also be set. in the break state, the sci receiver continues to operate, so if the fer bit is cleared to 0, it will be set to 1 again. sending a break signal: the txd pin i/o condition and level can be determined by means of the scp0dt bit in the port sc data register (scpdr) and bits scp0md0 and scp0md1 in the port sc control register (scpcr). this feature can be used to send breaks. to send a break during serial transmission, clear the scp0dt bit to 0 (designating low level), then clear the te bit to 0 (halting transmission). when the te bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, and 0 is output from the txd pin.
rev. 5.00, 09/03, page 486 of 760 tend flag and te bit processing: the tend flag is set to 1 during transmission of the stop bit of the last data. consequently, if the te bit is cleared to 0 immediately after setting of the tend flag has been confirmed, the stop bit will be in the process of transmission and will not be transmitted normally. therefore, the te bit should not be cleared to 0 for at least 0.5 serial clock cycles (or 1.5 cycles if two stop bits are used) after setting of the tend flag is confirmed. receive error flags and transmitter operation (synchronous mode only): when a receive error flag (orer, per, or fer) is set to 1, the sci will not start transmitting even if tdre is set to 1. be sure to clear the receive error flags to 0 before starting to transmit. note that clearing re to 0 does not clear the receive error flags. receive data sampling timing and receive margin in asynchronous mode: in asynchronous mode, the sci operates on a base clock of 16 times the transfer rate frequency. in receiving, the sci synchronizes internally with the falling edge of the start bit, which it samples on the base clock. receive data is latched at the rising edge of the eighth base clock pulse (figure 14.24). 0123456 7891011121314150123456 789101112131415012345 base clock receive data (rxd) synchro- nization sampling timing data sampling timing 8 clocks 16 clocks start bit ? 7.5 clocks +7.5 clocks d0 d1 figure 14.24 receive data sampling timing in asynchronous mode
rev. 5.00, 09/03, page 487 of 760 the receive margin in asynchronous mode can therefore be expressed as in equation 1. equation 1: m = 0.5 ? 1 2n d ? 0.5 n ? (l ? 0.5)f ? (1 + f) 100% where: m = receive margin ( % ) n = ratio of clock frequency to bit rate (n = 16) d = clock duty cycle (d = 0 to 1.0) l = frame length (l = 9 to 12) f = absolute deviation of clock frequency from equation 1, if f = 0 and d = 0.5, the receive margin is 46.875%, as in equation 2. equation 2: m = (0.5 ? 1/(2 16)) 100 % = 46.875 % this is a theoretical value. a reasonable margin to allow in system designs is 20% to 30%. notes on synchronous external clock mode: ? do not set te = re = 1 until at least four clocks after external clock sck has changed from 0 to 1. ? set te = re = 1 only when external clock sck is 1. ? when receiving, rdrf is set to 1 when re is set to zero 2.5?3.5 clocks after the rising edge of the sck input of the d7 bit in rxd, but data cannot be copied to scrdr. note on synchronous internal clock mode: when receiving, rdrf is set to 1 when re is cleared to zero 1.5 clocks after the rising edge of the sck output of the d7 bit in rxd, but data cannot be copied to scrdr.
rev. 5.00, 09/03, page 488 of 760
rev. 5.00, 09/03, page 489 of 760 section 15 smart card interface 15.1 overview as an added serial communications interface function, the sci supports an ic card (smart card) interface that conforms to the data transfer protocol (asynchronous half-duplex character transmission protocol) of the iso/iec7816-3 (identification card) standard. register settings are used to switch between the normal serial communication interface and the smart card interface. 15.1.1 features the smart card interface has the following features: ? asynchronous mode ? data length: 8 bits ? parity bit generation and check ? receive mode error signal detection (parity error) ? transmit mode error signal detection and automatic re-transmission of data ? supports both direct convention and inverse convention ? bit rate can be selected using on-chip baud rate generator. ? three types of interrupts: transmit-data-empty, receive-data-full, and communication-error interrupts are requested independently.
rev. 5.00, 09/03, page 490 of 760 15.1.2 block diagram figure 15.1 shows a block diagram of the smart card interface. rxd txd sck sci scbrr scscr scsmr sctdr sctsr scrdr scrsr scscmr scssr parity generation parity check clock external clock module data bus internal data bus p p /4 p /16 p /64 txi rxi eri bus interface baud rate generator transmit/ receive control scscmr: scrsr: scrdr: sctsr: sctdr: scsmr: scscr: scssr: scbrr: legend smart card mode register receive shift register receive data register transmit shift register transmit data register serial mode register serial control register serial status register bit rate register figure 15.1 block diagram of smart card interface
rev. 5.00, 09/03, page 491 of 760 15.1.3 pin configuration table 15.1 summarizes the smart card interface pins. table 15.1 smart card interface pins pin name abbreviation i/o function serial clock pin sck0 output clock output receive data pin rxd0 input receive data input transmit data pin txd0 output transmit data output 15.1.4 smart card interface registers table 15.2 summarizes the registers used by the smart card interface. the scsmr, scbrr, scscr, sctdr, and scrdr registers are the same as for the normal sci function. they are described in section 14, serial communication interface (sci). table 15.2 registers name abbreviation r/w initial value * 3 address access size serial mode register scsmr r/w h'00 h'fffffe80 8 bit rate register scbrr r/w h'ff h'fffffe82 8 serial control register scscr r/w h'00 h'fffffe84 8 transmit data register sctdr r/w h'ff h'fffffe86 8 serial status register scssr r/(w) * 1 h'84 h'fffffe88 8 receive data register scrdr r h'00 h'fffffe8a 8 smart card mode register scscmr r/w h'00 * 2 h'fffffe8c 8 notes: 1. only 0 can be written, to clear the flags. 2. bits 0, 2, and 3 are cleared. the value of the other bits is undefined. 3. initialized by a power-on or manual reset.
rev. 5.00, 09/03, page 492 of 760 15.2 register descriptions this section describes the registers added for the smart card interface and the bits whose functions are changed. 15.2.1 smart card mode register (scscmr) the smart card mode register (scscmr) is an 8-bit readable/writable register that selects smart card interface functions. scscmr bits 0, 2, and 3 are initialized to h'00 by a reset and in standby mode. bit:76543210 ????sdirsinv?smif initial value:???? 0 0 ? 0 r/w:rrrrr/wr/wrr/w bits 7 to 4 and 1?reserved: these bits are always read as 0. the write value should always be 0. bit 3?smart card data transfer direction (sdir): selects the serial/parallel conversion format. bit 3: sdir description 0 contents of sctdr are transferred lsb-first, and receive data is stored in scrdr lsb-first (initial value) 1 contents of sctdr are transferred msb-first, and receive data is stored in scrdr msb-first bit 2?smart card data inversion (sinv): specifies whether to invert the logic level of the data. this function is used in combination with bit 3 for transmitting and receiving with an inverse convention card. sinv does not affect the logic level of the parity bit. see section 15.3.4, register settings, for information on how parity is set. bit 2: sinv description 0 contents of sctdr are transferred unchanged, and receive data is stored in scrdr unchanged (initial value) 1 contents of sctdr are inverted before transfer, and receive data is inverted before storage in scrdr
rev. 5.00, 09/03, page 493 of 760 bit 0?smart card interface mode select (smif): enables the smart card interface function. bit 0 : smif description 0 smart card interface function disabled (initial value) 1 smart card interface function enabled 15.2.2 serial status register (scssr) in smart card interface mode, the function of scssr bit 4 is changed. the setting conditions for bit 2, the tend bit, are also changed. bit:76543210 tdre rdrf orer fer/ers per tend mpb mpbt initial value:10000100 r/w: r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * rrr/w note: only 0 can be written, to clear the flag. bit 7?transmit data register empty (tdre) bit 6?receive data register full (rdre) bit 5?overrun error (orer) these bits have the same function as in the ordinary sci. see section 14, serial communication interface (sci), for more information. bit 4?error signal status (ers): in the smart card interface mode, bit 4 indicates the state of the error signal returned from the receiving side during transmission. the smart card interface cannot detect framing errors. bit 4: ers description 0 receiving ended normally with no error signal (initial value) [clearing conditions] (1) by a reset or in standby mode (2) cleared by reading ers when ers = 1, then writing 0 to ers 1 an error signal indicating a parity error was transmitted from the receiving side [setting condition] if the error signal sampled is low note: the ers flag maintains its state even when the te bit in scscr is cleared to 0.
rev. 5.00, 09/03, page 494 of 760 bits 3 to 0: these bits have the same function as in the ordinary sci. see section 14, serial communication interface (sci), for more information. the setting conditions for bit 2, the transmit end bit (tend), are changed as follows. bit 2: tend description 0 transmission is in progress [clearing condition] cleared by reading tdre when tdre = 1, then writing 0 to tdre 1 end of transmission (initial value) [setting conditions] (1) the chip is reset or enters standby mode, (2) the te bit in scscr is 0 and the fer/ers bit is also 0, (3) the c/ a bit in scsmr is 0, and tdre = 1 and fer/ers = 0 (normal transmission) 2.5 etu after a one-byte serial character is transmitted, or (4) the c/ a bit in scsmr is 1, and tdre = 1 and fer/ers = 0 (normal transmission) 1.0 etu after a one-byte serial character is transmitted. note: etu: elementary time unit (time for transfer of 1 bit). 15.3 operation 15.3.1 overview the primary functions of the smart card interface are described below. 1. each frame consists of 8-bit data and 1 parity bit. 2. during transmission, the card leaves a guard time of at least 2 etu (elementary time units: time for transfer of 1 bit) from the end of the parity bit to the start of the next frame. 3. during reception, the card outputs an error signal low level for 1 etu after 10.5 etu has elapsed from the start bit if a parity error was detected. 4. during transmission, it automatically transmits the same data after allowing at least 2 etu from the time the error signal is sampled. 5. only start-stop type asynchronous communication functions are supported; no synchronous communication functions are available.
rev. 5.00, 09/03, page 495 of 760 15.3.2 pin connections figure 15.2 shows the pin connection diagram for the smart card interface. during communication with an ic card, transmission and reception are both carried out over the same data transfer line, so connect the txd and rxd pins on the chip. pull up the data transfer line to the power supply v cc side with a register. when using the clock generated by the smart card interface on an ic card, input the sck pin output to the ic card?s clk pin. this connection is not necessary when the internal clock is used on the ic card. use the chip?s port output as the reset signal. apart from these pins, power and ground pin connections are usually also required. note: when the ic card is not connected and both re and te are set to 1, closed communication is possible and auto-diagnosis can be performed. lsi txd io clk rst rxd sck px (port) clock line data line reset line ic card connected device v cc figure 15.2 pin connection diagram for smart card interface
rev. 5.00, 09/03, page 496 of 760 15.3.3 data format figure 15.3 shows the data format for the smart card interface. in this mode, parity is checked every frame while receiving and error signals sent to the transmitting side whenever an error is detected so that data can be re-transmitted. during transmission, error signals are sampled and data re-transmitted whenever an error signal is detected. ds d0 d1 d2 d3 d4d5 d6 d7 dp with no parity error transmitting station output ds d0 d1 d2 d3 d4d5 d6 d7 dp de with parity error transmitting station output receiving station output ds: d0 - d7: dp: de: start bit data bits parity bit error signal figure 15.3 data format for smart card interface the operating sequence is: 1. the data line is high-impedance when not in use and is fixed high with a pull-up register. 2. the transmitting side starts one frame of data transmission. the data frame starts with a start bit (ds, low level). the start bit is followed by eight data bits (d0?d7) and a parity bit (dp). 3. on the smart card interface, the data line returns to high-impedance after this. the data line is pulled high with a pull-up register. 4. the receiving side checks parity. when the data is received normally with no parity errors, the receiving side then waits to receive the next data. when a parity error occurs, the receiving side outputs an error signal (de, low level) and requests re-transfer of data. the receiving station returns the signal line to high-impedance after outputting the error signal for a specified period. the signal line is pulled high with a pull-up register.
rev. 5.00, 09/03, page 497 of 760 5. the transmitting side transmits the next frame of data unless it receives an error signal. if it does receive an error signal, it returns to step 2 to re-transmit the erroneous data. 15.3.4 register settings table 15.3 shows the bit map of the registers that the smart card interface uses. bits shown as 1 or 0 must be set to the indicated value. the settings for the other bits are described below. table 15.3 register settings for smart card interface register address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scsmr h'fffffe80 c/ a 01o/ e 1 0 cks1 cks0 scbrr h'fffffe82 brr7 brr6 brr5 brr4 brr3 brr2 brr1 brr0 scscr h'fffffe84 tie rie te re 0 0 cke1 cke0 sctdr h'fffffe86 tdr7 tdr6 tdr5 tdr4 tdr3 tdr2 tdr1 tdr0 scssr h'fffffe88 tdre rdrf orer fer/ ers per tend 0 0 scrdr h'fffffe8a rdr7 rdr6 rdr5 rdr4 rdr3 rdr2 rdr1 rdr0 scscmr h'fffffe8c ? ???sdirsinv?smif note: dashes indicate unused bits. 1. setting the serial mode register (scsmr): the c/ a bit selects the setting timing of the tend flag, and selects the clock output state in combination with bits cke1 and cke0 in the serial control register (scscr). clear the o/ e bit to 0 if the ic card uses the direct convention, and set it to 1 if the card uses the inverse convention. select the on-chip baud rate generator clock source with the cks1 and cks0 bits (see section 15.3.5, clock). 2. setting the bit rate register (scbrr): set the bit rate. see section 15.3.5, clock, to see how to calculate the set value. 3. setting the serial control register (scscr): the tie, rie, te and re bits function as they do for the ordinary sci. see section 14, serial communication interface (sci), for more information. the cke0 bit specifies the clock output. when no clock is output, clear cke0 to 0; when a clock is output, set cke0 to 1. 4. setting the smart card mode register (scscmr): the sdir and sinv bits are both cleared to 0 for ic cards that use the direct convention, and both set to 1 when the inverse convention is used. the smif bit is set to 1 for the smart card interface. figure 15.4 shows sample waveforms for register settings of the two types of ic cards (direct convention and inverse convention) and their start characters. in the direct convention type, the logical 1 level is state z, the logical 0 level is state a, and communication is lsb-first. the start character data is h'3b. parity is even (from the smart card standard), and so the parity bit is 1.
rev. 5.00, 09/03, page 498 of 760 in the inverse convention type, the logical 1 level is state a, the logical 0 level is state z, and communication is msb first. the start character data is h'3f. parity is even (from the smart card standard), and so the parity bit is 0, which corresponds to state z. only data bits d7?d0 are inverted by the sinv bit. to invert the parity bit, set the o/ e bit in scsmr to odd parity mode. this applies to both transmission and reception. ds d0 d1 d2 d3 d4d5 d6 d7 dp a (z) z z a z z z a a z (z) state a. direct convention (sdir, sinv, and o/ e are all 0) ds d7 d6 d5 d4d3 d2 d1 d0 dp a (z) z z a a a a a a z (z) state b. inverse convention (sdir, sinv, and o/ e are all 1) figure 15.4 waveform of start character 15.3.5 clock only the internal clock generated by the on-chip baud rate generator can be used as the communication clock in the smart card interface. the bit rate for the clock is set by the bit rate register (scbrr) and the cks1 and cks0 bits in the serial mode register (scsmr), and is calculated using the equation below. table 15.5 shows sample bit rates. if clock output is then selected by setting cke0 to 1, a clock with a frequency 372 times the bit rate is output from the sck0 pin. b = 10 6 1488 2 2n?1 (n + 1) p where: n = value set in scbrr (0 n 255) b = bit rate (bits/s) p = peripheral module operating frequency (mhz) n = 0 to 3 (table 15.4)
rev. 5.00, 09/03, page 499 of 760 table 15.4 relationship of n to cks1 and cks0 n cks1 cks0 000 101 210 311 table 15.5 examples of bit rate b (bits/s) for scbrr settings (n = = = = 0) p (mhz) n 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 0 9600.0 13440.9 14400.0 17473.1 19200.0 21505.4 24193.5 1 4800.0 6720.4 7200.0 8736.6 9600.0 10752.7 12096.8 2 3200.0 4480.3 4800.0 5824.4 6400.0 7168.5 8064.5 note: the bit rate is rounded to one decimal place. calculate the value to be set in the bit rate register (scbrr) from the operating frequency and the bit rate. n is an integer in the range 0 n 255, specifying a smallish error. n = 10 6 ? 1 1488 2 2n ? 1 b p table 15.6 examples of scbrr settings for bit rate b (bits/s) (n = = = = 0) (mhz) (9600 bits/s) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 n error n error n error n error n error n error n error 0 0.00 1 30.00 1 25.00 1 8.99 1 0.00 1 12.01 2 15.99
rev. 5.00, 09/03, page 500 of 760 table 15.7 maximum bit rates for frequencies (smart card interface mode) p (mhz) maximum bit rate (bits/s) n n 7.1424 9600 0 0 10.00 13441 0 0 10.7136 14400 0 0 13.00 17473 0 0 14.2848 19200 0 0 16.00 21505 0 0 18.00 24194 0 0 the bit rate error is found as follows: error (%) = ( 10 6 ? 1) 100 1488 2 2n ? 1 b (n + 1) p table 15.8 shows the relationship between transmit/receive clock register set values and output states on the smart card interface. table 15.8 register set values and sck pin register value sck pin setting smif c/ a a a a cke1 cke0 output state 1 * 1 1 0 0 0 port determined by setting of port register scp1md1 and scp1md0 bits 1001 sck (serial clock) output state 2 * 2 1 1 0 0 low output low output state 1101 sck (serial clock) output state 3 * 2 1 1 1 0 high output high output state 1111 sck (serial clock) output state notes: 1. the sck output state changes as soon as the cke0 bit is modified. the cke1 bit should be cleared to 0. 2. the clock duty remains constant despite stopping and starting of the clock by modification of the cke0 bit.
rev. 5.00, 09/03, page 501 of 760 15.3.6 data transmission and reception initialization: initialize the sci using the following procedure before sending or receiving data. initialization is also required for switching from transmit mode to receive mode or from receive mode to transmit mode. figure 15.5 shows a flowchart of the initialization process. 1. clear te and re in the serial control register (scscr) to 0. 2. clear error flags fer/ers, per, and orer to 0 in the serial status register (scssr). 3. set the c/ a bit, parity bit (o/ e bit), and baud rate generator select bits (cks1 and cks0 bits) in the serial mode register (scsmr). at this time also clear the chr and mp bits to 0 and set the stop and pe bits to 1. 4. set the smif, sdir, and sinv bits in the smart card mode register (scscmr). when the smif bit is set to 1, the txd and rxd pins both switch from ports to sci pins and become high-impedance. 5. set the value corresponding to the bit rate in the bit rate register (scbrr). 6. set the clock source select bits (cke1 and cke0 bits) in the serial control register (scscr). clear the tie, rie, te, re, mpie, and teie bits to 0. when the cke0 bit is set to 1, a clock is output from the sck pin. 7. after waiting at least 1 bit, set the tie, rie, te, and re bits in scscr. do not set the te and re bits simultaneously unless performing auto-diagnosis.
rev. 5.00, 09/03, page 502 of 760 initialization clear te and re bits in scscr to 0 set value in scbrr clear fer/ers, per and orer flags in scssr to 0 wait set tie, rie, te, and re bits in scscr has a 1-bit interval elapsed? end (2) set parity in o/ e bit, set clock in cks1 and cks0 bits, and set c/ a , in scsmr (3) set clock in cke1 and cke0 bits, and clear tie, rie, te, re, mpie, and teie bits to 0, in scscr (6) (5) (4) (1) (7) no yes set smif, sdir, and sinv bits in scsmr note: numbers in parentheses refer to steps in the preceding procedure description. figure 15.5 initialization flowchart (example)
rev. 5.00, 09/03, page 503 of 760 serial data transmission: the processing procedures in the smart card mode differ from ordinary sci processing because data is retransmitted when an error signal is sampled during a data transmission. this results in the transmission processing flowchart shown in figure 15.6. 1. initialize the smart card interface mode as described in initialization above. 2. check that the fer/ers bit in scssr is cleared to 0. 3. repeat steps 2 and 3 until the tend flag in scssr is set to 1. 4. write the transmit data into sctdr, clear the tdre flag to 0 and start transmitting. the tend flag will be cleared to 0. 5. to transmit more data, return to step 2. 6. to end transmission, clear the te bit to 0. this processing can be interrupted. when the tie bit is set to 1 and interrupt requests are enabled, a transmit-data-empty interrupt (txi) will be requested when the tend flag is set to 1 at the end of transmission. when the rie bit is set to 1 and interrupt requests are enabled, a communication error interrupt (eri) will be requested when the ers flag is set to 1 when an error occurs in transmission. see interrupt operation below for more information.
rev. 5.00, 09/03, page 504 of 760 start end of transmission start of transmission initialize write transmit data in sctdr and clear tdre flag in scssr to 0 (1) clear te bit in scscr to 0 (6) error handling (2) fer/ers = 0? tend = 1? yes yes yes yes no no all data transmitted? no tend = 1? no error handling fer/ers = 0? yes no (4) (5) (3) note: numbers in parentheses refer to steps in the preceding procedure description. figure 15.6 transmission flowchart
rev. 5.00, 09/03, page 505 of 760 serial data reception: the processing procedures in smart card mode are the same as in ordinary sci processing. the reception processing flowchart is shown in figure 15.7. 1. initialize the smart card interface mode as described above in initialization and in figure 15.5. 2. check that the orer and per flags in scssr are cleared to 0. if either flag is set, clear both to 0 after performing the appropriate error handling procedures. 3. repeat steps 2 and 3 until the rdrf flag is set to 1. 4. read the receive data from scrdr. 5. to receive more data, clear the rdrf flag to 0 and return to step 2. 6. to end reception, clear the re bit to 0. this processing can be interrupted. when the rie bit is set to 1 and interrupt requests are enabled, a receive-data-full interrupt (rxi) will be requested when the rdrf flag is set to 1 at the end of reception. when an error occurs during reception and either the orer or per flag is set to 1, a communication error interrupt (eri) will be requested. see interrupt operation below for more information. the received data will be transferred to scrdr even when a parity error occurs during reception and per is set to 1, so this data can still be read.
rev. 5.00, 09/03, page 506 of 760 start end of reception start of reception initialize write receive data from scrdr and clear rdrf flag in scssr to 0 (1) clear re bit in scscr to 0 (6) error handling (2) orer = 0 or per = 0? rdrf = 1? yes yes yes no no all data received? no (4) (5) (3) note: numbers in parentheses refer to steps in the preceding procedure description. figure 15.7 reception flowchart (example)
rev. 5.00, 09/03, page 507 of 760 switching modes: when switching from receive mode to transmit mode, check that the receive operation is completed before starting initialization, clearing re to 0, and setting te to 1. the rdrf, per, and orer flags can be used to check if reception is completed. when switching from transmit mode to receive mode, check that the transmit operation is completed before starting initialization, clearing te to 0, and setting re to 1. the tend flag can be used to check if transmission is completed. interrupt operation: in the smart card interface mode, there are three types of interrupts: transmit-data-empty (txi), communication error (eri) and receive-data-full (rxi). in this mode, the transmit-end interrupt (tei) cannot be requested. set the tend flag in scssr to 1 to request a txi interrupt. set the rdrf flag in scssr to 1 to request an rxi interrupt. set the orer, per, or fer/ers flag in scssr to 1 to request an eri interrupt (table 15.9). table 15.9 smart card mode operating state and interrupt sources mode state flag mask bit interrupt source transmit mode normal tend tie txi error fer/ers rie eri receive mode normal rdrf rie rxi error per, orer rie eri 15.4 usage notes when the sci is used as a smart card interface, be sure that all criteria in sections 15.4.1, receive data timing and receive margin in asynchronous mode and 15.4.2, retransmission are applied. 15.4.1 receive data timing and receive margin in asynchronous mode in asynchronous mode, the sci runs on a base clock with a frequency of 372 times the transfer rate. during reception, the sci samples the falling of the start bit using the base clock to achieve internal synchronization. receive data is latched internally at the rising edge of the 186th base clock cycle (figure 15.8).
rev. 5.00, 09/03, page 508 of 760 0 185 371 0 185 371 0 base clock receive data (rxd) synchro- nization sampling timing data sampling timing 186 clock cycles 372 clock cycles start bit d0 d1 figure 15.8 receive data sampling timing in smart card mode the receive margin is found from the following equation: for smart card mode: m = (0.5 ? ) 1 2n d ? 0.5 n ? (l ? 0.5)f ? (1 + f) 100% where: m = receive margin (%) n = ratio of bit rate to clock (n = 372) d = clock duty (d = 0 to 1.0) l = frame length (l = 10) f = absolute value of clock frequency deviation using this equation, the receive margin when f = 0 and d = 0.5 is as follows: m = (0.5 ? 1/2 372) 100 % = 49.866 %
rev. 5.00, 09/03, page 509 of 760 15.4.2 retransmission (receive and transmit modes) retransmission when sci is in receive mode: figure 15.9 shows the retransmission operation in the sci receive mode. 1. when the received parity bit is checked and an error is found, the per bit in scssr is automatically set to 1. if the rie bit in scscr is enabled at this time, an eri interrupt is requested. be sure to clear the per bit before the next parity bit is sampled. 2. the rdrf bit in scssr is not set in the frame that caused the error. 3. when the received parity bit is checked and no error is found, the per bit in scssr is not set. 4. when the received parity bit is checked and no error is found, reception is considered to have been completed normally and the rdrf bit in scssr is automatically set to 1. if the rie bit in scscr is enabled at this time, an rxi interrupt is requested. 5. when a normal frame is received, the pin maintains a three-state state when it transmits the error signal. d0 ds d2 d1 d4 d3 d6 d5 dp de d7 d0 ds d2 d1 d4 d3 d6 d5 dp (de) d7 d0 ds d2 d1 d4 d3 nth transfer frame rdrf per 2 1 4 5 3 retransmitted frame transfer frame n + 1 figure 15.9 retransmission in sci receive mode
rev. 5.00, 09/03, page 510 of 760 retransmission when sci is in transmit mode: figure 15.10 shows the retransmission operation in the sci transmit mode. 1. after transmission of one frame is completed, the fer/ers bit in scssr is set to 1 when a error signal is returned from the receiving side. if the rie bit in scscr is enabled at this time, an eri interrupt is requested. be sure to clear the fer/ers bit before the next parity bit is sampled. 2. the tend bit in scssr is not set in the frame that received the error signal indicating the error. 3. the fer/ers bit in scssr is not set when no error signal is returned from the receiving side. 4. when no error signal is returned from the receiving side, the tend bit in scssr is set to 1 when the transmission of the frame that includes the retransmission is considered completed. if the tie bit in scscr is enabled at this time, a txi interrupt will be requested. d0 ds d2 d1 d4 d3 d6 d5 dp de d7 d0 ds d2 d1 d4 d3 d6 d5 dp (de) d7 d0 ds d2 d1 d4 d3 nth transfer frame tend fer/ers transfer from sctdr to sctsr transfer from sctdr to sctsr transfer from sctdr to sctsr 1 2 4 3 retransmitted frame transfer frame n + 1 tdre figure 15.10 retransmission in sci transmit mode
rev. 5.00, 09/03, page 511 of 760 section 16 serial communication interface with fifo (scif) 16.1 overview the sh7709s has a two-channel serial communication interface with fifo (scif) that supports asynchronous serial communication. it also has 16-stage fifo registers for both transmission and reception that enable the sh7709s to perform efficient high-speed continuous communication. 16.1.1 features ? asynchronous serial communication: ? serial data communication is performed by start-stop in character units. the sci can communicate with a universal asynchronous receiver/transmitter (uart), an asynchronous communication interface adapter (acia), or any other communications chip that employs a standard asynchronous serial system. there are eight selectable serial data communication formats. ? data length: 7 or 8 bits ? stop bit length: 1 or 2 bits ? parity: even, odd, or none ? receive error detection: parity and framing errors ? break detection: break is detected when a framing error is followed by at least one frame at the space 0 level (low level). it is also detected by reading the rxd level directly from the port sc data register (scpdr) when a framing error occurs. ? full duplex communication: the transmitting and receiving sections are independent, so the sci can transmit and receive simultaneously. both sections use 16-stage fifo buffering, so high-speed continuous data transfer is possible in both the transmit and receive directions. ? on-chip baud rate generator with selectable bit rates ? internal or external transmit/receive clock source: from either baud rate generator (internal) or sck pin (external) ? four types of interrupts: transmit-fifo-data-empty, break, receive-fifo-data-full, and receive-error interrupts are requested independently. the direct memory access controller (dmac) can be activated to execute a data transfer by a transmit-fifo-data-empty or receive- fifo-data-full interrupt. ? when the scif is not in use, it can be stopped by halting the clock supplied to it, saving power. ? on-chip modem control functions (rts and cts) ? the quantity of data in the transmit and receive fifo registers and the number of receive errors of the receive data in the receive fifo register can be ascertained. ? a time-out error (dr) can be detected when receiving.
rev. 5.00, 09/03, page 512 of 760 16.1.2 block diagram figure 16.1 shows a block diagram of the scif. rxd txd sck scif scbrr scssr2 scscr2 scftdr2 sctsr scfrdr2 (16 (16 stages) stages) scrsr scsmr2 scfdr2 scfcr2 scpcr scfdr parity generation parity check clock external clock module data bus internal data bus p f p f /4 p f /16 p f /64 txi tei rxi bri bus interface baud rate generator transmit/ receive control scrsr: scfrdr2: sctsr: scftdr2: scsmr2: scscr2: legend receive shift register receive fifo data register 2 transmit shift register transmit fifo data register 2 serial mode register 2 serial control register 2 scssr2: scbrr2: scfcr2: scfdr2: scpdr: scpcr: serial status register 2 bit rate register 2 fifo control register 2 fifo data count register 2 port sc data register port sc control register transmit buffer receive buffer figure 16.1 block diagram of scif
rev. 5.00, 09/03, page 513 of 760 figures 16.2 to 16.4 show the scif i/o port pins. scif pin i/o and data control is performed by bits 11 to 8 of scpcr and bits 5 and 4 of scpdr. for details, see section 14.2.8, sc port control register (scpcr)/sc port data register (scpdr). internal data bus output enable clock input enable scif serial clock output serial clock input r scp5md0 pcrw reset c q q d r scp5md1 pcrw reset c q d r scp5dt1 pdrw reset scpt[5]/sck2 c d pdrw: legend scpdr write pdrr: pcrw: scpdr read scpcr write pdrr * note: * when reading the sck2 pin, clear the cke1 and cke0 bits in scscr to 0, and set the scp5md1 bit in scspr to 1 (see section 14.2.8, sc port control register (scpcr)/sc port data register (scpdr)). figure 16.2 scpt[5]/sck2 pin
rev. 5.00, 09/03, page 514 of 760 internal data bus output enable scif serial transmission output r scp4md0 pcrw reset c q q d r scp4md1 pcrw reset c q d r scp4dt1 pdrw reset scpt[4]/txd2 c d pcrw: pdrw: scpcr write scpdr write legend figure 16.3 scpt[4]/txd2 pin
rev. 5.00, 09/03, page 515 of 760 scif internal data bus pdrr * serial receive data scpt[4]/rxd2 pdrr: scpdr read legend note: * when reading the rxd2 pin, set the re bit in scscr to 1. figure 16.4 scpt[4]/rxd2 pin 16.1.3 pin configuration the scif has the serial pins summarized in table 16.1. table 16.1 scif pins pin name abbreviation i/o function serial clock pin sck2 i/o clock i/o receive data pin rxd2 input receive data input transmit data pin txd2 output transmit data output request to send pin rts2 output request to send clear to send pin cts2 input clear to send
rev. 5.00, 09/03, page 516 of 760 16.1.4 register configuration table 16.2 summarizes the scif internal registers. these registers specify the data format and bit rate, and control the transmitter and receiver sections. table 16.2 scif registers register name abbreviation r/w initial value address access size serial mode register 2 scsmr2 r/w h'00 h'04000150 (h'a4000150) * 2 8 bits bit rate register 2 scbrr2 r/w h'ff h'04000152 (h'a4000152) * 2 8 bits serial control register 2 scscr2 r/w h'00 h'04000154 (h'a4000154) * 2 8 bits transmit fifo data register 2 scftdr2 w ? h'04000156 (h'a4000156) * 2 8 bits serial status register 2 scssr2 r/(w) * 1 h'0060 h'04000158 (h'a4000158) * 2 16 bits receive fifo data register 2 scfrdr2 r undefined h'0400015a (h'a400015a) * 2 8 bits fifo control register 2 scfcr2 r/w h'00 h'0400015c (h'a400015c) * 2 8 bits fifo data count register 2 scfdr2 r h'0000 h'0400015e (h'a400015e) * 2 16 bits notes: these registers are located in area 1 of physical space. therefore, when the cache is on, either access these registers from the p2 area of logical space or else make an appropriate setting using the mmu so that these registers are not cached. 1. only 0 can be written to clear the flag. 2. when address translation by the mmu does not apply, the address in parentheses should be used.
rev. 5.00, 09/03, page 517 of 760 16.2 register descriptions 16.2.1 receive shift register (scrsr) the receive shift register (scrsr) receives serial data. data input at the rxd pin is loaded into scrsr in the order received, lsb (bit 0) first, converting the data to parallel form. when one byte has been received, it is automatically transferred to scfrdr, the receive fifo data register. the cpu cannot read or write to scrsr directly. bit:76543210 r/w:???????? 16.2.2 receive fifo data register (scfrdr) the 16-byte receive fifo data register (scfrdr) stores serial receive data. the scif completes the reception of one byte of serial data by moving the received data from the receive shift register (scrsr) into scfrdr for storage. continuous reception is possible until 16 bytes are stored. the cpu can read but not write to scfrdr. if data is read when there is no receive data in the scfrdr, the value is undefined. when this register is full of receive data, subsequent serial data is lost. bit:76543210 r/w:rrrrrrrr 16.2.3 transmit shift register (sctsr) the transmit shift register (sctsr) transmits serial data. the sci loads transmit data from the transmit fifo data register (scftdr) into sctsr, then transmits the data serially from the txd pin, lsb (bit 0) first. after transmitting one data byte, the sci automatically loads the next transmit data from scftdr into sctsr and starts transmitting again. the cpu cannot read or write to sctsr directly. bit:76543210 r/w:????????
rev. 5.00, 09/03, page 518 of 760 16.2.4 transmit fifo data register (scftdr) the transmit fifo data register (scftdr) is a fifo register comprising sixteen 8-bit stages that stores data for serial transmission. when the scif detects that the transmit shift register (sctsr) is empty, it moves transmit data written in the scftdr into sctsr and starts serial transmission. continuous serial transmission is performed until there is no transmit data left in scftdr. the cpu can always write to scftdr. when scftdr is full of transmit data (16 stages), no more data can be written. if writing of new data is attempted, the data is ignored. bit:76543210 r/w:wwwwwwww 16.2.5 serial mode register (scsmr) the serial mode register (scsmr) is an 8-bit register that specifies the scif serial communication format and selects the clock source for the baud rate generator. the cpu can always read and write to scsmr. scsmr is initialized to h'00 by a reset and in standby or module standby mode. bit:76543210 ? chr pe o/ e stop ? cks1 cks0 initial value:00000000 r/w: r r/w r/w r/w r/w r r/w r/w bit 7?reserved: this bit is always read as 0. the write value should always be 0. bit 6?character length (chr): selects 7-bit or 8-bit data in asynchronous mode. bit 6: chr description 0 8-bit data (initial value) 1 7-bit data * note: * when 7-bit data is selected, the msb (bit 7) of the transmit fifo data register is not transmitted.
rev. 5.00, 09/03, page 519 of 760 bit 5?parity enable (pe): selects whether to add a parity bit to transmit data and to check the parity of receive data. bit 5: pe description 0 parity bit not added or checked (initial value) 1 parity bit added and checked * note: * when pe is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (o/ e ) setting. receive data parity is checked according to the even/odd (o/ e ) mode setting. bit 4?parity mode (o/ e e e e ): selects even or odd parity when parity bits are added and checked. the o/ e setting is used only when the parity enable bit (pe) is set to 1 to enable parity addition and checking. the o/ e setting is ignored when parity addition and checking is disabled. bit 4: o/ e e e e description 0 even parity * 1 (initial value) 1 odd parity * 2 notes: 1. if even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 2. if odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined. bit 3?stop bit length (stop): selects one or two bits as the stop bit length. when receiving, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. bit 3: stop description 0 one stop bit * 1 (initial value) 1 two stop bits * 2 notes: 1. when transmitting, a single 1-bit is added at the end of each transmitted character. 2. when transmitting, two 1-bits are added at the end of each transmitted character. bit 2?reserved: this bit is always read as 0. the write value should always be 0.
rev. 5.00, 09/03, page 520 of 760 bits 1 and 0?clock select 1 and 0 (cks1, cks0): select the internal clock source of the on- chip baud rate generator. according to the setting of the cks1 and cks0 bits four clock sources are available. p , p /4, p /16 and p /64. for further information on the clock source, bit rate register settings, and baud rate, see section 16.2.8, bit rate register (scbrr). bit 1: cks1 bit 0: cks0 description 00p (initial value) 1p /4 10p /16 1p /64 note: p : peripheral clock 16.2.6 serial control register (scscr) the serial control register (scscr) operates the scif transmitter/receiver, selects the serial clock output in asynchronous mode, enables/disables interrupt requests, and selects the transmit/receive clock source. the cpu can always read and write to scscr. scscr is initialized to h'00 by a reset and in standby or module standby mode. bit:76543210 tie rie te re ? ? cke1 cke0 initial value:00000000 r/w: r/w r/w r/w r/w r r r/w r/w bit 7?transmit interrupt enable (tie): enables or disables the transmit-fifo-data-empty interrupt (txi) requested when the serial transmit data is transferred from the transmit fifo data register (scftdr) to the transmit shift register (sctsr), when the quantity of data in the transmit fifo register becomes less than the specified number of transmission triggers, and when the tdfe flag in the serial fifo status register (scfsr) is set to1. bit 7: tie description 0 transmit-fifo-data-empty interrupt request (txi) is disabled * (initial value) 1 transmit-fifo-data-empty interrupt request (txi) is enabled note: * the txi interrupt request can be cleared by writing a greater quantity of transmit data than the specified transmission trigger number to scftdr and by clearing tdfe to 0 after reading 1 from tdfe, or can be cleared by clearing tie to 0.
rev. 5.00, 09/03, page 521 of 760 bit 6?receive interrupt enable (rie): enables or disables the receive-data-full (rxi) and receive-error (eri) interrupts requested when serial receive data is transferred from the receive shift register (scrsr) to the receive fifo data register (scfrdr), when the quantity of data in the receive fifo register becomes more than the specified receive trigger number, and when the rdrf flag in scssr is set to1. bit 6: rie description 0 receive-data-full interrupt (rxi), receive-error interrupt (eri), and receive break interrupt (bri) requests are disabled * (initial value) 1 receive-data-full interrupt (rxi) and receive-error interrupt (eri) requests are enabled note: * rxi and eri interrupt requests can be cleared by reading the dr, er, or rdf flag after it has been set to 1, then clearing the flag to 0, or by clearing rie to 0. with the rdf flag, read 1 from the rdf flag and clear it to 0, after reading receive data from scrdr until the quantity of receive data becomes less than the specified receive trigger number. bit 5?transmit enable (te): enables or disables the scif serial transmitter. bit 5: te description 0 transmitter disabled (initial value) 1 transmitter enabled * note: * serial transmission starts after writing of transmit data into scftdr2. select the transmit format in scsmr2 and scfcr2 and reset the tfifo before setting te to 1. bit 4?receive enable (re): enables or disables the scif serial receiver. bit 4: re description 0 receiver disabled * 1 (initial value) 1 receiver enabled * 2 notes: 1. clearing re to 0 does not affect the receive flags (dr, er, brk, fer, per, and orer). these flags retain their previous values. 2. serial reception starts when a start bit is detected. select the receive format in scsmr2 before setting re to 1. bits 3 and 2?reserved: these bits are always read as 0. the write value should always be 0.
rev. 5.00, 09/03, page 522 of 760 bits 1 and 0?clock enable 1 and 0 (cke1, cke0): select the scif clock source and enable or disable clock output from the sck pin. depending on the combination of cke1 and cke0, the sck pin can be used for serial clock output or serial clock input. the cke0 setting is valid only when the scif is operating on the internal clock (cke1 = 0). the cke0 setting is ignored when an external clock source is selected (cke1 = 1). before selecting the scif operating mode in the serial mode register (scsmr), set cke1 and cke0. for further details on selection of the scif clock source, see table 16.7 in section 16.3, operation. bit 1: cke1 bit 0: cke0 description 0 0 internal clock, sck pin used for input pin (input signal is ignored) (initial value) 1 internal clock, sck pin used for clock output * 1 1 0 external clock, sck pin used for clock input * 2 1 external clock, sck pin used for clock input * 2 notes: 1. the output clock frequency is 16 times the bit rate. 2. the input clock frequency is 16 times the bit rate. 16.2.7 serial status register (scssr) the serial status register (scssr) is a 16-bit register. the upper 8 bits indicate the number of receive errors in the scfrdr data, and the lower 8 bits indicate the scif operating state. the cpu can always read and write to scssr, but cannot write 1 to the status flags (er, tend, tdfe, brk, oper, and dr). these flags can be cleared to 0 only if they have first been read (after being set to 1). bits 3 (fer) and 2 (per) are read-only bits that cannot be written. scssr is initialized to h'0060 by a reset and in standby or module standby mode. lower 8 bits:76543210 er tend tdfe brk fer per rdf dr initial value:01100000 r/w: r/(w) * r/(w) * r/(w) * r/(w) * rrr/(w) * r/(w) * note: * the only value that can be written is 0 to clear the flag.
rev. 5.00, 09/03, page 523 of 760 bit 7?receive error (er): indicates the occurrence of a framing error, or of a parity error when receiving data that includes parity. bit 7: er description 0 receiving is in progress or has ended normally * 1 (initial value) [clearing conditions] (1) by a power-on reset or in standby mode er is cleared to 0 when the chip is reset or enters standby mode (2) when 0 is written after 1 is read from er 1 a framing error or parity error has occurred * 2 [setting conditions] (1) er is set to 1 when the stop bit is 0 after checking whether or not the last stop bit of the received data is 1 at the end of one data receive operation * 2 (2) when the total number of 1s in the receive data plus parity bit does not match the even/odd parity specified by the o/ e bit in scsmr notes: 1. clearing the re bit to 0 in scscr does not affect the er bit, which retains its previous value. even if a receive error occurs, the receive data is transferred to scfrdr and the receive operation is continued. whether or not the data read from scrdr includes a receive error can be detected by the fer and per bits in scssr. 2. in stop mode, only the first stop bit is checked; the second stop bit is not checked. bit 6?transmit end (tend): indicates that when the last bit of a serial character was transmitted, scftdr did not contain valid data, so transmission has ended. bit 6: tend description 0 transmission is in progress [clearing condition] when data is written in scftdr 1 end of transmission (initial value) [setting conditions] (1) when the chip is reset or enters standby mode, when te is cleared to 0 in the serial control register (scscr) (2) when scftdr does not contain receive data when the last bit of a one-byte serial character is transmitted
rev. 5.00, 09/03, page 524 of 760 bit 5?transmit fifo data empty (tdfe): indicates that data has been transferred from the transmit fifo data register (scftdr) to the transmit shift register (sctsr), the quantity of data in scftdr has become less than the transmission trigger number specified by the ttrg1 and ttrg0 bits in the fifo control register (scfcr), and writing of transmit data to scftdr is enabled. bit 5: tdfe description 0 the quantity of transmit data written to scftdr is greater than the specified transmission trigger number (initial value) [clearing condition] tdfe is cleared to 0 when data exceeding the specified transmission trigger number is written to scftdr, or when software reads tdfe after it has been set to 1, then writes 0 to tdfe 1 the quantity of transmit data in scftdr is less than the specified transmission trigger number * [setting conditions] (1) tdfe is set to 1 by a reset or in standby mode (2) when the quantity of transmit data in scftdr becomes less than the specified transmission trigger number as a result of transmission note: * since scftdr is a 16-byte fifo register, the maximum quantity of data that can be written when tdfe is 1 is ?16 minus the specified transmission trigger number?. if an attempt is made to write additional data, the data is ignored. the quantity of data in scftdr is indicated by the upper 8 bits of scftdr. bit 4?break detection (brk): indicates that a break signal has been detected in receive data. bit 4: brk description 0 no break signal received (initial value) [clearing conditions] (1) brk is cleared to 0 when the chip is reset or enters standby mode (2) when software reads brk after it has been set to 1, then writes 0 to brk 1 break signal received * [setting conditions] (1) brk is set to 1 when data including a framing error is received (2) a framing error occurs with space 0 in the subsequent receive data note: * when a break is detected, transfer of the receive data (h'00) to scfrdr stops after detection. when the break ends and the receive signal becomes mark 1, the transfer of receive data resumes. the receive data of a frame in which a break signal is detected is transferred to scfrdr. after this, however, no receive data is transferred until a break ends with the received signal being mark 1, and the next data is received.
rev. 5.00, 09/03, page 525 of 760 bit 3?framing error (fer): indicates a framing error in the data read from the receive fifo data register (scfrdr). bit 3: fer description 0 no receive framing error occurred in the data read from scfrdr (initial value) [clearing conditions] (1) when the chip undergoes a power-on reset or enters standby mode (2) when no framing error is present in the data read from scfrdr 1 a receive framing error occurred in the data read from scfrdr [setting condition] when a framing error is present in the data read from scfrdr bit 2?parity error (per): indicates a parity error in the data read from the receive fifo data register (scfrdr). bit 2: per description 0 no receive parity error occurred in the data read from scfrdr (initial value) [clearing conditions] (1) when the chip undergoes a power-on reset or enters standby mode (2) when no parity error is present in the data read from scfrdr 1 a receive framing error occurred in the data read from scfrdr [setting condition] when a parity error is present in the data read from scfrdr
rev. 5.00, 09/03, page 526 of 760 bit 1?receive fifo data full (rdf): indicates that receive data has been transferred to the receive fifo data register (scfrdr), and the quantity of data in scfrdr has become greater than the receive trigger number specified by the rtrg1 and rtrg0 bits in the fifo control register (scfcr). bit 1: rdf description 0 the quantity of transmit data written to scfrdr is less than the specified receive trigger number (initial value) [clearing conditions] (1) by a power-on reset or in standby mode (2) when the quantity of receive data in scfrdr is less than the specified receive trigger value and 1 is read from rdf, which is then cleared to 0 1 the quantity of receive data in scfrdr is greater than the specified receive trigger number [setting condition] when a quantity of receive data greater than the specified receive trigger numbe r is stored in scfrdr * note: * since scftdr is a 16-byte fifo register, the maximum quantity of data that can be read when rdf is 1 is the specified receive trigger number. if an attempt is made to read after all the data in scfrdr has been read, the data is undefined. the quantity of receive data in scfrdr is indicated by the lower 8 bits of scftdr. bit 0?receive data ready (dr): indicates that the quantity of data in the receive fifo data register (scfrdr) is less than the specified receive trigger number, and that the next data has not yet been received after the elapse of 15 etu from the last stop bit. bit 0: dr description 0 receiving is in progress, or no receive data remains in scfrdr after receiving ended normally (initial value) [clearing conditions] (1) when the chip undergoes a power-on reset or enters standby mode (2) when software reads dr after it has been set to 1, then writes 0 to dr 1 next receive data has not been received [setting condition] when scfrdr contains less data than the specified receive trigger number, and the next data has not yet been received after the elapse of 15 etu from the last stop bit * note: * this is equivalent to 1.5 frames with the 8-bit, 1-stop-bit format. (etu: elementary time unit)
rev. 5.00, 09/03, page 527 of 760 upper 8 bits: 15 14 13 12 11 10 9 8 per3 per2 per1 per0 fer3 fer2 fer1 fer0 initial value:00000000 r/w:rrrrrrrr bits 15 to 12?number of parity errors 3 to 0 (per3 to per0): indicate the quantity of data including a parity error in the receive data stored in the receive fifo data register (scfrdr). the value indicated by bits 15 to 12 represents the number of parity errors in scfrdr. bits 11 to 8?number of framing errors 3 to 0 (fer3 to fer0): indicate the quantity of data including a framing error in the receive data stored in scfrdr. the value indicated by bits 11 to 8 represents the number of framing errors in scfrdr. 16.2.8 bit rate register (scbrr) the bit rate register (scbrr) is an 8-bit register that, together with the baud rate generator clock source selected by the cks1 and cks0 bits in the serial mode register (scsmr), determines the serial transmit/receive bit rate. the cpu can always read and write to scbrr. scbrr is initialized to h'ff by a reset and in module standby or standby mode. each channel has independent baud rate generator control, so different values can be set in two channels. bit:76543210 initial value:11111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the scbrr setting is calculated as follows: asynchronous mode: n = p 64 2 2n ? 1 b 10 6 ? 1 b: bit rate (bits/s) n: scbrr setting for baud rate generator (0 n 255) p : operating frequency for peripheral modules (mhz) n: baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n, see table 16.3.)
rev. 5.00, 09/03, page 528 of 760 table 16.3 scsmr settings scsmr settings n clock source cks1 cks0 0p 00 1p /4 0 1 2p /16 1 0 3p /64 1 1 note: the bit rate error is given by the following formula: error (%) = p 10 6 ? 1 100 (n+1) 64 2 2n ? 1 b table 16.4 lists examples of scbrr settings. table 16.4 bit rates and scbrr settings p (mhz) 2 2.097152 2.4576 bit rate (bits/s) n n error ( % % % % ) n n error ( % % % % ) n n error ( % % % % ) 110 1 141 0.03 1 148 ?0.04 1 174 ?0.26 150 1 103 0.16 1 108 0.21 1 127 0.00 300 0 207 0.16 0 217 0.21 0 255 0.00 600 0 103 0.16 0 108 0.21 0 127 0.00 1200 0 51 0.16 0 54 ?0.70 0 63 0.00 2400 0 25 0.16 0 26 1.14 0 31 0.00 4800 0 12 0.16 0 13 ?2.48 0 15 0.00 9600 0 6 ?6.99 0 6 ?2.48 0 7 0.00 19200 0 2 8.51 0 2 13.78 0 3 0.00 31250 0 1 0.00 0 1 4.86 0 1 22.88 38400 0 1 ?18.62 0 0 ?14.67 0 1 0.00
rev. 5.00, 09/03, page 529 of 760 p (mhz) 3 3.6864 4 bit rate (bits/s) n n error ( % % % % ) n n error ( % % % % ) n n error ( % % % % ) 110 1 212 0.03 2 64 0.70 2 70 0.03 150 1 155 0.16 1 191 0.00 1 207 0.16 300 1 77 0.16 1 95 0.00 1 103 0.16 600 0 155 0.16 0 191 0.00 0 207 0.16 1200 0 77 0.16 0 95 0.00 0 103 0.16 2400 0 38 0.16 0 47 0.00 0 51 0.16 4800 0 19 ?2.34 0 23 0.00 0 25 0.16 9600 0 9 ?2.34 0 11 0.00 0 12 0.16 19200 0 4 ?2.34 0 5 0.00 0 6 ?6.99 31250 0 2 0.00 0 3 ?7.84 0 3 0.00 38400 ? ? ? 0 2 0.00 0 2 8.51 p (mhz) 4.9152 5 6 bit rate (bits/s) n n error ( % % % % ) n n error ( % % % % ) n n error ( % % % % ) 110 2 86 0.31 2 88 ?0.25 2 106 ?0.44 150 1 255 0.00 2 64 0.16 2 77 0.16 300 1 127 0.00 1 129 0.16 1 155 0.16 600 0 255 0.00 1 64 0.16 1 77 0.16 1200 0 127 0.00 0 129 0.16 0 155 0.16 2400 0 63 0.00 0 64 0.16 0 77 0.16 4800 0 31 0.00 0 32 ?1.36 0 38 0.16 9600 0 15 0.00 0 15 1.73 0 19 ?2.34 19200 0 7 0.00 0 7 1.73 0 9 ?2.34 31250 0 4 ?1.70 0 4 0.00 0 5 0.00 38400 0 3 0.00 0 3 1.73 0 4 ?2.34
rev. 5.00, 09/03, page 530 of 760 p (mhz) 6.144 7.3728 8 bit rate (bits/s) n n error ( % % % % ) n n error ( % % % % ) n n error ( % % % % ) 110 2 108 0.08 2 130 ?0.07 2 141 0.03 150 2 79 0.00 2 95 0.00 2 103 0.16 300 1 159 0.00 1 191 0.00 1 207 0.16 600 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 2.40 0 6 5.33 0 7 0.00 38400 0 4 0.00 0 5 0.00 0 6 ?6.99 p (mhz) 9.8304 10 12 12.288 bit rate (bits/s) n n error ( % % % % )n n error ( % % % % )n n error ( % % % % )n n error ( % % % % ) 110 1 174 ?0.26 2 177 ?0.25 1 212 0.03 2 217 0.08 150 1 127 0.00 2 129 0.16 1 155 0.16 2 159 0.00 300 0 255 0.00 2 64 0.16 1 77 0.16 2 79 0.00 600 0 127 0.00 1 129 0.16 0 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 0 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 38 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 19 0.16 0 79 0.00 9600 0 31 0.00 0 32 ?1.36 0 9 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 4 0.16 0 19 0.00 31250 0 9 ?1.70 0 9 0.00 0 2 0.00 0 11 2.40 38400 0 1 0.00 0 7 1.73 0 9 ?2.34 0 9 0.00
rev. 5.00, 09/03, page 531 of 760 p (mhz) 14.7456 16 19.6608 20 bit rate (bits/s) n n error ( % % % % )n n error ( % % % % )n n error ( % % % % )n n error ( % % % % ) 110 3 64 0.70 3 70 0.03 3 86 0.31 3 88 ?0.25 150 2 191 0.00 2 207 0.16 2 255 0.00 2 64 0.16 300 2 95 0.00 2 103 0.16 2 127 0.00 2 129 0.16 600 1 191 0.00 1 207 0.16 1 255 0.00 1 64 0.16 1200 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 2400 0 191 0.00 0 207 0.16 0 255 0.00 0 64 0.16 4800 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 9600 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 19200 0 23 0.00 0 25 0.16 0 31 0.00 0 32 ?1.36 31250 0 14 ?1.70 0 15 0.00 0 19 ?1.70 0 19 0.00 38400 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 115200 0 3 0.00 0 3 8.51 0 4 6.67 0 4 8.51 500000 0 0 ?7.84 0 0 0.00 0 0 22.9 0 0 25.0 p (mhz) 24 24.576 28.7 30 bit rate (bits/s) n n error ( % % % % )n n error ( % % % % )n n error ( % % % % )n n error ( % % % % ) 110 3 106 ?0.44 3 108 0.08 3 126 0.31 3 132 0.13 150 3 77 0.16 3 79 0.00 3 92 0.46 3 97 ?0.35 300 2 155 0.16 2 159 0.00 2 186 ?0.08 2 194 0.16 600 2 77 0.16 2 79 0.00 2 92 0.46 2 97 ?0.35 1200 1 155 0.16 1 159 0.00 1 186 ?0.08 1 194 0.16 2400 1 77 0.16 1 79 0.00 1 92 0.46 1 97 ?0.35 4800 0 155 0.16 0 159 0.00 0 186 ?0.08 0 194 ?1.36 9600 0 77 0.16 0 79 0.00 0 92 0.46 0 97 ?0.35 19200 0 38 0.16 0 39 0.00 0 46 ?0.61 0 48 ?0.35 31250 0 23 0.00 0 24 ?1.70 0 28 ?1.03 0 29 0.00 38400 0 19 ?2.34 0 19 0.00 0 22 1.55 0 23 1.73 115200 0 6 ?6.99 0 6 ?4.76 0 7 ?2.68 0 7 1.73 500000 0 1 ?25.0 0 1 ?23.2 0 1 ?10.3 0 1 ?6.25
rev. 5.00, 09/03, page 532 of 760 table 16.5 indicates the maximum bit rates in asynchronous mode when the baud rate generator is used. table 16.6 list the maximum rates for external clock input. table 16.5 maximum bit rates for various frequencies with baud rate generator (asynchronous mode) settings p (mhz) maximum bit rate (bits/s) n n 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 8 250000 0 0 9.8304 307200 0 0 12 375000 0 0 14.7456 460800 0 0 16 500000 0 0 19.6608 614400 0 0 20 625000 0 0 24 750000 0 0 24.576 768000 0 0 28.7 896875 0 0 30 937500 0 0
rev. 5.00, 09/03, page 533 of 760 table 16.6 maximum bit rates with external clock input (asynchronous mode) p (mhz) external input clock (mhz) maximum bit rate (bits/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 8 2.0000 125000 9.8304 2.4576 153600 12 3.0000 187500 14.7456 3.6864 230400 16 4.0000 250000 19.6608 4.9152 307200 20 5.0000 312500 24 6.0000 375000 24.576 6.1440 384000 28.7 7.1750 448436 30 7.5000 468750
rev. 5.00, 09/03, page 534 of 760 16.2.9 fifo control register (scfcr) bit:76543210 rtrg1 rtrg0 ttrg1 ttrg0 mce tfrst rfrst loop initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the fifo control register (scfcr) resets the quantity of data in the transmit and receive fifo registers, sets the trigger data quantity, and contains an enable bit for loop-back testing. scfcr can always be read and written to by the cpu. it is initialized to h'00 by a reset, by the module standby function, and in standby mode. bits 7 and 6?receive fifo data trigger (rtrg1, rtrg0): set the quantity of receive data which sets the receive data full (rdf) flag in the serial status register (scssr). the rdf flag is set to 1 when the quantity of receive data stored in the receive fifo register (scfrdr) exceeds the set trigger number shown below. bit 7: rtrg1 bit 6: rtrg0 receive trigger number 0 0 1 (initial value) 014 108 1114 bits 5 and 4?transmit fifo data trigger (ttrg1, ttrg0): set the quantity of remaining transmit data which sets the transmit fifo data register empty (tdfe) flag in the serial status register (scssr). the tdfe flag is set to 1 when the quantity of transmit data in the transmit fifo data register (scftdr) becomes less than the set trigger number shown below. bit 5: ttrg1 bit 4: ttrg0 transmit trigger number 008 (8) * 0 1 4 (12) 1 0 2 (14) 1 1 1 (15) note: * initial value. values in parentheses mean the number of empty bits in scftdr when the tdfe flag is set to 1.
rev. 5.00, 09/03, page 535 of 760 bit 3?modem control enable (mce): enables modem control signals cts and rts. bit 3: mce description 0 modem signal disabled * (initial value) 1 modem signal enabled note: * cts is fixed at active 0 regardless of the input value, and rts is also fixed at 0. bit 2?transmit fifo data register reset (tfrst): disables the transmit data in the transmit fifo data register and resets the data to the empty state. bit 2: tfrst description 0 reset operation disabled * (initial value) 1 reset operation enabled note: * reset is executed in a reset or in standby mode. bit 1?receive fifo data register reset (rfrst): disables the receive data in the receive fifo data register and resets the data to the empty state. bit 1: rfrst description 0 reset operation disabled * (initial value) 1 reset operation enabled note: * reset is executed in a reset or in standby mode. bit 0?loop-back test (loop): internally connects the transmit output pin (txd) and receive input pin (rxd) and enables loop-back testing. bit 0: loop description 0 loop back test disabled (initial value) 1 loop back test enabled
rev. 5.00, 09/03, page 536 of 760 16.2.10 fifo data count register (scfdr) scfdr is a 16-bit register which indicates the quantity of data stored in the transmit fifo data register (scftdr) and the receive fifo data register (scfrdr). it indicates the quantity of transmit data in scftdr with the upper 8 bits, and the quantity of receive data in scfrdr with the lower 8 bits. scfdr can always be read by the cpu. upper 8 bits: 15 14 13 12 11 10 9 8 ? ? ? t4 t3 t2 t1 t0 initial value:00000000 r/w:rrrrrrrr the upper 8 bits of scfdr indicate the quantity of non-transmitted data stored in scftdr. h'00 means no transmit data, and h'10 means that scftdr is full of transmit data. lower 8 bits:76543210 ? ? ? r4 r3 r2 r1 r0 initial value:00000000 r/w:rrrrrrrr the lower 8 bits of scfdr indicate the quantity of receive data stored in scfrdr. h'00 means no receive data, and h'10 means that scfrdr full of receive data.
rev. 5.00, 09/03, page 537 of 760 16.3 operation 16.3.1 overview for serial communication, the scif has an asynchronous mode in which characters are synchronized individually. refer to section 14.3.2, operation in asynchronous mode. the scif has a 16-byte fifo buffer for both transmit and receive operations, reducing the overhead of the cpu, and enabling continuous high-speed communication. moreover, it has rts and cts signals as modem control signals. the transmission format is selected in the serial mode register (scsmr), as shown in table 16.7. the scif clock source is selected by the combination of the cke1 and cke0 bits in the serial control register (scscr), as shown in table 16.8. ? data length is selectable: 7 or 8 bits. ? parity and multiprocessor bits are selectable, as is the stop bit length (1 or 2 bits). the combination of the preceding selections constitutes the communication format and character length. ? in receiving, it is possible to detect framing errors (fer), parity errors (per), receive fifo data full, receive data ready, and breaks. ? in transmitting, it is possible to detect transmit fifo data empty. ? the number of stored data bytes is indicated for both the transmit and receive fifo registers. ? an internal or external clock can be selected as the scif clock source. ? when an internal clock is selected, the scif operates using the on-chip baud rate generator, and can output a serial clock signal with a frequency 16 times the bit rate. ? when an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (the on-chip baud rate generator is not used.) table 16.7 scsmr settings and scif communication formats scsmr settings scif communication format mode bit 6 chr bit 5 pe bit 3 stop data length parity bit stop bit length asynchronous 0 0 0 8-bit not set 1 bit 12 bits 10 set 1 bit 12 bits 1 0 0 7-bit not set 1 bit 12 bits 10 set 1 bit 12 bits
rev. 5.00, 09/03, page 538 of 760 table 16.8 scscr settings and scif clock source selection scscr settings scif transmit/receive clock mode bit 1 cke1 bit 0 cke0 clock source sck pin function 0 0 internal scif does not use the sck pin 1 outputs a clock with a frequency 16 times the bit rate 1 0 external asynchronous mode 1 inputs a clock with frequency 16 times the bit rate 16.3.2 serial operation transmit/receive formats: table 16.9 lists the eight communication formats that can be selected. the format is selected by settings in the serial mode register (scsmr). table 16.9 serial communication formats scsmr bits serial transmit/receive format and frame length chrpe stop 1 2345678 9 10 11 12 0 0 0 start 8-bit data stop 0 0 1 start 8-bit data stop stop 0 1 0 start 8-bit data p stop 0 1 1 start 8-bit data p stop stop 1 0 0 start 7-bit data stop 1 0 1 start 7-bit data stop stop 1 1 0 start 7-bit data p stop 1 1 1 start 7-bit data p stop stop start: start bit stop: stop bit p: parity bit
rev. 5.00, 09/03, page 539 of 760 clock: an internal clock generated by the on-chip baud rate generator or an external clock input from the sck pin can be selected as the scif transmit/receive clock. the clock source is selected by bits cke1 and cke0 in the serial control register (scscr) (table 16.8). when an external clock is input at the sck pin, it must have a frequency equal to 16 times the desired bit rate. when the scif operates on an internal clock, it can output a clock signal at the sck pin. the frequency of this output clock is 16 times the bit rate. transmitting and receiving data (scif initialization): before transmitting or receiving, clear the te and re bits to 0 in the serial control register (scscr), then initialize the scif as follows. when changing the communication format, always clear the te and re bits to 0 before following the procedure given below. clearing te to 0 initializes the transmit shift register (sctsr). clearing te and re to 0, however, does not initialize the serial status register (scssr), transmit fifo data register (scftdr), or receive fifo data register (scfrdr), which retain their previous contents. clear te to 0 after all transmit data has been transmitted and the tend flag in the scssr is set. the te bit can be cleared to 0 during transmission, but the transmit data goes to the high impedance state after the bit is cleared to 0. set the tfrst bit in scfcr to 1 and reset scftdr before te is set again to start transmission. when an external clock is used, the clock should not be stopped during initialization or subsequent operation. scif operation becomes unreliable if the clock is stopped. figure 16.5 shows a sample flowchart for initializing the scif. the procedure for initializing the scif is: 1. set the clock selection in scscr. be sure to clear bits rie tie, te, and re to 0. when clock output is selected, the clock is output immediately after scscr settings are made. 2. set the communication format in scsmr. 3. write a value corresponding to the bit rate into the bit rate register (scbrr). (not necessary if an external clock is used.) 4. wait at least one bit interval, then set the te bit or re bit in scscr to 1. also set the rie and tie bits. setting the te and re bits enables the txd and rxd pins to be used. when transmitting, the scif will go to the mark state; when receiving, it will go to the idle state, waiting for a start bit.
rev. 5.00, 09/03, page 540 of 760 initialization clear te and re bits in scscr to 0 set tfrst and rfrst bits in scfcr to 1 1-bit interval elapsed? set rtrg1-0, ttrg1-0, and mce in scfcr clear tfrst and rfrst bits to 0 set te and re bits in scscr to 1,and set rie, tie, teie, and mpie bits set communication format in scsmr yes no set value in scbrr set cke1 and cke0 bits in scscr (leaving te and re bits cleared to 0) end (1) (2) (3) (4) wait note: numbers in parentheses refer to steps in the preceding procedure description. figure 16.5 sample flowchart for scif initialization
rev. 5.00, 09/03, page 541 of 760 ? serial data transmission figure 16.6 shows a sample flowchart for serial transmission. use the following procedure for serial data transmission after enabling the scif for transmission. 1. scif status check and transmit data write: read serial status register (scssr) and check that the tdfe flag is set to 1, then write transmit data to the transmit fifo data register (scftdr), read 1 from the tdfe and tend flags, then clear these flags to 0. the number of transmit data bytes that can be written is (16 - transmit trigger set number). 2. serial transmission continuation procedure: to continue serial transmission, read 1 from the tdfe flag to confirm that writing is possible, then write data to scftdr, and then clear the tdfe flag to 0. 3. break output at the end of serial transmission: to output a break in serial transmission, set the port sc data register (scpdr) and port sc control register (scpcr), then clear the te bit to 0 in the serial control register (scscr). for information on scpdr and scpcr, see section 16.2.8, bit rate register (scbrr). in steps 1 and 2, it is possible to ascertain the number of data bytes that can be written from the number of transmit data bytes in scftdr indicated by the upper 8 bits of the fifo data count register (scfdr).
rev. 5.00, 09/03, page 542 of 760 start of transmission read tdfe bit in scssr tend= 1? read tend bit in scssr clear te bit in scscr to 0 set scpdr and scpcr yes no tdfe= 1? no all data transmitted? no yes yes break output? yes no write transmit data (16 - transmit trigger set number) to scftdr, read 1 from tdfe bit and tend flag in scssr, then clear to 0 end of transmission (1) (2) (3) note: numbers in parentheses refer to steps in the preceding procedure description. figure 16.6 sample flowchart for transmitting serial data
rev. 5.00, 09/03, page 543 of 760 in serial transmission, the scif operates as described below. 1. when data is written into the transmit fifo data register (scftdr), the scif transfers the data from scftdr to the transmit shift register (sctsr) and starts transmitting. confirm that the tdfe flag in the serial status register (scssr) is set to 1 before writing transmit data to scftdr. the number of data bytes that can be written is (16 ? transmit trigger setting). 2. when data is transferred from scftdr to sctsr and transmission is started, consecutive transmit operations are performed until there is no transmit data left in scftdr. when the number of transmit data bytes in scftdr falls below the transmit trigger number set in the fifo control register (scfcr), the tdfe flag is set. if the tie bit in the serial control register (scsr) is set to 1 at this time, a transmit-fifo-data-empty interrupt (txi) request is generated. the serial transmit data is sent from the txd pin in the following order. a. start bit: one-bit 0 is output. b. transmit data: 8-bit or 7-bit data is output in lsb-first order. c. parity bit: one parity bit (even or odd parity) is output. (a format in which a parity bit is not output can also be selected.) d. stop bit(s): one or two 1-bits (stop bits) are output. e. mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. the scif checks the scftdr transmit data at the timing for sending the stop bit. if data is present, the data is transferred from scftdr to sctsr, the stop bit is sent, and then serial transmission of the next frame is started. if there is no transmit data, the tend flag in scssr is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output continuously.
rev. 5.00, 09/03, page 544 of 760 figure 16.7 shows an example of the operation for transmission. 01 1 1 0/1 0 1 tdfe tend parity bit parity bit serial data start bit data stop bit start bit data stop bit idle (mark) state txi interrupt request data written to scftdr and tdfe flag read as 1 then cleared to 0 by txi interrupt handler one frame d 0 d 1 d 7 d 0 d 1 d 7 0/1 txi interrupt request figure 16.7 example of transmit operation (8-bit data, parity, one stop bit) 4. when modem control is enabled, transmission can be stopped and restarted in accordance with the cts input value. when cts is set to 1, if transmission is in progress, the line goes to the mark state after transmission of one frame. when cts is set to 0, the next transmit data is output starting from the start bit. figure 16.8 shows an example of the operation when modem control is used. 0 0/1 0 cts parity bit serial data txd start bit stop bit start bit d 0 d 1 d 7 d 0 d 1 d 7 0/1 rise at this point before stop bit figure 16.8 example of operation using modem control ( cts cts cts cts )
rev. 5.00, 09/03, page 545 of 760 ? serial data reception figures 16.9 and 16.10 show a sample flowchart for serial reception. use the following procedure for serial data reception after enabling the scif for reception. 1. receive error handling and break detection: read the dr, er, and brk flags in scssr to identify any error, perform the appropriate error handling, then clear the dr, er, and brk flags to 0. in the case of a framing error, a break can also be detected by reading the value of the rxd pin. 2. scif status check and receive data read : read the serial status register (scssr) and check that rdf = 1, then read the receive data in the receive fifo data register (scfrdr), read 1 from the rdf flag, and then clear the rdf flag to 0. the transition of the rdf flag from 0 to 1 can be identified by an rxi interrupt. 3. serial reception continuation procedure: to continue serial reception, read at least the receive trigger set number of receive data bytes from scfrdr, read 1 from the rdf flag, then clear the rdf flag to 0. the number of receive data bytes in scfrdr can be ascertained by reading the lower bits of scfdr.
rev. 5.00, 09/03, page 546 of 760 start of reception read orer, per, fer flags in scssr all data received? end of reception no yes per v fer v orer = 1? rdf = 1? yes yes clear re bit in scscr to 0 no no read rdf flag in scssr error handling read receive data from scfrdr, and clear rdf flag in scssr to 0 (1) (2) (3) note: numbers in parentheses refer to steps in the preceding procedure description. figure 16.9 sample flowchart for receiving serial data
rev. 5.00, 09/03, page 547 of 760 1. whether a framing error or parity error has occurred in the receive data read from scfrdr can be ascertained from the fer and per bits in scssr. 2. when a break signal is received, receive data is not transferred to scfrdr while the brk flag is set. however, note that the last data in scfrdr is h'00 and the break data in which a framing error occurred is stored. error handling end brk = 1? dr = 1? er = 1? yes yes yes clear dr, er, brk flags in scssr to 0 no no no receive error handling break processing read receive data from scfrdr (1) (2) figure 16.10 sample flowchart for receiving serial data (cont)
rev. 5.00, 09/03, page 548 of 760 in serial reception, the scif operates as described below. 1. the scif monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. the received data is stored in scrsr in lsb-to-msb order. 3. the parity bit and stop bit are received. after receiving these bits, the scif carries out the following checks. a. stop bit check: the scif checks whether the stop bit is 1. if there are two stop bits, only the first is checked. b. the scif checks whether receive data can be transferred from the receive shift register (scrsr) to scfrdr. c. break check: the scif checks that the brk flag is 0, indicating that the break state is not set. if all the above checks are passed, the receive data is stored in scfrdr. note: reception is not suspended when a receive error occurs. 4. if the rie bit in scsr is set to 1 when the rdf or dr flag changes to 1, a receive-fifo-data- full interrupt (rxi) request is generated. if the rie bit in scsr is set to 1 when the er flag changes to 1, a receive-error interrupt (eri) request is generated. if the rie bit in scsr is set to 1 when the brk flag changes to 1, a break reception interrupt (bri) request is generated.
rev. 5.00, 09/03, page 549 of 760 figure 16.11 shows an example of the operation for reception. rdf fer eri interrupt request generated by receive error one frame data read and rdf flag read as 1 then cleared to 0 by rxi interrupt handler rxi interrupt request 01 1 1 0/1 0 1 parity bit parity bit serial data start bit data stop bit start bit data stop bit idle (mark) state d 0 d 1 d 7 d 0 d 1 d 7 0/1 figure 16.11 example of scif receive operation (8-bit data, parity, one stop bit) 5. when modem control is enabled, the rts signal is output when scfrdr is empty. when rts is 0, reception is possible. when rts is 1, this indicates that scfrdr is full and reception is not possible. figure 16.12 shows an example of the operation when modem control is used. 0 0/1 0 1 rts parity bit serial data rxd start bit start d 0 d 1 d 2 d 7 figure 16.12 example of operation using modem control ( rts rts rts rts )
rev. 5.00, 09/03, page 550 of 760 16.4 scif interrupts the scif has four interrupt sources: transmit-fifo-data-empty (txi), receive-error (eri), receive-data-full (rxi), and break (bri). table 16.10 shows the interrupt sources and their order of priority. the interrupt sources are enabled or disabled by means of the tie and rie bits in scscr. a separate interrupt request is sent to the interrupt controller for each of these interrupt sources. when the tdfe flag in the serial status register (scssr) is set to 1, a txi interrupt request is generated. the dmac can be activated and data transfer performed when this interrupt is generated. when data exceeding the transmit trigger number is written to the transmit data register (scftdr) by the dmac, 1 is read from the tdfe flag, after which 0 is written to it to clear it. when the rdf flag in scssr is set to 1, an rxi interrupt request is generated. the dmac can be activated and data transfer performed when the rdf flag in scssr is set to 1. when receive data less than the receive trigger number is read from the receive data register (scfrdr) by the dmac, 1 is read from the rdf flag, after which 0 is written to it to clear it. when the er flag in scssr is set to 1, an eri interrupt request is generated. when the brk flag in scssr is set to 1, a bri interrupt request is generated. the txi interrupt indicates that transmit data can be written, and the rxi interrupt indicates that there is receive data in scfrdr. table 16.10 scif interrupt sources interrupt source description dmac activation priority on reset release eri interrupt initiated by receive error flag (er) not possible high rxi interrupt initiated by receive data fifo full flag (rdf) or data ready flag (dr) possible (rdf only) bri interrupt initiated by break flag (brk) not possible txi interrupt initiated by transmit fifo data empty flag (tdfe) possible low see section 4, exception handling, for priorities and the relationship to non-scif interrupts.
rev. 5.00, 09/03, page 551 of 760 16.5 usage notes note the following when using the scif. 1. scftdr writing and tdfe flag: the tdfe flag in the serial status register (scssr) is set when the number of transmit data bytes written in the transmit fifo data register (scftdr) has fallen below the transmit trigger number set by bits ttrg1 and ttrg0 in the fifo control register (scfcr). after tdfe is set, transmit data up to the number of empty bytes in scftdr can be written, allowing efficient continuous transmission. however, if the number of data bytes written to scftdr is equal to or less than the transmit trigger number, the tdfe flag will be set to 1 again even after having been cleared to 0. tdfe clearing should therefore be carried out after data exceeding the specified transmit trigger number has been written to scftdr. the number of transmit data bytes in scftdr can be found from the upper 8 bits of the fifo data count register (scfdr). 2. scfrdr reading and rdf flag: the rdf flag in the serial status register (scssr) is set when the number of receive data bytes in the receive fifo data register (scfrdr) has become equal to or greater than the receive trigger number set by bits rtrg1 and rtrg0 in the fifo control register (scfcr). after rdf is set, receive data equivalent to the trigger number can be read from scfrdr, allowing efficient continuous reception. however, if the number of data bytes in scfrdr exceeds the trigger number, the rdf flag will be set to 1 again even after having been cleared to 0. rdf should therefore be cleared to 0 after being read as 1 after all the receive data has been read. the number of receive data bytes in scfrdr can be found from the lower 8 bits of the fifo data count register (scfdr). 3. break detection and processing: break signals can be detected by reading the rxd pin directly when a framing error (fer) is detected. in the break state the input from the rxd pin consists of all 0s, so the fer flag is set and the parity error flag (per) may also be set. note that, although transfer of receive data to scfrdr is halted in the break state, the scif receiver continues to operate, so if the brk flag is cleared to 0 it will be set to 1 again. 4. sending a break signal: the i/o condition and level of the txd pin are determined by the scp4dt bit in the port sc data register (scpdr) and bits scp4md0 and scp4md1 in the port sc control register (scpcr). this feature can be used to send a break signal. to send a break signal during serial transmission, clear the scp4dt bit to 0 (designating low level), then set the scp4md0 and scp4md1 bits to 0 and 1, respectively, and finally clear the te bit to 0 (halting transmission). when the te bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, and 0 is output from the txd pin.
rev. 5.00, 09/03, page 552 of 760 5. tend flag and te bit processing: the tend flag is set to 1 during transmission of the stop bit of the last data. consequently, if the te bit is cleared to 0 immediately after setting of the tend flag has been confirmed, the stop bit will be in the process of transmission and will not be transmitted normally. therefore, the te bit should not be cleared to 0 for at least 0.5 serial clock cycles (or 1.5 cycles if two stop bits are used) after setting of the tend flag is confirmed. 6. receive data sampling timing and receive margin: the scif operates on a base clock with a frequency of 16 times the transfer rate. in reception, the scif synchronizes internally with the fall of the start bit, which it samples on the base clock. receive data is latched at the rising edge of the eighth base clock pulse. the timing is shown in figure 16.13. 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 base clock receive data (rxd) synchro- nization sampling timing data sampling timing 8 clocks 16 clocks start bit ? 7.5 clocks +7.5 clocks d0 d1 figure 16.13 receive data sampling timing in asynchronous mode the receive margin in asynchronous mode can therefore be expressed as shown in equation 1. equation 1: m = 0.5 ? 1 2n d ? 0.5 n ? (l ? 0.5) f ? (1 + f) 100% where: m: receive margin (%) n: ratio of clock frequency to bit rate (n = 16) d: clock duty cycle (d = 0 to 1.0) l: frame length (l = 9 to 12) f: absolute deviation of clock frequency from equation 1, if f = 0 and d = 0.5, the receive margin is 46.875%, as given by equation 2.
rev. 5.00, 09/03, page 553 of 760 equation 2: when d = 0.5 and f = 0: m = (0.5 ? 1/(2 16)) 100 % = 46.875 % this is a theoretical value. a reasonable margin to allow in system designs is 20% to 30%.
rev. 5.00, 09/03, page 554 of 760
rev. 5.00, 09/03, page 555 of 760 section 17 irda 17.1 overview the sh7709s has an on-chip infrared data association (irda) interface which is based on the irda 1.0 system and can perform infrared communication. it also can be used as the scif by making register settings. 17.1.1 features ? conforms to the irda 1.0 system ? asynchronous serial communication ? data length: 8 bits ? stop bit length: 1 bit ? parity bit: none ? on-chip 16-stage fifo buffers for both transmit and receive operations ? on-chip baud rate generator with selectable bit rates ? guard functions to protect the receiver during transmission ? clock supply halted to reduce power consumption when not using the irda interface
rev. 5.00, 09/03, page 556 of 760 17.1.2 block diagram figure 17.1 shows a block diagram of the irda. scif clock input txd transfer clock rxd switching irda/scif irda sck txd1 rxd1 modulation unit demodulation unit legend scif: serial communication interface with fifo figure 17.1 block diagram of irda
rev. 5.00, 09/03, page 557 of 760 figures 17.2 to 17.4 show the irda i/o port pins. scif pin i/o and data control is performed by bits 7 to 4 of scpcr and bits 3 and 2 of scpdr. for details, see section 14.2.8, sc port control register (scpcr)/sc port data register (scpdr). internal data bus output enable clock input enable irda serial clock output serial clock input r scp3md0 pcrw reset c q q d r scp3md1 pcrw reset c qd r scp3dt1 pdrw reset scpt[3]/sck1 c d pdrw: legend scpdr write pdrr: pcrw: scpdr read scpcr write pdrr * note: * when reading the sck1 pin, the cke1 and cke0 bits in scscr to 0, and set the scp3md1 bit in scpcr to 1 (see section 14.2.8, sc port control register (scpcr)/sc port data register (scpdr)). figure 17.2 scpt[3]/sck1 pin
rev. 5.00, 09/03, page 558 of 760 internal data bus output enable irda serial transfer output q r scp2dt1 pdrw reset scpt[2]/txd1 c d pcrw: pdrw: legend scpcr write scpdr write r scp2md0 pcrw reset c q d r scp2md1 pcrw reset c qd figure 17.3 scpt[2]/txd1 pin
rev. 5.00, 09/03, page 559 of 760 irda serial receive data internal data bus pdrr * scpt[2]/rxd1 legend pdrr: scpdr read note: * when reading the rxd1 pin, set the re bit in scscr to 1. figure 17.4 scpt[2]/rxd1 pin 17.1.3 pin configuration the irda has the serial pins summarized in table 17.1. table 17.1 irda pins pin name signal name i/o function serial clock pin sck1 i/o clock i/o receive data pin rxd1 input receive data input transmit data pin txd1 output transmit data output note: clock input from the serial clock pin cannot be set in irda mode.
rev. 5.00, 09/03, page 560 of 760 17.1.4 register configuration the irda has the internal registers shown in table 17.2. these registers select irda or scif mode, specify the data format and a bit rate, and control the transmit and receive units. table 17.2 irda registers register name abbreviation r/w initial value address access size serial mode register 1 scsmr1 r/w h'00 h'04000140 (h'a4000140) * 2 8 bits bit rate register 1 scbrr1 r/w h'ff h'04000142 (h'a4000142) * 2 8 bits serial control register 1 scscr1 r/w h'00 h'04000144 (h'a4000144) * 2 8 bits transmit fifo data register 1 scftdr1 w ? h'04000146 (h'a4000146) * 2 8 bits serial status register 1 scssr1 r/(w) * 1 h'0060 h'04000148 (h'a4000148) * 2 16 bits receive fifo data register 1 scfrdr1 r undefined h'0400014a (h'a400014a) * 2 8 bits fifo control register 1 scfcr1 r/w h'00 h'0400014c (h'a400014c) * 2 8 bits fifo data count register 1 scfdr1 r h'0000 h'0400014e (h'a400014e) * 2 16 bits notes: these registers are located in area 1 of physical space. therefore, when the cache is on, either access these registers from the p2 area of logical space or else make an appropriate setting using the mmu so that these registers are not cached. 1. only 0 can be written to clear the flag. 2. when address translation by the mmu does not apply, the address in parentheses should be used.
rev. 5.00, 09/03, page 561 of 760 17.2 register description specifications of the registers in the irda are the same as those in the scif except for the serial mode register described below. therefore, refer to section 16, serial communication interface with fifo (scif), for details of these registers. 17.2.1 serial mode register (scsmr) bit:76543210 irmod ick3 ick2 ick1 ick0 psel cks1 cks0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w scsmr is an 8-bit register that selects irda or scif mode, specifies the scif serial communication format, selects the irda output pulse width, and selects the baud rate generator clock source. this module operates as irda when the irmod bit is set to 1. at this time, bits 3 to 6 are fixed at 0. this register functions in the same way as the scsmr register in the scif when the irmod bit is cleared to 0; therefore, this module can also operate as an scif. scsmr is initialized to h'00 by a power-on reset or manual reset, when the module is stopped by the module standby function, and in standby mode. bit 7?irda mode (irmod): selects whether this module operates as an irda serial communication interface or as an scif. bit 7: irmod description 0 operates as an scif (initial value) 1 * operates as an irda note: * do not set the cke1 bit in the serial control register (scscrt) to 1 if the irmcd bit is set to 1.
rev. 5.00, 09/03, page 562 of 760 bits 6 to 3?ir clock select bits (ick3 to ick0) bit 2?output pulse width select (psel): psel selects an irda output pulse width that is 3/16 of the bit length for 115 kbps or 3/16 of the bit length for the selected baud rate. the ir clock select bits should be set properly to fix the output pulse width at 3/16 of the bit length for 115 kbps by setting the psel bit to 1. bit 6 bit 5 bit 4 bit 3 bit 2 description ick3 ick2 ick1 ick0 psel pulse width: 3/16 of 115 kbps bit length ick3 ick2 ick1 ick0 1 don?t care don?t care don?t care don?t care 0 pulse width: 3/16 of bit length it is necessary to generate a fixed clock pulse, irclk, by dividing the p clock by 1/2n + 2 (with the value of n determined by the setting of ick3?ick0). example: p clock: 14.7456 mhz irclk: 921.6 khz (fixed) n: setting of ick3?ick0 (0 n 15) ? 1 7 n p 2xirclk accordingly, n is 7. bits 1 and 0?clock select 1 and 0 (cks1, cks0): select the internal baud rate generator clock source. p , p /4, p /16, or p /64 can be selected by setting the cks1 and cks0 bits. refer to section 14.2.9, bit rate register (scbrr), for the relationship between the clock source, the bit rate register set value, and the baud rate. bit 1: cks1 bit 0: cks0 description 00p clock (initial value) 01p /4 clock 10p /16 11p /64 note: p : peripheral clock
rev. 5.00, 09/03, page 563 of 760 17.3 operation description the irda module can perform infrared communication conforming to irda 1.0 by connecting infrared transmit/receive units. the serial communication interface unit includes a 16-stage fifo buffer in the transmit unit and the receive unit, allowing cpu overhead to be reduced and continuous high-speed communication to be performed. this module also supports dmac data transfer. the irda module differs from the scif described in section 16, serial communication interface with fifo (scif) in that it does not include modem control signals rts and cts. refer to section 16.3, operation, for scif mode operation. 17.3.1 overview the irda module modifies txd/rxd transmit/receive data waveforms to satisfy the irda 1.0 specification for infrared communication. in the irda 1.0 specification, communication is first performed at a speed of 9600 bps, and the communication speed is changed. however, the communication rate cannot be automatically changed in this module, so the communication speed should be confirmed, and the appropriate speed set for this module by software. note: in irda mode, reception cannot be performed when the te bit in the serial control register (scscr) is set to 1 (enabling transmission). when performing reception, clear the te bit in scscr to 0. as the sh7709s's rxd1 pin is active-high in irda mode, a (schmidt) inverter must be inserted when connecting an active-low irda module. the rxd1 pin is active-low in scif mode. 17.3.2 transmitting in the case of a serial output signal (uart frame) from the scif, its waveforms are modified and the signal is converted into the ir frame serial output signal by the irda module, as shown in figure 17.5. when serial data is 0, a pulse of 3/16 the ir frame bit width is generated and output. when serial data is 1, no pulse is output. an infrared led is driven by this signal demodulated to 3/16 width.
rev. 5.00, 09/03, page 564 of 760 17.3.3 receiving received 3/16 ir frame bit-width pulses are demodulated and converted to a uart frame, as shown in figure 17.5. demodulation to 0 is performed for pulse output, and demodulation to 1 is performed for no pulse output. uart frame data ir frame data receive transmit stop bit stop bit start bit start bit bit cycle 3/16-bit cycle pulse width 01 01 0 0 11 0 1 01 01 0 01 1 01 figure 17.5 transmit/receive operation
rev. 5.00, 09/03, page 565 of 760 section 18 pin function controller 18.1 overview the pin function controller (pfc) is composed of registers for selecting the function of multiplexed pins and the input/output direction. the pin function and input/output direction can be selected for each pin individually without regard to the operating mode of the chip. table 18.1 lists the multiplexed pins. table 18.1 list of multiplexed pins port port function (related module) other function (related module) a pta7 input/output (port) d23 input/output (data bus) a pta6 input/output (port) d22 input/output (data bus) a pta5 input/output (port) d21 input/output (data bus) a pta4 input/output (port) d20 input/output (data bus) a pta3 input/output (port) d19 input/output (data bus) a pta2 input/output (port) d18 input/output (data bus) a pta1 input/output (port) d17 input/output (data bus) a pta0 input/output (port) d16 input/output (data bus) b ptb7 input/output (port) d31 input/output (data bus) b ptb6 input/output (port) d30 input/output (data bus) b ptb5 input/output (port) d29 input/output (data bus) b ptb4 input/output (port) d28 input/output (data bus) b ptb3 input/output (port) d27 input/output (data bus) b ptb2 input/output (port) d26 input/output (data bus) b ptb1 input/output (port) d25 input/output (data bus) b ptb0 input/output (port) d24 input/output (data bus) c ptc7 input/output (port)/pint7 input (intc) mcs7 output (bsc) c ptc6 input/output (port)/pint6 input (intc) mcs6 output (bsc) c ptc5 input/output (port)/pint5 input (intc) mcs5 output (bsc) c ptc4 input/output (port)/pint4 input (intc) mcs4 output (bsc) c ptc3 input/output (port)/pint3 input (intc) mcs3 output (bsc) c ptc2 input/output (port)/pint2 input (intc) mcs2 output (bsc) c ptc1 input/output (port)/pint1 input (intc) mcs1 output (bsc)
rev. 5.00, 09/03, page 566 of 760 port port function (related module) other function (related module) c ptc0 input/output (port)/pint0 input (intc) mcs0 output (bsc) d ptd7 input/output (port) dack1 output (dmac) d ptd6 input (port) dreq1 input (dmac) d ptd5 input/output (port) dack0 output (dmac) d ptd4 input (port) dreq0 input (dmac) d ptd3 input/output (port) wakeup output (wtc) d ptd2 input/output (port) resetout output d ptd1 input/output (port) drak0 output (dmac) d ptd0 input/output (port) drak1 output (dmac) e pte7 input/output (port) audsync output (aud) e pte6 input/output (port) ? e pte5 input/output (port) ce2b output (pcmcia) e pte4 input/output (port) ce2a output (pcmcia) e pte3 input/output (port) ? e pte2 input/output (port) ras3u output (bsc) e pte1 input/output (port) ? e pte0 input/output (port) tdo output (udi) f ptf7 input (port)/pint15 input (intc) trst input (aud, udi) f ptf6 input (port)/pint14 input (intc) tms input (udi) f ptf5 input (port)/pint13 input (intc) td1 input (udi) f ptf4 input (port)/pint12 input (intc) tck input (udi) f ptf3 input (port)/pint11 input (intc) irls3 input (intc) f ptf2 input (port)/pint10 input (intc) irls2 input (intc) f ptf1 input (port)/pint9 input (intc) irls1 input (intc) f ptf0 input (port)/pint8 input (intc) irls0 input (intc) g ptg7 input (port) iois16 input (pcmcia) g ptg6 input (port) asemd0 input (aud, udi) g ptg5 input (port) asebrkak output (aud) g ptg4 input (port) ckio2 output (cpg) g ptg3 input (port) audata3 output (aud) g ptg2 input (port) audata2 output (aud)
rev. 5.00, 09/03, page 567 of 760 port port function (related module) other function (related module) g ptg1 input (port) audata1 output (aud) g ptg0 input (port) audata0 output (aud) h pth7 input/output (port) tclk input/output (tmu) h pth6 input (port) audck input (aud) h pth5 input (port) adtrg input (adc) h pth4 input (port)/irq4 input (intc) irq4 input (intc) h pth3 input (port)/irq3 input (intc) irq3 input (intc) h pth2 input (port)/irq2 input (intc) irq2 input (intc) h pth1 input (port)/irq1 input (intc) irq1 input (intc) h pth0 input (port)/irq0 input (intc) irq0 input (intc) j ptj7 input/output (port) status1 output (cpg) j ptj6 input/output (port) status0 output (cpg) j ptj5 input/output (port) ? j ptj4 input/output (port) ? j ptj3 input/output (port) casu output (bsc) j ptj2 input/output (port) casl output (bsc) j ptj1 input/output (port) ? j ptj0 input/output (port) ras3l output (bsc) k ptk7 input/output (port) we3 output (bsc)/dqmuu output (bsc)/ iciowr output (bsc) k ptk6 input/output (port) we2 output (bsc)/dqmul output (bsc)/ iciord output (bsc) k ptk5 input/output (port) cke output (bsc) k ptk4 input/output (port) bs output (bsc) k ptk3 input/output (port) cs5 output (bsc)/ ce1a output (bsc) k ptk2 input/output (port) cs4 output (bsc) k ptk1 input/output (port) cs3 output (bsc) k ptk0 input/output (port) cs2 output (bsc) l ptl7 input (port) an7 input (adc)/da0 output (dac) l ptl6 input (port) an6 input (adc)/da1 output (dac) l ptl5 input (port) an5 input (adc)
rev. 5.00, 09/03, page 568 of 760 port port function (related module) other function (related module) l ptl4 input (port) an4 input (adc) l ptl3 input (port) an3 input (adc) l ptl2 input (port) an2 input (adc) l ptl1 input (port) an1 input (adc) l ptl0 input (port) an0 input (adc) scpt scpt7 input (port)/irq5 input (intc) cts2 input (uart ch 3)/irq5 input (intc) scpt scpt6 input/output (port) rts2 output (uart ch 3) scpt scpt5 input/output (port) sck2 input/output (uart ch 3) scpt scpt4 input (port) rxd2 input (uart ch 3) scpt4 output (port) txd2 output (uart ch 3) scpt scpt3 input/output (port) sck1 input/output (uart ch 2) scpt scpt2 input (port) rxd1 input (uart ch 2) scpt2 output (port) txd1 output (uart ch 2) scpt scpt1 input/output (port) sck0 input/output (uart ch 1) scpt scpt0 input (port) rxd0 input (uart ch 1) scpt0 output (port) txd0 output (uart ch 1) note: scpt0, scpt2, and scpt4 have the same data register to be accessed although they have different input pins and output pins.
rev. 5.00, 09/03, page 569 of 760 18.2 register configuration table 18.2 summarizes the registers of the pin function controller. table 18.2 pin function controller registers name abbreviation r/w initial value address access size port a control register pacr r/w h'0000 h'04000100 (h'a4000100) * 16 port b control register pbcr r/w h'0000 h'04000102 (h'a4000102) * 16 port c control register pccr r/w h'aaaa h'04000104 (h'a4000104) * 16 port d control register pdcr r/w h'aa8a h'04000106 (h'a4000106) * 16 port e control register pecr r/w h'aaaa/h'2aa8 h'04000108 (h'a4000108) * 16 port f control register pfcr r/w h'aaaa/h'00aa h'0400010a (h'a400010a) * 16 port g control register pgcr r/w h'aaaa/h'a200 h'0400010c (h'a400010c) * 16 port h control register phcr r/w h'aaaa/h'8aaa h'0400010e (h'a400010e) * 16 port j control register pjcr r/w h'0000 h'04000110 (h'a4000110) * 16 port k control register pkcr r/w h'0000 h'04000112 (h'a4000112) * 16 port l control register plcr r/w h'0000 h'04000114 (h'a4000114) * 16 sc port control register scpcr r/w h'a888 h'04000116 (h'a4000116) * 16 notes: 1. the initial value of the port e, f, g, and h control registers depends on the state of the asemd0 pin. if a low level is input at the asemd0 pin while the resetp pin is asserted, ase mode is entered; if a high level is input, normal mode is entered. see section 22, user debugging interface (udi), for more information on the udi. 2. these registers are located in area 1 of physical space. therefore, when the cache is on, either access these registers from the p2 area of logical space or else make an appropriate setting using the mmu so that these registers are not cached. * when address translation by the mmu does not apply, the address in parentheses should be used.
rev. 5.00, 09/03, page 570 of 760 18.3 register descriptions 18.3.1 port a control register (pacr) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pa7 md1 pa7 md0 pa6 md1 pa6 md0 pa5 md1 pa5 md0 pa4 md1 pa4 md0 pa3 md1 pa3 md0 pa2 md1 pa2 md0 pa1 md1 pa1 md0 pa0 md1 pa0 md0 initial value:0000000000000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w the port a control register (pacr) is a 16-bit readable/writable register that selects the pin functions. pacr is initialized to h'0000 by a power-on reset, but is not initialized by a manual reset, in standby mode, or in sleep mode. bits 15 and 14?pa7 mode 1 and 0 (pa7md1, pa7md0) bits 13 and 12?pa6 mode 1 and 0 (pa6md1, pa6md0) bits 11 and 10?pa5 mode 1 and 0 (pa5md1, pa5md0) bits 9 and 8?pa4 mode 1 and 0 (pa4md1, pa4md0) bits 7 and 6?pa3 mode 1 and 0 (pa3md1, pa3md0) bits 5 and 4?pa2 mode 1 and 0 (pa2md1, pa2md0) bits 3 and 2?pa1 mode 1 and 0 (pa1md1, pa1md0) bits 1 and 0?pa0 mode 1 and 0 (pa0md1, pa0md0) these bits select the pin functions and perform input pull-up mos control. bit (2n + 1) bit 2n panmd1 panmd0 pin function 0 0 other function (see table 18.1) (initial value) 0 1 port output 1 0 port input (pull-up mos: on) 1 1 port input (pull-up mos: off) (n = 0 to 7)
rev. 5.00, 09/03, page 571 of 760 18.3.2 port b control register (pbcr) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pb7 md1 pb7 md0 pb6 md1 pb6 md0 pb5 md1 pb5 md0 pb4 md1 pb4 md0 pb3 md1 pb3 md0 pb2 md1 pb2 md0 pb1 md1 pb1 md0 pb0 md1 pb0 md0 initial value:0000000000000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w the port b control register (pbcr) is a 16-bit readable/writable register that selects the pin functions. pbcr is initialized to h'0000 by a power-on reset, but is not initialized by a manual reset, in standby mode, or in sleep mode. bits 15 and 14?pb7 mode 1 and 0 (pb7md1, pb7md0) bits 13 and 12?pb6 mode 1 and 0 (pb6md1, pb6md0) bits 11 and 10?pb5 mode 1 and 0 (pb5md1, pb5md0) bits 9 and 8?pb4 mode 1 and 0 (pb4md1, pb4md0) bits 7 and 6?pb3 mode 1 and 0 (pb3md1, pb3md0) bits 5 and 4?pb2 mode 1 and 0 (pb2md1, pb2md0) bits 3 and 2?pb1 mode 1 and 0 (pb1md1, pb1md0) bits 1 and 0?pb0 mode 1 and 0 (pb0md1, pb0md0) these bits select the pin functions and perform input pull-up mos control. bit (2n + 1) bit 2n pbnmd1 pbnmd0 pin function 0 0 other function (see table 18.1) (initial value) 0 1 port output 1 0 port input (pull-up mos: on) 1 1 port input (pull-up mos: off) (n = 0 to 7)
rev. 5.00, 09/03, page 572 of 760 18.3.3 port c control register (pccr) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pc7 md1 pc7 md0 pc6 md1 pc6 md0 pc5 md1 pc5 md0 pc4 md1 pc4 md0 pc3 md1 pc3 md0 pc2 md1 pc2 md0 pc1 md1 pc1 md0 pc0 md1 pc0 md0 initial value:1010101010101010 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w the port c control register (pccr) is a 16-bit readable/writable register that selects the pin functions. pccr is initialized to h'aaaa by a power-on reset, but is not initialized by a manual reset, in standby mode, or in sleep mode. bits 15 and 14?pc7 mode 1 and 0 (pc7md1, pc7md0) bits 13 and 12?pb6 mode 1 and 0 (pc6md1, pc6md0) bits 11 and 10?pc5 mode 1 and 0 (pc5md1, pc5md0) bits 9 and 8?pc4 mode 1 and 0 (pc4md1, pc4md0) bits 7 and 6?pc3 mode 1 and 0 (pc3md1, pc3md0) bits 5 and 4?pc2 mode 1 and 0 (pc2md1, pc2md0) bits 3 and 2?pc1 mode 1 and 0 (pc1md1, pc1md0) bits 1 and 0?pc0 mode 1 and 0 (pc0md1, pc0md0) these bits select the pin functions and perform input pull-up mos control. bit (2n + 1) bit 2n pcnmd1 pcnmd0 pin function 0 0 other function (see table 18.1) 0 1 port output 1 0 port input (pull-up mos: on) (initial value) 1 1 port input (pull-up mos: off) (n = 0 to 7)
rev. 5.00, 09/03, page 573 of 760 18.3.4 port d control register (pdcr) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pd7 md1 pd7 md0 pd6 md1 pd6 md0 pd5 md1 pd5 md0 pd4 md1 pd4 md0 pd3 md1 pd3 md0 pd2 md1 pd2 md0 pd1 md1 pd1 md0 pd0 md1 pd0 md0 initial value:1010101010001010 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w the port d control register (pdcr) is a 16-bit readable/writable register that selects the pin functions. pdcr is initialized to h'aa8a by a power-on reset, but is not initialized by a manual reset, in standby mode, or in sleep mode. bits 15 and 14?pd7 mode 1 and 0 (pd7md1, pd7md0) bits 11 and 10?pd5 mode 1 and 0 (pd5md1, pd5md0) bits 7 and 6?pd3 mode 1 and 0 (pd3md1, pd3md0) bits 5 and 4?pd2 mode 1 and 0 (pd2md1, pd2md0) bits 3 and 2?pd1 mode 1 and 0 (pd1md1, pd1md0) bits 1 and 0?pd0 mode 1 and 0 (pd0md1, pd0md0) these bits select the pin functions and perform input pull-up mos control. bit (2n + 1) bit 2n pdnmd1 pdnmd0 pin function 0 0 other function (see table 18.1) (initial value) (n = 2) 0 1 port output 1 0 port input (pull-up mos: on) (initial value) (n = 0, 1, 3, 5, 7) 1 1 port input (pull-up mos: off) (n = 0 to 3, 5, 7) bits 13 and 12?pd6 mode 1 and 0 (pd6md1, pd6md0) bits 9 and 8?pd4 mode 1 and 0 (pd4md1, pd4md0) these bits select the pin functions and perform input pull-up mos control. bit (2n + 1) bit 2n pdnmd1 pdnmd0 pin function 0 0 other function (see table 18.1) 0 1 reserved 1 0 port input (pull-up mos: on) (initial value) 1 1 port input (pull-up mos: off) (n = 4, 6)
rev. 5.00, 09/03, page 574 of 760 18.3.5 port e control register (pecr) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pe7 md1 pe7 md0 pe6 md1 pe6 md0 pe5 md1 pe5 md0 pe4 md1 pe4 md0 pe3 md1 pe3 md0 pe2 md1 pe2 md0 pe1 md1 pe1 md0 pe0 md1 pe0 md0 initial value:1/001010101010101/00 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w the port e control register (pecr) is a 16-bit readable/writable register that selects the pin functions. pecr is initialized to h'aaaa ( asemd0 = 1) or h'2aa8 ( asemd0 = 0) by a power-on reset, but is not initialized by a manual reset, in software standby mode, or in sleep mode. bits 15 and 14?pe7 mode 1 and 0 (pe7md1, pe7md0) bits 13 and 12?pe6 mode 1 and 0 (pe6md1, pe6md0) bits 11 and 10?pe5 mode 1 and 0 (pe5md1, pe5md0) bits 9 and 8?pe4 mode 1 and 0 (pe4md1, pe4md0) bits 7 and 6?pe3 mode 1 and 0 (pe3md1, pe3md0) bits 5 and 4?pe2 mode 1 and 0 (pe2md1, pe2md0) bits 3 and 2?pe1 mode 1 and 0 (pe1md1, pe1md0) bits 1 and 0?pe0 mode 1 and 0 (pe0md1, pe0md0) these bits select the pin functions and perform input pull-up mos control. bit (2n + 1) bit 2n penmd1 penmd0 pin function 0 0 reserved (n = 0, 7) (see table 18.1) (initial value) ( asemd0 = 0) 0 1 port output 1 0 port input (pull-up mos: on) (initial value) ( asemd0 = 1) 1 1 port input (pull-up mos: off) (n = 0, 7) bit (2n + 1) bit 2n penmd1 penmd0 pin function 0 0 other function (n = 2, 4, 5) (see table 18.1), reserved (n = 1, 3, 6) 0 1 port output 1 0 port input (pull-up mos: on) (initial value) 1 1 port input (pull-up mos: off) (n = 1 to 6)
rev. 5.00, 09/03, page 575 of 760 18.3.6 port f control register (pfcr) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pf7 md1 pf7 md0 pf6 md1 pf6 md0 pf5 md1 pf5 md0 pf4 md1 pf4 md0 pf3 md1 pf3 md0 pf2 md1 pf2 md0 pf1 md1 pf1 md0 pf0 md1 pf0 md0 initial value: 1/0 0 1/0 0 1/0 0 1/0 0 1 0 1 0 1 0 1 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w the port f control register (pfcr) is a 16-bit readable/writable register that selects the pin functions. pfcr is initialized to h'aaaa (asemd0 = 1) or h'00aa (asemd0 = 0) by a power- on reset, but is not initialized by a manual reset, in standby mode, or in sleep mode. bits 15 and 14?pf7 mode 1 and 0 (pf7md1, pf7md0) bits 13 and 12?pf6 mode 1 and 0 (pf6md1, pf6md0) bits 11 and 10?pf5 mode 1 and 0 (pf5md1, pf5md0) bits 9 and 8?pf4 mode 1 and 0 (pf4md1, pf4md0) bits 7 and 6?pf3 mode 1 and 0 (pf3md1, pf3md0) bits 5 and 4?pf2 mode 1 and 0 (pf2md1, pf2md0) bits 3 and 2?pf1 mode 1 and 0 (pf1md1, pf1md0) bits 1 and 0?pf0 mode 1 and 0 (pf0md1, pf0md0) these bits select the pin functions and perform input pull-up mos control. bit (2n + 1) bit 2n pfnmd1 pfnmd0 pin function 0 0 other function (see table 18.1) (initial value) ( asemd0 = 0) 0 1 reserved 1 0 port input (pull-up mos: on) (initial value) ( asemd0 = 1) 1 1 port input (pull-up mos: off) (n = 4 to 7) bit (2n + 1) bit 2n pfnmd1 pfnmd0 pin function 0 0 other function (see table 18.1) 0 1 reserved 1 0 port input (pull-up mos: on) (initial value) 1 1 port input (pull-up mos: off) (n = 0 to 3)
rev. 5.00, 09/03, page 576 of 760 18.3.7 port g control register (pgcr) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pg7 md1 pg7 md0 pg6 md1 pg6 md0 pg5 md1 pg5 md0 pg4 md1 pg4 md0 pg3 md1 pg3 md0 pg2 md1 pg2 md0 pg1 md1 pg1 md0 pg0 md1 pg0 md0 initial value: 1 0 1 0 1/0 0 1 0 1/0 0 1/0 0 1/0 0 1/0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w the port g control register (pgcr) is a 16-bit readable/writable register that selects the pin functions. pgcr is initialized to h'aaaa ( asemd0 = 1) or h'a200 ( asemd0 = 0) by a power- on reset, but is not initialized by a manual reset, in standby mode, or in sleep mode. bits 15 and 14?pg7 mode 1 and 0 (pg7md1, pg7md0) bits 13 and 12?pg6 mode 1 and 0 (pg6md1, pg6md0) bits 11 and 10?pg5 mode 1 and 0 (pg5md1, pg5md0) bits 9 and 8?pg4 mode 1 and 0 (pg4md1, pg4md0) bits 7 and 6?pg3 mode 1 and 0 (pg3md1, pg3md0) bits 5 and 4?pg2 mode 1 and 0 (pg2md1, pg2md0) bits 3 and 2?pg1 mode 1 and 0 (pg1md1, pg1md0) bits 1 and 0?pg0 mode 1 and 0 (pg0md1, pg0md0) these bits select the pin functions and perform input pull-up mos control.
rev. 5.00, 09/03, page 577 of 760 bit (2n + 1) bit 2n pgnmd1 pgnmd0 pin function 0 0 other function (n = 1?3, 5) (see table 18.1) (initial value) ( asemd0 = 0) 0 1 reserved 1 0 port input (pull-up mos: on) (initial value) ( asemd0 = 1) 1 1 port input (pull-up mos: off) (n = 1 to 3, 5) bit (2n + 1) bit 2n pgnmd1 pgnmd0 pin function 0 0 other function (n = 4, 6, 7) (see table 18.1) 0 1 reserved 1 0 port input (pull-up mos: on) (initial value) * 1 1 port input (pull-up mos: off) (n = 4, 6, 7) note: * when n = 6, asemd0 /ptg6 functions as asemd0 input while the reset signal is asserted, and as ptg6 input immediately after the reset signal is nagated. bit 3 bit 0 pg1md1 * pg0md0 pin function 0 0 other function (see table 18.1) (initial value) asemd0 = 0 0 1 reserved 1 0 port input (pull-up mos: on) (initial value) asemd0 = 1 1 1 port input (pull-up mos: off) note: * controlled by pg1md1 (bit 3), not pg0md1 (bit 1). 18.3.8 port h control register (phcr) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ph7 md1 ph7 md0 ph6 md1 ph6 md0 ph5 md1 ph5 md0 ph4 md1 ph4 md0 ph3 md1 ph3 md0 ph2 md1 ph2 md0 ph1 md1 ph1 md0 ph0 md1 ph0 md0 initial value:101/00101010101010 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w the port h control register (phcr) is a 16-bit readable/writable register that selects the pin functions. phcr is initialized to h'aaaa ( asemd0 = 1) or h'8aaa ( asemd0 = 0) by a power-on reset, but is not initialized by a manual reset, in standby mode, or in sleep mode.
rev. 5.00, 09/03, page 578 of 760 bits 15 and 14?ph7 mode 1, 0 (ph7md1, ph7md0): these bits select the pin functions and perform input pull-up mos control. bit 15 bit 14 ph7md1 ph7md0 pin function 0 0 other function (see table 18.1) 0 1 port output 1 0 port input (pull-up mos: on) (initial value) 1 1 port input (pull-up mos: off) bits 13 and 12?ph6 mode 1 and 0 (ph6md1, ph6md0) bits 11 and 10?ph5 mode 1 and 0 (ph5md1, ph5md0) bits 9 and 8?ph4 mode 1 and 0 (ph4md1, ph4md0) bits 7 and 6?ph3 mode 1 and 0 (ph3md1, ph3md0) bits 5 and 4?ph2 mode 1 and 0 (ph2md1, ph2md0) bits 3 and 2?ph1 mode 1 and 0 (ph1md1, ph1md0) bits 1 and 0?ph0 mode 1 and 0 (ph0md1, ph0md0) these bits select the pin functions and perform input pull-up mos control. bit 13 bit 12 ph6md1 ph6md0 pin function 0 0 other function (see table 18.1) (initial value) ( asemd0 = 0) 0 1 reserved 1 0 port input (pull-up mos: on) (initial value) ( asemd0 = 1) 1 1 port input (pull-up mos: off) bit (2n + 1) bit 2n phnmd1 phnmd0 pin function 0 0 other function (see table 18.1) 0 1 reserved 1 0 port input (pull-up mos: on) (initial value) 1 1 port input (pull-up mos: off) (n = 0 to 5)
rev. 5.00, 09/03, page 579 of 760 18.3.9 port j control register (pjcr) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pj7 md1 pj7 md0 pj6 md1 pj6 md0 pj5 md1 pj5 md0 pj4 md1 pj4 md0 pj3 md1 pj3 md0 pj2 md1 pj2 md0 pj1 md1 pj1 md0 pj0 md1 pj0 md0 initial value:0000000000000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w the port j control register (pjcr) is a 16-bit readable/writable register that selects the pin functions. pjcr is initialized to h'0000 by a power-on reset, but is not initialized by a manual reset, in standby mode, or in sleep mode. bits 15 and 14?pj7 mode 1 and 0 (pj7md1, pj7md0) bits 13 and 12?pj6 mode 1 and 0 (pj6md1, pj6md0) bits 11 and 10?pj5 mode 1 and 0 (pj5md1, pj5md0) bits 9 and 8?pj4 mode 1 and 0 (pj4md1, pj4md0) bits 7 and 6?pj3 mode 1 and 0 (pj3md1, pj3md0) bits 5 and 4?pj2 mode 1 and 0 (pj2md1, pj2md0) bits 3 and 2?pj1 mode 1 and 0 (pj1md1, pj1md0) bits 1 and 0?pj0 mode 1 and 0 (pj0md1, pj0md0) these bits select the pin functions and perform input pull-up mos control. bit (2n + 1) bit 2n pjnmd1 pjnmd0 pin function 0 0 other function (n = 0, 2, 3, 6, 7) (see table 18.1), reserved (n = 1, 4, 5) (initial value) 0 1 port output 1 0 port input (pull-up mos: on) 1 1 port input (pull-up mos: off) (n = 0 to 7)
rev. 5.00, 09/03, page 580 of 760 18.3.10 port k control register (pkcr) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pk7 md1 pk7 md0 pk6 md1 pk6 md0 pk5 md1 pk5 md0 pk4 md1 pk4 md0 pk3 md1 pk3 md0 pk2 md1 pk2 md0 pk1 md1 pk1 md0 pk0 md1 pk0 md0 initial value:0000000000000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w the port k control register (pkcr) is a 16-bit readable/writable register that selects the pin functions. pkcr is initialized to h'0000 by a power-on reset, but is not initialized by a manual reset, in standby mode, or in sleep mode. bits 15 and 14?pk7 mode 1 and 0 (pk7md1, pk7md0) bits 13 and 12?pk6 mode 1 and 0 (pk6md1, pk6md0) bits 11 and 10?pk5 mode 1 and 0 (pk5md1, pk5md0) bits 9 and 8?pk4 mode 1 and 0 (pk4md1, pk4md0) bits 7 and 6?pk3 mode 1 and 0 (pk3md1, pk3md0) bits 5 and 4?pk2 mode 1 and 0 (pk2md1, pk2md0) bits 3 and 2?pk1 mode 1 and 0 (pk1md1, pk1md0) bits 1 and 0?pk0 mode 1 and 0 (pk0md1, pk0md0) these bits select the pin functions and perform input pull-up mos control. bit (2n + 1) bit 2n pknmd1 pknmd0 pin function 0 0 other function (see table 18.1) (initial value) 0 1 port output 1 0 port input (pull-up mos: on) 1 1 port input (pull-up mos: off) (n = 0 to 7)
rev. 5.00, 09/03, page 581 of 760 18.3.11 port l control register (plcr) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pl7 md1 pl7 md0 pl6 md1 pl6 md0 pl5 md1 pl5 md0 pl4 md1 pl4 md0 pl3 md1 pl3 md0 pl2 md1 pl2 md0 pl1 md1 pl1 md0 pl0 md1 pl0 md0 initial value:0000000000000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w the port l control register (plcr) is a 16-bit readable/writable register that selects the pin functions. plcr is initialized to h'0000 by a power-on reset, but is not initialized by a manual reset, in standby mode, or in sleep mode. bits 15 and 14?pl7 mode 1 and 0 (pl7md1, pl7md0) bits 13 and 12?pl6 mode 1 and 0 (pl6md1, pl6md0) bits 11 and 10?pl5 mode 1 and 0 (pl5md1, pl5md0) bits 9 and 8?pl4 mode 1 and 0 (pl4md1, pl4md0) bits 7 and 6?pl3 mode 1 and 0 (pl3md1, pl3md0) bits 5 and 4?pl2 mode 1 and 0 (pl2md1, pl2md0) bits 3 and 2?pl1 mode 1 and 0 (pl1md1, pl1md0) bits 1 and 0?pl0 mode 1 and 0 (pl0md1, pl0md0) these bits select the pin functions and perform input pull-up mos control. bit (2n + 1) bit 2n plnmd1 plnmd0 pin function 0 0 other function (see table 18.1) (initial value) 0 1 reserved 1 0 port input (pull-up mos: on) 1 1 port input (pull-up mos: off) (n = 0 to 7) when the da0 and da1 pins are used as the d/a converter outputs or when ptl7 and ptl6 are used in the ?other function? state, plcr should by kept at its initial value.
rev. 5.00, 09/03, page 582 of 760 18.3.12 sc port control register (scpcr) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scp7 md1 scp7 md0 scp6 md1 scp6 md0 scp5 md1 scp5 md0 scp4 md1 scp4 md0 scp3 md1 scp3 md0 scp2 md1 scp2 md0 scp1 md1 scp1 md0 scp0 md1 scp0 md0 initial value:1010100010001000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w the sc port control register (scpcr) is a 16-bit readable/writable register that selects the pin functions. the setting of scpcr is valid only when transmit/receive operations are disabled in the scscr register. scpcr is initialized to h'a888 by a power-on reset, but is not initialized by a manual reset, in standby mode, or in sleep mode. when the te bit in scscr is set to 1, the ?other function? output state has a higher priority than the scpcr setting for the txd[2:0] pins. when the re bit in scscr is set to 1, the input state has a higher priority than the scpcr setting for the rxd[2:0] pins. bits 15 and 14?scp7 mode 1 and 0 (scp7md1, scp7md0): these bits select the pin function and perform input pull-up mos control. bit 15 bit 14 scp7md1 scp7md0 pin function 0 0 other function (see table 18.1) 0 1 reserved 1 0 port input (pull-up mos: on) (initial value) 1 1 port input (pull-up mos: off) bits 13, 12?scp6 mode 1, 0 (scp6md1, scp6md0): these bits select the pin function and perform input pull-up mos control. bit 13 bit 12 scp6md1 scp6md0 pin function 0 0 other function (see table 18.1) 0 1 port output 1 0 port input (pull-up mos: on) (initial value) 1 1 port input (pull-up mos: off)
rev. 5.00, 09/03, page 583 of 760 bits 11 and 10?scp5 mode 1 and 0 (scp5md1, scp5md0): these bits select the pin functions and perform input pull-up mos control. bit 11 bit 10 scp5md1 scp5md0 pin function 0 0 other function (see table 18.1) 0 1 port output 1 0 port input (pull-up mos: on) (initial value) 1 1 port input (pull-up mos: off) bits 9 and 8?scp4 mode 1 and 0 (scp4md1, scp4md0): these bits select the pin function and perform input pull-up mos control. bit 9 bit 8 scp4md1 scp4md0 pin function 0 0 transmit data output 2 (txd2) receive data input 2 (rxd2) (initial value) 0 1 general output (scpt[4] output pin) receive data input 2 (rxd2) 1 0 scpt[4] input pin pull-up (input pin) transmit data output 2 (txd2) 1 1 general input (scpt[4] input pin) transmit data output 2 (txd2) note: there is no scpt[4] simultaneous i/o combination because one bit (scp4dt) is accessed using two pins, txd2 and rxd2. when port input is set (bit scpnmd1 is set to 1) and when the te bit in scscr is set to 1, the txd2 pin is in the output state. when the te bit is cleared to 0, the txd2 pin goes to the high- impedance state. bits 7 and 6?scp3 mode 1 and 0 (scp3md1, scp3md0): these bits select the pin function and perform input pull-up mos control. bit 7 bit 6 scp3md1 scp3md0 pin function 0 0 other function (see table 18.1) 0 1 port output 1 0 port input (pull-up mos: on) (initial value) 1 1 port input (pull-up mos: off)
rev. 5.00, 09/03, page 584 of 760 bits 5 and 4?scp2 mode 1 and 0 (scp2md1, scp2md0): these bits select the pin function and perform input pull-up mos control. bit 5 bit 4 scp2md1 scp2md0 pin function 0 0 transmit data output 1 (txd1) receive data input 1 (rxd1) (initial value) 0 1 general output (scpt[2] output pin) receive data input 1 (rxd1) 1 0 scpt[2] input pin pull-up (input pin) transmit data output 1 (txd1) 1 1 general input (scpt[2] input pin) transmit data output 1 (txd1) note: there is no scpt[2] simultaneous i/o combination because one bit (scp2dt) is accessed using two pins, txd1 and rxd1. when port input is set (bit scpnmd1 is set to 1) and when the te bit in scscr is set to 1, the txd1 pin is in the output state. when the te bit is cleared to 0, the txd1 pin goes to the high- impedance state. bits 3 and 2?scp1 mode 1 and 0 (scp1md1, scp1md0): these bits select the pin function and perform input pull-up mos control. bit 3 bit 2 scp1md1 scp1md0 pin function 0 0 other function (see table 18.1) 0 1 port output 1 0 port input (pull-up mos: on) (initial value) 1 1 port input (pull-up mos: off)
rev. 5.00, 09/03, page 585 of 760 bits 1 and 0?scp0 mode 1 and 0 (scp0md1, scp0md0): these bits select the pin function and perform input pull-up mos control. bit 1 bit 0 scp0md1 scp0md0 pin function 0 0 transmit data output 0 (txd0) receive data input 0 (rxd0) (initial value) 0 1 general output (scpt[0] output pin) receive data input 0 (rxd0) 1 0 scpt[0] input pin pull-up (input pin) transmit data output 0 (txd0) 1 1 general input (scpt[0] input pin) transmit data output 0 (txd0) note: there is no scpt[0] simultaneous i/o combination because one bit (scp0dt) is accessed using two pins, txd0 and rxd0. when port input is set (bit scpnmd1 is set to 1) and when the te bit in scscr is set to 1, the txd0 pin is in the output state. when the te bit is cleared to 0, the txd0 pin goes to the high- impedance state.
rev. 5.00, 09/03, page 586 of 760
rev. 5.00, 09/03, page 587 of 760 section 19 i/o ports 19.1 overview the sh7709s has twelve 8-bit ports (ports a to l and sc). all port pins are multiplexed with other pin functions (the pin function controller (pfc) handles the selection of pin functions and pull-up mos control). each port has a data register which stores data for the pins. 19.2 port a port a is an 8-bit input/output port with the pin configuration shown in figure 19.1. each pin has an input pull-up mos, which is controlled by the port a control register (pacr) in the pfc. pta7 (input/output) / d23 (input/output) pta6 (input/output) / d22 (input/output) pta5 (input/output) / d21 (input/output) pta4 (input/output) / d20 (input/output) pta3 (input/output) / d19 (input/output) pta2 (input/output) / d18 (input/output) pta1 (input/output) / d17 (input/output) pta0 (input/output) / d16 (input/output) port a figure 19.1 port a 19.2.1 register description table 19.1 summarizes the port a register. table 19.1 port a register name abbreviation r/w initial value address access size port a data register padr r/w h'00 h'04000120 (h'a4000120) * 8 notes: this register is located in area 1 of physical space. therefore, when the cache is on, either access this register from the p2 area of logical space or else make an appropriate setting using the mmu so that this register is not cached. * when address translation by the mmu does not apply, the address in parentheses should be used.
rev. 5.00, 09/03, page 588 of 760 19.2.2 port a data register (padr) bit:76543210 pa7dt pa6dt pa5dt pa4dt pa3dt pa2dt pa1dt pa0dt initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the port a data register (padr) is an 8-bit readable/writable register that stores data for pins pta7 to pta0. bits pa7dt to pa0dt correspond to pins pta7 to pta0. when the pin function is general output port, if the port is read the value of the corresponding padr bit is returned directly. when the function is general input port, if the port is read the corresponding pin level is read. table 19.2 shows the function of padr. padr is initialized to h'00 by a power-on reset. it retains its previous value in standby mode and sleep mode, and in a manual reset. table 19.2 port a data register (padr) read/write operations panmd1 panmd0 pin state read write 0 0 other function (see table 18.1) padr value value is written to padr, but does not affect pin state 1 output padr value write value is output from pin 1 0 input (pull-up mos on) pin state value is written to padr, but does not affect pin state 1 input (pull-up mos off) pin state value is written to padr, but does not affect pin state (n = 7 to 0)
rev. 5.00, 09/03, page 589 of 760 19.3 port b port b is an 8-bit input/output port with the pin configuration shown in figure 19.2. each pin has an input pull-up mos, which is controlled by the port b control register (pbcr) in the pfc. ptb7 (input/output) / d31 (input/output) ptb6 (input/output) / d30 (input/output) ptb5 (input/output) / d29 (input/output) ptb4 (input/output) / d28 (input/output) ptb3 (input/output) / d27 (input/output) ptb2 (input/output) / d26 (input/output) ptb1 (input/output) / d25 (input/output) ptb0 (input/output) / d24 (input/output) port b figure 19.2 port b 19.3.1 register description table 19.3 summarizes the port b register. table 19.3 port b register name abbreviation r/w initial value address access size port b data register pbdr r/w h'00 h'04000122 (h'a4000122) * 8 notes: this register is located in area 1 of physical space. therefore, when the cache is on, either access this register from the p2 area of logical space or else make an appropriate setting using the mmu so that this register is not cached. * when address translation by the mmu does not apply, the address in parentheses should be used.
rev. 5.00, 09/03, page 590 of 760 19.3.2 port b data register (pbdr) bit:76543210 pb7dt pb6dt pb5dt pb4dt pb3dt pb2dt pb1dt pb0dt initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the port b data register (pbdr) is an 8-bit readable/writable register that stores data for pins ptb7 to ptb0. bits pb7dt to pb0dt correspond to pins ptb7 to ptb0. when the pin function is general output port, if the port is read the value of the corresponding pbdr bit is returned directly. when the function is general input port, if the port is read the corresponding pin level is read. table 19.4 shows the function of pbdr. pbdr is initialized to h'00 by a power-on reset. it retains its previous value in standby mode and sleep mode, and in a manual reset. table 19.4 port b data register (pbdr) read/write operations pbnmd1 pbnmd0 pin state read write 0 0 other function (see table 18.1) pbdr value value is written to pbdr, but does not affect pin state 1 output pbdr value write value is output from pin 1 0 input (pull-up mos on) pin state value is written to pbdr, but does not affect pin state 1 input (pull-up mos off) pin state value is written to pbdr, but does not affect pin state (n = 7 to 0)
rev. 5.00, 09/03, page 591 of 760 19.4 port c port c is an 8-bit input/output port with the pin configuration shown in figure 19.3. each pin has an input pull-up mos, which is controlled by the port c control register (pccr) in the pfc. ptc7 (input/output) / pint7 (input) / msc7 (output) ptc6 (input/output) / pint6 (input) / msc6 (output) ptc5 (input/output) / pint5 (input) / msc5 (output) ptc4 (input/output) / pint4 (input) / msc4 (output) ptc3 (input/output) / pint3 (input) / msc3 (output) ptc2 (input/output) / pint2 (input) / msc2 (output) ptc1 (input/output) / pint1 (input) / msc1 (output) ptc0 (input/output) / pint0 (input) / msc0 (output) port c figure 19.3 port c 19.4.1 register description table 19.5 summarizes the port c register. table 19.5 port c register name abbreviation r/w initial value address access size port c data register pcdr r/w h'00 h'04000124 (h'a4000124) * 8 notes: this register is located in area 1 of physical space. therefore, when the cache is on, either access this register from the p2 area of logical space or else make an appropriate setting using the mmu so that this register is not cached. * when address translation by the mmu does not apply, the address in parentheses should be used.
rev. 5.00, 09/03, page 592 of 760 19.4.2 port c data register (pcdr) bit:76543210 pc7dt pc6dt pc5dt pc4dt pc3dt pc2dt pc1dt pc0dt initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the port c data register (pcdr) is an 8-bit readable/writable register that stores data for pins ptc7 to ptc0. bits pc7dt to pc0dt correspond to pins ptc7 to ptc0. when the pin function is general output port, if the port is read, the value of the corresponding pcdr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. table 19.6 shows the function of pcdr. pcdr is initialized to h'00 by a power-on reset, after which the general input port function (pull- up mos on) is set as the initial pin function, and the corresponding pin levels are read. pcdr retains its previous value in standby mode and sleep mode, and in a manual reset. table 19.6 port c data register (pcdr) read/write operations pcnmd1 pcnmd0 pin state read write 0 0 other function (see table 18.1) pcdr value value is written to pcdr, but does not affect pin state 1 output pcdr value write value is output from pin 1 0 input (pull-up mos on) pin state value is written to pcdr, but does not affect pin state 1 input (pull-up mos off) pin state value is written to pcdr, but does not affect pin state (n = 7 to 0)
rev. 5.00, 09/03, page 593 of 760 19.5 port d port d comprises a 6-bit input/output port and 2-bit input port with the pin configuration shown in figure 19.4. each pin has an input pull-up mos, which is controlled by the port d control register (pdcr) in the pfc. ptd7 (input/output) / dack1 (output) ptd6 (input) / dreq1 (input) ptd5 (input/output) / dack0 (output) ptd4 (input) / dreq0 (input) ptd3 (input/output) / wakeup (output) ptd2 (input/output) / resetout (output) ptd1 (input/output) / drak0 (output) ptd0 (input/output) / drak1 (output) port d figure 19.4 port d 19.5.1 register description table 19.7 summarizes the port d register. table 19.7 port d register name abbreviation r/w initial value address access size port d data register pddr r/w or r b'0 * 0 * 0000 h'04000126 (h'a4000126) * 1 8 notes: this register is located in area 1 of physical space. therefore, when the cache is on, either access this register from the p2 area of logical space or else make an appropriate setting using the mmu so that this register is not cached. * means no value. * 1 when address translation by the mmu does not apply, the address in parentheses should be used.
rev. 5.00, 09/03, page 594 of 760 19.5.2 port d data register (pddr) bit:76543210 pd7dt pd6dt pd5dt pd4dt pd3dt pd2dt pd1dt pd0dt initial value: 0 * 0 * 0000 r/w: r/w r r/w r r/w r/w r/w r/w note: * undefined the port d data register (pddr) is a 6-bit readable/writable and 2-bit read-only register that stores data for pins ptd7 to ptd0. bits pd7dt to pd0dt correspond to pins ptd7 to ptd0. when the pin function is general output port, if the port is read, the value of the corresponding pddr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. table 19.8 shows the function of pddr. pddr is initialized to b'0*0*0000 by a power-on reset. after initialization, the general input port function (pull-up mos on) is set as the initial pin function, and the corresponding pin levels are read from bits pd7dt?pd3dt, pd1dt, and pd0dt. pddr retains its previous value in standby mode and sleep mode, and in a manual reset. note that the low level is read if bits 6 and 4 are read except in general-purpose input. table 19.8 port d data register (pddr) read/write operations pdnmd1 pdnmd0 pin state read write 0 0 other function (see table 18.1) pddr value value is written to pddr, but does not affect pin state 1 output pddr value write value is output from pin 1 0 input (pull-up mos on) pin state value is written to pddr, but does not affect pin state 1 input (pull-up mos off) pin state value is written to pddr, but does not affect pin state (n = 0, 1, 2, 3, 5, 7) pdnmd1 pdnmd0 pin state read write 0 0 other function (see table 18.1) low level ignored (no effect on pin state) 1 reserved low level ignored (no effect on pin state) 1 0 input (pull-up mos on) pin state ignored (no effect on pin state) 1 input (pull-up mos off) pin state ignored (no effect on pin state) (n = 4, 6)
rev. 5.00, 09/03, page 595 of 760 19.6 port e port e is an 8-bit input/output port with the pin configuration shown in figure 19.5. each pin has an input pull-up mos, which is controlled by the port e control register (pecr) in the pfc. pte7 (input/output) / audsync (output) pte6 (input/output) pte5 (input/output) / ce2b (output) pte4 (input/output) / ce2a (output) pte3 (input/output) pte2 (input/output) / ras3u (output) pte1 (input/output) pte0 (input/output) / tdo (output) port e figure 19.5 port e 19.6.1 register description table 19.9 summarizes the port e register. table 19.9 port e register name abbreviation r/w initial value address access size port e data register pedr r/w h'00 h'04000128 (h'a4000128) * 8 notes: this register is located in area 1 of physical space. therefore, when the cache is on, either access this register from the p2 area of logical space or else make an appropriate setting using the mmu so that this register is not cached. * when address translation by the mmu does not apply, the address in parentheses should be used.
rev. 5.00, 09/03, page 596 of 760 19.6.2 port e data register (pedr) bit:76543210 pe7dt pe6dt pe5dt pe4dt pe3dt pe2dt pe1dt pe0dt initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the port e data register (pedr) is an 8-bit readable/writable register that stores data for pins pte7 to pte0. bits pe7dt to pe0dt correspond to pins pte7 to pte0. when the pin function is general output port, if the port is read the value of the corresponding pedr bit is returned directly. when the function is general input port, if the port is read the corresponding pin level is read. table 19.10 shows the function of pedr. pedr is initialized to h'00 by a power-on reset, after which the general input port function (pull- up mos on) is set as the initial pin function, and the corresponding pin levels are read. it retains its previous value in standby mode and sleep mode, and in a manual reset. table 19.10 port e data register (pedr) read/write operations penmd1 penmd0 pin state read write 0 0 other function (see table 18.1) pedr value value is written to pedr, but does not affect pin state 1 output pedr value write value is output from pin 1 0 input (pull-up mos on) pin state value is written to pedr, but does not affect pin state 1 input (pull-up mos off) pin state value is written to pedr, but does not affect pin state (n = 0 to 7)
rev. 5.00, 09/03, page 597 of 760 19.7 port f port f is an 8-bit input port with the pin configuration shown in figure 19.6. each pin has an input pull-up mos, which is controlled by the port f control register (pfcr) in the pfc. ptf7 (input) / pint15 (input) / trst (input) ptf6 (input) / pint14 (input) / tms (input) ptf5 (input) / pint13 (input) / tdi (input) ptf4 (input) / pint12 (input) / tck (input) ptf3 (input) / pint11 (input) / irls3 (input) ptf2 (input) / pint10 (input) / irsl2 (input) ptf1 (input) / pint9 (input) / irls1 (input) ptf0 (input) / pint8 (input) / irls0 (input) port f figure 19.6 port f 19.7.1 register description table 19.11 summarizes the port f register. table 19.11 port f register name abbreviation r/w initial value address access size port f data register pfdr r h' ** h'0400012a (h'a400012a) * 1 8 notes: this register is located in area 1 of physical space. therefore, when the cache is on, either access this register from the p2 area of logical space or else make an appropriate setting using the mmu so that this register is not cached. * means no value. * 1 when address translation by the mmu does not apply, the address in parentheses should be used.
rev. 5.00, 09/03, page 598 of 760 19.7.2 port f data register (pfdr) bit:76543210 pf7dt pf6dt pf5dt pf4dt pf3dt pf2dt pf1dt pf0dt initial value: ******** r/w:rrrrrrrr note: * undefined the port f data register (pfdr) is an 8-bit read-only register that stores data for pins ptf7 to ptf0. bits pf7dt to pf0dt correspond to pins ptf7 to ptf0. when the function is general input port, if the port is read the corresponding pin level is read. table 19.12 shows the function of pfdr. pfdr is initialized by a power-on reset, after which the general input port function (pull-up mos on) is set as the initial pin function, and the corresponding pin levels are read. table 19.12 port f data register (pfdr) read/write operations pfnmd1 pfnmd0 pin state read write 0 0 other function (see table 18.1) h'00 ignored (no effect on pin state) 1 reserved h'00 ignored (no effect on pin state) 1 0 input (pull-up mos on) pin state ignored (no effect on pin state) 1 input (pull-up mos off) pin state ignored (no effect on pin state) (n = 0 to 7)
rev. 5.00, 09/03, page 599 of 760 19.8 port g port g comprises a 5-bit input/output port and 3-bit input port with the pin configuration shown in figure 19.7. each pin has an input pull-up mos, which is controlled by the port g control register (pgcr) in the pfc. ptg7 (input) / iois16 (input) ptg6 (input) / asemd0 (input) ptg5 (input) / asebrkak (output) ptg4 (input) / ckio2 (output) ptg3 (input) / audata3 (input/output) ptg2 (input) / audata2 (input/output) ptg1 (input) / audata1 (input/output) ptg0 (input) / audata0 (input/output) port g figure 19.7 port g 19.8.1 register description table 19.13 summarizes the port g register. table 19.13 port g register name abbreviation r/w initial value address access size port g data register pgdr r/w h' ** h'0400012c (h'a400012c) * 1 8 notes: this register is located in area 1 of physical space. therefore, when the cache is on, either access this register from the p2 area of logical space or else make an appropriate setting using the mmu so that this register is not cached. * means no value. * 1 when address translation by the mmu does not apply, the address in parentheses should be used.
rev. 5.00, 09/03, page 600 of 760 19.8.2 port g data register (pgdr) bit:76543210 pg7dt pg6dt pg5dt pg4dt pg3dt pg2dt pg1dt pg0dt initial value: ******** r/w:rrrrrrrr note: * undefined the port g data register (pgdr) is an 8-bit read-only register that stores data for pins ptg7 to ptg0. bits pg7dt to pg0dt correspond to pins ptg7 to ptg0. when the function is general input port, if the port is read the corresponding pin level is read. table 19.14 shows the function of pgdr. pgdr is initialized by a power-on reset, after which the general input port function (pull-up mos on) is set as the initial pin function, and the corresponding pin levels are read. table 19.14 port g data register (pgdr) read/write operations pgnmd1 pgnmd0 pin state read write 0 0 other function (see table 18.1) h'00 ignored (no effect on pin state) 1 reserved h'00 ignored (no effect on pin state) 1 0 input (pull-up mos on) pin state ignored (no effect on pin state) 1 input (pull-up mos off) pin state ignored (no effect on pin state) (n = 0 to 7)
rev. 5.00, 09/03, page 601 of 760 19.9 port h port h comprises a 1-bit input/output port and 7-bit input port with the pin configuration shown in figure 19.8. each pin has an input pull-up mos, which is controlled by the port h control register (phcr) in the pfc. pth7 (input/output) / tclk (output) pth4 (input) / irq4 (input) pth3 (input) / irq3 (input) pth2 (input) / irq2 (input) pth6 (input) / audck (input) pth5 (input) / adtrg (input) pth1 (input) / irq1 (input) pth0 (input) / irq0 (input) port h figure 19.8 port h 19.9.1 register description table 19.15 summarizes the port h register. table 19.15 port h register name abbreviation r/w initial value address access size port h data register phdr r/w or r b'0 ******* h'0400012e (h'a400012e) * 1 8 notes: this register is located in area 1 of physical space. therefore, when the cache is on, either access this register from the p2 area of logical space or else make an appropriate setting using the mmu so that this register is not cached. * means no value. * 1 when address translation by the mmu does not apply, the address in parentheses should be used.
rev. 5.00, 09/03, page 602 of 760 19.9.2 port h data register (phdr) bit:76543210 ph7dt ph6dt ph5dt ph4dt ph3dt ph2dt ph1dt ph0dt initial value: 0 ******* r/w:r/wrrrrrrr note: * undefined the port h data register (phdr) is a 1-bit readable/writable and 7-bit read-only register that stores data for pins pth7 to pth0. bits ph7dt to ph0dt correspond to pins pth7 to pth0. when the pin function is general output port, if the port is read, the value of the corresponding phdr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. table 19.16 shows the function of phdr. phdr is initialized to b'0******* by a power-on reset, after which the general input port function (pull-up mos on) is set as the initial pin function, and the corresponding pin levels are read. it retains its previous value in standby mode and sleep mode, and in a manual reset. note that the low level is read if bits 6 to 0 are read except in general-purpose input. table 19.16 port h data register (phdr) read/write operations phnmd1 phnmd0 pin state read write 0 0 other function (see table 18.1) phdr value value is written to phdr, but does not affect pin state 1 output phdr value write value is output from pin 1 0 input (pull-up mos on) pin state value is written to phdr, but does not affect pin state 1 input (pull-up mos off) pin state value is written to phdr, but does not affect pin state (n = 7) phnmd1 phnmd0 pin state read write 0 0 other function (see table 18.1) low level ignored (no effect on pin state) 1 reserved low level ignored (no effect on pin state) 1 0 input (pull-up mos on) pin state ignored (no effect on pin state) 1 input (pull-up mos off) pin state ignored (no effect on pin state) (n = 0 to 6)
rev. 5.00, 09/03, page 603 of 760 19.10 port j port j is an 8-bit input/output port with the pin configuration shown in figure 19.9. each pin has an input pull-up mos, which is controlled by the port j control register (pjcr) in the pfc. ptj7 (input/output) / status1 (output) ptj6 (input/output) / status0 (output) ptj5 (input/output) ptj4 (input/output) ptj3 (input/output) / casu (output) ptj2 (input/output) / casl (output) ptj1 (input/output) ptj0 (input/output) / ras3l (output) port j figure 19.9 port j 19.10.1 register description table 19.17 summarizes the port j register. table 19.17 port j register name abbreviation r/w initial value address access size port j data register pjdr r/w h'00 h'04000130 (h'a4000130) * 8 notes: this register is located in area 1 of physical space. therefore, when the cache is on, either access this register from the p2 area of logical space or else make an appropriate setting using the mmu so that this register is not cached. * when address translation by the mmu does not apply, the address in parentheses should be used.
rev. 5.00, 09/03, page 604 of 760 19.10.2 port j data register (pjdr) bit:76543210 pj7dt pj6dt pj5dt pj4dt pj3dt pj2dt pj1dt pj0dt initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the port j data register (pjdr) is an 8-bit readable/writable register that stores data for pins ptj7 to ptj0. bits pj7dt to pj0dt correspond to pins ptj7 to ptj0. when the pin function is general output port, if the port is read the value of the corresponding pjdr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. table 19.18 shows the function of pjdr. pjdr is initialized to h'00 by a power-on reset. it retains its previous value in software standby mode and sleep mode, and in a manual reset. table 19.18 port j data register (pjdr) read/write operations pjnmd1 pjnmd0 pin state read write 0 0 other function (see table 18.1) pjdr value value is written to pjdr, but does not affect pin state 1 output pjdr value write value is output from pin 1 0 input (pull-up mos on) pin state value is written to pjdr, but does not affect pin state 1 input (pull-up mos off) pin state value is written to pjdr, but does not affect pin state (n = 0 to 7)
rev. 5.00, 09/03, page 605 of 760 19.11 port k port k is an 8-bit input/output port with the pin configuration shown in figure 19.10. each pin has an input pull-up mos, which is controlled by the port k control register (pkcr) in the pfc. ptk7 (input/output) / we3 (output) / dqmuu (output) / iciowr (output) ptk6 (input/output) / we2 (output) / dqmul (output) / iciord (output) ptk5 (input/output) / cke (output) ptk4 (input/output) / bs (output) ptk3 (input/output) / cs5 (output) / ce1a (output) ptk2 (input/output) / cs4 (output) ptk1 (input/output) / cs3 (output) ptk0 (input/output) / cs2 (output) port k figure 19.10 port k 19.11.1 register description table 19.19 summarizes the port k register. table 19.19 port k register name abbreviation r/w initial value address access size port k data register pkdr r/w h'00 h'04000132 (h'a4000132) * 8 notes: this register is located in area 1 of physical space. therefore, when the cache is on, either access this register from the p2 area of logical space or else make an appropriate setting using the mmu so that this register is not cached. * when address translation by the mmu does not apply, the address in parentheses should be used.
rev. 5.00, 09/03, page 606 of 760 19.11.2 port k data register (pkdr) bit:76543210 pk7dt pk6dt pk5dt pk4dt pk3dt pk2dt pk1dt pk0dt initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the port k data register (pkdr) is an 8-bit readable/writable register that stores data for pins ptk7 to ptk0. bits pk7dt to pk0dt correspond to pins ptk7 to ptk0. when the pin function is general output port, if the port is read, the value of the corresponding pkdr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. table 19.20 shows the function of pkdr. pkdr is initialized to h'00 by a power-on reset. it retains its previous value in standby mode and sleep mode, and in a manual reset. table 19.20 port k data register (pkdr) read/write operations pknmd1 pknmd0 pin state read write 0 0 other function (see table 18.1) pkdr value value is written to pkdr, but does not affect pin state 1 output pkdr value write value is output from pin 1 0 input (pull-up mos on) pin state value is written to pkdr, but does not affect pin state 1 input (pull-up mos off) pin state value is written to pkdr, but does not affect pin state (n = 0 to 7)
rev. 5.00, 09/03, page 607 of 760 19.12 port l port l is an 8-bit input port with the pin configuration shown in figure 19.11. ptl7 (input) / an7 (input) / da0 (input) ptl6 (input) / an6 (input) / da1 (input) ptl5 (input) / an5 (input) ptl4 (input) / an4 (input) ptl3 (input) / an3 (input) ptl2 (input) / an2 (input) ptl1 (input) / an1 (input) ptl0 (input) / an0 (input) port l figure 19.11 port l 19.12.1 register description table 19.21 summarizes the port l register. table 19.21 port l register name abbreviation r/w initial value address access size port l data register pldr r h'00 h'04000134 (h'a4000134) * 8 notes: this register is located in area 1 of physical space. therefore, when the cache is on, either access this register from the p2 area of logical space or else make an appropriate setting using the mmu so that this register is not cached. * when address translation by the mmu does not apply, the address in parentheses should be used.
rev. 5.00, 09/03, page 608 of 760 19.12.2 port l data register (pldr) bit:76543210 pl7dt pl6dt pl5dt pl4dt pl3dt pl2dt pl1dt pl0dt initial value:00000000 r/w:rrrrrrrr the port l data register (pldr) is an 8-bit read-only register that stores data for pins ptl7 to ptl0. bits pl7dt to pl0dt correspond to pins ptl7 to ptl0. when the function is general input port, if the port is read, the corresponding pin level is read. table 19.22 shows the function of pldr. pkdr is initialized to h'00 by power-on reset. it retains its previous value in software standby mode and sleep mode, and in a manual reset. the port l is also used as an analog pin, therefore does not have a pull-up mos. table 19.22 port l data register (pldr) read/write operation plnmd1 plnmd0 pin state read write 0 0 other function (see table 18.1) h'00 ignored (no effect on pin state) 1 reserved h'00 ignored (no effect on pin state) 1 0 input pin state ignored (no effect on pin state) 1 input pin state ignored (no effect on pin state) (n = 0 to 7)
rev. 5.00, 09/03, page 609 of 760 19.13 sc port the sc port comprises a 4-bit input/output port, 3-bit output port, and 4-bit input port with the pin configuration shown in figure 19.12. each pin has an input pull-up mos, which is controlled by the sc port control register (scpcr) in the pfc. scpt7 (input) / cts2 (input) / irq5 (input) scpt6 (input/output) / rts2 (output) scpt5 (input/output) / sck2 (input/output) scpt4 (input) / rxd2 (input) scpt4 (output) / txd2 (output) scpt3 (input/output) / sck1 (input/output) scpt2 (input) / rxd1 (input) scpt2 (output) / txd1 (output) scpt1 (input/output) / sck0 (input/output) scpt0 (input) / rxd0 (input) scpt0 (output) / txd0 (output) sc port figure 19.12 sc port 19.13.1 register description table 19.23 summarizes the sc port register. table 19.23 sc port register name abbreviation r/w initial value address access size sc port data register scpdr r/w or r b' * 0000000 h'04000136 (h'a4000136) * 1 8 notes: this register is located in area 1 of physical space. therefore, when the cache is on, either access this register from the p2 area of logical space or else make an appropriate setting using the mmu so that this register is not cached. * means no value. * 1 when address translation by the mmu does not apply, the address in parentheses should be used.
rev. 5.00, 09/03, page 610 of 760 19.13.2 sc port data register (scpdr) bit:76543210 scp7dt scp6dt scp5dt scp4dt scp3dt scp2dt scp1dt scp0dt initial value: * 0000000 r/w: r r/w r/w r/w r/w r/w r/w r/w note: * undefined the sc port data register (scpdr) is a 7-bit readable/writable and 1-bit read-only register that stores data for pins scpt7 to scpt0. bits scp7dt to scp0dt correspond to pins scpt7 to scpt0. when the pin function is general output port, if the port is read, the value of the corresponding scpdr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. table 19.24 shows the function of scpdr. scpdr is initialized to b'*0000000 by a power-on reset. after initialization, the general input port function (pull-up mos on) is set as the initial pin function, and the corresponding pin levels are read from bits scp7dt?scp5dt, scp3dt, and scp1dt. scpdr retains its previous value in standby mode and sleep mode, and in a manual reset. note that the low level is read if bit 7 is read except in general-purpose input. when the pin states of the rxd2 to rxd0 of the scp4dt, scp2dt, and scp0dt bits in scpdr are read while the te and re bits in scscr are not cleared to 0, the re bit in scscr should be set to 1. when the re bit is set to 1, the rxd pins become an input state and their pin states can be read prior to the scpcr setting.
rev. 5.00, 09/03, page 611 of 760 table 19.24 read/write operation of the sc port data register (scpdr) scpnmd1 scpnmd0 pin state read write 0 0 other function (see table 18.1) scpdr value value is written to scpdr, but does not affect pin state 1 output scpdr value write value is output from pin 1 0 input (pull-up mos on) pin state value is written to scpdr, but does not affect pin state 1 input (pull-up mos off) pin state value is written to scpdr, but does not affect pin state (n = 0 to 6) scpnmd1 scpnmd0 pin state read write 0 0 other function (see table 18.1) low level ignored (no effect on pin state) 1 output low level ignored (no effect on pin state) 1 0 input (pull-up mos on) pin state ignored (no effect on pin state) 1 input (pull-up mos off) pin state ignored (no effect on pin state) (n = 7)
rev. 5.00, 09/03, page 612 of 760
rev. 5.00, 09/03, page 613 of 760 section 20 a/d converter 20.1 overview the sh7709s includes a 10-bit successive-approximation a/d converter allowing selection of up to eight analog input channels. 20.1.1 features a/d converter features are listed below. ? 10-bit resolution ? eight input channels ? high-speed conversion ? conversion time: maximum 15 s per channel (p = 33 mhz operation) ? three conversion modes ? single mode: a/d conversion on one channel ? multi mode: a/d conversion on one to four channels ? scan mode: continuous a/d conversion on one to four channels ? four 16-bit data registers ? a/d conversion results are transferred for storage into data registers corresponding to the channels. ? sample-and-hold function ? a/d conversion can be externally triggered ? a/d interrupt requested at the end of conversion ? at the end of a/d conversion, an a/d end interrupt (adi) can be requested.
rev. 5.00, 09/03, page 614 of 760 20.1.2 block diagram figure 20.1 shows a block diagram of the a/d converter. 10-bit d/a addra addrb addrd bus interface peripheral data bus analog multi- plexer control circuit successive approxi- mation register + ? comparator sample-and- hold circuit adi interrupt signal av ss an0 an1 an2 an3 an4 an5 an6 an7 /8 /16 adcsr adcr av cc a/d converter adcr: a/d control register adcsr: a/d control/status register addra: a/d data register a addrb: a/d data register b addrc: a/d data register c addrd: a/d data register d legend internal data bus adtrg addrc figure 20.1 block diagram of a/d converter
rev. 5.00, 09/03, page 615 of 760 20.1.3 input pins table 20.1 summarizes the a/d converter?s input pins. the eight analog input pins are divided into two groups: group 0 (an0 to an3), and group 1 (an4 to an7). av cc and av ss are the power supply inputs for the analog circuits in the a/d converter. avcc also functions as the a/d converter reference voltage pin. table 20.1 a/d converter pins pin name abbreviation i/o function analog power supply pin avcc input analog power supply analog ground pin avss input analog ground and reference voltage analog input pin 0 an0 input group 0 analog inputs analog input pin 1 an1 input analog input pin 2 an2 input analog input pin 3 an3 input analog input pin 4 an4 input group1 analog inputs analog input pin 5 an5 input analog input pin 6 an6 input analog input pin 7 an7 input a/d external trigger input pin adtrg input external trigger input for starting a/d conversion
rev. 5.00, 09/03, page 616 of 760 20.1.4 register configuration table 20.2 summarizes the a/d converter?s registers. table 20.2 a/d converter registers name abbreviation r/w initial value address access size a/d data register ah addrah r h'00 h'04000080 (h'a4000080) * 2 16, 8 a/d data register al addral r h'00 h'04000082 (h'a4000082) * 2 8 a/d data register bh addrbh r h'00 h'04000084 (h'a4000084) * 2 16, 8 a/d data register bl addrbl r h'00 h'04000086 (h'a4000086) * 2 8 a/d data register ch addrch r h'00 h'04000088 (h'a4000088) * 2 16, 8 a/d data register cl addrcl r h'00 h'0400008a (h'a400008a) * 2 8 a/d data register dh addrdh r h'00 h'0400008c (h'a400008c) * 2 16, 8 a/d data register dl addrdl r h'00 h'0400008e (h'a400008e) * 2 8 a/d control/status register adcsr r/(w) * 1 h'00 h'04000090 (h'a4000090) * 2 8 a/d control register adcr r/w h'07 h'04000092 (h'a4000092) * 2 8 notes: these registers are located in area 1 of physical space. therefore, when the cache is on, either access these registers from the p2 area of logical space or else make an appropriate setting using the mmu so that these registers are not cached. 1. only 0 can be written to bit 7, to clear the flag. 2. when address translation by the mmu does not apply, the address in parentheses should be used.
rev. 5.00, 09/03, page 617 of 760 20.2 register descriptions 20.2.1 a/d data registers a to d (addra to addrd) upper register: h bit:76543210 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 initial value:00000000 r/w:rrrrrrrr lower register: l bit:76543210 ad1ad0?????? initial value:00000000 r/w:rrrrrrrr n = a to d the four a/d data registers (addra to addrd) are 16-bit read-only registers that store the results of a/d conversion. an a/d conversion produces 10-bit data, which is transferred for storage into the a/d data register corresponding to the selected channel. the upper 8 bits of the result are stored in the upper byte (bits 7 to 0) of the a/d data register. the lower 2 bits are stored in the lower byte (bits 7 and 6). bits 5 to 0 of an a/d data register are reserved bits that are always read as 0. table 20.3 indicates the pairings of analog input channels and a/d data registers. the a/d data registers are initialized to h'0000 by a reset and in standby mode. table 20.3 analog input channels and a/d data registers analog input channel group 0 group 1 a/d data register an0 an4 addra an1 an5 addrb an2 an6 addrc an3 an7 addrd
rev. 5.00, 09/03, page 618 of 760 20.2.2 a/d control/status register (adcsr) bit:76543210 adf adie adst multi cks ch2 ch1 ch0 initial value:00000000 r/w: r/(w) * r/w r/w r/w r/w r/w r/w r/w note: * write 0 to clear the flag. adcsr is an 8-bit readable/writable register that selects the mode and controls the a/d converter. adcsr is initialized to h'00 by a reset and in standby mode. bit 7?a/d end flag (adf): indicates the end of a/d conversion. bit 7: adf description 0 [clearing conditions] (initial value) (1) cleared by reading adf while adf = 1, then writing 0 to adf (2) cleared when dmac is activated by adi interrupt and addr is read 1 [setting conditions] (1) single mode: a/d conversion ends (2) multi mode: a/d conversion ends on all selected channels (3) scan mode: a/d conversion ends on all selected channels bit 6?a/d interrupt enable (adie): enables or disables the interrupt (adi) requested at the end of a/d conversion. the adie bit should be set while the a/d conversion stops. bit 6: adie description 0 a/d end interrupt request (adi) is disabled (initial value) 1 a/d end interrupt request (adi) is enabled
rev. 5.00, 09/03, page 619 of 760 bit 5?a/d start (adst): starts or stops a/d conversion. the adst bit remains set to 1 during a/d conversion. it can also be set to 1 by external trigger input at the adtrg pin. bit 5: adst description 0 a/d conversion is stopped (initial value) 1 (1) single mode: a/d conversion starts; adst is automatically cleared to 0 when conversion ends (2) multi mode: a/d conversion starts; adst is automatically cleared to 0 when conversion ends on all selected channels (3) scan mode: a/d conversion starts and continues, cycling through the selected channels, until adst is cleared to 0 by software, by a reset, or by a transition to standby mode bit 4?multi mode (multi): selects single mode, multi mode or scan mode. for further information on operation in these modes, see section 20.4, operation. bit 4: multi adcr: bit5: scn description 0 0 single mode (initial value) 1 1 0 multi mode 1 scan mode bit 3?clock select (cks): selects the a/d conversion time. clear the adst bit to 0 before changing the conversion time. bit 3:cks description 0 conversion time = 536 states (maximum) (initial value) 1 conversion time = 266 states (maximum)
rev. 5.00, 09/03, page 620 of 760 bits 2 to 0?channel select 2 to 0 (ch2 to ch0): these bits and the multi bit select the analog input channels. clear the adst bit to 0 before changing the channel selection. channel selection description ch2 ch1 ch0 single mode (multi = 0) multi mode and scan mode (multi = 1) 000an0 (initial value)an0 1 an1 an0, an1 1 0 an2 an0 to an2 1 an3 an0 to an3 100an4 an4 1 an5 an4, an5 1 0 an6 an4 to an6 1 an7 an4 to an7
rev. 5.00, 09/03, page 621 of 760 20.2.3 a/d control register (adcr) bit:76543210 trge1 trge0 scn resvd1 resvd2 ? ? ? initial value:00000111 r/w: r/w r/w r/w r/w r/w r r r adcr is an 8-bit readable/writable register that enables or disables external triggering of a/d conversion. adcr is initialized to h'07 by a reset and in standby mode. bit 7 and 6?trigger enable (trge1, trge0): enables or disables external triggering of a/d conversion. the trge1 and trge0 bits should only be set when conversion is not in progress. bit 7: trge1 bit 6: trge0 description 00 01 a/d conversion does not start when an external trigger is input (initial value) 10 11 a/d conversion starts at the falling edge of an input signal from the external trigger pin ( adtrg ) bit 5?scan mode (scn): selects multi mode or scan mode when the multi bit is set to 1. see the description of bit 4 in section 20.2.2, a/d control/status register (adcsr). bits 4 and 3?reserved (resvd1, resvd2): these bits are always read as 0. the write value should always be 0. bits 2 to 0?reserved: these bits are always read as 1. the write value should always be 1.
rev. 5.00, 09/03, page 622 of 760 20.3 bus master interface addra to addrd are 16-bit registers, but they are connected to the bus master by the upper 8 bits of the 16-bit peripheral data bus. therefore, although the upper byte can be accessed directly by the bus master, the lower byte is read through an 8-bit temporary register (temp). an a/d data register is read as follows. when the upper byte is read, the upper-byte value is transferred directly to the bus master and the lower-byte value is transferred into temp. next, when the lower byte is read, the temp contents are transferred to the bus master. when reading an a/d data register, always read the upper byte before the lower byte. it is possible to read only the upper byte, but if only the lower byte is read, the read value is not guaranteed. figure 20.2 shows the data flow for access to an a/d data register. see section 20.7.3, access size and read data. bus interface temp [h40] addrn l [h40] addrn h [haa] cpu (haa) upper byte read module internal data bus bus interface temp [h40] addrn l [h40] addrn h [haa] n = a to d cpu (h40) lower byte read module internal data bus figure 20.2 a/d data register access operation (reading h'aa40)
rev. 5.00, 09/03, page 623 of 760 20.4 operation the a/d converter operates by successive approximations with 10-bit resolution. it has three operating modes: single mode, multi mode, and scan mode. 20.4.1 single mode (multi = 0) single mode should be selected when only one a/d conversion on one channel is required. a/d conversion starts when the adst bit is set to 1 by software, or by external trigger input. the adst bit remains set to 1 during a/d conversion and is automatically cleared to 0 when conversion ends. when conversion ends the adf bit is set to 1. if the adie bit is also set to 1, an adi interrupt is requested at this time. to clear the adf bit to 0, first read adf when adf = 1, then write 0 to the adf bit. when the mode or analog input channel must be switched during a/d conversion, to prevent incorrect operation, first clear the adst bit to 0 in adcsr to halt a/d conversion. after making the necessary changes, set the adst bit to 1 to start a/d conversion again. the adst bit can be set at the same time as the mode or channel is changed. typical operations when channel 1 (an1) is selected in single mode are described next. figure 20.3 shows a timing diagram for this example. (the adcsr register specifies bits in the operation example.) 1. single mode is selected (multi = 0), input channel an1 is selected (ch2 = ch1 = 0, ch0 = 1), the a/d interrupt is enabled (adie = 1), and a/d conversion is started (adst = 1). 2. when a/d conversion is completed, the result is transferred into addrb. at the same time the adf flag is set to 1, the adst bit is cleared to 0, and the a/d converter becomes idle. 3. since adf = 1 and adie = 1, an adi interrupt is requested. 4. the a/d interrupt handling routine starts. 5. the routine reads adcsr, then writes 0 to the adf flag. 6. the routine reads and processes the conversion result (addrb = 0). 7. execution of the a/d interrupt handling routine ends. then, when the adst bit is set to 1, a/d conversion starts and steps 2 to 7 are executed.
rev. 5.00, 09/03, page 624 of 760 channel 0 (an0) operating adie adst adf channel 1 (an1) operating channel 2 (an2) operating channel 3 (an3) operating addra addrb addrc addrd waiting waiting waiting waiting waiting waiting a/d conversion starts set set set clear * clear a/d conversion result 1 a/d conversion result 2 read result read result a/d conversion 1 a/d conversion result 2 note: * vertical arrows ( ) indicate instruction execution by software. figure 20.3 example of a/d converter operation (single mode, channel 1 selected)
rev. 5.00, 09/03, page 625 of 760 20.4.2 multi mode (multi = 1, scn = 0) multi mode should be selected when performing a/d conversions on one or more channels. when the adst bit is set to 1 by software or external trigger input, a/d conversion starts on the first channel in the group (an0 when ch2 = 0, an4 when ch2 = 1). when two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (an1 or an5) starts immediately. when a/d conversions end on the selected channels, the adst bit is cleared to 0. the conversion results are transferred for storage into the a/d data registers corresponding to the channels. when the mode or analog input channel selection must be changed during a/d conversion, to prevent incorrect operation, first clear the adst bit to 0 in adcsr to halt a/d conversion. after making the necessary changes, set the adst bit to 1. a/d conversion will start again from the first channel in the group. the adst bit can be set at the same time as the mode or channel selection is changed. typical operations when three channels in group 0 (an0 to an2) are selected in scan mode are described next. figure 20.4 shows a timing diagram for this example. 1. multi mode is selected (multi = 1, scn = 0), channel group 0 is selected (ch2 = 0), analog input channels an0 to an2 are selected (ch1 = 1, ch0 = 0), and a/d conversion is started (adst = 1). 2. when a/d conversion of the first channel (an0) is completed, the result is transferred into addra. next, conversion of the second channel (an1) starts automatically. 3. conversion proceeds in the same way through the third channel (an2). 4. when conversion of all selected channels (an0 to an2) is completed, the adf flag is set to 1 and adst bit is cleared to 0. if the adie bit is set to 1, an adi interrupt is requested at this time.
rev. 5.00, 09/03, page 626 of 760 channel 0 (an0) operating adst adf channel 1 (an1) operating channel 2 (an2) operating channel 3 (an3) operating addra addrb addrc addrd waiting waiting waiting waiting set * clear * clear a/d conversion result 2 waiting waiting a/d conversion result 3 a/d conversion 1 waiting a/d conversion result 1 transfer a/d conversion 3 a/d conversion a/d conversion 2 note: * vertical arrows ( ) indicate instruction execution by software. figure 20.4 example of a/d converter operation (multi mode, channels an0 to an2 selected)
rev. 5.00, 09/03, page 627 of 760 20.4.3 scan mode (multi = 1, scn = 1) scan mode is useful for monitoring analog inputs in a group of one or more channels. when the adst bit in the a/d control/status register (adcsr) is set to 1 by software or external trigger input, a/d conversion starts on the first channel in the group (an0 when ch2 = 0, an4 when ch2 = 1)). when two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (an1 or an5) starts immediately. a/d conversion continues cyclically on the selected channels until the adst bit is cleared to 0. the conversion results are transferred for storage into the a/d data registers corresponding to the channels. when the mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the adst bit to 0 to halt a/d conversion. after making the necessary changes, set the adst bit to 1. a/d conversion will start again from the first channel in the group. the adst bit can be set at the same time as the mode or channel selection is changed. typical operations when three channels (an0 to an2) in group 0 are selected in scan mode are described next. figure 20.5 shows a timing diagram for this example. 1. scan mode is selected (multi = 1, scn = 1), channel group 0 is selected (ch2 = 0), analog input channels an0 to an2 are selected (ch1 = 1, ch0 = 0), and a/d conversion is started (adst = 1). 2. when a/d conversion of the first channel (an0) is completed, the result is transferred into addra. next, conversion of the second channel (an1) starts automatically. 3. conversion proceeds in the same way through the third channel (an2). 4. when conversion of all the selected channels (an0 to an2) is completed, the adf flag is set to 1 and conversion of the first channel (an0) starts again. if the adie bit is set to 1, an adi interrupt is requested at this time. 5. steps 2 to 4 are repeated as long as the adst bit remains set to 1. when the adst bit is cleared to 0, a/d conversion stops. after that, if the adst bit is set to 1, a/d conversion starts again from the first channel (an0).
rev. 5.00, 09/03, page 628 of 760 adst adf channel 0 (an 0 ) operating channel 1 (an 1 ) operating channel 2 (an 2 ) operating channel 3 (an 3 ) operating addra addrb addrc addrd waiting waiting waiting waiting waiting waiting waiting waiting waiting transfer a/d conversion 1 a/d conversion 4 a/d conversion 2 a/d conversion 3 a/d conversion result 1 a/d conversion result 4 a/d conversion result 2 a/d conversion result 3 clear * 1 clear * 1 set * 1 continuous a/d conversion a/d conversion 5 notes: 1. vertical arrows ( ) indicate instruction execution by software. 2. data during conversion is ignored. figure 20.5 example of a/d converter operation (scan mode, channels an0 to an2 selected)
rev. 5.00, 09/03, page 629 of 760 20.4.4 input sampling and a/d conversion time the a/d converter has a built-in sample-and-hold circuit. the a/d converter samples the analog input at a time t d after the adst bit is set to 1, then starts conversion. figure 20.6 shows the a/d conversion timing. table 20.4 indicates the a/d conversion time. as indicated in figure 20.6, the a/d conversion time includes t d and the input sampling time. the length of t d varies depending on the timing of the write access to adcsr. the total conversion time therefore varies within the ranges indicated in table 20.4. in multi mode and scan mode, the conversion time values given in table 20.4 apply to the first conversion. in the second and subsequent conversions, the conversion time is fixed at 512 states when cks = 0 in adcsr, or 256 states when cks = 1. in both cases, the cks bit should be set according to the p frequency so that the conversion time is within the range shown in table 23.10 in section 23, electrical characteristics. p write signal adf 1 1 input sampling timing legend t d a/d conversion start delay t spl input sampling time t conv a/d conversion time notes: 1. adcsr write cycle 2. adcsr address address 1 2 t d t spl t conv figure 20.6 a/d conversion timing
rev. 5.00, 09/03, page 630 of 760 table 20.4 a/d conversion time (single mode) cks = 0 cks = 1 symbol min typ max min typ max a/d conversion start delay t d 17?2810? 17 input sampling time t spl ?129??65? a/d conversion time t conv 514 ? 525 259 ? 266 note: values in the table are numbers of states (t cyc ). 20.4.5 external trigger input timing a/d conversion can be externally triggered. when the trge1 and trge0 bits are set to 1 in adcr, external trigger input is enabled at the adtrg pin. a high-to-low transition at the adtrg pin sets the adst bit to 1 in adcsr, starting a/d conversion. other operations, regardless of the conversion mode, are the same as if the adst bit had been set to 1 by software. figure 20.7 shows the timing. a/d conversion p adtrg external trigger signal adst figure 20.7 external trigger input timing
rev. 5.00, 09/03, page 631 of 760 20.5 interrupts the a/d converter generates an interrupt (adi) at the end of a/d conversion. the adi interrupt request can be enabled or disabled by the adie bit in adcsr. 20.6 definitions of a/d conversion accuracy the a/d converter compares an analog value input from an analog input channel with its analog reference value and converts it to 10-bit digital data. the absolute accuracy of this a/d conversion is the deviation between the input analog value and the output digital value. it includes the following errors: ? offset error ? full-scale error ? quantization error ? nonlinearity error these four error quantities are explained below with reference to figure 20.8. in the figure, the 10 bits of the a/d converter have been simplified to 3 bits. offset error is the deviation between actual and ideal a/d conversion characteristics when the digital output value changes from the minimum (zero voltage) 0000000000 (000 in the figure) to 000000001 (001 in the figure)(figure 20.8, item (1)). full-scale error is the deviation between actual and ideal a/d conversion characteristics when the digital output value changes from the 1111111110 (110 in the figure) to the maximum 1111111111 (111 in the figure)(figure 20.8, item (2)). quantization error is the intrinsic error of the a/d converter and is expressed as 1/2 lsb (figure 20.8, item (3)). nonlinearity error is the deviation between actual and ideal a/d conversion characteristics between zero voltage and full-scale voltage (figure 20.8, item (4)). note that it does not include offset, full-scale, or quantization error.
rev. 5.00, 09/03, page 632 of 760 111 110 101 100 011 010 001 000 0 1/8 2/8 3/8 4/8 5/8 6/8 7/8 fs analog input voltage fs: full-scale voltage (3) quantization error ideal a/d conversion characteristic (4) nonlinearity error ideal a/d conversion characteristic actual a/d convertion characteristic (2) full-scale error digital output analog input voltage (1) offset error fs digital output figure 20.8 definitions of a/d conversion accuracy 20.7 usage notes when using the a/d converter, note the following points. 20.7.1 setting analog input voltage ? analog input voltage range: during a/d conversion, the voltages input to the analog input pins ann should be in the range av ss ann av cc (n = 0 to 7). ? relationships of av cc and av ss : av cc and av ss should be related as follows: av cc = v cc 0.3 v and av ss = v ss . 20.7.2 processing of analog input pins to prevent damage from voltage surges at the analog input pins (an0 to an7), connect an input protection circuit like the one shown in figure 20.9. the circuit shown also includes an cr filter to suppress noise. this circuit is shown as an example; the circuit constants should be selected according to actual application conditions. table 20.5 lists the analog input pin specifications and figure 20.10 shows an equivalent circuit diagram of the analog input ports.
rev. 5.00, 09/03, page 633 of 760 20.7.3 access size and read data table 20.6 shows the relationship between access size and read data. note the read data obtained with different access sizes, bus widths, and endian modes. the case is shown here in which h'3ff is obtained when av cc is input as an analog input. ff is the data containing the upper 8 bits of the conversion result, and c0 is the data containing the lower 2 bits. 0.01 f 10 f av cc an0 to an7 av ss sh7709s 1 1 100 ? 0.1 f note: figure 20.9 example of analog input protection circuit 1.0 k ? an0 to an7 20 pf 1 m ? figure 20.10 analog input pin equivalent circuit
rev. 5.00, 09/03, page 634 of 760 table 20.5 analog input pin ratings item min max unit analog input capacitance ? 20 pf allowable signal-source impedance ? 5 k ? table 20.6 relationship between access size and read data bus width 32 bits (d31?d0) 16 bits (d15?d0) 8 bits (d7?d0) endian access size command big little big little big little byte access mov.l#addrah,r9 mov.b@r9,r8 mov.l#addral,r9 mov.b@r9,r8 ffffffff c0c0c0c0 ffffffff c0c0c0c0 ffff c0c0 ffff c0c0 ff c0 ff c0 word access mov.l#addrah,r9 mov.w@r9,r8 mov.l#addral,r9 mov.w@r9,r8 ffxxffxx c0xxc0xx ffxxffxx c0xxc0xx ffxx c0xx ffxx c0xx ff xx c0 xx xx ff xx c0 longword access mov.l#addrah,r9 mov.l@r9,r8 ffxxc0xx ffxxc0xx ffxx c0xx c0xx ffxx ff xx c0 xx xx c0 xx ff in this table: #addrah .equ h'04000080 #addral .equ h'04000082 values are shown in hexadecimal for the case where read data is output to an external device via r8.
rev. 5.00, 09/03, page 635 of 760 section 21 d/a converter 21.1 overview the sh7709s includes a d/a converter with two channels. 21.1.1 features d/a converter features are listed below. ? eight-bit resolution ? two output channels ? conversion time: maximum 10 s (with 20-pf capacitive load) ? output voltage: 0 v to avcc 21.1.2 block diagram figure 21.1 shows a block diagram of the d/a converter. av cc da 0 da 1 dacr dadr0 dadr1 module data bus bus interface on-chip data bus control circuit legend dacr: d/a control register dadr0: d/a data register 0 dadr1: d/a data register 1 8-bit d/a av ss figure 21.1 block diagram d/a converter
rev. 5.00, 09/03, page 636 of 760 21.1.3 i/o pins table 21.1 summarizes the d/a converter?s input and output pins. table 21.1 d/a converter pins pin name abbreviation i/o function analog power supply pin avcc input analog power supply analog ground pin avss input analog ground and reference voltage analog output pin 0 da0 output analog output, channel 0 analog output pin 1 da1 output analog output, channel 1 21.1.4 register configuration table 21.2 summarizes the d/a converter?s registers. table 21.2 d/a converter registers name abbreviation r/w initial value address * 1 d/a data register 0 dadr0 r/w h'00 h'040000a0 (h'a40000a0) * 2 d/a data register 1 dadr1 r/w h'00 h'040000a2 (h'a40000a2) * 2 d/a control register dacr r/w h'1f h'040000a4 (h'a40000a4) * 2 notes: these registers are located in area 1 of physical space. therefore, when the cache is on, either access these registers from the p2 area of logical space or else make an appropriate setting using the mmu so that these registers are not cached. 1. lower 16 bits of the address 2. when address translation by the mmu does not apply, the address in parentheses should be used.
rev. 5.00, 09/03, page 637 of 760 21.2 register descriptions 21.2.1 d/a data registers 0 and 1 (dadr0/1) bit:76543210 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the d/a data registers (dadr0 and dadr1) are 8-bit readable/writable registers that store the data to be converted. when analog output is enabled, the d/a data register values are constantly converted and output at the analog output pins. the d/a data registers are initialized to h'00 by a reset. 21.2.2 d/a control register (dacr) bit:76543210 daoe1daoe0dae????? initial value:00011111 r/w:r/wr/wr/wrrrrr dacr is an 8-bit readable/writable register that controls the operation of the d/a converter. dacr is initialized to h'1f by a reset. bit 7?d/a output enable 1 (daoe1): controls d/a conversion and analog output. bit 7: daoe1 description 0 da1 analog output is disabled (initial value) 1 channel-1 d/a conversion and da1 analog output are enabled bit 6?d/a output enable 0 (daoe0): controls d/a conversion and analog output. bit 6: daoe0 description 0 da0 analog output is disabled (initial value) 1 channel-0 d/a conversion and da0 analog output are enabled
rev. 5.00, 09/03, page 638 of 760 bit 5?d/a enable (dae): controls d/a conversion, together with bits daoe0 and daoe1. when the dae bit is cleared to 0, d/a conversion is controlled independently in channels 0 and 1. when the chip enters standby mode while d/a conversion is enabled, the d/a output is held and the analog power-supply current is equivalent to that during d/a conversion. to reduce the analog power-supply current in standby mode, clear the daoe0 and daoe1 bits and disable the d/a output. bit 7: daoe1 bit 6: daoe0 bit 5: dae description 0 0 ? d/a conversion is disabled in channels 0 and 1 (initial value) 0 1 0 d/a conversion is enabled in channel 0 d/a conversion is disabled in channel 1 0 1 1 d/a conversion is enabled in channels 0 and 1 1 0 0 d/a conversion is disabled in channel 0 d/a conversion is enabled in channel 1 1 0 1 d/a conversion is enabled in channels 0 and 1 1 1 ? d/a conversion is enabled in channels 0 and 1 when the dae bit is set to 1, even if bits daoe0 and daoe1 in dacr and the adst bit in adcsr are cleared to 0, the same current is drawn from the analog power supply as during a/d and d/a conversion. bits 4 to 0?reserved: read-only bits, always read as 1.
rev. 5.00, 09/03, page 639 of 760 21.3 operation the d/a converter has two built-in d/a conversion circuits that can perform conversion independently. d/a conversion is performed constantly while enabled in dacr. if the dadr0 or dadr1 value is modified, conversion of the new data begins immediately. the conversion results are output when bits daoe0 and daoe1 are set to 1. an example of d/a conversion on channel 0 is given next. timing is indicated in figure 21.2. 1. data to be converted is written in dadr0. 2. bit daoe0 is set to 1 in dacr. d/a conversion starts and da0 becomes an output pin. the converted result is output after the conversion time. the output value is (dadr0 contents/256) avcc. output of this conversion result continues until the value in dadr0 is modified or the daoe0 bit is cleared to 0. 3. if the dadr0 value is modified, conversion starts immediately, and the result is output after the conversion time. 4. when the daoe0 bit is cleared to 0, da0 becomes an input pin. dadr0 write cycle t dconv high-impedance state conversion result 1 conversion data 1 conversion data 2 conversion result 2 t dconv address bus dadr0 daoe0 da0 t dconv : d/a conversion time legend dacr write cycle dadr0 write cycle dacr write cycle figure 21.2 example of d/a converter operation
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rev. 5.00, 09/03, page 641 of 760 section 22 user debugging interface (udi) 22.1 overview this lsi incorporates a user debugging interface (udi) and advanced user debugger (aud) for program debugging. 22.2 user debugging interface (udi) the udi (user debugging interface) performs on-chip debugging which is su pported by this lsi. the udi described here is a serial interface which is compatible with jtag (joint test action group, ieee standard 1149.1 and ieee standard test access port and boundary-scan architecture) specifications. the udi in the sh7709s supports a boundary scan mode, and is also used for emulator connection. when using an emulator, udi functions should not be used. refer to the emulator manual for the method of connecting the emulator. 22.2.1 pin descriptions tck: udi serial data input/output clock pin. data is serially supplied to the udi from the data input pin (tdi), and output from the data output pin (tdo), in synchronization with this clock. tms: mode select input pin. the state of the tap control circuit is determined by changing this signal in synchronization with tck. the protocol complies with the jtag standard (ieee std. 1149.1). trst trst trst trst : udi reset input pin. input is accepted asynchronously with respect to tck, and when low, the udi is reset. see section 22.4.2, reset configuration, for more information. tdi: udi serial data input pin. data transfer to the udi is executed by changing this signal in synchronization with tck. tdo: udi serial data output pin. data output from the udi is executed by reading this signal in synchronization with tck. asemd0 asemd0 asemd0 asemd0 : ase mode select pin. if a low level is input at the asemd0 pin while the resetp pin is asserted, ase mode is entered; if a high level is input, normal mode is entered. when using on the user system alone, without an emulator and the udi, hold this pin at high level. in ase
rev. 5.00, 09/03, page 642 of 760 mode, boundary scan and emulator functions can be used. the input level at the asemd0 pin should be held for at least one cycle after resetp negation. asebrkak asebrkak asebrkak asebrkak : dedicated emulator pin 22.2.2 block diagram figure 22.1 shows a block diagram of the udi. sdir tck tdo tdi tms trst sdbpr mux sdbsr shift register tap controller decoder local bus figure 22.1 block diagram of udi 22.3 register descriptions the udi has the following registers. ? sdbpr: bypass register ? sdir: instruction register ? sdbsr: boundary scan register
rev. 5.00, 09/03, page 643 of 760 table 22.1 shows the udi register configuration. table 22.1 udi registers cpu side udi side initial name abbreviation r/w size address r/w size value * bypass register sdbpr ? ? ? r/w 1 undefined instruction register sdir r 16 h'04000200 r/w 16 h'ffff boundary register sdbsr ? ? ? r/w ? undefined note: * initialized when trst pin is low or when tap is in the test-logic-reset state. 22.3.1 bypass register (sdbpr) the bypass register is a 1-bit register that cannot be accessed by the cpu. when sdir is set to the bypass mode, sdbpr is connected between udi pins tdi and tdo. 22.3.2 instruction register (sdir) the instruction register (sdir) is a 16-bit read-only register. the register is in bypass mode in its initial state. it is initialized by trst assertion or in the tap test-logic-reset state, and can be written to by the udi irrespective of the cpu mode. operation is not guaranteed if a reserved command is set in this register bit: 15 14 13 12 11 10 9 8 ti3ti2ti1ti0???? initial value:11111111 bit:76543210 ???????? initial value:11111111 bits 15 to 12?test instruction bits (ti3 to ti0): cannot be written by the cpu.
rev. 5.00, 09/03, page 644 of 760 table 22.2 udi commands bit 15 to 12 ti3 ti2 ti1 ti0 description 0000extest 0100sample/preload 0101reserved 0110udi reset negate 0111udi reset assert 100?reserved 101?udi interrupt 110?reserved 1110reserved 1111bypass mode(initial value) 0001recovery from sleep bits 11 to 0?reserved: these bits are always read as 1. 22.3.3 boundary scan register (sdbsr) the boundary scan register (sdbsr) is a shift register, located on the pad, for controlling the input/output pins of the sh7709s. using the extest and sample/preload commands, a boundary scan test conforming to the jtag standard can be carried out. table 22.3 shows the correspondence between the pins of this lsi and boundary scan register bits.
rev. 5.00, 09/03, page 645 of 760 table 22.3 pins of this lsi and boundary scan register bits bit pin name i/o bit pin name i/o from tdi 308 d1 in 338 d31/ptb7 in 307 d0 in 337 d30/ptb6 in 306 md1 in 336 d29/ptb5 in 305 md2 in 335 d28/ptb4 in 304 nmi in 334 d27/ptb3 in 303 irq0/ irl0 /pth0 in 333 d26/ptb2 in 302 irq1/ irl1 /pth1 in 332 d25/ptb1 in 301 irq2/ irl2 /pth2 in 331 d24/ptb0 in 300 irq3/ irl3 /pth3 in 330 d23/pta7 in 299 irq4/pth4 in 329 d22/pta6 in 298 d31/ptb7 out 328 d21/pta5 in 297 d30/ptb6 out 327 d20/pta4 in 296 d29/ptb5 out 326 d19/pta3 in 295 d28/ptb4 out 325 d18/pta2 in 294 d27/ptb3 out 324 d17/pta1 in 293 d26/ptb2 out 323 d16/pta0 in 292 d25/ptb1 out 322 d15 in 291 d24/ptb0 out 321 d14 in 290 d23/pta7 out 320 d13 in 289 d22/pta6 out 319 d12 in 288 d21/pta5 out 318 d11 in 287 d20/pta4 out 317 d10 in 286 d19/pta3 out 316 d9 in 285 d18/pta2 out 315 d8 in 284 d17/pta1 out 314 d7 in 283 d16/pta0 out 313 d6 in 282 d15 out 312 d5 in 281 d14 out 311 d4 in 280 d13 out 310 d3 in 279 d12 out 309 d2 in 278 d11 out
rev. 5.00, 09/03, page 646 of 760 bit pin name i/o bit pin name i/o 277 d10 out 247 d12 control 276 d9 out 246 d11 control 275 d8 out 245 d10 control 274 d7 out 244 d9 control 273 d6 out 243 d8 control 272 d5 out 242 d7 control 271 d4 out 241 d6 control 270 d3 out 240 d5 control 269 d2 out 239 d4 control 268 d1 out 238 d3 control 267 d0 out 237 d2 control 266 d31/ptb7 control 236 d1 control 265 d30/ptb6 control 235 d0 control 264 d29/ptb5 control 234 bs /ptk4 in 263 d28/ptb4 control 233 we2 /dqmul/ iciord / ptk6 in 262 d27/ptb3 control 232 we3 /dqmuu/ iciord / ptk7 in 261 d26/ptb2 control 231 audsync /pte7 in 260 d25/ptb1 control 230 cs2 /ptk0 in 259 d24/ptb0 control 229 cs3 /ptk1 in 258 d23/pta7 control 228 cs4 /ptk2 in 257 d22/pta6 control 227 cs5 / ce1a /ptk3 in 256 d21/pta5 control 226 ce2a /pte4 in 255 d20/pta4 control 225 ce2b /pte5 in 254 d19/pta3 control 224 a0 out 253 d18/pta2 control 223 a1 out 252 d17/pta1 control 222 a2 out 251 d16/pta0 control 221 a3 out 250 d15 control 220 a4 out 249 d14 control 219 a5 out 248 d13 control 218 a6 out
rev. 5.00, 09/03, page 647 of 760 bit pin name i/o bit pin name i/o 217 a7 out 187 cs4 /ptk2 out 216 a8 out 186 cs5 / ce1a /ptk3 out 215 a9 out 185 cs6 / ce1b out 214 a10 out 184 ce2a /pte4 out 213 a11 out 183 ce2b /pte5 out 212 a12 out 182 a0 control 211 a13 out 181 a1 control 210 a14 out 180 a2 control 209 a15 out 179 a3 control 208 a16 out 178 a4 control 207 a17 out 177 a5 control 206 a18 out 176 a6 control 205 a19 out 175 a7 control 204 a20 out 174 a8 control 203 a21 out 173 a9 control 202 a22 out 172 a10 control 201 a23 out 171 a11 control 200 a24 out 170 a12 control 199 a25 out 169 a13 control 198 bs /ptk4 out 168 a14 control 197 rd out 167 a15 control 196 we0 /dqmll out 166 a16 control 195 we1 /dqmlu/ we out 165 a17 control 194 we2 /dqmul/ iciord / ptk6 out 164 a18 control 193 we3 /dqmuu/ iciowr / ptk7 out 163 a19 control 192 rd/ wr out 162 a20 control 191 audsync /pte7 out 161 a21 control 190 cs0 /mcs0 out 160 a22 control 189 cs2 /ptk0 out 159 a23 control 188 cs3 /ptk1 out 158 a24 control
rev. 5.00, 09/03, page 648 of 760 bit pin name i/o bit pin name i/o 157 a25 control 127 breq in 156 bs/ptk4 control 126 wait in 155 rd control 125 audck/pth6 in 154 we0 /dqmll control 124 iois16 /ptg7 in 153 we1 /dqmlu/ we control 123 asebrkak /ptg5 in 152 we2 /dqmul/ iciord / ptk6 control 122 ckio2/ptg4 in 151 we3 /dqmuu/ iciowr / ptk7 control 121 audata3/ptg3 in 150 rd/ wr control 120 audata2/ptg2 in 149 audsync /pte7 control 119 audata1/ptg1 in 148 cs0 /mcs0 control 118 audata0/ptg0 in 147 cs2 /ptk0 control 117 adtrg /pth5 in 146 cs3 /ptk1 control 116 irls3 /ptf3/pint11 in 145 cs4 /ptk2 control 115 irls2 /ptf2/pint10 in 144 cs5 / ce1a /ptk3 control 114 irls1 /ptf1/pint9 in 143 cs6 / ce1b control 113 irls0 /ptf0/pint8 in 142 ce2a /pte4 control 112 md0 in 141 ce2b /pte5 control 111 cke/ptk5 out 140 cke/ptk5 in 110 ras3l /ptj0 out 139 ras3l /ptj0 in 109 ptj1 out 138 ptj1 in 108 casl /ptj2 out 137 casl /ptj2 in 107 casu /ptj3 out 136 casu /ptj3 in 106 ptj4 out 135 ptj4 in 105 ptj5 out 134 ptj5 in 104 dack0/ptd5 out 133 dack0/ptd5 in 103 dack1/ptd7 out 132 dack1/ptd7 in 102 pte6 out 131 pte6 in 101 pte3 out 130 pte3 in 100 ras3u /pte2 out 129 ras3u /pte2 in 99 pte1 out 128 pte1 in 98 back out
rev. 5.00, 09/03, page 649 of 760 bit pin name i/o bit pin name i/o 97 asebrkak /ptg5 out 65 rxd2/scpt4 in 96 audata3/ptg3 out 64 wakeup /ptd3 in 95 audata2/ptg2 out 63 resetout /ptd2 in 94 audata1/ptg1 out 62 drak0/ptd1 in 93 audata0/ptg0 out 61 drak1/ptd0 in 92 cke/ptk5 control 60 dreq0 /ptd4 in 91 ras3l /ptj0 control 59 dreq1 /ptd6 in 90 ptj1 control 58 rxd1/scpt2 in 89 casl /ptj2 control 57 cts2 /irq5/scpt7 in 88 casu /ptj3 control 56 mcs7 /ptc7/pint7 in 87 ptj4 control 55 mcs6 /ptc6/pint6 in 86 ptj5 control 54 mcs5 /ptc5/pint5 in 85 dack0/ptd5 control 53 mcs4 /ptc4/pint4 in 84 dack1/ptd7 control 52 mcs3 /ptc3/pint3 in 83 pte6 control 51 mcs2 /ptc2/pint2 in 82 pte3 control 50 mcs1 /ptc1/pint1 in 81 ras3u /pte2 control 49 mcs0 /ptc0/pint0 in 80 pte1 control 48 md3 in 79 back control 47 md4 in 78 asebrkak /ptg5 control 46 md5 in 77 audata3/ptg3 control 45 status0/ptj6 out 76 audata2/ptg2 control 44 status1/ptj7 out 75 audata1/ptg1 control 43 tclk/pth7 out 74 audata0/ptg0 control 42 irqout out 73 status0/ptj6 in 41 txd0/scpt0 out 72 status1/ptj7 in 40 sck0/scpt1 out 71 tclk/pth7 in 39 txd1/scpt2 out 70 sck0/scpt1 in 38 sck1/scpt3 out 69 sck1/scpt3 in 37 txd2/scpt4 out 68 sck2/scpt5 in 36 sck2/scpt5 out 67 rts2 /scpt6 in 35 rts2/scpt6 out 66 rxd0/scpt0 in 34 mcs7 /ptc7/pint7 out
rev. 5.00, 09/03, page 650 of 760 bit pin name i/o bit pin name i/o 33 mcs6 /ptc6/pint6 out 15 sck1/scpt3 control 32 mcs5 /ptc5/pint5 out 14 txd2/scpt4 control 31 mcs4 /ptc4/pint4 out 13 sck2/scpt5 control 30 wakeup /ptd3 out 12 rts2/scpt6 control 29 resetout /ptd2 out 11 mcs7 /ptc7/pint7 control 28 mcs3 /ptc3/pint3 out 10 mcs6 /ptc6/pint6 control 27 mcs2 /ptc2/pint2 out 9 mcs5 /ptc5/pint5 control 26 mcs1 /ptc1/pint1 out 8 mcs4 /ptc4/pint4 control 25 mcs0 /ptc0/pint0 out 7 wakeup /ptd3 control 24 drak0/ptd1 out 6 resetout /ptd2 control 23 drak1/ptd0 out 5 mcs3 /ptc3/pint3 control 22 status0/ptj6 control 4 mcs2 /ptc2/pint2 control 21 status1/ptj7 control 3 mcs1 /ptc1/pint1 control 20 tclk/pth7 control 2 mcs0 /ptc0/pint0 control 19 irqout control 1 drak0/ptd1 control 18 txd0/scpt0 control 0 drak1/ptd0 control 17 sck0/scpt1 control to tdo 16 txd1/scpt2 control note: control is an active-low signal. when control is driven low, the corresponding pin is driven by the value of out.
rev. 5.00, 09/03, page 651 of 760 22.4 udi operation 22.4.1 tap controller figure 22.2 shows the internal states of the tap controller. state transitions basically conform with the jtag standard. test-logic-reset capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select-dr-scan run-test/idle 1 0 0 0 0 11 1 1 0 0 1 0 1 1 10 capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select-ir-scan 0 0 1 0 0 1 0 1 1 10 0 figure 22.2 tap controller state transitions note: the transition condition is the tms value at the rising edge of tck. the tdi value is sampled at the rising edge of tck; shifting occurs at the falling edge of tck. the tdo value changes at the tck falling edge. the tdo is at high impedance, except with shift- dr (shift-sr) and shift-ir states. during the change to trst = 0, there is a transition to test-logic-reset asynchronously with tck.
rev. 5.00, 09/03, page 652 of 760 22.4.2 reset configuration table 22.4 reset configuration asemd0 asemd0 asemd0 asemd0 * 1 resetp resetp resetp resetp trst trst trst trst chip state high-level low-level low-level normal reset and udi reset high-level normal reset high-level low-level udi reset only high-level normal operation low-level low-level low-level reset hold * 2 high-level ase user mode * 3 : normal reset ase break mode * 3 : resetp assertion masked high-level low-level udi reset only high-level normal operation notes: 1. selects main chip mode or ase mode asemd0 = h, normal mode asemd0 = l, ase mode set asemd0 = h when using on the user system alone, without an emulator and the udi. 2. in ase mode, reset hold is enabled by driving the resetp and trst pins low for a constant cycle. in this state, the cpu does not start up, even if resetp is driven high. when trst is driven high, udi operation is enabled, but the cpu does not start up. the reset hold state is cancelled by the following: ? boot request from udi ? another resetp assert (power-on reset) 3. there are two ase modes, one for executing software in the emulator?s firmware (ase break mode) and one for executing user software (ase user mode).
rev. 5.00, 09/03, page 653 of 760 22.4.3 udi reset an udi reset is executed by setting an udi reset assert command in sdir. an udi reset is of the same kind as a power-on reset. an udi reset is released by inputting an udi reset negate command. udi reset assert udi reset negate sdir chip internal reset cpu state branch to ha0000000 figure 22.3 udi reset 22.4.4 udi interrupt the udi interrupt function generates an interrupt by setting a command from the udi in the sdir. an udi interrupt is a general exception/interrupt operation, resulting in a branch to an address based on the vbr value plus offset, and with return by the rte instruction. this interrupt request has a fixed priority level of 15. udi interrupts are not accepted in sleep mode or standby mode. 22.4.5 bypass the jtag-based bypass mode for the udi pins can be selected by setting a command from the udi in sdir. 22.4.6 using udi to recover from sleep mode it is possible to recover from sleep mode by setting a command (0001) from the udi in sdir.
rev. 5.00, 09/03, page 654 of 760 22.5 boundary scan a command can be set in sdir by the udi to place the udi pins in the boundary scan mode stipulated by jtag. 22.5.1 supported instructions this lsi supports the three essential instructions defined in the jtag standard (bypass, sample/preload, and extest). bypass: the bypass instruction is an essential standard instruction that operates the bypass register. this instruction shortens the shift path to speed up serial data transfer involving other chips on the printed circuit board. while this instruction is executing, the test circuit has no effect on the system circuits. the instruction code is 1111. sample/preload: the sample/preload instruction inputs values from this lsi's internal circuitry to the boundary scan register, outputs values from the scan path, and loads data onto the scan path. when this instruction is executing, this lsi's input pin signals are transmitted directly to the internal circuitry, and internal circuit values are directly output externally from the output pins. this lsi's system circuits are not affected by execution of this instruction. the instruction code is 0100. in a sample operation, a snapshot of a value to be transferred from an input pin to the internal circuitry, or a value to be transferred from the internal circuitry to an output pin, is latched into the boundary scan register and read from the scan path. snapshot latching is performed in synchronization with the rise of tck in the capture-dr state. snapshot latching does not affect normal operation of this lsi. in a preload operation, an initial value is set in the parallel output latch of the boundary scan register from the scan path prior to the extest instruction. without a preload operation, when the extest instruction was executed an undefined value would be output from the output pin until completion of the initial scan sequence (transfer to the output latch) (with the extest instruction, the parallel output latch value is constantly output to the output pin). extest: this instruction is provided to test external circuitry when this lsi is mounted on a printed circuit board. when this instruction is executed, output pins are used to output test data (previously set by the sample/preload instruction) from the boundary scan register to the printed circuit board, and input pins are used to latch test results into the boundary scan register from the printed circuit board. if testing is carried out by using the extest instruction n times, the nth test data is scanned-in when test data (n-1) is scanned out.
rev. 5.00, 09/03, page 655 of 760 data loaded into the output pin boundary scan register in the capture-dr state is not used for external circuit testing (it is replaced by a shift operation). the instruction code is 0000. 22.5.2 points for attention 1. boundary scan mode covers clock-related signals (extal, extal2, xtal, xtal2, ckio). 2. boundary scan mode does not cover reset-related signals ( resetp , resetm , ca). 3. boundary scan mode does not cover udi-related signals (tck, tdi, tdo, tms, trst). 4. when a boundary scan test is carried out, ensure that the ckio clock operates constantly. the ckio frequency range is as follows: minimum: 1 mhz maximum: maximum frequency for respective clock mode specified in the cpg section set pins md[2:0] to the clock mode to be used. after powering on, wait for the ckio clock to stabilize before performing a boundary scan test. 5. fix the resetp pin low. 6. fix the ca pin high, and the asemd0 pin low. 22.6 usage notes 1. an udi command other than an udi interrupt, once set, will not be modified as long as another command is not re-issued from the udi. an udi interrupt command, however, will be changed to a bypass command once set. 2. because chip operations are suspended in standby mode, udi commands are not accepted. however, the tap controller remains in operation at this time. 3. the udi is used for emulator connection. therefore, udi functions cannot be used when using an emulator. 22.7 advanced user debugger (aud) the aud is a function exclusively for use by an emulator. refer to the user's manual for the relevant emulator for details of the aud.
rev. 5.00, 09/03, page 656 of 760
rev. 5.00, 09/03, page 657 of 760 section 23 electrical characteristics 23.1 absolute maximum ratings table 23.1 shows the absolute maximum ratings. table 23.1 absolute maximum ratings item symbol rating unit power supply voltage (i/o) vccq ?0.3 to 4.2 v power supply voltage (internal) vcc vcc ? pll1 vcc ? pll2 vcc ? rtc ?0.3 to 2.5 v input voltage (except port l) vin ?0.3 to vccq + 0.3 v input voltage (port l) vin ?0.3 to avcc + 0.3 v analog power-supply voltage avcc ?0.3 to 4.6 v analog input voltage v an ?0.3 to avcc + 0.3 v operating temperature topr ?20 to 75 c storage temperature tstr ?55 to 125 c caution: operating the chip in excess of the absolute maximum rating may result in permanent damage. ? order of turning on 1.7 v/1.8 v/1.9 v/2.0 v power (vcc, vcc-pll1, vcc-pll2, vcc-rtc) and 3.3 v power (vccq, avcc): 1. first turn on the 3.3 v power, then turn on the 1.7 v/1.8 v/1.9 v/2.0 v power within 1 ms. this interval should be as short as possible. 2. until voltage is applied to all power supplies, a low level is input at the resetp pin, and ckio has operated for a maximum of 4 clock cycles, internal circuits remain unsettled, and so pin states are also undefined. the system design must ensure that these undefined states do not cause erroneous system operation. note that the resetp pin cannot receive a low level signal while a low level signal is being input to the ca pin. waveforms at power-on are shown in the following figure.
rev. 5.00, 09/03, page 658 of 760 power-on sequence ? power-off order 1. in the reverse order of powering-on, first turn off the 1.7 v/1.8 v/1.9 v/2.0 v power, then turn off the 3.3 v power within 1 ms. this interval should be as short as possible. 2. pin states are undefined while only the 1.7 v/1.8 v/1.9 v/2.0 v power is off. the system design must ensure that these undefined states do not cause erroneous system operation.
rev. 5.00, 09/03, page 659 of 760 23.2 dc characteristics tables 23.2 and 23.3 list dc characteristics. table 23.2 dc characteristics ta = ?20 to 75c item symbol min typ max unit measurement conditions power supply voltage vccq 3.0 3.3 3.6 v vcc, 1.85 2.00 2.15 200 mhz model * vcc-pll1, 1.75 1.90 2.05 167 mhz model vcc-pll2, 1.65 1.80 2.05 133 mhz model vcc-rtc 1.55 1.70 1.95 100 mhz model icc ? 410 680 ma vcc = 2.0 v, i = 200 mhz current dissipation normal operation 330 540 vcc = 1.9 v, i = 167 mhz ? 250 410 vcc = 1.8 v, i = 133 mhz ? 190 310 vcc = 1.7 v, i = 100 mhz iccq ? 20 40 vccq = 3.3 v, b = 33 mhz sleep mode * 1 icc ? 15 30 iccq ? 10 20 * 1 when there is no other external bus cycle other than the refresh cycle. vcc = 1.9 v, vccq = 3.3 v b = 33mhz standby mode icc ? 40 120 a iccq ? 10 30 ta = 25c (rtc on) vccq = 3.3 v, vcc = 1.55 v to 2.15 v icc ? 290 900 iccq ? 10 30 ta = 25c (rtc off), crystal is not used. vccq = 3.3 v, vcc = 1.55 v to 2.15 v
rev. 5.00, 09/03, page 660 of 760 item symbol min typ max unit measurement conditions input high voltage resetp , resetm , nmi, irq5 to irq0, md5 to md0, i rl 3 to irl0 , irls3 to irls0 , pint15 to pint0, asemd0 , adtrg , trst , extal, ckio, rxd1, ca v ih vccq 0.9 ? vccq + 0.3 v extal2 ? ? ? when not connecting to a crystal oscillator, connect to vcc. port l 2.0 ? avcc + 0.3 other input pins 2.0 ? vccq + 0.3
rev. 5.00, 09/03, page 661 of 760 item symbol min typ max unit measurement conditions input low voltage resetp , resetm , nmi, irq5?irq0, md5?md0, irl3 to irl0 , irls3 to irls0 , pint15? pint0, asemd0 , adtrg , trst , extal, ckio, rxd1, ca v il ?0.3 ? vccq 0.1 v extal2 ? ? ? when not connecting to a crystal oscillator, connect to vcc. port l ?0.3 ? avcc 0.2 other input pins ?0.3 ? vccq 0.2 input leak current all input pins i iin i ? ? 1.0 a vin = 0.5 to vccq?0.5 v three- state leak current i/o, all output pins (off condition) i isti i ? ? 1.0 a vin = 0.5 to vccq?0.5 v output high voltage all output pins v oh 2.4 ? ? v vccq = 3.0 v, i oh = ?200 a 2.0 ? ? vccq = 3.0 v, i oh = ?2 ma output low voltage all output pins v ol ? ? 0.55 vccq = 3.6 v, i ol = 1.6 ma pull-up resistance port pin rpull 30 60 120 k ? pin capacity all pins c ? ? 10 pf
rev. 5.00, 09/03, page 662 of 760 item symbol min typ max unit measurement conditions analog power- supply voltage avcc 3.0 3.3 3.6 v analog power- supply during a/d conversion aicc ? 0.8 2 ma current during a/d and d/a conversion ?2.46 ma idle ? 1 20 a ta = 25c notes: even when pll is not used, always connect vcc-pll1 and vcc-pll2 to vcc and connect vss-pll1 and vss-pll2 to vss. even when rtc is not used, always supply power between vcc-rtc and vss-rtc. avcc must be under condition of vccq ? 0.3 v avcc vccq + 0.3 v. if the a/d and d/a converters are not used, do not leave the avcc and avss pins open. connect avcc to vccq, and connect avss to vssq. current dissipation values shown are the values at which all output pins are without load under conditions of v ih min = vccq ? 0.5 v, v il max = 0.5 v. the same voltage should be supplied to vcc, vcc-rtc, vcc-pll1, and vcc-pll2. * if the irl and irls interrupts are used, the minimum is 1.9 v. table 23.3 permitted output current values vccq = 3.3 0.3 v, vcc = 1.55 to 2.15 v, avcc = 3.3 0.3 v, ta = ?20 to 75c item symbol min typ max unit output low-level permissible current (per pin) i ol ??2.0ma output low-level permissible current (total) i ol ??120ma output high-level permissible current (per pin) ?i oh ??2.0ma output high-level permissible current (total) (?i oh )??40ma caution: to ensure lsi reliability, do not exceed the value for output current given in table 23.3.
rev. 5.00, 09/03, page 663 of 760 23.3 ac characteristics in general, inputting for this lsi should be clock synchronous. keep the setup and hold times for each input signal unless otherwise specified. table 23.4 operating frequency range vccq = 3.3 0.3 v, vccq = 1.55 to 2.15 v, avcc = 3.3 0.3 v, ta = ?20 to 75c item symbol min typ max unit remarks cpu, cache, tlb f 30 ? 200 mhz 200 mhz model operating frequency 25 167 167 mhz model 133 133 mhz model 100 100 mhz model external bus 30 ? 66.67 200 mhz model 25 167 mhz model 133 mhz model 100 mhz model peripheral module 7.5 ? 33.34 200 mhz model 6.25 167 mhz model 133 mhz model 100 mhz model
rev. 5.00, 09/03, page 664 of 760 23.3.1 clock timing table 23.5 clock timing vccq = 3.3 0.3 v, vcc = 1.55 to 2.15 v, avcc = 3.3 0.3 v, ta = ?20 to 75c item symbol min max unit figure extal clock input frequency (clock mode 0) f ex 25 66.67 mhz 23.1 extal clock input cycle time (clock mode 0) t excyc 15 40 ns extal clock input frequency (clock mode 1) f ex 6.25 16.67 mhz extal clock input cycle time (clock mode 2) t excyc 60 160 ns extal clock input low pulse width t exl 1.5 ? ns extal clock input high pulse width t exh 1.5 ? ns extal clock input rise time t exr ?6 ns extal clock input fall time t exf ?6 ns ckio clock input frequency f cki 20 66 mhz 23.2 ckio clock input cycle time t ckicyc 15.2 40 ns ckio clock input low pulse width t ckil 1.5 ? ns ckio clock input high pulse width t ckih 1.5 ? ns ckio clock input rise time t ckir ?6 ns ckio clock input fall time t ckif ?6 ns ckio clock output frequency f op 25 66 mhz 23.3 ckio clock output cycle time t cyc 15.2 40 ns ckio clock output low pulse width t ckol 3?ns ckio clock output high pulse width t ckoh 3?ns ckio clock output rise time t ckor ?5 ns ckio clock output fall time t ckof ?5 ns ckio2 clock output delay time t ck2d ?3 3 ns ckio2 clock output rise time t ck20r ?7 ns ckio2 clock output fall time t ck20f ?7 ns power-on oscillation settling time t osc1 10 ? ms 23.4 resetp setup time t resps 20 ? ns 23.4, 23.5 resetm setup time t resms 6?ns resetp assert time t respw 20 ? t cyc resetm assert time t resmw 20 ? t cyc standby return oscillation settling time 1 t osc2 10 ? ms 23.5 standby return oscillation settling time 2 t osc3 10 ? ms 23.6 standby return oscillation settling time 3 t osc4 11 ? ms 23.7 pll synchronization settling time 1 (standby canceled) t pll1 100 ? s 23.8, 23.9 pll synchronization settling time 2 (multiplication rete modified) t pll2 100 ? s 23.10 irq/irl interrupt determination time (rtc used and standby mode) t irlstb 100 ? s 23.9
rev. 5.00, 09/03, page 665 of 760 t exh t exf t exr t exl t excyc v ih v ih v ih 1/2 v cc q 1/2 v cc q v il v il extal * (input) note: * the clock input from the extal pin. figure 23.1 extal clock input timing t ckih t ckif t ckir t ckil t ckicyc v ih 1/2 v cc q 1/2 v cc q v ih v il v ih v il ckio (input) figure 23.2 ckio clock input timing t cyc t ckol t ckoh v oh 1/2v cc q ckio (output) 1/2v cc q t ckor t ckof v oh v ol v ol v oh t ck2d t ck2d v oh ckio2 (output) t ck2or t ck2of v oh v ol v ol v oh figure 23.3 ckio clock output timing
rev. 5.00, 09/03, page 666 of 760 figure 23.4 power-on oscillation settling time figure 23.5 oscillation settling time at standby return (return by reset)
rev. 5.00, 09/03, page 667 of 760 figure 23.6 oscillation settling time at standby return (return by nmi) figure 23.7 oscillation settling time at standby return (return by irq4 to irq0, pint0/1, irl3 irl3 irl3 irl3 to irl0 irl0 irl0 irl0 )
rev. 5.00, 09/03, page 668 of 760 extal input or ckio input stable input clock reset or nmi interrupt request stable input clock normal normal standby pll output, ckio output internal clock status 0 status 1 pll synchronization note: pll oscillation settling time during the continued oscillation mode or when clock is input from extal pin or ckio pin t pll1 pll synchronization figure 23.8 pll synchronization settling time during standby recovery (reset or nmi) figure 23.9 pll synchronization settling time during standby recovery (irq/irl or pint0/pint1 interrupt)
rev. 5.00, 09/03, page 669 of 760 extal input * 1 (ckio input) ckio output * 2 (pll output) internal clock multiplication rate modified t pll2 notes: 1. ckio input in clock mode 7 2. pll output in other than clock mode 7 figure 23.10 pll synchronization settling time when frequency multiplication rate modified
rev. 5.00, 09/03, page 670 of 760 23.3.2 control signal timing table 23.6 control signal timing vcc = 3.3 0.3 v, vcc = 1.55 to 2.15 v, avcc = 3.3 0.3 v, ta = ?20 to 75c item symbol min max unit figure resetp pulse width t respw 20 * 2 ?tcyc23.11, resetp setup time * 1 t resps 20 ? ns 23.12 resetp hold time t resph 4?ns resetm pulse width t resmw 20 * 3 ?tcyc resetm setup time t resms 6?ns resetm hold time t resmh 34 ? ns breq setup time t breqs 6?ns23.14 breq hold time t breqh 4?ns nmi setup time * 1 t nmis 10 ? ns 23.12 nmi hold time t nmih 4?ns irq5?irq0 setup time * 1 t irqs 10 ? ns irq5?irq0 hold time t irqh 4?ns irqout delay time t irqod ?10ns23.13 back delay time t backd ?10ns23.14, status1, status0 delay time t std ?10ns23.15 bus tri-state delay time 1 t boff1 015ns bus tri-state delay time 2 t boff2 015ns bus buffer-on time 1 t bon1 015ns bus buffer-on time 2 t bon2 015ns notes: 1. resetp , nmi, and irq5 to irq0 are asynchronous. changes are detected at the clock fall when the setup shown is used. when the setup cannot be used, detection can be delayed until the next clock falls. 2. in the standby mode, t respw = t osc1 (100 s) when xtal oscillation is continued and t respw = t osc2 (10 ms) when xtal oscillation is off. in the sleep mode, t respw = t pll1 (100 s). when the clock multiplication ratio is changed, t respw = t pll1 (100 s). 3. in the standby mode, t resmw = t osc2 (10 ms). in the sleep mode, resetm must be kept low until status (0-1) changes to reset (hh). when the clock multiplication ratio is changed, resetm must be kept low until status (0-1) changes to reset (hh).
rev. 5.00, 09/03, page 671 of 760 figure 23.11 reset input timing figure 23.12 interrupt signal input timing figure 23.13 irqout irqout irqout irqout timing
rev. 5.00, 09/03, page 672 of 760 figure 23.14 bus release timing figure 23.15 pin drive timing at standby
rev. 5.00, 09/03, page 673 of 760 23.3.3 ac bus timing table 23.7 bus timing clock modes 0/1/2/7, vccq = 3.3 0.3 v, vcc = 1.55 to 2.15 v, avcc = 3.3 0.3 v, ta = ?20 to 75c item symbol min max unit figure address delay time t ad 1.5 12 ns 23.16?23.36, 23.39?23.46 address setup time t as 0 ? ns 23.16?23.18 address hold time * 1 t ah 4 ? ns 23.16?23.21 bs delay time t bsd ? 10 ns 23.16?23.36, 23.40?23.46 cs delay time 1 t csd1 0 10 ns 23.16?23.21, 23.40?23.46 cs delay time 2 t csd2 ? 10 ns 23.16?23.21 cs delay time (sdram access) t csd3 1.5 10 ns 23.22?23.39 read/write delay time t rwd 1.5 10 ns 23.16?23.46, 23.39?23.46 read/write hold time t rwh 0 ? ns 23.16?23.21 read strobe delay time t rsd ? 10 ns 23.16?23.21 23.40?23.43 read data setup time 1 t rds1 6 ? ns 23.16?23.21, 23.40?23.46 read data setup time 2 t rds2 5 ? ns 23.22?23.25, 23.30?23.33 read data hold time 1 * 2 t rdh1 0 ? ns 23.16?23.21, 23.40?23.46 read data hold time 2 t rdh2 1 ? ns 23.22?23.25, 23.30?23.33 write enable delay time t wed ? 10 ns 23.16?23.18, 23.40, 23.41 write data delay time 1 t wdd1 ? 14 ns 23.16?23.18, 23.40, 23.41, 23.44?23.46 write data delay time 2 t wdd2 1.5 12 ns 23.26?23.29, 23.34?23.36 write data hold time 1 t wdh1 1.5 ? ns 23.16?23.18, 23.40, 23.41, 23.44?23.46 write data hold time 2 t wdh2 1.5 ? ns 23.26?23.29, 23.34?23.36 write data hold time 3 t wdh3 2 ? ns 23.16?23.18 write data hold time 4 t wdh4 2 ? ns 23.40, 23.41, 23.44?23.46 wait setup time t wts 5 ? ns 23.17?23.21, 23.41, 23.43, 23.45, 23.46 wait hold time t wth 0 ? ns 23.17?23.21, 23.41, 23.43, 23.45, 23.46 ras delay time 2 t rasd2 1.5 10 ns 23.22?23.39 cas delay time 2 t casd2 1.5 10 ns 23.22?23.39 dqm delay time t dqmd 1.5 10 ns 23.22?23.36 cke delay time t cked 1.5 10 ns 23.38
rev. 5.00, 09/03, page 674 of 760 item symbol min max unit figure iciord delay time t icrsd ? 10 ns 23.44?23.46 iciowr delay time t icwsd ? 10 ns 23.44?23.46 iois16 setup time t io16s 6 ? ns 23.45, 23.46 iois16 hold time t io16h 4 ? ns 23.45, 23.46 dack delay time 1 (reference for ckio rise) t dakd1 ? 10 ns 23.16?23.36, 23.39?23.46 dack delay time 2 (reference for ckio fall) t dakd2 ? 10 ns 23.16?23.22 notes: 1. specified based on the slowest negate timing for csn , rd , or wen 2. specified based on whichever negate timing is faster, csn or rd .
rev. 5.00, 09/03, page 675 of 760 23.3.4 basic timing t 1 ckio a25 to a0 rd/ d31 to d0 (read) d31 to d0 (write) bs t 2 t ad t ah t ad t csd1 t rwd t rsd figure 23.16 basic bus cycle (no wait)
rev. 5.00, 09/03, page 676 of 760 t 1 t w t 2 ckio a25 to a0 rd/ d31 to d0 (read) d31 to d0 (write) t ad t ad t rwd t rwh t ah t ah t rsd t csd1 t wed figure 23.17 basic bus cycle (one wait)
rev. 5.00, 09/03, page 677 of 760 figure 23.18 basic bus cycle (external wait, waitsel = 1)
rev. 5.00, 09/03, page 678 of 760 23.3.5 burst rom timing figure 23.19 burst rom bus cycle (no wait)
rev. 5.00, 09/03, page 679 of 760 figure 23.20 burst rom bus cycle (two waits)
rev. 5.00, 09/03, page 680 of 760 figure 23.21 burst rom bus cycle (external wait, waitsel = 1)
rev. 5.00, 09/03, page 681 of 760 23.3.6 synchronous dram timing cke figure 23.22 synchronous dram read bus cycle (rcd = = = = 0, cas latency = = = = 1, tpc = = = = 0)
rev. 5.00, 09/03, page 682 of 760 figure 23.23 synchronous dram read bus cycle (rcd = = = = 2, cas latency = = = = 2, tpc = = = = 1)
rev. 5.00, 09/03, page 683 of 760 figure 23.24 synchronous dram read bus cycle (burst read (single read 4), rcd = = = = 0, cas latency = = = = 1, tpc = = = = 1)
rev. 5.00, 09/03, page 684 of 760 figure 23.25 synchronous dram read bus cycle (burst read (single read 4), rcd = = = = 1, cas latency = = = = 3, tpc = = = = 0)
rev. 5.00, 09/03, page 685 of 760 figure 23.26 synchronous dram write bus cycle (rcd = = = = 0, tpc = = = = 0, trwl = 0)
rev. 5.00, 09/03, page 686 of 760 figure 23.27 synchronous dram write bus cycle (rcd = = = = 2, tpc = = = = 1, trwl = 1)
rev. 5.00, 09/03, page 687 of 760 figure 23.28 synchronous dram write bus cycle (burst mode (single write 4), rcd = = = = 0, tpc = = = = 1, trwl = 0)
rev. 5.00, 09/03, page 688 of 760 figure 23.29 synchronous dram write bus cycle (burst mode (single write 4), rcd = = = = 1, tpc = = = = 0, trwl = 0)
rev. 5.00, 09/03, page 689 of 760 figure 23.30 synchronous dram burst read bus cycle (ras down, same row address, cas latency = 1)
rev. 5.00, 09/03, page 690 of 760 a25 to a16 (high) t ad t ad t ad t casd2 t csd3 t rwd t dqmd t bsd t rdh2 t rds2 t rdh2 t rds2 t bsd t rasd2 t casd2 t dqmd t rwd t csd3 t ad t ad t ad tc1 tc2 tc3/td1 tc4/td2 td3 td4 ckio a12 or a10 a15 to a0 csn rd/ wr ras cas dqmxx d31 to d0 bs cke row address dackn t dakd1 t dakd1 column address read command figure 23.31 synchronous dram burst read bus cycle (ras down, same row address, cas latency = 2)
rev. 5.00, 09/03, page 691 of 760 figure 23.32 synchronous dram burst read bus cycle (ras down, different row address, tpc = 0, rcd = 0, cas latency = 1)
rev. 5.00, 09/03, page 692 of 760 figure 23.33 synchronous dram burst read bus cycle (ras down, different row address, tpc = 1, rcd = 0, cas latency = 1)
rev. 5.00, 09/03, page 693 of 760 figure 23.34 synchronous dram burst write bus cycle (ras down, same row address)
rev. 5.00, 09/03, page 694 of 760 figure 23.35 synchronous dram burst write bus cycle (ras down, different row address, tpc = 0, rcd = 0)
rev. 5.00, 09/03, page 695 of 760 figure 23.36 synchronous dram burst write bus cycle (ras down, different row address, tpc = 1, rcd = 1)
rev. 5.00, 09/03, page 696 of 760 figure 23.37 synchronous dram auto-refresh timing (tras = 1, tpc = 1)
rev. 5.00, 09/03, page 697 of 760 figure 23.38 synchronous dram self-refresh cycle (tras = = = = 1, tpc = = = = 1)
rev. 5.00, 09/03, page 698 of 760 figure 23.39 synchronous dram mode register write cycle
rev. 5.00, 09/03, page 699 of 760 23.3.7 pcmcia timing figure 23.40 pcmcia memory bus cycle (ted = 0, teh = 0, no wait)
rev. 5.00, 09/03, page 700 of 760 figure 23.41 pcmcia memory bus cycle (ted = 2, teh = 1, one wait, external wait, waitsel = 1)
rev. 5.00, 09/03, page 701 of 760 figure 23.42 pcmcia memory bus cycle (burst read, ted = 0, teh = 0, no wait)
rev. 5.00, 09/03, page 702 of 760 figure 23.43 pcmcia memory bus cycle (burst read, ted = 1, teh = 1, two waits, burst pitch = 3, waitsel = 1)
rev. 5.00, 09/03, page 703 of 760 figure 23.44 pcmcia i/o bus cycle (ted = 0, teh = 0, no wait)
rev. 5.00, 09/03, page 704 of 760 figure 23.45 pcmcia i/o bus cycle (ted = 2, teh = 1, one wait, external wait, waitsel = 1)
rev. 5.00, 09/03, page 705 of 760 figure 23.46 pcmcia i/o bus cycle (ted = 1, teh = 1, one wait, bus sizing, waitsel = 1)
rev. 5.00, 09/03, page 706 of 760 23.3.8 peripheral module signal timing table 23.8 peripheral module signal timing vccq = 3.3 0.3 v, vcc = 1.55 to 2.15 v, avcc = 3.3 0.3 v, ta = ?20 to 75c module item symbol min max unit figure timer input setup time t tclks 15 ? ns 23.47 tmu, rtc timer clock input setup time t tcks 15 ? 23.48 edge specification t tckwh 1.5 ? pcyc timer clock pulse width both edge specification t tckwl 2.5 ? oscillation settling time t rosc 3 ? s 23.49 sci asynchronization t scyc 4?pcyc * 23.50 input clock cycle clock synchronization 6 ? 23.51 input clock rise time t sckr ? 1.5 23.50 input clock fall time t sckf ?1.5 input clock pulse width t sckw 0.4 0.6 tscyc transmission data delay time t txd ? 100 ns 23.51 receive data setup time (clock synchronization) t rxs 100 ? receive data hold time (clock synchronization) t rxh 100 ? rts delay time t rtsd ?100 cts setup time (clock synchronization) t ctss 100 ? cts hold time (clock synchronization) t ctsh 100 ? port output data delay time t portd ? 17 ns 23.52 input data setup time t ports1 15 ? input data hold time t porth1 8? input data setup time t ports2 tcyc + 15 ? input data hold time t porth2 8? input data setup time t ports3 3 tcyc + 15 ? input data hold time t porth3 8? dmac dreq setup time t drqs 6 ? ns 23.53 dreq hold time t dreqh 4? drak delay time t drakd ? 10 23.54 note: * pcyc is the p clock cycle.
rev. 5.00, 09/03, page 707 of 760 figure 23.47 tclk input timing t tcks t tcks t tckwh t tckwl ckio tclk (input) figure 23.48 tclk clock input timing rtc crystal oscillator stable oscillation v cc v ccmin t rosc figure 23.49 oscillation settling time at rtc crystal oscillator power-on t sckw sck (input) t sckr t sckf t scyc figure 23.50 sck input clock timing
rev. 5.00, 09/03, page 708 of 760 t scyc t txd sck txd (data trans- missiion) rxd (data reception) t rxh t rxs t rtsd rts cts t ctsh t ctss figure 23.51 sci i/o timing in clock synchronous mode figure 23.52 i/o port timing figure 23.53 dreq dreq dreq dreq input timing
rev. 5.00, 09/03, page 709 of 760 figure 23.54 drak output timing 23.3.9 udi-related pin timing table 23.9 udi-related pin timing vccq = 3.3 0.3v, vcc = 1.55 to 2.15 v, avcc = 3.3 0.3v, ta = ?20 to 75 c item symbol min max unit figure tck cycle time t tckcyc 50 ? ns 23.55 tck high pulse width t tckh 12 ? ns tck low pulse width t tckl 12 ? ns tck rise/fall time t tckf ?4 ns trst setup time t trsts 12 ? ns 23.56 trst hold time t trsth 50 ? t cyc tdi setup time t tdis 10 ? ns 23.57 tdi hold time t tdih 10 ? ns tms setup time t tmss 10 ? ns tms hold time t tmsh 10 ? ns tdo delay time t tdod ?16ns asemd0 setup time t asemdh 12 ? ns 23.58 asemd0 hold time t asemds 12 ? ns figure 23.55 tck input timing
rev. 5.00, 09/03, page 710 of 760 figure 23.56 trst trst trst trst input timing (reset hold) tck tdi tms t tdis t tmss t tdih t tckcyc t tmsh t tdod tdo figure 23.57 udi data transfer timing figure 23.58 asemd0 asemd0 asemd0 asemd0 input timing
rev. 5.00, 09/03, page 711 of 760 23.3.10 ac characteristics measurement conditions ? i/o signal reference level: vccq/2 (vccq = 3.3 0.3 v, vcc = 1.55 to 2.15 v) ? input pulse level: vss to 3.0 v (where resetp , resetm , asend0 , irls3 to irls0 , irl3 to irl0 , adtrg , pint15 to pint0, trst , rxd1, ca, nmi, irq5 ? irq0 , ckio, and md5?md0 are within vss to vcc) ? input rise and fall times: 1 ns figure 23.59 output load circuit
rev. 5.00, 09/03, page 712 of 760 23.3.11 delay time variation due to load capacitance a graph (reference data) of the variation in delay time when a load capacitance greater than that stipulated (30 or 50 pf) is connected to this lsi's pins is shown below. the graph shown in figure 23.60 should be taken into consideration in the design process if the stipulated capacitance is exceeded in connecting an external device. if the connected load capacitance exceeds the range shown in figure 23.60, the graph will not be a straight line. figure 23.60 load capacitance vs. delay time
rev. 5.00, 09/03, page 713 of 760 23.4 a/d converter characteristics table 23.10 lists the a/d converter characteristics. table 23.10 a/d converter characteristics vccq = 3.3 0.3 v, vcc = 1.55 to 2.15 v, avcc = 3.3 0.3 v, ta = ?20 to 75c item min typ max unit resolution 10 10 10 bits conversion time 15 ? ? s analog input capacitance ? ? 20 pf permissible signal-source (single- source) impedance ??5 k ? nonlinearity error ? ? 3.0 lsb offset error ? ? 2.0 lsb full-scale error ? ? 2.0 lsb quantization error ? ? 0.5 lsb absolute accuracy ? ? 4.0 lsb 23.5 d/a converter characteristics table 23.11 lists the d/a converter characteristics. table 23.11 d/a converter characteristics vccq = 3.3 0.3 v, vcc = 1.55 to 2.15 v, avcc = 3.3 0.3 v, ta = ?20 to 75c item min typ max unit test conditions resolution 8 8 8 bits conversion time ? ? 10.0 s 20-pf capacitive load absolute accuracy ? 2.5 4.0 lsb 2-m ? resistance load
rev. 5.00, 09/03, page 714 of 760
rev. 5.00, 09/03, page 715 of 760 appendix a pin functions a.1 pin states table a.1 shows pin states during resets, power-down states, and the bus-released state. table a.1 pin states during resets, power-down states, and bus-released state reset power-down category pin power-on reset manual reset standby sleep bus released extal i iiii xtal o * 1 o * 1 o * 1 o * 1 o * 1 ckio io * 1 io * 1 io * 1 io * 1 io * 1 extal2 i iiii xtal2 o oooo clock cap1, cap2 ? ???? resetp i iiii resetm i iiii breq i iiii back o ooo l md[5:0] i iiii ca i iiii system control status[1:0]/ptj[7:6] o op * 2 op * 2 op * 2 op * 2 irq[3:0]/ irl[3:0] / pth[3:0] v * 7 iiii irq[4]/ pth[4] v * 7 iiii nmi i iiii irls[3:0] /ptf[3:0]/ pint[11:8] viizii mcs [7:0]/ptc[7:0]/ pint[7:0] vop * 2 zh * 10 k * 2 op * 2 zp * 2 tck/ptf[4]/pint[12] iv i iz i i tdi/ptf[5]/pint[13] iv i iz i i tms/ptf[6]/pint[14] iv i iz i i trst /ptf[7]/pint[15] iv i iz i i interrupt irqout o oooo
rev. 5.00, 09/03, page 716 of 760 reset power-down category pin power-on reset manual reset standby sleep bus released address bus a[25:0] z o zl * 9 oz d[15:0] z i z io z d[23:16]/pta[7:0] z ip * 2 zk * 2 iop * 2 zp * 2 data bus d[31:24]/ptb[7:0] z ip * 2 zk * 2 iop * 2 zp * 2 cs0 / mcs0 hozh * 10 oz cs[2:4] /ptk[0:2] h op * 2 zh * 10 k * 2 op * 2 zp * 2 cs5 / ce1a /ptk[3] h op * 2 zh * 10 k * 2 op * 2 zp * 2 cs6 / ce1b hozh * 10 oz bs /ptk[4] h op * 2 zh * 10 k * 2 op * 2 zp * 2 ras3l /ptj[0] h op * 2 zok * 3 op * 2 zop * 3 ras3u /pte[2] v op * 2 zok * 3 op * 2 zop * 3 casl /ptj[2] h op * 2 zok * 3 op * 2 zop * 3 casu /ptj[3] h op * 2 zok * 3 op * 2 zop * 3 we0 /dqmll h o zh * 10 oz we1 /dqmlu/ we hozh * 10 oz we2 /dqmul/ iciord / ptk[6] hop * 2 zh * 10 k * 2 op * 2 zp * 2 we3 /dqmuu/ iciowr / ptk[7] hop * 2 zh * 10 k * 2 op * 2 zp * 2 rd/ wr hozh * 10 oz rd hozh * 10 oz cke/ptk[5] h op * 2 ok * 2 op * 2 op * 2 bus control wait ziziz dreq0 /ptd[4] v zi * 6 zi i dack0 /ptd[5] v op * 2 zk * 2 op * 2 op * 2 drak0/ptd[1] v op * 2 zh * 10 k * 2 op * 2 op * 2 dreq1 /ptd[6] v zi * 6 zi i dack1 /ptd[7] v op * 2 zk * 2 op * 2 op * 2 dmac drak1/ptd[0] v op * 2 zh * 10 k * 2 op * 2 op * 2 timer tclk/pth[7] v zp iop * 4 iop * 4 iop * 4
rev. 5.00, 09/03, page 717 of 760 reset power-down category pin power-on reset manual reset standby sleep bus released rxd0/scpt[0] z zi * 6 ziz * 5 iz * 5 txd0/scpt[0] z zo * 6 zk * 2 oz * 5 oz * 5 sci/smart card without fifo sck0/scpt[1] v zp * 2 zk * 2 iop * 4 iop * 4 rxd1/scpt[2] z zi * 6 ziz * 5 iz * 5 txd1/scpt[2] z zo * 6 zk * 2 oz * 5 oz * 5 scif/irda with fifo sck1/scpt[3] v zp * 2 zk * 2 iop * 4 iop * 4 rxd2/scpt[4] z zi * 6 ziz * 5 iz * 5 txd2/scpt[4] z zo * 6 zk * 2 oz * 5 oz * 5 sck2/scpt[5] v zp * 2 zk * 2 iop * 4 iop * 4 rts2 /scpt[6] v op * 2 zk * 2 op * 2 op * 2 scif with fifo cts2 /irq5/scpt[7] v * 7 zi * 6 iii audsync /pte[7] ov op * 2 ok * 2 op * 2 op * 2 ce2b /pte[5] v op * 2 zh * 10 k * 2 op * 2 zp * 2 ce2a /pte[4] v op * 2 zh * 10 k * 2 op * 2 zp * 2 tdo/pte[0] ov op * 2 ok * 2 op * 2 op * 2 iois16 /ptg[7] v i z i i ptg[5:0] v i z i i audck/pht[6] v i z i i adtrg /pth[5] v * 7 iizi i wakeup /ptd[3] v op * 2 ok * 2 op * 2 zp * 2 resetout /ptd[2] o op * 2 zk * 2 op * 2 op * 2 audata[3:0]/ptg[3:0] ov ok ok ok ok ckio2/ptg[4] v oi oz oi oi asebrkak /ptg[5] ov oi oz oi oi asemd0 /ptg[6] i i z i i ptj[1] h op * 2 zok * 3 op * 2 zop * 3 pte[1] v op * 2 zok * 3 op * 2 zop * 3 pte[6] v op * 2 zok * 3 op * 2 zop * 3 pte[3] v op * 2 zok * 3 op * 2 zop * 3 ptj[4] h op * 2 zok * 3 op * 2 zop * 3 port ptj[5] h op * 2 zok * 3 op * 2 zop * 3
rev. 5.00, 09/03, page 718 of 760 reset power-down category pin power-on reset manual reset standby sleep bus released an[5:0]/ptl[5:0] z zi * 6 zi i analog an[6:7]/da[1:0]/ptl[6:7] z zi * 6 oz * 11 io * 8 io * 8 i: input o: output h: high-level output l: low-level output z: high impedance p: input or output depending on register setting k: input pin is high impedance, output pin holds its state v: i/o buffer off, pull-up mos on notes: 1. depending on the clock mode (md2?md0 setting). 2. k or p when the port function is used. 3. k or p when the port function is used. z or o when the port function is not used depending on register setting. 4. k or p when the port function is used. i or o when the port function is not used depending on register setting. 5. depending on register setting. 6. i or o when the port function is used. 7. input schmitt buffers of irq[5.0] and adtrg on; other input buffers off. 8. o when da output is enabled; otherwise i depending on register setting. 9. in standby mode, z or l depending on register setting. 10. in standby mode, z or h depending on register setting. 11. o when da output is enabled; z otherwise.
rev. 5.00, 09/03, page 719 of 760 a.2 pin specifications table a.2 shows the pin specifications. table a.2 pin specifications pin pin no. (fp-208c, fp-208e) pin no. (bp-240a) i/o function md5 197 c6 i operating mode pin (endian mode) md4, md3 196, 195 d6, a7 i operating mode pin (area 0 bus width) md2 to md0 2, 1, 144 c2, d2,g19 i operating mode pin (clock mode) ras3l /ptj[0] 106 u18 i/o ras (sdram) / i/o port ptj[1] 107 u19 i/o i/o port ce2a /pte[4] 103 v17 i/o pcmcia ce2a / i/o port ce2b /pte[5] 104 v16 i/o pcmcia ce2b / i/o port rxd0/scpt[0] 171 b13 i serial port 0 data input / input port rxd1/scpt[2] 172 c13 i serial port 1 data input / input port rxd2/scpt[4] 174 b12 i serial port 2 data input / input port txd0/scpt[0] 164 c15 o serial port 0 data output / output port txd1/scpt[2] 166 a14 o serial port 1 data output / output port txd2/scpt[4] 168 c14 o serial port 2 data output / output port sck0/scpt[1] 165 d15 i/o serial port 0 clock input/output / i/o port sck1/scpt[3] 167 b14 i/o serial port 1 clock input/output / i/o port sck2/scpt[5] 169 d14 i/o serial port 2 clock input/output / i/o port rts2 /scpt[6] 170 a13 i/o serial port 2 transfer request / i/o port status1/ptj[7] 158 b17 i/o processor state / i/o port status0/ptj[6] 157 b16 i/o processor state / i/o port
rev. 5.00, 09/03, page 720 of 760 pin pin no. (fp-208c, fp-208e) pin no. (bp-240a) i/o function a25 to a0 86, 84, 82, 80, 78 to 72, 70, 68 to 60, 58, 56 to 53 v12, t12, v11, w10, v10, u9, t9, v9, w9, t8, u8, w8, u7, v7, w7, t6, u6, v6, w6, t5, u5, w5, w4, v5, v3, v4 o address bus d31 to d24/ ptb[7] to ptb[0] 13 to 18, 20, 22 f4, g1, g2, g3, g4, h1, h3, j1 i/o data bus / i/o port d23 to d16/ pta[7] to pta[0] 23 to 26, 28, 30 to 32 j2, j4, j3, k2, k1, l2, l1, m4 i/o data bus / i/o port d15 to d0 34, 36 to 44, 46, 48 to 52 m2, n4, n3, n2, n1, p4, p3, p2, p1, r4, t4, t3, t1, r2, u2,t2 i/o data bus mcs[7:0] / ptc[7:0]/ pint[7:0] 177 to 180,185 to 188 b11, d11, c11, b10, d9, b9, a9, d8 i/o mask rom chip select / i/o port / port interrupt request wakeup /ptd[3] 182 d10 i/o wakeup / i/o port resetout / ptd[2] 184 c9 i/o reset output / i/o port drak0/ptd[1] 189 c8 i/o dma control pin / i/o port drak1/ptd[0] 190 b8 i/o dma control pin / i/o port dreq0 /ptd[4] 191 a8 i dma transfer request 0 / input port dreq1 /ptd[6] 192 d7 i dma transfer request 1 / input port an[5:0]/ptl[5:0] 204 to 199 c4, a5, d4, c5, d5, a6 i analog input pin / input port an[7:6]/da[1:0]/ ptl[7:6] 207, 206 b3, b5 i/o analog i/o pin / input port cs6 / ce1b 102 v15 o chip select 6 / pcmcia ce1b cs5 / ce1a / ptk[3] 101 w16 i/o chip select 5 / pcmcia ce2b / i/o port cs4 /ptk[2] 100 u16 i/o chip select 4 / i/o port cs3 /ptk[1] 99 w15 i/o chip select 3 / i/o port
rev. 5.00, 09/03, page 721 of 760 pin pin no. (fp-208c, fp-208e) pin no. (bp-240a) i/o function cs2 /ptk[0] 98 t16 i/o chip select 2 / i/o port cs0 / mcs0 96 t15 o chip select 0 / mask rom chip select 0 bs /ptk[4] 87 w12 i/o bus cycle start / i/o port ptj[5] 113 r17 i/o i/o port ptj[4] 112 u17 i/o i/o port casu /ptj[3] 110 t17 i/o cas(sdram) / i/o port casl /ptj[2] 108 r18 i/o cas(sdram) / i/o port dack0 /ptd[5] 114 r16 i/o dma transfer strobe 0 / i/o port dack1 /ptd[7] 115 p19 i/o dma transfer strobe 1 / i/o port rd 88 t13 o read strobe pin we0 / dqmll 89 u13 o d7?d0 select signal/ dqm(sdram) we1 /dqmlu/ we 90 v13 o d15?d8 select signal / dqm(sdram)/ pcmcia we signal we2 /dqmul/ iciord /ptk[6] 91 w13 i/o d23?d16 select signal / dqm(sdram) / pcmcia iord signal / i/o port we3 /dqmuu/ iciowr /ptk[7] 92 t14 i/o d31?d24 select signal /dqm(sdram) / pcmcia iowr signal / i/o port rd/ wr 93 u14 o read/write select signal audsync / pte[7] 94 v14 i/o aud synchronous i/o port pte[6] 116 p18 i/o i/o port pte[3] 117 p17 i/o i/o port ras3u /pte[2] 118 p16 i/o ras(sdram) / i/o port pte[1] 119 n19 i/o i/o port tdo/pte[0] 120 n18 i/o test data output i/o port resetm 124 m18 i manual reset input adtrg /pth[5] 125 m17 i adc trigger request / input port iois16 /ptg[7] 126 m16 i i/o for pc card / input port asmd0 /ptg[6] 127 l19 i ase mode / input port asebrkak / ptg[5] 128 l18 i ase break accept / input port
rev. 5.00, 09/03, page 722 of 760 pin pin no. (fp-208c, fp-208e) pin no. (bp-240a) i/o function ckio2/ptg[4] 129 l16 i/o system clock output / input port audata[3]/ ptg[3] 130 l17 i aud data / input port audata[2]/ ptg[2] 131 k18 i aud data / input port audata[1]/ ptg[1] 133 k19 i aud data / input port audata[0]/ ptg[0] 135 j18 i aud data / input port trst /ptf[7]/ pint[15] 136 j19 i test reset / input port / port interrupt request tms/ptf[6]/ pint[14] 137 h16 i test mode switch / input port / port interrupt request tdi/ptf[5]/ pint[13] 138 h17 i test data input / input port / port interrupt request tck/ptf[4]/ pint[12] 139 h18 i test clock / input port / port interrupt request irls [3:0]/ ptf[3:0]/ pint[11:8] 140 to 143 h19, g16, g17, g18 i external interrupt request / input port / port interrupt request audck/pth[6] 151 d16 i aud clock / input port wait 123 m19 i hardware wait request breq 122 n16 i bus request back 121 n17 o bus acknowledge irqout 160 a16 o interrupt / refresh request output resetp 193 c7 i power-on reset input nmi 7 c3 i nonmaskable interrupt request irq[3:0]/ irl[3:0] / pth[3:0] 11 to 8 f2, f1, e4, e3 i external interrupt request / external interrupt source / input port irq4/pth[4] 12 f3 i external interrupt request / input port cts2 /irq5/ scpt[7] 176 a11 i serial port 2 transfer enable / external interrupt request / input port tclk/pth[7] 159 b15 i/o clock i/o (for tmu/rtc) / i/o port extal 156 d18 i external clock / crystal oscillator pin xtal 155 c18 o crystal oscillator pin cap1 146 f17 ? external capacitance pin (for pll1) cap2 149 e16 ? external capacitance pin (for pll2)
rev. 5.00, 09/03, page 723 of 760 pin pin no. (fp-208c, fp-208e) pin no. (bp-240a) i/o function ckio 162 a15 i/o system clock i/o xtal2 4 d1 o crystal oscillator pin (for on-chip rtc) extal2 5 d3 i crystal oscillator pin (for on-chip rtc) cke/ptk[5] 105 t18 i/o ck enable for sdram / i/o port ca 194 b7 i setting hardware standby pin v cc q 21, 35, 47, 59, 71, 85, 97, 111, 163, 183 h4, m1, r1, u3, v8, u15, r19, c17, a10, u12 power supply power supply (3.3 v) v cc ?rtc 3 e2 power supply rtc oscillator power supply (2.0/1.9/1.8/1.7 v) v cc ?pll1 v cc ?pll2 145 150 f16, e17 power supply pll power supply (2.0/1.9/1.8/1.7 v) av cc 205 a4 power supply analog power supply (3.3 v) v ss q 19, 33, 45, 57, 69, 83, 95, 109, 161, 181 h2, m3, r3, t7, u4, w11, w14, t19, c16, c10 power supply power supply (0 v) v cc 29, 81, 134, 154, 175 l3, l4, u11, t11, j17, j16, e18, c19, c12, d12 power supply internal power supply (2.0/1.9/1.8/1.7 v) v ss 27, 79, 132, 152, 153, 173 k3, k4, u10, t10, k17, k16, e19, d17, d19, a12, d13 power supply internal power supply (0 v) v ss ?rtc 6 e1 power supply rtc-oscillator power supply (0 v) v ss ?pll1 v ss ?pll2 147 148 f18 f19 power supply pll power supply (0 v) av ss 198, 208 b6, b4 power supply analog power supply (0 v) note: except in hardware standby mode, power must be supplied constantly to all power supply pins. in hardware standby mode, power must be supplied to vcc-rtc and vss-rtc at least.
rev. 5.00, 09/03, page 724 of 760 a.3 treatment of unused pins ? when rtc is not used ? extal2: pull up (2.0/1.9/1.8/1.7 v) ? xtal2: leave unconnected ? v cc ?rtc: power supply (2.0/1.9/1.8/1.7 v) ? v ss ?rtc: power supply (0 v) ? when pll2 is not used ? cap2: leave unconnected ? v cc ?pll2: power supply (2.0/1.9/1.8/1.7 v) ? v ss ?pll2: power supply (0 v) ? when on-chip crystal oscillator is not used ? xtal: leave unconnected ? when extal pin is not used ? extal: pull up (3.3 v) ? when a/d converter is not used ? an[7:0]: leave unconnected ? av cc : power supply (3.3 v) ? av ss : power supply (0 v) ? when udi is not used ? asemd0: pull up (3.3 v)
rev. 5.00, 09/03, page 725 of 760 a.4 pin states in access to each address space table a.3 pin states (ordinary memory/little endian) 8-bit bus width 16-bit bus width pin byte/word/long- word access byte access (address 2n) byte access (address 2n + 1) word/longword access cs6 to cs2 , cs0 enabled enabled enabled enabled r low low low low rd w high high high high r high high high high rd/ wr w low low low low bs enabled enabled enabled enabled ras3u /pte[2] high high high high ras3l /ptj[0] high high high high casl /ptj[2] high high high high casu /ptj[3] high high high high r high high high high we0 /dqmll w low low high low r high high high high we1 /dqmlu/ we w high high low low r high high high high we2 /dqmul/ iciord /ptk[6] w high high high high r high high high high we3 /dqmuu/ iciowr /ptk[7] w high high high high ce2a /pte[4] high high high high ce2b /pte[5] high high high high cke/ptk[5] disabled disabled disabled disabled wait enabled * 1 enabled * 1 enabled * 1 enabled * 1 iois16 /ptg[7] disabled disabled disabled disabled a25 to a0 address address address address d7 to d0 valid data valid data invalid data valid data d15 to d8 high-z * 2 invalid data valid data valid data d31 to d16 high-z * 2 high-z * 2 high-z * 2 high-z * 2
rev. 5.00, 09/03, page 726 of 760 32-bit bus width pin byte access (address 4n) byte access (address 4n + 1) byte access (address 4n + 2) byte access (address 4n + 3) word access (address 4n) word access (address 4n + 2) longword access cs6 to cs2 , cs0 enabled enabled enabled enabled enabled enabled enabled r low low low low low low low rd w high high high high high high high r high high high high high high high rd/ wr w low low low low low low low bs enabled enabled enabled enabled enabled enabled enabled ras3u /pte[2] high high high high high high high ras3l /ptj[0] high high high high high high high casl /ptj[2] high high high high high high high casu /ptj[3] high high high high high high high r high high high high high high high we0 /dqmll w low high high high low high low r high high high high high high high we1 /dqmlu/ we w high low high high low high low r high high high high high high high we2 /dqmul/ iciord /ptk[6] w high high low high high low low r high high high high high high high we3 /dqmuu/ iciowr /ptk[7] w high high high low high low low ce2a /pte[4] high high high high high high high ce2b /pte[5] high high high high high high high cke/ptk[5] disabled disabled disabled disabled disabled disabled disabled wait enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 iois16 /ptg[7] disabled disabled disabled disabled disabled disabled disabled a25 to a0 address address address address address address address d7 to d0 valid data invalid data invalid data invalid data valid data invalid data valid data d15 to d8 invalid data valid data invalid data invalid data valid data invalid data valid data d23 to d16 invalid data invalid data valid data invalid data invalid data valid data valid data d31 to d24 invalid data invalid data invalid data valid data invalid data valid data valid data notes: 1. disabled when wcr2 register wait setting is 0. 2. unused data pins should be switched to the port function, or pulled up.
rev. 5.00, 09/03, page 727 of 760 table a.4 pin states (ordinary memory/big endian) 8-bit bus width 16-bit bus width pin byte/word/long- word access byte access (address 2n) byte access (address 2n + 1) word/longword access cs6 to cs2 , cs0 enabled enabled enabled enabled r low low low low rd w high high high high r high high high high rd/ wr w low low low low bs enabled enabled enabled enabled ras3u /pte[2] high high high high ras3l /ptj[0] high high high high casl /ptj[2] high high high high casu /ptj[3] high high high high r high high high high we0 /dqmll w low high low low r high high high high we1 /dqmlu/ we w high low high low r high high high high we2 /dqmul/ iciord /ptk[6] w high high high high r high high high high we3 /dqmuu/ iciowr /ptk[7] w high high high high ce2a /pte[4] high high high high ce2b /pte[5] high high high high cke/ptk[5] disabled disabled disabled disabled wait enabled * 1 enabled * 1 enabled * 1 enabled * 1 iois16 /ptg[7] disabled disabled disabled disabled a25 to a0 address address address address d7 to d0 valid data invalid data valid data valid data d15 to d8 high-z * 2 valid data invalid data valid data d31 to d16 high-z * 2 high-z * 2 high-z * 2 high-z * 2
rev. 5.00, 09/03, page 728 of 760 32-bit bus width pin byte access (address 4n) byte access (address 4n + 1) byte access (address 4n + 2) byte access (address 4n + 3) word access (address 4n) word access (address 4n + 2) longword access cs6 to cs2 , cs0 enabled enabled enabled enabled enabled enabled enabled r low low low low low low low rd w high high high high high high high r high high high high high high high rd/ wr w low low low low low low low bs enabled enabled enabled enabled enabled enabled enabled ras3u /pte[2] high high high high high high high ras3l /ptj[0] high high high high high high high casl /ptj[2] high high high high high high high casu /ptj[3] high high high high high high high r high high high high high high high we0 /dqmll w high high high low high low low r high high high high high high high we1 /dqmlu/ we w high high low high high low low r high high high high high high high we2 /dqmul/ iciord /ptk[6] w high low high high low high low r high high high high high high high we3 /dqmuu/ iciowr /ptk[7] w low high high high low high low ce2a /pte[4] high high high high high high high ce2b /pte[5] high high high high high high high cke/ptk[5] disabled disabled disabled disabled disabled disabled disabled wait enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 iois16 /ptg[7] disabled disabled disabled disabled disabled disabled disabled a25 to a0 address address address address address address address d7 to d0 invalid data invalid data invalid data valid data invalid data valid data valid data d15 to d8 invalid data invalid data valid data invalid data invalid data valid data valid data d23 to d16 invalid data valid data invalid data invalid data valid data invalid data valid data d31 to d24 valid data invalid data invalid data invalid data valid data invalid data valid data notes: 1. disabled when wcr2 register wait setting is 0. 2. unused data pins should be switched to the port function, or pulled up.
rev. 5.00, 09/03, page 729 of 760 table a.5 pin states (burst rom/little endian) 8-bit bus width 16-bit bus width pin byte/word/long- word access byte access (address 2n) byte access (address 2n + 1) word/longword access cs6 to cs2 , cs0 enabled enabled enabled enabled r low low low low rd w? ??? r high high high high rd/ wr w? ??? bs enabled enabled enabled enabled ras3u /pte[2] high high high high ras3l /ptj[0] high high high high casl /ptj[2] high high high high casu /ptj[3] high high high high r high high high high we0 /dqmll w? ??? r high high high high we1 /dqmlu/ we w? ??? r high high high high we2 /dqmul/ iciord /ptk[6] w? ??? r high high high high we3 /dqmuu/ iciowr /ptk[7] w? ??? ce2a /pte[4] high high high high ce2b /pte[5] high high high high cke/ptk[5] disabled disabled disabled disabled wait enabled * 1 enabled * 1 enabled * 1 enabled * 1 iois16 /ptg[7] disabled disabled disabled disabled a25 to a0 address address address address d7 to d0 valid data valid data invalid data valid data d15 to d8 high-z * 2 invalid data valid data valid data d31 to d16 high-z * 2 high-z * 2 high-z * 2 high-z * 2
rev. 5.00, 09/03, page 730 of 760 32-bit bus width pin byte access (address 4n) byte access (address 4n + 1) byte access (address 4n + 2) byte access (address 4n + 3) word access (address 4n) word access (address 4n + 2) longword access cs6 to cs2 , cs0 enabled enabled enabled enabled enabled enabled enabled r low low low low low low low rd w??????? r high high high high high high high rd/ wr w??????? bs enabled enabled enabled enabled enabled enabled enabled ras3u /pte[2] high high high high high high high ras3l /ptj[0] high high high high high high high casl /ptj[2] high high high high high high high casu /ptj[3] high high high high high high high r high high high high high high high we0 /dqmll w??????? r high high high high high high high we1 /dqmlu/ we w??????? r high high high high high high high we2 /dqmul/ iciord /ptk[6] w??????? r high high high high high high high we3 /dqmuu/ iciowr /ptk[7] w??????? ce2a /pte[4] high high high high high high high ce2b /pte[5] high high high high high high high cke/ptk[5] disabled disabled disabled disabled disabled disabled disabled wait enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 iois16 /ptg[7] disabled disabled disabled disabled disabled disabled disabled a25 to a0 address address address address address address address d7 to d0 valid data invalid data invalid data invalid data valid data invalid data valid data d15 to d8 invalid data valid data invalid data invalid data valid data invalid data valid data d23 to d16 invalid data invalid data valid data invalid data invalid data valid data valid data d31 to d24 invalid data invalid data invalid data valid data invalid data valid data valid data notes: 1. disabled when wcr2 register wait setting is 0. 2. unused data pins should be switched to the port function, or pulled up.
rev. 5.00, 09/03, page 731 of 760 table a.6 pin states (burst rom/big endian) 8-bit bus width 16-bit bus width pin byte/word/long- word access byte access (address 2n) byte access (address 2n + 1) word/longword access cs6 to cs2 , cs0 enabled enabled enabled enabled r low low low low rd w? ??? r high high high high rd/ wr w? ??? bs enabled enabled enabled enabled ras3u /pte[2] high high high high ras3l /ptj[0] high high high high casl /ptj[2] high high high high casu /ptj[3] high high high high r high high high high we0 /dqmll w? ??? r high high high high we1 /dqmlu/ we w? ??? r high high high high we2 /dqmul/ iciord /ptk[6] w? ??? r high high high high we3 /dqmuu/ iciowr /ptk[7] w? ??? ce2a /pte[4] high high high high ce2b /pte[5] high high high high cke/ptk[5] disabled disabled disabled disabled wait enabled * 1 enabled * 1 enabled * 1 enabled * 1 iois16 /ptg[7] disabled disabled disabled disabled a25 to a0 address address address address d7 to d0 valid data invalid data valid data valid data d15 to d8 high-z * 2 valid data invalid data valid data d31 to d16 high-z * 2 high-z * 2 high-z * 2 high-z * 2
rev. 5.00, 09/03, page 732 of 760 32-bit bus width pin byte access (address 4n) byte access (address 4n + 1) byte access (address 4n + 2) byte access (address 4n + 3) word access (address 4n) word access (address 4n + 2) longword access cs6 to cs2 , cs0 enabled enabled enabled enabled enabled enabled enabled r low low low low low low low rd w??????? r high high high high high high high rd/ wr w??????? bs enabled enabled enabled enabled enabled enabled enabled ras3u /pte[2] high high high high high high high ras3l /ptj[0] high high high high high high high casl /ptj[2] high high high high high high high casu /ptj[3] high high high high high high high r high high high high high high high we0 /dqmll w??????? r high high high high high high high we1 /dqmlu/ we w??????? r high high high high high high high we2 /dqmul/ iciord /ptk[6] w??????? r high high high high high high high we3 /dqmuu/ iciowr /ptk[7] w??????? ce2a /pte[4] high high high high high high high ce2b /pte[5] high high high high high high high cke/ptk[5] disabled disabled disabled disabled disabled disabled disabled wait enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 iois16 /ptg[7] disabled disabled disabled disabled disabled disabled disabled a25 to a0 address address address address address address address d7 to d0 invalid data invalid data invalid data valid data invalid data valid data valid data d15 to d8 invalid data invalid data valid data invalid data invalid data valid data valid data d23 to d16 invalid data valid data invalid data invalid data valid data invalid data valid data d31 to d24 valid data invalid data invalid data invalid data valid data invalid data valid data notes: 1. disabled when wcr2 register wait setting is 0. 2. unused data pins should be switched to the port function, or pulled up.
rev. 5.00, 09/03, page 733 of 760 table a.7 pin states (synchronous dram/little endian) 32-bit bus width pin byte access (address 4n) byte access (address 4n + 1) byte access (address 4n + 2) byte access (address 4n + 3) word access (address 4n) word access (address 4n + 2) longword access cs6 to cs2 , cs0 enabled enabled enabled enabled enabled enabled enabled r high high high high high high high rd w high high high high high high high r high high high high high high high rd/ wr w low low low low low low low bs enabled enabled enabled enabled enabled enabled enabled ras3u /pte[2] high/low * 1 high/low * 1 high/low * 1 high/low * 1 high/low * 1 high/low * 1 high/low * 1 ras3l /ptj[0] low/high * 1 low/high * 1 low/high * 1 low/high * 1 low/high * 1 low/high * 1 low/high * 1 casl /ptj[2] low low low low low low low casu /ptj[3] high high high high high high high r low high high high low high low we0 /dqmll w low high high high low high low r high low high high low high low we1 /dqmlu/ we w high low high high low high low r high high low high high low low we2 /dqmul/ iciord /ptk[6] w high high low high high low low r high high high low high low low we3 /dqmuu/ iciowr /ptk[7] w high high high low high low low ce2a /pte[4] high high high high high high high ce2b /pte[5] high high high high high high high cke/ptk[5] high * 2 high * 2 high * 2 high * 2 high * 2 high * 2 high * 2 wait disabled disabled disabled disabled disabled disabled disabled iois16 /ptg[7] disabled disabled disabled disabled disabled disabled disabled a25 to a0 address command address command address command address command address command address command address command d7 to d0 valid data invalid data invalid data invalid data valid data invalid data valid data d15 to d8 invalid data valid data invalid data invalid data valid data invalid data valid data d23 to d16 invalid data invalid data valid data invalid data invalid data valid data valid data d31 to d24 invalid data invalid data invalid data valid data invalid data valid data valid data notes: 1. lower 32-mb access/ upper 32-mb access/64-mb access 2. normally high. low in self-refreshing.
rev. 5.00, 09/03, page 734 of 760 table a.8 pin states (synchronous dram/big endian) 32-bit bus width pin byte access (address 4n) byte access (address 4n + 1) byte access (address 4n + 2) byte access (address 4n + 3) word access (address 4n) word access (address 4n + 2) longword access cs6 to cs2 , cs0 enabled enabled enabled enabled enabled enabled enabled r high high high high high high high rd w high high high high high high high r high high high high high high high rd/ wr w low low low low low low low bs enabled enabled enabled enabled enabled enabled enabled ras3u /pte[2] high/low * 1 high/low * 1 high/low * 1 high/low * 1 high/low * 1 high/low * 1 high/low * 1 ras3l /ptj[0] low/high * 1 low/high * 1 low/high * 1 low/high * 1 low/high * 1 low/high * 1 low/high * 1 casl /ptj[2] low low low low low low low casu /ptj[3] high high high high high high high r high high high low high low low we0 /dqmll w high high high low high low low r high high low high high low low we1 /dqmlu/ we w high high low high high low low r high low high high low high low we2 /dqmul/ iciord /ptk[6] w high low high high low high low r low high high high low high low we3 /dqmuu/ iciowr /ptk[7] w low high high high low high low ce2a /pte[4] high high high high high high high ce2b /pte[5] high high high high high high high cke/ptk[5] high * 2 high * 2 high * 2 high * 2 high * 2 high * 2 high * 2 wait disabled disabled disabled disabled disabled disabled disabled iois16 /ptg[7] disabled disabled disabled disabled disabled disabled disabled a25 to a0 address command address command address command address command address command address command address command d7 to d0 invalid data invalid data invalid data valid data invalid data valid data valid data d15 to d8 invalid data invalid data valid data invalid data invalid data valid data valid data d23 to d16 invalid data valid data invalid data invalid data valid data invalid data valid data d31 to d24 valid data invalid data invalid data invalid data valid data invalid data valid data notes: 1. lower 32-mb access/ upper 32-mb access/64-mb access 2. normally high. low in self-refreshing.
rev. 5.00, 09/03, page 735 of 760 table a.9 pin states (pcmcia/little endian) pcmcia memory interface (area 5) pcmcia/io interface (area 5) 8-bit bus width 16-bit bus width 8-bit bus width 16-bit bus width pin byte/ word/ long- word access byte access (ad- dress 2n) byte access (ad- dress 2n + 1) word/ long- word access byte/ word/ long- word ac cess byte access (ad- dress 2n) byte access (ad- dress 2n + 1) word/ long- word access cs6 to cs2 , cs0 enabled enabled high enabled enabled enabled high enabled r low low low low high high high high rd w high high high high high high high high r high high high high high high high high rd/ wr w low low low low low low low low bs enabled enabled enabled enabled enabled enabled enabled enabled ras3u /pte[2] high high high high high high high high ras3l /ptj[0] high high high high high high high high casl /ptj[2] high high high high high high high high casu /ptj[3] high high high high high high high high r high high high high high high high high we0 /dqmll w high high high high high high high high r high high high high high high high high we1 /dqmlu/ we w low low low low high high high high r high high high high low low low low we2 /dqmul/ iciord /ptk[6] w high high high high high high high high r high high high high high high high high we3 /dqmuu/ iciowr /ptk[7] w high high high high low low low low ce2a /pte[4] high high low low high high low low ce2b /pte[5] high high high high high high high high cke/ptk[5] disabled disabled disabled disabled disabled disabled disabled disabled wait enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 iois16 /ptg[7] disabled disabled disabled disabled disabled disabled enabled enabled a25 to a0 address address address address address address address address d7 to d0 valid data valid data invalid data valid data valid data valid data invalid data valid data d15 to d8 high-z * 2 invalid data valid data valid data high-z * 2 invalid data valid data valid data d31 to d16 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2
rev. 5.00, 09/03, page 736 of 760 pcmcia memory interface (area 6) pcmcia/io interface (area 6) 8-bit bus width 16-bit bus width 8-bit bus width 16-bit bus width pin byte/ word/ long- word access byte access (ad- dress 2n) byte access (ad- dress 2n + 1) word/ long- word access byte/ word/ long- word access byte access (ad- dress 2n) byte access (ad- dress 2n+1) word/ long- word access cs6 to cs2 , cs0 enabled enabled high enabled enabled enabled high enabled r low low low low high high high high rd w high high high high high high high high r high high high high high high high high rd/ wr w low low low low low low low low bs enabled enabled enabled enabled enabled enabled enabled enabled ras3u /pte[2] high high high high high high high high ras3l /ptj[0] high high high high high high high high casl /ptj[2] high high high high high high high high casu /ptj[3] high high high high high high high high r high high high high high high high high we0 /dqmll w high high high high high high high high r high high high high high high high high we1 /dqmlu/ we w low low low low high high high high r high high high high low low low low we2 /dqmul/ iciord /ptk[6] w high high high high high high high high r high high high high high high high high we3 /dqmuu/ iciowr /ptk[7] w high high high high low low low low ce2a /pte[4] high high high high high high high high ce2b /pte[5] high high low low high high low low cke/ptk[5] disabled disabled disabled disabled disabled disabled disabled disabled wait enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 iois16 /ptg[7] disabled disabled disabled disabled disabled disabled enabled enabled a25 to a0 address address address address address address address address d7 to d0 valid data valid data invalid data valid data valid data valid data invalid data valid data d15 to d8 high-z * 2 invalid data valid data valid data high-z * 2 invalid data valid data valid data d31 to d16 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2 notes: 1. disabled when wcr2 register wait setting is 0. 2. unused data pins should be switched to the port function, or pulled up.
rev. 5.00, 09/03, page 737 of 760 table a.10 pin states (pcmcia/big endian) pcmcia memory interface (area 5) pcmcia i/o interface (area 5) 8-bit bus width 16-bit bus width 8-bit bus width 16-bit bus width pin byte/ word/ long- word access byte access (ad- dress 2n) byte access (ad- dress 2n + 1) word/ long- word access byte/ word/ long- word access byte access (ad- dress 2n) byte access (ad- dress 2n + 1) word/ long- word access cs6 to cs2 , cs0 enabled enabled high enabled enabled enabled high enabled r low low low low high high high high rd w high high high high high high high high r high high high high high high high high rd/ wr w low low low low low low low low bs enabled enabled enabled enabled enabled enabled enabled enabled ras3u /pte[2] high high high high high high high high ras3l /ptj[0] high high high high high high high high casl /ptj[2] high high high high high high high high casu /ptj[3] high high high high high high high high r high high high high high high high high we0 /dqmll w high high high high high high high high r high high high high high high high high we1 /dqmlu/ we w low low low low high high high high r high high high high low low low low we2 /dqmul/ iciord /ptk[6] w high high high high high high high high r high high high high high high high high we3 /dqmuu/ iciowr /ptk[7] w high high high high low low low low ce2a /pte[4] high high low low high high low low ce2b /pte[5] high high high high high high high high cke/ptk[5] disabled disabled disabled disabled disabled disabled disabled disabled wait enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 iois16 /ptg[7] disabled disabled disabled disabled disabled disabled disabled disabled a25 to a0 address address address address address address address address d7 to d0 valid data invalid data valid data valid data valid data invalid data valid data valid data d15 to d8 high-z * 2 valid data invalid data valid data high-z * 2 valid data invalid data valid data d31 to d16 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2
rev. 5.00, 09/03, page 738 of 760 pcmcia memory interface (area 6) pcmcia/io interface (area 6) 8-bit bus width 16-bit bus width 8-bit bus width 16-bit bus width pin byte/ word/ long- word access byte access (ad- dress 2n) byte access (ad- dress 2n + 1) word/ long- word access byte/ word/ long- word access byte access (ad- dress 2n) byte access (ad- dress 2n+1) word/ long- word access cs6 to cs2 , cs0 enabled enabled high enabled enabled enabled high enabled r low low low low high high high high rd w high high high high high high high high r high high high high high high high high rd/ wr w low low low low low low low low bs enabled enabled enabled enabled enabled enabled enabled enabled ras3u /pte[2] high high high high high high high high ras3l /ptj[0] high high high high high high high high casl /ptj[2] high high high high high high high high casu /ptj[3] high high high high high high high high r high high high high high high high high we0 /dqmll w high high high high high high high high r high high high high high high high high we1 /dqmlu/ we w low low low low high high high high r high high high high low low low low we2 /dqmul/ iciord /ptk[6] w high high high high high high high high r high high high high high high high high we3 /dqmuu/ iciowr /ptk[7] w high high high high low low low low ce2a /pte[4] high high high high high high high high ce2b /pte[5] high high low low high high low low cke/ptk[5] disabled disabled disabled disabled disabled disabled disabled disabled wait enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 iois16 /ptg[7] disabled disabled disabled disabled disabled disabled enabled enabled a25 to a0 address address address address address address address address d7 to d0 valid data invalid data valid data valid data valid data invalid data valid data valid data d15 to d8 high-z * 2 valid data invalid data valid data high-z * 2 valid data invalid data valid data d31 to d16 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2 notes: 1. disabled when wcr2 register wait setting is 0. 2. unused data pins should be switched to the port function, or pulled up.
rev. 5.00, 09/03, page 739 of 760 appendix b memory-mapped control registers b.1 register address map table b.1 memory-mapped control registers control register module * 1 bus * 2 address * 4 size (bits) access size (bits) 3. pteh ccn l fffffff0 32 32 ptel ccn l fffffff4 32 32 ttb ccn l fffffff8 32 32 tea ccn l fffffffc 32 32 mmucr ccn l ffffffe0 32 32 basra ccn l ffffffe4 32 32 basrb ccn l ffffffe8 32 32 ccr ccn l ffffffec 32 32 ccr2 ccn i 40000b0 32 32 tra ccn l ffffffd0 32 32 expevt ccn l ffffffd4 32 32 intevt ccn l ffffffd8 32 32 bara ubc l ffffffb0 32 32 bamra ubc l ffffffb4 32 32 bbra ubc l ffffffb8 16 16 barb ubc l ffffffa0 32 32 bamrb ubc l ffffffa4 32 32 bbrb ubc l ffffffa8 16 16 bdrb ubc l ffffff90 32 32 bdmrb ubc l ffffff94 32 32 brcr ubc l ffffff98 16 16 betr ubc l ffffff9c 16 16 brsr ubc l ffffffac 32 32 brdr ubc l ffffffbc 32 32 frqcr cpg i ffffff80 16 16 stbcr cpg i ffffff82 8 8 stbcr2 cpg i ffffff88 8 8 wtcnt cpg i ffffff84 8 16
rev. 5.00, 09/03, page 740 of 760 control register module * 1 bus * 2 address * 4 size (bits) access size (bits) * 3 wtcsr cpg i ffffff86 8 16 bcr1 bsc i ffffff60 16 16 bcr2 bsc i ffffff62 16 16 wcr1 bsc i ffffff64 16 16 wcr2 bsc i ffffff66 16 16 mcr bsc i ffffff68 16 16 pcr bsc i ffffff6c 16 16 rtcsr bsc i ffffff6e 16 16 rtcnt bsc i ffffff70 16 16 rtcor bsc i ffffff72 16 16 rfcr bsc i ffffff74 16 16 sdmr bsc i ffffd000? ffffefff ?8 mcscr0 bsc i ffffff50 16 16 mcscr1 bsc i ffffff52 16 16 mcscr2 bsc i ffffff54 16 16 mcscr3 bsc i ffffff56 16 16 mcscr4 bsc i ffffff58 16 16 mcscr5 bsc i ffffff5a 16 16 mcscr6 bsc i ffffff5c 16 16 mcscr7 bsc i ffffff5e 16 16 r64cnt rtc p fffffec0 8 8 rseccnt rtc p fffffec2 8 8 rmincnt rtc p fffffec4 8 8 rhrcnt rtc p fffffec6 8 8 rwkcnt rtc p fffffec8 8 8 rdaycnt rtc p fffffeca 8 8 rmoncnt rtc p fffffecc 8 8 ryrcnt rtc p fffffece 8 8 rsecar rtc p fffffed0 8 8 rminar rtc p fffffed2 8 8 rhrar rtc p fffffed4 8 8
rev. 5.00, 09/03, page 741 of 760 control register module * 1 bus * 2 address * 4 size (bits) access size (bits) * 3 rwkar rtc p fffffed6 8 8 rdayar rtc p fffffed8 8 8 rmonar rtc p fffffeda 8 8 rcr1 rtc p fffffedc 8 8 rcr2 rtc p fffffede 8 8 icr0 intc i fffffee0 16 16 ipra intc i fffffee2 16 16 iprb intc i fffffee4 16 16 tocr tmu p fffffe90 8 8 tstr tmu p fffffe92 8 8 tcor0 tmu p fffffe94 32 32 tcnt0 tmu p fffffe98 32 32 tcr0 tmu p fffffe9c 16 16 tcor1 tmu p fffffea0 32 32 tcnt1 tmu p fffffea4 32 32 tcr1 tmu p fffffea8 16 16 tcor2 tmu p fffffeac 32 32 tcnt2 tmu p fffffeb0 32 32 tcr2 tmu p fffffeb4 16 16 tcpr2 tmu p fffffeb8 32 32 scsmr sci p fffffe80 8 8 scbrr sci p fffffe82 8 8 scscr sci p fffffe84 8 8 sctdr sci p fffffe86 8 8 scssr sci p fffffe88 8 8 scrdr sci p fffffe8a 8 8 scscmr sci p fffffe8c 8 8 intevt2 intc i 4000000 32 32 irr0 intc i 4000004 16 8 irr1 intc i 4000006 16 8 irr2 intc i 4000008 16 8
rev. 5.00, 09/03, page 742 of 760 control register module * 1 bus * 2 address * 4 size (bits) access size (bits) * 3 icr1 intc i 4000010 16 16 icr2 intc i 4000012 16 16 pinter intc i 4000014 16 16 iprc intc i 4000016 16 16 iprd intc i 4000018 16 16 ipre intc i 400001a 16 16 sar0 dmac p 4000020 32 16,32 dar0 dmac p 4000024 32 16,32 dmatcr0 dmac p 4000028 32 16,32 chcr0 dmac p 400002c 32 8,16,32 sar1 dmac p 4000030 32 16,32 dar1 dmac p 4000034 32 16,32 dmatcr1 dmac p 4000038 32 16,32 chcr1 dmac p 400003c 32 8,16,32 sar2 dmac p 4000040 32 16,32 dar2 dmac p 4000044 32 16,32 dmatcr2 dmac p 4000048 32 16,32 chcr2 dmac p 400004c 32 8,16,32 sar3 dmac p 4000050 32 16,32 dar3 dmac p 4000054 32 16,32 dmatcr3 dmac p 4000058 32 16,32 chcr3 dmac p 400005c 32 8,16,32 dmaor dmac p 4000060 16 8,16 cmstr cmt p 4000070 16 8,16,32 cmcsr cmt p 4000072 16 8,16,32 cmcnt cmt p 4000074 16 8,16,32 cmcor cmt p 4000076 16 8,16,32 addrah a/d p 4000080 8 8,16,32 * 5 * 6 addral a/d p 4000082 8 8,16 * 5 addrbh a/d p 4000084 8 8,16,32 * 5 * 6 addrbl a/d p 4000086 8 8,16 * 5 addrch a/d p 4000088 8 8,16,32 * 5 * 6
rev. 5.00, 09/03, page 743 of 760 control register module * 1 bus * 2 address * 4 size (bits) access size (bits) * 3 addrcl a/d p 400008a 8 8,16 * 5 addrdh a/d p 400008c 8 8,16,32 * 5 * 6 addrdl a/d p 400008e 8 8,16 * 5 adcsr a/d p 4000090 8 8,16,32 * 5 * 6 adcr a/d p 4000092 8 8,16 dadr0 d/a p 40000a0 8 8,16,32 * 5 * 6 dadr1 d/a p 40000a2 8 8,16 * 5 dacr d/a p 40000a4 8 8,16,32 pacr port p 4000100 16 16 pbcr port p 4000102 16 16 pccr port p 4000104 16 16 pdcr port p 4000106 16 16 pecr port p 4000108 16 16 pfcr port p 400010a 16 16 pgcr port p 400010c 16 16 phcr port p 400010e 16 16 pjcr port p 4000110 16 16 pkcr port p 4000112 16 16 plcr port p 4000114 16 16 scpcr port p 4000116 16 16 padr port p 4000120 8 8 pbdr port p 4000122 8 8 pcdr port p 4000124 8 8 pddr port p 4000126 8 8 pedr port p 4000128 8 8 pfdr port p 400012a 8 8 pgdr port p 400012c 8 8 phdr port p 400012e 8 8 pjdr port p 4000130 8 8 pkdr port p 4000132 8 8 pldr port p 4000134 8 8 scpdr port p 4000136 8 8
rev. 5.00, 09/03, page 744 of 760 control register module * 1 bus * 2 address * 4 size (bits) access size (bits) * 3 scsmr1 irda p 4000140 8 8 scbrr1 irda p 4000142 8 8 scscr1 irda p 4000144 8 8 scftdr1 irda p 4000146 8 8 scssr1 irda p 4000148 16 16 scfrdr1 irda p 400014a 8 8 scfcr1 irda p 400014c 8 8 scfdr1 irda p 400014e 16 16 scsmr2 scif p 4000150 8 8 scbrr2 scif p 4000152 8 8 scscr2 scif p 4000154 8 8 scftdr2 scif p 4000156 8 8 scssr2 scif p 4000158 16 16 scfrdr2 scif p 400015a 8 8 scfcr2 scif p 400015c 8 8 scfdr2 scif p 400015e 16 16 sdir udi i 4000200 16 16 notes: 1. modules: ccn: cache controller ubc: user break controller cpg: clock pulse generator bsc: bus state controller rtc: realtime clock intc: interrupt controller tmu: timer unit sci: serial communication interface 2. internal buses: l: cpu, ccn, cache, tlb connected i: bsc, cache, dmac, intc, cpg, and udi connected p: bsc and peripheral modules (rtc, tmu, sci, scif, irda, a/d, d/a, dmac, port, cmt) connected 3. the access size shown is for control register access (read/write). an incorrect result will be obtained if a different size from that shown is used for access. 4. to exclude area 1 control registers from address translation by the mmu, set the first 3 bits of the logical address to 101, to locate the registers in the p2 space. 5. with 16-bit access, it is not possible to read data in two registers simultaneously. 6. with 32-bit access, it is possible to read data in the register at [accessed address + 2] simultaneously.
rev. 5.00, 09/03, page 745 of 760 b.2 register bits table b.2 register bits register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module ???? sdmr bsc scsmr c/a chr pe o/e stop mp cks1 cks0 sci scbrr sci scscr tie rie te re mpie teie cke1 cke0 sci sctdr sci scssr tdre rdrf orer fer per tend mpb mpbt sci scrdr sci scscmr ? ? ? ? sdir sinv ? smif sci tocr ???????tcoetmu tstr ? ? ? ? ? str2 str1 str0 tmu tcor0 tmu tcnt0 tmu ???????unf tcr0 ? ? unie ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tmu tcor1 tmu tcnt1 tmu
rev. 5.00, 09/03, page 746 of 760 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module ???????unf tcr1 ? ? unie ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tmu tcor2 tmu tcnt2 tmu ??????icpfunf tcr2 icpe1 icpe0 unie ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tmu tcpr2 tmu r64cnt ? 1 hz 2 hz 4 hz 8 hz 16 hz 32 hz 64 hz rtc rseccnt ? 10 sec 1 sec rtc rmincnt ? 10 min 1 min rtc rhrcnt ? ? 10 hours 1 hour rtc rwkcnt ? ? ? ? ? day of week rtc rdaycnt ? ? 10 days 1 day rtc rmoncnt ? ? ? 10 months 1 month rtc ryrcnt 10 years 1 year rtc rsecar enb 10 sec 1 sec rtc rminar enb 10 min 1 min rtc rwkar enb ? ? ? ? day of week rtc rhrar enb ? 10 hours 1 hour rtc rdayar enb ? 10 days 1 day rtc rmonar enb ? ? 10 months 1 month rtc
rev. 5.00, 09/03, page 747 of 760 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module rcr1 cf ? ? cie aie ? ? af rtc rcr2 pef pes2 pes1 pes0 rtcen adj reset start rtc nml??????nmie icr0 ???????? intc tmu0 tmu1 ipra tmu2 rtc intc wdt ref iprb sci ???? intc pula puld hizmem hizcnt endian a0bst1 a0bst0 a5bst1 bcr1 a5bst0 a6bst1 a6bst0 dramtp2 dramtp1 dramtp0 a5pcm a6pcm bsc ? ? a6sz1 a6sz0 a5sz1 a5sz0 a4sz1 a4sz0 bcr2 a3sz1 a3sz0 a2sz1 a2sz0 ? ? ? ? bsc waitsel ? a6iw1 a6iw0 a5iw1 a5iw0 a4iw1 a4iw0 wcr1 a3iw1 a3iw0 a2iw1 a2iw0 ? ? a0iw1 a0iw0 bsc a6w2 a6w1 a6w0 a5w2 a5w1 a5w0 a4w2 a4w1 wcr2 a4w0 a3w1 a3w0 a2w1 a2w0 a0w2 a0w1 a0w0 bsc tpc1 tpc0 rcd1 rcd0 trwl1 trwl0 tras1 tras0 mcr rasd amx3 amx2 amx1 amx0 rfsh rmode ? bsc a6w3 a5w3 ? ? a5ted2 a6ted2 a5teh2 a6teh2 pcr a5ted1 a5ted0 a6ted1 a6ted0 a5teh1 a5teh0 a6teh1 a6teh0 bsc ???????? rtcsr cmf cmie cks2 cks1 cks0 ovf ovie lmts bsc ???????? rtcnt bsc ???????? rtcor bsc
rev. 5.00, 09/03, page 748 of 760 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module ???????? rfcr bsc stc2 ifc2 pfc2 ? ? ? slpfrq ckoen frqcr pllen pstby stc1 stc0 ifc1 ifc0 pfc1 pfc0 cpg stbcr stby ? ? stbxtl ? mstp2 mstp1 mstp0 cpg stbcr2 mstp9 mdchg mstp8 mstp7 mstp6 mstp5 mstp4 mstp3 cpg wtcnt cpg wtcsr tme wt/it rsts wovf iovf cks2 cks1 cks0 cpg bdrb ubc bdmrb ubc ???????? ? ? basma basmb ? ? ? ? scmfca scmfcb scmfda scmfdb pcte pcba ? ? brcr dbeb pcbb ? ? seq ? ? etbe ubc barb ubc bamrb ? ? ? ? ? basm bam bam ubc ???????? bbrb cdb1 cdb0 idb1 idb0 rwb1 rwb0 szb1 szb0 ubc bara ubc
rev. 5.00, 09/03, page 749 of 760 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module bamra ubc ???????? bbra cda1 cda0 ida1 ida0 rwa1 rwa0 sza1 sza0 ubc ???? betr ubc svf pid2 pid1 pid0 bsa27 bsa26 bsa25 bsa24 bsa23 bsa22 bsa21 bsa20 bsa19 bsa18 bsa17 bsa16 bsa15 bsa14 bsa13 bsa12 bsa11 bsa10 bsa9 bsa8 brsr bsa7 bsa6 bsa5 bsa4 bsa3 bsa2 bsa1 bsa0 ubc dvf ? ? ? bda27 bda26 bda25 bda24 bda23 bda22 bda21 bda20 bda19 bda18 bda17 bda16 bda15 bda14 bda13 bda12 bda11 bda10 bda9 bda8 brdr bda7 bda6 bda5 bda4 bda3 bda2 bda1 bda0 ubc ???????? ???????? ?????? tra ?? ccn ???????? ???????? ???? expevt ccn ???????? ???????? ???? intevt ccn ???????? ???????? ???????sv mmucr ? ? rc rc ? tf ix at ccn
rev. 5.00, 09/03, page 750 of 760 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module basra ubc basrb ubc ?????? ? ? ?????? ? ? ?????? ? ? ccr ? ? 0 0 cf cb wt ce ccn w3load w3lock cdr2 w2load w2lock ccn ?? pteh ccn ?v ptel ?prprsz c d sh ? ccn ttb ccn tea ccn intevt2 intc
rev. 5.00, 09/03, page 751 of 760 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module irr0 pint0r pint1r irq5r irq4r irq3r irq2r irq1r irq0r intc irr1 txi1r bri1r rxi1r eri1r dei3r dei2r dei1r dei0r intc irr2 ? ? ? adir txi2r bri2r rxi2r eri2r intc mai irqlvl blmsk ? irq51s irq50s irq41s irq40s icr1 irq31s irq30s irq21s irq20s irq11s irq10s irq01s irq00s intc pint15s pint14s pint13s pint12s pint11s pint10s pint9s pint8s icr2 pint7s pint6s pint5s pint4s pint3s pint2s pint1s pint0s intc pint15e pint14e pint13e pint12e pint11e pint10e pint9e pint8e pinter pint7e pint6e pint5e pint4e pint3e pint2e pint1e pint0e intc irq3 level irq2 level iprc irq1 level irq0 level intc pint0 to 7 level pint8 to 15 level iprd irq5 level irq4 level intc dmac level irda level ipre scif level a/d level intc sar0 dmac dar0 dmac ???????? dmatcr0 dmac
rev. 5.00, 09/03, page 752 of 760 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module ???????? ?????rlamal dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 chcr0 ?dstmts1ts0ietede dmac sar1 dmac dar1 dmac ???????? dmatcr1 dmac ???????? ?????rlamal dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 dmac chcr1 ?dstmts1ts0ietede sar2 dmac dar2 dmac ???????? dmatcr2 dmac
rev. 5.00, 09/03, page 753 of 760 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module ???????? ????ro??? dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 chcr2 ? ? tm ts1 ts0 ie te de dmac sar3 dmac dar3 dmac ???????? dmatcr3 dmac ???????? ???di???? dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 chcr3 ? ? tm ts1 ts0 ie te de dmac ??????pr1pr0 dmaor ? ? ? ? ? ae nmif dme dmac ???????? cmstr ???????str cmt ???????? cmcsr cmf ? ? ? ? ? cks1 cks0 cmt cmcnt cmt cmcor cmt addrah ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/dc addral ad1 ad0 ? ? ? ? ? ? a/dc
rev. 5.00, 09/03, page 754 of 760 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module addrbh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/dc addrbl ad1 ad0 ? ? ? ? ? ? a/dc addrch ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/dc addrcl ad1 ad0 ? ? ? ? ? ? a/dc addrdh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/dc addrdl ad1 ad0 ? ? ? ? ? ? a/dc adcsr adf ade adst mult1 cks ch2 ch1 ch0 a/dc adcr trge1 trge2 scn resvd1 resvd2 ? ? ? a/dc dadr0 d/ac dadr1 d/ac dacr daoe1 daoe0 dae ? ? ? ? ? d/ac pa7m d1 pa7m d0 pa6m d1 pa6m d0 pa5m d1 pa5m d0 pa4m d1 pa4m d0 pacr pa3m d1 pa3m d0 pa2m d1 pa2m d0 pa1m d1 pa1m d0 pa0m d1 pa0m d0 port pb7m d1 pb7m d0 pb6m d1 pb6m d0 pb5m d1 pb5m d0 pb4m d1 pb4m d0 pbcr pb3m d1 pb3m d0 pb2m d1 pb2m d0 pb1m d1 pb1m d0 pb0m d1 pb0m d0 port pc7m d1 pc7m d0 pc6m d1 pc6m d0 pc5m d1 pc5m d0 pc4m d1 pc4m d0 pcdr pc3m d1 pc3m d0 pc2m d1 pc2m d0 pc1m d1 pc1m d0 pc0m d1 pc0m d0 port pd7m d1 pd7m d0 pd6m d1 pd6m d0 pd5m d1 pd5m d0 pd4m d1 pd4m d0 pdcr pd3m d1 pd3m d0 pd2m d1 pd2m d0 pd1m d1 pd1m d0 pd0m d1 pd0m d0 port pe7m d1 pe7m d0 pe6m d1 pe6m d0 pe5m d1 pe5m d0 pe4m d1 pe4m d0 pecr pe3m d1 pe3m d0 pe2m d1 pe2m d0 pe1m d1 pe1m d0 pe0m d1 pe0m d0 port pf7m d1 pf7m d0 pf6m d1 pf6m d0 pf5m d1 pf5m d0 pf4m d1 pf4m d0 pfcr pf3m d1 pf3m d0 pf2m d1 pf2m d0 pf1m d1 pf1m d0 pf0m d1 pf0m d0 port
rev. 5.00, 09/03, page 755 of 760 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module pg7m d1 pg7m d0 pg6m d1 pg6m d0 pg5m d1 pg5m d0 pg4m d1 pg4m d0 pgcr pg3m d1 pg3m d0 pg2m d1 pg2m d0 pg1m d1 pg1m d0 pg0m d1 pg0m d0 port ph7m d1 ph7m d0 ph6m d1 ph6m d0 ph5m d1 ph5m d0 ph4m d1 ph4m d0 phcr ph3m d1 ph3m d0 ph2m d1 ph2m d0 ph1m d1 ph1m d0 ph0m d1 ph0m d0 port pj7m d1 pj7m d0 pj6m d1 pj6m d0 pj5m d1 pj5m d0 pj4m d1 pj4m d0 pjcr pj3m d1 pj3m d0 pj2m d1 pj2m d0 pj1m d1 pj1m d0 pj0m d1 pj0m d0 port pk7m d1 pk7m d0 pk6m d1 pk6m d0 pk5m d1 pk5m d0 pk4m d1 pk4m d0 pkcr pk3m d1 pk3m d0 pk2m d1 pk2m d0 pk1m d1 pk1m d0 pk0m d1 pk0m d0 port pl7m d1 pl7m d0 pl6m d1 pl6m d0 pl5m d1 pl5m d0 pl4m d1 pl4m d0 plcr pl3m d1 pl3m d0 pl2m d1 pl2m d0 pl1m d1 pl1m d0 pl0m d1 pl0m d0 port scp7m d1 scp7m d0 scp6m d1 scp6m d0 scp5m d1 scp5m d0 scp4m d1 scp4m d0 scpcr scp3m d1 scp3m d0 scp2m d1 scp2m d0 scp1m d1 scp1m d0 scp0m d1 scp0m d0 port padr pa7dt pa6dt pa5dt pa4dt pa3dt pa2dt pa1dt pa0dt port pbdr pb7dt pb6dt pb5dt pb4dt pb3dt pb2dt pb1dt pb0dt port pcdr pc7dt pc6dt pc5dt pc4dt pc3dt pc2dt pc1dt pc0dt port pddr pd7dt pd6dt pd5dt pd4dt pd3dt pd2dt pd1dt pd0dt port pedr pe7dt pe6dt pe5dt pe4dt pe3dt pe2dt pe1dt pe0dt port pfdr pf7dt pf6dt pf5dt pf4dt pf3dt pf2dt pf1dt pf0dt port pgdr pg7dt pg6dt pg5dt pg4dt pg3dt pg2dt pg1dt pg0dt port phdr ph7dt ph6dt ph5dt ph4dt ph3dt ph2dt ph1dt ph0dt port pjdr pj7dt pj6dt pj5dt pj4dt pj3dt pj2dt pj1dt pj0dt port pkdr pk7dt pk6dt pk5dt pk4dt pk3dt pk2dt pk1dt pk0dt port pldr pl7dt pl6dt pl5dt pl4dt pl3dt pl2dt pl1dt pl0dt port scpdr scp7dt scp6dt scp5dt scp4dt scp3dt scp2dt scp1dt scp0dt port
rev. 5.00, 09/03, page 756 of 760 register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 module ti3 ti2 ti1 ti0 ? ? ? ? sdir ???????? udi scsmr1 irm0d ick3 ick2 ick1 ick0 psel cks1 cks0 irda scbrr1 irda scscr1 tie rie te re ? ? cke1 cke0 irda scftdr1 irda per3 per2 per1 per0 fer3 fer2 fer1 fer0 scssr1 er tend tdfe brk fer per rdf dr irda scfrdr1 irda scfcr1 rtrg1 rtrg0 ttrg1 ttrg0 mce tfrst rfrst loop irda ? ? ?t4t3t2t1t0 scfdr1 ? ? ? r4r3r2r1r0 irda scsmr2 ? chr pe o/e stop ? cks1 cks0 scif scbrr2 scif scscr2 tie rie te re ? ? cke1 cke0 scif scftdr2 scif per3 per2 per1 per0 fer3 fer2 fer1 fer0 scssr2 er tend tdfe brk fer per rdf dr scif scfrdr2 scif scfcr2 rtrg1 rtrg0 ttrg1 ttrg0 mce tfrst rfrst loop scif ? ? ?t4t3t2t1t0 scfdr2 ? ? ? r4r3r2r1r0 scif legend mmu: memory management unit ubc: user break controller cpg: clock pulse generator bsc: bus state controller rtc: realtime clock intc: interrupt controller tmu: timer unit sc1: serial communication interface controller irda: serial communication interface with irda scif: serial communication interface with fifo ccn: cache controller dmac: direct memory access controller adc: analog to digital converter dac: digital to analog converter port: port controller udi: user debugging interface
rev. 5.00, 09/03, page 757 of 760 appendix c product lineup table c.1 sh7709s models power supply voltage abbr. i/o internal operating frequency model marking package 2.00.15 v 200 mhz hd6417709shf200b 208-pin plastic hqfp (fp-208e) hd6417709sf167b 208-pin plastic lqfp (fp-208c) 1.90.15 v 167 mhz HD6417709SBP167B 240-pin csp (bp-240a) hd6417709sf133b 208-pin plastic lqfp (fp-208c) 1.8+0.25 v 1.8?0.15 v 133 mhz hd6417709sbp133b 240-pin csp (bp-240a) hd6417709sf100b 208-pin plastic lqfp (fp-208c) sh7709s 3.30.3 v 1.7+0.25 v 1.7?0.15 v 100 mhz hd6417709sbp100b 240-pin csp (bp-240a)
rev. 5.00, 09/03, page 758 of 760 appendix d package dimensions figures d.1 to d.3 show the sh7709s package dimensions. package code jedec jeita mass (reference value) fp-208c ? conforms 2.7 g p dimension including the plating thickness base material dimension 30.0 0.2 30.0 0.2 0.5 1.70 max 0 ? 8 p 0.17 0.05 156 105 104 52 1 157 208 53 p 0.22 0.05 0.08 m 0.08 1.40 0.5 0.1 1.0 28 0.10 0.05 1.25 0.20 0.04 0.15 0.04 unit: mm figure d.1 package dimensions (fp-208c)
rev. 5.00, 09/03, page 759 of 760 package code jedec jeita mass (reference value) fp-208e ? conforms 5.3 g p dimension including the plating thickness base material dimension 30.6 0.2 30.6 0.2 0.5 3.56 max 0 ? 8 p 0.17 0.05 156 105 104 52 1 157 208 53 p 0.22 0.05 0.10 m 0.10 3.20 0.5 0.1 1.3 28 0.15 +0.10 ? 0.15 1.25 0.20 0.04 0.15 0.04 unit: mm figure d.2 package dimensions (fp-208e)
rev. 5.00, 09/03, page 760 of 760 0.65 0.65 13.00 13.00 0.15 4 0.2 c c 0.10 c 0.65 0.33 0.05 1.40max b a d c f e h g k j m l p n t r v u w 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 0.20 c a 0.20 c b b c f 0.08 ab 240 f 0.40 0.05 m 0.65 a unit: mm package code jedec jeita mass (reference value) bp-240a ? ? 0.4 g figure d.3 package dimensions (bp-240a)
sh7709s group hardware manual publication date: 1st edition, september 2001 rev.5.00, september 18, 2003 published by: sales strategic planning div. renesas technology corp. edited by: technical documentation & information department renesas kodaira semiconductor co., ltd. ?2001, 2003 renesas technology corp. all rights reserved. printed in japan.
colophon 1.0 sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500 fax: <1> (408) 382-7501 renesas technology europe limited. dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, united kingdom tel: <44> (1628) 585 100, fax: <44> (1628) 585 900 renesas technology europe gmbh dornacher str. 3, d-85622 feldkirchen, germany tel: <49> (89) 380 70 0, fax: <49> (89) 929 30 11 renesas technology hong kong ltd. 7/f., north tower, world finance centre, harbour city, canton road, hong kong tel: <852> 2265-6688, fax: <852> 2375-6836 renesas technology taiwan co., ltd. fl 10, #99, fu-hsing n. rd., taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology (shanghai) co., ltd. 26/f., ruijin building, no.205 maoming road (s), shanghai 200020, china tel: <86> (21) 6472-1001, fax: <86> (21) 6415-2952 renesas technology singapore pte. ltd. 1, harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas sales offices
sh7709s group hardware manual rej09b0081-0500o (ade-602-250c)

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