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preliminary preliminary specification hd66765 396-channel segment driver with internal ram for 4096-color displays target specification rev.0.1 january, 2001 description the hd66765, 396-channel segment driver lsi, displays 132rgb-by-176-dot graphics on stn displays in 4096 colors. it is for driving stn color lcd displays to a maximum of 132rgb by 176 dots, in combination with the hd66764 common driver. the hd66765s bit-operation functions, 16- bit high-speed bus interface, and high-speed ram-write functions enable efficient data transfer and high-speed rewriting of data to the graphics ram. the hd66765 and hd66764 have various functions for reducing the power consumption of an lcd system. the hd66765 has a low-voltage operation (1.8 v min.) and an internal ram to display a maximum of 132rgb-by-176-dot color, and the hd66764 has a step-up circuit to generate the lcd- drive voltage, a bleeder resistor for the drive interface with the lcd, and voltage-followers. since the hd66765 incorporates a circuit that interfaces with the hd66764, it can set instructions for the hd66764. in add ition, precise power control can be achieved by combining these hardware functions with software functions, such as a partial display that only requires a low drive-voltage duty, and standby and sleep modes. this lsi is suitable for any medium-sized or small portable battery-driven product requiring long-term driving capabil ities, such as digital cellular phones supporting a www browser, bidirectional pagers, and small pdas. features 132rgb x 176-dot graphics display lcd controller/driver for 4,096 stn colors (when hd66764 is used) low-voltage drive and flickerless pwm grayscale drive 16-/8-bit high-speed bus interface and serial peripheral interface (spi) high-speed burst-ram write function writing to a window-ram address area by using a window-address function bit-operation functions for graphics processing: ? write-data mask function in bit units ? logical operation in pixel unit and conditional write function
hd66765 2 preliminary specification various color-display control functions: ? 4,096 out of 13,824 possible colors can be displayed at the same time (grayscale palette included) ? vertical scroll display function in raster-row units low-power operation supports: ? vcc = 1.8 to 3.6 v (low-voltage range) ? vlcd = 2.0 to 4.0 v (liquid crystal drive voltage) ? power-save functions such as the standby mode and sleep mode ? partial lcd drive of two screens in any position ? programmable drive duty ratios (1/16C1/176) and bias values (1/4C1/13) displayed on lcd ? maximum 12-times step-up circuit for liquid crystal drive voltage (hd66764) ? voltage followers to decrease direct current flow in the lcd drive bleeder-resistors (hd66764) ? 128-step contrast adjuster (hd66764) built-in circuit for interfacing with the hd66764 common driver maximum 132rgb-by-176-dot display in combination with the hd66764 common driver internal ram capacity: 34,848 bytes 396-segment liquid crystal display driver n-raster-row ac liquid-crystal drive (c-pattern waveform drive) internal oscillation and hardware reset shift change of segment driver type number type number external appearance HD66765TB0 bending tcp hcd66765bp au-bump chip
preliminary 3 preliminary specification hd66765 block diagram index register (ir) vcc osc1 osc2 im2-1, im0/id cs* cl1 flm m dcclk seg1 to seg396 disptmg rs e/wr*/scl rw/rd* db0/sdi, db1/sdo, to db15 ccs* ccl cda reset* test 716 12 12 12 16 16 48 16 16 12 system interface - 16 bits - 8 bits - serial peripheral (spi) common driver interface (serial) segment driver latch circuit gnd vsl vsh grayscale selection circuit latch circuit control register (cr) address counter (ac) bit operation write data latch read data latch palette register (pk) pwm grayscale circuit timing generator cpg graphics ram (gram) 34,848 bytes
hd66765 4 preliminary specification hd66765 pad arrangement (top view) hd66765 y x seg11 seg12 seg75 seg77 seg76 dummy1 dummy40 dummy41 dummy42 - chip size : 13.22mm x 3.85mm - chip thickness : 550um (typ.) - pad coordinate : pad center - coordinate origine : chip center - au bump size : (1) 80um x 80 um dummy1, dummy2-dummy39, dummy40, dummy41, dummy42 (2) 35um x 80um seg304-seg93 (3) 80um x 35um seg386-seg321, seg76-seg11 (4) 45um x 80um seg10-seg1, seg396-seg387, seg320-seg305, seg92-seg77 - au bump pitch : refer pad coordinate - au bump height : 15um (typ.) seg78 seg94 seg93 seg305 seg30 6 seg320 seg31 9 seg386 seg385 seg322 seg321 seg30 4 seg30 3 vcc vcc v cc gnd gnd gnd cs* vcc gnd vsh vsh vsh vsh gnd gnd vcc v cc vsh vsh r w/rd* rs osc2 r eset gnddum2 v cc dum1 im1 im2 cl1 flm disptmg ccl dcclk db15 r eset db14 db12 db13 db11 db10 db 9 g ndd u m1 db8 db7 db6 db5 db3 db4 db2 db0/sdi d b1/sdo e/wr*/scl gnd gnd gnd gnd gnd osc1 im0/id test m ccs cda s e g9 2 seg91 s e g 1 seg2 seg9 s e g 1 0 seg387 seg388 s eg395 s eg396 d ummy17 dummy16 dummy3 d u mmy2 dummy39 dummy38 dummy19 dummy18 n o. 1 n o. 2 n o. 500 n o. 434 n o. 435 n o. 433 no.122 no.123 n o.121 no.189 no.188 no.190 type code hd66765
hd66765 5 preliminary specification hd66765 pad coordinate unit: m rev 0.1 no. pad name x y no. pad name x y no. pad name x y no. pad nam e x y no. pad name x y 1 dummy1 -6480 -1795 101 dummy29 4522 -1795 201 seg309 5573 1795 301 seg209 525 1795 401 seg109 -4477 1795 2 seg10 -6234 -1795 102 dummy30 4623 -1795 202 seg308 5513 1795 302 seg208 475 1795 402 seg108 -4527 1795 3 seg9 -6174 -1795 103 dummy31 4723 -1795 203 seg307 5453 1795 303 seg207 425 1795 403 seg107 -4577 1795 4 seg8 -6113 -1795 104 dummy32 4823 -1795 204 seg306 5393 1795 304 seg206 375 1795 404 seg106 -4627 1795 5 seg7 -6053 -1795 105 dummy33 4923 -1795 205 seg305 5333 1795 305 seg205 325 1795 405 seg105 -4677 1795 6 seg6 -5993 -1795 106 dummy34 5023 -1795 206 seg304 5278 1795 306 seg204 275 1795 406 seg104 -4727 1795 7 seg5 -5933 -1795 107 dummy35 5123 -1795 207 seg303 5228 1795 307 seg203 225 1795 407 seg103 -4777 1795 8 seg4 -5873 -1795 108 dummy36 5223 -1795 208 seg302 5178 1795 308 seg202 175 1795 408 seg102 -4827 1795 9 seg3 -5813 -1795 109 dummy37 5323 -1795 209 seg301 5128 1795 309 seg201 125 1795 409 seg101 -4877 1795 10 seg2 -5753 -1795 110 dummy38 5423 -1795 210 seg300 5078 1795 310 seg200 75 1795 410 seg100 -4928 1795 11 seg1 -5693 -1795 111 dummy39 5523 -1795 211 seg299 5028 1795 311 seg199 25 1795 411 seg99 -4978 1795 12 dummy2 -5505 -1795 112 seg396 5693 -1795 212 seg298 4978 1795 312 seg198 -25 1795 412 seg98 -5028 1795 13 dummy3 -5405 -1795 113 seg395 5753 -1795 213 seg297 4928 1795 313 seg197 -75 1795 413 seg97 -5078 1795 14 dummy4 -5305 -1795 114 seg394 5813 -1795 214 seg296 4877 1795 314 seg196 -125 1795 414 seg96 -5128 1795 15 dummy5 -5205 -1795 115 seg393 5873 -1795 215 seg295 4827 1795 315 seg195 -175 1795 415 seg95 -5178 1795 16 dummy6 -5105 -1795 116 seg392 5933 -1795 216 seg294 4777 1795 316 seg194 -225 1795 416 seg94 -5228 1795 17 dummy7 -5005 -1795 117 seg391 5993 -1795 217 seg293 4727 1795 317 seg193 -275 1795 417 seg93 -5278 1795 18 dummy8 -4905 -1795 118 seg390 6053 -1795 218 seg292 4677 1795 318 seg192 -325 1795 418 seg92 -5333 1795 19 dummy9 -4805 -1795 119 seg389 6113 -1795 219 seg291 4627 1795 319 seg191 -375 1795 419 seg91 -5393 1795 20 dummy10 -4705 -1795 120 seg388 6174 -1795 220 seg290 4577 1795 320 seg190 -425 1795 420 seg90 -5453 1795 21 dummy11 -4605 -1795 121 seg387 6234 -1795 221 seg289 4527 1795 321 seg189 -475 1795 421 seg89 -5513 1795 22 dummy12 -4504 -1795 122 dummy40 6480 -1795 222 seg288 4477 1795 322 seg188 -525 1795 422 seg88 -5573 1795 23 dummy13 -4404 -1795 123 seg386 6480 -1626 223 seg287 4427 1795 323 seg187 -575 1795 423 seg87 -5633 1795 24 dummy14 -4304 -1795 124 seg385 6480 -1576 224 seg286 4377 1795 324 seg186 -625 1795 424 seg86 -5693 1795 25 dummy15 -4204 -1795 125 seg384 6480 -1526 225 seg285 4327 1795 325 seg185 -675 1795 425 seg85 -5753 1795 26 dummy16 -4104 -1795 126 seg383 6480 -1476 226 seg284 4277 1795 326 seg184 -725 1795 426 seg84 -5813 1795 27 dummy17 -4004 -1795 127 seg382 6480 -1426 227 seg283 4227 1795 327 seg183 -775 1795 427 seg83 -5873 1795 28 reset* -3874 -1795 128 seg381 6480 -1376 228 seg282 4177 1795 328 seg182 -825 1795 428 seg82 -5933 1795 29 db15 -3743 -1795 129 seg380 6480 -1326 229 seg281 4127 1795 329 seg181 -875 1795 429 seg81 -5993 1795 30 db14 -3613 -1795 130 seg379 6480 -1276 230 seg280 4077 1795 330 seg180 -925 1795 430 seg80 -6053 1795 31 db13 -3483 -1795 131 seg378 6480 -1226 231 seg279 4027 1795 331 seg179 -975 1795 431 seg79 -6113 1795 32 db12 -3352 -1795 132 seg377 6480 -1176 232 seg278 3977 1795 332 seg178 -1026 1795 432 seg78 -6174 1795 33 db11 -3222 -1795 133 seg376 6480 -1126 233 seg277 3927 1795 333 seg177 -1076 1795 433 seg77 -6234 1795 34 db10 -3091 -1795 134 seg375 6480 -1076 234 seg276 3877 1795 334 seg176 -1126 1795 434 dummy42 -6480 1795 35 db9 -2961 -1795 135 seg374 6480 -1026 235 seg275 3827 1795 335 seg175 -1176 1795 435 seg76 -6480 1626 36 db8 -2831 -1795 136 seg373 6480 -975 236 seg274 3777 1795 336 seg174 -1226 1795 436 seg75 -6480 1576 37 gnddum1 -2731 -1795 137 seg372 6480 -925 237 seg273 3727 1795 337 seg173 -1276 1795 437 seg74 -6480 1526 38 db7 -2631 -1795 138 seg371 6480 -875 238 seg272 3677 1795 338 seg172 -1326 1795 438 seg73 -6480 1476 39 db6 -2500 -1795 139 seg370 6480 -825 239 seg271 3627 1795 339 seg171 -1376 1795 439 seg72 -6480 1426 40 db5 -2370 -1795 140 seg369 6480 -775 240 seg270 3577 1795 340 seg170 -1426 1795 440 seg71 -6480 1376 41 db4 -2239 -1795 141 seg368 6480 -725 241 seg269 3527 1795 341 seg169 -1476 1795 441 seg70 -6480 1326 42 db3 -2109 -1795 142 seg367 6480 -675 242 seg268 3477 1795 342 seg168 -1526 1795 442 seg69 -6480 1276 43 db2 -1979 -1795 143 seg366 6480 -625 243 seg267 3427 1795 343 seg167 -1576 1795 443 seg68 -6480 1226 44 db1/sdo -1848 -1795 144 seg365 6480 -575 244 seg266 3377 1795 344 seg166 -1626 1795 444 seg67 -6480 1176 45 db0/sdi -1718 -1795 145 seg364 6480 -525 245 seg265 3327 1795 345 seg165 -1676 1795 445 seg66 -6480 1126 46 rw/rd* -1587 -1795 146 seg363 6480 -475 246 seg264 3277 1795 346 seg164 -1726 1795 446 seg65 -6480 1076 47 e/wr*/scl -1457 -1795 147 seg362 6480 -425 247 seg263 3227 1795 347 seg163 -1776 1795 447 seg64 -6480 1026 48 rs -1327 -1795 148 seg361 6480 -375 248 seg262 3177 1795 348 seg162 -1826 1795 448 seg63 -6480 975 49 cs* -1196 -1795 149 seg360 6480 -325 249 seg261 3127 1795 349 seg161 -1876 1795 449 seg62 -6480 925 50 gnd -1066 -1795 150 seg359 6480 -275 250 seg260 3077 1795 350 seg160 -1926 1795 450 seg61 -6480 875 51 gnd -966 -1795 151 seg358 6480 -225 251 seg259 3027 1795 351 seg159 -1976 1795 451 seg60 -6480 825 52 gnd -866 -1795 152 seg357 6480 -175 252 seg258 2977 1795 352 seg158 -2026 1795 452 seg59 -6480 775 53 gnd -766 -1795 153 seg356 6480 -125 253 seg257 2926 1795 353 seg157 -2076 1795 453 seg58 -6480 725 54 gnd -666 -1795 154 seg355 6480 -75 254 seg256 2876 1795 354 seg156 -2126 1795 454 seg57 -6480 675 55 gnd -565 -1795 155 seg354 6480 -25 255 seg255 2826 1795 355 seg155 -2176 1795 455 seg56 -6480 625 56 gnd -465 -1795 156 seg353 6480 25 256 seg254 2776 1795 356 seg154 -2226 1795 456 seg55 -6480 575 57 gnd -365 -1795 157 seg352 6480 75 257 seg253 2726 1795 357 seg153 -2276 1795 457 seg54 -6480 525 58 gnd -265 -1795 158 seg351 6480 125 258 seg252 2676 1795 358 seg152 -2326 1795 458 seg53 -6480 475 59 gnd -165 -1795 159 seg350 6480 175 259 seg251 2626 1795 359 seg151 -2376 1795 459 seg52 -6480 425 60 gnd -65 -1795 160 seg349 6480 225 260 seg250 2576 1795 360 seg150 -2426 1795 460 seg51 -6480 375 61 vcc 65 -1795 161 seg348 6480 275 261 seg249 2526 1795 361 seg149 -2476 1795 461 seg50 -6480 325 62 vcc 165 -1795 162 seg347 6480 325 262 seg248 2476 1795 362 seg148 -2526 1795 462 seg49 -6480 275 63 vcc 265 -1795 163 seg346 6480 375 263 seg247 2426 1795 363 seg147 -2576 1795 463 seg48 -6480 225 64 vcc 365 -1795 164 seg345 6480 425 264 seg246 2376 1795 364 seg146 -2626 1795 464 seg47 -6480 175 65 vcc 465 -1795 165 seg344 6480 475 265 seg245 2326 1795 365 seg145 -2676 1795 465 seg46 -6480 125 66 vcc 565 -1795 166 seg343 6480 525 266 seg244 2276 1795 366 seg144 -2726 1795 466 seg45 -6480 75 67 vsh 696 -1795 167 seg342 6480 575 267 seg243 2226 1795 367 seg143 -2776 1795 467 seg44 -6480 25 68 vsh 796 -1795 168 seg341 6480 625 268 seg242 2176 1795 368 seg142 -2826 1795 468 seg43 -6480 -25 69 vsh 896 -1795 169 seg340 6480 675 269 seg241 2126 1795 369 seg141 -2876 1795 469 seg42 -6480 -75 70 vsh 996 -1795 170 seg339 6480 725 270 seg240 2076 1795 370 seg140 -2926 1795 470 seg41 -6480 -125 71 vsh 1096 -1795 171 seg338 6480 775 271 seg239 2026 1795 371 seg139 -2977 1795 471 seg40 -6480 -175 72 vsh 1196 -1795 172 seg337 6480 825 272 seg238 1976 1795 372 seg138 -3027 1795 472 seg39 -6480 -225 73 osc2 1327 -1795 173 seg336 6480 875 273 seg237 1926 1795 373 seg137 -3077 1795 473 seg38 -6480 -275 74 osc1 1457 -1795 174 seg335 6480 925 274 seg236 1876 1795 374 seg136 -3127 1795 474 seg37 -6480 -325 75 gnddum2 1557 -1795 175 seg334 6480 975 275 seg235 1826 1795 375 seg135 -3177 1795 475 seg36 -6480 -375 76 im2 1657 -1795 176 seg333 6480 1026 276 seg234 1776 1795 376 seg134 -3227 1795 476 seg35 -6480 -425 77 im1 1787 -1795 177 seg332 6480 1076 277 seg233 1726 1795 377 seg133 -3277 1795 477 seg34 -6480 -475 78 im0/id 1918 -1795 178 seg331 6480 1126 278 seg232 1676 1795 378 seg132 -3327 1795 478 seg33 -6480 -525 79 vccdum1 2018 -1795 179 seg330 6480 1176 279 seg231 1626 1795 379 seg131 -3377 1795 479 seg32 -6480 -575 80 test 2118 -1795 180 seg329 6480 1226 280 seg230 1576 1795 380 seg130 -3427 1795 480 seg31 -6480 -625 81 dcclk 2248 -1795 181 seg328 6480 1276 281 seg229 1526 1795 381 seg129 -3477 1795 481 seg30 -6480 -675 82 cl1 2379 -1795 182 seg327 6480 1326 282 seg228 1476 1795 382 seg128 -3527 1795 482 seg29 -6480 -725 83 flm 2509 -1795 183 seg326 6480 1376 283 seg227 1426 1795 383 seg127 -3577 1795 483 seg28 -6480 -775 84 m 2640 -1795 184 seg325 6480 1426 284 seg226 1376 1795 384 seg126 -3627 1795 484 seg27 -6480 -825 85 disptmg 2770 -1795 185 seg324 6480 1476 285 seg225 1326 1795 385 seg125 -3677 1795 485 seg26 -6480 -875 86 ccs 2900 -1795 186 seg323 6480 1526 286 seg224 1276 1795 386 seg124 -3727 1795 486 seg25 -6480 -925 87 ccl 3031 -1795 187 seg322 6480 1576 287 seg223 1226 1795 387 seg123 -3777 1795 487 seg24 -6480 -975 88 cda 3161 -1795 188 seg321 6480 1626 288 seg222 1176 1795 388 seg122 -3827 1795 488 seg23 -6480 -1026 89 reset* 3292 -1795 189 dummy41 6480 1795 289 seg221 1126 1795 389 seg121 -3877 1795 489 seg22 -6480 -1076 90 dummy18 3422 -1795 190 seg320 6234 1795 290 seg220 1076 1795 390 seg120 -3927 1795 490 seg21 -6480 -1126 91 dummy19 3522 -1795 191 seg319 6174 1795 291 seg219 1026 1795 391 seg119 -3977 1795 491 seg20 -6480 -1176 92 dummy20 3622 -1795 192 seg318 6113 1795 292 seg218 975 1795 392 seg118 -4027 1795 492 seg19 -6480 -1226 93 dummy21 3722 -1795 193 seg317 6053 1795 293 seg217 925 1795 393 seg117 -4077 1795 493 seg18 -6480 -1276 94 dummy22 3822 -1795 194 seg316 5993 1795 294 seg216 875 1795 394 seg116 -4127 1795 494 seg17 -6480 -1326 95 dummy23 3922 -1795 195 seg315 5933 1795 295 seg215 825 1795 395 seg115 -4177 1795 495 seg16 -6480 -1376 96 dummy24 4022 -1795 196 seg314 5873 1795 296 seg214 775 1795 396 seg114 -4227 1795 496 seg15 -6480 -1426 97 dummy25 4122 -1795 197 seg313 5813 1795 297 seg213 725 1795 397 seg113 -4277 1795 497 seg14 -6480 -1476 98 dummy26 4222 -1795 198 seg312 5753 1795 298 seg212 675 1795 398 seg112 -4327 1795 498 seg13 -6480 -1526 99 dummy27 4322 -1795 199 seg311 5693 1795 299 seg211 625 1795 399 seg111 -4377 1795 499 seg12 -6480 -1576 100 dummy28 4422 -1795 200 seg310 5633 1795 300 seg210 575 1795 400 seg110 -4427 1795 500 seg11 -6480 -1626
hd66765 6 preliminary specification pin functions table 1 pin functional description signals number of pins i/o connected to functions im2-1, im0/id 3 i gnd or v cc selects the mpu interface mode: im1 gnd gnd vcc vcc im0/id gnd vcc gnd vcc mpu interface mode 68-system 16-bit bus interface 68-system 8-bit bus interface 80-system 16-bit bus interface 80-system 8-bit bus interface im2 gnd gnd gnd gnd vcc gnd id serial peripheral interface (spi) when a serial interface is selected, the im0 pin is used as the id setting for a device code. cs* 1 i mpu selects the hd66765: low: hd66765 is selected and can be accessed high: hd66765 is not selected and cannot be accessed must be fixed at gnd level when not in use. rs 1 i mpu selects the register. low: index/status high: control e/wr*/scl 1 i mpu for a 68-system bus interface, serves as an enable signal to activate data read/write operation. for an 80-system bus interface, serves as a write strobe signal and writes data at the low level. for a synchronous clock interface, serves as the synchronous clock signal. rw/rd* 1 i mpu for a 68-system bus interface, serves as a signal to select data read/write operation. low: write high: read for an 80-system bus interface, serves as a read strobe signal and reads data at the low level. db0/sdi 1 i/o mpu serves as a 16-bit bidirectional data bus. for an 8-bit bus interface, data transfer uses db15- db8; fix unused db7-db0 to the vcc or gnd level. for a clock-synchronous serial interface, serves as the serial data input pin (sdi). the input level is read on the rising edge of the scl signal.
hd66765 7 preliminary specification table 1 pin functional description (cont) signals number of pins i/o connected to functions db1/sdo 1 i/o mcu serves as a 16-bit bidirectional data bus. for an 8-bit bus interface, data transfer uses db15- db8; fix unused db7-db0 to the vcc or gnd level. for a clock-synchronous serial interface, serves as a serial data output pin (sdo). successive bit values are output on the falling edge of the scl signal. db2-db15 14 i/o mpu serves as a 16-bit bidirectional data bus. for an 8-bit bus interface, data transfer uses db15- db8; fix unused db7-db0 to the vcc or gnd level. seg1Cse g396 396 o lcd output signals for segment drive. in the display-off period (d1C0 = 00, 01) or standby mode (stb = 1), all pins output gnd level. the sgs bit can change the shift direction of the segment signal. for example, if sgs = 0, ram address 0000 is output from seg1. if sgs = 1, it is output from seg396. seg1, seg4, seg7, ... display red (r), seg2, seg5, seg8, ... display green (g), and seg3, seg6, seg9, ... display blue (b) (sgs = 0). cl1 1 o hd66764 the one-raster-row-cycle pulse is output. m 1 o hd66764 the ac-cycle signal is output. flm 1 o hd66764 the frame-start pulse is output. disptmg 1 o hd66764 outputs the display period signal. dcclk 1 o hd66764 outputs clocks for the step-up. ccl 1 o hd66764 clock signal for a serial transfer of register setting values to the common driver. data is output on the falling edge of this clock. cda 1 o hd66764 data signal for serial transfer as register setting values to the common driver. ccs* 1 o hd66764 chip-select for the hd66764. low: the hd66764 is selected and can receive a serial transfer. high: the hd66764 is not selected and cannot receive a serial transfer. vsh 1 i hd66764 input for the lcd-drive voltage for the segment driver, which can be provided by the hd66764s on-chip power supply. vsh 4.0 v v cc , gnd 2 power supply v cc : + 1.8 v to + 3.6 v; gnd (logic): 0
hd66765 8 preliminary specification table 1 pin functional description (cont) signals number of pins i/o connected to functions osc1, osc2 2 i or o oscillation- resistor connect an external resistor for r-c oscillation. when providing clocks from outside, open osc2. reset* 1 i mpu or external r-c circuit reset pin. initializes the lsi when low. must be reset after power-on. vccdum o input pins outputs the internal v cc level; shorting this pin sets the adjacent input pin to the v cc level. gnddum o input pins outputs the internal gnd level; shorting this pin sets the adjacent input pin to the gnd level. dummy dummy pad. must be left disconnected. test 1 i gnd test pin. must be fixed at gnd level.
hd66765 9 preliminary specification block function description system interface the hd66765 has five high-speed system interfaces: an 80-system 16-bit/8-bit bus, a 68-system 16-bit/8- bit bus, and a serial peripheral (spi: serial peripheral interface port). the interface mode is selected by the im2-0 pins. the hd66765 has three 16-bit registers: an index register (ir), a write data register (wdr), and a read data register (rdr). the ir stores index information from the control registers and the gram. the wdr temporarily stores data to be written into control registers and the gram, and the rdr temporarily stores data read from the gram. data written into the gram from the mpu is first written into the wdr and then is automatically written into the gram by internal operation. data is read through the rdr when reading from the gram, and the first read data is invalid and the second and the following data are normal. when a logic operation is performed inside of the hd66765 by using the display data set in the gram and the data written from the mpu, the data read through the rdr is used. accordingly, the mpu does not need to read data twice nor to fetch the read data into the mpu. this enables high-speed processing. execution time for instruction excluding oscillation start is 0 clock cycle and instructions can be written in succession. table 2 register selection (8/16 parallel interface) 80-system bus 68-system bus wr rd r/w rs operations 0 1 0 0 writes indexes into ir 1 0 1 0 reads internal status 0 1 0 1 writes into control registers and gram through wdr 1 0 1 1 reads from gram through rdr table 3 register selection (serial peripheral interface) start bytes r/w bits rs bits operations 0 0 writes indexes into ir 1 0 reads internal status 0 1 writes into control registers and gram through wdr 1 1 reads from gram through rdr
hd66765 10 preliminary specification bit operation the hd66765 supports the following functions: a write data mask function that selects and writes data into the gram in bit units, and a logic operation function that performs logic operations or conditional determination on the display data set in the gram and writes into the gram. with the 16-bit bus interface, these functions can greatly reduce the processing loads of the mpu graphics software and can rewrite the display data in the gram at high speed. for details, see the graphics operation function section. address counter (ac) the address counter (ac) assigns addresses to the gram. when an address set instruction is written into the ir, the address information is sent from the ir to the ac. after writing into the gram, the ac is automatically incremented by 1 (or decremented by 1). after reading from the data, the ac is not updated. a window address function allows for data to be written only to a window area specified by gram. graphics ram (gram) the graphics ram (gram) has eight bits/pixel and stores the bit-pattern data of 132 x 176 bytes. pwm grayscale circuit the pwm grayscale circuit generates a pwm signal that corresponds to the grayscale levels as specified in the grayscale palette register. any 4096 out of 13,824 possible colors can be displayed at the same time. for details, see the grayscale palette section. grayscale selection circuit the grayscale selection circuit reads data from the gram and controls the signal generated in the pwm grayscale circuit. pwm (pulse width modulation) is used to control each color in the display. for details, see the grayscale palette section. timing generator the timing generator generates timing signals for the operation of internal circuits such as the gram. the ram read timing for display and internal operation timing by mpu access are generated separately to avoid interference with one another. the timing generator generates the interface signals (m, flm, cl1, disptmg, and dcclk) for the common driver. oscillation circuit (osc) the hd66765 can provide r-c oscillation simply through the addition of an external oscillation-resistor between the osc1 and osc2 pins. the appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the external-resistor value. clock pulses can also be supplied externally. since r-c oscillation stops during the standby mode, current consumption can be reduced. for details, see the oscillation circuit section.
hd66765 11 preliminary specification liquid crystal display driver circuit the liquid crystal display driver circuit consists of 396 segment signal drivers (seg1 to seg396). display pattern data is latched when 396-bit data has arrived. the latched data then enables the segment signal drivers to generate drive waveform outputs. the shift direction of 396-bit data can be changed by the sgs bit by selecting an appropriate direction for the device mounting configuration. when multiplexing drive is not used, or during standby mode, all of the common and segment signal drivers listed above, and the common drivers from the hd66764, output the gnd level, halting the display. interface with common driver a serial interface circuit provides an interface with the hd66764 common driver. when sending an instruction setting from the hd66765 to a common driver, a register setting value from within the hd66765 is transferred via the serial interface circuit. a transfer is started by setting a serial transfer enable in the hd66765. however, transfer to and reading from the common driver are not possible during standby. for details, see the common serial transfer section.
hd66765 12 preliminary specification table relationship between gram address and display position (sgs=0) cms=0 seg/com pins seg1 cms=1 db 11 db 0 com1 seg2 seg3 seg4 seg5 seg6 com176 "0000"h "0001"h "0100"h "0101"h "0200"h "0201"h "0300"h "0301"h "0400"h "0401"h "0500"h "0501"h "0600"h "0601"h "0700"h "0701"h "0800"h "0801"h "0900"h "0901"h "0a00"h "0a01"h "0b00"h "0b01"h "0c00"h "0c01"h "0d00"h "0d01"h "0e00"h "0e01"h "0f00"h "0f01"h "1000"h "1001"h "1100"h "1101"h "1200"h "1201"h "1300"h "1301"h "a800"h "a801"h "a900"h "a901"h "aa00"h "aa01"h "ab00"h "ab01"h "ac00"h "ac01"h "ad00"h "ad01"h "ae00"h "ae01"h "af00"h "af01"h "0082"h "0083"h "0182"h "0183"h "0282"h "0283"h "0382"h "0383"h "0482"h "0483"h "0582"h "0583"h "0682"h "0683"h "0782"h "0783"h "0882"h "0883"h "0982"h "0983"h "0a82"h "0a83"h "0b82"h "0b83"h "0c82"h "0c83"h "0d82"h "0d83"h "0e82"h "0e83"h "0f82"h "0f83"h "1082"h "1083"h "1182"h "1183"h "1282"h "1283"h "1382"h "1383"h "a882"h "a883"h "a982"h "a983"h "aa82"h "aa83"h "ab82"h "ab83"h "ac82"h "ac83"h "ad82"h "ad83"h "ae82"h "ae83"h "af82"h "af83"h com2 com175 com3 com174 com4 com173 com5 com172 com6 com171 com7 com170 com8 com169 com9 com168 com10 com167 com11 com166 com12 com165 com13 com164 com14 com163 com15 com162 com16 com161 com17 com160 com18 com159 com19 com158 com20 com157 com169 com8 com170 com7 com171 com6 com172 com5 com173 com4 com174 com3 com175 com2 com176 com1 db 11 db 0 seg391 db 11 db 0 seg392 seg393 seg394 seg395 seg396 db 11 db 0 table relationship between gram data and output pin (sgs=0) gram data db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 selected palette n/a pk palette pk palette pk palette output pin n/a seg (3n+1) seg (3n+2) seg (3n+3) n = lower 6-bits address (0 to 131)
hd66765 13 preliminary specification table relationship between gram address and display position (sgs=1) cms=0 seg/com pins cms=1 com1 "0000"h "0001"h "0100"h "0101"h "0200"h "0201"h "0300"h "0301"h "0400"h "0401"h "0500"h "0501"h "0600"h "0601"h "0700"h "0701"h "0800"h "0801"h "0900"h "0901"h "0a00"h "0a01"h "0b00"h "0b01"h "0c00"h "0c01"h "0d00"h "0d01"h "0e00"h "0e01"h "0f00"h "0f01"h "1000"h "1001"h "1100"h "1101"h "1200"h "1201"h "1300"h "1301"h com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com8 com7 com6 com5 com4 com3 com2 com1 com176 com175 com174 com173 com172 com171 com170 com169 com168 com167 com166 com165 com164 com163 com162 com161 com160 com159 com158 com157 com169 com170 com171 com172 com173 com174 com175 com176 "a800"h "a801"h "a900"h "a901"h "aa00"h "aa01"h "ab00"h "ab01"h "ac00"h "ac01"h "ad00"h "ad01"h "ae00"h "ae01"h "af00"h "af01"h seg1 db 11 db 0 seg2 seg3 seg4 seg5 seg6 db 11 db 0 seg391 db 11 db 0 seg392 seg393 seg394 seg395 seg396 db 11 db 0 "0083"h "0183"h "0283"h "0383"h "0483"h "0583"h "0683"h "0783"h "0883"h "0983"h "0a83"h "0b83"h "0c83"h "0d83"h "0e83"h "0f83"h "1083"h "1183"h "1283"h "1383"h "a883"h "a983"h "aa83"h "ab83"h "ac83"h "ad83"h "ae83"h "af83"h "0082"h "0182"h "0282"h "0382"h "0482"h "0582"h "0682"h "0782"h "0882"h "0982"h "0a82"h "0b82"h "0c82"h "0d82"h "0e82"h "0f82"h "1082"h "1182"h "1282"h "1382"h "a882"h "a982"h "aa82"h "ab82"h "ac82"h "ad82"h "ae82"h "af82"h table relationship between gram data and output pin (sgs=1) gram data db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 selected palette n/a pk palette pk palette pk palette output pin n/a seg (396n-3n) seg (395-3n) seg (394-3n) n = lower 6-bits address (0 to 131)
hd66765 14 preliminary specification instructions outline the hd66765 uses the 16-bit bus architecture. before the internal operation of the hd66765 starts, control information is temporarily stored in the registers described below to allow high-speed interfacing with a high-performance microcomputer. the internal operation of the hd66765 is determined by signals sent from the microcomputer. these signals, which include the register selection signal (rs), the read/write signal (r/w), and the data bus signals (db15 to db0), make up the hd66765 instructions. there are nine categories of instructions that: ? specify the index ? read the status ? control the display ? control power management ? process the graphics data ? set internal gram addresses ? transfer data to and from the internal gram ? set grayscale level for the internal grayscale palette table ? interface with the common driver normally, instructions that write data are used the most. however, an auto-update of internal gram addresses after each data write can lighten the microcomputer program load. because instructions are executed in 0 cycles, they can be written in succession.
hd66765 15 preliminary specification instruction descriptions index the index instruction specifies the ram control indexes (r00h to r37h). it sets the register number in the range of 00000 to 110111 in binary form. however, r40 to r44 are disabled since they are test registers. r/w w 0 * id6 id5 id4 id3 id2 id1 id0 rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 * * * * * * * * figure 1 index instruction status read the status read instruction reads the internal status of the hd66765. l7C0: indicate the driving raster-row position where the liquid crystal display is being driven. c6C0: read the contrast setting values (ct6C0). r/w r 0 c6 c5 c4 c3 c2 c1 c0 rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 l5 l4 l3 l2 l1 l0 0 l7 l6 figure 2 status read instruction start oscillation (r00h) the start oscillation instruction restarts the oscillator from the halt state in the standby mode. after issuing this instruction, wait at least 10 ms for oscillation to stabilize before issuing the next instruction. (see the standby mode section.) if this register is read forcibly, *765h is read. r/w w1 1 rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 * * * * * * * * * * * * * * * r1 1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 0 figure 3 start oscillation instruction
hd66765 16 preliminary specification driver output control (r01h) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w1 nl0 nl1 nl2 nl3 nl4 0 0 0 sgs cms 0 0 0 0 0 0 figure 4 driver output control instruction cms: selects the output shift direction of a common driver. when cms = 0, com1 shifts to com176. when cms = 1, com176 shifts to com1. sgs: selects the output shift direction of a segment. when sgs = 0, seg1 shifts to seg396 and color is assigned from seg1. when sgs = 1, seg396 shifts to seg1 and color is assigned from seg396. re-write to the ram when intending to change the sgs bit. note: the cms bit is for setting the common driver. control according to the bits value is executed by the common driver. for details, see the data sheet for the common driver. nl4C0: specify the lcd drive duty ratio. the duty ratio can be adjusted for every eight raster-rows. gram address mapping does not depend on the setting value of the drive duty ratio.
hd66765 17 preliminary specification table 8 nl bits and drive duty nl4 nl3 nl2 nl1 nl0 display size lcd drive duty common driver used 0 0 0 0 0 setting disabled setting disabled setting disabled 0 0 0 0 1 396 x 16 dots 1/16 duty com1Ccom16 0 0 0 1 0 396 x 24 dots 1/24 duty com1Ccom24 0 0 0 1 1 396 x 32 dots 1/32 duty com1Ccom32 0 0 1 0 0 396 x 40 dots 1/40 duty com1Ccom40 0 0 1 0 1 396 x 48 dots 1/48 duty com1Ccom48 0 0 1 1 0 396 x 56 dots 1/56 duty com1Ccom56 0 0 1 1 1 396 x 64 dots 1/64 duty com1Ccom64 0 1 0 0 0 396 x 72 dots 1/72 duty com1Ccom72 0 1 0 0 1 396 x 80 dots 1/80 duty com1Ccom80 0 1 0 1 0 396 x 88 dots 1/88 duty com1Ccom88 0 1 0 1 1 396 x 96 dots 1/96 duty com1Ccom96 0 1 1 0 0 396 x 104 dots 1/104 duty com1Ccom104 0 1 1 0 1 396 x 112 dots 1/112 duty com1Ccom112 0 1 1 1 0 396 x 120 dots 1/120 duty com1Ccom120 0 1 1 1 1 396 x 128 dots 1/128 duty com1Ccom128 1 0 0 0 0 396 x 136 dots 1/136 duty com1Ccom136 1 0 0 0 1 396 x 144 dots 1/144 duty com1Ccom144 1 0 0 1 0 396 x 152 dots 1/152 duty com1Ccom152 1 0 0 1 1 396 x 160 dots 1/160 duty com1Ccom160 1 0 1 0 0 396 x 168 dots 1/168 duty com1Ccom168 1 0 1 0 1 396 x 176 dots 1/176 duty com1Ccom176
hd66765 18 preliminary specification lcd-driving-waveform control (r02h) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w1 nw0 nw1 nw2 nw3 nw4 nw5 0 0 eor b/c 0 0 0 0 0 0 figure 5 lcd-driving-waveform control instruction b/c: when b/c = 0, a b-pattern waveform is generated and alternates in every frame for lcd drive. when b/c = 1, a c-pattern waveform is generated and alternates in each raster-row specified by bits eor and nw4Cnw0 in the lcd-driving-waveform control register. for details, see the n-raster-row reversed ac drive section. eor: when the c-pattern waveform is set (b/c = 1) and eor = 1, the odd/even frame-select signals and the n-raster-row reversed signals are eored for alternating drive. eor is used when the lcd is not alternated by combining the set values of the lcd drive duty ratio and the n raster-row. for details, see the n-raster-row reversed ac drive section. nw5C0: specify the number of raster-rows n that will alternate at the c-pattern waveform setting (b/c = 1). nw4Cn w0 alternate for every set value + 1 raster-row , and the f ir st to the 64th raster- rows can be selected. power control 1 (r03h) power control 2 (r0ch) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w1 stb slp ap0 ap1 dc0 dc1 dc2 0 bt0 bt1 bt2 bt3 bs0 bs1 bs2 0 w1 vc0 vc1 vc2 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 6 power control instruction bs2C0: the lcd drive bias value is set. the lcd drive bias value can be selected according to its drive duty ratio and voltage. bt3C0: the output factor of step-up is switched. the lcd drive voltage level can be selected according to its drive duty ratio and bias. lower amplification of the step-up circuit consumes less current. dc2C0: the operating frequency in the step-up circuit is selected. when the step-up operating frequency is high, the driving ability of the step-up circuit and the display quality become high, but the current consumption is increased. adjust the frequency considering the display quality and the current consumption. ap1C0: the amount of fixed current from the fixed current source in the operational amplifier for the lcd is adjusted. when the amount of fixed current is large, the lcd driving ability and the display quality become high, but the current consumption is increased. adjust the fixed current considering the display quality and the current consumption.
hd66765 19 preliminary specification during no display, when ap1C0 = 00, the current consumption can be reduced by ending the operational amplifier and step-up circuit operation. vc2-0: sets an adjustment factor for the vci voltage (vc2-0). slp: when slp = 1, the hd66765 enters the sleep mode, where the internal display operations are halted except for the r-c oscillator, thus reducing current consumption. only the following instructions can be executed during the sleep mode. power control (bs2C0, bt3C0, dc2C0, ap1C0, slp, and stb bits) common interface control (te, idx) during the sleep mode, the other gram data and instructions cannot be updated although they are retained. note: bs2-0, bt3-0, dc2-0, ap1-0, vc2-0 and slp bits are for setting the common driver. control ac cor ding to the bits values is exe cuted by the common dr iver. for de tails, se e the da ta sheet for the common driver. stb: when stb = 1, the hd66765 enters the standby mode, where display operation completely stops, halting all the internal operations including the internal r-c oscillator. further, no external clock pulses are supplied. for details, see the standby mode section. only the following instructions can be executed during the standby mode. a. standby mode cancel (stb = 0) b. start oscillation during the standby mode, the gram data and instructions may be lost. to prevent this, they must be set again after the standby mode is canceled. serial transfer to the common driver is not possible when it is in standby mode. transfer the data again after it has been released from standby mode. contrast control (r04h) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w1 ct0 ct1 ct2 vr0 vr1 vr2 ct3 ct4 ct5 ct6 0 vr3 0 0 0 0 figure 7 contrast control instruction ct6C0: these bits control the lcd drive voltage to adjust 128-step contrast. for details, see the contrast adjuster section. vr3C0: these bits adjust the output voltage in the lcd drive reference generator. note: ct6-0 and vr3-0 bits are for setting the common driver. control according to the bits values is executed by the common driver. for details, see the data sheet for the common driver.
hd66765 20 preliminary specification entry mode (r05h) compare register (r06h) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w1 lg0 lg1 lg2 am i/d0 i/d1 0 0 0 hwm 0 0 0 0 0 0 w1 cp0 cp1 cp2 cp3 cp4 cp5 cp6 cp7 cp8 cp9 cp10 cp11 0 0 0 0 figure 8 entry mode and compare register instruction the write data sent from the microcomputer is modified in the hd66765 and written to the gram. the display data in the gram can be quickly rewritten to reduce the load of the microcomputer software processing. for details, see the graphics operation function section. hwm: when hwm=1, data can be written to the gram at high speed. in high-speed write mode, four words of data are written to the gram in a single operation after writing to ram four times. write to ram four times, otherwise the four words cannot be written to the gram. thus, set the lower 2 bits to 0 when setting the ram address. for details, see high-speed ram write mode section. i/d1-0: when i/d1-0 = 1, the address counter (ac) is automatically incremented by 1 after the data is written to the gram. when i/d1-0 = 0, the ac is automatically decremented by 1 after the data is written to the gram. the increment/decrement setting of the address counter by i/d1-0 is done independently for the upper (ad15-8) and lower (ad7-0) addresses. the direction of moving through the addresses when the gram is written to is set by the am bit. am: set the automatic update method of the ac after the data is written to the gram. when am = 0, the data is continuously written in parallel. when am = 1, the data is continuously written vertically. when window address range is specified, the gram in the window address range can be written to according to the i/d1-0 and am settings.
hd66765 21 preliminary specification am = "0" horizontal 0000h af83h 0000h af83h 0000h af83h i/d1-0 = "00" horizontal: decrement vertical: decrement note: when a window address range has been set, the gram can only be witten to within that range. i/d1-0 = "10" horizontal: decrement vertical: increment i/d1-0 = "11" horizontal: increment vertical: increment i/d1-0 = "01" horizontal: increment vertical: decrement am = "1" vertical 0000h af83h 0000h af83h 0000h af83h 0000h af83h 0000h af83 direction settings figure 9 address direction settings lg2C0: compare the data read from the gram by the microcomputer with the compare registers (cp7C0) by a compare/logical operation and write the results to gram. for details, see the logical/compare operation function. cp11C0: set the compare register for the compare operation with the data read from the gram or written by the microcomputer. db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 1 1 1 0 0 0 1 1 0 0 0 1 write data sent from the microcomputer (db11-0) logical/compare operation (lg2-0) write data mask * (wm11-0) logical operaion (with read data and write data) lg2-0 = "000" replace lg2-0 = "001" or lg2-0 = "010" and lg2-0 = "011" eor compare operaion (with compare register) lg2-0 = "100" replacement of matched readdata lg2-0 = "101" replacement of unmatched read data lg2-0 = "110" replacement of matched write data lg2-0 = "111" replacement of ummatched write data write data mask (wm11-0) gram note : the write data mask (wm11-0) is set by the register in the ram write data mask section. figure 10 logical/compare operation and swapping for the gram
hd66765 22 preliminary specification display control (r07h) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w1 d0 d1 rev 00 0 0 0 spt vle1 vle2 0 0 0 0 0 figure 11 display control instruction vle2C1: when vle1 = 1, a vertical scroll is performed in the 1st screen. when vle2 = 1, a vertical scroll is performed in the 2nd screen. vertical scrolling on the two screens can be independently controlled. spt: when spt = 1, the 2-division lcd drive is performed. for details, see the screen-division driving function section. rev: displays all character and graphics display sections with reversal when rev = 1. for details, see the reversed display function section. since the grayscale level can be reversed, display of the same data is enabled on normally-white and normally-black panels. d1C0: display is on when d1 = 1 and off when d1 = 0. when off, the display data remains in the gram, and can be displayed instantly by setting d1 = 1. when d1 is 0, the display is off with all of the seg/com pin outputs set to the gnd level. because of this, the hd66765 can control the charging current for the lcd with ac driving. when d1C0 = 01, the internal display of the hd66765 is performed although the display is off. when d1-0 = 00, the internal display operation halts and the display is off. table 9 d bits and operation d1 d0 seg/com output hd66765 internal display operation master/slave signal (cl1, flm, m, and disptmg) 0 0 gnd halt halt 0 1 gnd operate operate 1 0 unlit display operate operate 1 1 display operate operate notes: 1. writing from the microcomputer to the gram is independent from d1C0. 2. in the sleep and standby modes, d1C0 = 00. however, the register contents of d1C0 are not modified. note: spt and d1 bits are for setting the common driver. control according to the bits values is executed by the common driver. for details, see the data sheet for the common driver.
hd66765 23 preliminary specification com driver interface control (r0ah) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w1 idx0 idx1 idx2 idx0 idx1 idx2 00 0 0 0 te te 000 00 0 0 0 0 r1 00 0 0 0 0 0 0 0 0 figure 12 com driver interface control instruction idx2-0 : index bits that select instructions for the common driver. the instruction that corresponds to the setting made here is transferred, with the index, to the common driver via the serial interface. these instructions are transferred in bit rows as shown below. the upper 3 bits correspond to idx2-0. the idx2-0 setting at the time of transfer selects the instruction for the common driver as listed below. to change an instruction setting on the common driver, first change the instruction bit on the hd66765, select the instruction, which includes the changed instruction bit, from the list below, by setting idx2-0 as required. the instruction is transferred to the common driver as the transfer starts (te=1), and is the executed . te: ser ial tra nsfe r e nable for the common dr ive r. w hen te=0, se rial tr ansfe r is possible . do not change the instruction during transfer. when te=1, transfer starts. te returning to 0 indicates the end of the transfer. note that, serial transfer to the common driver requires 18 clock cycles at most. do not change the instruction during the transfer. * new instructions should be transferred to the common driver soon after they have been set on the hd66765.
hd66765 24 preliminary specification table of common driver (hd66764) instructions idx2 idx1 idx0 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 slp ap0 ap1 vc0 vc1 vc2 dc1 dc0 0 bt0 bt1 bt2 0 bs1 bs0 bt3 00 bs2 0 0 0 00 0 0 0 0 0 1 0 0 ct0 ct1 ct2 vr0 vr2 vr1 ct4 ct3 ct5 ct6 0 vr3 0 0 1 0 ss10 ss11 ss12 spt d1 cms ss14 ss13 ss15 ss16 ss17 se10 se11 se12 se14 se13 se15 se16 se17 0 0 1 1 0 0 00 ss20 ss21 ss22 ss24 ss23 ss125 ss26 ss27 se20 se21 se22 se24 se23 se25 se26 se27 0 0 00 1 10 1 1 1 0 00 0 0 0 0 00 0 0 instruction setting change index set r0ah instruction read specify the idx2 to 0 in the hd66764 instruction including a changed instruction bit common side index (idx2 to 0) te = 1 (transfer start) te = "0" no (during transfer) yes (transfer can be executed) transfer to the common driver must be executed immediately after setting up the instruction change the instruction bit setting corresponding to the hd66765 notes: 1. transfer to the common driver must take place immediately after setting up the instruction. 2. the serial transfer period takes a maximum of 1/fosc x 18 clock cycles (sec). 3. serial transfer cannot be executed in standby mode. if the chip enters standbymode during transfer, the serial transfer is forcibly suspended. transfer must be executed again because correct transfer is not guaranteed in this situation. 4. serial transfer can be forcibly suspended by writing te = 0. transfer must be executed again because correct transfer is not guaranteed in this situation. 5. do not enter standby mode during transfer or forcibly terminate transfer except in case of emergency. before executing, confirm that the transfer is completed. figure 13 common interface: serial transfer sequence
hd66765 25 preliminary specification frame cycle control (r0bh) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w1 rtn0 rtn1 rtn2 rtn3 0 0 0 0 div0 div1 0 0 0 0 0 0 figure 14 frame cycle control instruction rtn3-0: set the line retrace period (rtn3-0) to be added to raster-row cycles. the raster-row cycle becomes longer according to the number of clocks set at rtn3-0. div1-0: set the division ratio of clocks for internal operation (div1-0). internal operations are driven by clocks which are frequency divided according to the div1-0 setting. frame frequency can be adjusted along with the line retrace period (rtn3-0). when changing the drive-duty cycle, adjust the frame frequency. for details, see the frame frequency adjustment function section. table 10 rtn bits and clock cycles rtn3 rtn2 rtn1 rtn0 line retrace period (clock cycles) clock cycles per raster-row 0000 0 25 0001 1 26 0010 2 27 0011 3 28 :::: : : 1110 14 39 1111 15 40 table 11 div bits and clock frequency div1 div0 division ratio internal operation clock frequency 0 0 1 fosc / 1 0 1 2 fosc / 2 1 0 4 fosc / 4 1 1 8 fosc / 8 * fosc = r-c oscillation frequency
hd66765 26 preliminary specification formula for the frame frequency fosc frame frequency = [h z] clock cycles per raster-row division ratio 1/duty cycle fosc: r-c oscillation frequency duty: drive duty (nl bit) division ratio: div bit clock cycles per raster-row: (rtn + 25) clock cycles vertical scroll control (r11h) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w1 vl10 vl11 vl12 vl13 vl14 vl15 vl16 vl17 vl20 vl21 vl22 vl23 vl24 vl25 vl26 vl27 figure 15 vertical scroll control instruction vl17C10: specify the display-start raster-row at the 1st screen display for vertical smooth scrolling. any raster-row from the first to 176th can be selected. after the 176th raster-row is displayed, the display restarts from the first raster-row. the display-start raster-row (vl17C10) is valid only when vle1 = 1. the raster-row display is fixed when vle1 = 0. (vle1 is the 1st-screen vertical-scroll enable bit.) vl27C20: specify the display-start raster-row at the 2nd screen display. the display-start raster-row (vl27C20) is valid only when vle2 = 1. the raster-row display is fixed when vle2 = 0. (vle2 is the 2nd-screen vertical-scroll enable bit.) the vertical scroll for the 1st and 2nd screens can be independently set. table 22 vl bits and display-start raster-row vl27 vl17 vl26 vl16 vl25 vl15 vl24 vl14 vl23 vl13 vl22 vl12 vl21 vl11 vl20 vl10 display-start raster-row 0000 000 0 1st raster-row 0000 000 1 2nd raster-row 0000 001 0 3rd raster-row :::: ::: :: 1010 111 0 175th raster-row 1010 111 1 176th raster-row note: do not set over the 176th (afh) raster-row.
hd66765 27 preliminary specification 1st screen driving position (r14h) 2nd screen driving position (r15h) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w1 ss10 ss11 ss12 ss13 ss14 ss15 ss16 ss17 se10 se11 se12 se13 se14 se15 se16 se17 w1 ss20 ss21 ss22 ss23 ss24 ss25 ss26 ss27 se20 se21 se22 se23 se24 se25 se26 se27 figure 16 1st screen driving position and 2nd screen driving position instructions ss17C0: specify the driving start position for the first screen in a line unit. the lcd driving starts from the 'set value + 1' common driver. se17C0: specify the driving end position for the first screen in a line unit. the lcd driving is performed to the 'set value + 1' common driver. for instance, when ss17C10 = 07h and se17C10 = 10h are set, the lcd driving is performed from com8 to com17, and non-selection driving is performed for com1 to com7, com18, and others. ensure that ss17C10 se17C10 afh. for details, see the screen-division driving function section. ss27C0: specify the driving start position for the second screen in a line unit. the lcd driving starts from the 'set value + 1' common driver. the second screen is driven when spt = 1. se27C0: specify the driving end position for the second screen in a line unit. the lcd driving is performed to the 'set value + 1' common driver. for instance, when spt = 1, ss27C20 = 20h, and se27C20 = afh are set, the lcd driving is performed from com33 to com80. ensure that ss17C10 se17C10 ss27C20 se27C20 4fh. for details, see the screen-division driving function section.
hd66765 28 preliminary specification horizontal ram address position (r16h) vertical ram address position (r17h) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w1 hsa0 hsa1 hsa2 hsa3 hsa4 hsa5 hsa6 hsa7 hea0 hea1 hea2 hea3 hea4 hea5 hea6 hea7 w1 vsa0 vsa1 vsa2 vsa3 vsa4 vsa5 vsa6 vsa7 vea0 vea1 vea2 vea3 vea4 vea5 vea6 vea7 figure 17 horizontal/vertical ram address position instruction hsa7-0/hea7-0: specify the horizontal start/end positions of a window for access in memory. data can be written to the gram from the address specified by hea7-0 from the address specified by hsa7-0. note that an address must be set before ram is written to. ensure 00h hsa7-0 hea7-0 3fh. vsa7-0/vea7-0: specify the vertical start/end positions of a window for access in memory. data can be written to the gram from the address specified by vea7-0 from the address specified by vsa7-0. note that an address must be set before ram is written to. ensure 00h vsa7-0 vea7-0 afh. vsa vea hsa gram address space 0000h af83h hea window address window address setting range "00"h hsa7-0 hea7-0 "83"h "00"h vsa7-0 vea7-0 "af"h note: 1. ensure that the window address area is within the gram address space. 2. in high-speed write mode, data are written to gram in four-words. thus, dummy write operations should be inserted depending on the window address area. for details, see the high-speed burst ram write function section. figure 18 window address setting range
hd66765 29 preliminary specification ram write data mask (r20h) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w1 wm 0 wm 1 wm 2 wm 3 wm 4 wm 5 wm 6 wm 7 wm 8 wm 9 wm 10 wm 11 0 0 0 0 figure 19 ram write data mask instruction wm11C0: in writing to the gram, these bits mask writing in a bit unit. when wm11 = 1, this bit masks the write data of db11 and does not write to the gram. similarly, the wm10C0 bits mask the write data of db10C0 in a bit unit. when swp = 1, the upper and lower bytes in the write data mask are swapped. for details, see the graphics operation function section. ram address set (r21h) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w1 ad 0 ad 1 ad 2 ad 3 ad 4 ad 5 ad 6 ad 7 ad 8 ad 9 ad 10 ad 11 ad 12 ad 13 ad 14 ad 15 figure 20 ram address set instruction ad15C0: initially set gram addresses to the address counter (ac). once the gram data is written, the ac is automatically updated according to the am and i/d bit settings. this allows consecutive accesses without resetting addresses. once the gram data is read, the ac is not automatically updated. gram address setting is not allowed in the standby mode. ensure that the address is set within the specified window address. table 13 gram address range in eight-grayscale mode ad14Cad0 gram setting "0000"hC"0083"h bitmap data for com1 "0100"hC"0183"h bitmap data for com2 "0200"hC"0283"h bitmap data for com3 "0300"hC"0383"h bitmap data for com4 : : "ac00"hC"ac83"h bitmap data for com173 "ad00"hC"ad83"h bitmap data for com174 "ae00"hC"ae83"h bitmap data for com175 "af00"hC"af83"h bitmap data for com176
hd66765 30 preliminary specification write data to gram (r22h) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w1 0000 wd 0 wd 1 wd 2 wd 3 wd 4 wd 5 wd 6 wd 7 wd 8 wd 9 wd 10 wd 11 figure 21 write data to gram instruction wd11C0 : write 12-bit data to the gram. this data calls each grayscale palette. after a write, the address is automatically updated according to the am and i/d bit settings. during the standby mode, the gram cannot be accessed. db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 wd 0 wd 1 wd 2 wd 3 wd 4 wd 5 wd 6 wd 7 wd 8 wd 9 wd 10 wd 11 gram write data 1 pixel data r0 r1 r2 0000 r3 b0 b1 b2 b3 g0 g1 g2 g3 figure 22 gram write data instruction table 14 gram data and grayscale palette gram data setting r3 r2 r1 r0 g3 g2 g1 g0 b3 b2 b1 b0 grayscale palette 0000 pk04 pk03 pk02 pk01 pk00 0001 pk14 pk13 pk12 pk11 pk10 0010 pk24 pk23 pk22 pk21 pk20 0011 pk34 pk33 pk32 pk31 pk30 0100 pk44 pk43 pk42 pk41 pk40 0101 pk54 pk53 pk52 pk51 pk50 0110 pk64 pk63 pk62 pk61 pk60 0111 pk74 pk73 pk72 pk71 pk70 1000 pk84 pk83 pk82 pk81 pk80 1001 pk94 pk93 pk92 pk91 pk90 1010 pk104 pk103 pk102 pk101 pk100 1011 pk114 pk113 pk112 pk111 pk110 1100 pk124 pk123 pk122 pk121 pk120 1101 pk134 pk133 pk132 pk131 pk130 1110 pk144 pk143 pk142 pk141 pk140 1111 pk154 pk153 pk152 pk151 pk150
hd66765 31 preliminary specification read data from gram (r22h) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 r1 0000 rd 0 rd 1 rd 2 rd 3 rd 4 rd 5 rd 6 rd 7 rd 8 rd 9 rd 10 rd 11 figure 23 read data from gram instruction rd11C0: read 12-bit data from the gram. when the data is read to the microcomputer, the first-word read immediately after the gram address setting is latched from the gram to the internal read-data latch. the data on the data bus (db11C0) becomes invalid and the second-word read is normal. when bit processing, such as a logical operation, is performed within the hd66765, only one read can be processed since the latched data in the first word is used. address: n set dummy read (invalid data) gram -> read-data latch read (data of address n) read-data latch -> db11-0 first word second word i) data read to the microcomputer ii) logical operation processing in the hd66765 address: m set dummy read (invalid data) gram -> read-data latch read (data of address m) read-data latch -> db11-0 first word second word sets the i/d, am, hsa/hea, and vsa/vea bits address: n set dummy read (invalid data) gram -> read-data latch sets the i/d, am, hsa/hea, and vsa/vea bits read (data of address n) db11-0 -> gram dummy read (invalid data) gram -> read-data latch write (data of address n+ ) db11-0 -> gram automatic address update: n + a a first word second word first word second word figure 24 gram read sequence
hd66765 32 preliminary specification grayscale palette control (r30h to r39h) r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 w r30h 1 pk10 pk11 pk12 pk13 0 0 0 0 0 0 w r31h 1 pk30 pk31 pk32 pk33 0 0 0 0 0 0 w r32h 1 pk50 pk51 pk52 pk53 0 0 0 0 0 0 w r33h 1 pk70 pk71 pk72 pk73 0 0 0 0 0 0 w r34h 1 pk90 pk91 pk92 pk93 0 0 0 0 0 0 w r35h 1 pk110 pk111 pk112 pk113 0 0 0 0 0 0 w r36h 1 pk130 pk131 pk132 pk133 0 0 0 0 0 0 w r37h 1 pk150 pk151 pk152 pk153 pk14 pk34 pk54 pk74 pk94 pk114 pk134 pk154 pk00 pk01 pk02 pk03 pk20 pk21 pk22 pk23 pk40 pk41 pk42 pk43 pk60 pk61 pk62 pk63 pk80 pk81 pk82 pk83 pk100 pk101 pk102 pk103 pk120 pk121 pk122 pk123 pk140 pk141 pk142 pk143 pk04 pk24 pk44 pk64 pk84 pk104 pk124 pk144 0 0 0 0 0 0 figure 25 grayscale palette control instruction rk154C00: specify the grayscale level for 16-palettes from the 24-grayscale level. for details, see the grayscale palette and grayscale palette table sections.
table 17 instruction list reg. upper code lower code no. register name r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 description ir index 0 0 *********id6id5id4id3id2id1id0sets the i ndex register value. 0 sr status read 1 0 l7 l6 l5 l4 l3 l2 l1 l0 0 c6 c5 c4 c3 c2 c1 c0 reads the driving raster-row position (l7-0) and contrast setting (c6-0). 0 r00h start oscillation 0 1 ***************1starts the oscillation mode. 10 ms device code read 110000011101100011 reads 0765h. 0 r01h driver output control 01000000cmssgs000nl4nl3nl2nl1nl0 sets the common driver shift direction ( cms ) , se g ment driver shift 0 direction (sgs), and driving duty ratio (nl4-0). r02h lcd-driving-waveform 01000000b/ceor00nw5nw4nw3nw2nw1nw0 sets the lcd drive ac waveform ( b/c ) , eor output ( eor ) , and the 0 control number of n-raster-rows ( nw5-0 ) at c-pattern ac drive. r03h power control 1 0 1 0 bs2 bs1 bs0 bt3 bt2 bt1 bt0 0 dc2 dc1 dc0 ap1 ap0 slp stb sets the standby mode (stb), lcd power on (ap1-0), 0 sleep mode (slp), boosting cycle (dc2-0), boosting ouput multiplying factor (bt3-0), and lcd drive bias value (bs2-0). r04h contrast control 010000vr3vr2vr1vr00ct6ct5ct4ct3ct2ct1ct0 sets the contrast adjustment (ct6-0) and regulator adjustment (vr3-0). 0 r05h entry mode 01000000hwm000i/d1i/d0amlg2lg1lg0 specifies the logical operation (lg2-0), ac counter mode (am), increment/ 0 decrement mode (i/d1-0) and high-speed-write mode (hwm). r06h compare register 0100000000cp7cp6cp5cp4cp3cp2cp1cp0sets the compare register (cp7-0). 0 r07h display control 0100000 vle2 vle1 spt 00000revd1d0 specifies display on (d1-0), reversed display (rev), ,screen division driving 0 (spt), and vertical scroll (vle2-1). r0ah com driver interface control 010000000te00000 idx2 idx1 idx0 specifies the serial transfer enable (te) and index for the com transfer 0 110000000te00000 idx2 idx1 idx0 instructions (idx2-0). 0 r0bh frame cycle control 01000000div1div00000 rtn3 rtn2 rtn1 rtn0 sets the line retrace period (rtn3-0) and operating clock frequency-division ratio (div1-0) 0 r0ch power control 2 010000000000000vc2vc1vc0sets an adjust ment factor for the vci voltage (vc2-0). 0 r11h vertical scroll control 0 1 vl27 vl26 vl25 vl24 vl23 vl22 vl21 vl20 vl17 vl16 vl15 vl14 vl13 vl12 vl11 vl10 specifies the 1st-screen display-start raster-row (vl17-10) a nd 2nd- 0 screen display-start raster-row (vl27-20). r14h 1st screen driving position 0 1 se17 se16 se15 se14 se13 se12 se11 se10 ss17 ss16 ss15 ss14 ss13 ss12 ss11 ss10 sets 1st-screen driving start (ss17-10) and end (se17-10). 0 r15h 2nd screen driving position 0 1 se27 se26 se25 se24 se23 se22 se21 se20 ss27 ss26 ss25 ss24 ss23 ss22 ss21 ss20 sets 2nd-screen driving start (ss27-20) and end (se27-20). 0 r16h horizontal ram address position 0 1 hea7 hea6 hea5 hea4 hea3 hea2 hea1 hea0 hsa7 hsa6 hsa5 hsa4 hsa3 hsa2 hsa1 hsa0 sets the start (hsa7-0) and end (hea7-0) of the horizontal ram address range. 0 r17h vertical ram address position 0 1 vea7 vea6 vea5 vea4 vea3 vea2 vea1 vea0 vsa7 vsa6 vsa5 vsa4 vsa3 vsa2 vsa1 vsa0 sets the start (vsa7-0) and end (vea7-0) of the vertical ram address range. 0 r20h ram write data mask 010000wmwmwm9wm8wm7wm6wm5wm4wm3wm2wm1wm0 specifies write data mask (wm15-0) at ram write. 0 11 10 r21h ram address set 0 1 ad15-8 (upper) ad7-0 (lower) initially sets the ram address to the address counter (ac). 0 r22h write data to gram 0 1 write data (upper) write data (lower) write data to ram. 0 write data from gram 1 1 read data (upper) read data (lower) read data from ram. 0 r30h grayscale palette control (1) 01000 pk14 pk13 pk12 pk11 pk10 0 0 0 pk04 pk03 pk02 pk01 pk00 specifies the grayscale palette. 0 r31h grayscale palette control (2) 01000 pk34 pk33 pk32 pk31 pk30 0 0 0 pk24 pk23 pk22 pk21 pk20 specifies the grayscale palette. 0 r32h grayscale palette control (3) 01000 pk54 pk53 pk52 pk51 pk50 0 0 0 pk44 pk43 pk42 pk41 pk40 specifies the grayscale palette. 0 r33h grayscale palette control (4) 01000 pk74 pk73 pk72 pk71 pk70 0 0 0 pk64 pk63 pk62 pk61 pk60 specifies the grayscale palette. 0 r34h grayscale palette control (5) 01000 pk94 pk93 pk92 pk91 pk90 0 0 0 pk84 pk83 pk82 pk81 pk80 specifies the grayscale palette. 0 r35h grayscale palette control (6) 01000 pk114 pk113 pk112 pk111 pk110 0 0 0 pk104 pk103 pk102 pk101 pk100 specifies the grayscale palette. 0 r36h grayscale palette control (7) 01000 pk134 pk133 pk132 pk131 pk130 0 0 0 pk124 pk123 pk122 pk121 pk120 specifies the grayscale palette. 0 r37h grayscale palette control (8) 01000 pk154 pk153 pk152 pk151 pk150 0 0 0 pk144 pk143 pk142 pk141 pk140 specifies the grayscale palette. 0 note: 1. '*' means 'doesn't matter'. 2. after setting te = 1, 18 (max.) clock cycles are required for a serial transfer to be completed. during that time, do not change the bits of instructions which are to be transferred. 3. high-speed write mode is available only for the ram writing. execu-tion cycle hitachi 33
hd66765 34 preliminary specification reset function the hd66765 is internally initialized by reset input. reset the common driver as its settings are not automatically reinitialized when the hd66765 is reset. the reset input must be held for at least 1 ms. do not access the gram or initially set the instructions until the r-c oscillation frequency is stable after power has been supplied (10 ms). instruction set initialization: 1. start oscillation executed 2. driver output control (nl4C0 = 10101, sgs = 0, cms = 0) 3. b-pattern waveform ac drive (b/c = 0, ecr = 0, nw5C0 = 00000) 4. power control 1 (dc2C0 = 000, ap1C0 = 00: lcd power off, stb = 0: standby mode off, slp = 0, bs2-0 = 000, bt2-0 = 000) 5. contrast control (weak contrast (vr3-0 = 0000, ct6C0 = 0000000)) 6. entry mode set (hwm = 0, i/d1-0 = 11: increment by 1, am = 0: horizontal move, lg2C0 = 000: replace mode) 7. compare register (cp7C0: 00000000) 8. display control (vle2C1 = 00: no vertical scroll, spt = 0, rev = 0, d1C0 = 00: display off) 9. com driver interface control (te = 0, idx2-0 = 000) 10. frame cycle control (div1-0 = 00: 1-divided clock, rtn2-0: no retrace line period) 11. power control 2 (vc2-0 = 000) 12. vertical scroll (vl27C20 = 00000000, vl17C10 = 00000000) 13. 1st screen division (se17-10 = 11111111, ss17-10 = 00000000) 14. 2nd screen division (se27-20 = 11111111, ss27-20 = 00000000) 15. horizontal ram address position (hea7-0 = 00111111, hsa7-0 = 000000) 16. vertical ram address position (vea7-0 = 10101111, vsa7-0 = 00000000) 17. ram write data mask (wm11C0 = 000h: no mask) 18. ram address set (ad15C0 = 0000h) 19. grayscale palette pk04C00 = 00000, pk14C10 = 00010, pk24C20 = 00100, pk34C30 = 00110, pk44C40 = 00111, pk54C50 = 01000, pk64C60 = 01001, pk74C70 = 01010, pk84C80 = 01011, pk94C90 = 01100, pk104C100 = 01101, pk114C110 = 01110, pk124C120 = 10000, pk134C130 = 10010, pk144C140 = 10101, pk154C150 = 10111 gram data initialization: this is not automatically initialized by reset input but must be initialized by software while display is off (d1C0 = 00). output pin initialization: 1. lcd driver output pins (seg/com): output gnd level 2. oscillator output pin (osc2): outputs oscillation signal 3. common interface signals (ccs*, ccl, and cda): halt 4. timing signals (cl1, m, flm, disptmg, and dcclk): halt
hd66765 35 preliminary specification parallel data transfer 16-bit bus interface setting the im2/1/0 (interface mode) to the gnd/gnd/gnd level allows 68-system e-clock- synchronized 16-bit parallel data transfer. setting the im2/1/0 to the gnd/vcc/gnd level allows 80- system 16-bit parallel data transfer. when the number of buses or the mounting area is limited, use an 8- bit bus interface. csn* a1 hwr* (rd*) d15-d0 cs* rs wr* (rd*) db15-db0 h8/2245 hd66765 16 figure 26 interface to 16-bit microcomputer 8-bit bus interface setting the im2/1/0 (interface mode) to the gnd/gnd/vcc level allows 68-system e-clock-synchronized 8-bit parallel data transfer using pins db15Cdb8. setting the im1/0 to the vcc/vcc level allows 80- system 8-bit parallel data transfer. the 16-bit instructions and ram data are divided into eight upper/lower bits and the transfer starts from the upper eight bits. fix unused pins db7Cdb0 to the vcc or gnd level. note that the upper bytes must also be written when the index register is written to. csn* a1 hwr* (rd*) d15-d8 cs* rs wr* (rd*) db15-db8 db7-0 h8/2245 hd66765 8 8 gnd figure 27 interface to 8-bit microcomputer note: transfer synchronization function for an 8-bit bus interface the hd66765 supports the transfer synchronization function which resets the upper/lower counter to count upper/lower 8-bit data transfer in the 8-bit bus interface. noise causing transfer mismatch between the eight upper and lower bits can be corrected by a reset triggered by consecutively writing a 00h instruction four times. the next transfer starts from the upper eight bits. executing synchronization function periodically can recover any runaway in the display system.
hd66765 36 preliminary specification rs r/w e "00"h upper or lower upper 8-bit transfer syhchronization lower (1) (2) (3) (4) "00"h "00"h "00"h db15-db8 figure 28 8-bit transfer synchronization
hd66765 37 preliminary specification serial data transfer setting the im1 pin to the gnd level and the im2 pin to the vcc level allows standard clock- synchronized serial data (spi) transfer, using the chip select line (cs*), serial transfer clock line (scl), serial input data (sdi), and serial output data (sdo). for a serial interface, the im0/id pin function uses an id pin. if the chip is set up for serial interface, the db15-2 pins which are not used must be fixed at vcc or gnd. the hd66765 initiates serial data transfer by transferring the start byte at the fa lling edge of cs* input. it ends serial data transfer at the rising edge of cs* input. the hd66765 is selected when the 6-bit chip address in the start byte transferred from the transm itting device matches the 6-bit device identification code assigned to the hd66765. the hd66765, when selected, receives the subsequent data string. the least significant bit of the identification code can be determined by the id pin. the five upper bits must be 01110. two different chip addresses must be assigned to a single hd66765 because the seventh bit of the start byte is used as a register select bit (rs): that is, when rs = 0, data can be written to the index register or status can be read, and when rs = 1, an instruction can be issued or data can be written to or read from ram. read or write is selected according to the eighth bit of the start byte (r/w bit). the data is received when the r/w bit is 0, and is transmitted when the r/w bit is 1. after receiving the start byte, the hd66765 receives or transmits the subsequent data byte-by-byte. the data is transferred with the msb first. all hd66765 instructions are 16 bits. two bytes are received with the msb f ir st (db15 to 0), then the instruc tions ar e inte rnally e xec ute d. afte r the star t byte has be en received, the first byte is fetched internally as the upper eight bits of the instruction and the second byte is fetched internally as the lower eight bits of the instruction. four bytes of ram read data after the start byte are invalid. the hd66765 starts to read correct ram data from the fifth byte. table 18 start byte format transfer bit s 1 2 3 4 5 6 7 8 start byte format transfer start device id code rs r/w 011 10id note: id bit is selected by the im0/id pin. table 19 rs and r/w bit function rs r/w function 0 0 sets index register 0 1 reads status 1 0 writes instruction or ram data 1 1 reads instruction or ram data
hd66765 38 preliminary specification 1 "0" "0" id rs rs rw r/w db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 "1" "1" "1" cs* (input) device id code msb lsb start byte index register setting, instruction, ram data write status read, instruction read, ram data read transfer start transfer end scl (input) sdi (input) sdo (output) 2 3 4 5 6 7 8 9 10 11 12 13 14 21 22 23 24 15 16 17 18 19 20 a) timing of basic data-transfer through clock-synchronized serial bus interface 12345 6 78 91011121314 21222324 15 16 1718 19 20 31 32 25 26 2728 29 30 cs* (input) scl (input) start byte note: the first byte after the start byte is always the upper eight bits. instruction 1: execution time end start instruction 1: upper eight bits sdi (input) instruction 2: upper eight bits instruction 1: lower eight bits b) timing of consecutive data-transfer through clock-synchronized serial bus interface cs* (input) scl (input) start byte rs = 1, r/w = 1 note: five bytes of the ram read data after the start byte are invalid. the hd66765 starts to read the correct ram data from the sixth byte. sdi (input) dummy read 1 dummy read 2 dummy read 3 dummy read 4 dummy read 5 ram read: upper eight bits ram read: lower eight bits c) ram-data read-transfer timing sdo (output) start end figure 29 procedure for transfer on clock-synchronized serial bus interface
hd66765 39 preliminary specification cs* (input) scl (input) start byte rs = 0, r/w = 1 note: one byte of the read data after the start byte are invalid. the hd66765 starts to read the correct data from the second byte. sdi (input) sdo (output) start end dummy read 1 status read: upper eight bits status read: lower eight bits d) status read/instruction read figure 29 procedure for transfer on clock-synchronized serial bus interface (cont)
hd66765 40 preliminary specification high-speed burst ram write function the hd66765 has a high-speed burst ram-write function that can be used to write data to ram in one- fourth the access time required for an equivalent standard ram-write operation. this function is especially suitable for applications which require the high-speed rewriting of the display data, for example, display of color animations, etc. when the high-speed ram-write mode (hwm) is selected, data for writing to ram is once stored to the hd66765 internal register. when data is selected four times per word, all data is written to the on-chip ram. while this is taking place, the next data can be written to an internal register so that high-speed and consecutive ram writing can be executed for animated displays, etc. microcomputer register 1 "0000"h "0001"h "0002"h "0003"h 16 12 register 2 gram register 3 register 4 address counter (ac) 48 figure 30 flow of operation in high-speed consecutive writing to ram cs* (input) e (input) index (r22h) index (r22h) ram data 1 to 4 "0000"h "0004"h "0008"h "000a"h ram write data (64 bits) ram address (ac15 to 0) ram data 1 ram data 2 ram data 3 ram data 4 123412341234 ram data 5 ram data 6 ram data 7 ram data 8 ram data 9 ram data 10 ram data 11 ram data 12 note: when a high-speed ram write is canceled, the next instruction must only be executed after the ram write execution time has elapsed. the lower two bits of the address must be set in the following way in high-speed write mode. when id0 becomes 0, the lower two bits of the address must be set to 11 when id1 becomes 1, the lower two bits of the address must be set to 00. ram write execution time db15-0 (input/output) ram write execution time ram write execution time ram data 5 to 8 ram data 9 to 12 * figure 31 example of the operation of high-speed consecutive writing to ram
hd66765 41 preliminary specification when high-speed ram write mode is used, note the following. notes: 1. the logical and compare operations cannot be used. 2. data is written to ram each four words. when an address is set, the lower two bits in the address must be set to the following values. *when id0=0, the lower two bits in the address must be set to 11 and be written to ram. *when id0=1, the lower two bits in the address must be set to 00 and be written to ram. 3. data is written to ram each four words. if less than four words of data is written to ram, the last data will not be written to ram. 4. when the index register and ram data write (r22h) have been selected, the data is always written first. ram cannot be written to and read from at the same time. hwm must be set to 0 while ram is being read. 5. high-speed and normal ram write operations cannot be executed at the same time. the mode must be switched and the address must then be set. 6. when high-speed ram write is used with a window address-range specified, dummy write operation may be required to suit the window address range-specification. refer to the high- speed ram write in the window address section. table 20 comparison between normal and high-speed ram write operations normal ram write (hwm=0) high-speed ram write (hwm=1) logical operation function can be used cannot be used compare operation function can be used cannot be used swap function can be used can be used write mask function can be used can be used ram address set can be specified by word id0 bit=0: set the lower two bits to 11 id0 bit=1: set the lower two bits to 00 ram read can be read by word cannot be used ram write can be written by word dummy write operations may have to be inserted according to a window address- range specification window address can be set by word can be set by word
hd66765 42 preliminary specification high-speed ram write in the window address when a window address range is specified, ram data which is in an optional window area can be rewritten consecutively and quickly by inserting dummy write operations so that ram access c ounts become 4n as shown in the tables below. dummy write operations may have to be inserted as the first or last operations for a row of data, depending on the horizontal window-address range specification bits (hsa1 to 0, hea1 to 0). number of dummy write operations of a row must be 4n. table 21 number of dummy write operations in high-speed ram write (hsa bits) hsa1 hsa0 number of dummy write operations to be inserted at the start of a row 00 0 01 1 10 2 11 3 table 22 number of dummy write operations in high-speed ram write (hea bits) hea1 hea0 number of dummy write operations to be inserted at the end of a row 00 3 01 2 10 1 11 0 each row of access must consist of 4 n operations, including the dummy writes. horizontal access count = first dummy write count + write data count + last dummy write count = 4 n
hd66765 43 preliminary specification an example of high-speed ram write with a window address-range specified is shown below. the window address-range can be rewr itten to consecutively and quickly by inserting two dummy writes at the start of a row and three dummy writes at the end of a row, as determined by using the window address-range specification bits (hsa1 to 0 = 10, hea1 to 0 = 00). writing in the horizontal direction am = 0, id0 = 1 window address-range setting hsa = "12"h, hea = "30"h vsa = "80"h, vea = "a0"h high-speed ram write mode setting hwm = 1 address set ad = "8010"h * dummy ram write 2 dummy ram write 3 "0000"h gram address map "8012"h "a030"h "a083"h window address-range specification (rewrite area) window address-range setting hsa = "12"h, hea = "30"h vsa = "80"h, vea = "a0"h note: the address set for the high-speed ram write must be 00 or 11 according to the value of the id0 bit. only ram in the specified window address-range will be overwritten. ram write 31 152 figure 32 example of the high-speed ram write with a window address-range specification
hd66765 44 preliminary specification window address function when data is written to the on-chip gram, a wi ndow address-range which is specified by the horizontal address register (start: hsa7-0, end: hea7-0) or the vertical address register (start: vsa7-0, end: vea7-0) can be written to consecutively. data is written to addresses in the direction specified by the am bit (increment/decrement). when image data, etc. is being written, data can be written consecutively without thinking a data wrap by doing this. the window must be specified to be within the gram address area described below. addresses must be set within the window address. [restriction on window address-range settings] (horizontal direction) 00h hsa7-0 hea7-0 3fh (vertical direction) 00h vsa7-0 vea7-0 afh [restriction on address settings during the window address] (ram address) hsa5 to 0 ad7-0 hea7-0 vsa7-0 ad15-8 vea7-0 note: in high-speed ram-write mode, the lower two bits of the address must be set as shown below according to the value of the id0 bit. id0 = 0: the lower two bits of the address must be set to 11. id0 = 1: the lower two bits of the address must be set to 00.
hd66765 45 preliminary specification gram address map "2010"h "2110"h "202f"h "212f"h window address-range specification area hsa7-0 = "10"h, hse7-0 = "2f"h vsa7-0 = "20"h, vea7-0 = "5f"h i/d = "1" (increment) am = "0" (horizontal writing) "5f2f"h "5f10"h "0000"h "0083"h "af83"h "af00"h window address area figure 33 example of address operation in the window address specification
hd66765 46 preliminary specification graphics operation function the hd66765 can greatly reduce the load of the microcomputer graphics software processing through the 16-bit bus architecture and internal graphics-bit operation function. this function supports the following: 1. a write data mask function that selectively rewrites some of the bits in the 12-bit write data. 2. a logical operation write function that writes the data sent from the microcomputer and the original ram data by a logical operation. 3. a conditional write function that compares the original ram data or write data and the compare- bit data and writes the data sent from the microcomputer only when the conditions match. even if the display size is large, the display data in the graphics ram (gram) can be quickly rewritten. the graphics bit operation can be controlled by combining the entry mode register, the bit set value of the ram-write-data mask register, and the read/write from the microcomputer. table 23 graphics operation bit setting operation mode i/d am lg2C0 operation and usage write mode 1 0/1 0 000 horizontal data replacement, horizontal-border drawing write mode 2 0/1 1 000 vertical data replacement, vertical-border drawing write mode 3 0/1 0 110 111 conditional horizontal data replacement, horizontal- border drawing write mode 4 0/1 1 110 111 conditional vertical data replacement, vertical-border drawing read/write mode 1 0/1 0 001 010 011 horizontal data write with logical operation, horizontal-border drawing read/write mode 2 0/1 1 001 010 011 vertical data write with logical operation, vertical- border drawing read/write mode 3 0/1 0 100 101 conditional horizontal data replacement, horizontal- border drawing read/write mode 4 0/1 1 100 101 conditional vertical data replacement, vertical-border drawing
hd66765 47 preliminary specification read-data latch logical/compare operation (lg2e0:) write bit mask write-data latch graphics ram (gram) 000: replacement, 001: or, 010: and, 011: eor, 100: replacement with matched read, 101: replacement with unmatched read, 110: replacement with matched write, 111: replacement with unmatched write microcomputer address counter (ac) logical operation bit (lg2e0) 3 16 12 write-mask register (wm11e0) 12 16 +1/-1 +256 12 12 12 compare bit (cp11e0) 12 figure 34 data processing flow of the graphics operation
hd66765 48 preliminary specification write-data mask function the hd66765 has a bit-wise write-data mask function that controls writing the two-byte data from the microcomputer to the gram. bits that are 0 in the write-data mask register (wm11C0) cause the corresponding db bit to be written to the gram. bits that are 1 prevent writing to the corresponding gram bit to the gram; the data in the gram is retained. this function can be used when only one- pixel data is rewritten or the particular display color is selectively rewritten. db11 db0 gram data data written by the microcomputer r 03 r 02 r 01 r 00 g 03 g 02 g 01 g 00 b 03 b 02 b 01 b 00 g 03 g 02 g 01 b 01 b 00 db11 db0 write-data mask 1 1 1 1 1 1 1 0 0 0 0 0 db11 db0 * * * * * * * figure 35 example of write-data mask function operation
hd66765 49 preliminary specification logical/compare operation function the hd66765 performs a logical operation or conditional replacement between the two-byte write data sent from the microcomputer and the read data from the gram. the logical operation function has four types: replacement, or, and, and eor. the conditional replacement performs a compare operation for the set value of the compare register (cp11C0) and the read data value from the gram, and rewrites only the pixel data in the gram that satisfies the conditions (in a byte unit). this function can be used when a particular color is selectively rewritten. the swap function or write-data mask function can be effectively used. table 24 logical/compare operation bit setting lg2 lg1 lg0 description of logical/compare operation function 0 0 0 writes the data written from the microcomputer directly to the gram. only write processing is performed since the data in the read-data latch is not used. 0 0 1 ors the data in the read-data latch and the data written by the microcomputer. writes the result to gram. read, modify, or write processing is performed. 0 1 0 ands the data in the read-data latch and the data written by the microcomputer. writes the result to gram. 0 1 1 eors the data in the read-data latch and the data written by the microcomputer. writes the result to gram. 1 0 0 compares the data in the read-data latch and the set value of the compare register (cp11C0). when the read data matches cp11C0, the data from the microcomputer is written to the gram. only the particular color specified in the compare register can be rewritten. read, modify, or write processing is performed. 1 0 1 compares the data in the read-data latch and the set value of the compare register (cp11C0). when the read data does not match cp11C0, the data from the microcomputer is written to the gram. colors other than the particular one specified in the compare register can be rewritten. read, modify, or write processing is performed. 1 1 0 compares the data written to the gram by the microcomputer and the set value of the compare register (cp11C0). when the write data matches cp11C0, the data from the microcomputer is written to the gram. only write processing is performed. 1 1 1 compares the data written to the gram by the microcomputer and the set value of the compare register (cp11C0). when the write data does not match cp11C0, the data from the microcomputer is written to the gram. only write processing is performed.
hd66765 50 preliminary specification graphics operation processing 1. write mode 1: am = 0, lg2C0 = 000 this mode is used when the data is horizontally written at high speed. it can also be used to initialize the graphics ram (gram) or to draw borders. the write-data mask function (wm11C0) is also enabled in these operations. after writing, the address counter (ac) automatically increments by 1 (i/d = 1) or decrements by 1 (i/d = 0), and automatically jumps to the counter edge one-raster-row below after it has reached the left or right edge of the gram. operation examples: 1) i/d = "1", am = "0", lg2-0 = "000" 2) wm11e0 = "0ff"h 3) ac = "0000"h write-data mask: 0 db11 db0 00011111111 1 db11 db0 00110010100 110000110000 write data (1): write data (2): "0000"h "0001"h "0002"h write data (1) write data (2) gram *write mask for plain and . note: the bits in the gram indicated by '*' are not changed. 1001 ******** 1100 ******** figure 36 writing operation of write mode 1
hd66765 51 preliminary specification 2. write mode 2: am = 1, lg2C0 = 000 this mode is used when the data is vertically written at high speed. it can also be used to initialize the gram, develop the font pattern in the vertical direction, or draw borders. the write-data mask function (wm11C0) is also enabled in these operations. after writing, the address counter (ac) automatically increments by 256, and automatically jumps to the upper-right edge (i/d = 1) or upper- left edge (i/d = 0) following the i/d bit after it has reached the lower edge of the gram. operation examples: 1) i/d = "1", am = "1", lg2-0 = "000" 2) wm11e0 = "0ff"h 3) ac = "0000"h write-data mask: 0 db11 db0 00011111111 1 db11 db0 00110010100 110000110000 write data (1): write data (2): 011101000001 011101000001 write data (3): "0000"h "0001"h "0002"h write data (1) write data (3) write data (2) gram note: 1001 ******** 1100 ******** 1. the bits in the gram indicated by '*' are not changed. 2. after writin to address "af00"h, the ac jumps to "0001"h. figure 37 writing operation of write mode 2
hd66765 52 preliminary specification 3. write mode 3: am = 0, lg2C0 = 110/111 this mode is used when the data is horizontally written by comparing the write data and the set value of the compare register (cp11C0). when the result of the comparison in a byte unit satisfies the condition, the write data sent from the microcomputer is written to the gram. in this operation, the write-data mask function (wm11C0) is also enabled. after wr iting, the address counter (ac) automatically increments by 1 (i/d = 1) or decrements by 1 (i/d = 0), and automatically jumps to the counter edge one-raster-row below after it has reached the left or right edge of the gram. operation examples: 1) i/d = "1", am = "0", lg2-0 = "110" (matched write) 2) cp11e0 = "530"h 3) wm11e0 = "000"h 4) ac = "0000"h write-data mask: 0 db11 db0 000 0000 0000 compare register: 0 db11 db0 compare operaton conditional replacement replacement (matched) conditional replacement compare operaton 101 0011 0000 010100110000 010100110000 ************ 000011110000 write data (1): write data (2): "0000"h "0001"h "0002"h matched replacement of write data (1) gram 010100110000 ************ c c r r figure 38 writing operation of write mode 3
hd66765 53 preliminary specification 4. write mode 4: am = 1, lg2C0 = 110/111 this mode is used when a vertical comparison is performed between the write data and the set value of the compare register (cp11C0) to write the data. when the result by the comparison in a byte unit satisfies the condition, the write data sent from the microcomputer is written to the gram. in this operation, the write-data mask function (wm11C0) are also enabled. after wr iting, the address counter (ac) automatically increments by 256, and automatically jumps to the upper-right edge (i/d = 1) or upper-left edge (i/d = 0) following the i/d bit after it has reached the lower edge of the gram. operation examples: 1) i/d = "1", am = "1", lg2-0 = "111" (unmatched write) 2) cp11e0 = "530"h 3) wm11e0 = "000"h 4) ac = "0000"h write-data mask: 0 db11 db0 000 0000 0000 compare register: 0 db11 db0 compare operaton conditional replacement (unmatched) (matched) conditional replacement compare operaton 101 0011 0000 100110011001 100110011001 ************ 010100110000 write data (1): write data (2): "0000"h "0001"h "af00"h write data (1) gram 100110011001 ************ c c r r figure 39 writing operation of write mode 4
hd66765 54 preliminary specification 5. read/write mode 1: am = 0, lg2C0 = 001/010/011 this mode is used when the data is horizontally written at high speed by performing a logical operation with the original data. it reads the display data (original data), which has already been written in the gram, performs a logical operation with the write data sent from the microcomputer, and rewrites the data to the gram. this mode reads the data during the same access-pulse width (68-system: enabled high level, 80-system: rd* low level) as the write operation since reading the original data does not latch the read data into the microcomputer but temporarily holds it in the read- data latch. however, the bus cycle requires the same time as the read operation. the write-data mask function (wm11C0) is also enabled in these operations. after wr iting, the address counter (ac) automatically increments by 1 (i/d = 1) or decrements by 1 (i/d = 0), and automatically jumps to the counter edge one-raster-row below after it has reached the left or right edges of the gram. operation examples: 1) i/d = "1", am = "0", lg2-0 = "001" (logical or) 2) wm11e0 = "000"h 3) ac = "0000"h write-data mask: 0 db11 db0 000 0000 0000 read data (1): 1 db11 db0 logical operation (or) logical operation (or) 001 1001 0100 101111000110 101111010110 101111010110 110011111000 110011111000 000011110000 write data (1): read data (2): 110000111000 write data (2): "0000"h "0001"h "0002"h read data (1) + write data (1) read data (2) + write data (2) gram figure 40 writing operation of read/write mode 1
hd66765 55 preliminary specification 6. read/write mode 2: am = 1, lg1C0 = 001/010/011 this mode is used when the data is vertically written at high speed by performing a logical operation with the original data. it reads the display data (original data), which has already been written in the gram, performs a logical operation with the write data sent from the microcomputer, and rewrites the data to the gram. this mode can read the data during the same access-pulse width (68-system: enabled high level, 80-system: rd* low level) as for the write operation since the read operation of the original data does not latch the read data into the microcomputer and temporarily holds it in the read-data latch. however, the bus cycle requires the same time as the read operation. the write-data mask function (wm11C0) is also enabled in these operations. after writing, the address counter (ac) automatically increments by 256, and automatically jumps to the upper-right edge (i/d = 1) or upper- left edge (i/d = 0) following the i/d bit after it has reached the lower edge of the gram. operation examples: 1) i/d = "1", am = "1", lg2-0 = "001" (logical or) 2) wm11e0 = "ff0"h 3) ac = "0000"h write-data mask: 1 db11 db0 111 1111 0000 read data (1): 1 db11 db0 logical operation (or) logical operation (or) 000 1001 0101 101111000110 101111010111 ******** 0111 110011111000 ******** 1000 000011110000 write data (1): read data (2): 110000111000 write data (2): "0000"h "0001"h "af00"h read data (1) + write data (1) read data (2) + write data (2) gram note: 1. the bits in the gram indicated by '*' are not changed. 2. after writin to address "af00"h, the ac jumps to "0001"h. figure 41 writing operation of read/write mode 2
hd66765 56 preliminary specification 7. read/write mode 3: am = 0, lg2C0 = 100/101 this mode is used when the data is horizontally written by comparing the original data and the set value of compare register (cp11C0). it reads the display data (original data), which has already been written in the gram, compares the original data and the set value of the compare register in byte units, and writes the data sent from the microcomputer to the gram only when the result of the comparison satisfies the condition. this mode reads the data during the same access-pulse width (68- system: enabled high level, 80-system: rd* low level) as write operation since reading the original data does not latch the read data into the microcomputer but temporarily holds it in the read-data latch. however, the bus cycle requires the same time as the read operation. the write-data mask function (wm11C0) is also enabled in these operations. after wr iting, the address counter (ac) automatically increments by 1 (i/d = 1) or decrements by 1 (i/d = 0), and automatically jumps to the counter edge one-raster-row below after it has reached the left or right edges of the gram. operation examples: 1) i/d = "1", am = "0", lg2-0 = "100" (matched write) 2) cp11e0 = "530"h 3) wm11e0 = "000"h 4) ac = "0000"h write-data mask: 0 db11 db0 000 0000 0000 compare register: 0 db11 db0 compare operaton (matched) conditional replacement 101 0011 0000 0101 0011 0000 101111000110 101111000110 101111000110 read data (1): write data (1): "0000"h "0001"h matched replacement write data (1) gram c r compare operaton conditional replacement 000011110000 000011110000 000011110000 110000111000 read data (2): write data (2): c r figure 42 writing operation of read/write mode 3
hd66765 57 preliminary specification 8. read/write mode 4: am = 1, lg2C0 = 100/101 this mode is used when the data is vertically written by comparing the original data and the set value of the compare register (cp11C0). it reads the display data (original data), which has already been written in the gram, compares the original data and the set value of the compare register in byte units, and writes the data sent from the microcomputer to the gram only when the result of the compare operation satisfies the condition. this mode reads the data during the same access-pulse width (68-system: enabled high level, 80-system: rd* low level) as the write operation since reading the original data does not latch the read data into the microcomputer but temporarily holds it in the read-data latch. however, the bus cycle requires the same time as the read operation. the write-data mask function (wm11C0) is also enabled in these operations. after writing, the address counter (ac) automatically increments by 256, and automatically jumps to the upper-right edge (i/d = 1) or upper- left edge (i/d = 0) following the i/d bit after it has reached the lower edge of the gram. operation examples: 1) i/d = "1", am = "1", lg2-0 = "101" (ummatched write) 2) cp11e0 = "530"h 3) wm11e0 = "000"h 4) ac = "0000"h write-data mask: 0 db11 db0 000 0000 0000 compare register: 0 db11 db0 compare operaton (unmatched) conditional replacement 101 0011 0000 1001 1001 0101 101111000110 101111000110 101111000110 read data (1): write data (1): "0000"h "0001"h "af00"h write data (1) write data (2) gram c r compare operaton conditional replacement 010100110000 010100110000 010100110000 110000111000 read data (2): write data (2): c r note: 1. the bits in the gram indicated by '*' are not changed. 2. after writin to address "af00"h, the ac jumps to "0001"h. figure 43 writing operation of read/write mode 4
hd66765 58 preliminary specification grayscale palette the hd66765 incorporates a grayscale palette to simultaneously display 4,096 out of 13,824 possible colors. the grayscales consist of sixteen five-bit palettes. the 24-stage grayscale levels can be selected from the five-bit palette data. in this palette, a pulse-width control system (pwm) is used to eliminate flicker in the lcd display. the time over which the lcds are switched on is adjusted according to the level and grayscales are displayed so that flicker is reduced and grayscales are clearly displayed. display data "0000" palette graphics ram (gram) msb lsb pk 03 pk 02 pk 01 pk 03 4 "0001" pk 13 pk 12 pk 11 rk 13 "0010" pk 23 pk 22 pk 21 pk 23 "0011" pk 33 pk 32 pk 31 pk 33 "0100" pk 43 pk 42 pk 41 pk 43 "0101" pk 53 pk 52 pk 51 pk 53 "0110" pk 63 pk 62 pk 61 pk 63 "0111" pk 73 pk 04 pk 14 pk 24 pk 34 pk 44 pk 54 pk 64 pk 74 pk 72 pk 71 pk 73 pk 83 pk 82 pk 81 pk 80 pk 93 pk 92 pk 91 rk 90 pk10 3 pk 102 pk 101 pk 100 pk 113 pk 112 pk 111 pk 110 pk 123 pk 122 pk 121 pk 120 pk 133 pk 132 pk 131 pk 130 pk 143 pk 142 pk 141 pk 140 pk 153 pk 84 pk 94 pk 104 pk 114 pk 124 pk 134 pk 144 pk 154 pk 152 pk 151 pk 150 "1000" "1001" "1010" "1011" "1100" "1101" "1110" "1111" 24 grayscale ontrol < r > lcd lcd driver 24 grayscale ontrol < g > lcd driver 24 grayscale ontrol < b > lcd driver rg b r 1 r 2 r 0 g 3 g 2 g 1 g 0 b 1 b 0 r 3 b 3 b 2 4 4 5 5 5 figure 44 grayscale palette control
hd66765 59 preliminary specification grayscale palette table the grayscale register that is set for the rgb palette register (pk) can be set to any level. 24-grayscale lighting levels can be set according to palette values (00000 to 10111). table 25 grayscale control level palette register value (pk) grayscale control level 0 0 0 0 0 unlit level *1 0 0 0 0 1 2/24 level 0 0 0 1 0 3/24 level 0 0 0 1 1 4/24 level 0 0 1 0 0 5/24 level 0 0 1 0 1 6/24 level 0 0 1 1 0 7/24 level 0 0 1 1 1 8/24 level 0 1 0 0 0 9/24 level 0 1 0 0 1 10/24 level 0 1 0 1 0 11/24 level 0 1 0 1 1 12/24 level 0 1 1 0 0 13/24 level 0 1 1 0 1 14/24 level 0 1 1 1 0 15/24 level 0 1 1 1 1 16/24 level 1 0 0 0 0 17/24 level 1 0 0 0 1 18/24 level 1 0 0 1 0 19/24 level 1 0 0 1 1 20/24 level 1 0 1 0 0 21/24 level 1 0 1 0 1 22/24 level 1 0 1 1 0 23/24 level 1 0 1 1 1 all-lit level *2 notes: 1. the unlit level corresponds to a black display when a normally-black color-lcd panel is used, and a white display when a normally-white color-lcd panel is used. 2. the all-lit level corresponds to a white display when a normally-black color-lcd panel is used, and a black display when a normally-white color-lcd panel is used.
hd66765 60 preliminary specification common driver interface the hd66765 and the hd66764 common driver can drive displays of up to 132 (rgb) 176 dots in size. signals to set instructions for cr oscillation, the display timing signal, and the common driver are supplied from the hd66765 to the common driver. the lcd drive voltage is generated by the common driver. the lcd segment drive level (vsh) is also supplied from the common driver. on/off control of the display is required to be controlled by both the common and segment driver. follow the on/off sequence of the display. seg1 to 396 (segment driver) osc1 note: the oscillation resistance (rf) must be located near the chip. osc2 vsh cl1 flm m disptmg dcclk ccs* ccl cda vsh cl1 flm m disptmg dcclk ccs* ccl cda rf hd66765 com1 to 176 (common driver) hd66764 figure 45 connection to the common driver
hd66765 61 preliminary specification common driver serial transfer the hd66765 has an on-chip serial circuit to interface with the common driver (hd66764). registers of the common driver can be set by transferring register settings from the hd66765. the serial interface consists of the seria l chip se lec t (ccs*), se rial tr ansfe r clock (ccl) , and seria l transf er data (cda ) lines. the hd66765 serial interface circuit is only for transm itting, and ca nnot be used for receiving data from the common driver. serial transfer is started by setting the serial transfer register (te) in the hd66765 to 1. after te has been set to 1, cda will be output in synchronization with ccs*, ccl, and ccl. transfer is in 16-bit blocks. the data transferred consists of a common driver index register (idx2 to 0) and an instruction for a register selected by idx2 to 0. for more information on the common driver indices and instructions, refer to the common-driver data sheet. serial transfer is independent of the hd66765 s internal operation, so other instructions can be executed during transfer. serial transfer to the common driver requires a maximum of 18 clock cycles. when the serial transfer is finished, te is automatically cleared to 0. after reading the register to confirm that te=0, serial transfer of the next instruction may be started. mpu hd66765 cs* wr* rd* ccs* ccl cda ccs* ccl cda rs db15-0 16 hd66764 a) example of interface with common driver hd66764 1 idx2 idx1 idx0 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 ccs* (output) msb lsb index instruction data transfer start transfer end cda (output) ccl (output) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 b) basic serial transfer figure 46 common driver serial transfer
hd66765 62 preliminary specification instruction setting change index set r0ah instruction read specify the idx2 to 0 in the common side instruction including a changed instruction bit common side index (idx2 to 0) te = 1 (transfer start) te = "0" no (during transfer) yes (transfer can be executed) transfer to the common driver must be executed immediately after setting up the instruction change the instruction bit setting corresponding to the hd66765 c) serial transfer sequence figure 46 common driver serial transfer (cont) notes: 1. transfer to the common driver must take place immediately after setting up the instruction. 2. the serial transfer period takes a maximum of 1/fosc 18 clock cycles (sec). 3. serial transfer cannot be executed in standby mode. if the chip enters standby mode during tra nsf er , the se rial tr ansfe r is forc ibly suspended. t ransfe r must be exe cuted aga in af te r standby has been canceled because correct transfer is not guaranteed in this situation. 4. serial transfer can be forcibly suspended by writing te=0. transfer must be executed again because correct transfer is not guaranteed in this situation. 5. the instruction bit for the common driver is not executed when it is not transferred to the common driver. when the setting is changed, transfer must be executed again. when transfer to the common driver is executed, the transfer is executed by using one of the following common driver (hd66764) instructions, corresponding to the value set by the idx2 to 0. table 26 common driver (hd66764) instructions idx2 idx1 idx0 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 slp ap0 ap1 vc0 vc1 vc2 dc1 dc0 0 bt0 bt1 bt2 0 bs1 bs0 bt3 00 bs2 0 0 0 00 0 0 0 0 0 1 0 0 ct0 ct1 ct2 vr0 vr2 vr1 ct4 ct3 ct5 ct6 0 vr3 0 0 1 0 ss10 ss11 ss12 spt d1 cms ss14 ss13 ss15 ss16 ss17 se10 se11 se12 se14 se13 se15 se16 se17 0 0 1 1 0 0 00 ss20 ss21 ss22 ss24 ss23 ss125 ss26 ss27 se20 se21 se22 se24 se23 se25 se26 se27 0 0 00 1 10 1 1 1 0 00 0 0 0 0 00 0 0
hd66765 63 preliminary specification instruction setting flow when the common driver hd66764 is used, follow the below about each instruction setting. the instruction setting for the common driver is executed by the serial interface. when the instruction for the common driver is set, the serial transfer must be executed to the common driver. the transfer to the common driver must be executed immediately after the instruction set. follow the below serial transfer flow about each setting and then transfer must be executed. [display on/off] [duty setting] [partial setting] power off (ap1 to 0 = 00) power setting partial setting duty setting, etc. display off (d1 to 0 = 00) serial transfer serial transfer serial transfer serial transfer display on (d1 to 0 = 10) display on (d1 to 0 = 11) wait at least one frame note: for more information on the flow for power settings, refer to the common-driver data sheet. [standby] display off flow oscillation start standby cancel (stb = "0") standby set (stb = "1") wait 10 ms display on flow power setting [sleep] display off flow serial transfer serial transfer sleep set (slp = "1") sleep cancel (slp = "0") display on flow power setting flow display off display on standby set standby cancel sleep set sleep cancel figure 47 instruction setting flow
hd66765 64 preliminary specification oscillation circuit the hd66765 can oscillate between the osc1 and osc2 pins using an internal r-c oscillator with an external oscillation resistor. note that in r-c oscillation, the oscillation frequency is changed according to the external resistance value, wiring length, or operating power-supply voltage. if rf is increased or power supply voltage is decrease, the oscillation frequency decreases. for the relationship between rf resistor value and oscillation frequency, see the electric characteristics notes section. clock (200 khz) osc1 osc2 hd66765 1) external clock mode damping resistance (2 k ) rf osc1 osc2 hd66765 note: the rf resistance must be located near the osc1/osc2 pin on the chip. 2) external resistance oscillation mode figure 48 oscillation circuits when using the hd66765 with the hd66764 common driver, the relationship between the seg and com output levels is as shown in the following figure. the lcd drive level (vsh, vsl) which is used by the hd66765 is supplied from the hd66764 common driver. while the display is off, seg and com outputs go to gnd level. m vch lit lit lit no lit no lit no lit seg waveform vsh vm vsl (gnd) vcl com waveform figure 49 relationship with seg/com output level
hd66765 65 preliminary specification frame-frequency adjustment function the hd66765 has an on-chip frame-frequency adjustment function. the frame frequency can be adjusted by the instruction setting (div, rtn) during the lcd drive as the oscillation frequency is always same. when the display duty is changed, the frame frequency can be adjusted to be the same. if the oscillation frequency is set to high, an animation or a static image can be displayed in suitable ways by changing the frame frequency. when a static image is displayed, the frame frequency can be set low and the low-power consumption mode can be entered. when high-speed screen switching, for an animated display, etc. is required, the frame frequency can be set high. relationship between lcd drive duty and frame frequency the relationship between the lcd drive duty and the frame frequency is calculated by the following expression. the frame frequency can be adjusted in the retrace-line period bit (rtn) and in the operation clock division bit (div) by the instruction. (formula for the frame frequency) fosc frame frequency = [hz] clock cycles per raster-row division ratio 1/duty cycle fosc: r-c oscillation frequency duty: drive duty (nl bit) division ratio: div bit clock cycles per raster-row: (rtn + 25) clock cycles
hd66765 66 preliminary specification example calculation 1 to set the maximum frame frequency to 60 hz display duty: 1/176 retrace-line period: 0 clock (rtn3 to 0 = 0000) operation clock division ratio: 1 division fosc = 60 hz (0 + 25) clock 1 division 176 lines = 264 (khz) in this case, the cr oscillation frequency becomes 264 khz. the external resistance value of the cr oscillator must be adjusted to be 264 khz. the display duty can be changed by the partial display, etc. and the frame frequency can be the same by setting the rnt bit and div bit to achieve the following. partial display display duty: 1/40 retrace-line period: 3 clock (rtn3 to 0 = 0011) operation clock division ratio: 4 division frame frequency = 264 khz/ ((3 + 25) clock 4 division 40 lines) = 58.9 (hz) example calculation 2 switching the frame frequency to suit animation/static image display (animation display) frame frequency: 90 hz display duty: 1/176 retrace-line period: 0 clock (rtn3 to 0 = 0000) operation clock division ratio: 1 division fosc = 90 hz (0 + 25) clock 1 division 176 lines = 396 (khz) (static image display) frame frequency: 60 hz display duty: 1/176 retrace-line period: 13 clock (rtn3 to 0 = 1101) operation clock division ratio: 1 division frame frequency: 396 khz/ ((13 + 25) clock 2 division 176 lines) = 59.2 (hz)
hd66765 67 preliminary specification n-raster-row reversed ac drive the hd66765 supports not only the lcd reversed ac drive in a one-frame unit (b-pattern waveform) but also the n-raster-row reversed ac drive which alternates in an n-raster-row unit from one to 64 raster- rows (c-pattern waveform). when a problem affecting display quality occurs, such as crosstalk at high- duty driving of more than 1/64 duty, the n-raster-row reversed ac drive (c-pattern waveform) can improve the quality. determine the number of raster-rows n (nw bit set value + 1) for alternating after confirmation of the display quality with the actual lcd panel. however, if the number of ac raster-rows is reduced, the lcd alternating frequency becomes high. because of this, the charge or discharge current is increased in the lcd cells. 1 2 3 4 5 6 7 8 9 10111213 79 80 1 2 3 4 5 6 7 8 9 10 111213 7980 1 2 3 b-pat t ern wa veform drive ? 1/80 duty 1 frame 1 frame c- pat tern wav eform drive ? 1/80 duty ? 11-raster-row revers al ? without eors c- pat tern wav eform drive ? 1/80 duty ? 11-rast er-row reversal ? with eors note: specify t he numb er of ac drive rast er-rows and the necess ity of e or so t hat the dc bias is not generated f the liquid crys tal. figure 50 example of an ac signal under n-raster-row reversed ac drive
hd66765 68 preliminary specification screen-division driving function the hd66765 can select and drive two screens at any position with the screen-driving position registers (r14h and r15h). any two screens required for display are selectively driven and a duty ratio is lowered by lcd-driving duty setting (nl4-0), thus reducing lcd-driving voltage and power consumption. for the 1st division screen, start line (ss17-10) and end line (se17-10) are specified by the 1st screen- driving position register (r14h). for the 2nd division screen, start line (ss27-20) and end line (se27-20) are specified by the 2nd screen-driving position register (r15h). the 2nd screen control is effective when the spt bit is 1. the total count of selection-driving lines for the 1st and 2nd screens must correspond to the lcd-driving duty set value. 1st screen : 7 raster-row driving 2nd screen : 17 raster-row driving 1/24 duty driving on 2 screen - driving duty : nl4-0 = "00010" (1/24 duty) - 1st screen setting : ss17-10 = "00"h, se17-10 = "06"h - 2nd screen setting : ss27-20 = "19"h, se27-20 = "29"h, spt = "1" com1 com17 always applying non-selection level always applying non-selection level com26 com42 figure 51 display example in 2-screen division driving
hd66765 69 preliminary specification restrictions on the 1st/2nd screen driving position register settings the following restrictions must be satisfied when setting the start line (ss17-10) and end line (se17-10) of the 1st screen driving position register (r14) and the start line (ss27-20) and end line (se27-20) of the 2nd screen driving position register (r15) for the hd66765. note that incorrect display may occur if the restrictions are not satisfied. table 27 restrictions on the 1st/2nd screen driving position register settings 1st screen driving (spt = 0) 2nd screen driving (spt = 1) register setting ss17-10 se17-0 afh ss17-10 se17-10 < ss27-20 se27-20 afh display operation time-sharing driving for com pins (ss1+1) to (se1+1) non-selection level driving for others time-sharing driving for com pins (ss1+1) to (se1+1) and (ss2+1) to (se2+1) non-selection level driving for others notes: 1. when the total line count in screen division driving settings is less than the duty setting, non- selection level driving is performed without the screen division driving setting range. 2. when the total line count in screen division driving settings is larger than the duty setting, the start line, the duty-setting line, and the lines between them are displayed and non-selection level driving is performed for other lines. 3. for the 1st screen driving, the ss27-20 and se27-20 settings are ignored.
hd66765 modification history revision 0.1 - first release
hd66765 when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all right reserved: no one is permitted to reproduce or duplicated, in any form, the whole or part of this document without hitachi's permission. 3. hitachi will not be held res ponsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachi's semiconductor products. hitachi assumes no responsib ility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party of hitachi, ltd. 6. medical applications: hitachi's products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachi's sales company. such use includes, but is not limited to use in life support systems. buyers of hitachi's products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications.

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