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graphics & speciality drams 256 mbit ddr reduced latency dram version 1.42 nov. 2002 hyb18rl25632ac hyb18rl25616ac
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 2 infineon technologies this specification is preliminary and subject to change without notice edition jun. 2002 this edition was realized using the software system framemaker . published by infineon technologies, marketing-kommunikation, balanstra?e 73, 81541 mnchen ? infineon technologies 6/30/2002. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for application s, processes and circuits imple- mented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon te chnologies companies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for information on the types in question please cont act your nearest in- fineon technologies office. infineon technologies is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you ? get in touch with your nearest sales office. by agreeme nt we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for an y costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of infineon technologies, may only be used in life-support devices or systems 2 with the express written approval of infineon tech- nologies. 1 a critical component is a component used in a life-support dev ice or system whose failure can reasonably be expected to cause the failure of that life- support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sust ain human life. if they fail, it is reasonable to assume that the health of the user may be endangered. hyb18rl25616/32ac revision history: current version 1.42 subjects (major changes since last revision) previous version: 1.34 new formating of the specification document 16 elimination of 4ma driver strength in mrs 17 elimination of configurations 5 and 6 in configuration table. 23 tckdqs (max) changed to 3.7ns for all speed sorts tckdqs (min) changed from 2.3ns to 2.7ns for all speed sorts 25, 26 introduction of "read followed by write, write data on bus prior to read data" timings. 35 reference voltage range changed to 0.49 * vddq to 0.51 * vddq ac operation : hstl strong : vih and vil changed to vref +/- 0.3v previous version: 1.4 15 power up sequence modified: addresses may be applied with specified setup and hold timings during mrs commands. previous version: 1.41 22,23 22,23 t dqsq changed back to t qsq (typo) 22 22 data window = min(t dqsh , t dqsl ) - 2 * t qsq max 23 23 note 4 : tqsq and tqsqhz are absolute values
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 3 infineon technologies this specification is preliminary and subject to change without notice 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.3 ball configuration package and ballout . . . . . . . . . . . . . . . . . . . . . . .6 1.3.1 ball description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.4 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 1.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.5.1 command table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.5.2 description of commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 clocks, commands and addresses . . . . . . . . . . . . . . . . . . . . . . . . .15 2.2 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.3 mode register set command (mrs) . . . . . . . . . . . . . . . . . . . . . . . .17 2.4 configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 2.5 writes (wr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 2.5.1 write - basic information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 2.5.2 write - cyclic bank access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 2.5.2.1 burst length (bl) = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 2.5.2.2 burst length (bl) = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 2.5.3 write data mask timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 2.5.3.1 burst length (bl) = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 2.5.3.2 burst length (bl) = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 2.5.4 write followed by read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2.5.4.1 burst length (bl) = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2.5.4.2 burst length (bl) = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2.6 reads (rd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 2.6.1 read - basic information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 2.6.2 read - cyclic bank access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.6.2.1 burst length (bl) = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.6.2.2 burst length (bl) = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.6.3 read followed by write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 3 ieee 1149.1 serial boundary scan (jtag) . . . . . . . . . . . . . . 29 3.1 test access port (tap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.1.1 test clock (tck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.1.2 test mode select (tms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.1.3 test data-in (tdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.1.4 test data-out (tdo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.2 tap registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.2.1 instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.2.2 bypass register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.2.3 boundary scan register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.2.4 identification (id) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.3 tap instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.4 boundary scan exit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 3.4.1 x16 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 3.4.2 x32 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 3.5 tap operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.6 jtag tap block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.7 jtag tap controller state diagram . . . . . . . . . . . . . . . . . . . . . . . . .34 3.8 jtag dc operating conditons . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.9 jtag ac operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 3.10 jtag ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .35 3.11 jtag timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 4 infineon technologies this specification is preliminary and subject to change without notice 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 4.2 recommended power & dc operation ratings . . . . . . . . . . . . . . . .37 4.3 ac operation ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 4.4 output test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 4.5 pin capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 4.6 operating currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 5 infineon technologies this specification is preliminary and subject to change without notice 1overview 1.1 features 256 megabit (256m) 0.17m process technology cyclic bank addressing for maximum data out bandwidth organization 8m x 32, 16m x 16 in 8 banks non-multiplexed addresses non-interruptible sequential bursts of 2 (2-bit prefetch) and 4 (4-bit prefetch), ddr up to 600mb/sec/pin data rate programmable read latency (rl) of 5..6 data valid signal (dvld) activated as read data is available data mask signals (dm0 / dm1) to mask first and second part of write data burst ieee 1149.1 compliant jtag boundary scan pseudo-hstl 1.8v io supply internal autoprecharge refresh requirements: 32ms at 100c junction temperature (8k refresh for each bank, 64k refresh commands must be issued in total each 32ms) package t-fbga 144 2.5v v ext , 1.8v v dd , 1.8v v ddq table 1 key timing parameters (confi guration example x32, x16 device) speed sort -3.3 -4.0 -5.0 units frequency 300 250 200 mhz t rc 26.7 28.0 25.0 ns 875cycles read latency 6 5 5 cyles
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 6 infineon technologies this specification is preliminary and subject to change without notice 1.2 general description the infineon 256m reduced latency dram (rldram) contains 8 banks x 32 mb of memory accessible with 32bit or 16bit i/o?s in a double data rate (ddr) format where the data is provided and synchronized with a differential echo clock signal. rldram does not require row/column address multiplexing and is optimized for fast random access and high data bandwidth. rldram is designed for communication data storages like transmit or receive buffers in telecommunication systems as well as data or instruction cache applications requiring large amounts of memory. 1.3 ball configuration package and ballout figure 1 t-fbga 144 package 256 mbit ddr reduced latency dram note: all dimensions in mm 3 bottom view 4 0.8 8.8 11 17 18.5 1 12 11 10 9 8 7 6 54 21 a b c d e f g h j k l m n p r t u v ? 0.51 typ 1.20 max side view
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 7 infineon technologies this specification is preliminary and subject to change without notice figure 2 ballout of 256 mbit reduce d latency dram (x32 configuration) vdd vref vext vss vss vss dq10 dq9 vssq vssq vssq vddq vddq dqs1 dq11 vss vss dq15 vss dqs1# dq13 dq12 dq14 dm0 vdd vss vdd vss vdd vssq vddq a5 a6 a7 a8 a9 vss a18 ba2 vdd as# ref# vdd vdd we# cs# vss a15 a16 a17 dm1 vss vss a b c d e f g h j k l m n p r t u v vss vss vref vssq vss vddq vssq dq16 vss vext dq17 dq18 dq19 dq24 dq20 dvld dq22 dq21 dq23 vss vext vss tck vss dq1 dq0 vssq vss vddq dq2 vssq dq3 dqs0# dq8 tms dq5 vddq dq4 vssq dq7 dq6 a0 a1 a2 vdd vss vss a4 a3 vdd vdd ba0 ck vdd vdd ba1 ck# vss vss a14 a13 vdd a12 a11 a10 vssq dq29 vddq vssq vss vddq vssq vext vss tdi tdo vss vss dq28 dq30 dqs3 dq26 dq25 dq27 dq31 dqs3# vss 1234 9101112 56 7 8 dqs0 dqs2# dqs2 nc vss
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 8 infineon technologies this specification is preliminary and subject to change without notice figure 3 ballout of 256mbit reduced latency dram (x16 configuration) note: nc : no connect : these signals are in ternally connected and have parasitic charac terisitcs of an io. they may optionally be connected to ground for improved heat dissipation. vdd vref vext vss vss vss nc vssq vssq vssq vddq vddq nc vss vss nc vss nc nc dm0 vdd vss vdd vss vdd vssq vddq a5 a6 a7 a8 a9 vss as# ba2 vdd we# ref# vdd vdd a19 cs# vss a15 a16 a17 dm1 vss vss a b c d e f g h j k l m n p r t u v vss vref vss vssq vss vddq vssq vss vext nc nc dvld nc nc vss vext vss tck vss dq1 vssq vss vddq vssq dq3 dqs0# tms dq5 vddq vssq dq7 a0 a1 a2 vdd vss vss a4 a3 vdd vdd ba0 ck vdd vdd ba1 ck# vss vss a14 a13 vdd a12 a11 a10 vssq dq13 a18 vddq vssq vss vddq vssq vext vss tdi tdo vss vss dq9 dq11 dq15 dqs1# vss 1234 9101112 56 7 8 dqs0 nc nc nc nc nc nc nc nc nc nc nc dq10 dqs1 dq12 dq14 dq0 dq2 dq4 dq6 dq8 vss
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 9 infineon technologies this specification is preliminary and subject to change without notice 1.3.1 ball description table 2 ball description ball type detailed function ck, ck# input input clock: ck and ck# are differential clock inputs. addresses and commands are latched on the rising edge of ck, input data is latched on the both edges of ck. ck# is ideally 180 degrees out of phase with ck. cs# input chip select: cs# enables the command decoder when low and disables it when high. when the command decoder is disabled new commands are ignored, but internal operations continue. as#, we#, ref# input command inputs: sampled at the positive edge of ck. as#, we# and ref# define (together with cs#) the command to be executed. a[19:0] input address inputs: a[19:0] define the row and column addresses for read and write operations. during an mode register set the address inputs a[17:0] define the register settings. the addresses are sampled at the rising edge of ck. in the x32 configuration, a[19] is not used. in the x16 configuration with bl2, a[19] is used. ba[0:2] input bank select: select to which internal bank a command is being applied. dq[31:0] input/ output data input / output: the dq signals form the 32 bit data bus. during read commands the data is referenced to both edges of dqs/dqs#. during write commands the data is sampled at both edges of ck. dqsx, dqsx# output data read strobes : dqsx and dqsx# are the differential data read strobes. during reads, they are transmitted by the rldram and edge-aligned with data. dqsx is ideally 180 degrees out of phase with dqsx#. dqs0, dqs0# are aligned with dq0-dq7. dqs1, dqs1# are aligned with dq8-dq15. dqs2, dqs2# are aligned with dq16-dq23. dqs3, dqs3# are aligned with dq24-dq31. dvld output data valid: the dvld indicates valid output data. dvld is edge-aligned with dqsx, dqsx#. dm0, dm1 input data mask: dm0 and dm1 are the input masks for write data. the first half of the input data burst is masked when dm0 is sampled high along with the write command. the second half of the input data burst is masked when dm1 is sampled high along with the write command. tck input ieee 1149.1 clock input: jedec standard 1.8v io levels. these pin must be tied to v ss if the jtag function is not used in the circuit. tms, tdi input ieee 1149.1 test inputs: jedec standard 1.8v io levels. these pins may be left not connected if the jtag function is not used in the circuit. tdo output ieee 1149.1 test output: jedec standard 1.8v io level tracking vddq. v ref supply input reference voltage: nominally vddq/2. provides a reference voltage for the input buffers. v ext supply power supply: 2.5v nominal. see dc electrical characteristics and operating conditions for range. v dd supply power supply: 1.8v nominal. see dc electrical characteristics and operating conditions for range. v ddq supply power supply: isolated output buffer supply. 1.8v nominal. see dc electrical characteristics and operating conditions for range. v ss supply power supply: gnd v ssq supply power supply: isolated output buffer supply. gnd nc - no connect : these pins may be connected to ground to improve heat dissipation.
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 10 infineon technologies this specification is preliminary and subject to change without notice 1.4 functional block diagram figure 4 functional block diagram 8m x 32 configuration note: when the bl4 setting is used, a18 is a "don?t care" a0-a18, b0, b1, b2 column address counter column address buffer row address buffer refresh counter input buffers row decoder memory array bank 0 sense amp and data bus column decoder row decoder memory array bank 1 sense amp and data bus column decoder row decoder memory array bank 2 sense amp and data bus column decoder row decoder memory array bank 3 sense amp and data bus column decoder row decoder memory array bank 7 sense amp and data bus column decoder row decoder memory array bank 6 sense amp and data bus column decoder row decoder memory array bank 5 sense amp and data bus column decoder row decoder memory array bank 4 sense amp and data bus column decoder output buffers data read strobe output data valid control logic and timing generators dvld dqs[3:0], dqs#[3:0] dq0-dq31 ck ck# as# dm0 we# cs# ref# dm1 vref
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 11 infineon technologies this specification is preliminary and subject to change without notice figure 5 functional block diagram 16m x 16 configuration note: 1 when the bl4 setting is used, a19 is a "don?t care". note: 2 in the 16mx16 configuration, only dqs[1:0] & dqs#[1:0] are used a0-a19, b0, b1, b2 column address counter column address buffer row address buffer refresh counter input buffers row decoder memory array bank 0 sense amp and data bus column decoder row decoder memory array bank 1 sense amp and data bus column decoder row decoder memory array bank 2 sense amp and data bus column decoder row decoder memory array bank 3 sense amp and data bus column decoder row decoder memory array bank 7 sense amp and data bus column decoder row decoder memory array bank 6 sense amp and data bus column decoder row decoder memory array bank 5 sense amp and data bus column decoder row decoder memory array bank 4 sense amp and data bus column decoder output buffers data read strobe output data valid control logic and timing generators dvld dqs[1:0], dqs#[1:0] dq0-dq15 ck ck# as# dm0 we# cs# ref# dm1 vref
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 12 infineon technologies this specification is preliminary and subject to change without notice 1.5 commands 1.5.1 command table according to the functional signal description the following command sequences are possible. all input states or sequences not shown are illegal or reserved. all command and address inputs must meet setup and hold times around the rising edge of ck. table 3 truth table note: 1: x = ?don?t care? ; h = logic high; l = logic low note: 2: only a[17:0] are used for the mrs command. note: 3: see table 4 table 4 address width table note: 1: the x32 and x16 configurations have different ballouts (see fig. 2 & fig. 3) operation device state code cs# as# we# ref# a[19:0] 1)3) ba]2:0] dm]1:0] no operation any nop l h h h x x x deselect 4) any h x x x x x x mode register set 2) idle mrs l l l l valid x x read any read l l h h valid valid x write any write l l l h valid valid valid auto refresh idle l h h l x valid x data width 32 16 burst length bl 2 a[18:0] a[19:0] bl 4 a[17:0] a[18:0]
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 13 infineon technologies this specification is preliminary and subject to change without notice 1.5.2 description of commands table 5 description of commands note: 1: actual refresh is 32ms/8k/8 = 0.488s note: 2: actual refresh is 32ms/8k = 3.90s command description desel / nop the nop command is used to perform a no operation to the rldram; this is equal to deselecting the chip. use nop command to prevent unwanted commands from being registered during idle or wait states. operations already in progress are not affected. output values depend on command history. mrs the mode register is set via the address inputs a[17:0]. see the mode register description in the register description section. the mrs command can only be issued when all banks are idle and no bursts are in progress. read the read command is used to initiate a burst read access to a bank. the value on the ba[2:0] inputs selects the bank, and the address provided on inputs a[19:0] selects the data location within the bank. write the wr command is used to initiate a burst write access to a bank. the value on the ba[2:0] inputs selects the bank, and the address provided on inputs a[19:0] selects the data location within the bank. input data appearing on the dqs is written to the memory array subject to the dmx input logic levels appearing coincident with the write command. if dm0 is registered low, the first half of the burst write da ta will be written to the memory array, if registerd high this data will be ignored i.e, this part of the data word will not be written. if dm1 is registered low the second half of the burst write data will be written to the memory array, if registerd high this data will be ignored i.e, this part of the data word will not be written. aref the aref is used during normal operation of the rldram to refresh the memory content of a bank. the value on the ba[2:0] inputs selects the bank. the refresh address is generated by the internal refresh controller. this makes the address bits ?don?t care? during an aref command. the rldram requires 64k aref cycles at an average periodic interval of 0.49 s 1) (maximum). to improve efficiency a burst of eight aref commands (one aref for each bank) can be posted to the rldram at an average periodic interval of 3.9s 2) .
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 14 infineon technologies this specification is preliminary and subject to change without notice 2 functional description 2.1 clocks, commands and addresses figure 6 clock command/address timings table 6 general timing parameters for -2.5, -3.3 and -5.0 ns speed sorts note: 1. all timings are measured relatively to the crossing point of ck/ck# and to the crossing point with vref of the command and address signals. note: 2. the signal imput slew rate must be 1v/ns. note: 3. ck/ck# input slew rate must be 1v/ns ( 2v/ns if measured differentially). parameter symbol -3.3 -4.0 -5.0 units min max min max min max clock clock cycle time t ck 3.3 - 4.0 - 5.0 - ns clock high level width t ckh 0.45 0.55 0.45 0.55 0.45 0.55 t ck clock low level width t ckl 0.45 0.55 0.45 0.55 0.45 0.55 t ck setup times address/command input setup time t as, t cs 1.0 ? 1.0 ? 1.0 ? ns hold times address/command input hold time t ah, t ch 1.0 ? 1.0 ? 1.0 ? ns don't care ck# ck t ckh t ckl t as, t cs t ck cmd, addr vaild vaild vaild t ah, t ch
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 15 infineon technologies this specification is preliminary and subject to change without notice 2.2 initialization the rldram must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operation or permanent damage to the device. the following sequence is used for power-up: 1. apply power (v ext , v dd , v ddq , v ref ) and start clock as soon as the supply voltages are stable. apply v dd and v ext before or at the same time as v ddq , apply v ddq before or at the same time as v ref . there is no timing relation between v ext and v dd , the chip starts the power up sequence only when both voltages are at their nominal level. however, the pad supply must not be applied before the core supplies. maintain all pins in nop conditions. 2. maintain stable conditions for 200 s minimum. 3. issue three mode register set commands - 2 dummies plus 1 valid mrs (figure 7). 4. after t mrsc issue 8 auto refresh commands, one on each bank and separated by 2048 cycles. 5. after t rc the chip is ready for normal operation. figure 7 power up sequence note: when the rldram is powered up with the matched impe dance mode inactive, the 2048 cycles between the 8 refresh commands are not required . these c ycles are necessary in order to calibrate the output drivers. don't care mrs: mrs command a.c.: any command rf: refresh ck mrs t mrsc mrs mrs min. 200 s com. vdd vddq vref ck# vext min. 2048 cycles rf a.c. rf rf 6 x 2048 cycles t rc add ba0 ba1 ba7
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 16 infineon technologies this specification is preliminary and subject to change without notice 2.3 mode register set command (mrs) the mode register stores the data for controlling the operating modes of the memory. it programs the rldram configuration, burst length, test mode and io options. during a mode register set command the address inputs a<17:0> are sampled and stored in the mode register. t mrsc must be met before any command can be issued to the rldram. the mode register may only be set immediately after power up sequence. figure 9 mode register set timing table 7 timing parameters mrs figure 10 mode register bitmap note: 1 hstl compliant current specification note: 2 bits a<17:6> must be set to zero note: 3 automatic io impedance calibration is activated in matched mode parameter symbol -3.3 -4.0 -5.0 units notes min max min max min max mode register set cycle time t mrsc 4?4?4?t ck ck# ck we# ref# a[17:0] don't care cod: code to be loaded into the register cs# cod a[19:18] ba<2:0> as# figure 8 mode register set ck# ck don't care t mrsc command mrs: mrs command a.c.: any command mrs nop a.c. nop rldram configuration a3 0 1 burst length 2 (default) 4 rldram configuration a2 a1 a0 do not use 110 4 100 do not use 101 a2 a4 a5 a6 a<17:7> a3 3 011 1 001 2 010 3 (default) 000 burst length matched mode driver strength test mode reserved 2 a1 a0 a4 0 1 matched mode inactive (default) active 3 a5 0 1 driver strength 1 8ma (default) do not use a6 0 1 test mode (default) test mode 1 1 1 do not use
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 17 infineon technologies this specification is preliminary and subject to change without notice 2.4 configuration table the following table shows, for different operating frequencies, the different rldram configurations that can be programmed into the mode register. the read latency (t rl ) and the write latency (t wl ) used by the rldram for the two burst lengths (bl) are also indicated. finally the minimum row cycle time (t rc) in clock cycles and in ns are shown as well. the shaded areas correspond to configurations that are not allowed. note: 1: the speed sort -3.3 provides parts functional up to 300mhz in the configuration 4 only. the functionality of the config urations 1,2 and 3 is not guaranteed for speed sort -3.3. note: 2: the speed sort -4.0 provides parts functional up to 250m hz in the configurations 3 and 4 only. the functionality of the configurations 1 and 2 is not guaranteed for speed sort -4.0. note: 3: the speed sort -5.0 provides par ts functional in all configurations. table 8 rldram configuration table configuration frequency unit 1 2 34 t rc cycles 5 6 78 t rl cycles 5 5 56 t wl (bl2) cycles 2 2 23 t wl (bl4) cycles 1 1 12 300 mhz (-3.3) t rc ns 26.7 t rl ns 20 t wl (bl2) ns 10 t wl (bl4) ns 6.7 250 mhz (-4.0) t rc ns 28.0 32.0 t rl ns 20.0 24.0 t wl (bl2) ns 8.0 12.0 t wl (bl4) ns 4.0 8.0 200 mhz (-5.0) t rc ns 25.0 30.0 35.0 40.0 t rl ns 25.0 25.0 25.0 30.0 t wl (bl2) ns 10.0 10.0 10.0 15.0 t wl (bl4) ns 5.0 5.0 5.0 10.0
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 18 infineon technologies this specification is preliminary and subject to change without notice 2.5 writes (wr) 2.5.1 write - basic information write accesses are initiated with a write command, as shown in figure 11. row and bank addresses are provided together with the write command. during write commands, data will be registered at both edges of ck according to the programmed burst length bl. the first valid data is registered with the first rising ck edge wl (write latency) cycles after the write command has been issued. any write burst may be followed by a subsequent read command. figure 17 and figure 18 illustrate the timing requirements for a write followed by a read for a burst of 2 and 4 respectively. setup and hold time for incoming dqs relative to the ck edges are specified as t ds and t dh . the first or the second part of the incoming data burst is masked if the corresponding dmx signal is sampled high along with the write command. setup and hold time for dm is the same as for addresses and commands. figure 12 basic write burst timing table 9 write timing parameters note: 1. all timings are measured relatively to the crossing point of ck/ck# and to the crossing point with vref of the command and address signals. note: 2. the signal imput slew rate must be 1v/ns. note: 3. ck/ck# input slew rate must be 1v/ns ( 2v/ns if measured differentially). parameter symbol -3.3 -4.0 -5.0 units notes min max min max min max data-in to ck setup time t ds 0.5?0.5?0.5? ns data-in to ck hold time t dh 0.5?0.5?0.5? ns ck# ck ba[2:0] a ba a: address ba: bank address don't care cs# we# ref# a[19:0] dm dm[1:0] dm: data mask as# figure 11 write command dq don't care d0 d1 d2 d3 ck# ck write latency t dh t ds t dh t ds
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 19 infineon technologies this specification is preliminary and subject to change without notice 2.5.2 write - cyclic bank access 2.5.2.1 burst length (bl) = 2 figure 13 write burst basic sequence, bl = 2, wl = 3 2.5.2.2 burst length (bl) = 4 figure 14 write burst basic sequence, bl = 4, wl = 2 ck# ck com 01234567 8 add wl = 3 dq d0a d0d d1a d0b d1b d2a d2b d3a d3b d4a wr a ba0 a ba1 a ba2 a ba3 a ba4 a ba5 a ba6 a ba7 a ba0 wr wr wr wr wr wr wr wr don't care wr: write dxy: data part y to bank x a/bax: address a of bank x wl: write latency d4b d5a ck# ck com 01234567 8 addr wl = 2 dq d0a d0d d0c d0b d0d d1a d1b d1c d1d d2b wr a ba0 a ba1 nop wr wr wr wr nop nop nop a ba3 a ba0 a ba2 don't care wr: write dxy: data part y to bank x a / bax: address a of bank x wl: write latency d2a d2c d2d d3a
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 20 infineon technologies this specification is preliminary and subject to change without notice 2.5.3 write data mask timing 2.5.3.3 burst length (bl) = 2 figure 15 write data mask timing, bl = 2, wl = 2 2.5.3.4 burst length (bl) = 4 figure 16 write data mask timing, bl=4, wl = 1 ck# ck com 01234567 8 add wl = 2 dq d0a d0d d0b d1b d2a d4a wr a ba0 a ba1 a ba2 a ba3 a ba4 a ba5 a ba6 a ba7 a ba0 wr wr wr wr wr wr wr wr d4b d5a d5b d6a data not written into the memory don't care wr: write dxy: data part y to bank x a/bax: address a of bank x wl: write latency dm1 dm0 ck# ck com 01234567 8 addr wl = 1 dq wr a ba0 a ba1 nop wr wr wr wr nop nop nop a ba3 a ba0 a ba2 don't care wr: write dxy: data part y to bank x a / bax: address a of bank x wl: write latency d0a d0d d0c d0b d0d d1c d1d d2b d2a dm0 dm1 data not written into the memory
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 21 infineon technologies this specification is preliminary and subject to change without notice 2.5.4 write followed by read 2.5.4.5 burst length (bl) = 2 figure 17 write followed by read bl = 2, rl = 5, wl = 2 2.5.4.6 burst length (bl) = 4 figure 18 write followed by read bl = 4, rl = 5, wl = 1 ck# ck com 01234567 8 addr wl = 2 dq 9 d0a d0b rl = 5 wr rd rd nop nop nop nop nop nop nop a ba0 a ba1 a ba2 dqs dqs# t ckdqs q1a q2b q2a q1b wr: write dxy: data part y to bank x a/bax: address a of bank x wl: write latency don't care rd: read qxy: data part y of bank x rl: read latency ck# ck com 01234567 8 addr wl = 1 dq 9 q1a q1b d0a rl = 5 wr rd rd nop nop nop nop nop nop nop a ba0 a ba1 dqs dqs# t ckdqs d0b d0c d0d q1c q1d q2a q2b q2c a ba1 wr: write dxy: data part y to bank x a/bax: address a of bank x wl: write latency don't care rd: read qxy: data part y of bank x rl: read latency
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 22 infineon technologies this specification is preliminary and subject to change without notice 2.6 reads (rd) 2.6.1 read - basic information read accesses are initiated with a read command, as shown in figure 19. row and bank addresses are provided with the read command. during read bursts the memory device drives the read data edge aligned with the dqs signal. after a programmable read latency, data is available at the outputs. the data valid signal indicates that valid read data will be present on the bus after 0.5clock cycles. the skew between dqs and ck is specified as t ckdqs . t dqsq is the skew between dqs edge and the last valid data edge. t dqsq is derived at each dqs clock edge and is not cumulative over time. after completion of a burst, assuming no other commands have been initiated, output data will go high-z. back to back read commands are possible, producing a continuous flow of output data. the data valid window is derived for each dqs transition and is defined as: min(t dqsh , t dqsl ) - 2* t qsqmax . any read burst may be followed by a subsequent write command. figure 23 shows the corresponding timing requirements for a read followed by a write. a read to write delay has to be buit in in order to prevent bus contention. some systems having long line lengths or severe skews may need additional idle cycles inserted. figure 20 basic read burst timing ck# ck we# cs# ref# ba<2:0> a ba a: address ba: bank address don't care a<19:0> as# figure 19 read command d0 d1 d2 d3 t ckh t ckl t ckdqs t ck don't care t qsq t qsq data valid window dqs dqs# dvld dq t qsvld t qsvld ck# ck t dqsl t dqsh
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 23 infineon technologies this specification is preliminary and subject to change without notice table 10 read timing parameters for -2.5, -3-3 and -5.0 speed sorts note: 1 all timings are measured relatively to the crossing point of ck/ck# (dqsx/dqsx#), and to the crossing point with vref of the command and address signals. note: 2. the signal imput slew rate must be 1v/ns. note: 3. ck/ck# input slew rate must be 1v/ns ( 2v/ns if measured differentially). note: 4. tdqsq and tqsqhz are absolute values. parameter symbol -3.3 -4.0 -5.0 units notes min max min max min max read cycle timing parameters for data and data strobe dqs / dqs# high pulse width t dqsh 0.4 0.6 0.4 0.6 0.4 0.6 t ck dqs / dqs# low pulse width t dqsl 0.4 0.6 0.4 0.6 0.4 0.6 t ck dqs edge to clock edge skew t ckdqs 2.7 3.7 2.7 3.7 2.7 3.7 ns dqs edge to output data edge t qsq 0.3 0.3 0.3 ns 4 dqs edge to data out hiz t qsqhz 0.4 0.4 0.4 ns 4 dqs edge to dvld edge t qsvld -0.4 0.4 -0.4 0.4 -0.4 0.4 ns
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 24 infineon technologies this specification is preliminary and subject to change without notice 2.6.2 read - cyclic bank access 2.6.2.1 burst length (bl) = 2 figure 21 read burst, bl = 2, rl = 5 2.6.2.2 burst length (bl) = 4 figure 22 read burst, bl = 4, rl = 5 q0a q1a q0b q1b q2a q2b q3a ck# ck com. 01234567 8 addr. rl = 5 dqs dqs# dq rd a ba0 a ba1 a ba2 a ba3 a ba4 a ba5 a ba6 a ba7 a ba0 rd rd rd rd rd rd rd rd don't care a / bax: address a of bank x rd: read qxy: data part y from bank x rl: read latency t ckdqs q0a q0c q0b q0d q1a q1b q1c ck# ck com. 01234567 8 addr. rl = 5 dqs dqs# dq rd rd rd rd rd don't care a / bax: address a of bank x rd: read qxy: data part y from bank x rl: read latency t ckdqs nop nop nop nop a ba0 a ba1 a ba3 a ba0 a ba2
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 25 infineon technologies this specification is preliminary and subject to change without notice 2.6.3 read followed by write figure 23 read followed by writ e, bl=2, rl = 5, wl = 2 figure 24 read followed by write, write data on bus prior read data, bl=2, rl=5, wl=2 q0a q0b d1a d2b d2a d1b ck# ck com. 01234567 addr. rl = 5 dq wl = 2 nop rd nop wr nop 8 wr nop nop nop a ba0 a ba1 a ba2 dqs dqs# t ckdqs wr: write dxy: data part y to bank x a/bax: address a of bank x wl: write latency don't care rd: read qxy: data part y from bank x rl: read latency ck# ck com. 01234567 addr. rl = 5 dq wl = 2 nop rd nop nop 8 nop nop nop wr a ba0 a ba1 dqs dqs# t ckdqs q0a q0b d1a d1b wr: write dxy: data part y to bank x a/bax: address a of bank x wl: write latency don't care rd: read qxy: data part y from bank x rl: read latency nop
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 26 infineon technologies this specification is preliminary and subject to change without notice figure 25 read followed by writ e, bl=4, rl = 5, wl = 1 figure 26 read followed by write, write data on system bus prior read data, bl=4, rl=5, wl=1 ck# ck com. 012345 addr. rl = 5 dq wl = 1 nop rd nop nop nop nop a ba0 nop dqs dqs# t ckdqs q0a q0d q0c q0b 67 wr 89 nop nop nop d1a d1d d1c d1b a ba1 10 wr: write dxy: data part y to bank x a/bax: address a of bank x wl: write latency don't care rd: read qxy: data part y from bank x rl: read latency ck# ck com. 012345 addr. rl = 5 dq wl = 1 nop rd nop nop nop nop a ba0 wr dqs dqs# t ckdqs q0a q0d q0c q0b 67 nop 8 nop d1a d1d d1c d1b a ba1 wr: write dxy: data part y to bank x a/bax: address a of bank x wl: write latency don't care rd: read qxy: data part y from bank x rl: read latency
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 27 infineon technologies rl-ii_xxxxx_1.2_xxxx_xx this specification is preliminary and subject to change without notice 3 ieee 1149.1 serial boundary scan (jtag) the rldram incorporates a serial boundary scan test access port (tap). this port operates fully complient with ieee standard 1149.1-1990. it contains a tap controller, instruction register, boundary scan register, bypass register, and id code register. it is possible to operate the rldram without using the jtag feature. to disable the tap controller, tck must be tied low while tdi, tms and tdo may be left unconnected. upon power-up, the tap will come up in a reset state which will not interfere with the normal operation of the device. 3.1 test access port (tap) 3.1.1 test clock (tck) the test clock is used only with the tap controller. the pin must be tied low if the tap is not used. 3.1.2 test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. this pin may be left unconnected if the tap is not used. 3.1.3 test data-in (tdi) the tdi pin is used to serially input information into the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. tdi is connected to the most significant bit (msb) of any register (see figure 27). this pin may be left unconnected if the tap is not used. 3.1.4 test data-out (tdo) the tdo output pin is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine (see figure 28). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register (see figure 27). this pin may be left unconnected if the tap is not used. 3.2 tap registers registers are connected between the tdi and tdo pins and allow data to be scanned into and shifted out of the rldram test circuitry (see figure 27). only one register is selected at a time through the instruction register. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. 3.2.1 instruction register eight-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins as shown in figure 27. upon power-up, the instruction register is internally preloaded with the idcode instruction. when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board-level serial test data path. 3.2.2 bypass register the bypass register is a single-bit register that can be placed between the tdi and tdo pins. this allows data to be shifted through the rldram with minimal delay. the bypass register is set low during the capture-dr state when the bypass instruction is loaded in the instruction register.
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 28 infineon technologies rl-ii_xxxxx_1.2_xxxx_xx this specification is preliminary and subject to change without notice 3.2.3 boundary scan register the boundary scan register is connected to all the io pins on the rldram. it allows to observe and control the data flowing into and out of the device, depending on the instruction being loaded in the instruction register. the boundary scan register is 104 bits long. the register is the same for the x16 and x32 configurations of the rldram. pins not used in the x16 configurations read a high into the boundary scan register in the capture-dr controller state. differential inputs (ck/ck#) and outputs (dqsx/dqsx#) are equipped with two boundary scan cells each. thus, the differential nature of these pins is not visible to the test circuitry. however, it is recommended that during testing differential signals are always applied to these pin pairs. 3.2.4 identification (id) register the id register is loaded with a hardwired, vendor-specific, 32-bit code during the capture-dr state when the idcode instruction is loaded in the instruction register. the code can be shifted out when the tap controller is in the shift-dr state. two different codes are implemented for the x16 and x32 configurations of the rldram (see table 11). . 3.3 tap instructions the tap implements the 6 instructions bypass, extest, sample/preload and idcode for user access (see table 12). the implementation of these instructions fully complies with the ieee standard. all other instructions are reserved and should not be used. table 12 jtag instruction register table 11 id register definition revision number part number infineon jedec code l s b bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x16 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0 1 1 x32 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0 1 1 instruction register code instruction description hex x7 .. x0 00 0000 0000 extest selects the boundary scan register to be connected between tdi and tdo. data received at input pins are sampled and loaded into the boundary scan register. data driven by output pins are determined from values contained in the boundary scan register. 05 0000 0101 sample / preload selects the boundary scan register to be connected between tdi and tdo. data receivedat input pins are sampled and loaded int the boundary scan register. initial ouput data are shifted into the boundary scan register prior to an extest intruction. instruction does not interfere with the normal operation of the device. 21 0010 0001 idcode selects the id code register to be connected to tdi and tdo. instructin does not interfere with the normal operation of the device. ff 1111 1111 bypass selects the bypass register to be connected between tdi and tdo. instruction does not interfere with the normal operation of the device.
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 29 infineon technologies rl-ii_xxxxx_1.2_xxxx_xx this specification is preliminary and subject to change without notice 3.4 boundary scan exit order 3.4.1 x16 configuration note: 1: input pins are connected to ob serve-only boundary scan register cells. note: 2: output pins are connected to force-only boundary scan register cells. note: 3: io pins are connected to contro l-and-observe boundary scan register cells. note: 4: for bl 4 the content of the register 101 will be set to 0 if a19 is not connected. otherwise, the register content will be equal to the logical value applied to pin a19. scan reg# reg content pin descr . pin name ball # ball # pin name pin descr . reg content scan reg # 27 28 data enb i/o dq1 b10 b3 dq9 i/o enb data 26 25 29 30 data enb i/o dq0 b11 b2 dq8 i/o enb data 24 23 31 32 data enb i/o dq3 c10 c3 dq11 i/o enb data 22 21 33 34 data enb i/o dq2 c11 c2 dq10 i/o enb data 20 19 35 data o dqs0# d10 d3 dqs1# o data 18 36 data o dqs0 d11 d2 dqs1 o data 17 37 38 data enb i/o dq4 e11 e2 dq12 i/o enb data 16 15 39 40 data enb i/o dq5 e10 e3 dq13 i/o enb data 14 13 41 42 data enb i/o dq6 f11 f2 dq14 i/o enb data 12 11 43 44 data enb i/o dq7 f10 f3 dq15 i/o enb data 10 9 45 data o dvld f12 f1 dm0 i data 8 46 data i a1 g11 g2 a6 i data 7 47 data i a2 g10 g3 a7 i data 6 48 data i a0 g12 g1 a5 i data 5 49 data i a3 h12 h1 a8 i data 4 50 data i a4 h11 h2 a9 i data 3 51 data i b0 j11 j2 b2 i data 2 52 data i ck j12 j1 as# i data 1 53 data i ck# k12 k1 we# i data 104 54 data i b1 k11 k2 ref# i data 103 55 data i a14 l11 l2 cs# i data 102 56 data i a13 l12 l1 a19 i data 101 57 data i a10 m12 m1 a15 i data 100 58 data i a12 m10 m3 a17 i data 99 59 data i a11 m11 m2 a16 i data 98 60 data i a18 n12 n1 dm1 i data 97 61 62 data enb i/o dq31 n10 n3 dq23 i/o enb data 96 95 63 64 data enb i/o dq30 n11 n2 dq22 i/o enb data 94 93 65 66 data enb i/o dq29 p10 p3 dq21 i/o enb data 92 91 67 68 data enb i/o dq28 p11 p2 dq20 i/o enb data 90 89 69 data o dqs3 r11 r2 dqs2 o data 88 70 data o dqs3# r10 r3 dqs2# o data 87 71 72 data enb i/o dq26 t11 t2 dq18 i/o enb data 86 85 73 74 data enb i/o dq27 t10 t3 dq19 i/o enb data 84 83 75 76 data enb i/o dq24 u11 u2 dq16 i/o enb data 82 81 77 78 data enb i/o dq25 u10 u3 dq17 i/o enb data 80 79
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 30 infineon technologies rl-ii_xxxxx_1.2_xxxx_xx this specification is preliminary and subject to change without notice 3.4.2 x32 configuration note: 1: input pins are connected to ob serve-only boundary scan register cells. note: 2: output pins are connected to force-only boundary scan register cells. note: 3: io pins are connected to contro l-and-observe boundary scan register cells. note: 4: for bl 4 the content of the register 101 will be set to 0 if a18 is not connected. otherwise, the register content will be equal to the logical value applied to pin a18. scan reg# reg content pin descr . pin name ball # ball # pin name pin descr . reg content scan reg # 27 28 data enb i/o dq1 b10 b3 dq9 i/o enb data 26 25 29 30 data enb i/o dq0 b11 b2 dq8 i/o enb data 24 23 31 32 data enb i/o dq3 c10 c3 dq11 i/o enb data 22 21 33 34 data enb i/o dq2 c11 c2 dq10 i/o enb data 20 19 35 data o dqs0# d10 d3 dqs1# o data 18 36 data o dqs0 d11 d2 dqs1 o data 17 37 38 data enb i/o dq4 e11 e2 dq12 i/o enb data 16 15 39 40 data enb i/o dq5 e10 e3 dq13 i/o enb data 14 13 41 42 data enb i/o dq6 f11 f2 dq14 i/o enb data 12 11 43 44 data enb i/o dq7 f10 f3 dq15 i/o enb data 10 9 45 data o dvld f12 f1 dm0 i data 8 46 data i a1 g11 g2 a6 i data 7 47 data i a2 g10 g3 a7 i data 6 48 data i a0 g12 g1 a5 i data 5 49 data i a3 h12 h1 a8 i data 4 50 data i a4 h11 h2 a9 i data 3 51 data i b0 j11 j2 b2 i data 2 52 data i ck j12 j1 as# i data 1 53 data i ck# k12 k1 we# i data 104 54 data i b1 k11 k2 ref# i data 103 55 data i a14 l11 l2 cs# i data 102 56 data i a13 l12 l1 a18 i data 101 57 data i a10 m12 m1 a15 i data 100 58 data i a12 m10 m3 a17 i data 99 59 data i a11 m11 m2 a16 i data 98 60 data i nc n12 n1 dm1 i data 97 61 62 data enb i/o dq31 n10 n3 dq23 i/o enb data 96 95 63 64 data enb i/o dq30 n11 n2 dq22 i/o enb data 94 93 65 66 data enb i/o dq29 p10 p3 dq21 i/o enb data 92 91 67 68 data enb i/o dq28 p11 p2 dq20 i/o enb data 90 89 69 data o dqs3 r11 r2 dqs2 o data 88 70 data o dqs3# r10 r3 dqs2# o data 87 71 72 data enb i/o dq26 t11 t2 dq18 i/o enb data 86 85 73 74 data enb i/o dq27 t10 t3 dq19 i/o enb data 84 83 75 76 data enb i/o dq24 u11 u2 dq16 i/o enb data 82 81 77 78 data enb i/o dq25 u10 u3 dq17 i/o enb data 80 79
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 31 infineon technologies rl-ii_xxxxx_1.2_xxxx_xx this specification is preliminary and subject to change without notice 3.5 tap operation the user must be aware that the tap controller clock can only operate at a frequency up to 50 mhz, while the rldram clock operates much faster. as a consequence, it is possible that an input or output will undergo a transition right at the moment when the tap takes the snapshot in the capture-dr state of the sample/preload instruction. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to the value that will be captured. to guarantee that the boundary scan register will capture the correct value of a signal, the signal must meet the tap's setup and hold time ( tcs plus tch) around the rising edge of tck. 3.6 jtag tap block diagram figure 27 tap block diagram test access port (tap) controller tms tck 0 3 4 2 1 0 5 6 7 30 31 1 0 bypass register instruction register id code register tdi tdo
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 32 infineon technologies rl-ii_xxxxx_1.2_xxxx_xx this specification is preliminary and subject to change without notice 3.7 jtag tap controller state diagram figure 28 tap controller state diagram 3.8 jtag dc operating conditons parameter symbol limit values unit notes min. typ. max. input logic high voltage, dc v tih v ref + 0.15 -v ddq + 0.3 v input logic low voltage, dc v til v ssq -0.3 -v ref - 0.15 v output logic high voltage (i oh = -tbd ma) v toh v ref + tbd --v output logic low voltage (i ol = tbd ma) v tol --v ref - tbd v test logic reset run test idle select dr select ir 1 0 0 111 capture dr 0 shift dr 1 exit dr pause dr exit2 dr update dr capture ir 0 shift ir exit ir pause ir exit2 ir update ir 0 1 0 1 1 1 0 1 0 1 1 1 1 0 0 1 0 0 0 0 0 0
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 33 infineon technologies rl-ii_xxxxx_1.2_xxxx_xx this specification is preliminary and subject to change without notice 3.9 jtag ac operating conditions 3.10 jtag ac electrical characteristics 3.11 jtag timing diagram parameter symbol min. typ. max. unit notes input logic high voltage, ac v tih v ref +0.3 - v ddq +0.3 v input logic low voltage, ac v til v ssq -0.3 - v ref -0.3 v input slew rate t tsl 1.0 - - v/ns input and output timing reference level v ref v ddq /2 v parameter symbol min. max. unit notes tck cycle time t tck 20 - ns tck high pulse width t tckh 10 - ns tck low pulse width t tckl 10 - ns tck low to tdo valid t tckdo -10ns tdi set up time t tdis 5-ns tms set up time t tmss 5-ns tdi hold time t tdih 5-ns tms hold time t tmsh 5-ns t tck t tckh t tckl t tmsh t tmss t tdih t tdis t tckdo tck tms tdi tdo
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 34 infineon technologies this specification is preliminary and subject to change without notice 4 electrical characteristics 4.1 absolute maximum ratings storage temperature range............................................ ? 55 to + 150 c input/output pins voltage........................................? 0.3 to v ddq + 0.3v inputs and v ref voltage.......................................? 0.3 to v ddq + 0.3v power supply voltage v dd ............................................... ? 0.3 to + 2.1v power supply voltage vext ................................ ........... ? 0.3 to + 2.8v power supply voltage v ddq ............................................ ? 0.3 to + 2.1v junction temperature ......................................................... 0c to 100c note: stresses above those listed under ?absolute maximum ratings ? may cause permanent damage of the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 4.2 recommended power & dc operation ratings all values are recommended operating conditions unless otherwise noted. table 13 power & dc operating conditions note: 1. typically the value of vref is expected to be 0.5 * v ddq of the transmitting device. vref is expected to track variations in v ddq note: 2. peak to peak ac noise on vref may not exceed 2% vref (dc) note: 3. vtt of the transmitting device must track vref of the receiving device. note: 4. recommanded on board decouping capacitors : vddq: 2 x 0.1f / device, vdd: 2 x 0.1f / dev ice, vref : 0.1f / device, vext: 0.1f / device. parameter symbol min. typ. max. unit notes power supply voltages v ext 2.38 2.5 2.63 v v dd 1.75 1.8 1.85 v power supply voltage for i/o v ddq 1.7 1.8 1.9 v reference voltage vref 0.49* v ddq 0.9 0.51* v ddq v 1,2,3 input leakage current i i l -5 +5 a clk input leakage current i i lc -5 +5 a output leakage current i ol -5 +5 a v ref current i ref -5 +5 a matched impedance 1.8v input logic high voltage, dc v i h vref + 0.15 ? v ddq + 0.3 v input logic low voltage, dc v i l v ssq - 0.3 ? vref - 0.15 v output high voltage v oh vddq - - v output low voltage v ol --0v hstl strong input logic high voltage, dc v i h vref + 0.1 ? v ddq + 0.3 v input logic low voltage, dc v i l v ssq - 0.3 ? vref - 0.1 v output high voltage v oh vddq-0.4 - - v output low voltage v ol --0.4v
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 35 infineon technologies this specification is preliminary and subject to change without notice 4.3 ac operation ratings table 14 ac operation conditions for matched impedance mode 4.4 output test conditions figure 29 output test circuits note: vddq=1.8v 0.1v, tj = 0 c to 100 c 4.5 pin capacitances table 15 pin capacitances parameter symbol min. typ. max. unit notes matched impedance 1.8v input logic high voltage, ac ddr v i h vref + 0.3 ? v ddq + 0.3 v input logic low voltage, ac ddr v i l v ssq - 0.3 ? vref - 0.3 v clock differential input voltage (clk/ clk#) v i d 0.6 ? v ddq + 0.6 v clock input crossing point (clk/ clk#) v i x vref - 0.15 vref vref + 0.15 v i/o reference voltage v ref 0.49*v ddq 0.51*v ddq v hstl strong input logic high voltage, ac ddr v i h vref + 0.3 ? v ddq + 0.3 v input logic low voltage, ac ddr v i l v ssq - 0.3 ? vref - 0.3 v clock differential input voltage (clk/ clk#) v i d 0.6 ? v ddq + 0.6 v clock input crossing point (clk/ clk#) v i x vref - 0.15 vref vref + 0.15 v i/o reference voltage v ref 0.49*v ddq 0.51*v ddq v pin min typ. max unit a<19:0>, ba<2:0>, cs#, aref#, we# 2.0 3.0 4.0 pf clk, clk# 2.0 3.0 4.0 pf dq<31:0>, dqs0, dqs0#, dqs1, dqs1#, dvld, dm 2.0 3.0 4.0 pf 10 pf dq test point 20 pf dq 50 ohm test point + v tt = 0.5 x v ddq hstl matched impedance mode
hyb18rl25616/32ac 256 mbit ddr reduced latency dram version 1.42 page 36 infineon technologies this specification is preliminary and subject to change without notice 4.6 operating currents table 16 i dd specifications and conditions parameter symbol/ freq limit values unit notes x16 x32 idd1 (*) operating current (average power supply current) 300mhz vdd vext tbd tbd tbd tbd ma ma burst length = 2 t ck =min, t rc =min, 1 bank active, address change one time during min t rc , read/write command cycling 1.) 250mhz vdd vext tbd tbd tbd tbd ma ma 200mhz vdd vext tbd tbd tbd tbd ma ma idd4r (*) operating current (average power supply current) 300mhz vdd vext tbd tbd tbd tbd ma ma burst length = 4 t ck =min, t rc =min, 4 banks interleave, address change with each bank activation, continuous read operation 1.) 250mhz vdd vext tbd tbd tbd tbd ma ma 200mhz vdd vext tbd tbd tbd tbd ma ma idd8 (*) operating current (average power supply current) 300mhz vdd vext tbd tbd tbd tbd ma ma burst length = 2 t ck =min, t rc =min, 8banks interleave, address change with each bank activation, continuous read operation 1.) 250mhz vdd vext tbd tbd tbd tbd ma ma 200mhz vdd vext tbd tbd tbd tbd ma ma standby current 300mhz vdd vext tbd tbd tbd tbd ma ma t ck =min all banks idle, cs =1 address/data toggling one time/4 clk clock inputs 250mhz vdd vext tbd tbd tbd tbd ma ma 200mhz vdd vext tbd tbd tbd tbd ma ma auto refresh current 300mhz vdd vext tbd tbd tbd tbd ma ma t ck =min all banks idle, cs =1 64k refresh commands/ 32ms 250mhz vdd vext tbd tbd tbd tbd ma ma 200mhz vdd vext tbd tbd tbd tbd ma ma

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