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spider - TLE7243SL 8 channel protected low-side relay switch datasheet, rev. 1.2, may 2011 automotive power
datasheet 2 rev. 1.2, 2011-05-23 spi driver for enhanced relay control spider - TLE7243SL table of contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.3 voltage and current naming definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 general product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 input and power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1.1 limp home mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.2 input circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.2.1 inductive output clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2.2 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3 input and power stages characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 over load protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 over temperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.3 reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.4 protection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 diagnosis features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.1 diagnosis characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.1 spi signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.2 daisy chain capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.3 spi protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.3.1 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.4 spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table of contents
pg-ssop-24-7 type package marking spider - TLE7243SL pg-ssop-24-7 TLE7243SL datasheet 3 rev. 1.2, 2011-05-23 spi driver for enhanced relay control spider - TLE7243SL spider - TLE7243SL 1overview features ? 4 input pins providing flexible pwm configuration ? limp home functionality (direct driving) provided by a dedicated pin ? 16 bit spi for diagnostics and control ? daisy chain capability also com patible with 8bit spi devices ? very wide range of digital supply voltage ? green product (rohs compliant) ? aec qualified description the spider - TLE7243SL is a eight channel low-side switch in pg-ssop-24-7 package providing embedded protective functions. it is especially designed as relay driver in automotive applications. a serial peripheral interface (spi) is utilized for control and diagnosis of the device and the load. for direct control and pwm there are four input pins available. the device is monolithically inte grated. the power transistors are built by n-channel mosfets. diagnostic features ? latched diagnostic info rmation via spi register ? overtemperature monitoring ? overload detection in on state ? open load detection in off state table 1 basic electrical data digital supply voltage v dd 3.0 v ... 5.5 v analog supply voltage v dda 4.5 v ... 5.5 v max. on state resistance at t j = 150c for each channel r ds(on,max) 2.1 ? nominal load current i l (nom) 260 ma overload switch off threshold i d (ovl,max) 950 ma output leakage current per channel at 25 c i d (stb,max) 1 a drain to source clamping voltage v ds(az) 41 v maximum spi clock frequency f sclk,max 5 mhz
spi driver for enhanced relay control spider - TLE7243SL overview datasheet 4 rev. 1.2, 2011-05-23 protection functions ? short circuit ? over load ? over temperature ? electrostatic discharge (esd) application ? all types of resistive, in ductive and capacitive loads ? especially designed for driving relays in automotive applications detailed description the spider - TLE7243SL is a eight channel low-side relay switch designed for typical automotive relays providing embedded protective functions. the pg-ssop- 24-7 package is used to get a footprint optimized solution. the 16 bit serial peri pheral interface (spi) is ut ilized for control and diagnosis of the device and the loads. the spi interface provi des daisy chain capability. the spider - TLE7243SL is equipped with four input pins that can be individually routed to the output control of their dedicated channels thus offering flexibility in design and pcb layout. th e input multiplexer is controlled via spi. there is a dedicated limp home pin lhi which provides a straightforward usage of the input pins as dedicated driver for four outputs. the device provides full diagnosis of the load, which is open load as well as short circuit detection. the spi diagnosis bits indicate latched fault conditions that may have occurred. each output stage is protected against short circuit. in case of over load, the affected channel switches off. there are temperature sensors available for each channel to protect the device in case of over temperature. the device is supplied by two power supply lines. the anal og supply supports 5 v, the digital supply offers a very wide flexibility in supply voltage ra nging from 3.0 v up to 5.5 v. the power transistors are built by n-channel vertical power mosfets. the inputs are ground referenced cmos compatible. the device is monolithically integrated in smart power technology. in terms of pcb layout improvement, all output pins are av ailable at one side of the device. the other side bundles the signals to the micro-controller.
datasheet 5 rev. 1.2, 2011-05-23 spi driver for enhanced relay control spider - TLE7243SL block diagram 2 block diagram figure 1 block diagram for the spider - TLE7243SL blockdiagram .emf gnd cs si sclk so spi control, diagnostic and protective functions diagnosis register vdda vdd rst out3 out2 out1 out7 out6 out5 out4 out8 stand-by control input mux and control in1 in2 in3 in4 lhi open load detection temperature sensor gate control short circuit detection
spi driver for enhanced relay control spider - TLE7243SL pin configuration datasheet 6 rev. 1.2, 2011-05-23 3 pin configuration 3.1 pin assignment figure 2 pin configuration 3.2 pin definitions and functions 20 pin symbol i/o 1) function power supply 13 vdd - digital supply voltage; connected to 3.3v or 5v voltage with reverse protection diode and filter against emc 24 vdda - analog supply voltage; connected to 5v voltage with reverse protection diode and filter against emc 1,2,11,12 gnd - ground; common ground for digital, analog and power power stages 3out1 o output channel 1; drain of power transistor channel 1 4out2 o output channel 2; drain of power transistor channel 2 5out3 o output channel 3; drain of power transistor channel 3 6out4 o output channel 4; drain of power transistor channel 4 7out5 o output channel 5; drain of power transistor channel 5 8out6 o output channel 6; drain of power transistor channel 6 9out7 o output channel 7; drain of power transistor channel 7 10 out8 o output channel 8; drain of power transistor channel 8 inputs 17 in1 i pd control input; digital input 3.3 v or 5v. in case of not used keep open. 16 in2 i pd control input; digital input 3.3 v or 5v. in case of not used keep open. pinout.emf (top view ) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 out2 out3 out4 out5 gnd gnd out1 gnd gnd out6 out7 out8 in2 in3 cs sclk in1 si so rst lhi in4 vdda vdd
datasheet 7 rev. 1.2, 2011-05-23 spi driver for enhanced relay control spider - TLE7243SL pin configuration 15 in3 i pd control input; digital input 3.3 v or 5v. in case of not used keep open. 14 in4 i pd control input; digital input 3.3 v or 5v. in case of not used keep open. 18 lhi i pd limp home; digital input 3.3 v or 5v. in case of not used keep open. 21 rst ipd reset input pin; digital input 3.3 v or 5v. low active spi 23 cs ipu spi chip select; digital input 3.3 v or 5v. low active 20 sclk i pd serial clock; digital input 3.3 v or 5v. 22 si i pd serial data in; digital input 3.3 v or 5v. 19 so o serial data out; digital output with vo ltage level referring to v dd . 1) o: output, i: input, pd: pull-down resistor integrated, pu: pull-up resistor integrated pin symbol i/o 1) function
spi driver for enhanced relay control spider - TLE7243SL pin configuration datasheet 8 rev. 1.2, 2011-05-23 3.3 voltage and current naming definition figure 3 shows all the terms used in this data sheet, with associated convention for positive values. figure 3 terms terms.emf gnd i gnd i d1 out1 out2 i d3 out3 i d2 v dd i dd vdd v rst i rst rst i dda vdda v dda out4 i d5 out5 out6 i d7 out7 i d4 i d6 out8 i d8 v ds1 v bat v ds6 v ds8 v ds7 v ds2 v ds4 v ds3 v ds5 i in 1 in1 i in 2 in2 v in 1 v cs v sc l k v si so sclk si cs v so i cs i sc l k i si i so i in 3 in3 i in 4 in4 v in 2 v in 3 v in 4 i lhi lhi v lhi
datasheet 9 rev. 1.2, 2011-05-23 spi driver for enhanced relay control spider - TLE7243SL general product characteristics 4 general product characteristics 4.1 absolute maximum ratings absolute maximum ratings 1) unless otherwise specified: t j = -40 c to +150 c; v dd = 3.0 v to v dda , v dda = 4.5v to 5.5v all voltages with respect to ground, positive current flowing into pin 1) not subject to production test, specified by design. pos. parameter symbol limit values unit conditions min. max. power supply 4.1.1 digital supply voltage v dd -0.3 5.5 v ? 4.1.2 analog supply voltage v dda -0.3 5.5 v ? 4.1.3 output voltage for sh ort circuit protection (single pulse) v out 036 v? power stages 4.1.4 load current i d -0.5 0.5 a ? 4.1.5 voltage at power transistor v ds ? 41 v active clamped 4.1.6 maximum energy dissipation one channel e as mj 2) v bat =16v, v clamp =45v, 2) pulse shape represents inductive switch off: i d (t) = i d (0) (1 - t / t pulse ); 0 < t < t pulse single pulse ? 67 t j(0) = 150 c i d(0) =0.50 a repetitive (1 10 4 cycles) e ar ?38 t j(0) = 105 c i d(0) =0.35 a repetitive (1 10 6 cycles) ? 30 t j(0) = 105 c i d(0) =0.35 a logic pins 4.1.7 in1,in2,in3,in4; voltage at input pins v in -0.3 5.5 v ? 4.1.8 rst; voltage at reset pin v rst -0.3 5.5 v ? 4.1.9 lhi; voltage at limp home input pin v lhi -0.3 5.5 v ? 4.1.10 cs; voltage at chip select v cs -0.3 v dd + 0.3 v 3) 3) level must not exceed v dd +0.3v < 5.5 v 4.1.11 sclk; voltage at serial clock pin v sclk -0.3 v dd + 0.3 v 3) 4.1.12 si; voltage at serial input pin v si -0.3 v dd + 0.3 v 3) 4.1.13 so; voltage at serial output pin v so -0.3 v dd + 0.3 v 3) temperatures 4.1.14 junction temperature t j -40 150 c? 4.1.15 storage temperature t stg -55 150 c? esd susceptibility 4.1.16 esd resistivity v esd -4 4 kv hbm 4) 4) esd susceptibility, hbm a ccording to eia/jesd 22-a114
spi driver for enhanced relay control spider - TLE7243SL general product characteristics datasheet 10 rev. 1.2, 2011-05-23 note: stresses above the ones listed here may cause perm anent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: integrated protection functions are designed to prevent ic destruction under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. protection functions are not designed for continuous repetitive operation. 4.2 functional range note: within the functional range the ic operates as de scribed in the circuit description. the electrical characteristics are specifi ed within the conditions given in the re lated electrical ch aracteristics table. 4.3 thermal resistance note: this thermal data was generated in accordance with jedec jesd51 standards. for more information, go to www.jedec.org . pos. parameter symbol limit values unit conditions min. max. 4.2.1 digital supply voltage v dd 3.0 5.5 v ? 4.2.1 analog supply voltage v dda 4.5 5.5 v ? 4.2.2 extended supply range v dda 4.0 4.5 parameter deviations are possible 4.2.3 digital supply current in reset mode i dd(rst) ?10a t j = 85 c 4.2.4 digital supply current (all channels active) i dd(on) ?0.5ma v dd = v dda = 5 v v rst = v cs = v dd v sclk = 0 v v in = 0 v 4.2.5 analog supply current (all channels active) i dda(on) ?5ma? 4.2.6 analog supply turn-on time t dda(on) 15 ? s v dda = 0v to 5v (linear) pos. parameter symbol limit values unit conditions min. typ. max. 4.3.7 junction to soldering point r thjsp ??25k/w 1) 2) 1) not subject to production test, specified by design 2) specified r thjsp value is simulated at natural convection on a cold pl ate setup (all pins are fix ed to ambient temperature). t a = 25 c. ls1 to ls8 are dissipating 1 w power (0.125 w each). 4.3.8 junction to ambient (1s0p+600mm 2 cu) r thja ?68?k/w 1) 3) 3) specified r thja value is according to jedec jesd51-2,-3 at natural convection on fr4 1s0p board; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm board with additional heatspreading copper area of 600mm 2 and 70 m thickness. t a = 25 c, ls1 to ls8 are dissipating 1 w power (0.125 w each). 4.3.9 junction to ambient (2s2p) r thja ?60?k/w 1) 4) 4) specified r thja value is according to jedec jesd51-2,-7 at natural convection on fr4 2s2p board; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 m cu, 2 x 35 m cu). t a = 25 c, ls1 to ls8 are dissipating 1 w power (0.125 w each).
datasheet 11 rev. 1.2, 2011-05-23 spi driver for enhanced relay control spider - TLE7243SL input and power stages 5 input and power stages the spider - TLE7243SL is a eight channel low-side relay switch. the power stages are built by n-channel vertical power mosfet transistors. 5.1 power supply the spider - TLE7243SL is supplied by two power supply lines v dd and v dda . the digital power supply line v dd is designed to be functional at a ve ry wide voltage range. the analog power supply v dda supports 5 v supply. there are power-on reset functions implemented for both supply lines. after start-up of the power supply, all spi registers are reset to their default values and th e device is in idle mode . capacitors at pins v dd -gnd and v dda - gnd are recommended. there is a reset pin available. low level at this pin causes all registers to be set to their default values and the quiescent supply currents are minimized. 5.1.1 limp home mode the spider - TLE7243SL offers the cap ability of driving dedicated channels during eventual fa il-safe operation of the system. this limp home mode is activated by a high signal at pin lhi. in this mode, the spi registers are reset and the input pins are directly routed to their corresponding channels out1 to out4, see table 2 for details. out5 to out8 are turned off in limp home mode. furthermore, the spi is ignored and all input pin are referred to v dda in order to ensure a defined operation mode if the digital supply or the microcontroller fail. a high signal on lhi overrides a reset signal on rst. in case of a limp home du ring standby the device will therefore wake up and enter the limp home mode. after limp home operation all registers are reset and the device enters in standby mode following low logic rst state, or returns to idle (all channels off). next spi tr ansmission will receive a ter flag. table 2 routing during limp home mode 5.2 input circuit there are four input pins available at spider - TLE7243SL, which can be configured to be used for control of the output stages. the inn parameter of the spi selects the input pin to be used. figure 4 shows the input circuit of spider - TLE7243SL. during limp home mode a default routing is switched and the spi commands are ignored. input controlled output in1 out1 in2 out2 in3 out3 in4 out4
spi driver for enhanced relay control spider - TLE7243SL input and power stages datasheet 12 rev. 1.2, 2011-05-23 figure 4 input matrix and logic the current sink to ground ensures that the channels switch off in case of open input pin. the zener diode protects the input circuit against esd pulses. after power-on reset, the device enters idle mode (all channel off). 5.2.1 inductive output clamp when switching off inductive loads, the potential at pin out rises to v ds(cl) potential, because the inductance intends to continue driving the current. the voltage clam ping is necessary to prevent destruction of the device, see figure 5 for details. nevertheless, the maxi mum allowed load inductance is limited. inputlogic.emf i in 3 in3 i in 2 in2 i in 1 in1 channel 8 lhi in8 off off off channel 7 lhi in7 off off off channel 6 lhi in6 off off off channel 5 lhi in5 off off off channel 2 lhi in2 off off channel 3 lhi in3 off off channel 4 lhi in4 off off i in 4 in4 channel 1 lhi in1 off in1 in2 in3 in4 on on on on off on on on on i lhi lhi lhi
datasheet 13 rev. 1.2, 2011-05-23 spi driver for enhanced relay control spider - TLE7243SL input and power stages figure 5 output clamp implementation maximum load inductance during demagnetization of inductive lo ads, energy has to be dissipated in the spider - TLE7243SL. this energy can be calculated with following equation: following equation simplifies under the assumption of r l = 0: the maximum energy, which is converted into heat, is limited by the therma l design of the component. 5.2.2 timing diagrams the power transistors are switched on and off with a dedicated slope via the in bits of the serial peripheral interface spi. the switching times t on and t off are designed equally. figure 6 switching a resistive load in input mode, a high signal at the input pin is equivalent to a spi on command and a low signal to spi off command respectively . please refer to section 8.3 for details on operation modes. outputclamp .emf v bat i d v ds(cl) out v ds gnd l , r l ev ds(cl) v bat v ? ds(cl) r l ------------------------------------ ln ? 1 r l i l ? v bat v ? ds(cl) ------------------------------------ ? ?? ?? ?? i l + l r l ------ ?? = e 1 2 -- - li l 2 1 v bat v bat v ? ds(cl) ------------------------------------ ? ?? ?? ?? ? = cs v ds t switch on . e m f t on t off t 20% 80% spi: on spi: off
spi driver for enhanced relay control spider - TLE7243SL input and power stages datasheet 14 rev. 1.2, 2011-05-23 5.3 input and power st ages characteristics note: characteristics show the deviat ion of parameter at given supply volt age and junction temperature. typical values show the typical parameter s expected from manufacturing. electrical characteristics: supply and input all voltages with respect to ground, positive current flowing into pin unless otherwise specified: v dd = 3.0 v to v dda , v dda = 4.5v to 5.5v, t j = -40 c to +150 c pos. parameter symbol limit values unit conditions min. typ. max. power supply 5.3.1 digital supply voltage v dd 3.0 ? 5.5 v ? 5.3.2 digital supply current, all channels on i dd(on) ??0.5ma v dd = v dda = 5 v v rst = v cs = v dd v sclk = 0 v v in = 0 v 5.3.3 digital supply stand-by current, all channels in stand-by mode i dd(stb) ? ? ? ? ? ? 20 20 40 a f sclk = 0 hz v cs = v dd t j = 25 c 1) t j = 85 c 1) t j = 150 c 5.3.4 digital supply reset current i dd(rst) ? ? ? ? ? ? 10 10 20 a v rst = v lhi = 0 v t j = 25 c 1) t j = 85 c 1) t j = 150 c 5.3.5 digital power-on reset threshold voltage v dd(po) ??2.7v? 5.3.6 analog supply voltage v dda 4.5 ? 5.5 v ? 5.3.7 analog supply current all channels on i dda(on) ??5ma? 5.3.8 analog supply stand-by current all channels in stand-by mode i dda(stb) ? ? ? ? ? ? 20 20 40 a v cs = v dd v si = 0 v v sclk = 0 v t j = 25 c 1) t j = 85 c 1) t j = 150 c 5.3.9 analog supply reset current i dda(rst) ? ? ? ? ? ? ? ? 5 5 20 a v rst = v lhi = 0 v t j = 25 c 1) t j = 85 c 1) t j = 150 c 5.3.10 analog power-on reset threshold voltage v dda(po) ??4.0v?
datasheet 15 rev. 1.2, 2011-05-23 spi driver for enhanced relay control spider - TLE7243SL input and power stages output characteristics 5.3.11 on-state resistance per channel r ds(on) ?1.2? ? i l = 400 ma t j = 25 c 1) ?1.752.1 i l = 400 ma t j = 150 c 5.3.12 nominal load current i l(nom) 260 ? ? ma 1) all channels on t a = 85 c t j,max = 150 c based on r thja,2s2p 5.3.13 output leakage current in stand-by mode (per channel) i d(stb) ? ? ? ? ? ? 1 2 5 a v ds = 13.5 v t j = 25 c 1) t j = 85 c 1) t j = 150 c 5.3.14 output clamping voltage v ds(cl) 41 ? 54 v ? input characteristics 5.3.15 l level of pins in1..in4 and lhi v in(l) 0?0.6 v ? 5.3.16 h level of pins in1..in4 and lhi v in(h) 2.0 ? 5.5 v 2) 5.3.17 l-input pull-down current through pin in i in(l) 31280 a 1) v in = 0.6 v 5.3.18 h-input pull-down current through pin in i in(h) 10 40 80 a v dd = 5.5 v v in = v dd reset characteristics 5.3.19 l level of pin rst v rst(l) 0 ? 0.2* v dd ? 5.3.20 h level of pin rst v rst(h) 0.4* v dd ? v dd ? 5.3.21 l-input pull-down current through pin rst i rst(l) 31280 a 1) v rst = 0.6 v 5.3.22 h-input pull-down current through pin rst i rst(h) 10 40 80 a v dd = 5.5 v v rst = v dd timings 5.3.23 reset wake-up time t wu(rst) ??200 s? 5.3.24 reset and lhi signal duration t rst(l) 50 ? ? s? 5.3.25 turn-on time v ds = 20% v bat t on ?3050 s v bat = 13.5 v resistive load all channels i ds = 180 ma 5.3.26 turn-off time v ds = 80% v bb t off ?3050 s v bat = 13.5 v resistive load all channels i ds = 180 ma 1) not subject to production test, specified by design. 2) level must not exceed v dd +0.3v < 5.5 v electrical characteristics: supply and input all voltages with respect to ground, positive current flowing into pin unless otherwise specified: v dd = 3.0 v to v dda , v dda = 4.5v to 5.5v, t j = -40 c to +150 c pos. parameter symbol limit values unit conditions min. typ. max.
spi driver for enhanced relay control spider - TLE7243SL protection functions datasheet 16 rev. 1.2, 2011-05-23 6 protection functions the device provides embedded protecti ve functions. integrat ed protection functions are designed to prevent ic destruction under fault conditions described in this datash eet. fault conditions are co nsidered as ?outside? normal operating range. protection functions are not designed for continuous repetitive operation. 6.1 over load protection the spider - TLE7243SL is protected in case of over load or short circuit of the load. after time t off(ovl) , the over loaded channel n switches off and the a ccording diagnosis flag dn is set.the channel can be switched on after clearing the diagnosis flag. please refer to figure 7 for details. figure 7 shut down at over load the current sink to ground ensures that the channels switch off in case of open input pin. the zener diode protects the input circuit against esd pulses. after po wer-on reset, the devi ce enters idle mode. 6.2 over temperature protection a temperature sensor for each channel causes an overheated channel n to switch off to prevent destruction and the according diagnosis flag dn is set. the channel can be switched on after clearing the diagnosis flag. please refer to chapter 7.1 for information on diagnosis features. 6.3 reverse polarity protection in case of reverse polarity, the intrinsic body diode of the power transistor causes power dissipation. the reverse current through the intrinsic body diode of the power tr ansistor has to be limited by the connected load. the v dd and v dda supply pins must be protected aga inst reverse polarity externally. the over temperature and over load protection is not active during reverse polarity. in1 i out1 t t overload.emf t off(ovl) i out(ovl) d1 = 1 b in1 = 01 b d1 = 0 b d1 = 0 b program out 1 to standby and to in1 again
datasheet 17 rev. 1.2, 2011-05-23 spi driver for enhanced relay control spider - TLE7243SL protection functions 6.4 protection characteristics note: characteristics show the deviat ion of parameter at given supply volt age and junction temperature. typical values show the typical parameter s expected from manufacturing. electrical characteristics: protection all voltages with respect to ground, positive current flowing into pin unless otherwise specified: v dd = 3.0 v to v dda , v dda = 4.5v to 5.5v, t j = -40 c to +150 c pos. parameter symbol limit values unit conditions min. typ. max. over load protection 6.4.1 over load detection current i d(ovl) 0.5 ? 0.95 a ? all channels ? 6.4.2 over load shut-down delay time t off(ovl) 3?50 s? over temperature protection 6.4.3 thermal shut down temperature t j(sc) 150 170 1) 1) not subject to production test, specified by design ? c?
spi driver for enhanced relay control spider - TLE7243SL diagnosis features datasheet 18 rev. 1.2, 2011-05-23 7 diagnosis features the spi of spider - TLE7243SL provides diagnosis inform ation about the device and about the load. there are following diagnosis flags implemented: the diagnosis information of the protective functions of channel n is latched in the diagnosis flag dn . the open load diagnosis of channel n is latched in the diagnosis flag oln . both flags are cleared by programming the specific channel to standby (stb). 7.1 diagnosis characteristics note: characteristics show the deviat ion of parameter at given supply volt age and junction temperature. typical values show the typical parameter s expected from manufacturing. failure mode comment open load or short circuit to ground diagnosis, when channel n is switched on: none diagnosis, when channel n is switched off: according to volt age level at the output pin, flag oln is set after time t d(ol) . when the channel is in off there is diagnosis active, in standby the diagnosis is not enabled over temperature when over temperature occurs, the according diagnosis flag dn is set. if the affected channel n was active it is switched off. the diagnosis flags are latche d until they have been cleared by programming the channel stb. over load (short circuit) when over load is detected at channel n , the affected channel is switched off after time t off(ovl) and the dedicated diagnosis flag dn is set. the diagnosis flags are latche d until they have been cleared by programming the channel stb electrical characteristics: diagnosis all voltages with respect to ground, positive current flowing into pin unless otherwise specified: v dd = 3.0 v to v dda , v dda = 4.5v to 5.5v, t j = -40 c to +150 c pos. parameter symbol limit values unit conditions min. typ. max. off state diagnosis 7.1.1 open load detection threshold voltage v ds(ol) 1.0 ? 2.5 v ? 7.1.2 output pull-down diagnosis current per channel i d(pd) ??80 a v ds = 13.5 v 7.1.3 open load diagnosis delay time t d(ol) 30 ? 200 s? on state diagnosis 7.1.4 over load detection current i d(ovl) 0.5 ? 0.95 a ? 7.1.5 over load detection delay time t off(ovl) 3?50 s?
datasheet 19 rev. 1.2, 2011-05-23 spi driver for enhanced relay control spider - TLE7243SL serial peripheral interface (spi) 8 serial peripheral interface (spi) the diagnosis and control interface is based on a serial peripheral interface (spi). the spi is a full duplex synchronous serial slave in terface, which uses four lines: so, si, sclk and cs . data is transferred by the lines si and so at the data rate given by sclk. the falling edge of cs indicates the beginning of a data access. data is sampled in on line si at the falling ed ge of sclk and shifted ou t on line so at the rising edge of sclk. each access must be terminated by a rising edge of cs . a modulo 8 counter ensures that data is taken only, when a multiple of 8 bit has been transf erred, while the minimum of 16 bit is also taken into consideration. therefore the inte rface provides daisy chain capab ility even with 8 bit spi devices. figure 8 serial peripheral interface the spi protocol is described in section 8.3 . it is reset to the defaul t values after power-on reset. 8.1 spi signal description cs - chip select: the system micro controller selects t he spider - TLE7243SL by means of the cs pin. whenever the pin is in low state, data transfer can take place. when cs is in high state, any signals at the sclk and si pins are ignored and so is forced into a high impedance state. cs high to low transition: ? the diagnosis information is transferred into the shift register. ? so changes from high impedance state to high or lo w state depending on the logi c or combination between the transmission error flag ( ter ) and the signal level at pin si. as a re sult, even in daisy chain configuration, a high signal indicates a faulty transmission. the transmissi on error flag is set after any kind of reset, so a reset between two spi commands is indicated. for details, please refer to figure 9 . this information stays available to the first rising edge of sclk. figure 9 transmission error flag on so line 14 13 12 11 14 13 12 11 msb msb spi.emf lsb 6 5 4 3 2 1 lsb 6 5 4 3 2 1 10 9 8 10 9 8 7 7 so si cs sclk time te r. em f si spi or ter 0 1 so cs sclk s so s si
spi driver for enhanced relay control spider - TLE7243SL serial peripheral interface (spi) datasheet 20 rev. 1.2, 2011-05-23 cs low to high transition: data from shift register is transferred into the input matrix register only, when after the fa lling edge of cs exactly a multiple (1, 2, 3, ?) of eight sc lk signals have been detected, while t he minimum valid length is of course 16 clocks for the 16 register bits of spider - TLE7243SL. sclk - serial clock: this input pin clocks the in ternal shift register. the serial input (si) transfers da ta into the shift register on the falling edge of sclk while the serial output (s o) shifts diagnostic information out on the rising edge of the serial clock. it is essential that the sclk pin is in low state whenever chip select cs makes any transition. si - serial input: serial input data bits are shifted in at this pin, the most significant bit first. si information is r ead on the falling edge of sclk. please refer to section 8.3 for further information. so - serial output: data is shifted out serially at this pin, the most significant bit first. so is in high impedance state until the cs pin goes to low state. new data will appe ar at the so pin following the risi ng edge of sclk. please refer to section 8.3 for further information. 8.2 daisy chain capability the spi of spider - TLE7243SL provides daisy chain capa bility. in this configur ation several devices are activated by the same cs signal mcs . the si line of one device is connect ed with the so line of another device (see figure 10 ), which builds a chain. the ends of the chain are connected with the output and input of the master device, mo and mi respectively. the ma ster device provides the master clock mclk, which is connected to the sclk line of each device in the chain. figure 10 daisy chain configuration in the spi block of each device, there is one shift register where one bit from si line is shifted in each sclk. the bit shifted out can be seen at so. after 16 sclk cycles, the data transfer for one spider - TLE7243SL has been finished. in single chip configuration, the cs line must go high to make the device accept the transferred data. in daisy chain configuration the data shifted out at device #1 has been shifted in to device #2. when using multiple devices in daisy chain, the number of bits must be correspond with the number of register bits. figure 11 is showing a example with 3 spi devices, where #1 and #3 ar e 16 bit spi and #2 has a 8 bit spi. to get a successful transmission, there have to be 2* 16 bit + 1* 8bi t shifted through the devices. after that, the mcs line must go high. si device 1 spi sclk so cs si device 2 spi sclk so cs si device 3 spi sclk so cs mo mi mcs mclk spi _dasychain. emf
datasheet 21 rev. 1.2, 2011-05-23 spi driver for enhanced relay control spider - TLE7243SL serial peripheral interface (spi) figure 11 data transfer in daisy chain configuration 8.3 spi protocol the spi protocol of the spider - TLE7243SL provides two registers. the input register and the diagnosis register. the diagnosis register contai ns eight pairs of diagnosis flags, t he input register contains the input multiplexer configuratio n. after power-on reset, all register bits are set to 1 and the device is in idle mode. note: if all channels are programmed to standby, the devic e changes to power down st atus with minimum current consumption (sleep mode). si default: ffff h 1514131211109876543210 in8 in7 in6 in5 in4 in3 in2 in1 field bits type description inn (n = 8 - 1) 15:14, 13:12, 11:10, 9:8, 7:6, 5:4, 3:2, 1:0 w input register channel n 00 b stand-by mode: channel is switched off. diagnosis flags are cleared. diagnosis current is disabled. 01 b input mode: channel is switched according to signal at input pin. diagnosis current is enabled in off-state. 10 b on mode: channel is switched on. 11 b off mode: channel is switched off. diagnosis current is enabled. mi mo mcs mclk si device 3 si device 2 si device 1 so device 3 so device 2 so device 1 time spi_dasychain2.emf
spi driver for enhanced relay control spider - TLE7243SL serial peripheral interface (spi) datasheet 22 rev. 1.2, 2011-05-23 8.3.1 timing diagrams figure 12 timing diagram so reset value: 10000 h cs 1) 1514131211109876543210 terol8d8ol7d7ol6d6ol5d5ol4d4ol3d3ol2d2ol1d1 1) this bit is valid between cs hi -> lo and first sclk lo -> hi transition. field bits type description ter cs r transmission error 0 previous transmission was su ccessful (modulo 8 clocks received, minimum 16 bit). 1 previous transmission failed or first transmission after reset. oln (n = 8 - 1) 15,13, 11,9,7, 5, 3, 1 r open load flag of channel n 0 normal operation. 1 open load has occurred in off state. dn (n = 8 - 1) 14,12, 10,8,6, 4, 2, 0 r diagnosis flag of channel n 0 normal operation. 1 over load or over temperature switch off has occurred in on state . cs sclk si t cs( l ead) t cs(td) t cs(l ag) t sclk(h) t sclk(l) t sclk(p) t si(su) t si(h) so t so(v) t so(en) t so(dis) 0. 7 v cc 0. 2 v cc 0. 7 v cc 0. 2 v cc 0. 7 v cc 0. 2 v cc 0. 7 v cc 0. 2 v cc spi timing.emf
datasheet 23 rev. 1.2, 2011-05-23 spi driver for enhanced relay control spider - TLE7243SL serial peripheral interface (spi) 8.4 spi characteristics note: characteristics show the deviat ion of parameter at given supply volt age and junction temperature. typical values show the typical parameter s expected from manufacturing. electrical characteristics: seri al peripheral interface (spi) all voltages with respect to ground, positive current flowing into pin unless otherwise specified: v dd = 3.0 v to v dda , v dda = 4.5v to 5.5v, t j = -40 c to +150 c pos. parameter symbol limit values unit conditions min. typ. max. i nput characteristics (cs , sclk, si) 8.4.1 l level of pin cs sclk si v cs(l) v sclk(l) v si(l) 0 ? 0.2* v dd ? 8.4.2 h level of pin cs sclk si v cs(h) v sclk(h) v si(h) 0.4* v dd ? v dd ? 8.4.3 l-input pull-up current through cs i cs(l) 31740 a v cs = 0 v 8.4.4 h-input pull-up current through cs i cs(h) 31540 a 1) v cs = 0.4* v dd 8.4.5 l-input pull-down current through pin sclk si i sclk(l) i si(l) 31280 a 1) v sclk = 0.6 v v si = 0.6 v 8.4.6 h-input pull-down current through pin sclk si i sclk(h) i si(h) 10 40 80 a v sclk = v dd v si = v dd o utput characteristics (so ) 8.4.7 l level output voltage v so(l) 0?0.6v i so = -2 ma 8.4.8 h level output voltage v so(h) v dd - 0.4 v ? v dd i so = 1.5 ma 8.4.9 output tristate leakage current i so(off) -10 ? 10 a v cs = v dd timings 8.4.10 serial clock frequency f sclk 0?5mhz 1) 8.4.11 serial clock period t sclk(p) 200 ? ? ns 1) 8.4.12 serial clock high time t sclk(h) 50 ? ? ns 1) 8.4.13 serial clock low time t sclk(l) 50 ? ? ns 1) 8.4.14 enable lead time (falling cs to rising sclk) t cs(lead) 250 ? ? ns 1) 8.4.15 enable lag time (falling sclk to rising cs ) t cs(lag) 250 ? ? ns 1) 8.4.16 transfer delay time (rising cs to falling cs ) t cs(td) 250 ? ? ns 1)2) 8.4.17 data setup time (required time si to falling sclk) t si(su) 20 ? ? ns 1)
spi driver for enhanced relay control spider - TLE7243SL serial peripheral interface (spi) datasheet 24 rev. 1.2, 2011-05-23 8.4.18 output enable time (falling cs to so valid) t so(en) ??200ns c l = 50 pf 1) 8.4.19 output disable time (rising cs to so tri-state) t so(dis) ??200ns c l = 50 pf 1) 8.4.20 output data valid time with capacitive load t so(v) ??100ns c l = 50 pf 1) 1) not subject to production test, specified by design. 2) diagnosis flag update needs the time specified in chapter 7.1 to get valid information electrical characteristics: seri al peripheral interface (spi) all voltages with respect to ground, positive current flowing into pin unless otherwise specified: v dd = 3.0 v to v dda , v dda = 4.5v to 5.5v, t j = -40 c to +150 c pos. parameter symbol limit values unit conditions min. typ. max.
datasheet 25 rev. 1.2, 2011-05-23 spi driver for enhanced relay control spider - TLE7243SL application information 9 application information note: the following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. figure 13 shows a simplified application circ uit. vdd and vdda need to be exte rnally reverse polarity protected. figure 13 application diagram note: this is a very simplified example of an application ci rcuit. the function must be verified in the real application. for further information you may contact http://www.infin eon.com/spider gnd spi gnd gnd vcc v bat +5v vdd vdd 100nf so sclk si cs in2 in1 TLE7243SL.emf spi out1 out2 out3 out4 out8 low-side gate control in3 lhi limp home signal (eg w d out of sbc tle 8264 g herm es) in4 out5 out6 out7 vdda c xc2000 rst kl15 relay kl50 relay wiper relay horn relay gpio limp home circuit possibility to control out 1- 4 via inputs in1-4 during malfunction of c
spi driver for enhanced relay control spider - TLE7243SL package outlines datasheet 26 rev. 1.2, 2011-05-23 10 package outlines figure 14 pg-ssop-24-7 (plastic dual small outline package) green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb- free finish on leads and suitable for pb-fre e soldering according to ipc/jedec j-std-020). please specify the package needed (e.g. green package) when placing an order pg-ssop-24-5, -6 1) does not include plastic or metal protrusion of 0.15 max. per side 112 24 13 2) does not include dambar protrusion of 0.13 max. 8.65 ?.1 0.65 0.25 2) m c 0.17 b 24x ?.05 a a index marking b (1.47) 1.75 max. 0.1 b seating plane ?.1 3.9 1) 0.35 x 45? 8? max. ?.25 0.64 ?.2 c 6 m 0.2 8? max. 0.07 0.175 0?...8? +0.06 0.19 8 ? max. c 0?...8? 1) you can find all of our packages, so rts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products . dimensions in mm
datasheet 27 rev. 1.2, 2011-05-23 spi driver for enhanced relay control spider - TLE7243SL revision history 11 revision history version date changes rev. 1.2 2011-05-23 parameter 4.1.6 on page 9, condition and max limit values changed rev. 1.1 2011-03-24 new parameter 4.2.6 on page 10 ?analog supply turn-on time? added 5.1 power supply on page 11: change from ?device is in standby mode? to ?device is in idle mode? after power-on reset (as already described on page 12, 16 and 21) rev. 1.0 2009-09-30 released datasheet
edition 2011-05-23 published by infineon technologies ag 81726 munich, germany ? 2011 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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