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| v850e/me2 32-bit single-chip microcontroller hardware user?s manual pd703111a printed in japan document no. u16031ej3v0ud00 (3rd edition) date published june 2004 n cp(k) ?
2 user?s manual u16031ej3v0ud [memo] 3 user?s manual u16031ej3v0ud 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. notes for cmos devices 4 user?s manual u16031ej3v0ud the information in this document is current as of february, 2004. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). ? ? ? ? ? ? m8e 02. 11-1 5 user?s manual u16031ej3v0ud regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [global support] http://www.necel.com/en/support/support.html nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 nec electronics hong kong ltd. hong kong tel: 2886-9318 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-558-3737 nec electronics shanghai ltd. shanghai, p.r. china tel: 021-5888-5400 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 j04.1 n ec electronics (europe) gmbh duesseldorf, germany tel: 0211-65030 ? sucursal en espa?a madrid, spain tel: 091-504 27 87 vlizy-villacoublay, france tel: 01-30-67 58 00 ? succursale fran?aise ? filiale italiana milano, italy tel: 02-66 75 41 ? branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 ? tyskland filial taeby, sweden tel: 08-63 80 820 ? united kingdom branch milton keynes, uk tel: 01908-691-133 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify: 6 user?s manual u16031ej3v0ud introduction readers this manual is intended for users who wish to understand the functions of the v850e/me2 ( ? ? ? ? ? ? ? ? ? ? ? ? ? 7 user?s manual u16031ej3v0ud conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (ove rscore over pin or signal name) memory map address: higher addresse s on the top and lower addresses on the bottom note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numeric representation: binary ... xxxx or xxxxb decimal ... xxxx hexadecimal ... xxxxh prefix indicating power of 2 (address space, memory capacity): k (kilo): 2 10 = 1,024 m (mega): 2 20 = 1,024 2 g (giga): 2 30 = 1,024 3 data type: word ... 32 bits halfword ... 16 bits byte ... 8 bits related documents the related documents indicated in this pub lication may include preliminary versions. however, preliminary versions are not marked as such. document related to v850e/me2 document name document no. v850e1 architecture user?s manual u14559e v850e/me2 hardware user?s manual this manual v850e/me2 hardware application note u16794e v850e/me2 usb function driver s application note u17069e 8 user?s manual u16031ej3v0ud document related to developm ent tools (user?s manuals) document name document no. operation u16053e c language u16054e ca850 (ver. 2.50) (c compiler package) assembly language u16042e pm plus ver. 5.10 u16569e basics u13430e installation u13410e rx850 (ver. 3.13 or later) (real-time os) technical u13431e basics u13773e installation u13774e rx850 pro (ver. 3.15) (real-time os) technical u13772e rd850 (ver. 3.01) (task debugger) u13737e rd850 pro (ver. 3.01) (task debugger) u13916e user?s manual u16031ej3v0ud 9 contents chapter 1 introduction ...................................................................................................... .........17 1.1 outline........................................................................................................................ ................17 1.2 features ....................................................................................................................... ..............18 1.3 applications................................................................................................................... ............20 1.4 ordering information ........................................................................................................... .....20 1.5 pin configuration .............................................................................................................. ........21 1.6 function blocks ................................................................................................................ ........26 1.6.1 internal bl ock di agram ......................................................................................................... .........26 1.6.2 on-chip units.................................................................................................................. ..............27 chapter 2 pin functions .................................................................................................... ..........30 2.1 list of pin functions .......................................................................................................... ......30 2.2 pin status..................................................................................................................... ..............38 2.3 description of pin functions ......................................... .......................................................... 40 2.4 pin i/o circuits and recommended connection of unused pins........................................56 2.5 pin i/o circuits ............................................................................................................... ...........59 chapter 3 cpu function..................................................................................................... ..........60 3.1 features ....................................................................................................................... ..............60 3.2 cpu register set............................................................................................................... ........61 3.2.1 program regi ster set ........................................................................................................... .........62 3.2.2 system regi ster set ............................................................................................................ ..........63 3.3 operating modes................................................................................................................ .......66 3.3.1 operating modes ................................................................................................................ .........66 3.3.2 operating mode specific ation................................................................................................... ....66 3.4 address space .................................................................................................................. ........67 3.4.1 cpu addre ss space .............................................................................................................. .......67 3.4.2 image .......................................................................................................................... .................68 3.4.3 wrap-around of cpu address s pace ...........................................................................................69 3.4.4 memory map ..................................................................................................................... ...........70 3.4.5 area ........................................................................................................................... ..................71 3.4.6 recommended use of address s pace..........................................................................................75 3.4.7 peripheral i/o regist ers ....................................................................................................... .........77 3.4.8 specific re gisters............................................................................................................. ...........103 3.4.9 system wait control register (vswc) .........................................................................................103 3.4.10 initializatio n seque nce........................................................................................................ ........104 chapter 4 bus control function.........................................................................................106 4.1 features ....................................................................................................................... ............106 4.2 bus control pins ............................................................................................................... ......106 4.2.1 pin status during internal instruction ram, internal data ram, and peripheral i/o access ........107 4.3 memory block function .........................................................................................................1 08 user?s manual u16031ej3v0ud 10 4.3.1 chip select co ntrol f unction ................................................................................................... .....109 4.4 bus cycle type control function .................................. ...................................................... 112 4.4.1 bus cycle type configur ation registers 0, 1 (bct0, bct1) .........................................................113 4.5 bus access ..................................................................................................................... ........ 114 4.5.1 number of ac cess cl ocks ........................................................................................................ ...114 4.5.2 bus sizing functi on ............................................................................................................ .........115 4.5.3 endian contro l func tion........................................................................................................ .......116 4.5.4 big endian method usage restrictions in nec electronics dev elopment t ools ............................117 4.5.5 bus wid th...................................................................................................................... ..............119 4.5.6 data read cont rol func tion ..................................................................................................... .....138 4.6 bus clock control function.................................................................................................. 143 4.7 wait function.................................................................................................................. ........ 145 4.7.1 programmable wa it func tion..................................................................................................... ..145 4.7.2 external wait function ......................................................................................................... ........150 4.7.3 relationship between programmable wait a nd external wait......................................................150 4.7.4 bus cycles in which wait function is valid ...................................................................................15 1 4.8 idle state insertion function.............................................. ................................................... 1 52 4.9 instruction cache function................................................................................................... 15 4 4.9.1 cache configur ation regist er (bhc) ...........................................................................................15 4 4.9.2 8 kb 2-way set asso ciative cache..............................................................................................1 56 4.9.3 lru algor ithm .................................................................................................................. ..........156 4.9.4 instruction cache control f unction............................................................................................. ..157 4.9.5 tag clear functi on............................................................................................................. ..........159 4.9.6 auto fill function (way 0 only)................................................................................................ ......160 4.9.7 cautio ns ....................................................................................................................... ..............160 4.10 internal instruction ram control function ......................................................................... 161 4.10.1 internal instruction ram mode register (ira mm).......................................................................161 4.10.2 operation ...................................................................................................................... .............162 4.10.3 cautio ns ....................................................................................................................... ..............163 4.11 bus hold function .............................................................................................................. ... 164 4.11.1 function ou tline............................................................................................................... ...........164 4.11.2 bus hold pr ocedure ............................................................................................................. .......165 4.11.3 operation in po wer-save mode ..................................................................................................1 65 4.11.4 bus hold timing................................................................................................................ ...........166 4.11.5 bus hold timi ng (sram) ......................................................................................................... ....167 4.11.6 bus hold timi ng (s dram) ........................................................................................................ ..170 4.12 bus priority order ............................................................................................................. ..... 174 4.13 boundary operation conditions........................................ ................................................... 174 4.13.1 program space.................................................................................................................. .........174 4.13.2 data s pace ..................................................................................................................... ............174 4.14 timing at which t0 state is not inserted .................... ........................................................ 175 chapter 5 memory access control function .............................................................. 176 5.1 sram, external rom, external i/o interface ....................................................................... 176 5.1.1 featur es ....................................................................................................................... ..............176 5.1.2 sram conn ecti on ................................................................................................................ ......177 5.1.3 sram, external rom, external i/o access ................................................................................179 user?s manual u16031ej3v0ud 11 5.2 page rom controller (romc) ...............................................................................................189 5.2.1 featur es....................................................................................................................... ..............189 5.2.2 page rom co nnecti on ............................................................................................................ ...190 5.2.3 on-page/off-pa ge judgm ent ...................................................................................................... .191 5.2.4 page rom configurati on register (prc) ....................................................................................192 5.2.5 page rom access ................................................................................................................ .....193 5.3 dram controller (sdram) ....................................................................................................199 5.3.1 featur es....................................................................................................................... ..............199 5.3.2 sdram con nection............................................................................................................... .....199 5.3.3 address multip lex func tion ..................................................................................................... ....200 5.3.4 sdram configuration regist ers 1, 3, 4, 6 (scr1, scr3, scr4 , scr6 ) ...................................202 5.3.5 sdram a ccess................................................................................................................... .......205 5.3.6 refresh contro l func tion ....................................................................................................... ......229 5.3.7 self-refresh cont rol function .................................................................................................. .....234 5.3.8 sdram initializa tion sequence .................................................................................................. 236 chapter 6 dma functions (dma controller) ..................................................................239 6.1 features ....................................................................................................................... ............239 6.2 configuration.................................................................................................................. .........240 6.3 control registers .............................................................................................................. ......241 6.3.1 dma source address registers 0 to 3 (dsa0 to dsa3 )..............................................................241 6.3.2 dma destination address register s 0 to 3 (dda 0 to dda 3) ....................................................... 243 6.3.3 dma transfer count registers 0 to 3 (dbc0 to dbc3 ) ................................................................245 6.3.4 dma addressing control registers 0 to 3 (dadc0 to dadc 3).................................................... 246 6.3.5 dma channel control register s 0 to 3 (dchc 0 to dchc3 ) ........................................................249 6.3.6 dma terminal count output c ontrol register (dtoc) ..................................................................252 6.3.7 dma trigger factor registers 0 to 3 (dtfr0 to dtfr 3).............................................................. 253 6.3.8 dma interface control register (difc)........................................................................................25 9 6.4 transfer modes ................................................................................................................. ......260 6.4.1 single trans fer m ode........................................................................................................... .......260 6.4.2 single-step tran sfer mode ...................................................................................................... ....262 6.4.3 block trans fer m ode ............................................................................................................ .......263 6.5 transfer types ................................................................................................................. .......264 6.5.1 2-cycle tr ansfer ............................................................................................................... ...........264 6.5.2 flyby tr ansfer ................................................................................................................. ............275 6.6 transfer target................................................................................................................ ........287 6.6.1 transfer type and transfer target.............................................................................................. ..287 6.6.2 external bus cycles dur ing dma tr ansfer ...................................................................................289 6.7 dma channel priorities ......................................................................................................... .289 6.8 next address setting function ..................................... ........................................................290 6.9 dma transfer start factors ...................................................................................................29 2 6.10 terminal count output u pon dma transfer end ........................ ........................................294 6.11 forcible interruption.......................................................................................................... .....295 6.12 forcible termination ........................................................................................................... ...296 6.13 times related to dma transfer.............................................................................................297 6.14 maximum response time for dma tr ansfer request ........................................................298 6.15 cautions....................................................................................................................... ............299 user?s manual u16031ej3v0ud 12 6.15.1 interrupt factors .............................................................................................................. ............300 6.16 dma transfer end ............................................................................................................... ... 300 chapter 7 interrupt/exception processing function............................................... 301 7.1 features ....................................................................................................................... ........... 301 7.2 non-maskable interrupt s ....................................................................................................... 3 05 7.2.1 operation ...................................................................................................................... .............306 7.2.2 restore........................................................................................................................ ...............308 7.2.3 non-maskable interrupt status fl ag (np) ....................................................................................309 7.2.4 edge detecti on func tion........................................................................................................ ......309 7.3 maskable interrupts ............................................................................................................ ... 310 7.3.1 operation ...................................................................................................................... .............310 7.3.2 restore........................................................................................................................ ...............312 7.3.3 priorities of ma skable inte rrupts .............................................................................................. ...313 7.3.4 interrupt control r egister ( xxicn)............................................................................................. ....317 7.3.5 interrupt mask registers 0 to 5 (imr0 to imr5 ) ..........................................................................320 7.3.6 nmi reset status register (nrs) ................................................................................................ .322 7.3.7 in-service priority register (ispr) ............................................................................................ ...323 7.3.8 maskable interrupt st atus flag (id) ............................................................................................ .323 7.3.9 selecting interrupt trigger mode ............................................................................................... ..324 7.4 software exception ............................................................................................................. ... 339 7.4.1 operation ...................................................................................................................... .............339 7.4.2 restore........................................................................................................................ ...............340 7.4.3 exception stat us flag (ep) ..................................................................................................... .....341 7.5 exception trap ................................................................................................................. ...... 342 7.5.1 illegal opcode definit ion...................................................................................................... ........342 7.5.2 debug trap ..................................................................................................................... ............344 7.6 multiple interrupt servicing cont rol..................................................................................... 346 7.7 interrupt latency time........................................................... .............................................. .. 348 7.8 periods in which interrupts are not acknowledged.. ........................................................ 349 chapter 8 clock generation function............................................................................. 350 8.1 features ....................................................................................................................... ........... 350 8.2 configuration.................................................................................................................. ........ 351 8.3 control registers .............................................................................................................. ..... 351 8.3.1 clock control regi ster (ckc)................................................................................................... ....351 8.3.2 clock source select register (cks)............................................................................................. 354 8.3.3 sscg control regist er (sscgc) ................................................................................................35 6 8.3.4 usb clock control r egister ( uckc) ............................................................................................35 8 8.3.5 lock register (lockr) .......................................................................................................... .....359 8.3.6 oscillation stabilization time select regist er (ost s)................................................................... 360 8.4 operation ...................................................................................................................... .......... 361 8.4.1 operation status of each clock ................................................................................................. ..361 8.4.2 setting of input clock (f x ) ...........................................................................................................361 8.5 operating clock provisions .................................................................................................. 362 8.5.1 calculating busc lk frequ ency .................................................................................................36 3 8.5.2 calculating operatin g clock frequency of each on-ch ip peripheral functi on ................................363 user?s manual u16031ej3v0ud 13 8.6 power-save control............................................................................................................. ...366 8.6.1 overvi ew ....................................................................................................................... .............366 8.6.2 control re gisters.............................................................................................................. ...........368 8.6.3 halt mode...................................................................................................................... ..........371 8.6.4 idle mode ...................................................................................................................... ...........375 8.6.5 software st op m ode ............................................................................................................. ...379 8.7 securing oscillation stabilization time ....................... ........................................................385 8.7.1 oscillation stabilization time security spec ificatio n .....................................................................385 8.7.2 time base coun ter (tbc)........................................................................................................ ...385 chapter 9 timer/counter function (real-time pulse unit)......................................386 9.1 timer c........................................................................................................................ .............386 9.1.1 featur es....................................................................................................................... ..............386 9.1.2 function ov erview .............................................................................................................. ........386 9.1.3 basic confi guratio n............................................................................................................ .........387 9.1.4 timer c ........................................................................................................................ ..............389 9.1.5 control re gisters.............................................................................................................. ...........393 9.1.6 operation ...................................................................................................................... .............401 9.1.7 application exampl es ........................................................................................................... ......408 9.1.8 cautio ns....................................................................................................................... ..............415 9.2 timer d........................................................................................................................ .............416 9.2.1 featur es....................................................................................................................... ..............416 9.2.2 function ov erview .............................................................................................................. ........416 9.2.3 basic confi guratio n............................................................................................................ .........416 9.2.4 timer d ........................................................................................................................ ..............417 9.2.5 control re gisters.............................................................................................................. ...........420 9.2.6 operation ...................................................................................................................... .............422 9.2.7 application exampl es ........................................................................................................... ......424 9.2.8 cautio ns....................................................................................................................... ..............424 9.3 timer enc1..................................................................................................................... .........425 9.3.1 featur es....................................................................................................................... ..............425 9.3.2 function ov erview .............................................................................................................. ........425 9.3.3 basic confi guratio n............................................................................................................ .........427 9.3.4 timer enc1 ..................................................................................................................... ..........429 9.3.5 control re gisters.............................................................................................................. ...........434 9.3.6 operation ...................................................................................................................... .............445 9.3.7 supplementary description of internal operatio n ........................................................................457 chapter 10 serial interface function ..............................................................................461 10.1 features ....................................................................................................................... ............461 10.1.1 switching between uartb0 and csi30 modes ........................................................................461 10.2 asynchronous serial interfaces b0, b1 (uartb0, uartb1).............................................462 10.2.1 featur es....................................................................................................................... ..............462 10.2.2 configur ation.................................................................................................................. ............463 10.2.3 control re gisters.............................................................................................................. ...........467 10.2.4 interrupt requests............................................................................................................. ..........484 10.2.5 control method ................................................................................................................. .........487 user?s manual u16031ej3v0ud 14 10.2.6 operation ...................................................................................................................... .............490 10.2.7 dedicated baud rate generat ors 0, 1 (brg 0, brg1 ) .................................................................501 10.2.8 control flow ................................................................................................................... .............507 10.2.9 cautio ns ....................................................................................................................... ..............517 10.3 clocked serial interfaces 30, 31 (c si30, csi31).................................................................. 518 10.3.1 featur es ....................................................................................................................... ..............518 10.3.2 configur ation.................................................................................................................. ............519 10.3.3 control re gisters.............................................................................................................. ...........521 10.3.4 dedicated baud rate generat ors 0, 1 (brg 0, brg1 ) .................................................................533 10.3.5 operation ...................................................................................................................... .............535 10.3.6 usage .......................................................................................................................... ...............553 10.3.7 cautio ns ....................................................................................................................... ..............559 chapter 11 usb function controller (usbf)................................................................. 560 11.1 overview ....................................................................................................................... .......... 560 11.2 configuration.................................................................................................................. ........ 561 11.3 requests ....................................................................................................................... .......... 562 11.3.1 automatic requests ............................................................................................................. .......562 11.3.2 other r equests ................................................................................................................. ..........570 11.4 register configurat ion ......................................................................................................... . 571 11.4.1 control re gisters.............................................................................................................. ...........571 11.4.2 data hold registers ............................................................................................................ .........624 11.4.3 request data r egister area..................................................................................................... ....649 11.4.4 peripheral cont rol regi sters ................................................................................................... .....665 11.5 stall handshake or no handshake............................. ...................................................... 667 11.6 register values in specific status ....................................................................................... 668 11.7 fw processing .................................................................................................................. ..... 670 11.7.1 initialization processing ...................................................................................................... ........672 11.7.2 interrupt se rvicing............................................................................................................ ...........675 11.7.3 usb main pr ocessi ng............................................................................................................ .....676 11.7.4 suspend/resume processi ng ....................................................................................................70 3 11.7.5 processing after pow er applicat ion ............................................................................................7 06 11.7.6 receiving data for bulk trans fer (out) in dma m ode ................................................................ 709 11.7.7 transmitting data for bulk tran sfer (in) in dma m ode ................................................................ 713 11.7.8 usb connection example ......................................................................................................... ..718 chapter 12 a/d converter ................................................................................................... .... 719 12.1 features ....................................................................................................................... ........... 719 12.2 configuration.................................................................................................................. ........ 720 12.3 control registers .............................................................................................................. ..... 722 12.4 operation ...................................................................................................................... .......... 729 12.4.1 basic oper ation ................................................................................................................ ..........729 12.4.2 operation mode and trigger mode .............................................................................................730 12.5 operation in a/d trigger mode ............................................................................................. 735 12.5.1 select mode operation .......................................................................................................... .....735 12.5.2 scan mode op eratio ns ........................................................................................................... ....737 12.6 operation in timer trigger mode ......................................................................................... 738 user?s manual u16031ej3v0ud 15 12.6.1 select mode operation .......................................................................................................... .....739 12.6.2 scan mode op eration............................................................................................................ .....741 12.7 operation in external trigger mode........................... ...........................................................742 12.7.1 select mode operat ions ......................................................................................................... ....742 12.7.2 scan mode op eration............................................................................................................ .....745 12.8 notes on operation............................................................................................................. ....746 12.9 how to read a/d converter characte ristics table .............................................................748 chapter 13 pwm unit........................................................................................................ ............752 13.1 features ....................................................................................................................... ............752 13.2 configuration.................................................................................................................. .........752 13.3 control registers .............................................................................................................. ......754 13.4 operation ...................................................................................................................... ...........757 13.4.1 pwm basic op eration............................................................................................................ .....757 13.4.2 starting/stopping pwm operat ion ..............................................................................................76 0 13.4.3 setting active leve l of pw m pulse.............................................................................................. 762 13.4.4 specifying pwm pulse wi dth rewrite period ...............................................................................763 13.4.5 repeat cycle ................................................................................................................... ...........764 chapter 14 port functions .................................................................................................. ....765 14.1 features ....................................................................................................................... ............765 14.2 port configuratio n ............................................................................................................. .....765 14.3 port pin functions ............................................................................................................. .....794 14.3.1 port 1 ......................................................................................................................... ................794 14.3.2 port 2 ......................................................................................................................... ................799 14.3.3 port 5 ......................................................................................................................... ................804 14.3.4 port 6 ......................................................................................................................... ................809 14.3.5 port 7 ......................................................................................................................... ................814 14.3.6 port al ........................................................................................................................ ...............817 14.3.7 port ah ........................................................................................................................ ..............822 14.3.8 port dh ........................................................................................................................ ..............824 14.3.9 port cs ........................................................................................................................ ..............833 14.3.10 port ct ........................................................................................................................ ..............836 14.3.11 port cm........................................................................................................................ ..............839 14.3.12 port cd ........................................................................................................................ ..............842 14.4 configuration of reset, a2 to a15, and d0 to d15 pins ...................................................844 14.5 operation of port function ....................................................................................................8 46 14.5.1 writing to i/o port............................................................................................................ ...........846 14.5.2 reading from i/o port .......................................................................................................... ......846 14.5.3 output status of alternate function in co ntrol m ode.................................................................... 846 14.6 noise eliminator............................................................................................................... .......847 14.6.1 interrupt in put pin ............................................................................................................ ...........847 14.6.2 a/d converter input pin ........................................................................................................ ......848 14.6.3 timer c and timer e nc1 input pins ...........................................................................................848 chapter 15 reset functions................................................................................................. ...852 user?s manual u16031ej3v0ud 16 15.1 overview ....................................................................................................................... .......... 852 15.2 configuration.................................................................................................................. ........ 852 15.3 operation ...................................................................................................................... .......... 853 15.4 initialization................................................................................................................. ............ 858 chapter 16 debug function (dcu) ........................................................................................ 864 16.1 functional outline............................................................................................................. ..... 864 16.1.1 debug f unction ................................................................................................................. ..........864 16.1.2 trace f uncti on ................................................................................................................. ...........865 16.1.3 event f uncti on ................................................................................................................. ...........866 16.2 connection with n-wire type emulator....................... ........................................................ 867 16.2.1 emulator co nnector ............................................................................................................. .......868 16.2.2 recommended circ uit exam ple ..................................................................................................86 9 chapter 17 electrical specifications ............................................................................... 870 chapter 18 package drawings .............................................................................................. 91 5 chapter 19 recommended soldering conditions......................................................... 917 appendix a notes ............................................................................................................ .............. 918 a.1 restriction on conflict between sld instruction and interrupt request .......................... 918 a.1.1 descrip tion .................................................................................................................... .............918 a.1.2 counterm easure ................................................................................................................. .......918 a.2 restriction on 2-cycle dma transf er to internal data ram .............................................. 919 a.2.1 descrip tion .................................................................................................................... .............919 a.2.2 counterm easur es................................................................................................................ .......919 appendix b register index .................................................................................................. ..... 920 appendix c instruction set list ........................................................................................... 933 c.1 conventions.................................................................................................................... ........ 933 c.2 instruction set (in alphabetical order) ........................ ........................................................ 936 appendix d revision history ................................................................................................ ... 943 d.1 major revisions in this edition............................................................................................ 943 d.2 revision history up to previous edition.............................................................................. 946 17 user?s manual u16031ej3v0ud chapter 1 introduction the v850e/me2 is a product of the nec electronics single-ch ip microcontroller ?v850 series?. this chapter gives a simple outline of the v850e/me2. 1.1 outline the v850e/me2 is a 32-bit single-chip microcontroller that integrates the v850e1 cp u, which is a 32-bit risc- type cpu core for asic, newly developed as the cpu core central to system lsi for the current age of system-on- chip. this device incorporates cache, data ram, instruct ion ram, and various peripheral functions such as memory controllers, a dma controller, real-time pulse unit, seri al interfaces, usb function controller (usbf), and an a/d converter for realizing high-capacity data pr ocessing and sophisticated real-time control. (1) v850e1 cpu the v850e1 cpu is a cpu core that enhances the external bus interf ace performance of the v850 cpu, which is the cpu core integrated in the v850 series , and has added instructions supporting high-level languages, such as c-language switch statement processing, table lookup branching, stack frame creation/deletion, and data conversion. this enhances the performance of both data processing and control. it is possible to use the software resources of the v850 cpu integrated system since the instruction codes of the v850e1 are upwardly compatible at the obj ect code level with those of the v850 cpu. (2) external memory interface function the v850e/me2 features various on-chip external memory interfaces including separately configured address (26 bits) and data (32 bits) buses, and sdram and rom interfaces, as well as on-chip memory controllers that can be directly lin ked to page rom, etc., thereby ra ising system perform ance and reducing the number of parts needed for application systems. also, through the dma controller, cpu internal ca lculations and data transfers can be performed simultaneously with transfers to and from the external memory, so it is possible to process large volumes of image data or voice data, etc., and thro ugh high-speed exec ution of instructions using internal data ram and instruction ram, motor control, co mmunications control and other real-t ime control tasks can be realized simultaneously. (3) internal instruction ram the instruction ram can be accessed at high speed, in one clock, so that application programs can be executed in real time. (4) a full range of middleware and development environment products the v850e/me2 can execute middleware such as jpeg, jbig, mh/mr/mmr, and tcp/ip at high speed. also, middleware that enables speech recognition, voic e synthesis, and other such processing is available, and by including these middleware programs , a multimedia system can be easily realized. a development environment system that includes an opti mized c compiler, debugger, in-circuit emulator, and other elements is also available. chapter 1 introduction 18 user?s manual u16031ej3v0ud 1.2 features { number of instructions: 83 { minimum instruction execution time: 10 ns/7.5 ns/6 .7 ns (at internal 100 mhz/133 mhz/150 mhz operation) { general-purpose registers: 32 bits 32 { instruction set: v850e1 cpu signed multiplication (16 bits 16 bits 32 bits or 32 bits 32 bits 64 bits): 1 to 2 clocks saturated operation instructions (with overflow/underflow detection function) 32-bit shift instructions: 1 clock bit manipulation instructions load/store instructions with long/short format signed load instructions { memory space: 256 mb linear addre ss space (common program/data use) chip select output function: 8 spaces memory block division function: 2, 4, 6, 8, 64 mb/block programmable wait function idle state insertion function { external bus interface: 32-bit data bus (address/data separated) 32-/16-/8-bit bus sizing function external bus division function: 1/1, 1/2, 1/3, 1/4 (66 mhz max.) bus hold function external wait function address setup wait function endian control function { internal memory instruction ram: 128 kb data ram: 16 kb { instruction cache 8 kb 2-way set associative { interrupts/exceptions: external interrupts: 40 (including nmi) internal interrupts: 59 sources exceptions: 2 sources eight levels of priorities can be set. { memory access controller dram controller (compatible with sdram) page rom controller speculative read/write buffer function chapter 1 introduction 19 user?s manual u16031ej3v0ud { dma controller: 4 channels transfer unit: 8 bits/16 bits/32 bits maximum transfer count: 65,536 (2 16 ) transfer type: flyby (1-cycle)/2-cycle transfer mode: single/single step/block transfer target: memory ? memory, memory ? i/o transfer request: external req uest/on-chip peripheral i/o/ software dma transfer terminate (terminal count) output signal next address setting function { i/o lines: input ports: 1 i/o ports: 77 { real-time pulse unit: 16-bit timer/event count er: 6 channels (no capture operation for 2 channels) 16-bit timers: 6 16-bit capture/compare registers: 12 16-bit interval timer: 4 channels 16-bit up/down counter/timer for 2-phase encoder input: 2 channels 16-bit capture/compare registers: 4 16-bit compare registers: 4 { serial interfaces (sio): asynchronous serial interface b (uartb) clocked serial interface 3 (csi3) csi3/uartb: 1 channel uartb: 1 channel csi3: 1 channel usb function controller (usbf): 1 channel full speed (12 mbps) endpoint control transfer: 64 bytes 2 interrupt transfer: 8 bytes 2 bulk transfer (in): 64 bytes 2 banks 2 bulk transfer (out): 64 bytes 2 banks 2 { a/d converter: 10-bit resolution a/d converter: 8 channels { pwm (pulse width modulation): 16-bit resolution pwm: 2 channels { clock generator: 8 function using sscg { power-save function: halt/idle/software stop mode { package: 176-pin plastic lqfp (fine pitch) (24 24) 240-pin plastic fbga (16 16) { cmos technology: all static circuits chapter 1 introduction 20 user?s manual u16031ej3v0ud 1.3 applications servo control, nc machine tools, ink-jet printers, fa csimiles, dvd players, video printers, ppc, information equipment, etc. 1.4 ordering information part number package maximum operating frequency pd703111agm-10-ueu 176-pin plastic lqfp (fine pitch) (24 24) 100 mhz pd703111agm-13-ueu 176-pin plastic lqfp (fine pitch) (24 24) 133 mhz pd703111agm-15-ueu 176-pin plastic lqfp (fine pitch) (24 24) 150 mhz pd703111af1-10-ga3 240-pin plastic fbga (16 16) 100 mhz pd703111af1-13-ga3 240-pin plastic fbga (16 16) 133 mhz pd703111af1-15-ga3 240-pin plastic fbga (16 16) 150 mhz chapter 1 introduction 21 user?s manual u16031ej3v0ud 1.5 pin configuration ? 176-pin plastic lqfp (fine pitch) (24 24) pd703111agm-10-ueu pd703111agm-13-ueu pd703111agm-15-ueu top view 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 trcdata3 pdh15/d31/intpd15/pwm1 pdh14/d30/intpd14/pwm0 ev ss ev dd pdh13/d29/intpd13/tiud11 pdh12/d28/intpd12/to11 pdh11/d27/intpd11/intp111/tclr11 pdh10/d26/intpd10/intp110/tcud11 pdh9/d25/intpd9/tiud10 pdh8/d24/intpd8/to10 pdh7/d23/intpd7/intp101/tclr10 pdh6/d22/intpd6/intp100/tcud10 pdh5/d21/intpd5/toc5 pdh4/d20/intpd4 pdh3/d19/intpd3 ev ss ev dd pdh2/d18/intpd2/toc4 pdh1/d17/intpd1 pdh0/d16/intpd0 d15 d14 d13 d12 d11 d10 d9 d8 iv ss iv dd ev ss ev dd d7 d6 d5 d4 d3 d2 d1 d0 sdcke/pcd0 ev ss ev dd 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 p72/dmarq2/intpc20/tic2 p73/dmaak2/intpc21 p74/tc2/toc2 p75/dmarq3/intpc30/tic3 p76/dmaak3/intpc31 p77/tc3/toc3 ssel0 ssel1 pllv ss pllv dd oscv ss x2 x1 oscv dd uv dd udm udp p10/uclk/intp10 iv ss iv dd pllsel p11/sck0/intp11 p12/rxd0/si0 p13/txd0/so0 p20/nmi ev ss ev dd p21/rxd1/intp21 p22/txd1/intp22 p23/sck1/intp23 p24/si1/intp24 p25/so1/intp25 dck dms drst ddi ddo trcclk trcend trcdata0 trcdata1 iv ss iv dd trcdata2 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 a25/pah9 a24/pah8 a23/pah7 a22/pah6 a21/pah5 a20/pah4 a19/pah3 a18/pah2 ev dd ev ss iv dd iv ss a17/pah1 a16/pah0 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 ev dd ev ss a4 a3 a2 intpl1/a1/pal1 intpl0/a0/pal0 bcyst/pct7 we/wr/pct5 rd/pct4 uudqm/uube/uuwr/pct3 pct2/ulwr/ulbe/uldqm pct1/luwr/lube/ludqm pct0/llwr/llbe/lldqm iv dd iv ss sdras/pcd3 sdcas/pcd2 busclk/pcd1 jit1 jit0 av dd av refp ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 av refm av ss mode1 mode0 intp67/toc1/p67 intp66/intpc11/p66 intp65/tic1/intpc10/p65 toc0/tc1/p55 intpc01/dmaak1/p54 intpc00/tic0/dmarq1/p53 intp52/tc0/p52 intp51/dmaak0/p51 intp50/dmarq0/p50 iv dd iv ss reset adtrg/selfref/pcm5 refrq/pcm4 hldrq/pcm3 hldak/pcm2 pcm1 wait/pcm0 cs7/pcs7 cs6/pcs6 iord/cs5/pcs5 ev dd ev ss cs4/pcs4 cs3/pcs3 iowr/cs2/pcs2 cs1/pcs1 cs0/pcs0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 chapter 1 introduction 22 user?s manual u16031ej3v0ud ? 240-pin plastic fbga (16 16) pd703111af1-10-ga3 pd703111af1-13-ga3 pd703111af1-15-ga3 bottom view top view 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 vutrpnmlkjhgfedcba abcdefghjklmnprtuv index mark chapter 1 introduction 23 user?s manual u16031ej3v0ud (1/2) pin no. pin name pin no. pin name pin no. pin name a1 ? c12 iv dd g3 ev ss a2 iv ss c13 pah2/a18 g4 d7 a3 pct0/llwr/llbe/lldqm c14 pah4/a20 g15 pcm1 a4 ? c15 pah6/a22 g16 pcm3/hldrq a5 pct4/rd c16 ? g17 pcm4/refrq a6 ? c17 pcs0/cs0 g18 pcm5/adtrg/selfref a7 ? c18 ? h1 ? a8 ev dd d1 d0 h2 d8 a9 a9 d2 ev ss h3 d9 a10 ? d3 pcd0/sdcke h4 d10 a11 a14 d4 ev dd h5 iv ss a12 iv ss d5 pct1/luwr/lube/ludqm h14 ? a13 ev dd d6 ? h15 reset a14 ? d7 pal0/intpl0/a0 h16 iv ss a15 pah5/a21 d8 a4 h17 ? a16 pah7/a23 d9 a6 h18 iv dd a17 pah9/a25 d10 ? j1 ? a18 ? d11 a13 j2 d11 b1 ? d12 ev ss j3 d12 b2 pcd1/busclk d13 pah3/a19 j4 ? b3 pcd2/sdcas d14 ? j5 d13 b4 ? d15 ? j14 ? b5 pct3/uuwr/uube/uudqm d16 pcs2/cs2/iowr j15 p50/intp50/dmarq0 b6 pct7/bcyst d17 pcs3/cs3 j16 p51/intp51/dmaak0 b7 a2 d18 ev dd j17 p52/intp52/tc0 b8 ? e1 d3 j18 p53/intpc00/tic0/dmarq1 b9 a8 e2 d2 k1 d14 b10 a12 e3 d1 k2 d15 b11 pah0/a16 e4 ? k3 pdh0/d16/intpd0 b12 ? e8 a3 k4 pdh1/d17/intpd1 b13 ? e9 a5 k5 pdh2/d18/intpd2/toc4 b14 ? e10 a10 k14 p55/toc0/tc1 b15 ? e11 pah1/a17 k15 p54/intpc01/dmaak1 b16 pah8/a24 e15 pcs4/cs4 k16 p65/intp65/intpc10/tic1 b17 ? e16 ev ss k17 p66/intp66/intpc11 b18 pcs1/cs1 e17 pcs5/cs5/iord k18 ? c1 ? e18 pcs6/cs6 l1 ev dd c2 ? f1 d6 l2 ? c3 pcd3/sdras f2 d5 l3 ev ss c4 iv dd f3 d4 l4 pdh3/d19/intpd3 c5 pct2/ulwr/ulbe/uldqm f4 ? l5 pdh4/d20/intpd4 c6 pct5/we/wr f15 ? l14 mode1 c7 pal1/intpl1/a1 f16 pcs7/cs7 l15 ? c8 ev ss f17 pcm0/wait l16 mode0 c9 a7 f18 pcm2/hldak l17 ? c10 a11 g1 iv dd l18 p67/intp67/toc1 c11 a15 g2 ev dd m1 ? chapter 1 introduction 24 user?s manual u16031ej3v0ud (2/2) pin no. pin name pin no. pin name pin no. pin name m2 pdh5/d21/intpd5/toc5 r7 dck u4 ? m3 pdh6/d22/intpd6/intp100/tcud10 r8 ev dd u5 trcclk m4 ? r9 p11/intp11/sck0 u6 drst m15 ani6 r10 iv ss u7 p25/intp25/so1 m16 av refm r11 udm u8 p22/intp22/txd1 m17 ani7 r12 x2 u9 ev ss m18 av ss r13 pllv dd u10 iv dd n1 pdh7/d23/intpd7/intp101/tclr10 r14 ssel0 u11 ? n2 pdh8/d24/intpd8/to10 r15 ? u12 oscv dd n3 pdh9/d25/intpd9/tiud10 r16 av refp u13 ? n4 pdh10/d26/intpd10/intp110/tcud11 r17 av dd u14 ? n15 ani2 r18 ? u15 p76/intpc31/dmaak3 n16 ani3 t1 ev dd u16 p73/intpc21/dmaak2 n17 ani4 t2 trcdata3 u17 p72/intpc20/tic2/dmarq2 n18 ani5 t3 ? u18 ? p1 ? t4 trcdata1 v1 ? p2 pdh11/d27/intpd11/intp111/tclr11 t5 trcend v2 trcdata2 p3 pdh13/d29/intpd13/tiud11 t6 ddi v3 iv ss p4 ? t7 ? v4 trcdata0 p8 p23/intp23/sck1 t8 p21/intp21/rxd1 v5 ? p9 p12/si0/rxd0 t9 p20/nmi v6 dms p10 ? t10 ? v7 p24/intp24/si1 p11 uv dd t11 udp v8 ? p15 ? t12 x1 v9 p13/so0/txd0 p16 ani0 t13 oscv ss v10 pllsel p17 ani1 t14 ssel1 v11 p10/intp10/uclk p18 ? t15 p75/intpc30/tic3/dmarq3 v12 ? r1 pdh12/d28/intpd12/to11 t16 ? v13 ? r2 ev ss t17 jit1 v14 ? r3 pdh14/d30/intpd14/pwm0 t18 jit0 v15 pllv ss r4 iv dd u1 pdh15/d31/intpd15/pwm1 v16 p77/toc3/tc3 r5 ? u2 ? v17 p74/toc2/tc2 r6 ddo u3 ? v18 ? remark leave the a1, a4, a6, a7, a10, a14, a18, b1, b4, b8 , b12 to b15, b17, c1, c2, c16, c18, d6, d10, d14, d15, e4, f4, f15, h1, h14, h17, j1, j4, j14, k18, l2, l15, l17, m1, m4, p1, p4, p10, p15, p18, r5, r15, r18, t3, t7, t10, t16, u2 to u4, u11, u1 3, u14, u18, v1, v5, v8, v12 to v14, and v18 pins open. chapter 1 introduction 25 user?s manual u16031ej3v0ud pin identification a0 to a25: address bus p72 to p77: port 7 adtrg: a/d trigger input pah0 to pah9: port ah ani0 to ani7: analog input pal0, pal1: port al av dd : analog power supply pcd0 to pcd3: port cd av refm : analog reference voltage pcm0 to pcm5: port cm av refp : analog reference voltage pcs0 to pcs7: port cs av ss : analog ground pct0 to pct5, pct7: port ct bcyst: bus cycle start timing pdh0 to pdh15: port dh busclk: bus clock output pllsel: pll operating mode select cs0 to cs7: chip select pllv dd : pll power supply d0 to d31: data bus pllv ss : pll ground dck: debug clock input pwm0, pwm1: pulse width modulation ddi: debug data input rd: read strobe ddo: debug data output refrq: refresh request drst: debug reset reset: reset dms: debug mode rxd0, rxd1: receive data dmaak0 to dmaak3: dma acknowle dge sck0, sck1: serial clock dmarq0 to dmarq3: dma request sdcas: sdram column address strobe ev dd : power supply for external pins sdcke: sdram clock enable ev ss : ground for external pins sdras: sdram row address strobe hldak: hold acknowledge selfref: self-refresh request hldrq: hold request si0, si1: serial input intp10, intp11, : external interrupt input so0, so1: serial output intp21 to intp25, intp50 to intp52, ssel0, ssel1: clock generator operating mode select intp65 to intp67, tc0 to tc3: terminal count signal intp100, intp101, tclr10, tclr11: timer clear intp110, intp111, tcud10, tcud 11: timer control pulse input intpc00, intpc01, tic0 to tic3: timer input intpc10, intpc11, tiud10, tiud11: timer count pulse input intpc20, intpc21, to10, to11, : timer output intpc30, intpc31, toc0 to toc5 intpd0 to intpd15 trcclk: trace clock intpl0, intpl1 trcdata0 to: trace data output iord: i/o read strobe trcdata3 iowr: i/o write strobe trcend: trace end status output iv dd : power supply for internal unit txd0, txd1: transmit data iv ss : ground for internal unit uclk: usb external clock input jit0, jit1: sscg jitter select udm: usb data input & output ( ? ) llbe: lower byte enable (d0 to d7) udp: usb data input & output (+) lldqm: lower dq mask enable (d0 to d7) ulbe: upper byte enable (d16 to d23) llwr: lower write strobe (d0 to d7) lube: lower byte enable (d8 to d15) uldqm: upper dq mask enable (d16 to d23) ludqm: lower dq mask enable (d8 to d 15) ulwr: upper write strobe (d16 to d23) luwr: lower write strobe (d8 to d15) uube: upper byte enable (d24 to d31) mode0, mode1: mode nmi: non-maskable interrupt request uudqm: upper dq mask enable (d24 to d31) oscv dd : clock generator power supply uuwr: upper write strobe (d24 to d31) oscv ss : clock generator ground uv dd : power supply for usb unit p10 to p13: port 1 wait: wait p20 to p25: port 2 we: write enable p50 to p55: port 5 wr: write strobe output enable p65 to p67: port 6 x1, x2: crystal chapter 1 introduction 26 user?s manual u16031ej3v0ud 1.6 function blocks 1.6.1 internal block diagram cpu 32-bit barrel shifter pc system registers general-purpose registers (32 bits 32) alu multiplier (32 32 64) ports p10 to p13 p20 p21 to p25 p50 to p55 p65 to p67 p72 to p77 pal0, pal1 pah0 to pah9 pcd0 to pcd3 pcm0 to pcm5 pcs0 to pcs7 pct0 to pct5, pct7 pdh0 to pdh15 adc usbf pwm system controller bcu instruction queue memc sram rom sdram dma si0/rxd0 so0/txd0 sck0 toc4, toc5 toc0 to toc3 tic0 to tic3 to10, to11 nmi drst, dck, dms, ddi wait hldrq hldak a0 to a25 d0 to d31 dmarq0 to dmarq3 dmaak0 to dmaak3 tc0 to tc3 cs0, cs1, cs3, cs4, cs6, cs7 cs2/iowr cs5/iord bcyst rd ani0 to ani7 adtrg av refp , av refm av dd av ss reset mode0, mode1 iv dd iv ss ev dd ev ss pwm0, pwm1 udp udm uclk uv dd xxwr/xxbe wr busclk sdcke sdras sdcas we xxdqm refrq selfref ddo, trcclk, trcdata0 to trcdata3 , trcend intp100, intp110 intp101, intp111 intp10, intp11 intp21 to intp25 intp50 to intp52 intp65 to intp67 intpd0 to intpd15 intpl0, intpl1 tclr10, tclr11 tiud10, tiud11 tcud10, tcud11 intpc00, intpc01, intpc10, intpc11, intpc20, intpc21, intpc30, intpc31 si1 so1 sck1 rxd1 txd1 ssel0, ssel1 jit0, jit1 pllsel x1 x2 oscv dd oscv ss pllv dd pllv ss tmc tmc tmenc1 intc dcu tmd csi30/uartb0 csi31 uartb1 cg 8 kb instruction cache 128 kb instruction ram 16 kb data ram bbr remark xx: ll, lu, ul, uu chapter 1 introduction 27 user?s manual u16031ej3v0ud 1.6.2 on-chip units (1) cpu the cpu uses five-stage pipeline control to enable sing le-clock execution of addres s calculations, arithmetic logic operations, data transfers, and almo st all other instruction processing. other dedicated on-chip hardware, such as a multiplier (16 bits 16 bits 32 bits or 32 bits 32 bits 64 bits) and a barrel shifter (32 bits), help acce lerate processing of complex instructions. (2) bus control unit (bcu) the bcu starts the required external bus cycle bas ed on the physical address obtained by the cpu. when an instruction is fetched from external memory area an d the cpu does not send a bus cycle start request, the bcu generates a prefetch address a nd prefetches the instruction code. the prefetched in struction code is stored in an instruction queue in the cpu. the bcu controls a dram controll er (dramc), page rom controller (romc), and dma controller (dmac) and performs external memory access and dma transfer. (a) sdram controller the sdram controller generates the sdras, s dcas, uudqm, uldqm, ludqm, and lldqm signals and performs access control for sdram. cas latency 1 (excluding flyby dma transfer), 2, and 3 ar e supported, and the burst length is fixed to 1. a refresh function that supports the cbr refresh cycle and a dynamic self-refresh function based on an external input are also available. (b) page rom controller (romc) this controller supports accessing rom that includes the page access function. it performs address comparisons with the immediately preceding bus cycle and executes wait control for normal access (off-page)/page access (on-page). it can handle page widths of 8 to 128 bytes. (c) dma controller (dmac) this controller controls data transfer between memory and i/o instead of the cpu. there are two address modes: flyby (1-cycle) transfer, and 2-cycle transfer. there are three bus modes, single transfer, single step transfer, and block transfer. (3) ram instruction ram (128 kb) and dat a ram (16 kb) are provided. the instruction ram can be accessed in one clock from the cpu when an instructio n is fetched. its write access time depends on the busclk fr equency to the cs0 space and the number of wait cycles. this ram is mapped from address 00000000h. the data ram can be accessed in one clock from the cpu when its data is read. it is mapped from address ffff8000h. (4) cache a 2-way set associative instruction cache (8 kb) is provided. chapter 1 introduction 28 user?s manual u16031ej3v0ud (5) interrupt controller (intc) this controller handles ha rdware interrupt requests (nmi, intpn) from on-chip peripheral i/o and external hardware. eight levels of interrupt priorities can be specified for these interrupt requests, and multiple- interrupt servicing control can be performed for interrupt sources (n = 10, 11, 21 to 25, 50 to 52, 65 to 67, d0 to d15, l0, l1, c00, c01, c10, c11, c20, c21, c30, c31). (6) clock generator (cg) this clock generator supplies frequencies which are 8 times the input clock (f x ) (using an on-chip pll) as the internal system clock (f clk ). as the input clock, an external o scillator is input from pins x1 and x2. (7) real-time pulse unit (rpu) this unit incorporates a 6-channel 16-bit timer/event co unter, 4-channel 16-bit interval timer, and 2-channel 16-bit up/down counter/timer for 2- phase encoder input and can meas ure pulse widths or frequency and output a programmable pulse. (8) serial interfaces (sio) the serial interfaces consist of 3 channels divided between an asynchronous serial interface b (uartb) and clocked serial interface 3 (csi3). of these 3 channels, one is alternative with uartb and csi3, one is fixed to csi3, and one is fixed to uartb. uartb transfers data by using the txdn and rxdn pins (n = 0, 1). csi3 transfers data by using the son, sin, and sckn pins (n = 0, 1). in addition, a usb function controller (usbf) is also provided. (9) a/d converter (adc) this high-speed, high-resolution 10-bit a/d converter in cludes 8 analog input pins. conversion is performed using the successive approximation method. (10) pwm two channels for pwm signal output of 16-bit resoluti on have been provided. by connecting an external low-pass filter, pwm output can be used as digital to analog conversion output. pwm is ideal for actuator control signals such as those in motors. chapter 1 introduction 29 user?s manual u16031ej3v0ud (11) ports as shown below, the following ports have general -purpose port functions and control pin functions. port i/o control function port 1 4-bit i/o serial interface i/o, usb clock signal input, external interrupt input port 2 1-bit input, 5-bit i/o nmi input, serial interface i/o, external interrupt input port 5 6-bit i/o dma controller i/o, exter nal interrupt input, real-time pulse unit i/o port 6 3-bit i/o real-time pulse unit i/o, external interrupt input port 7 6-bit i/o dma controller i/o, real-t ime pulse unit i/o, external interrupt input port al 2-bit i/o external addre ss bus, external interrupt input port ah 10-bit i/o external address bus port dh 16-bit i/o external data bus, external in terrupt input, pwm output, real-time pulse unit i/o port cs 8-bit i/o external bus interface control signal output port ct 7-bit i/o external bus interface control signal output port cm 6-bit i/o wait insertion signal input, external bus interface control signal i/o, self-refresh request signal input, a/d converter external trigger input port cd 4-bit i/o external bus interfac e control signal output, bus clock output user?s manual u16031ej3v0ud 30 chapter 2 pin functions the names and functions of the pins in the v850e/me2 are listed below. these pins can be divided into port pins and non-port pins according to their functions. 2.1 list of pin functions (1) port pins (1/3) pin name i/o function alternate function p10 intp10/uclk p11 intp11/sck0 p12 si0/rxd0 p13 i/o port 1 4-bit i/o port input/output can be specified in 1-bit units. so0/txd0 p20 input nmi p21 intp21/rxd1 p22 intp22/txd1 p23 intp23/sck1 p24 intp24/si1 p25 i/o port 2 p20 is an input port dedicat ed to checking the nmi input status. if a valid edge is input, it operates as an nmi input. p21 to p25 are a 5-bit i/o port. input/output can be specified in 1-bit units. intp25/so1 p50 intp50/dmarq0 p51 intp51/dmaak0 p52 intp52/tc0 p53 intpc00/tic0/dmarq1 p54 intpc01/dmaak1 p55 i/o port 5 6-bit i/o port input/output can be specified in 1-bit units. toc0/tc1 p65 intp65/intpc10/tic1 p66 intp66/intpc11 p67 i/o port 6 3-bit i/o port input/output can be specified in 1-bit units. intp67/toc1 p72 intpc20/tic2/dmarq2 p73 intpc21/dmaak2 p74 toc2/tc2 p75 intpc30/tic3/dmarq3 p76 intpc31/dmaak3 p77 i/o port 7 6-bit i/o port input/output can be specified in 1-bit units. toc3/tc3 pah0 to pah9 i/o port ah 8-/10-bit i/o port input/output can be specified in 1-bit units. a16 to a25 chapter 2 pin functions 31 user?s manual u16031ej3v0ud (2/3) pin name i/o function alternate function pal0 intpl0/a0 pal1 i/o port al 2-bit i/o port input/output can be specified in 1-bit units. intpl1/a1 pdh0 d16/intpd0 pdh1 d17/intpd1 pdh2 d18/intpd2/toc4 pdh3 d19/intpd3 pdh4 d20/intpd4 pdh5 d21/intpd5/toc5 pdh6 d22/intpd6/intp100/tcud10 pdh7 d23/intpd7/intp101/tclr10 pdh8 d24/intpd8/to10 pdh9 d25/intpd9/tiud10 pdh10 d26/intpd10/intp110/tcud11 pdh11 d27/intpd11/intp111/tclr11 pdh12 d28/intpd12/to11 pdh13 d29/intpd13/tiud11 pdh14 d30/intpd14/pwm0 pdh15 i/o port dh 8-/16-bit i/o port input/output can be specified in 1-bit units. d31/intpd15/pwm1 pcd0 sdcke pcd1 busclk pcd2 sdcas pcd3 i/o port cd 4-bit i/o port input/output can be specified in 1-bit units. sdras pcm0 wait pcm1 ? pcm2 hldak pcm3 hldrq pcm4 refrq pcm5 i/o port cm 6-bit i/o port input/output can be specified in 1-bit units. adtrg/selfref pcs0 cs0 pcs1 cs1 pcs2 cs2/iowr pcs3 cs3 pcs4 cs4 pcs5 cs5/iord pcs6 cs6 pcs7 i/o port cs 8-bit i/o port input/output can be specified in 1-bit units. cs7 chapter 2 pin functions 32 user?s manual u16031ej3v0ud (3/3) pin name i/o function alternate function pct0 llwr/llbe/lldqm pct1 luwr/lube/ludqm pct2 ulwr/ulbe/uldqm pct3 uuwr/uube/uudqm pct4 rd pct5 we/wr pct7 i/o port ct 7-bit i/o port input/output can be specified in 1-bit units. bcyst chapter 2 pin functions 33 user?s manual u16031ej3v0ud (2) non-port pins (1/5) pin name i/o function alternate function a0 pal0/intpl0 a1 pal1/intpl1 a2 to a9 ? a10 to a15 ? a16 to a25 output 26-bit address bus for external memory pah0 to pah9 adtrg input a/d converter external trigger input pcm5/selfref ani0 to ani7 input analog inputs to a/d converter ? av dd ? 3.3 v positive power supply for a/d converter ? av refm ? av refp input reference voltage applied to a/d converter ? av ss ? ground potential for a/d converter ? bcyst output strobe signal output that shows the start of the bus cycle pct7 busclk output clock output for sdram pcd1 cs0 pcs0 cs1 pcs1 cs2 pcs2/iowr cs3 pcs3 cs4 pcs4 cs5 pcs5/iord cs6 pcs6 cs7 output chip select signal output pcs7 d0 to d15 ? d16 pdh0/intpd0 d17 pdh1/intpd1 d18 pdh2/intpd2/toc4 d19 pdh3/intpd3 d20 pdh4/intpd4 d21 pdh5/intpd5/toc5 d22 pdh6/intpd6/intp100/tcud10 d23 pdh7/intpd7/intp101/tclr10 d24 pdh8/intpd8/to10 d25 pdh9/intpd9/tiud10 d26 pdh10/intpd10/intp110/tcud11 d27 pdh11/intpd11/intp111/tclr11 d28 pdh12/intpd12/to11 d29 pdh13/intpd13/tiud11 d30 pdh14/intpd14/pwm0 d31 i/o 32-bit data bus for external memory pdh15/intpd15/pwm1 chapter 2 pin functions 34 user?s manual u16031ej3v0ud (2/5) pin name i/o function alternate function dck input debug clock input ? ddi input debug data input ? ddo output debug data output ? dmaak0 p51/intp51 dmaak1 p54/intpc01 dmaak2 p73/intpc21 dmaak3 output dma acknowledge signal output p76/intpc31 dmarq0 p50/intp50 dmarq1 p53/intpc00/tic0 dmarq2 p72/intpc20/tic2 dmarq3 input dma request signal input p75/intpc30/tic3 dms input debug mode select ? drst input reset input for debug ? ev dd ? 3.3 v positive power supply for external pin ? ev ss ? ground potential for external pin ? hldak output bus hold acknowledge output pcm2 hldrq input bus hold request input pcm3 intp10 p10/uclk intp11 p11/sck0 intp21 p21/rxd1 intp22 p22/txd1 intp23 p23/sck1 intp24 p24/si1 intp25 p25/so1 intp50 p50/dmarq0 intp51 p51/dmaak0 intp52 p52/tc0 intp65 p65/tic1/intpc10 intp66 p66/intpc11 intp67 p67/toc1 intpd0 pdh0/d16 intpd1 pdh1/d17 intpd2 pdh2/toc4/d18 intpd3 pdh3/d19 intpd4 pdh4/d20 intpd5 pdh5/toc5/d21 intpd6 pdh6/intp100/tcud10/d22 intpd7 pdh7/intp101/tclr10/d23 intpd8 pdh8/to10/d24 intpd9 pdh9/tiud10/d25 intpd10 input external maskable interrupt request input pdh10/intp110/tcud11/d26 chapter 2 pin functions 35 user?s manual u16031ej3v0ud (3/5) pin name i/o function alternate function intpd11 pdh11/intp111/tclr11/d27 intpd12 pdh12/to11/d28 intpd13 pdh13/tiud11/d29 intpd14 pdh14/pwm0/d30 intpd15 pdh15/pwm1/d31 intpl0 pal0/a0 intpl1 input external maskable interrupt request input pal1/a1 intp100 pdh6/tcud10/d22/intpd6 intp101 input timer enc10 external capture trigger input pdh7/tclr10/d23/intpd7 intp110 pdh10/tcud11/d26/intpd10 intp111 input timer enc11 external capture trigger input pdh11/tclr11/d27/intpd11 intpc00 p53/tic0/dmarq1 intpc01 external maskable interrupt request input/timer c0 external capture trigger input p54/dmaak1 intpc10 p65/intp65/tic1 intpc11 external maskable interrupt request input/timer c1 external capture trigger input p66/intp66 intpc20 p72/tic2/dmarq2 intpc21 external maskable interrupt request input/timer c2 external capture trigger input p73/dmaak2 intpc30 p75/tic3/dmarq3 intpc31 input external maskable interrupt request input/timer c3 external capture trigger input p76/dmaak3 iord output dma read strobe signal output pcs5/cs5 iowr output dma write strobe signal output pcs2/cs2 iv dd 1.5 v positive power supply for internal unit ? iv ss ? ground potential for internal unit ? jit0 ? jit1 input specifying sscg operating mode ? llbe output external data bus byte enable signal output (lowest byte (d0 to d7)) pct0/lldqm/llwr lldqm output output disable/write mask signal output for sdram (lowest byte (d0 to d7)) pct0/llwr/llbe llwr output external data bus write strobe signal output (lowest byte (d0 to d7)) pct0/llbe/lldqm lube output external data bus byte enable signal output (third byte (d8 to d15)) pct1/ludqm/luwr ludqm output output disable/write mask signal output for sdram (third byte (d8 to d15)) pct1/luwr/lube luwr output external data bus write strobe signal output (third byte (d8 to d15)) pct1/lube/ludqm mode0 ? mode1 input specifying v850e/me2 operating mode ? nmi input non-maskable interrupt request signal input p20 oscv dd 3.3 v positive power supply for oscillator ? oscv ss ? ground potential for oscillator ? pllsel input input specifying pll operating mode ? chapter 2 pin functions 36 user?s manual u16031ej3v0ud (4/5) pin name i/o function alternate function pllv dd 1.5 v positive power supply for pll synthesizer ? pllv ss ? ground potential for pll synthesizer ? pwm0 pdh14/d30/intpd14 pwm1 output pwm pulse signal output pdh15/d31/intpd15 rd output external data bus read strobe signal output pct4 refrq output refresh request signal output for sdram pcm4 reset input system reset input ? rxd0 p12/si0 rxd1 input uartb0 and uartb1 serial receive data input p21/intp21 sck0 p11/intp11 sck1 i/o csi30 and csi31 serial clock i/o (3-wire) p23/intp23 sdcas output column address strobe signal output for sdram pcd2 sdcke output sdram clock enable signal output pcd0 sdras output row address strobe signal output for sdram pcd3 selfref input self-refresh request input for sdram pcm5/adtrg si0 p12/rxd0 si1 input csi30 and csi31 serial receive data input (3-wire) p24/intp24 so0 p13/txd0 so1 output csi30 and csi31 serial transmit data output (3-wire) p25/intp25 ssel0 ? ssel1 input specifying the clock generator?s operating mode ? tc0 p52/intp52 tc1 p55/toc0 tc2 p74/toc2 tc3 output dma transfer end (terminal count) signal output p77/toc3 tclr10 pdh7/d23/intpd7/intp101 tclr11 input clear signal input to timer enc10 and enc11 pdh11/d27/intpd11/intp111 tcud10 pdh6/d22/intpd6/intp100 tcud11 input count operation switching signal input to timer enc10 and enc11 pdh10/d26/intpd10/intp110 tic0 p53/dmarq1/intpc00 tic1 p65/intp65/intpc10 tic2 p72/intpc20/dmarq2 tic3 input external count clock input of timer c0 to c3 p75/intpc30/dmarq3 tiud10 pdh9/d25/intpd9 tiud11 input external count clock input to timer enc10 and enc11 pdh13/d29/intpd13 to10 pdh8/d24/intpd8 to11 output pulse signal output of timer enc10 and enc11 pdh12/d28/intpd12 chapter 2 pin functions 37 user?s manual u16031ej3v0ud (5/5) pin name i/o function alternate function toc0 p55/tc1 toc1 p67/intp67 toc2 p74/tc2 toc3 p77/tc3 toc4 pdh2/d18/intpd2 toc5 output pulse signal output of timer c0 to c5 pdh5/d21/intpd5 trcclk output trace clock output ? trcdata0 output ? trcdata1 output ? trcdata2 output ? trcdata3 output trace data output (d0 to d3) ? trcend output trace end status output ? txd0 p13/so0 txd1 output uartb0 and uartb1 serial transmit data output p22/intp22 uclk note input usb clock signal input p10/intp10 udm i/o usb data i/o ( ? ) ? udp i/o usb data i/o (+) ? ulbe output external data bus byte enable signal output (second byte (d16 to d23)) pct2/uldqm/ulwr uldqm output output disable/write mask signal output for sdram (second byte (d16 to d23)) pct2/ulwr/ulbe ulwr output external data bus write strobe signal output (second byte (d16 to d23)) pct2/ulbe/uldqm uube output external data bus byte enable signal output (highest byte (d24 to d31)) pct3/uuwr/uudqm uudqm output output disable/write mask signal output for sdram (highest byte (d24 to d31)) pct3/uuwr/uube uuwr output external data bus write strobe signal output (highest byte (d24 to d31)) pct3/uudqm/uube uv dd ? 3.3 v positive power supply for usb ? wait input control signal input that inserts a wait in the bus cycle pcm0 we output write enable signal output for sdram pct5/wr wr output write strobe signal output for sdram pct5/we x1 input ? x2 ? connects the crystal resonator for system clock oscillation. ? note when using as the uclk pin, be careful to avoid the inpu t of a staircase waveform due to reflection, etc., or the input of noise. chapter 2 pin functions 38 user?s manual u16031ej3v0ud 2.2 pin status the status of each pin after reset, in power-save mo de (software stop, idle, halt modes), and during dma transfer, refresh, and bus hold (th) is shown below. operating status pin reset idle mode/software stop mode halt mode/during dma transfer, refresh bus hold (th) note 1 a0 to a1 (pal0 to pal1) hi-z hi-z operating hi-z a2 to a15 hi-z hi-z operating hi-z a16 to a25 (pah0 to pah9) hi-z hi-z operating hi-z d0 to d15 hi-z hi-z operating hi-z d16 to d31 (pdh to pdh15) hi-z hi-z operating hi-z cs0 to cs7 (pcs0 to pcs7) hi-z h operating hi-z iowr (pcs2) h operating hi-z iord (pcs5) h operating hi-z llwr, luwr, ulwr, uuwr (pct0 to pct3) hi-z h operating hi-z llbe, lube, ulbe, uube (pct0 to pct3) h operating hi-z lldqm, ludqm, uldqm, uudqm (pct0 to pct3) h operating hi-z rd (pct4) hi-z h operating hi-z wr (pct5) hi-z h operating hi-z we (pct5) h operating hi-z bcyst (pct7) hi-z h operating hi-z wait (pcm0) hi-z ? operating ? hldak (pcm2) hi-z h operating l hldrq (pcm3) hi-z ? operating operating refrq (pcm4) hi-z operating note 2 operating operating selfref (pcm5) hi-z ? operating operating sdcke (pcd0) hi-z l note 2 operating operating busclk (pcd1) operating l operating operating sdcas (pcd2) hi-z self operating hi-z sdras (pcd3) hi-z self operating hi-z dmaak0 (p51) h operating h dmaak1 (p54) h operating h dmaak2 (p73) h operating h dmaak3 (p76) h operating h peripheral function input pin other than above ? operating operating peripheral function output pin other than above hold operating operating port input pin other than above hi-z ? ? operating port output pin other than above hold hold operating remark explanation on note and remark are given on the next page. chapter 2 pin functions 39 user?s manual u16031ej3v0ud notes 1. the pin set in the port mode hold s the status immediately before. 2. high-level output when the sdram controller is not used remark hi-z: high-impedance h: high-level output l: low-level output ? : no sampling of input : no select function at reset self: self-refresh state when pins are connected to sdram notes on turning on/off power the v850e/me2 has two power supply pins: a power supply pin for internal units (iv dd ) and a power supply pin for external pins (ev dd ). the i/o status of an alternate-functi on i/o pin may be undefined outside the range in which the operation is guaranteed. if this un defined i/o status affects the system, the pin can be made to go into a high-impedance state usi ng the following measure. ? when turning on power keep the voltage on the ev dd pin at 0 v until the voltage on the iv dd pin reaches the operation guaranteed range (1.35 to 1.65 v). ? when turning off power keep the voltage on the iv dd pin to within the operation guaranteed ran ge (1.35 to 1.65 v) until the voltage on the ev dd pin drops to 0 v. 1.35 v 0 v 0 v iv dd ev dd reset (input) 1.35 v oscillation stabilization time chapter 2 pin functions 40 user?s manual u16031ej3v0ud 2.3 description of pin functions (1) p10 to p13 (port 1) 3-state i/o p10 to p13 function as a 4-bit i/o port that ca n be set to input or output in 1-bit units. besides functioning as an i/o port, in the control mode, these pins operate as serial interface i/o (uartb0, csi30), usb clock signal input, and external interrupt request input. the operation mode can be set to port or control mode in 1-bit units, specified by the port 1 mode control register (pmc1). (a) port mode p10 to p13 can be set to input or output in 1- bit units using the port 1 mode register (pm1). (b) control mode p10 to p13 can be set to port/control mode in 1-bit units using the pmc1 register. (i) intp10, intp11 (interrupt re quest from peripherals) input these are external interrupt request input pins. (ii) so0 (serial output) output this is a serial transmit data output pin of csi30. (iii) si0 (serial input) input this is a serial receive data input pin of csi30. (iv) sck0 (serial clock) 3-state i/o this is a csi30 serial clock i/o pin. (v) txd0 (transmit data) output this is a serial transmit data output pin of uartb0. (vi) rxd0 (receive data) input this is a serial receive data input pin of uartb0. (vii) uclk (usb clock) input this is a clock input pin of the usb. when using as the uclk pin, be careful to avoid the input of a staircase waveform due to reflection, etc., or the input of noise. chapter 2 pin functions 41 user?s manual u16031ej3v0ud (2) p20 to p25 (port 2) 3-state i/o port 2, except p20, which is an i nput pin dedicated to checki ng the input status of nmi, is a 5-bit i/o port that can be set to input or output in 1-bit units. besides functioning as an i/o port, in the control mode, these pins operate as serial interface i/o (uartb1/csi31) and external interrupt request input. the operation mode can be set to port or control mode in 1-bit units, specified by the port 2 mode control register (pmc2). (a) port mode p21 to p25 can be set to input or output in 1-bit unit s using the port 2 mode register (pm2). p20 is an input port dedicated to checking the nmi input status, and if a valid edge is input, it operates as an nmi input. (b) control mode p21 to p25 can be set to port/control mode in 1-bit units using the pmc2 register. (i) nmi (non-maskable inte rrupt request) input this is the non-maskable interrupt request input pin. (ii) intp21 to intp25 (interrupt request from peri pherals) input these are external interrupt request input pins. (iii) so1 (serial output) output this is a serial transmit data output pin of csi31. (iv) si1 (serial input) input this is a serial receive data input pin of csi31. (v) sck1 (serial clock) 3-state i/o this is a csi31 serial clock i/o pin. (vi) txd1 (transmi t data) output this is a serial transmit data output pin of uartb1. (vii) rxd1 (receive data) input this is a serial receive data input pin of uartb1. chapter 2 pin functions 42 user?s manual u16031ej3v0ud (3) p50 to p55 (port 5) 3-state i/o p50 to p55 function as a 6-bit i/o port that ca n be set to input or output in 1-bit units. besides functioning as an i/o port, in the control mode, these pins operate as dma request input, dma acknowledge output, dma transfer te rmination output (terminal count), real-time pulse unit (rpu) i/o, and external interrupt request input. the operation mode can be set to port or control mode in 1-bit units, specified by the port 5 mode control register (pmc5). (a) port mode p50 to p55 can be set to input or output in 1-bi t units using the port 5 mode register (pm5). (b) control mode p50 to p55 can be set to port/control mode in 1-bit units using the pmc5 register. (i) dmarq0, dmarq1 (dma request) input these are dma service request signal input pins. they correspond to dma channels 0 and 1, respectively, and operate independently of each ot her. the priority order is fixed to dmarq0 > dmarq1 > dmarq2 > dmarq3. these signals are sampled at the rising edge of the busclk signal. maintain an active level until a dma request is acknowledged. (ii) dmaak0, dmaak1 (dma acknowledge) output these are acknowledge signal output pins that show a dma servic e request was granted. they correspond to dma channels 0 and 1, respective ly, and operate independently of each other. in flyby transfer, these signals become active when external memory is being accessed and internal instruction ram (in the write mode) is being a ccessed. when dma transfers are being executed between internal data ram, internal instruction ram (in the read mode), and on-chip peripheral i/o, they do not become active. in 2-cycle transfer, these are used as the signals to control the dmarq0 and dmarq1 signals. (iii) tc0, tc1 (terminal count) output these are terminal count signal output pins that sh ow that the dma transfer from the dma controller is complete. these pins correspond to dma channels 0 and 1 respectively, and operate independently of each other. the terminal count signals of dma channels 0 to 3 can be commonly output from the tc0 pin. (iv) intpc00, intpc01 (interrupt request from peripherals) input these are external interrupt request input pins and the external capture trigger input pins of timer c0. (v) tic0 (timer input) input this is an external count clock input pin of timer c0. (vi) toc0 (timer output) output this is a pulse signal output pin of timer c0. (vii) intp50 to intp52 (interrupt request from peri pherals) input these are external interrupt request input pins. chapter 2 pin functions 43 user?s manual u16031ej3v0ud (4) p65 to p67 (port 6) 3-state i/o p65 to p67 function as a 3-bit i/o port that ca n be set to input or output in 1-bit units. besides functioning as an i/o port, in the control mode, these pins operate as real -time pulse unit (rpu) i/o and external interrupt request input. the operation mode can be set to port or control mode in 1-bit units, specified by the port 6 mode control register (pmc6). (a) port mode p65 to p67 can be set to input or output in 1- bit units using the port 6 mode register (pm6). (b) control mode p65 to p67 can be set to port/control mode in 1-bit units using the pmc6 register. (i) tic1 (timer input) input this is the external count clock input pin for timer c1. (ii) toc1 (timer output) output this is the pulse signal output pin for timer c1. (iii) intp65 to intp67 (interrupt request from peri pherals) input these are external interrupt request input pins. (iv) intpc10, intpc11 (interrupt request from peripherals) input these are external interrupt request input pins and the external capture trigger input pins of timer c1. chapter 2 pin functions 44 user?s manual u16031ej3v0ud (5) p72 to p77 (port 7) 3-state i/o p72 to p77 function as a 6-bit i/o port that ca n be set to input or output in 1-bit units. besides functioning as an i/o port, in the control mode, these pins operate as dma request input, dma acknowledge output, dma transfer te rmination output (terminal count), real-time pulse unit (rpu) i/o, and external interrupt request input. the operation mode can be set to port or control mode in 1-bit units, specified by the port 7 mode control register (pmc7). (a) port mode p72 to p77 can be set to input or output in 1- bit units using the port 7 mode register (pm7). (b) control mode p72 to p77 can be set to port/control mode in 1-bit units using the pmc7 register. (i) dmarq2, dmarq3 (dma request) input these are dma service request signal input pins. they correspond to dma channels 2 and 3, respectively, and operate independently of each ot her. the priority order is fixed to dmarq0 > dmarq1 > dmarq2 > dmarq3. these signals are sampled at the rising edge of the busclk signal. maintain an active level until a dma request is acknowledged. (ii) dmaak2, dmaak3 (dma acknowledge) output these are acknowledge signal output pins that show a dma servic e request was granted. they correspond to dma channels 2 and 3, respective ly, and operate independently of each other. in flyby transfer, these signals become active only when external memory is being accessed and internal instruction ram (in the write mode) is being accessed. when dma transfers are being executed between internal data ram, internal instruction ram (in the read mode), and on-chip peripheral i/o, they do not become active. in 2-cycle transfer, these are used as the signals to control the dmarq2 and dmarq3 signals. (iii) tc2, tc3 (terminal count) output these are terminal count signal ou tput pins that show that dma tr ansfer from the dma controller is complete. these pins correspond to dma channels 2 and 3 respectively, and operate independently of each other. the terminal count signals of dma channels 0 to 3 can be commonly output from the tc0 pin. (iv) intpc20, intpc21, intpc30, intpc31 (interrupt request from peripherals) input these are external interrupt request input pins and th e external capture trigger input pins of timers c2 and c3. (v) tic2, tic3 (timer input) input these are external count clock input pins of timers c2 and c3. (vi) toc2, toc3 (timer output) output these are pulse signal output pins of timers c2 and c3. chapter 2 pin functions 45 user?s manual u16031ej3v0ud (6) pcm0 to pcm5 (port cm) 3-state i/o pcm0 to pcm5 function as a 6-bit i/o port that can be set to input or output in 1-bit units. besides functioning as a port, in the control mode, thes e pins operate as wait insertion signal input, bus hold control signal, refresh request signal output for sdram, self-refresh request signal input, and a/d converter external trigger input. the operation mode can be set to port or control in 1-bit units, specified by the por t cm mode control register (pmccm). (a) port mode pcm0 to pcm5 can be set to input or output in 1- bit units using the port cm mode register (pmcm). (b) control mode pcm0 to pcm5 can be set to port/control mode in 1-bit units using the pmccm register. (i) wait (wait) input this is the control signal input pi n at which a data wait is inserted in the bus cycle. the wait signal can be input asynchronously to the busclk signal. when the busclk signal falls, sampling is executed. when the set/hold time is not terminat ed within the sampling timing, wait insertion may not be executed. caution input to the wait pin is valid immediately after reset rel ease. if a low level is input to the wait pin because an external pull-do wn resistor is connected to it, the external bus is placed in the bus hold status. (ii) hldak (hold ack nowledge) output this is the acknowledge signal output pin that i ndicates the high impedance status for the address bus, data bus, and control bus when the v8 50e/me2 receives a bus hold request. while this signal is active, the impedance of the address bus, data bus, and control bus becomes high and the bus mastership is transferred to the external bus master. (iii) hldrq (hold request) input this is the input pin through which an external device requests the v850e/me2 to release the address bus, data bus, and control bus. the hldrq signal can be input asynchronously to the busclk signal. when this pin is active, the address bus, data bus, and control bus are set to the high impedance status. this occurs either when the v850e/me2 completes execution of the current bus cycle or immediately if no bus cycle is being ex ecuted, then the hldak signal is set as active and the bus is released. in order to make the bus hold state secure, k eep the hldrq signal active until the hldak signal is output. caution input to the hldrq pin is valid immediat ely after reset release. if a low level is input to the hldrq pin becau se an external pull-down resist or is connected to it, the external bus is placed in the bus hold status. chapter 2 pin functions 46 user?s manual u16031ej3v0ud (iv) refrq (refresh request) output this is the refresh request signal output pin for sdram. this signal becomes active during the refresh cycle. also, during bus hold, it becomes active when a refresh request is generated and informs the exte rnal bus master that a refresh request was generated. in cases when external simms are connected, this signal is used for ras control during the refresh cycle. (v) selfref (self refresh request) input this is a self-refresh request signal input pin for sdram. the internal data ram and internal instruction ram (in the read mode) can be accessed even in the self-refresh cycle. however, acce ss to a peripheral i/o register or external device is held pending until the self-refresh cycle is cancelled. caution input to the selfref pin becomes valid immediately after the reset signal has been cleared. consequently, if a low level is input to the selfref pin by an external pull-down resistor, self refreshi ng is started. note that, at this time, the normal instruction fetch cycle does not occur. (vi) adtrg (a/d trigger input) input this is an external trigger input pin of the a/d converter. (7) pct0 to pct5, pct7 (port ct) 3-state i/o pct0 to pct5 and pct7 function as a 7-bit i/o port t hat can be set to input or output in 1-bit units. besides functioning as a port, in the control mode, these pins operate as control signal outputs for when memory is expanded externally. the operation mode can be set to port or control mode in 1-bit units, specified by the port ct mode control register (pmcct). (a) port mode pct0 to pct5 and pct7 can be set to input or output in 1-bit units using the port ct mode register (pmct). (b) control mode pct0 to pct5 and pct7 can be set to port/control mode in 1-bit units using the pmcct register. (i) llwr (lower lower byte write strobe) 3-state output this is a strobe signal output pin that shows whether the bus cycl e currently being executed is a write cycle for the sram, external rom, or external peripheral i/o area. for the data bus, the lowest byte (d0 to d7) becomes valid. if the bus cycle is a lowest memory write, it becomes active at t he falling edge of the busclk sign al in the t1 state and becomes inactive at the falling edge of the busclk signal in the t2 state. chapter 2 pin functions 47 user?s manual u16031ej3v0ud (ii) luwr (lower upper byte write strobe) 3-state output this is a strobe signal output pin that shows whether the bus cycl e currently being executed is a write cycle for the sram, external rom, or external peripheral i/o area. for the data bus, the third byte (d8 to d15) becomes valid. if the bus cycle is a third byte memory write, it becomes active at t he falling edge of the busclk sign al in the t1 state and becomes inactive at the falling edge of the busclk signal in the t2 state. (iii) ulwr (upper lower byte write strobe) 3-state output this is a strobe signal output pin that shows whether the bus cycl e currently being executed is a write cycle for the sram, external rom, or external peripheral i/o area. for the data bus, the second byte (d16 to d23) becomes valid. if the bus cycle is a second byte memory write, it becomes active at the falling edge of the busclk signal in the t1 state and becomes inactive at the falling edge of t he busclk signal in the t2 state. (iv) uuwr (upper upper byte write strobe) 3-state output this is a strobe signal output pin that shows whether the bus cycl e currently being executed is a write cycle for the sram, external rom, or external peripheral i/o area. for the data bus, the highest byte (d24 to d31) be comes valid. if the bus cycle is a highest memory write, it becomes active at t he falling edge of the busclk sign al in the t1 state and becomes inactive at the falling edge of the busclk signal in the t2 state. (v) llbe (lower lower byte enable) 3-state output this is a signal output pin that enables the lowe st byte (d0 to d7) of the external data bus. (vi) lube (lower upper byte enable) 3-state output this is a signal output pin that enables the thir d byte (d8 to d15) of the external data bus. (vii) ulbe (upper lower byte enable) 3-state output this is a signal output pin that enables the second byte (d16 to d23) of the external data bus. (viii) uube (upper upper byte enable) 3-state output this is a signal output pin that enables the highes t byte (d24 to d31) of the external data bus. (ix) lldqm (lower lower dq mask enable) 3-state output this is a control signal output pin for the data bus to sdram. for the data bus, the lowest byte (d0 to d7) is valid. this signal carries out sdram out put disable control during a read operation, and sdram byte mask control during a write operation. (x) ludqm (lower upper dq mask enable) 3-state output this is a control signal output pin for the data bus to sdram. for the data bus, the third byte (d8 to d15) is valid. this signal carries out sdram out put disable control during a read operation, and sdram byte mask control during a write operation. (xi) uldqm (upper lower dq mask enable) 3-state output this is a control signal output pin for the data bus to sdram. for the data bus, the second byte (d16 to d23) is valid. this signal carries out sdram output disable control during a read operation, and sdram byte mask control during a write operation. chapter 2 pin functions 48 user?s manual u16031ej3v0ud (xii) uudqm (upper upper dq mask enable) 3-state output this is a control signal output pin for the data bus to sdram. for the data bus, the highest byte (d24 to d31) is valid. this signal carries out sdram output disable control during a read operation, and sdram byte mask control during a write operation. (xiii) rd (read strobe) 3-state output this is a strobe signal output pin that shows the bus cycle current ly being executed is a read cycle for the sram, external rom, external peripheral i/o, or page rom area. in the idle state (ti), it becomes inactive. (xiv) wr (write str obe) 3-state output this is a strobe signal output pin that shows the bus cycle current ly being executed is a write cycle for the sram, external rom, or external peripheral i/o area. it becomes active at the falling edge of the busclk signal in the t1 state and becomes inactive at the falling edge of the busclk signal in the t2 state. (xv) we (write enable) 3-state output this is a enable signal ou tput pin that shows the bus cycle curr ently being executed is a write cycle for the sdram area. in the idle state (ti), it becomes inactive. (xvi) bcyst (bus cycle start timing) 3-state output this is a status signal output pin that shows the start of the bus cycl e. it becomes active for 1-clock cycle from the start of each cycle. chapter 2 pin functions 49 user?s manual u16031ej3v0ud (8) pcs0 to pcs7 (port cs) 3-state i/o pcs0 to pcs7 function as an 8-bit i/o port that can be set to input or output in 1-bit units. besides functioning as a port, in the control mode, th ese pins operate as control signal outputs for when memory and peripheral i/o are expanded externally. the operation mode can be set to port or control mode in 1-bit units, specified by the port cs mode control register (pmccs). (a) port mode pcs0 to pcs7 can be set to input or output in 1- bit units using the port cs mode register (pmcs). (b) control mode pcs0 to pcs7 can be set to port/control mode in 1-bit units using the pmccs register. (i) cs0 to cs7 (chip select) 3-state output these are the chip select signal output pins for the sram, external rom, external peripheral i/o, and page rom area. the csn signal is assigned to memory block n (n = 0 to 7). it becomes active while the bus cycle that accesses the correspondi ng memory block is activated. in the idle state (ti), it becomes inactive. (ii) iowr (i/o write) 3-state output this is a write strobe signal output pin for exte rnal i/o during dma flyby transfer. it indicates whether the bus cycle currently be ing executed is a write cycle fo r external i/o during dma flyby transfer, or a write cycle for the sram area. note that if the ioen bit of the bus cycle period cont rol register (bcp) is set (1), this signal can be output even in the normal sram, exte rnal rom, or external i/o cycle. (iii) iord (i/o read) 3-state output this is a read strobe signal output pin for exte rnal i/o during dma flyby transfer. it indicates whether the bus cycle currently be ing executed is a read cycle for external i/o during dma flyby transfer, or a read cycle for the sram area. note that if the ioen bit of the bcp register is set (1), this signal can be output even in the normal sram, external rom, or external i/o cycle. chapter 2 pin functions 50 user?s manual u16031ej3v0ud (9) pcd0 to pcd3 (port cd) 3-state i/o pcd0 to pcd3 function as a 4-bit i/o port that can be set to input or output in 1-bit units. besides functioning as a port, in control mode, these pins operate as control signal outputs for when the memory and peripheral i/o are expanded externally. the operation mode can be set to port or control mode in 1-bit units, specified by the port cd mode control register (pmccd). (a) port mode pcd0 to pcd3 can be set to input or output in 1-bit units using the port cd mode register (pmcd). (b) control mode pcd0 to pcd3 can be set to port or control mode in 1-bit units using the pmccd register. (i) sdcke (sdram clock enable) output this is the sdram clock enable output signal. it becomes inactive in self-refresh and standby mode. (ii) busclk (clock output) output this is a clock output pin for sdram. (iii) sdcas (sdram column address strobe) 3-state output this is a command output signal for sdram. (iv) sdras (sdram row address strobe) 3-state output this is a command output signal for sdram. (10) pah0 to pah9 (port ah) 3-state i/o pah0 to pah9 function as an 8- or 10-bit i/o port that can be set to input or output in 1-bit units. besides functioning as a port, in control mode, these pins operate as an address bus (a16 to a25) for when the memory is expanded externally. the operation mode can be set to port or control mode in 1-bit units, specified by the port ah mode control register (pmcah). (a) port mode pah0 to pah9 can be set to input or output in 1-bi t units using the port ah mode register (pmah). (b) control mode pah0 to pah9 can be set to function alternately as a16 to a25 using the pmcah register. (i) a16 to a25 (address) 3-state output these are the address output pins of the higher 10 bits of the address bus?s 26-bit address when the external memory is accessed. the output changes in synchronization with the fall of t he busclk signal in the t1 state. in the idle state (ti), the address of the bus cycl e immediately before is retained. chapter 2 pin functions 51 user?s manual u16031ej3v0ud (11) pal0, pal1 (port al) 3-state i/o pal0 and pal1 function as a 2-bit i/o port that c an be set to input or output in 1-bit units. besides functioning as a port, in control mode, thes e pins operate as an address bus (a0, a1) and external interrupt request input for when the memory is expanded externally. the operation mode can be set to port or control mode in 1-bit units, specified by the port al mode control register (pmcal). (a) port mode pal0 and pal1 can be set to input or output in 1-bi t units using the port al mode register (pmal). (b) control mode pal0 and pal1 can be set to port or control m ode in 1-bit units using the pmcal register. (i) a0, a1 (address) 3-state output these are the address output pins of the lower 2 bi ts of the address bus?s 26-bit address when the external memory is accessed. the output changes in synchronization with the fall of t he busclk signal in the t1 state. in the idle state (ti), the address of the bus cycl e immediately before is retained. (ii) intpl0, intpl1 (interrupt request from peripherals) input these are external interrupt request input pins. chapter 2 pin functions 52 user?s manual u16031ej3v0ud (12) pdh0 to pdh15 (port dh) 3-state i/o pdh0 to pdh15 function as an 8- or 16-bit i/o port that can be set to input or output in 1-bit units. besides functioning as a port, in c ontrol mode, these pins operate as real-time pulse unit (rpu) i/o, pwm output, data bus (d16 to d31), and external interrupt request input. the operation mode can be set to port or control mode in 1-bit units, specified by the port dh mode control register (pmcdh). (a) port mode pdh0 to pdh15 can be set to input or output in 1- bit units using the port dh mode register (pmdh). (b) control mode pdh0 to pdh15 can be set to port or control mode in 1-bit units using the pmcdh register. (i) intpd0 to intpd15 (interrupt request from peripherals) input these are external interrupt request input pins. (ii) toc4, toc5 (timer output) output these are pulse signal output pins of timers c4 and c5. (iii) intp100, intp101, intp110, intp111 (t imer capture trigge r input) input these are external capture trigger input pins of timers enc10 and enc11. (iv) tiud10, tiud11 (timer count pulse input) input these are external count clock input pins of timers enc10 and enc11. (v) tcud10, tcud11 (timer control pulse input) input these are external count clock input pins of timers enc10 and enc11. (vi) tclr10, tclr11 (timer clear) input these are clear signal input pins of timers enc10 and enc11. (vii) to10, to11 (timer output) output these are pulse signal output pins of timers enc10 and enc11. (viii) pwm0, pwm1 (pulse width modulation) output these pins output the pwm pulse signal. (ix) d16 to d31 (data) 3-state i/o these pins constitute a data bus for when the exte rnal memory is accessed. these are the higher 16-bit i/o bus pins of the 32-bit data. the output changes in synchronization with the rise of the busclk signal in the t1 state. (13) pllsel (pll operating mode select) input this is an input pin used to specify the pll oper ating mode. fix the operating mode via a resistor. (14) pllv dd (pll power supply) this is an 1.5 v positive power supply pin for pll synthesizer. chapter 2 pin functions 53 user?s manual u16031ej3v0ud (15) pllv ss (pll ground) this is a ground pin for pll synthesizer. (16) ssel0, ssel1 (clock generator operating mode sel ect) input these are input pins used to specify the clock gener ator?s operating mode. fix the operating mode via a resistor. (17) jit0, jit1 (sscg (spread spectrum freque ncy synthesizer phase locked loop) clock generator operating mode select) input these are input pins used to specify the sscg operat ing mode. fix the operating mode via a resistor. (18) dck (debug clock) input this pin inputs a debug clock. at the rising edge of the dck signal, the dms and ddi signals are sampled, and data is output from the ddo pi n at the falling edge of the dck signal. keep this pin high when the debug function is not used. (19) ddi (debug data input) input this pin inputs debug data. this pin is sampled at the rising edge of the dck signal when the debug serial interface is in the shift state. data is input with t he lsb first. keep this pin high when the debug function is not used. (20) ddo (debug data output) 3-state output this pin outputs debug data. it outputs data at the fa lling edge of the dck signal when the debug serial interface is in the shift state. data is output with the lsb first. (21) dms (debug mode select) input this input pin selects a debug mode. depending on the level of the dms signal, the state machine of the debug serial interface changes. this pin is sampled at the rising edge of the dck signal. keep this pin high when the debug function is not used. (22) drst (debug reset) input this pin inputs a debug reset signal that is a negative-logic signal to initialize the dcu asynchronously. when this signal goes low, the dcu is reset/invalidat ed. keep this pin low when the debug function is not used. (23) mode0, mode1 (mode) input these are input pins used to specify the operat ing mode. fix the operating mode via a resistor. (24) reset (reset) input reset is a signal that is input asynchronously and t hat has a constant low level width regardless of the operating clock?s status. when this signal is input, a system reset is executed as the first priority ahead of all other operations. in addition to being used for ordinary initialization/star t operations, this pin can also be used to release a standby mode (halt, idle, or software stop). (25) x1, x2 (crystal) these pins are used to connect the res onator that generates the system clock. chapter 2 pin functions 54 user?s manual u16031ej3v0ud (26) ani0 to ani7 (analog input) input these are analog input pins for the a/d converter. connect a capacitor between these pins and av ss to prevent noise-related operation faults. also, do not apply voltage that is outside the range for av ss and av dd to pins that are being used as inputs for the a/d converter. if it is possible for noise above the av dd range or below the av ss to enter, clamp these pins using a diode that has a small v f value. (27) av refm , av refp (analog reference voltage) input these are reference voltage supply pins for the a/d converter. (28) av dd (analog power supply) this is a 3.3 v positive power s upply pin for the a/d converter. (29) av ss (analog ground) this is a ground pin for the a/d converter. (30) ev dd (port power supply) this is a 3.3 v positive power supply pin for port. (31) ev ss (port ground) this is a ground pin for port. (32) oscv dd (power supply for clock generator) this is a 3.3 v positive power s upply pin for the clock generator. (33) oscv ss (ground for clock generator) this is a ground pin for the clock generator. (34) uv dd (ground) this is a 3.3 v positive power supply pin for the usb. (35) udp (usb data +) i/o this is a data i/o pin (+) of the usb. (36) udm (usb data ? ? chapter 2 pin functions 55 user?s manual u16031ej3v0ud (40) d0 to d15 (data) 3-state i/o these pins constitute a data bus for when the external memory is accessed. these are the lower 16-bit i/o bus pins of the 32-bit data. the output changes in synchronization with the ri se of the busclk signal in the t1 state. (41) trcclk (trace clock) output this is a trace clock output pin. (42) trcdata0 to trcdata3 (trace data out put) output these are trace data output (d0 to d3) pins. (43) trcend (trace end status output) output this is a trace end status output pin. chapter 2 pin functions 56 user?s manual u16031ej3v0ud 2.4 pin i/o circuits and recommende d connection of unused pins it is recommended that 1 to 10 k ? resistors be used when connecting to v dd or v ss via resistors. (1/3) pin name i/o circuit type recommended connection p10/intp10/uclk 5 p11/intp11/sck0 p12/si0/rxd0 8-j p13/so0/txd0 5 input: independently connect to ev dd or ev ss via a resistor. output: leave open. p20/nmi 2 connect to v ss directly. p21/intp21/rxd1 8-j p22/intp22/txd1 5 p23/intp23/sck1 p24/intp24/si1 8-j p25/intp25/so1 5 input: independently connect to ev dd or ev ss via a resistor. output: leave open. p50/intp50/dmarq0 5 input: independently connect to ev dd via a resistor. output: leave open. p51/intp51/dmaak0 p52/intp52/tc0 5 input: independently connect to ev dd or ev ss via a resistor. output: leave open. p53/intpc00/tic0/dmarq1 5 input: independently connect to ev dd via a resistor. output: leave open. p54/intpc01/dmaak1 p55/toc0/tc1 p65/intp65/intpc10/tic1 p66/intp66/intpc11 p67/intp67/toc1 5 input: independently connect to ev dd or ev ss via a resistor. output: leave open. p72/intpc20/tic2/dmarq2 5 input: independently connect to ev dd via a resistor. output: leave open. p73/intpc21/dmaak2 p74/toc2/tc2 5 input: independently connect to ev dd or ev ss via a resistor. output: leave open. p75/intpc30/tic3/dmarq3 5 input: independently connect to ev dd via a resistor. output: leave open. p76/intpc31/dmaak3 p77/toc3/tc3 pal0/intpl0/a0, pal1/intpl1/a1 pah0/a16 to pah9/a25 5 input: independently connect to ev dd or ev ss via a resistor. output: leave open. chapter 2 pin functions 57 user?s manual u16031ej3v0ud (2/3) pin name i/o circuit type recommended connection pdh0/d16/intpd0 pdh1/d17/intpd1 pdh2/d18/intpd2/toc4 pdh3/d19/intpd3 pdh4/d20/intpd4 pdh5/d21/intpd5/toc5 pdh6/d22/intpd6/intp100/tcud10 pdh7/d23/intpd7/intp101/tclr10 pdh8/d24/intpd8/to10 pdh9/d25/intpd9/tiud10 pdh10/d26/intpd10/intp110/tcud11 pdh11/d27/intpd11/intp111/tclr11 pdh12/d28/intpd12/to11 pdh13/d29/intpd13/tiud11 pdh14/d30/intpd14/pwm0 pdh15/d31/intpd15/pwm1 pcs0/cs0 pcs1/cs1 pcs2/cs2/iowr pcs3/cs3 pcs4/cs4 pcs5/cs5/iord pcs6/cs6 pcs7/cs7 pct0/llwr/llbe/lldqm pct1/luwr/lube/ludqm pct2/ulwr/ulbe/uldqm pct3/uuwr/uube/uudqm pct4/rd pct5/we/wr pct7/bcyst 5 input: independently connect to ev dd or ev ss via a resistor. output: leave open. pcm0/wait 5 input: independently connect to ev dd via a resistor. output: leave open. pcm1 8-j pcm2/hldak 5 input: independently connect to ev dd or ev ss via a resistor. output: leave open. chapter 2 pin functions 58 user?s manual u16031ej3v0ud (3/3) pin name i/o circuit type recommended connection pcm3/hldrq 5 input: independently connect to ev dd via a resistor. output: leave open. pcm4/refrq 5 input: independently connect to ev dd or ev ss via a resistor. output: leave open. pcm5/adtrg/selfref 5 input: independently connect to ev dd via a resistor. output: leave open. pcd0/sdcke pcd1/busclk pcd2/sdcas pcd3/sdras a2 to a15 d0 to d15 5 input: independently connect to ev dd or ev ss via a resistor. output: leave open. av dd ? connect to ev dd . av ss ? connect to ev ss . dck ddi dms 1 connect to ev dd via a resistor. ddo 1 leave open. drst 1 connect to ev ss . trcclk 1 trcdata0 to trcdata3 1 trcend 1 leave open. uv dd ? connect to ev dd . udm udp 24-a ani0 to ani7 9-e av refm ? connect to ev ss . av refp ? connect to ev dd . chapter 2 pin functions 59 user?s manual u16031ej3v0ud 2.5 pin i/o circuits type 1 type 2 type 5 p-ch n-ch in v dd in schmitt-triggered input with hysteresis characteristics p-ch n-ch v dd in/out data output disable input enable type 8-j p-ch n-ch v dd in/out data output disable type 9-e type 24-a in av ref av ss + ? output data output data input data uv dd p-ch n-ch in/out ev ss 60 user?s manual u16031ej3v0ud chapter 3 cpu function the cpu of the v850e/me2 is based on risc architecture and executes almost all the instructions in one clock cycle using 5-stage pipeline control. 3.1 features minimum instruction execution time: 10 ns/7.5 ns/6 .7 ns (@100 mhz/133 mhz/150 mhz internal operation) memory space program space: 64 mb linear data space: 4 gb linear thirty-two 32-bit general-purpose registers internal 32-bit architecture five-stage pipeline control multiply/divide instructions saturated operation instructions one-clock 32-bit shift instruction load/store instruction with long/short format four types of bit manipulation instructions set1 clr1 not1 tst1 chapter 3 cpu function 61 user?s manual u16031ej3v0ud 3.2 cpu register set the registers of the v850e/me2 can be classified into tw o categories: a general-purpose program register set and a dedicated system register set. a ll the registers have a 32-bit width. for details, refer to v850e1 architecture user?s manual . figure 3-1. cpu register set (1) program register set (2) system register set r0 (zero register) r1 (assembler-reserved register) r2 r3 (stack pointer (sp)) r4 (global pointer (gp)) r5 (text pointer (tp)) r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 (element pointer (ep)) r31 (link pointer (lp)) 31 0 pc (program counter) 31 0 eipc (status saving register during interrupt) eipsw (status saving register during interrupt) fepc (status saving register during nmi) fepsw (status saving register during nmi) ecr (interrupt source register) psw (program status word) ctpc (status saving register during callt execution) ctpsw (status saving register during callt execution) dbpc (status saving register during exception/debug trap) dbpsw (status saving register during exception/debug trap) ctbp (callt base pointer) 31 0 chapter 3 cpu function 62 user?s manual u16031ej3v0ud 3.2.1 program register set the program register set includes general -purpose registers and a program counter. (1) general-purpose registers thirty-two general-purpose registers, r0 to r31, are av ailable. any of these registers can be used as a data variable or address variable. however, r0 and r30 are implicitly used by instruct ions, and care must be exercised when using these registers. r0 is a register that always holds 0, and is used for operations using 0 and offset 0 addressing. r30 is used, by means of the sld and sst instructions, as a base pointer for when memory is accessed. also, r1, r3 to r5, and r31 are implicitly used by the as sembler and c compiler. ther efore, before using these registers, their contents must be save d so that they are not lost. th e contents must be restored to the registers after the registers have been used. r2 may be used by the real-time os. if the real-time os does not use r2, it can be used as a variable register. table 3-1. program registers name usage operation r0 zero register always holds 0 r1 assembler-reserved register working register for genera ting 32-bit immediate data r2 address/data variable register (when r2 is not used by the real-time os) r3 stack pointer used to generate stack frame when function is called r4 global pointer used to acce ss global variable in data area r5 text pointer register to indicate the start of the text area (where program code is located) r6 to r29 address/dat a variable registers r30 element pointer base pointer when memory is accessed r31 link pointer used by compiler when calling function pc program counter holds instruction address during program execution (2) program counter (pc) this register holds the instruction address during program execution. the lower 26 bi ts of this register are valid, and bits 31 to 26 are fixed to 0. if a carry occurs from bit 25 to 26, it is ignored. bit 0 is fixed to 0, and branching to an odd address cannot be performed. 31 26 25 1 0 pc fixed to 0 instruction address during execution 0 after reset 00100000h chapter 3 cpu function 63 user?s manual u16031ej3v0ud 3.2.2 system register set system registers control the status of the cpu and hold interrupt information. to read/write these system r egisters, specify a system register number indicated below using the system register load/store instruction (lds r or stsr instruction). table 3-2. system register numbers operand specification no. system register name ldsr instruction stsr instruction 0 status saving register during interrupt (eipc) note 1 { { 1 status saving register during interrupt (eipsw) note 1 { { 2 status saving register during nmi (fepc) { { 3 status saving register during nmi (fepsw) { { 4 interrupt source register (ecr) { 5 program status word (psw) { { 6 to 15 reserved for future function ex pansion (operations that access these register numbers cannot be guaranteed). 16 status saving register du ring callt execution (ctpc) { { 17 status saving register du ring callt execution (ctpsw) { { 18 status saving register du ring exception/debug trap (dbpc) { note 2 { 19 status saving register during exception/debug trap (dbpsw) { note 2 { 20 callt base pointer (ctbp) { { 21 to 31 reserved for future function ex pansion (operations that access these register numbers cannot be guaranteed). notes 1. because these registers have only one set, to enable multiple interrupts, it is necessary to save these registers by program. 2. these registers can be accessed only in the debug mode. if they are accessed in the user mode, the result is undefined. caution even if bit 0 of eipc, fepc, or ctpc is set to 1 by the ldsr instruction, bit 0 will be ignored when the program is returned by the reti instruction after in terrupt servicing (because bit 0 of the pc is fixed to 0). when setting the value of eipc, fepc, and ctpc, use an even value (bit 0 = 0) unless there is a special reason not to. remark { : access allowed : access prohibited chapter 3 cpu function 64 user?s manual u16031ej3v0ud (1) interrupt source register (ecr) 31 0 ecr fecc eicc after reset 00000000h 16 15 bit position bit name function 31 to 16 fecc exception code of non-maskable interrupt (nmi) 15 to 0 eicc exception code of exception/maskable interrupt (2) program status word (psw) (1/2) 31 0 1 2 3 4 5 6 7 8 psw rfu np ep id sat cy ov sz after reset 00000020h bit position flag function 31 to 8 rfu reserved field (fixed to 0). 7 np indicates that non-maskable interrupt (nmi ) servicing is in prog ress. this flag is set when an nmi is acknowledged, and disables multiple interrupts. 0: nmi servicing not under execution. 1: nmi servicing under execution. 6 ep indicates that exception processing is in progress. this flag is set when an exception is generated. moreover, interrupt requests can be acknowledged when this bit is set. 0: exception processing not under execution. 1: exception processing under execution. 5 id indicates whether a maskable interrupt request can be acknowledged or not. 0: interrupt enabled (ei). 1: interrupt disabled (di). chapter 3 cpu function 65 user?s manual u16031ej3v0ud (2/2) bit position flag function 4 sat note indicates that the operation result of a saturated operation processing instruction is saturated due to overflow. due to the cumulative flag, if the operation result is saturated by the saturation operation instruction, this bit is set (1), but is not cleared (0) even if the operation results of subsequent instructions are not saturated. to clear (0) this bit, load data in psw. note that in a general arithmetic operation, this bit is neither set (1) nor cleared (0). 0: not saturated. 1: saturated. 3 cy this flag is set if a carry or borrow occurs as the result of an operation (if a carry or borrow does not occur, it is reset). 0: carry or borrow does not occur. 1: carry or borrow occurs. 2 ov note this flag is set if an overflow occurs during operation (if an overflow does not occur, it is reset). 0: overflow does not occur. 1: overflow occurs. 1 s note this flag is set if the result of an operati on is negative (it is reset if the result is positive). 0: the operation result was positive or 0. 1: the operation result was negative. 0 z this flag is set if the result of an operati on is zero (if the result is not zero, it is reset). 0: the operation result was not 0. 1: the operation result was 0. note the result of a saturation-processed operation is dete rmined by the contents of the ov and s flags in the saturation operation. simply setting the ov flag (1 ) will set the sat flag (1) in a saturation operation. flag status status of operation result sat ov s saturation-processed operation result maximum positive value exceeded 1 1 0 7fffffffh maximum negative value exceeded 1 1 1 80000000h positive (not exceeding the maximum) 0 negative (not exceeding the maximum) retains the value before operation 0 1 operation result itself chapter 3 cpu function 66 user?s manual u16031ej3v0ud 3.3 operating modes 3.3.1 operating modes the v850e/me2 has the following operating modes. m ode specification is carri ed out using the mode0 and mode1 pins. (1) normal operation mode 32-bit mode, 16-bit mode after system reset is cleared, each pi n related to the bus interface enter s the control mode, the sram cycle branches to 0100000h (reset entry address) of the ex ternal device (memory), and instruction processing starts. in the 32-bit mode, the bus interface functions as a 32 -bit data bus; it functions as a 16-bit data bus in the 16-bit mode. caution be sure to allocate external memory to address 0100000h for correct operation. 3.3.2 operating mode specification the operating mode is specif ied according to the status of the mode0 and mode1 pins. in an application system fix the specification of these pins and do not change them durin g operation. operation is not guaranteed if these pins are changed during operation. mode1 mode0 operating mode remarks l l 32-bit mode 32-bit data bus l h normal operation mode 16-bit mode 16-bit data bus other than above setting prohibited remark l: low-level input h: high-level input chapter 3 cpu function 67 user?s manual u16031ej3v0ud 3.4 address space 3.4.1 cpu address space the cpu of the v850e/me2 is of 32-bit architecture and supports up to 4 gb of linear address space (data space) during operand addressing (data access). also, in instru ction address addressing, a maximum of 64 mb of linear address space (program space) is supported. figure 3-2 shows the cpu address space. figure 3-2. cpu address space ffffffffh 04000000h 03ffffffh 00000000h data area (4 gb linear) program area (64 mb linear) cpu address space chapter 3 cpu function 68 user?s manual u16031ej3v0ud 3.4.2 image a 256 mb physical address space is seen as 16 images in the 4 gb cpu address space. in actuality, the same 256 mb physical address space is accessed regardless of the values of bits 31 to 28 of the cpu address. figure 3-3 shows the image of the virtual addressing space. physical address x0000000h can be seen as cpu address 00000000h, and in addition, can be seen as address 10000000h, address 20000000h, ? , address e0000000h, or address f0000000h. figure 3-3. images on address space ffffffffh f0000000h efffffffh 00000000h internal instruction ram image image image internal data ram peripheral i/o external memory physical address space fffffffh 0000000h image image e0000000h dfffffffh 20000000h 1fffffffh 10000000h 0fffffffh cpu address space chapter 3 cpu function 69 user?s manual u16031ej3v0ud 3.4.3 wrap-around of cpu address space (1) program space of the 32 bits of the pc (program counter), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. even if a carry or borrow occurs from bit 25 to 26 as a result of a branch address calculation, the higher 6 bits ignore the carry or borrow. therefore, the lower-limit address of the program sp ace, address 00000000h, and the upper-limit address 03ffffffh become contiguous addresses. wrap-around refers to a sit uation like this w hereby the lower- limit address and upper-limit address become contiguous. caution the 32 kb area of 03fff800h to 03ffffffh can be seen as an image of 0ffff800h to 0fffffffh. instructions cannot be fetched from this area because it is an on-chip peripheral i/o area, internal da ta ram area, or access-prohibi ted area. therefore, do not execute any branch addr ess calculation in which the result will reside in any part of this area. 03fffffeh 03ffffffh 00000000h 00000001h program space program space (+) direction ( ) direction (2) data space the result of an operand address calculation that exceeds 32 bits is ignored. therefore, the lower-limit address of the program sp ace, address 00000000h, and the upper-limit address ffffffffh are contiguous addresses, and the data space is wrapped around at th e boundary of these addresses. fffffffeh ffffffffh 00000000h 00000001h data space data space (+) direction ( ) direction chapter 3 cpu function 70 user?s manual u16031ej3v0ud 3.4.4 memory map areas are reserved in the v850e/me2 as shown in figure 3-4. figure 3-4. memory map 32-bit mode, 16-bit mode on-chip peripheral i/o/ internal data ram area internal data ram area (16 kb) on-chip peripheral i/o area (4 kb) access-prohibited area note 2 external memory area external memory area on-chip peripheral i/o mirror note 1 internal data ram mirror access-prohibited area note 2 internal instruction ram area (128 kb) xfffffffh xfff8000h xfff7fffh xfffffffh xfff8000h xffff000h xfffefffh xfffb000h xfffafffh x4000000h x3ffffffh x3fff000h x3ffefffh x3ffb000h x3ffafffh x3ff8000h x3ff7fffh x0100000h x00fffffh x0020000h x001ffffh x0000000h internal instruction ram area (1 mb) program area (64 mb) notes 1. accessing addresses 3fff000h to 3ffffffh is prohibited. specify addresses ffff000h to fffffffh to access the on- chip peripheral i/o. 2. the operation is not guaranteed if an access-prohibited area is accessed. caution external memory access cannot be made to the internal data ram, in ternal instruction ram, and on-chip peripheral i/o areas. chapter 3 cpu function 71 user?s manual u16031ej3v0ud 3.4.5 area (1) internal instruction ram area (a) memory map 1 mb of internal instruction ram area, addresses 00000h to fffffh, is reserved. 128 kb are provided at addresses 000000h to 01ffffh as physical instruction ram. caution external memory access cannot be made to addresses 020000h to ffffffh. if this area is accessed, the address bus (a0 to a25) outputs a low level, the data bus (d0 to d31) goes into a high-imped ance state without outputting anything, and the external bus control signal becomes inactive. (b) interrupt/exception table the v850e/me2 increases the interrupt response s peed by assigning handler addresses corresponding to interrupts/exceptions. the collection of these handler addresses is called an interrupt/exception table, which is located in the internal instruction ram area. when an interrupt/exc eption request is acknowledged, execution jumps to the handler address, and the program wr itten in that memory is execut ed. table 3-3 shows the sources of interrupts/exceptions, and t he corresponding addresses. table 3-3. interrupt/exception table (1/2) start address of interrupt/exception table interrupt/exception source start address of interrupt/exception table interrupt/exception source 00100000h reset 00000170h intpd2 00000010h nmi0 00000180h intpd3 00000040h trap0n (n = 0 to f) 00000190h intpd4 00000050h trap1n (n = 0 to f) 000001a0h intpd5 00000060h ilgop/dbg0 000001b0h intpd6 00000080h intp10 000001c0h intpd7 00000090h intp11 000001d0h intpd8 000000a0h intp21 000001e0h intpd9 000000b0h intp22 000001f0h intpd10 000000c0h intp23 00000200h intpd11 000000d0h intp24 00000210h intpd12 000000e0h intp25 00000220h intpd13 000000f0h intp50 00000230h intpd14 00000100h intp51 00000240h intpd15 00000110h intp52 00000250h intpl0 00000120h intp65 00000260h intpl1 00000130h intp66 00000270h intovc0 00000140h intp67 00000280h intovc1 00000150h intpd0 00000290h intovc2 00000160h intpd1 000002a0h intovc3 chapter 3 cpu function 72 user?s manual u16031ej3v0ud table 3-3. interrupt/exception table (2/2) start address of interrupt/exception table interrupt/exception source start address of interrupt/exception table interrupt/exception source 000002b0h intovc4 00000470h intov11 000002c0h intovc5 00000480h intud11 000002d0h intpc00/intccc00 00000490h intdma0 000002e0h intpc01/intccc01 000004a0h intdma1 000002f0h intpc10/intccc10 000004b0h intdma2 00000300h intpc11/intccc11 000004c0h intdma3 00000310h intpc20/intccc20 000004d0h intcsi30 00000320h intpc21/intccc21 000004e0h intcovf30 00000330h intpc30/intccc30 000004f0h intcsi31 00000340h intpc31/intccc31 00000500h intcovf31 00000350h intccc40 00000510h ubtire0 00000360h intccc41 00000520h ubtir0 00000370h intccc50 00000530h ubtit0 00000380h intccc51 00000540h ubtif0 00000390h intcmd0 00000550h ubtito0 000003a0h intcmd1 00000560h ubtire1 000003b0h intcmd2 00000570h ubtir1 000003c0h intcmd3 00000580h ubtit1 000003d0h intcc100 00000590h ubtif1 000003e0h intcc101 000005a0h ubtito1 000003f0h intcm100 000005b0h intad 00000400h intcm101 000005c0h intusb0b 00000410h intov10 000005d0h intusb1b 00000420h intud10 000005e0h intusb2b 00000430h intcc110 000005f0h usbsp2b 00000440h intcc111 00000600h usbsp4b 00000450h intcm110 00000610h intrsum 00000460h intcm111 chapter 3 cpu function 73 user?s manual u16031ej3v0ud (2) internal data ram area the 16 kb area of addresses fffb000h to fffefffh is provided as the internal data ram area. the 16 kb area of 3ffb000h to 3ffefffh can be seen as an image of fffb000h to fffefffh. cautions 1. external memo ry access cannot be made to a ddresses xfff8000h to xfffafffh and x3ff8000h to x3ffafffh. the operation is not guaranteed if external memory access is performed. 2. do not execute the program in the internal data ram area. fffefffh fffb000h fffafffh fff8000h internal data ram area (16 kb) access-prohibited area chapter 3 cpu function 74 user?s manual u16031ej3v0ud (3) on-chip peripheral i/o area 4 kb of memory, addresses ffff000h to fffffffh, ar e provided as an on-chip peripheral i/o area. an image of addresses ffff000h to fffffffh can be seen at addresses 3fff000h to 3ffffffh note . note addresses 3fff000h to 3ffffffh ar e access-prohibited. to acce ss the on-chip peripheral i/o, specify addresses ffff000h to fffffffh. fffffffh ffff000h on-chip peripheral i/o area (4 kb) peripheral i/o registers associated with the operating mo de specification and the state monitoring for the on- chip peripheral i/o are all memory-mapp ed to the on-chip perip heral i/o area. program fetches cannot be executed from this area. cautions 1. for registers in which byte access is possible, if halfword access is executed, the higher 8 bits become undefined during a read ope ration, and the lower 8 bits of data are written to the register during a write operation. do not access an 8-bit register in halfword units. 2. addresses that are not defined as registers are reserved for future expansion. if these addresses are accessed, the operation is undefined and not guaranteed. addresses 3fff000h to 3ffffffh cannot be specified as the source/destination address of dma transfer. be sure to use addresses ffff000h to fffffffh for the source/destination address of dma transfer. (4) external memory area 256 mb are available for external memory area. the lower 64 mb can be used as program/data area and the higher 192 mb as data area. the external me mory area is addresses x0100000h to xfdfffffh. access to the external memory area is performed using th e chip select signal assi gned to each memory block (which is carried out in the cs unit set by chip area select control regist ers 0 and 1 (csc0, csc1)). note that the internal instruction ram, internal da ta ram, and on-chip peripher al i/o areas cannot be used as external memory areas. chapter 3 cpu function 75 user?s manual u16031ej3v0ud 3.4.6 recommended use of address space the architecture of the v850e/me2 r equires that a register that serves as a pointer be secured for address generation in operand data accessing of da ta space. operand data access from instruction can be directly executed at the address in this pointer register 32 kb. however, because the general-purpose registers that can be used as a pointer register are limited, by minimizing the deteriora tion of address calculation performance when changing the pointer value, the number of usable general-purpose register s for handling variables is maximized, and the program size can be saved. in connection with the memory map of the v850e/me2, the following usage is recommended to enhance the efficiency of pointer operation. (1) program space of the 32 bits of the program counter (pc), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. therefore, a contiguous 64 mb space, star ting from address 00000000h, unconditionally corresponds to the memory map of the program space. (2) data space to efficiently operate the resources using wrap-around of the data space, a consec utive 16 mb are used as a data space at each of the 4 gb cpu address spaces of 00000000h to 00ffffffh and ff000000h to ffffffffh. with the v850e/me2, a 256 mb physical a ddress space is seen as 16 images in the 4 gb cpu address space. the highest bit (bit 25) of this 26-bit address is assigned as an address sign-extended to 32 bits. example application of wrap-around is as shown below. 32 kb 4 kb 16 kb 12 kb 0001ffffh 00007fffh (r=) 00000000h fffff000h ffffefffh ffffb000h ffffafffh ffff8000h internal instruction ram area on-chip peripheral i/o area internal data ram area access-prohibited area when r = r0 (zero register) is s pecified with the ld/st disp16[r] in struction, an addressing range of 00000000h 32 kb can be referenced with the sign-extended disp16. the zero register (r0) is a register fixed to 0 by the hardware, and eliminates the need for additional registers for the pointer. chapter 3 cpu function 76 user?s manual u16031ej3v0ud figure 3-5. recommended memory map data space program space on-chip peripheral i/o on-chip peripheral i/o internal data ram access prohibited note 2 access prohibited note 2 internal data ram access prohibited note 2 internal data ram external memory internal instruction ram external memory external memory on-chip peripheral i/o note 1 program space 64 mb internal instruction ram internal instruction ram ffffffffh fffff000h ffffefffh ffffb000h ffffafffh ffff8000h ffff7fffh xfffffffh xffff000h xfffefffh xfff8000h xfff7fffh x0100000h x00fffffh x0020000h x0000000h x001ffffh xfffb000h xfffafffh 04000000h 03ffffffh 03fff000h 03ffefffh 03ffb000h 03ffafffh 03ff8000h 03ff7fffh 00100000h 000fffffh 00020000h 00000000h 0001ffffh notes 1. this area is access-prohibited. to access the on-chip peripheral i/o, specify addresses ffff000h to fffffffh. 2. the operation is not guaranteed if an a ccess-prohibited area is accessed. remark the arrows indicate the recommended area. chapter 3 cpu function 77 user?s manual u16031ej3v0ud 3.4.7 peripheral i/o registers (1/26) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff000h port al pal r/w undefined fffff000h port all pall r/w undefined fffff001h port alh palh r 00h fffff002h port ah pah r/w undefined fffff002h port ahl pahl r/w undefined fffff003h port ahh pahh r/w undefined fffff006h port dh pdh r/w undefined fffff006h port dhl pdhl r/w undefined fffff007h port dhh pdhh r/w undefined fffff008h port cs pcs r/w undefined fffff00ah port ct pct r/w undefined fffff00ch port cm pcm r/w undefined fffff00eh port cd pcd r/w undefined fffff020h port al mode register pmal r/w ffffh fffff020h port al mode register l pmall r/w ffh fffff021h port al mode register h pmalh r ffh fffff022h port ah mode register pmah r/w ffffh fffff022h port ah mode register l pmahl r/w ffh fffff023h port ah mode register h pmahh r/w ffh fffff026h port dh mode register pmdh r/w ffffh fffff026h port dh mode register l pmdhl r/w ffh fffff027h port dh mode register h pmdhh r/w ffh fffff028h port cs mode register pmcs r/w ffh fffff02ah port ct mode register pmct r/w ffh fffff02ch port cm mode register pmcm r/w ffh fffff02eh port cd mode register pmcd r/w ffh fffff040h port al mode control register pmcal r/w 0002h fffff040h port al mode control register l pmcall r/w 02h fffff041h port al mode control register h pmcalh r 00h fffff042h port ah mode control register pmcah r/w 03ffh fffff042h port ah mode control register l pmcahl r/w ffh fffff043h port ah mode control register h pmcahh r/w 03h fffff046h port dh mode control register pmcdh r/w 0000h fffff046h port dh mode control register l pmcdhl r/w 00h fffff047h port dh mode control register h pmcdhh r/w 00h fffff048h port cs mode control register pmccs r/w ffh fffff049h port cs function control register pfccs r/w 00h chapter 3 cpu function 78 user?s manual u16031ej3v0ud (2/26) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff04ah port ct mode control register pmcct r/w bfh fffff04bh port ct function control register pfcct r/w 00h fffff04ch port cm mode control register pmccm r/w 3dh fffff04dh port cm function control register pfccm r/w 00h fffff04eh port cd mode control register pmccd r/w 0fh fffff056h port dh function control register pfcdh r/w 0000h fffff056h port dh function control register l pfcdhl r/w 00h fffff057h port dh function control register h pfcdhh r/w 00h fffff058h port al function control register l pfcall r/w 03h fffff060h chip area select control register 0 csc0 r/w 2c11h fffff062h chip area select control register 1 csc1 r/w 2c11h fffff068h endian configuration register bec r/w 0000h fffff06ah cache configuration register bhc r/w 0000h fffff06eh system wait control register vswc r/w 77h fffff070h instruction cache control register icc r/w 0003h note 1 fffff070h instruction cache control register l iccl r/w 03h note 2 fffff071h instruction cache control register h icch r/w 00h fffff074h instruction cache data configuration register icd r/w undefined fffff080h dma source address register 0l dsa0l r/w undefined fffff082h dma source address register 0h dsa0h r/w undefined fffff084h dma destination address register 0l dda0l r/w undefined fffff086h dma destination address register 0h dda0h r/w undefined fffff088h dma source address register 1l dsa1l r/w undefined fffff08ah dma source address register 1h dsa1h r/w undefined fffff08ch dma destination address register 1l dda1l r/w undefined fffff08eh dma destination address register 1h dda1h r/w undefined fffff090h dma source address register 2l dsa2l r/w undefined fffff092h dma source address register 2h dsa2h r/w undefined fffff094h dma destination address register 2l dda2l r/w undefined fffff096h dma destination address register 2h dda2h r/w undefined fffff098h dma source address register 3l dsa3l r/w undefined fffff09ah dma source address register 3h dsa3h r/w undefined fffff09ch dma destination address register 3l dda3l r/w undefined notes 1. this register is set to 0003h and the tag is automatically initialized when the reset signal becomes active. when initialization of the tag is co mpleted, the register is cleared to 0000h. 2. this register is set to 03h and the tag is automatically initialized when the reset signal becomes active. when initialization of the tag is complete d, the register is cleared to 00h. chapter 3 cpu function 79 user?s manual u16031ej3v0ud (3/26) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff09eh dma destination address register 3h dda3h r/w undefined fffff0c0h dma transfer count register 0 dbc0 r/w undefined fffff0c2h dma transfer count register 1 dbc1 r/w undefined fffff0c4h dma transfer count register 2 dbc2 r/w undefined fffff0c6h dma transfer count register 3 dbc3 r/w undefined fffff0d0h dma addressing control register 0 dadc0 r/w 0000h fffff0d2h dma addressing control register 1 dadc1 r/w 0000h fffff0d4h dma addressing control register 2 dadc2 r/w 0000h fffff0d6h dma addressing control register 3 dadc3 r/w 0000h fffff0e0h dma channel control register 0 dchc0 r/w 00h fffff0e2h dma channel control register 1 dchc1 r/w 00h fffff0e4h dma channel control register 2 dchc2 r/w 00h fffff0e6h dma channel control register 3 dchc3 r/w 00h fffff100h interrupt mask register 0 imr0 r/w ffffh fffff100h interrupt mask register 0l imr0l r/w ffh fffff101h interrupt mask register 0h imr0h r/w ffh fffff102h interrupt mask register 1 imr1 r/w ffffh fffff102h interrupt mask register 1l imr1l r/w ffh fffff103h interrupt mask register 1h imr1h r/w ffh fffff104h interrupt mask register 2 imr2 r/w ffffh fffff104h interrupt mask register 2l imr2l r/w ffh fffff105h interrupt mask register 2h imr2h r/w ffh fffff106h interrupt mask register 3 imr3 r/w ffffh fffff106h interrupt mask register 3l imr3l r/w ffh fffff107h interrupt mask register 3h imr3h r/w ffh fffff108h interrupt mask register 4 imr4 r/w ffffh fffff108h interrupt mask register 4l imr4l r/w ffh fffff109h interrupt mask register 4h imr4h r/w ffh fffff10ah interrupt mask register 5 imr5 r/w ffffh fffff10ah interrupt mask register 5l imr5l r/w ffh fffff10bh interrupt mask register 5h imr5h r/w ffh fffff110h interrupt control register 0 p1ic0 r/w 47h fffff112h interrupt control register 1 p1ic1 r/w 47h fffff114h interrupt control register 2 p2ic1 r/w 47h fffff116h interrupt control register 3 p2ic2 r/w 47h fffff118h interrupt control register 4 p2ic3 r/w 47h fffff11ah interrupt control register 5 p2ic4 r/w 47h fffff11ch interrupt control register 6 p2ic5 r/w 47h chapter 3 cpu function 80 user?s manual u16031ej3v0ud (4/26) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff11eh interrupt control register 7 p5ic0 r/w 47h fffff120h interrupt control register 8 p5ic1 r/w 47h fffff122h interrupt control register 9 p5ic2 r/w 47h fffff124h interrupt control register 10 p6ic5 r/w 47h fffff126h interrupt control register 11 p6ic6 r/w 47h fffff128h interrupt control register 12 p6ic7 r/w 47h fffff12ah interrupt control register 13 pdic0 r/w 47h fffff12ch interrupt control register 14 pdic1 r/w 47h fffff12eh interrupt control register 15 pdic2 r/w 47h fffff130h interrupt control register 16 pdic3 r/w 47h fffff132h interrupt control register 17 pdic4 r/w 47h fffff134h interrupt control register 18 pdic5 r/w 47h fffff136h interrupt control register 19 pdic6 r/w 47h fffff138h interrupt control register 20 pdic7 r/w 47h fffff13ah interrupt control register 21 pdic8 r/w 47h fffff13ch interrupt control register 22 pdic9 r/w 47h fffff13eh interrupt control register 23 pdic10 r/w 47h fffff140h interrupt control register 24 pdic11 r/w 47h fffff142h interrupt control register 25 pdic12 r/w 47h fffff144h interrupt control register 26 pdic13 r/w 47h fffff146h interrupt control register 27 pdic14 r/w 47h fffff148h interrupt control register 28 pdic15 r/w 47h fffff14ah interrupt control register 29 plic0 r/w 47h fffff14ch interrupt control register 30 plic1 r/w 47h fffff14eh interrupt control register 31 ovcic0 r/w 47h fffff150h interrupt control register 32 ovcic1 r/w 47h fffff152h interrupt control register 33 ovcic2 r/w 47h fffff154h interrupt control register 34 ovcic3 r/w 47h fffff156h interrupt control register 35 ovcic4 r/w 47h fffff158h interrupt control register 36 ovcic5 r/w 47h fffff15ah interrupt control register 37 ccc0ic0 r/w 47h fffff15ch interrupt control register 38 ccc0ic1 r/w 47h fffff15eh interrupt control register 39 ccc1ic0 r/w 47h fffff160h interrupt control register 40 ccc1ic1 r/w 47h fffff162h interrupt control register 41 ccc2ic0 r/w 47h fffff164h interrupt control register 42 ccc2ic1 r/w 47h fffff166h interrupt control register 43 ccc3ic0 r/w 47h fffff168h interrupt control register 44 ccc3ic1 r/w 47h chapter 3 cpu function 81 user?s manual u16031ej3v0ud (5/26) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff16ah interrupt control register 45 ccc4ic0 r/w 47h fffff16ch interrupt control register 46 ccc4ic1 r/w 47h fffff16eh interrupt control register 47 ccc5ic0 r/w 47h fffff170h interrupt control register 48 ccc5ic1 r/w 47h fffff172h interrupt control register 49 cmdic0 r/w 47h fffff174h interrupt control register 50 cmdic1 r/w 47h fffff176h interrupt control register 51 cmdic2 r/w 47h fffff178h interrupt control register 52 cmdic3 r/w 47h fffff17ah interrupt control register 53 cc10ic0 r/w 47h fffff17ch interrupt control register 54 cc10ic1 r/w 47h fffff17eh interrupt control register 55 cm10ic0 r/w 47h fffff180h interrupt control register 56 cm10ic1 r/w 47h fffff182h interrupt control register 57 ov1ic0 r/w 47h fffff184h interrupt control register 58 ud1ic0 r/w 47h fffff186h interrupt control register 59 cc11ic0 r/w 47h fffff188h interrupt control register 60 cc11ic1 r/w 47h fffff18ah interrupt control register 61 cm11ic0 r/w 47h fffff18ch interrupt control register 62 cm11ic1 r/w 47h fffff18eh interrupt control register 63 ov1ic1 r/w 47h fffff190h interrupt control register 64 ud1ic1 r/w 47h fffff192h interrupt control register 65 dmaic0 r/w 47h fffff194h interrupt control register 66 dmaic1 r/w 47h fffff196h interrupt control register 67 dmaic2 r/w 47h fffff198h interrupt control register 68 dmaic3 r/w 47h fffff19ah interrupt control register 69 csi3ic0 r/w 47h fffff19ch interrupt control register 70 covf3ic0 r/w 47h fffff19eh interrupt control register 71 csi3ic1 r/w 47h fffff1a0h interrupt control register 72 covf3ic1 r/w 47h fffff1a2h interrupt control register 73 ureic0 r/w 47h fffff1a4h interrupt control register 74 uric0 r/w 47h fffff1a6h interrupt control register 75 utic0 r/w 47h fffff1a8h interrupt control register 76 uific0 r/w 47h fffff1aah interrupt control register 77 utoic0 r/w 47h fffff1ach interrupt control register 78 ureic1 r/w 47h fffff1aeh interrupt control register 79 uric1 r/w 47h fffff1b0h interrupt control register 80 utic1 r/w 47h fffff1b2h interrupt control register 81 uific1 r/w 47h fffff1b4h interrupt control register 82 utoic1 r/w 47h chapter 3 cpu function 82 user?s manual u16031ej3v0ud (6/26) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff1b6h interrupt control register 83 adic r/w 47h fffff1b8h interrupt control register 84 us0bic r/w 47h fffff1bah interrupt control register 85 us1bic r/w 47h fffff1bch interrupt control register 86 us2bic r/w 47h fffff1beh interrupt control register 87 usp2ic r/w 47h fffff1c0h interrupt control register 88 usp4ic r/w 47h fffff1c2h interrupt control register 89 rsumic r/w 47h fffff1fah in-service priority register ispr r 00h fffff1fch command register prcmd w undefined fffff1feh power-save control register psc r/w 00h fffff200h a/d converter mode register 0 adm0 r/w 00h fffff201h a/d converter mode register 1 adm1 r/w 00h fffff202h a/d converter mode register 2 adm2 r/w 00h fffff210h a/d conversion result register 0 adcr0 r undefined fffff211h a/d conversion result register 0h adcr0h r undefined fffff212h a/d conversion result register 1 adcr1 r undefined fffff213h a/d conversion result register 1h adcr1h r undefined fffff214h a/d conversion result register 2 adcr2 r undefined fffff215h a/d conversion result register 2h adcr2h r undefined fffff216h a/d conversion result register 3 adcr3 r undefined fffff217h a/d conversion result register 3h adcr3h r undefined fffff218h a/d conversion result register 4 adcr4 r undefined fffff219h a/d conversion result register 4h adcr4h r undefined fffff21ah a/d conversion result register 5 adcr5 r undefined fffff21bh a/d conversion result register 5h adcr5h r undefined fffff21ch a/d conversion result register 6 adcr6 r undefined fffff21dh a/d conversion result register 6h adcr6h r undefined fffff21eh a/d conversion result register 7 adcr7 r undefined fffff21fh a/d conversion result register 7h adcr7h r undefined fffff220h adc trigger select register adts r/w 00h fffff402h port 1 p1 r/w undefined fffff404h port 2 p2 r/w undefined fffff40ah port 5 p5 r/w undefined fffff40ch port 6 p6 r/w undefined fffff40eh port 7 p7 r/w undefined fffff422h port 1 mode register pm1 r/w ffh fffff424h port 2 mode register pm2 r/w ffh fffff42ah port 5 mode register pm5 r/w ffh chapter 3 cpu function 83 user?s manual u16031ej3v0ud (7/26) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff42ch port 6 mode register pm6 r/w ffh fffff42eh port 7 mode register pm7 r/w ffh fffff442h port 1 mode control register pmc1 r/w 00h fffff444h port 2 mode control register pmc2 r/w 01h fffff44ah port 5 mode control register pmc5 r/w 00h fffff44ch port 6 mode control register pmc6 r/w 00h fffff44eh port 7 mode control register pmc7 r/w 00h fffff462h port 1 function control register pfc1 r/w 00h fffff464h port 2 function control register pfc2 r/w 00h fffff46ah port 5 function control register pfc5 r/w 00h fffff46ch port 6 function control register pfc6 r/w 00h fffff46eh port 7 function control register pfc7 r/w 00h fffff480h bus cycle type configuration register 0 bct0 r/w 8888h fffff482h bus cycle type configuration register 1 bct1 r/w 8888h fffff484h data wait control register 0 dwc0 r/w 7777h fffff486h data wait control register 1 dwc1 r/w 7777h fffff488h bus cycle control register bcc r/w ffffh fffff48ah address setup wait control register asc r/w ffffh fffff48ch bus cycle period control register bcp r/w 00h fffff48eh local bus sizing control register lbs r/w 5555h/aaaah note fffff490h line buffer control register 0 lbc0 r/w 0000h fffff492h line buffer control register 1 lbc1 r/w 0000h fffff494h dma flyby transfer wait control register fwc r/w 7777h fffff496h dma flyby transfer idle control register fic r/w 3333h fffff498h bus mode control register bmc r/w 00h fffff49ah page rom configuration register prc r/w 7000h fffff49ch write access synchronization control register was w undefined fffff4a4h sdram configuration register 1 scr1 r/w 30c0h fffff4a6h sdram refresh control register 1 rfs1 r/w 0000h fffff4ach sdram configuration register 3 scr3 r/w 30c0h fffff4aeh sdram refresh control register 3 rfs3 r/w 0000h fffff4b0h sdram configuration register 4 scr4 r/w 30c0h fffff4b2h sdram refresh control register 4 rfs4 r/w 0000h fffff4b8h sdram configuration register 6 scr6 r/w 30c0h fffff4bah sdram refresh control register 6 rfs6 r/w 0000h note 32-bit mode: aaaah 16-bit mode: 5555h for details of 32-bit mode and 16-bit mode, refer to 3.3.1 operating modes. chapter 3 cpu function 84 user?s manual u16031ej3v0ud (8/26) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff540h timer d0 tmd0 r 0000h fffff542h compare register d0 cmd0 r/w 0000h fffff544h timer mode control register d0 tmcd0 r/w 00h fffff550h timer d1 tmd1 r 0000h fffff552h compare register d1 cmd1 r/w 0000h fffff554h timer mode control register d1 tmcd1 r/w 00h fffff560h timer d2 tmd2 r 0000h fffff562h compare register d2 cmd2 r/w 0000h fffff564h timer mode control register d2 tmcd2 r/w 00h fffff570h timer d3 tmd3 r 0000h fffff572h compare register d3 cmd3 r/w 0000h fffff574h timer mode control register d3 tmcd3 r/w 00h fffff5a0h timer enc10 tmenc10 r/w 0000h fffff5a2h compare register 100 cm100 r/w 0000h fffff5a4h compare register 101 cm101 r/w 0000h fffff5a6h capture/compare register 100 cc100 r/w 0000h fffff5a8h capture/compare register 101 cc101 r/w 0000h fffff5aah capture/compare control register 10 ccr10 r/w 00h fffff5abh timer unit mode register 10 tum10 r/w 00h fffff5ach timer control register 10 tmc10 r/w 00h fffff5adh valid edge select register 10 sesa10 r/w 00h fffff5aeh prescaler mode register 10 prm10 r/w 07h fffff5afh status register 10 status10 r 00h fffff5c0h noise elimination width setting register 10 ncw10 r/w 02h fffff5d0h timer enc11 tmenc11 r/w 0000h fffff5d2h compare register 110 cm110 r/w 0000h fffff5d4h compare register 111 cm111 r/w 0000h fffff5d6h capture/compare register 110 cc110 r/w 0000h fffff5d8h capture/compare register 111 cc111 r/w 0000h fffff5dah capture/compare control register 11 ccr11 r/w 00h fffff5dbh timer unit mode register 11 tum11 r/w 00h fffff5dch timer control register 11 tmc11 r/w 00h fffff5ddh valid edge select register 11 sesa11 r/w 00h fffff5deh prescaler mode register 11 prm11 r/w 07h fffff5dfh status register 11 status11 r 00h fffff5f0h noise elimination width setting register 11 ncw11 r/w 02h fffff600h timer c0 tmc0 r 0000h fffff602h capture/compare register c00 ccc00 r/w 0000h chapter 3 cpu function 85 user?s manual u16031ej3v0ud (9/26) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff604h capture/compare register c01 ccc01 r/w 0000h fffff606h timer mode control register c00 tmcc00 r/w 00h fffff608h timer mode control register c01 tmcc01 r/w 20h fffff609h valid edge select register c0 sesc0 r/w 00h fffff610h noise elimination width setting register c0 ncwc0 r/w 02h fffff620h timer c1 tmc1 r 0000h fffff622h capture/compare register c10 ccc10 r/w 0000h fffff624h capture/compare register c11 ccc11 r/w 0000h fffff626h timer mode control register c10 tmcc10 r/w 00h fffff628h timer mode control register c11 tmcc11 r/w 20h fffff629h valid edge select register c1 sesc1 r/w 00h fffff630h noise elimination width setting register c1 ncwc1 r/w 02h fffff640h timer c2 tmc2 r 0000h fffff642h capture/compare register c20 ccc20 r/w 0000h fffff644h capture/compare register c21 ccc21 r/w 0000h fffff646h timer mode control register c20 tmcc20 r/w 00h fffff648h timer mode control register c21 tmcc21 r/w 20h fffff649h valid edge select register c2 sesc2 r/w 00h fffff650h noise elimination width setting register c2 ncwc2 r/w 02h fffff660h timer c3 tmc3 r 0000h fffff662h capture/compare register c30 ccc30 r/w 0000h fffff664h capture/compare register c31 ccc31 r/w 0000h fffff666h timer mode control register c30 tmcc30 r/w 00h fffff668h timer mode control register c31 tmcc31 r/w 20h fffff669h valid edge select register c3 sesc3 r/w 00h fffff670h noise elimination width setting register c3 ncwc3 r/w 02h fffff680h timer c4 tmc4 r 0000h fffff682h capture/compare register c40 ccc40 r/w 0000h fffff684h capture/compare register c41 ccc41 r/w 0000h fffff686h timer mode control register c40 tmcc40 r/w 00h fffff688h timer mode control register c41 tmcc41 r/w 20h fffff6a0h timer c5 tmc5 r 0000h fffff6a2h capture/compare register c50 ccc50 r/w 0000h fffff6a4h capture/compare register c51 ccc51 r/w 0000h fffff6a6h timer mode control register c50 tmcc50 r/w 00h fffff6a8h timer mode control register c51 tmcc51 r/w 20h fffff6c0h oscillation stabilization time select register osts r/w 04h fffff80ah internal instruction ram mode register iramm r/w 03h chapter 3 cpu function 86 user?s manual u16031ej3v0ud (10/26) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff80ch nmi reset status register nrs r 00h fffff810h dma trigger factor register 0 dtfr0 r/w 00h fffff812h dma trigger factor register 1 dtfr1 r/w 00h fffff814h dma trigger factor register 2 dtfr2 r/w 00h fffff816h dma trigger factor register 3 dtfr3 r/w 00h fffff820h power-save mode register psmr r/w 00h fffff822h clock control register ckc r/w 03h fffff824h lock register lockr r 01h fffff82ch clock source select register cks r/w 00h fffff82eh usb clock control register uckc r/w 00h fffff836h sscg control register sscgc r/w note 1 fffff8a0h dma terminal count output control register dtoc r/w 01h fffff8a8h dma interface control register difc r/w 00h fffffa00h uartb0 control register 0 ub0ctl0 r/w 10h fffffa02h uartb0 control register 2 ub0ctl2 r/w ffffh fffffa04h uartb0 status register ub0str r/w 00h fffffa06h uartb0 receive data register ap note 2 ub0rxap r 00ffh fffffa06h uartb0 receive data register ub0rx r ffh fffffa08h uartb0 transmit data register ub0tx w ffh fffffa0ah uartb0 fifo control register 0 ub0fic0 r/w 00h fffffa0bh uartb0 fifo control register 1 ub0fic1 r/w 00h fffffa0ch uartb0 fifo control register 2 ub0fic2 r/w 0000h fffffa0ch uartb0 fifo control register 2l ub0fic2l r/w 00h fffffa0dh uartb0 fifo control register 2h ub0fic2h r/w 00h fffffa0eh uartb0 fifo status register 0 ub0fis0 r 00h fffffa0fh uartb0 fifo status register 1 ub0fis1 r 10h fffffa20h uartb1 control register 0 ub1ctl0 r/w 10h fffffa22h uartb1 control register 2 ub1ctl2 r/w ffffh fffffa24h uartb1 status register ub1str r/w 00h fffffa26h uartb1 receive data register ap note 2 ub1rxap r 00ffh fffffa26h uartb1 receive data register ub1rx r ffh fffffa28h uartb1 transmit data register ub1tx w ffh fffffa2ah uartb1 fifo control register 0 ub1fic0 r/w 00h fffffa2bh uartb1 fifo control register 1 ub1fic1 r/w 00h notes 1. for details, see 8.3.3 sscg control register (sscgc) . 2. this register can be used only in fifo mode. chapter 3 cpu function 87 user?s manual u16031ej3v0ud (11/26) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffffa2ch uartb1 fifo control register 2 ub1fic2 r/w 0000h fffffa2ch uartb1 fifo control register 2l ub1fic2l r/w 00h fffffa2dh uartb1 fifo control register 2h ub1fic2h r/w 00h fffffa2eh uartb1 fifo status register 0 ub1fis0 r 00h fffffa2fh uartb1 fifo status register 1 ub1fis1 r 10h fffffb00h pwm control register 0 pwmc0 r/w 08h fffffb02h pwm modulo register 0 pwm0 r/w 0000h fffffb02h pwm modulo register l0 pwml0 r/w 00h fffffb03h pwm modulo register h0 pwmh0 r/w 00h fffffb10h pwm control register 1 pwmc1 r/w 08h fffffb12h pwm modulo register 1 pwm1 r/w 0000h fffffb12h pwm modulo register l1 pwml1 r/w 00h fffffb13h pwm modulo register h1 pwmh1 r/w 00h fffffc02h external interrupt falling edge specification register 1 intf1 r/w 00h fffffc04h external interrupt falling edge specification register 2 intf2 r/w 00h fffffc0ah external interrupt falling edge specification register 5 intf5 r/w 00h fffffc0ch external interrupt falling edge specification register 6 intf6 r/w 00h fffffc10h external interrupt falling edge specification register al intfal r/w 00h fffffc16h external interrupt falling edge specification register dh intfdh r/w 0000h fffffc16h external interrupt falling edge specification register dhl intfdhl r/w 00h fffffc17h external interrupt falling edge specification register dhh intfdhh r/w 00h fffffc22h external interrupt rising edge specification register 1 intr1 r/w 03h fffffc24h external interrupt rising edge specification register 2 intr2 r/w 3fh fffffc2ah external interrupt rising edge specification register 5 intr5 r/w 07h fffffc2ch external interrupt rising edge specification register 6 intr6 r/w e0h fffffc30h external interrupt rising edge specification register al intral r/w 03h chapter 3 cpu function 88 user?s manual u16031ej3v0ud (12/26) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffffc36h external interrupt rising edge specification register dh intrdh r/w ffffh fffffc36h external interrupt rising edge specification register dhl intrdhl r/w ffh fffffc37h external interrupt rising edge specification register dhh intrdhh r/w ffh fffffd00h clocked serial interf ace mode register 30 csim30 r/w 00h fffffd01h clocked serial interface clock select register 30 csic30 r/w 07h fffffd02h receive data buffer register 30 sirb30 r 0000h fffffd02h receive data buffer register 30l sirb30l r 00h fffffd03h receive data buffer register 30h sirb30h r 00h fffffd06h transmit data csi buffer register 30 sfdb30 r/w 0000h fffffd06h transmit data csi buffer register 30l sfdb30l r/w 00h fffffd07h transmit data csi buffer register 30h sfdb30h r/w 00h fffffd08h csibuf status register 30 sfa30 r/w 20h fffffd09h transfer data length select register 30 csil30 r/w 00h fffffd0ch transfer data number specification register 30 sfn30 r/w 00h fffffd20h clocked serial interf ace mode register 31 csim31 r/w 00h fffffd21h clocked serial interface clock select register 31 csic31 r/w 07h fffffd22h receive data buffer register 31 sirb31 r 0000h fffffd22h receive data buffer register 31l sirb31l r 00h fffffd23h receive data buffer register 31h sirb31h r 00h fffffd26h transmit data csi buffer register 31 sfdb31 r/w 0000h fffffd26h transmit data csi buffer register 31l sfdb31l r/w 00h fffffd27h transmit data csi buffer register 31h sfdb31h r/w 00h fffffd28h csibuf status register 31 sfa31 r/w 20h fffffd29h transfer data length select register 31 csil31 r/w 00h fffffd2ch transfer data number specification register 31 sfn31 r/w 00h fffffdf0h usb function 0 dma channel select register uf0cs r/w 0000h fffffdf2h usb function 0 buffer control register uf0bc r/w 00h fffffe00h uf0 ep0nak register uf0e0n r/w 00h fffffe01h uf0 ep0nakall register uf0e0na r/w 00h fffffe02h uf0 epnak register uf0en r/w 00h fffffe03h uf0 epnak mask register uf0enm r/w 00h fffffe04h uf0 sndsie register uf0sds r/w 00h fffffe05h uf0 clr request register uf0clr r 00h fffffe06h uf0 set request register uf0set r 00h fffffe07h uf0 ep status 0 register uf0eps0 r 00h chapter 3 cpu function 89 user?s manual u16031ej3v0ud (13/26) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffffe08h uf0 ep status 1 register uf0eps1 r 00h fffffe09h uf0 ep status 2 register uf0eps2 r 00h fffffe10h uf0 int status 0 register uf0is0 r 00h fffffe11h uf0 int status 1 register uf0is1 r 00h fffffe12h uf0 int status 2 register uf0is2 r 00h fffffe13h uf0 int status 3 register uf0is3 r 00h fffffe14h uf0 int status 4 register uf0is4 r 00h fffffe17h uf0 int mask 0 register uf0im0 r/w 00h fffffe18h uf0 int mask 1 register uf0im1 r/w 00h fffffe19h uf0 int mask 2 register uf0im2 r/w 00h fffffe1ah uf0 int mask 3 register uf0im3 r/w 00h fffffe1bh uf0 int mask 4 register uf0im4 r/w 00h fffffe1eh uf0 int clear 0 register uf0ic0 w ffh fffffe1fh uf0 int clear 1 register uf0ic1 w ffh fffffe20h uf0 int clear 2 register uf0ic2 w ffh fffffe21h uf0 int clear 3 register uf0ic3 w ffh fffffe22h uf0 int clear 4 register uf0ic4 w ffh fffffe26h uf0 int & dmarq register uf0idr r/w 00h fffffe27h uf0 dma status 0 register uf0dms0 r 00h fffffe28h uf0 dma status 1 register uf0dms1 r 00h fffffe30h uf0 fifo clear 0 register uf0fic0 w 00h fffffe31h uf0 fifo clear 1 register uf0fic1 w 00h fffffe35h uf0 data end register uf0dend r/w 00h fffffe37h uf0 gpr register uf0gpr w 00h fffffe3ah uf0 mode control register uf0modc r/w 00h fffffe3ch uf0 mode status register uf0mods r 00h fffffe40h uf0 active interface number register uf0aifn r/w 00h fffffe41h uf0 active alternative setting register uf0aas r/w 00h fffffe42h uf0 alternative setting status register uf0ass r 00h fffffe43h uf0 endpoint 1 interface mapping register uf0e1im r/w 00h fffffe44h uf0 endpoint 2 interface mapping register uf0e2im r/w 00h fffffe45h uf0 endpoint 3 interface mapping register uf0e3im r/w 00h fffffe46h uf0 endpoint 4 interface mapping register uf0e4im r/w 00h fffffe49h uf0 endpoint 7 interface mapping register uf0e7im r/w 00h fffffe4ah uf0 endpoint 8 interface mapping register uf0e8im r/w 00h fffffe80h uf0 ep0 read register uf0e0r r undefined fffffe81h uf0 ep0 length register uf0e0l r 00h fffffe82h uf0 ep0 setup register uf0e0st r 00h chapter 3 cpu function 90 user?s manual u16031ej3v0ud (14/26) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffffe83h uf0 ep0 write register uf0e0w w undefined fffffe84h uf0 bulk out 1 register uf0bo1 r undefined fffffe85h uf0 bulk out 1 length register uf0bo1l r 00h fffffe86h uf0 bulk out 2 register uf0bo2 r undefined fffffe87h uf0 bulk out 2 length register uf0bo2l r 00h fffffe88h uf0 bulk in 1 register uf0bi1 w undefined fffffe89h uf0 bulk in 2 register uf0bi2 w undefined fffffe8ah uf0 interrupt 1 register uf0int1 w undefined fffffe8bh uf0 interrupt 2 register uf0int2 w undefined fffffea2h uf0 device status register l uf0dstl r/w 00h fffffea6h uf0 ep0 status register l uf0e0sl r/w 00h fffffea8h uf0 ep1 status register l uf0e1sl r/w 00h fffffeaah uf0 ep2 status register l uf0e2sl r/w 00h fffffeach uf0 ep3 status register l uf0e3sl r/w 00h fffffeaeh uf0 ep4 status register l uf0e4sl r/w 00h fffffeb4h uf0 ep7 status register l uf0e7sl r/w 00h fffffeb6h uf0 ep8 status register l uf0e8sl r/w 00h fffffec0h uf0 address register uf0adrs r 00h fffffec1h uf0 configuration register uf0cnf r 00h fffffec2h uf0 interface 0 register uf0if0 r 00h fffffec3h uf0 interface 1 register uf0if1 r 00h fffffec4h uf0 interface 2 register uf0if2 r 00h fffffec5h uf0 interface 3 register uf0if3 r 00h fffffec6h uf0 interface 4 register uf0if4 r 00h fffffed0h uf0 descriptor length register uf0dscl r/w 00h fffffed1h uf0 device descriptor register 0 uf0dd0 r/w undefined fffffed2h uf0 device descriptor register 1 uf0dd1 r/w undefined fffffed3h uf0 device descriptor register 2 uf0dd2 r/w undefined fffffed4h uf0 device descriptor register 3 uf0dd3 r/w undefined fffffed5h uf0 device descriptor register 4 uf0dd4 r/w undefined fffffed6h uf0 device descriptor register 5 uf0dd5 r/w undefined fffffed7h uf0 device descriptor register 6 uf0dd6 r/w undefined fffffed8h uf0 device descriptor register 7 uf0dd7 r/w undefined fffffed9h uf0 device descriptor register 8 uf0dd8 r/w undefined fffffedah uf0 device descriptor register 9 uf0dd9 r/w undefined fffffedbh uf0 device descriptor register 10 uf0dd10 r/w undefined fffffedch uf0 device descriptor register 11 uf0dd11 r/w undefined fffffeddh uf0 device descriptor register 12 uf0dd12 r/w undefined chapter 3 cpu function 91 user?s manual u16031ej3v0ud (15/26) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffffedeh uf0 device descriptor register 13 uf0dd13 r/w undefined fffffedfh uf0 device descriptor register 14 uf0dd14 r/w undefined fffffee0h uf0 device descriptor register 15 uf0dd15 r/w undefined fffffee1h uf0 device descriptor register 16 uf0dd16 r/w undefined fffffee2h uf0 device descriptor register 17 uf0dd17 r/w undefined fffffee3h uf0 configuration/interface/ endpoint descriptor register 0 uf0cie0 r/w undefined fffffee4h uf0 configuration/interface/ endpoint descriptor register 1 uf0cie1 r/w undefined fffffee5h uf0 configuration/interface/ endpoint descriptor register 2 uf0cie2 r/w undefined fffffee6h uf0 configuration/interface/ endpoint descriptor register 3 uf0cie3 r/w undefined fffffee7h uf0 configuration/interface/ endpoint descriptor register 4 uf0cie4 r/w undefined fffffee8h uf0 configuration/interface/ endpoint descriptor register 5 uf0cie5 r/w undefined fffffee9h uf0 configuration/interface/ endpoint descriptor register 6 uf0cie6 r/w undefined fffffeeah uf0 configuration/interface/ endpoint descriptor register 7 uf0cie7 r/w undefined fffffeebh uf0 configuration/interface/ endpoint descriptor register 8 uf0cie8 r/w undefined fffffeech uf0 configuration/interface/ endpoint descriptor register 9 uf0cie9 r/w undefined fffffeedh uf0 configuration/interface/ endpoint descriptor register 10 uf0cie10 r/w undefined fffffeeeh uf0 configuration/interface/ endpoint descriptor register 11 uf0cie11 r/w undefined fffffeefh uf0 configuration/interface/ endpoint descriptor register 12 uf0cie12 r/w undefined fffffef0h uf0 configuration/interface/ endpoint descriptor register 13 uf0cie13 r/w undefined fffffef1h uf0 configuration/interface/ endpoint descriptor register 14 uf0cie14 r/w undefined fffffef2h uf0 configuration/interface/ endpoint descriptor register 15 uf0cie15 r/w undefined fffffef3h uf0 configuration/interface/ endpoint descriptor register 16 uf0cie16 r/w undefined fffffef4h uf0 configuration/interface/ endpoint descriptor register 17 uf0cie17 r/w undefined fffffef5h uf0 configuration/interface/ endpoint descriptor register 18 uf0cie18 r/w undefined chapter 3 cpu function 92 user?s manual u16031ej3v0ud (16/26) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffffef6h uf0 configuration/interface/ endpoint descriptor register 19 uf0cie19 r/w undefined fffffef7h uf0 configuration/interface/ endpoint descriptor register 20 uf0cie20 r/w undefined fffffef8h uf0 configuration/interface/ endpoint descriptor register 21 uf0cie21 r/w undefined fffffef9h uf0 configuration/interface/ endpoint descriptor register 22 uf0cie22 r/w undefined fffffefah uf0 configuration/interface/ endpoint descriptor register 23 uf0cie23 r/w undefined fffffefbh uf0 configuration/interface/ endpoint descriptor register 24 uf0cie24 r/w undefined fffffefch uf0 configuration/interface/ endpoint descriptor register 25 uf0cie25 r/w undefined fffffefdh uf0 configuration/interface/ endpoint descriptor register 26 uf0cie26 r/w undefined fffffefeh uf0 configuration/interface/ endpoint descriptor register 27 uf0cie27 r/w undefined fffffeffh uf0 configuration/interface/ endpoint descriptor register 28 uf0cie28 r/w undefined ffffff00h uf0 configuration/interface/ endpoint descriptor register 29 uf0cie29 r/w undefined ffffff01h uf0 configuration/interface/ endpoint descriptor register 30 uf0cie30 r/w undefined ffffff02h uf0 configuration/interface/ endpoint descriptor register 31 uf0cie31 r/w undefined ffffff03h uf0 configuration/interface/ endpoint descriptor register 32 uf0cie32 r/w undefined ffffff04h uf0 configuration/interface/ endpoint descriptor register 33 uf0cie33 r/w undefined ffffff05h uf0 configuration/interface/ endpoint descriptor register 34 uf0cie34 r/w undefined ffffff06h uf0 configuration/interface/ endpoint descriptor register 35 uf0cie35 r/w undefined ffffff07h uf0 configuration/interface/ endpoint descriptor register 36 uf0cie36 r/w undefined ffffff08h uf0 configuration/interface/ endpoint descriptor register 37 uf0cie37 r/w undefined ffffff09h uf0 configuration/interface/ endpoint descriptor register 38 uf0cie38 r/w undefined ffffff0ah uf0 configuration/interface/ endpoint descriptor register 39 uf0cie39 r/w undefined ffffff0bh uf0 configuration/interface/ endpoint descriptor register 40 uf0cie40 r/w undefined chapter 3 cpu function 93 user?s manual u16031ej3v0ud (17/26) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset ffffff0ch uf0 configuration/interface/ endpoint descriptor register 41 uf0cie41 r/w undefined ffffff0dh uf0 configuration/interface/ endpoint descriptor register 42 uf0cie42 r/w undefined ffffff0eh uf0 configuration/interface/ endpoint descriptor register 43 uf0cie43 r/w undefined ffffff0fh uf0 configuration/interface/ endpoint descriptor register 44 uf0cie44 r/w undefined ffffff10h uf0 configuration/interface/ endpoint descriptor register 45 uf0cie45 r/w undefined ffffff11h uf0 configuration/interface/ endpoint descriptor register 46 uf0cie46 r/w undefined ffffff12h uf0 configuration/interface/ endpoint descriptor register 47 uf0cie47 r/w undefined ffffff13h uf0 configuration/interface/ endpoint descriptor register 48 uf0cie48 r/w undefined ffffff14h uf0 configuration/interface/ endpoint descriptor register 49 uf0cie49 r/w undefined ffffff15h uf0 configuration/interface/ endpoint descriptor register 50 uf0cie50 r/w undefined ffffff16h uf0 configuration/interface/ endpoint descriptor register 51 uf0cie51 r/w undefined ffffff17h uf0 configuration/interface/ endpoint descriptor register 52 uf0cie52 r/w undefined ffffff18h uf0 configuration/interface/ endpoint descriptor register 53 uf0cie53 r/w undefined ffffff19h uf0 configuration/interface/ endpoint descriptor register 54 uf0cie54 r/w undefined ffffff1ah uf0 configuration/interface/ endpoint descriptor register 55 uf0cie55 r/w undefined ffffff1bh uf0 configuration/interface/ endpoint descriptor register 56 uf0cie56 r/w undefined ffffff1ch uf0 configuration/interface/ endpoint descriptor register 57 uf0cie57 r/w undefined ffffff1dh uf0 configuration/interface/ endpoint descriptor register 58 uf0cie58 r/w undefined ffffff1eh uf0 configuration/interface/ endpoint descriptor register 59 uf0cie59 r/w undefined ffffff1fh uf0 configuration/interface/ endpoint descriptor register 60 uf0cie60 r/w undefined ffffff20h uf0 configuration/interface/ endpoint descriptor register 61 uf0cie61 r/w undefined ffffff21h uf0 configuration/interface/ endpoint descriptor register 62 uf0cie62 r/w undefined chapter 3 cpu function 94 user?s manual u16031ej3v0ud (18/26) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset ffffff22h uf0 configuration/interface/ endpoint descriptor register 63 uf0cie63 r/w undefined ffffff23h uf0 configuration/interface/ endpoint descriptor register 64 uf0cie64 r/w undefined ffffff24h uf0 configuration/interface/ endpoint descriptor register 65 uf0cie65 r/w undefined ffffff25h uf0 configuration/interface/ endpoint descriptor register 66 uf0cie66 r/w undefined ffffff26h uf0 configuration/interface/ endpoint descriptor register 67 uf0cie67 r/w undefined ffffff27h uf0 configuration/interface/ endpoint descriptor register 68 uf0cie68 r/w undefined ffffff28h uf0 configuration/interface/ endpoint descriptor register 69 uf0cie69 r/w undefined ffffff29h uf0 configuration/interface/ endpoint descriptor register 70 uf0cie70 r/w undefined ffffff2ah uf0 configuration/interface/ endpoint descriptor register 71 uf0cie71 r/w undefined ffffff2bh uf0 configuration/interface/ endpoint descriptor register 72 uf0cie72 r/w undefined ffffff2ch uf0 configuration/interface/ endpoint descriptor register 73 uf0cie73 r/w undefined ffffff2dh uf0 configuration/interface/ endpoint descriptor register 74 uf0cie74 r/w undefined ffffff2eh uf0 configuration/interface/ endpoint descriptor register 75 uf0cie75 r/w undefined ffffff2fh uf0 configuration/interface/ endpoint descriptor register 76 uf0cie76 r/w undefined ffffff30h uf0 configuration/interface/ endpoint descriptor register 77 uf0cie77 r/w undefined ffffff31h uf0 configuration/interface/ endpoint descriptor register 78 uf0cie78 r/w undefined ffffff32h uf0 configuration/interface/ endpoint descriptor register 79 uf0cie79 r/w undefined ffffff33h uf0 configuration/interface/ endpoint descriptor register 80 uf0cie80 r/w undefined ffffff34h uf0 configuration/interface/ endpoint descriptor register 81 uf0cie81 r/w undefined ffffff35h uf0 configuration/interface/ endpoint descriptor register 82 uf0cie82 r/w undefined ffffff36h uf0 configuration/interface/ endpoint descriptor register 83 uf0cie83 r/w undefined ffffff37h uf0 configuration/interface/ endpoint descriptor register 84 uf0cie84 r/w undefined chapter 3 cpu function 95 user?s manual u16031ej3v0ud (19/26) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset ffffff38h uf0 configuration/interface/ endpoint descriptor register 85 uf0cie85 r/w undefined ffffff39h uf0 configuration/interface/ endpoint descriptor register 86 uf0cie86 r/w undefined ffffff3ah uf0 configuration/interface/ endpoint descriptor register 87 uf0cie87 r/w undefined ffffff3bh uf0 configuration/interface/ endpoint descriptor register 88 uf0cie88 r/w undefined ffffff3ch uf0 configuration/interface/ endpoint descriptor register 89 uf0cie89 r/w undefined ffffff3dh uf0 configuration/interface/ endpoint descriptor register 90 uf0cie90 r/w undefined ffffff3eh uf0 configuration/interface/ endpoint descriptor register 91 uf0cie91 r/w undefined ffffff3fh uf0 configuration/interface/ endpoint descriptor register 92 uf0cie92 r/w undefined ffffff40h uf0 configuration/interface/ endpoint descriptor register 93 uf0cie93 r/w undefined ffffff41h uf0 configuration/interface/ endpoint descriptor register 94 uf0cie94 r/w undefined ffffff42h uf0 configuration/interface/ endpoint descriptor register 95 uf0cie95 r/w undefined ffffff43h uf0 configuration/interface/ endpoint descriptor register 96 uf0cie96 r/w undefined ffffff44h uf0 configuration/interface/ endpoint descriptor register 97 uf0cie97 r/w undefined ffffff45h uf0 configuration/interface/ endpoint descriptor register 98 uf0cie98 r/w undefined ffffff46h uf0 configuration/interface/ endpoint descriptor register 99 uf0cie99 r/w undefined ffffff47h uf0 configuration/interface/ endpoint descriptor register 100 uf0cie100 r/w undefined ffffff48h uf0 configuration/interface/ endpoint descriptor register 101 uf0cie101 r/w undefined ffffff49h uf0 configuration/interface/ endpoint descriptor register 102 uf0cie102 r/w undefined ffffff4ah uf0 configuration/interface/ endpoint descriptor register 103 uf0cie103 r/w undefined ffffff4bh uf0 configuration/interface/ endpoint descriptor register 104 uf0cie104 r/w undefined ffffff4ch uf0 configuration/interface/ endpoint descriptor register 105 uf0cie105 r/w undefined ffffff4dh uf0 configuration/interface/ endpoint descriptor register 106 uf0cie106 r/w undefined chapter 3 cpu function 96 user?s manual u16031ej3v0ud (20/26) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset ffffff4eh uf0 configuration/interface/ endpoint descriptor register 107 uf0cie107 r/w undefined ffffff4fh uf0 configuration/interface/ endpoint descriptor register 108 uf0cie108 r/w undefined ffffff50h uf0 configuration/interface/ endpoint descriptor register 109 uf0cie109 r/w undefined ffffff51h uf0 configuration/interface/ endpoint descriptor register 110 uf0cie110 r/w undefined ffffff52h uf0 configuration/interface/ endpoint descriptor register 111 uf0cie111 r/w undefined ffffff53h uf0 configuration/interface/ endpoint descriptor register 112 uf0cie112 r/w undefined ffffff54h uf0 configuration/interface/ endpoint descriptor register 113 uf0cie113 r/w undefined ffffff55h uf0 configuration/interface/ endpoint descriptor register 114 uf0cie114 r/w undefined ffffff56h uf0 configuration/interface/ endpoint descriptor register 115 uf0cie115 r/w undefined ffffff57h uf0 configuration/interface/ endpoint descriptor register 116 uf0cie116 r/w undefined ffffff58h uf0 configuration/interface/ endpoint descriptor register 117 uf0cie117 r/w undefined ffffff59h uf0 configuration/interface/ endpoint descriptor register 118 uf0cie118 r/w undefined ffffff5ah uf0 configuration/interface/ endpoint descriptor register 119 uf0cie119 r/w undefined ffffff5bh uf0 configuration/interface/ endpoint descriptor register 120 uf0cie120 r/w undefined ffffff5ch uf0 configuration/interface/ endpoint descriptor register 121 uf0cie121 r/w undefined ffffff5dh uf0 configuration/interface/ endpoint descriptor register 122 uf0cie122 r/w undefined ffffff5eh uf0 configuration/interface/ endpoint descriptor register 123 uf0cie123 r/w undefined ffffff5fh uf0 configuration/interface/ endpoint descriptor register 124 uf0cie124 r/w undefined ffffff60h uf0 configuration/interface/ endpoint descriptor register 125 uf0cie125 r/w undefined ffffff61h uf0 configuration/interface/ endpoint descriptor register 126 uf0cie126 r/w undefined ffffff62h uf0 configuration/interface/ endpoint descriptor register 127 uf0cie127 r/w undefined ffffff63h uf0 configuration/interface/ endpoint descriptor register 128 uf0cie128 r/w undefined chapter 3 cpu function 97 user?s manual u16031ej3v0ud (21/26) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset ffffff64h uf0 configuration/interface/ endpoint descriptor register 129 uf0cie129 r/w undefined ffffff65h uf0 configuration/interface/ endpoint descriptor register 130 uf0cie130 r/w undefined ffffff66h uf0 configuration/interface/ endpoint descriptor register 131 uf0cie131 r/w undefined ffffff67h uf0 configuration/interface/ endpoint descriptor register 132 uf0cie132 r/w undefined ffffff68h uf0 configuration/interface/ endpoint descriptor register 133 uf0cie133 r/w undefined ffffff69h uf0 configuration/interface/ endpoint descriptor register 134 uf0cie134 r/w undefined ffffff6ah uf0 configuration/interface/ endpoint descriptor register 135 uf0cie135 r/w undefined ffffff6bh uf0 configuration/interface/ endpoint descriptor register 136 uf0cie136 r/w undefined ffffff6ch uf0 configuration/interface/ endpoint descriptor register 137 uf0cie137 r/w undefined ffffff6dh uf0 configuration/interface/ endpoint descriptor register 138 uf0cie138 r/w undefined ffffff6eh uf0 configuration/interface/ endpoint descriptor register 139 uf0cie139 r/w undefined ffffff6fh uf0 configuration/interface/ endpoint descriptor register 140 uf0cie140 r/w undefined ffffff70h uf0 configuration/interface/ endpoint descriptor register 141 uf0cie141 r/w undefined ffffff71h uf0 configuration/interface/ endpoint descriptor register 142 uf0cie142 r/w undefined ffffff72h uf0 configuration/interface/ endpoint descriptor register 143 uf0cie143 r/w undefined ffffff73h uf0 configuration/interface/ endpoint descriptor register 144 uf0cie144 r/w undefined ffffff74h uf0 configuration/interface/ endpoint descriptor register 145 uf0cie145 r/w undefined ffffff75h uf0 configuration/interface/ endpoint descriptor register 146 uf0cie146 r/w undefined ffffff76h uf0 configuration/interface/ endpoint descriptor register 147 uf0cie147 r/w undefined ffffff77h uf0 configuration/interface/ endpoint descriptor register 148 uf0cie148 r/w undefined ffffff78h uf0 configuration/interface/ endpoint descriptor register 149 uf0cie149 r/w undefined ffffff79h uf0 configuration/interface/ endpoint descriptor register 150 uf0cie150 r/w undefined chapter 3 cpu function 98 user?s manual u16031ej3v0ud (22/26) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset ffffff7ah uf0 configuration/interface/ endpoint descriptor register 151 uf0cie151 r/w undefined ffffff7bh uf0 configuration/interface/ endpoint descriptor register 152 uf0cie152 r/w undefined ffffff7ch uf0 configuration/interface/ endpoint descriptor register 153 uf0cie153 r/w undefined ffffff7dh uf0 configuration/interface/ endpoint descriptor register 154 uf0cie154 r/w undefined ffffff7eh uf0 configuration/interface/ endpoint descriptor register 155 uf0cie155 r/w undefined ffffff7fh uf0 configuration/interface/ endpoint descriptor register 156 uf0cie156 r/w undefined ffffff80h uf0 configuration/interface/ endpoint descriptor register 157 uf0cie157 r/w undefined ffffff81h uf0 configuration/interface/ endpoint descriptor register 158 uf0cie158 r/w undefined ffffff82h uf0 configuration/interface/ endpoint descriptor register 159 uf0cie159 r/w undefined ffffff83h uf0 configuration/interface/ endpoint descriptor register 160 uf0cie160 r/w undefined ffffff84h uf0 configuration/interface/ endpoint descriptor register 161 uf0cie161 r/w undefined ffffff85h uf0 configuration/interface/ endpoint descriptor register 162 uf0cie162 r/w undefined ffffff86h uf0 configuration/interface/ endpoint descriptor register 163 uf0cie163 r/w undefined ffffff87h uf0 configuration/interface/ endpoint descriptor register 164 uf0cie164 r/w undefined ffffff88h uf0 configuration/interface/ endpoint descriptor register 165 uf0cie165 r/w undefined ffffff89h uf0 configuration/interface/ endpoint descriptor register 166 uf0cie166 r/w undefined ffffff8ah uf0 configuration/interface/ endpoint descriptor register 167 uf0cie167 r/w undefined ffffff8bh uf0 configuration/interface/ endpoint descriptor register 168 uf0cie168 r/w undefined ffffff8ch uf0 configuration/interface/ endpoint descriptor register 169 uf0cie169 r/w undefined ffffff8dh uf0 configuration/interface/ endpoint descriptor register 170 uf0cie170 r/w undefined ffffff8eh uf0 configuration/interface/ endpoint descriptor register 171 uf0cie171 r/w undefined ffffff8fh uf0 configuration/interface/ endpoint descriptor register 172 uf0cie172 r/w undefined chapter 3 cpu function 99 user?s manual u16031ej3v0ud (23/26) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset ffffff90h uf0 configuration/interface/ endpoint descriptor register 173 uf0cie173 r/w undefined ffffff91h uf0 configuration/interface/ endpoint descriptor register 174 uf0cie174 r/w undefined ffffff92h uf0 configuration/interface/ endpoint descriptor register 175 uf0cie175 r/w undefined ffffff93h uf0 configuration/interface/ endpoint descriptor register 176 uf0cie176 r/w undefined ffffff94h uf0 configuration/interface/ endpoint descriptor register 177 uf0cie177 r/w undefined ffffff95h uf0 configuration/interface/ endpoint descriptor register 178 uf0cie178 r/w undefined ffffff96h uf0 configuration/interface/ endpoint descriptor register 179 uf0cie179 r/w undefined ffffff97h uf0 configuration/interface/ endpoint descriptor register 180 uf0cie180 r/w undefined ffffff98h uf0 configuration/interface/ endpoint descriptor register 181 uf0cie181 r/w undefined ffffff99h uf0 configuration/interface/ endpoint descriptor register 182 uf0cie182 r/w undefined ffffff9ah uf0 configuration/interface/ endpoint descriptor register 183 uf0cie183 r/w undefined ffffff9bh uf0 configuration/interface/ endpoint descriptor register 184 uf0cie184 r/w undefined ffffff9ch uf0 configuration/interface/ endpoint descriptor register 185 uf0cie185 r/w undefined ffffff9dh uf0 configuration/interface/ endpoint descriptor register 186 uf0cie186 r/w undefined ffffff9eh uf0 configuration/interface/ endpoint descriptor register 187 uf0cie187 r/w undefined ffffff9fh uf0 configuration/interface/ endpoint descriptor register 188 uf0cie188 r/w undefined ffffffa0h uf0 configuration/interface/ endpoint descriptor register 189 uf0cie189 r/w undefined ffffffa1h uf0 configuration/interface/ endpoint descriptor register 190 uf0cie190 r/w undefined ffffffa2h uf0 configuration/interface/ endpoint descriptor register 191 uf0cie191 r/w undefined ffffffa3h uf0 configuration/interface/ endpoint descriptor register 192 uf0cie192 r/w undefined ffffffa4h uf0 configuration/interface/ endpoint descriptor register 193 uf0cie193 r/w undefined ffffffa5h uf0 configuration/interface/ endpoint descriptor register 194 uf0cie194 r/w undefined chapter 3 cpu function 100 user?s manual u16031ej3v0ud (24/26) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset ffffffa6h uf0 configuration/interface/ endpoint descriptor register 195 uf0cie195 r/w undefined ffffffa7h uf0 configuration/interface/ endpoint descriptor register 196 uf0cie196 r/w undefined ffffffa8h uf0 configuration/interface/ endpoint descriptor register 197 uf0cie197 r/w undefined ffffffa9h uf0 configuration/interface/ endpoint descriptor register 198 uf0cie198 r/w undefined ffffffaah uf0 configuration/interface/ endpoint descriptor register 199 uf0cie199 r/w undefined ffffffabh uf0 configuration/interface/ endpoint descriptor register 200 uf0cie200 r/w undefined ffffffach uf0 configuration/interface/ endpoint descriptor register 201 uf0cie201 r/w undefined ffffffadh uf0 configuration/interface/ endpoint descriptor register 202 uf0cie202 r/w undefined ffffffaeh uf0 configuration/interface/ endpoint descriptor register 203 uf0cie203 r/w undefined ffffffafh uf0 configuration/interface/ endpoint descriptor register 204 uf0cie204 r/w undefined ffffffb0h uf0 configuration/interface/ endpoint descriptor register 205 uf0cie205 r/w undefined ffffffb1h uf0 configuration/interface/ endpoint descriptor register 206 uf0cie206 r/w undefined ffffffb2h uf0 configuration/interface/ endpoint descriptor register 207 uf0cie207 r/w undefined ffffffb3h uf0 configuration/interface/ endpoint descriptor register 208 uf0cie208 r/w undefined ffffffb4h uf0 configuration/interface/ endpoint descriptor register 209 uf0cie209 r/w undefined ffffffb5h uf0 configuration/interface/ endpoint descriptor register 210 uf0cie210 r/w undefined ffffffb6h uf0 configuration/interface/ endpoint descriptor register 211 uf0cie211 r/w undefined ffffffb7h uf0 configuration/interface/ endpoint descriptor register 212 uf0cie212 r/w undefined ffffffb8h uf0 configuration/interface/ endpoint descriptor register 213 uf0cie213 r/w undefined ffffffb9h uf0 configuration/interface/ endpoint descriptor register 214 uf0cie214 r/w undefined ffffffbah uf0 configuration/interface/ endpoint descriptor register 215 uf0cie215 r/w undefined ffffffbbh uf0 configuration/interface/ endpoint descriptor register 216 uf0cie216 r/w undefined chapter 3 cpu function 101 user?s manual u16031ej3v0ud (25/26) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset ffffffbch uf0 configuration/interface/ endpoint descriptor register 217 uf0cie217 r/w undefined ffffffbdh uf0 configuration/interface/ endpoint descriptor register 218 uf0cie218 r/w undefined ffffffbeh uf0 configuration/interface/ endpoint descriptor register 219 uf0cie219 r/w undefined ffffffbfh uf0 configuration/interface/ endpoint descriptor register 220 uf0cie220 r/w undefined ffffffc0h uf0 configuration/interface/ endpoint descriptor register 221 uf0cie221 r/w undefined ffffffc1h uf0 configuration/interface/ endpoint descriptor register 222 uf0cie222 r/w undefined ffffffc2h uf0 configuration/interface/ endpoint descriptor register 223 uf0cie223 r/w undefined ffffffc3h uf0 configuration/interface/ endpoint descriptor register 224 uf0cie224 r/w undefined ffffffc4h uf0 configuration/interface/ endpoint descriptor register 225 uf0cie225 r/w undefined ffffffc5h uf0 configuration/interface/ endpoint descriptor register 226 uf0cie226 r/w undefined ffffffc6h uf0 configuration/interface/ endpoint descriptor register 227 uf0cie227 r/w undefined ffffffc7h uf0 configuration/interface/ endpoint descriptor register 228 uf0cie228 r/w undefined ffffffc8h uf0 configuration/interface/ endpoint descriptor register 229 uf0cie229 r/w undefined ffffffc9h uf0 configuration/interface/ endpoint descriptor register 230 uf0cie230 r/w undefined ffffffcah uf0 configuration/interface/ endpoint descriptor register 231 uf0cie231 r/w undefined ffffffcbh uf0 configuration/interface/ endpoint descriptor register 232 uf0cie232 r/w undefined ffffffcch uf0 configuration/interface/ endpoint descriptor register 233 uf0cie233 r/w undefined ffffffcdh uf0 configuration/interface/ endpoint descriptor register 234 uf0cie234 r/w undefined ffffffceh uf0 configuration/interface/ endpoint descriptor register 235 uf0cie235 r/w undefined ffffffcfh uf0 configuration/interface/ endpoint descriptor register 236 uf0cie236 r/w undefined ffffffd0h uf0 configuration/interface/ endpoint descriptor register 237 uf0cie237 r/w undefined ffffffd1h uf0 configuration/interface/ endpoint descriptor register 238 uf0cie238 r/w undefined chapter 3 cpu function 102 user?s manual u16031ej3v0ud (26/26) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset ffffffd2h uf0 configuration/interface/ endpoint descriptor register 239 uf0cie239 r/w undefined ffffffd3h uf0 configuration/interface/ endpoint descriptor register 240 uf0cie240 r/w undefined ffffffd4h uf0 configuration/interface/ endpoint descriptor register 241 uf0cie241 r/w undefined ffffffd5h uf0 configuration/interface/ endpoint descriptor register 242 uf0cie242 r/w undefined ffffffd6h uf0 configuration/interface/ endpoint descriptor register 243 uf0cie243 r/w undefined ffffffd7h uf0 configuration/interface/ endpoint descriptor register 244 uf0cie244 r/w undefined ffffffd8h uf0 configuration/interface/ endpoint descriptor register 245 uf0cie245 r/w undefined ffffffd9h uf0 configuration/interface/ endpoint descriptor register 246 uf0cie246 r/w undefined ffffffdah uf0 configuration/interface/ endpoint descriptor register 247 uf0cie247 r/w undefined ffffffdbh uf0 configuration/interface/ endpoint descriptor register 248 uf0cie248 r/w undefined ffffffdch uf0 configuration/interface/ endpoint descriptor register 249 uf0cie249 r/w undefined ffffffddh uf0 configuration/interface/ endpoint descriptor register 250 uf0cie250 r/w undefined ffffffdeh uf0 configuration/interface/ endpoint descriptor register 251 uf0cie251 r/w undefined ffffffdfh uf0 configuration/interface/ endpoint descriptor register 252 uf0cie252 r/w undefined ffffffe0h uf0 configuration/interface/ endpoint descriptor register 253 uf0cie253 r/w undefined ffffffe1h uf0 configuration/interface/ endpoint descriptor register 254 uf0cie254 r/w undefined ffffffe2h uf0 configuration/interface/ endpoint descriptor register 255 uf0cie255 r/w undefined chapter 3 cpu function 103 user?s manual u16031ej3v0ud 3.4.8 specific registers specific registers are registers that are protected from being written with illegal data due to erroneous program execution, etc. the v850e /me2 has four specific registers, t he power-save control register (psc) (see 8.6.2 (3) power-save control register (psc) ), clock control register (ckc) (see 8.3.1 clock control register (ckc) ), clock source select register (cks) (see 8.3.2 clock source select register (cks) ), and sscg control register (sscgc) (see 8.3.3 sscg control register (sscgc) ). disable dma transfer when writing to a specific register. there is also the command register (prcmd), a protection register s upporting write operations for specific registers to avoid an unexpe cted stoppage of the applicati on system due to erroneous program execution (see 8.6.2 (2) command register (prcmd) ). 3.4.9 system wait control register (vswc) the system wait control regist er (vswc) is a register t hat controls the bus access wa it for the on-chip peripheral i/o registers. access to on-chip peripheral i/o registers is made in 3 cl ocks (without wait), however, in the v850e/me2 waits may be required depending on the operation frequency. set the values described in the table below to the vswc in accordance with the operation frequency used. this register can be read or written in 1-bit or 8-bit units (address: fffff06e h, initial value: 77h). operation frequency (f x ) vswc setting value 10.00 mhz f x 25.00 mhz 00h 25.00 mhz < f x 34.00 mhz 10h 34.00 mhz < f x 68.00 mhz 11h 68.00 mhz < f x 75.00 mhz 12h 75.00 mhz < f x 103.00 mhz 22h 103.00 mhz < f x 125.00 mhz 23h 125.00 mhz < f x 150.00 mhz 33h remark if the timing of changing a count value contend with the timing of accessing a register when accessing a register having status flags that indicate the status of the on-ch ip peripheral functions (such as ubnstr) or a register that indicates the count value of a timer (such as tmcn), the register access is retried. as a result, it may take a longer time to access an on-chip peripheral i/o register. chapter 3 cpu function 104 user?s manual u16031ej3v0ud 3.4.10 initialization sequence initialize the v850e/me2 in the following sequence. <1> automatically branch to addr ess 100000h after reset is cleared set the following registers that affect the external bus access performance using the program located at address 100000h. execution automatically branches to 100000h when the reset signal is input in the power-on status. ? system wait control register (vswc) setting of a wait cycle for acce ssing the on-chip peripheral i/o ? data wait control registers 0 and 1 (dwc0 and dwc1) setting of a data wait cycle of the external bus ? address setup wait control register (asc) setting of an address setup wait cycle of the external bus ? bus cycle control register (bcc) setting of an idle state of the external bus as necessary, set chip area select control registers 0 and 1 (csc0 and csc1), bus cycle type configuration registers 0 and 1 (bct0 and bct1), the local bus si zing control register (lbs), the endian configuration register (bec), line buffer control registers 0 and 1 (lbc0 and lbc1), the page rom configuration register (prc), port dh function control register (pfcdh), and port cs function control register (pfccs). cautions 1. disable all interrupts from when the reset signal is cleared until when the program code is completely transferred to the intern al instruction ram (while steps <1> to <3> of the initialization sequence are being execu ted). maskable interrupts are masked by default and do not h ave to be disabled. 2. set sdram configuration registers 1, 3, 4, and 6 (scr1, scr3, scr4, and scr6) after the processing of step <2>. <2> checking lock bit of lock register (lockr) after setting the registers in <1> above, check whether the lock bit of the lockr register is cleared to 0 (pll is locked), and set the registers as follows. (i) system wait control register (vswc) set to x7h (x: value set in <1>) for example, if 11h is set in <1>, set 17h here. (ii) bus mode control register (bmc) set the frequency division value of the external bus. (iii) system wait control register (vswc) re-set the value set in <1>. (iv) clock control register (ckc) set the internal system clo ck frequency division value. (v) clock source select register (cks) switch from osc output to sscg output (switch the clock supply to the cpu from the input frequency to the x1 and x2 pins to the frequency multiplied by 8 by the pll). remark the ckc and cks registers must be rewritten in a special sequence because they are specific registers. chapter 3 cpu function 105 user?s manual u16031ej3v0ud <3> transferring progr am code to internal instruction ram transfer the program code to the internal instruction ram by program processing or using the dma function. when using the dma function, check the comp letion of dma transfer by polling bit 7 (dmaifn) of the dma interrupt control register (dmaicn), without using the dma transfer end interrupt (intdman) (n = 0 to 3). after transferring the program code, set the internal instruction ram in the read mode using the following procedure. (i) set the read mode by using (clearing to 0) the ira mm0 bit of the internal instruction ram mode register (iramm). note that the setting of the iramm0 bi t must not be changed before it is cleared here. (ii) after clearing the iramm0 bit of the iramm register to 0, read the iramm0 bit that has been cleared to 0 to confirm that the read mode has been set (to prevent speculative in struction execution by pipeline operation). (iii) branch to the internal instruction ra m area by executing a branch instruction. cautions 1. after the reset signal has been clear ed, the nmi input is masked by hardware. the nmi is unmasked as soon as the iramm0 bit of the i ramm register is cleared in step <3> of the initialization sequence. 2. if it is necessary to confirm nmi i nput immediately after th e reset signal has been cleared and before the intern al instruction ram is set in the read mode, read the nmirs bit of the nmi reset status register (nrs). if this bit is set to 1, it indicates that the nmi valid edge has been input. execu te the nmi servicing routine as necessary. the nrs register is used only to check nmi input afte r the reset signal has been cleared and before the internal instruction ram is set in the read mode. this register is not cleared after the re set signal has been cleared. 3. the software exception and exception tr ap cannot be masked. do not execute the trap and dbtrap instructions until the pr ogram code has been transferred to the internal instruction ram. remarks 1. the nmirs bit of the nrs register is also set to 1 if an nmi is input after the internal instruction ram has been set in the read mode. in this case, execution automatically branches to the nmi servicing routine and it is not necessary to confirm the status of the nmirs bit. 2. the nmi input mask function is valid after the reset signal has been cleared and before the internal instruction ram is set in the read mode. 3. to write data to instruction ram bank 0 of the internal instruction ram in the middle of program execution, set the np bit of the psw to 1 to disable nmi and maskable interrupts, so that the software exception and exception trap do not occur. clear the np bit after the program has been rewritten, and after it has been confirmed that the iramm0 bit of the iramm register has been set to 1 and the read mode has been set. 4. nmi and maskable interrupt requests that are gener ated while the np bit of the psw is set to 1 are held pending. an nmi request is acknowledged immediately after the np bit has been cleared to 0. a maskable interrupt is acknowledged immediately after the np bit has been cleared to 0 if interrupts are not disabled (di status) and the interrupt request is not cleared (by clearing the xxifn bit of the interrupt contro l register (xxicn) to 0) before the np bit is cleared to 0, and if the xxmkn bit of the interrupt control register is not set to 1. however, only one of the nmi and maskable interrupt requests is held pending for each interrupt source, and only one interrupt request is acknow ledged even if the same interrupt request is generated two times or more. 106 user?s manual u16031ej3v0ud chapter 4 bus control function the v850e/me2 is provided with an exte rnal bus interface function by whic h external i/o and memories, such as rom and ram, can be connected. 4.1 features 32-bit/16-bit/8-bit data bus sizing function 8-space chip select function wait function programmable wait function, through which up to 7 wait states can be inserted for each memory block external wait function via wait pin idle state insertion function bus mastership arbitration function bus hold function external device connection enabled via bus control/port alternate function pins 4.2 bus control pins the following pins are used for connection to external devices. bus control pin (function when in control mode) func tion when in port mode register for port/control mode switching data bus (d0 to d15) ? ? data bus (d16 to d31) pdh0 to pdh15 (port dh) pmcdh address bus (a0, a1) pa l0, pal1 (port al) pmcal address bus (a16 to a25) pah0 to pah9 (port ah) pmcah chip select (cs0 to cs7, iowr, iord) pcs0 to pcs7 (port cs) pmccs sdram sync control (sdcke) pcd0 (port cd) bus clock (busclk) pcd1 (port cd) sdram control (sdcas, sdras) pcd2, pcd3 (port cd) pmccd read/write control (llwr/llbe/lldqm, luwr/lube/ludqm, ulwr/ulbe/uldqm, uudqm/uube/uuwr, rd, we/wr) pct0 to pct5 (port ct) bus cycle start (bcyst) pct7 (port ct) pmcct external wait control (wait) pcm0 (port cm) bus hold control (hldrq, hldak) pcm2, pcm3 (port cm) sdram refresh control (r efrq) pcm4 (port cm) self-refresh control (selfref) pcm5 (port cm) pmccm remark when the system is reset, each bus control pin becomes unconditionally valid. (however, d16 to d31, ulwr/ulbe/uldqm, and uuwr/uube/uudqm are valid only in 32-bit mode.) chapter 4 bus control function 107 user?s manual u16031ej3v0ud 4.2.1 pin status during internal instruction ram, internal data ram, and peripheral i/o access while accessing internal inst ruction ram (in the read mode), internal data ram, and peripheral i/o, the address bus outputs low level, and the data bus outputs nothing and enters the high-impedance state. the external bus control signals become inactive. when the internal instruction ram is accessed (in the writ e mode), the address bus and data bus output data. the external bus control signals other than uuwr, ulwr, lu wr, llwr, and wr become active. if output of the iowr signal is enabled by setting the ioen bit of the bus cycle period control register (bcp) to 1, the iowr signal becomes inactive. chapter 4 bus control function 108 user?s manual u16031ej3v0ud 4.3 memory block function the 256 mb memory space is divided into four areas including seven 2 mb memory blocks and one 1 mb memory block. the area that can be used as progr am area is the 64 mb space of addresses 0000000h to 3ffffffh. block 7 (2 mb) block 6 (2 mb) block 5 (2 mb) block 4 (2 mb) block 3 (2 mb) block 2 (2 mb) block 1 (2 mb) block 0 (1 mb) on-chip peripheral i/o mirror note 1 (4 kb) access-prohibited area note 2 internal data ram mirror (16 kb) internal instruction ram area (1 mb) internal data ram area (16 kb) on-chip peripheral i/o area (4 kb) access-prohibited area note 2 fffffffh fe00000h fdfffffh fc00000h fbfffffh fa00000h f9fffffh f800000h f7fffffh c000000h bffffffh 8000000h 7ffffffh 4000000h 3ffffffh 3fff000h 3ffefffh 3ffb000h 3ffafffh 3ff8000h 3ff7fffh 0800000h 07fffffh 0600000h 05fffffh 0400000h 03fffffh 0200000h 01fffffh 0100000h 00fffffh 0000000h fffffffh ffff000h fffefffh fffb000h fffafffh fff8000h external memory area area 3 cs7, cs6, cs5 cs6 cs4 cs3 cs1 cs2, cs1, cs0 area 2 area 1 area 0 notes 1. addresses 3fff000h to 3ffffffh are access-pr ohibited. to access the on-chip peripheral i/o, specify addresses ffff000h to fffffffh. 2. the operation is not guaranteed if an access-prohibited area is accessed. chapter 4 bus control function 109 user?s manual u16031ej3v0ud 4.3.1 chip select control function each memory block can be divided by chip area select cont rol registers 0 and 1 (csc0, csc1) to control the chip select signal. the memory area can be effectively used by dividing it into memory blocks using the chip select control function. the priority order is described below. (1) chip area select control registers 0, 1 (csc0, csc1) these registers can be read or written in 16-bit units and become valid by setting each bit to 1. if different chip select signal outputs are set to the sa me block, the priority order is controlled as follows. csc0: cs0 > cs2 > cs1 csc1: cs7 > cs5 > cs6 if both the cs0n and cs2n bits of the csc0 register are set to 0, cs1 is output to the corresponding block (n = 0 to 3). similarly, if both the cs5n and cs7n bits of the csc1 register are set to 0, cs6 is output to the corresponding block (n = 0 to 3). caution write to the csc0 and csc1 registers af ter reset, and then do not change the set value. chapter 4 bus control function 110 user?s manual u16031ej3v0ud 15 cs33 csc0 address fffff060h after reset 2c11h 14 cs32 13 cs31 12 cs30 11 cs23 10 cs22 9 cs21 8 cs20 7 cs13 6 cs12 5 cs11 4 cs10 3 cs03 2 cs02 1 cs01 0 cs00 15 cs43 csc1 address fffff062h after reset 2c11h 14 cs42 13 cs41 12 cs40 11 cs53 10 cs52 9 cs51 8 cs50 7 cs63 6 cs62 5 cs61 4 cs60 3 cs73 2 cs72 1 cs71 0 cs70 bit position bit name function chip select is enabled by setting the csnm bit to 1. csnm cs operation cs00 cs0 output during block 0 access cs01 cs0 output during block 1 access. cs02 cs0 output during block 2 access. cs03 cs0 output during block 3 access. cs10 to cs13 setting has no meaning. cs20 cs2 output during block 0 access. cs21 cs2 output during block 1 access. cs22 cs2 output during block 2 access. cs23 cs2 output during block 3 access. cs30 to cs33 setting has no meaning. cs40 to cs43 setting has no meaning. cs50 cs5 output during block 7 access. cs51 cs5 output during block 6 access. cs52 cs5 output during block 5 access. cs53 cs5 output during block 4 access. cs60 to cs63 setting has no meaning. cs70 cs7 output during block 7 access. cs71 cs7 output during block 6 access. cs72 cs7 output during block 5 access. cs73 cs7 output during block 4 access. 15 to 0 csnm (n = 0 to 7) (m = 0 to 3) the following diagram shows the cs signal that is enabled for area 0 w hen the csc0 register is set to 0f03h. when the csc0 register is set to 0f03h, cs0 and cs2 are output to block 0 and block 1, but since cs0 has priority over cs2, cs0 is output if the addr esses of block 0 and block 1 are accessed. if the addresses of block 2 and block 3 are accessed, cs2 is output. if the addresses of area 0 other than blocks 0 to 3 are accessed, cs1 is output. the following shows an example when the csc0 register is set to 0803h and the csc1 register is set to 0601h. chapter 4 bus control function 111 user?s manual u16031ej3v0ud figure 4-1. example when csc0 register is set to 0803h and csc1 register is set to 0601h block 7 (2 mb) block 6 (2 mb) block 5 (2 mb) block 4 (2 mb) block 3 (2 mb) block 2 (2 mb) block 1 (2 mb) block 0 (1 mb) fixed area (1 mb) fffffffh fe00000h fdfffffh fc00000h fbfffffh fa00000h f9fffffh f800000h f7fffffh c000000h bffffffh 8000000h 7ffffffh 4000000h 3ffffffh 0800000h 07fffffh 0600000h 05fffffh 0400000h 03fffffh 0200000h 01fffffh 0100000h 00fffffh 0000000h area 3 area 2 area 1 area 0 2 mb 4 mb 58 mb 64 mb 64 mb 56 mb 2 mb 2 mb 3 mb ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cs7 is output. cs5 is output. cs6 is output. cs4 is output. cs3 is output. cs1 is output. cs2 is output. cs1 is output. cs0 is output. internal instruction ram area chapter 4 bus control function 112 user?s manual u16031ej3v0ud 4.4 bus cycle type control function in the v850e/me2, the following external devices ca n be connected directly to each memory block. ? sram, external rom, external i/o ? page rom ? sdram connected external devices are spec ified by bus cycle type configuration registers 0 and 1 (bct0 and bct1). chapter 4 bus control function 113 user?s manual u16031ej3v0ud 4.4.1 bus cycle type configuratio n registers 0, 1 (bct0, bct1) (1) bus cycle type configuration registers 0, 1 (bct0, bct1) these registers can be read or written in 16-bit units. be sure to clear bits 14, 10, 6, and 2 to 0. if they are set to 1, the operation is not guaranteed. caution write to the bct0 and bct1 registers after reset, and then do not change the set value. also, do not access an external memory area other than the one for this initialization routine until the initial setting of the bct0 and bct1 registers is complete. however, it is possible to access external memory areas who se initialization setti ngs are complete. cs1 cs2 cs0 cs6 cs5 cs4 bct0 csn signal bct1 csn signal 15 me3 14 0 13 bt31 12 bt30 11 me2 10 0 9 bt21 8 bt20 7 me1 6 0 5 bt11 4 bt10 3 me0 2 0 1 bt01 0 bt00 15 me7 14 0 13 bt71 12 bt70 11 me6 10 0 9 bt61 8 bt60 7 me5 6 0 5 bt51 4 bt50 3 me4 2 0 1 bt41 0 bt40 address fffff480h address fffff482h after reset 8888h after reset 8888h cs3 cs7 bit position bit name function 15, 11, 7, 3 men sets memory controller operation enable for each chip select. 0: operation disabled 1: operation enabled specifies the device to be connected to the csn signal. btn1 btn0 external device connected to csn signal 0 0 sram, external i/o 0 1 page rom 1 0 setting prohibited 1 1 n = 1, 3, 4, 6: sdram n = 0, 2, 5, 7: setting prohibited 13, 12, 9, 8, 5, 4, 1, 0 btn1, btn0 remark n = 0 to 7 chapter 4 bus control function 114 user?s manual u16031ej3v0ud 4.5 bus access 4.5.1 number of access clocks the number of base clocks necessary for ac cessing each resource is as follows. operand data access bus cycle configuration resource (bus width) instruction fetch read write internal instruction ram (32 bits) 1 1 2 note internal data ram (32 bits) ? 1 note when the internal instruction ram is accessed (in the write mode), programmable waits, address setup waits, and idle states can be inserted in the cs0 space. if none of the above states is set, t he instruction ram is accessed using a 2 busclk frequency clock. remark unit: clock/access chapter 4 bus control function 115 user?s manual u16031ej3v0ud 4.5.2 bus sizing function the bus sizing function controls the dat a bus width for each cs space. the data bus width is specified by using the local bus sizing control register (lbs). (1) local bus sizing control register (lbs) this register can be read or written in 16-bit units. cautions 1. write to the lbs register after reset, and then do not change the set value. also, do not access an external memory area other than the one for this initialization routine until the initial setting of the lbs register is comp lete. however, it is possible to access external memory areas whose initiali zation settings are complete. 2. when the data bus width is specified as 8 bits, only the signal shown below becomes active. llwr: when accessing sram, external ro m, or external i/o (write cycle) 3. when the data bus width is specified as 16 bits, only the signals shown below become active. llwr, luwr: when accessing sram, exter nal rom, or external i/o (write cycle) cs4 cs0 lbs csn signal 15 lb71 14 lb70 13 lb61 12 lb60 11 lb51 10 lb50 9 lb41 8 lb40 7 lb31 6 lb30 5 lb21 4 lb20 3 lb11 2 lb10 1 lb01 0 lb00 address fffff48eh after reset note 5555h/ aaaah cs5 cs3 cs2 cs1 cs6 cs7 note when in 32-bit mode: aaaah when in 16-bit mode: 5555h for details of 32-bit mode and 16-bit mode, refer to 3.3.1 operating modes. bit position bit name function sets the data bus width of the csn space. lbn1 lbn0 data bus width of csn space 0 0 8 bits 0 1 16 bits 1 0 1 1 32 bits 15 to 0 lbn1, lbn0 remark n = 0 to 7 chapter 4 bus control function 116 user?s manual u16031ej3v0ud 4.5.3 endian control function the endian control function can be used to set processi ng of word data in memory using either the big endian method or the little endian method for each cs space selected wi th the chip select signals (cs0 to cs7). switching of the endian method is specified using the endian configuration register (bec). caution in the following areas, the data processing method is fixed to little endian, so the setting of the bec register is invalid. ? on-chip peripheral i/o area ? internal instruction ram area ? internal data ram area ? area same as internal data ram area of addresses 3ff8000h to 3ffbfffh ? program fetch area for external memory (1) endian configuration register (bec) this register can be read or written in 16-bit units. be sure to clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to 0. if they are set to 1, the operation is not guaranteed. caution write to the bec register after re set, and then do not change the set value. 15 0 bec csn signal address fffff068h after reset 0000h 14 be70 13 0 12 be60 11 0 10 be50 9 0 8 be40 7 0 6 be30 5 0 4 be20 3 0 2 be10 1 0 0 be00 cs3 cs2 cs1 cs0 cs4 cs5 cs6 cs7 bit position bit name function 14, 12, 10, 8, 6, 4, 2, 0 ben0 specifies the endian method. 0: little endian method 1: big endian method remark n = 0 to 7 chapter 4 bus control function 117 user?s manual u16031ej3v0ud figure 4-2. big endian addresses within word 0008h 0009h 000ah 000bh 0004h 0005h 0006h 0007h 0000h 0001h 0002h 0003h 31 24 23 16 15 8 7 0 figure 4-3. little endian addresses within word 000bh 000ah 0009h 0008h 0007h 0006h 0005h 0004h 0003h 0002h 0001h 0000h 31 24 23 16 15 8 7 0 4.5.4 big endian method usage restricti ons in nec electronics development tools (1) when using a debugger (id850) the big endian method is supported only in the memory window display. (2) when using a compiler (ca850) (a) restrictions in c language (i) there are restrictions for variables allocated to/l ocated in the big endian space, as shown below. ? union cannot be used. ? bitfield cannot be used. ? access with cast (changing access size) cannot be used. ? variables with initial values cannot be used. (ii) it is necessary to specify the following optimi zation inhibit options because optimization may cause a change in the access size. ? for global optimization part (opt850)? -wo, -xtb ? for optimization depending on model part (impr 850)? -wi, +arg_reg_opt=off, +stld_trans_opt=off the specification of the optimization inhibit options shown above is not necessary, however, if the access is not an access with cast or with masking/shifting note . note this is on the condition that a pattern that may cause the following optimization is not used. however, because it is very difficult for users to check the patterns comp letely in cases such as when several patterns are mixed (especially for optimization depending on model part), it is recommended that the optimization inhi bit options shown above be specified. chapter 4 bus control function 118 user?s manual u16031ej3v0ud [related global optimization part] ? 1-bit set using bit or int i; i ^=1; ? 1-bit clear using bit and i &= ~1; ? 1-bit not using bit xor i ^= 1; ? 1-bit test using bit and if(i & 1); [related optimization depending on model part] accessing the same variab le in a different size ? cast ? mask ? shift example int i, *ip; char c; . . . c=*((char*)ip); . . . c = 0xff & i; . . . i = (i<<24) >>24; (b) restrictions in assembly language for variables located in the big endian space, a quasi directive that secures an area of other than byte size (.hword, .word, .float, .shword) cannot be used. chapter 4 bus control function 119 user?s manual u16031ej3v0ud 4.5.5 bus width the v850e/me2 accesses peripheral i/o and external memory in 8-bit, 16-bit, or 32-bit units. the following shows the operation for each type of access. all data is acce ssed in order starting from the lower order side. (1) byte access (8 bits) (a) when the data bus width is 32 bits (little endian) <1> access to address (4n) <2> access to address (4n + 1) <3> access to address (4n + 2) <4> access to address (4n + 3) 7 0 7 0 15 8 23 16 31 24 byte data external data bus address 4n 7 0 7 0 15 8 23 16 31 24 byte data external data bus address 4n + 1 7 0 7 0 15 8 23 16 31 24 byte data external data bus address 4n + 2 7 0 7 0 15 8 23 16 31 24 byte data external data bus address 4n + 3 (b) when the data bus width is 16 bits (little endian) <1> access to address (4n) <2> access to address (4n + 1) <3> access to address (4n + 2) <4> access to address (4n + 3) 7 0 7 0 byte data 15 8 external data bus 4n address 7 0 7 0 15 8 4n + 1 address byte data external data bus 7 0 7 0 byte data 15 8 external data bus 4n + 2 address 7 0 7 0 15 8 4n + 3 address byte data external data bus chapter 4 bus control function 120 user?s manual u16031ej3v0ud (c) when the data bus width is 8 bits (little endian) <1> access to address (4n) <2> access to address (4n + 1) <3> access to address (4n + 2) <4> access to address (4n + 3) 7 0 7 0 4n address byte data external data bus 7 0 7 0 4n + 1 address byte data external data bus 7 0 7 0 4n + 2 address byte data external data bus 7 0 7 0 4n + 3 address byte data external data bus (d) when the data bus width is 32 bits (big endian) <1> access to address (4n) <2> access to address (4n + 1) <3> access to address (4n + 2) <4> access to address (4n + 3) 7 0 7 0 15 8 23 16 31 24 byte data external data bus address 4n 7 0 7 0 15 8 23 16 31 24 byte data external data bus address 4n + 1 7 0 7 0 15 8 23 16 31 24 byte data external data bus address 4n + 2 7 0 7 0 15 8 23 16 31 24 byte data external data bus address 4n + 3 (e) when the data bus width is 16 bits (big endian) <1> access to address (4n) <2> access to address (4n + 1) <3> access to address (4n + 2) <4> access to address (4n + 3) 7 0 7 0 15 8 4n address byte data external data bus 7 0 7 0 byte data 15 8 external data bus 4n + 1 address 7 0 7 0 15 8 4n + 2 address byte data external data bus 7 0 7 0 byte data 15 8 external data bus 4n + 3 address chapter 4 bus control function 121 user?s manual u16031ej3v0ud (f) when the data bus width is 8 bits (big endian) <1> access to address (4n) <2> access to address (4n + 1) <3> access to address (4n + 2) <4> access to address (4n + 3) 7 0 7 0 4n address byte data external data bus 7 0 7 0 4n + 1 address byte data external data bus 7 0 7 0 4n + 2 address byte data external data bus 7 0 7 0 4n + 3 address byte data external data bus chapter 4 bus control function 122 user?s manual u16031ej3v0ud (2) halfword access (16 bits) (a) when the data bus width is 32 bits (little endian) <1> access to address (4n) <2> access to address (4n + 1) 7 0 7 0 15 8 15 8 23 16 31 24 external data bus address 4n 4n + 1 halfword data 7 0 7 0 15 8 15 8 23 16 31 24 external data bus address 4n + 1 4n + 2 halfword data <3> access to address (4n + 2) <4> access to address (4n + 3) 1st access 2nd access 7 0 7 0 15 8 15 8 23 16 31 24 external data bus address 4n + 2 4n + 3 halfword data 7 0 7 0 15 8 15 8 23 16 31 24 external data bus address 4n + 3 7 0 7 0 15 8 15 8 23 16 31 24 external data bus address 4n + 4 halfword data halfword data chapter 4 bus control function 123 user?s manual u16031ej3v0ud (b) when the data bus width is 16 bits (little endian) <1> access to address (4n) <2> access to address (4n + 1) 1st access 2nd access 7 0 7 0 15 8 15 8 external data bus 4n 4n + 1 address halfword data 7 0 7 0 15 8 15 8 external data bus 4n + 1 address 7 0 7 0 15 8 15 8 external data bus 4n + 2 address halfword data halfword data <3> access to address (4n + 2) <4> access to address (4n + 3) 1st access 2nd access 7 0 7 0 15 8 15 8 external data bus 4n + 2 4n + 3 address halfword data 7 0 7 0 15 8 15 8 external data bus 4n + 3 address 7 0 7 0 15 8 15 8 external data bus 4n + 4 address halfword data halfword data chapter 4 bus control function 124 user?s manual u16031ej3v0ud (c) when the data bus width is 8 bits (little endian) <1> access to address (4n) <2> access to address (4n + 1) 1st access 2nd access 1st access 2nd access 7 0 7 0 halfword data halfword data 15 8 external data bus 4n address address 7 0 7 0 15 8 external data bus 4n + 1 7 0 7 0 15 8 external data bus 4n + 1 address address 7 0 7 0 15 8 external data bus 4n + 2 halfword data halfword data <3> access to address (4n + 2) <4> access to address (4n + 3) 1st access 2nd access 1st access 2nd access 7 0 7 0 15 8 external data bus 4n + 2 address address 7 0 7 0 15 8 external data bus 4n + 3 halfword data halfword data 7 0 7 0 15 8 external data bus 4n + 3 address address 7 0 7 0 15 8 external data bus 4n + 4 halfword data halfword data chapter 4 bus control function 125 user?s manual u16031ej3v0ud (d) when the data bus width is 32 bits (big endian) <1> access to address (4n) <2> access to address (4n + 1) 7 0 7 0 15 8 15 8 23 16 31 24 external data bus address 4n + 1 4n halfword data 7 0 7 0 15 8 15 8 23 16 31 24 external data bus address 4n + 2 4n + 1 halfword data <3> access to address (4n + 2) <4> access to address (4n + 3) 1st access 2nd access 7 0 7 0 15 8 15 8 23 16 31 24 external data bus address 4n + 3 4n + 2 halfword data 7 0 7 0 15 8 15 8 23 16 31 24 external data bus address 4n + 3 7 0 7 0 15 8 15 8 23 16 31 24 external data bus address 4n + 4 halfword data halfword data chapter 4 bus control function 126 user?s manual u16031ej3v0ud (e) when the data bus width is 16 bits (big endian) <1> access to address (4n) <2> access to address (4n + 1) 1st access 2nd access 7 0 7 0 15 8 15 8 external data bus 4n + 1 4n address halfword data 7 0 7 0 15 8 15 8 external data bus 4n + 1 address 7 0 7 0 15 8 15 8 external data bus 4n + 2 address halfword data halfword data <3> access to address (4n + 2) <4> access to address (4n + 3) 1st access 2nd access 7 0 7 0 15 8 15 8 external data bus 4n + 3 4n + 2 address halfword data 7 0 7 0 15 8 15 8 external data bus 4n + 3 address 7 0 7 0 15 8 15 8 external data bus 4n + 4 address halfword data halfword data chapter 4 bus control function 127 user?s manual u16031ej3v0ud (f) when the data bus width is 8 bits (big endian) <1> access to address (4n) <2> access to address (4n + 1) 1st access 2nd access 1st access 2nd access 7 0 7 0 15 8 external data bus 4n address address 7 0 7 0 15 8 external data bus 4n + 1 halfword data halfword data 7 0 7 0 15 8 external data bus 4n + 1 address address 7 0 7 0 15 8 external data bus 4n + 2 halfword data halfword data <3> access to address (4n + 2) <4> access to address (4n + 3) 1st access 2nd access 1st access 2nd access 7 0 7 0 15 8 external data bus 4n + 2 address address 7 0 7 0 15 8 external data bus 4n + 3 halfword data halfword data 7 0 7 0 15 8 external data bus 4n + 3 address address 7 0 7 0 15 8 external data bus 4n + 4 halfword data halfword data chapter 4 bus control function 128 user?s manual u16031ej3v0ud (3) word access (32 bits) (a) when the data bus width is 32 bits (little endian) <1> access to address (4n) <2> access to address (4n + 1) 1st access 2nd access 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 word data external data bus address 4n 4n + 1 4n + 2 4n + 3 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 word data external data bus address address 4n + 1 4n + 2 4n + 3 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 word data external data bus 4n + 4 <3> access to address (4n + 2) <4> access to address (4n + 3) 1st access 2nd access 1st access 2nd access 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 word data external data bus address address 4n + 2 4n + 3 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 word data external data bus 4n + 4 4n + 5 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 word data external data bus address address 4n + 3 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 word data external data bus 4n + 5 4n + 4 4n + 6 chapter 4 bus control function 129 user?s manual u16031ej3v0ud (b) when the data bus width is 16 bits (little endian) (1/2) <1> access to address (4n) 1st access 2nd access 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n 4n + 1 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 3 4n + 2 <2> access to address (4n + 1) 1st access 2nd access 3rd access 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 1 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 3 4n + 2 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 4 chapter 4 bus control function 130 user?s manual u16031ej3v0ud (b) when the data bus width is 16 bits (little endian) (2/2) <3> access to address (4n + 2) 1st access 2nd access 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 2 4n + 3 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 5 4n + 4 <4> access to address (4n + 3) 1st access 2nd access 3rd access 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 3 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 5 4n + 4 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 6 chapter 4 bus control function 131 user?s manual u16031ej3v0ud (c) when the data bus width is 8 bits (little endian) (1/2) <1> access to address (4n) 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n 23 16 31 24 7 0 7 0 word data external data bus 4n + 1 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 2 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 3 address 15 8 23 16 31 24 <2> access to address (4n + 1) 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n + 1 23 16 31 24 7 0 7 0 word data external data bus 4n + 2 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 3 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 4 address 15 8 23 16 31 24 chapter 4 bus control function 132 user?s manual u16031ej3v0ud (c) when the data bus width is 8 bits (little endian) (2/2) <3> access to address (4n + 2) 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n + 2 23 16 31 24 7 0 7 0 word data external data bus 4n + 3 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 4 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 5 address 15 8 23 16 31 24 <4> access to address (4n + 3) 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n + 3 23 16 31 24 7 0 7 0 word data external data bus 4n + 4 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 5 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 6 address 15 8 23 16 31 24 chapter 4 bus control function 133 user?s manual u16031ej3v0ud (d) when the data bus width is 32 bits (big endian) <1> access to address (4n) <2> access to address (4n + 1) 1st access 2nd access 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 word data external data bus address 4n + 3 4n + 2 4n + 1 4n 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 word data external data bus address address 4n + 1 4n + 2 4n + 3 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 word data external data bus 4n + 4 <3> access to address (4n + 2) <4> access to address (4n + 3) 1st access 2nd access 1st access 2nd access 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 word data external data bus address 4n + 5 4n + 4 address 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 word data external data bus 4n + 3 4n + 2 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 word data external data bus address address 4n + 3 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 word data external data bus 4n + 5 4n + 6 4n + 4 chapter 4 bus control function 134 user?s manual u16031ej3v0ud (e) when the data bus width is 16 bits (big endian) (1/2) <1> access to address (4n) 1st access 2nd access 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n 4n + 1 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 3 4n + 2 <2> access to address (4n + 1) 1st access 2nd access 3rd access 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 1 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 2 4n + 3 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 4 chapter 4 bus control function 135 user?s manual u16031ej3v0ud (e) when the data bus width is 16 bits (big endian) (2/2) <3> access to address (4n + 2) 1st access 2nd access 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 2 4n + 3 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 5 4n + 4 <4> access to address (4n + 3) 1st access 2nd access 3rd access 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 3 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 4 4n + 5 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 6 chapter 4 bus control function 136 user?s manual u16031ej3v0ud (f) when the data bus width is 8 bits (big endian) (1/2) <1> access to address (4n) 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n + 3 23 16 31 24 7 0 7 0 word data external data bus 4n + 2 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 1 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n address 15 8 23 16 31 24 <2> access to address (4n + 1) 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n + 4 23 16 31 24 7 0 7 0 word data external data bus 4n + 3 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 2 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 1 address 15 8 23 16 31 24 chapter 4 bus control function 137 user?s manual u16031ej3v0ud (f) when the data bus width is 8 bits (big endian) (2/2) <3> access to address (4n + 2) 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n + 5 23 16 31 24 7 0 7 0 word data external data bus 4n + 4 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 3 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 2 address 15 8 23 16 31 24 <4> access to address (4n + 3) 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n + 6 23 16 31 24 7 0 7 0 word data external data bus 4n + 5 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 4 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 3 address 15 8 23 16 31 24 chapter 4 bus control function 138 user?s manual u16031ej3v0ud 4.5.6 data read control function (1) line buffer control re gisters 0, 1 (lbc0, lbc1) the v850e/me2 has a read buffer. the lbc0 and lbc1 registers set the operating co nditions of the read buffer in each cs space. these registers can be read or written in 16-bit units. be sure to clear bits 15, 14, 11, 10, 7, 6, 3, and 2 to 0. if they are set to 1, the operation is not guaranteed. cautions 1. be sure to write data to the lbc0 and lbc1 registers a fter reset. after writing data to these registers, do not change their values. 2. when the speculati ve read function is set for each cs n space, do not insert an idle state in the csn space for which the sp eculative read function is enabled by the bcc register (n = 0 to 7). if an idle state is require d to be inserted in the csn space for which the speculative read function is enabled, enable the speculati ve read function for all csn spaces (set the lbc0 and lbc1 registers to 3333h) or disable the speculative read function for all csn spaces (set the l bc0 and lbc1 registers to 0000h). 3. do not enable the specul ative read function for sdram that is accessed via a 32-bit bus. cs1 cs2 cs0 cs6 cs5 cs4 lbc0 csn signal lbc1 csn signal 15 0 14 0 13 rb31 12 rb30 11 0 10 0 9 rb21 8 rb20 7 0 6 0 5 rb11 4 rb10 3 0 2 0 1 rb01 0 rb00 15 0 14 0 13 rb71 12 rb70 11 0 10 0 9 rb61 8 rb60 7 0 6 0 5 rb51 4 rb50 3 0 2 0 1 rb41 0 rb40 address fffff490h address fffff492h after reset 0000h after reset 0000h cs3 cs7 bit position bit name function these bits set the operating conditions of the read buffer (timing of speculative read) in each csn space. rbn1 rbn0 timing of speculative read 0 0 0 1 without speculative read (operation of read buffer is prohibited) 1 0 setting prohibited 1 1 in all cycles (including data access) 13, 12, 9, 8, 5, 4, 1, 0 rbn1, rbn0 remarks 1. n = 0 to 7 2. if the setting of the rbn1 and rbn0 bits is c hanged, the data in the read buffer is immediately invalidated. chapter 4 bus control function 139 user?s manual u16031ej3v0ud (a) speculative read functi on (read buffer function) the v850e/me2 has speculative read buffers consisting of 4 words (128 bits). if the operating conditions set by the lbc0 or lbc1 register are satisfied when a read request is issued from the cpu or dma controller to a csn space, the requested address is read and the remaining three words of data are read (speculatively) to the read buffers, regardless of whether a request is issued from the cpu or dma controller. data is read to the read buffers in the sequence of critical first access. example of transfer: for spec ulative reading of 32 bits (i) xxxxx00h xxxxx04h xxxxx08h xxxxx0ch (ii) xxxxx04h xxxxx08h xxxxx0ch xxxxx00h (iii) xxxxx01h xxxxx05h xxxxx09h xxxxx0dh note note if the lower 2 bits of an address are not used in the 32-bit mode, the operation is the same as (i) above. the four words of data t hat have been read are held in the read bu ffers. if the following conditions are satisfied, the data in the buffers is lost. ? speculative read miss hit (read request to external memory area not stored in read buffer) ? writing bct0 or bct1 register ? writing lbs register ? writing lbc0 or lbc1 register ? generation of bus hold ? generation of dma flyby cycle (not dependent on cs space) ? memory write access to speculatively read line address if the cpu or dma controller requests reading the data held in the read buffers, the data is transferred to the cpu or dma controller without ge nerating an external memory cycle. remark if the speculative read function is enabled in the 32-bit mode (with a 32-bit data bus width) and the ld.w instruction is executed at address xxxxx0dh, the following bus cycles are successively generated. xxxxx0ch xxxxx00h xxxxx04h xxxxx08h penalty cycle due to speculative reading xxxxx10h xxxxx14h xxxxx18h xxxxx1ch penalty cycle due to speculative reading the cpu reads the following data when it stores data in the read buffer. xxxxx0dh (8 bits) xxxxx0eh (16 bits) xxxxx10h (8 bits) chapter 4 bus control function 140 user?s manual u16031ej3v0ud the speculative read oper ation is outlined below. figure 4-4. outline of sp eculative read operation read buffer 1 (32 bits) read buffer 2 (32 bits) read buffer 3 (32 bits) read buffer 4 (32 bits) cpu or dma controller <1> <3> <4> <5> <6> <2> external interface (a) a read cycle to the address requested by the cpu or dma controller is executed (<1>). (b) the cpu or dma controller reads the data loaded to read buffer 1 (<2>). (c) read buffers 2 to 4 are speculatively read, and a re ad cycle of the remaining thr ee words is executed (<3> to <5>). (d) if the cpu or dma controller generates a read requ est to an address that has already been speculatively read, data is read from read buffers 2 to 4 (a read ac cess to the external memory does not occur) (<6>). remarks 1. (b) and (c) are executed in parallel ((d) is also executed in parallel if data is stored in the read buffers). 2. if the cpu or dma controller issues a read reques t to an address that is not speculatively read in (c) in the cycle of (d), the operation is kept waiting until the operation of (c) is completed. after completion of the operation of (c), all data in the read buffers is discarded, and an operation in response to the next address request is executed starting from (a) (miss hit operation of the speculative read function). (b) write buffer function the v850e/me2 has an on-chip write buffer of 4 words (1 28 bits). the write buffe r stores data if a write cycle cannot be execut ed while the extern al bus is occupied note . the next instructions are speculatively executed until the write buffer becomes full. the write buffer is valid for all the external memory areas. if a write request is generated while the write buffer is full, the next instru ction execution is postponed until there is a vacancy in the write buffer. while data is being stored in the write buffer (when a write operation to the external memory has not been completed), dma flyby and bus hold requests are not acknowledged (dma flyby and bus hold requests are acknowledged and an enable signal is ge nerated after all the data of the write buffers has been written to the external memory). note the external bus is occupied when there is a bus cycle currently under execution. if instruction fetch cycles are successively executed, all write cycl es for the write data stored in the write buffer are always generated after the bus cycle currently under execution (instruction fetch cycle) is completed. chapter 4 bus control function 141 user?s manual u16031ej3v0ud cautions 1. because the write buffer consists of four stages, the write buffer becomes full after 4 bytes (32 bits) when a byte write operati on is executed (while a write operation to the external memory is standing by). sim ilarly, the conditions under which the write buffer becomes full vary due to an address miss-align access, etc. 2. when data is written to an external d evice, the write operation to the external device may not be executed even when a cpu wr ite operation has been completed by the write buffer. the cpu can access the on-ch ip peripheral i/o registers after the write operation has been completed, regardl ess of whether a write operation to the external device is executed. therefore, if it is necessary to change the value of an on-chip peripheral i/o register after completion of executio n of an external memory cycle, write the same value as the default val ue to the lbc0 or lbc1 register or write 00h to the was register before wr iting the on-chip peripheral i/o register whose value is to be changed. when writ ing an on-chip peripheral i/o register other than the lbc0 or lbc1 register without writing the same value as the default value to the lbc0 or lbc1 register, or writing an on-chip peripheral i/o register other than the was register without writing 00h to the was register, the register value may be changed before completion of the extern al memory cycle. although rewriting the lbc0 and lbc1 registers is prohibited, the same value can be rewritten to the registers in this case. how ever, if a value different from the default value is written to the lbc0 or lbc1 register , the operation is not guaranteed. 3. during 2-cycle transfer that writes data to the external device, the write operation to the external device may not be completed ev en if tcn bit of dchcn register = 1 (dma transfer completion) is read by the wr ite buffer (n = 0 to 3). if it is necessary to change the value of an on-chip periph eral i/o register after completion of dma transfer (completion of a write operation to the external device), perform either of the following operations. ? monitor the tcn signal (the tcn signal becomes active in synchronization with a write operation to the external device). ? after detecting setting (to 1) of the tcn bi t, write 00h to the was register or write the same value as the default value to th e lbc0 or lbc1 register, and then change the value of the on-chip peripheral i/o register. if the value of an on-chip peripheral i/o register other than the lbc0 and lbc1 registers is changed without writing the same value to lbc0 or lbc1 or the value of an on-chip peripheral i/o register other than the was register is changed without writing 00h to the was register, the value of the on-chip peripheral i/o register may be changed before completion of dma transfer. although rewriting the lbc0 and lbc1 registers is prohibited, the same value can be rewritten to the registers in this case. however, if a value different from the default value is written to the lbc0 or lbc1 register, the operation is not guaranteed. chapter 4 bus control function 142 user?s manual u16031ej3v0ud (2) write access synchronization control register (was) when an external device is written, even if the write operation by the cp u via the write buffer is complete, writing to the external device may not be complete. the was register is used to complete writing all data in the write buffer to the external device. refer to 4.5.6 (1) (b) write buffer function for details. this register is write-only, in 8-bit units. 000000 00 76543210 was address fffff49ch after reset undefined chapter 4 bus control function 143 user?s manual u16031ej3v0ud 4.6 bus clock control function (1) bus mode control register (bmc) this register sets the division ra te of the bus clock (busclk) with re spect to the internal system clock. writing the bmc register stops busc lk once at low level. busclk resumes operation with the set divided clock after it has been stopped. while busclk is st opped, the operation of the sdram refresh control register (rfsn) of sdram is also stopped (n = 1, 3, 4, 6). this register can be read or written in 8-bit units. be sure to clear bits 7 to 2 to 0. if they are set to 1, the operation is not guaranteed. cautions 1. write the bmc register after reset, and then do not change the value that has been written. 2. before writing to the bmc register, be sure to set the vswc register to x7h (x: value before setting the bmc register). after writi ng the set value to the bmc register, re-set the value of the vswc register to the value be fore the set value of the bmc register was written (see 3.4.10 initialization sequence). 3. set the number of waits (using the dwcm .dwk2 to dwcm.dwk0 bits) or address setup waits (using the asc.ack1 and asc.ack0 bits) for all the cs spaces in which an sram or page-rom interface cycle is activated to 1 or more when the same clock is used as the internal system clock and bus clock (ckm1 and ckm0 bits = 00) and the speculative read function is enabled (lbcm.rbk1 an d lbcm.rbk0 bits = 11) (m = 0 or 1 , chapter 4 bus control function 144 user?s manual u16031ej3v0ud figure 4-5. bmc register switching timing internal system clock (f clk ) rd (output) a0 to a25 (output) wr (output) d0 to d31 (i/o) cs0 to cs7 (output) busclk (output) within internal system clock 12 clocks internal system clock 12 clocks bcyst (output) note 2 (output) bmc register changed t0 note 1 t1 notes 1. state (t0) inse rted between bus cycles 2. uube, ulbe, lube, llbe remark the broken lines indicate the high-impedance state. chapter 4 bus control function 145 user?s manual u16031ej3v0ud 4.7 wait function 4.7.1 programmable wait function (1) data wait control registers 0, 1 (dwc0, dwc1) to facilitate interfacing with low-speed memory and i/os, it is possible to insert up to 7 data wa it states in the starting bus cycle for each cs space. the number of wait states can be sp ecified by program using dwc0 and dw c1 registers. just after system reset, all blocks have 7 data wait states inserted. these registers can be read or written in 16-bit units. cautions 1. the internal instru ction ram area (in the read mode) and internal data ram area are not subject to programmable waits and ordina rily no wait access is carried out. when the internal inst ruction ram area is accessed (in the write mode), the programmable wait value set fo r the cs0 space becomes valid. the on-chip peripheral i/o area is not subject to programmable wait s, with wait control performed by each peripheral function only. 2. in the following cases, th e settings of the dwc0 and dwc1 registers are invalid (wait control is performed by each memory controller). ? page rom on-page access ? sdram access 3. write to the dwc0 and dwc1 registers after reset, and then do not change the set values. also, do not access an external memo ry area other than the one for this initialization routine until the initial se tting of the dwc0 and dwc1 registers is complete. however, it is possible to access external memory areas whose initialization settings are complete. chapter 4 bus control function 146 user?s manual u16031ej3v0ud 15 dwc0 csn signal address fffff484h after reset 7777h 14131211109876543210 0 dw32 dw31 dw30 0 dw22 dw21 dw20 0 dw12 dw11 dw10 0 dw02 dw01 dw00 0 dw72 dw71 dw70 0 dw62 dw61 dw60 0 dw52 dw51 dw50 0 dw42 dw41 dw40 cs3 cs2 cs1 cs0 cs7 cs6 cs5 cs4 15 dwc1 csn signal address fffff486h after reset 7777h 14131211109876543210 bit position bit name function specifies the number of wait states inserted in the csn space. dwn2 dwn1 dwn0 number of wait states inserted in csn space 0 0 0 not inserted 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 14 to 12, 10 to 8, 6 to 4, 2 to 0 dwn2 to dwn0 remark n = 0 to 7 chapter 4 bus control function 147 user?s manual u16031ej3v0ud (2) address setup wait control register (asc) the v850e/me2 allows insertion of address setup wa it states before the sram /page rom cycle (the setting of the asc register in the sdram cycle is invalid). the number of address setup wait states can be set with the asc register for each cs space. this register can be read or written in 16-bit units. cautions 1. the internal instru ction ram area (in the read mode), internal data ram area, and on- chip peripheral i/o area are not subj ect to address setup wait insertion. when the internal instruction ram area is accessed (in the write mode), the address setup wait value set for th e cs0 space becomes valid. 2. during an address setup wait, the wait pi n-based external wait function is disabled. 3. write to the asc register after reset , and then do not ch ange the set value. 4. be sure to set the number of waits to 1 or more if the csn signal is delayed using the pfccs register. 15 ac71 asc csn signal address fffff48ah after reset ffffh 14 ac70 13 ac61 12 ac60 11 ac51 10 ac50 9 ac41 8 ac40 7 ac31 6 ac30 5 ac21 4 ac20 3 ac11 2 ac10 1 ac01 0 ac00 cs3 cs2 cs1 cs0 cs4 cs5 cs6 cs7 bit position bit name function specifies the number of address setup wait states inserted before the sram/page rom cycle for each csn space. acn1 acn0 number of wait states 0 0 not inserted 0 1 1 1 0 2 1 1 3 15 to 0 acn1, acn0 remark n = 0 to 7 chapter 4 bus control function 148 user?s manual u16031ej3v0ud (3) bus cycle period control register (bcp) with the v850e/me2, the operations of iord and iowr can be enabled or disabled in the sram, external rom, and external i/o cycles. this register can be read or written in 8-bit or 1-bit units. be sure to clear bits 7 to 4 and 2 to 0 to 0. if they are set to 1, the operation is not guaranteed. cautions 1. during a flyby dma transfer for sram, external rom, or external i/o, the iord and iowr signals are always output, irr espective of the ioen bit setting. flyby transfer from external i/o to external memory: iord and wr signals become active. flyby transfer from external me mory to external i/o: iowr and rd signals become active. in page rom cycle, on the other ha nd, the ioen bit setting has no meaning. 2. write to the bcp register after reset , and then do not change the set values. 3. if the internal instruction ram is accessed while the ioen bit is set (1) (write mode), the iowr signal beco mes inactive. 0 0 0 0 ioen 0 0 0 76543210 bcp address fffff48ch after reset 00h bit position bit name function specifies whether to enable/disable the operation of iord and iowr in sram, external rom, and external i/o cycles. ioen enable/disable iord and iowr operation 0 disables the operation of iord and iowr in sram, external rom, and external i/o cycles. 1 enables the operation of iord and iowr in sram, external rom, and external i/o cycles. 3 ioen chapter 4 bus control function 149 user?s manual u16031ej3v0ud (4) dma flyby transfer wait control register (fwc) the fwc register sets the number of data wait cycles during dma flyby transfer for each channel n (see the timing chart in 6.5.2 flyby transfer ) (n = 0 to 3). the set value of this register is valid during dma flyb y transfer, and the set values of the dwc0, dwc1, and prc registers are invalid. this register can be read or written in 16-bit units. cautions 1. the internal inst ruction ram area and internal data ram area are not subject to the programmable wait operation and are always ac cessed with no wait cycle. the on-chip peripheral i/o area is also not subject to the programmable wait operation, and is subject only to wait control by each peripheral function. 2. write to the fwc register after reset , and then do not change the set values. 3. dma flyby transfer that accesses sdram inserts the set value + 1 data wait cycles. 0 fw32 fw31 fw30 0 fw22 fw21 fw20 0 fw12 fw11 fw10 0 fw02 fw01 fw00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 fwc address fffff494h after reset 7777h bit position bit name function these bits set the number of data wait cycles to each channel n during dma flyby transfer. number of data wait cycles fwn2 fwn1 fwn0 when sdram is not accessed when sdram is accessed 0 0 0 not inserted 1 0 0 1 1 2 0 1 0 2 3 0 1 1 3 4 1 0 0 4 5 1 0 1 5 6 1 1 0 6 7 1 1 1 7 8 14 to 12, 10 to 8, 6 to 4, 2 to 0 fwn2 to fwn0 remark n = 0 to 3 chapter 4 bus control function 150 user?s manual u16031ej3v0ud 4.7.2 external wait function when an extremely slow device, i/o, or asynchronous system is connected, an arbitrary number of wait states can be inserted in the bus cycle by the external wait pin (wait) for synchronization with the external device. just as with programmable waits, accessing internal instru ction ram (in the read mode), internal data ram, and on-chip peripheral i/o areas cannot be controlled by exte rnal waits. the external wait signal can be input asynchronously to busclk and is sampled at the rising edge of busclk immediately after the t1 and tw states of a bus cycle. if the setup/hold time in the sampling timing is not satisfied, the wait state may or may not be inserted in the next state. caution be sure to make the wait pin high when the intern al instruction ram is accessed (in the write mode). 4.7.3 relationship between programm able wait and external wait a wait cycle is inserted as the result of an or operation between the wait cycle specifi ed by the set value of the programmable wait and t he wait cycle controlled by the wait pin. wait control programmable wait wait by wait pin for example, if the timings of the pr ogrammable wait and the wait pin signal are as illustrated below, three wait states will be inserted in the bus cycle. figure 4-6. example of wait insertion t1 tw tw tw t2 busclk wait pin wait by wait pin programmable wait wait control remark the circle { indicates the sampling timing. chapter 4 bus control function 151 user?s manual u16031ej3v0ud 4.7.4 bus cycles in which wait functi on is valid in the v850e/me2, the number of waits can be specified a ccording to the memory type specified for each memory block. the following shows t he bus cycles in which the wait function is valid and the re gisters used for wait setting. table 4-1. bus cycles in which wait function is valid programmable wait setting bus cycle type of wait register bit wait count wait from wait pin address setup wait asc acn1, acn0 0 to 3 ? ? ? ? ? ? ? chapter 4 bus control function 152 user?s manual u16031ej3v0ud 4.8 idle state insertion function (1) bus cycle control register (bcc) to facilitate interfacing with low-speed memory devices, an idle state (ti) c an be inserted into the current bus cycle after the t2 state to meet t he data output float delay time (t df ) on memory read access for each cs space. the bus cycle following the t2 state starts after the idle state is inserted. an idle state is inserted at the timing shown below. ? after read/write cycles for sram, external i/o, or external rom ? after a read cycle for page rom ? after a read cycle for sdram the idle state insertion setting c an be specified by program using the bus cycle control register (bcc). immediately after the system reset, idle state insertion is aut omatically programmed for all memory blocks. for the timing when an idle state is inserted, see the memory access timings in chapter 5. this register can be read or written in 16-bit units. cautions 1. the internal inst ruction ram area (in the read mode), internal data ram area, and on- chip peripheral i/o area are not subject to idle state insertion. when the internal instruction ram area is accessed (in the write mode), the idle state value set for the cs 0 space becomes valid. 2. write to the bcc register after reset, and then do not change the set values. also, do not access an external memory area other than th e one for this initialization routine until the initial setting of the bcc register is co mplete. however, it is possible to access external memory areas whose initia lization settings are complete. 3. the chip select signal (csn ) does not become active in th e idle state (n = 0 to 7). 15 bc71 bcc csn signal address fffff488h after reset ffffh 14 bc70 13 bc61 12 bc60 11 bc51 10 bc50 9 bc41 8 bc40 7 bc31 6 bc30 5 bc21 4 bc20 3 bc11 2 bc10 1 bc01 0 bc00 cs3 cs2 cs1 cs0 cs4 cs5 cs6 cs7 bit position bit name function specifies the insertion of an idle state in the csn space. bcn1 bcn0 idle state in csn space 0 0 not inserted 0 1 1 1 0 2 1 1 3 15 to 0 bcn1, bcn0 remark n = 0 to 7 chapter 4 bus control function 153 user?s manual u16031ej3v0ud (2) dma flyby transfer idle control register (fic) the fic register sets the number of idle states during dma flyby transfer for each dma channel n (see the timing chart in 6.5.2 flyby transfer ) (n = 0 to 3). the idle state is inse rted at the end of dma flyby transfer. during dma flyby transfer, the set valu e of this register is valid, and the set value of the bus cycle control register (bcc) is invalid. this register can be read or written in 16-bit units. cautions 1. the internal instruction ram area, internal data ram area, and on-chip peripheral i/o area are not subject to idle state insertion. 2. write to the fic register after rese t, and then do not change the set values. 00 fi31 fi30 00 fi21 fi20 00 fi11 fi10 00 fi01 fi00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 fic address fffff496h after reset 3333h bit position bit name function these bits specify the number of idle states during dma flyby transfer for each channel n. fin1 fin0 idle state during dma flyby transfer 0 0 not inserted 0 1 1 1 0 2 1 1 3 13, 12, 9, 8, 5, 4, 1, 0 fin1, fin0 remark n = 0 to 3 chapter 4 bus control function 154 user?s manual u16031ej3v0ud 4.9 instruction cache function the v850e/me2 has an 8 kb 2-way set associative instruction cache. this instruction cache uses an lru (least recently used ) algorithm. this cache uses two ways as the cache, with the way to be replaced in case of a miss hit determined by the internal lru bit. if the way is specified as a cacheable area, a 4-word burst sequential read cycle is i ssued (when the external 32-bit bus operates) (when the external 16-bit bus operates, an 8-halfword burst read cycle is issued). set the instruction cache using the fo llowing procedure, a fter system reset. <1> wait until the value of t he icc register reaches ?0000h? (until the tag is initialized). <2> make the setting of the instruction cache cacheable by using the bhc register. caution be sure to set the bhc regist er in an uncached area (instructions cannot be fetched correctly if it is set from a cacheable area). 4.9.1 cache configuration register (bhc) (1) cache configuration register (bhc) this register can set the configuration of the cache memory in each cs space selected by the chip select signals (cs0 to cs2). setting a cacheable area becomes valid immediately after the bhc register has been set. this register can be read or written in 16-bit units. be sure to clear bits 15 to 5 to 0. if they are set to 1, the operat ion is not guaranteed. cautions 1. write the bhc register after re set, and then do not change the set values. 2. the area that includes the instruction that sets the bhc re gister cannot be set from an uncached area to a cacheable ar ea, or from a cacheable area to an uncached area. in this case, branch to area 1 and then set area 0 to a cacheable area by an instruction in area 1. if necessary, branch to area 0 again. an uncached area and a cachea ble area can be set in an y cs space in the internal instruction ram area. (example of prohibited setting) ? if the instruction that sets the bhc register is in area 0 area 0 before setting bhc area 1 uncached area uncached area area 0 after setting bhc (area 0 is set as cacheable area in area 0) area 1 cacheable area uncached area chapter 4 bus control function 155 user?s manual u16031ej3v0ud cautions 3. if adjacent memory areas are a cacheable area and an uncached area, only a branch instruction can be used to successively access this me mory boundary. the operation is not guaranteed if this memory boundary is successively a ccessed by an instruction other than a branch instruction. (operation example) ? an access from area 0 to area 1 can be made only by a branch instruction. ? successive accesses can be made from area 1 to area 2. area 0 area 1 uncached area cacheable area area 2 cacheable area cs0 bhc csn signal 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 bh20 3 0 2 bh10 1 0 0 bh00 address fffff06ah after reset 0000h cs2 cs1 bit position bit name function 4, 2, 0 bhn0 these bits set the instruction cache placed in the csn space. 0: uncached 1: cacheable remark n = 0 to 2 chapter 4 bus control function 156 user?s manual u16031ej3v0ud 4.9.2 8 kb 2-way set associative cache the data memory of the 8 kb 2-way set associative ca che has two ways each consisting of 4-word lines and blocks of 256 entries, and has a total capa city of 8 kb. if a cache miss occurs, the data memory is refilled in 1-line units. only the instructions related to dat a access of the cacheable area can be cached in the instruction cache. figure 4-7. configuration of 8 kb 2- way set associative instruction cache 12 25 11 4 3 2 1 0 tag index tag data (4 words) comparator iihit selector instruction data way select control signal when a hit occurs internal bus internal bus 32 32 32 256 entries 2 8 14 1 word 1 word 1 word 1 word . . . . . . . . . . . . 14 14 4.9.3 lru algorithm this algorithm is used to record accesses to blocks an d replace the block that has not been used for the longest time, so that information that may be necessary is not discarded immediately. chapter 4 bus control function 157 user?s manual u16031ej3v0ud 4.9.4 instruction cache control function (1) instruction cache control register (icc) this register sets two types of functions, tag clear and auto fill. this register can be read or written in 16-bit units. if the higher 8 bits of the icc register are used as an icch register, and t he lower 8 bits, as an iccl register, these registers can be read or wr itten in 8-bit or 1-bit units. bit 12 can only be read and cleared. be sure to clear bits 15 to 13, 11 to 5, 3, and 2 to 0. if they are set to 1, the operation is not guaranteed. cautions 1. do not forcibly clear bi ts 0, 1, and 4 when they are set to 1. 2. do not set bit 4 to 1 at the same time as the other bits. 3. do not set bit 12 to 1. th is bit can only be cleared to 0. 4. be sure to set the icc register in an uncached area (except setting of bit 4). 000 locki0 0000 0 0 0 fill0 00 tclr1tclr0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 icc address fffff070h after reset 0003h note note the value of this register is 0003h when the reset signal becomes active, and initialization of the tag is automatically started. w hen initialization of the tag has been comple ted, the value of this register is cleared to 0000h. bit position bit name function 12 locki0 indicates the cache lock status of way 0. the cache is locked when way 0 is filled, and this bit is automatically set to 1. when this bit is cleared to 0, cache lock of way 0 is cleared. 0: way 0 is not locked. 1: way 0 is locked. 4 fill0 sets auto fill of way 0. when this bit is set to 1, way 0 is automatically filled. when auto fill has been completed, this bit is automatically cleared to 0. 0: filling way 0 is completed. 1: way 0 is being filled. 1 tclr1 sets tag clear of way 1. when this bit is set to 1, the tag of way 1 is cleared (invalidated). when clearing the tag has been completed, th is bit is automatically cleared to 0. 0: clearing tag of way 1 is completed. 1: tag of way 1 is being cleared. 0 tclr0 sets tag clear of way 0. when this bit is set to 1, the tag of way 0 is cleared (invalidated). when clearing the tag has been completed, th is bit is automatically cleared to 0. 0: clearing tag of way 0 is completed. 1: tag of way 0 is being cleared. chapter 4 bus control function 158 user?s manual u16031ej3v0ud (2) instruction cache data configuration register (icd) this register sets the address of t he memory area that is automatically filled by the auto fill function. this register can be read or written in 16-bit units. be sure to clear bit 0 to 0. if it is set to 1, the operation is not guaranteed. cautions 1. do not rewrite the icd register during the auto fill operation. the operation is not guaranteed if it is rewritten. 2. because the default value of the icd register is undefined, be sure to set a value to the icd register when the auto fill function is used, and then set the fill0 bit of the icc register to 1. if the fill0 bit of the icc re gister is set to 1 without setting a value to the icd register, the operation is not guaranteed. 15 0 14 icd 14 13 icd 13 12 icd 12 11 icd 11 10 icd 10 9 icd 9 8 icd 8 7 icd 7 6 icd 6 5 icd 5 4 icd 4 3 icd 3 2 icd 2 1 icd 1 0 0 icd address fffff074h after reset undefined bit position bit name function 14 to 1 icd14 to icd1 set the higher 14 bits of tag information (bits 25 to 12 of the first address of the memory area to be automatically filled). chapter 4 bus control function 159 user?s manual u16031ej3v0ud 4.9.5 tag clear function the tag of one way is cleared (invalidated). after reset, all the ways, tags, and lru are automatically cleared (invalidated). the instruction cache tag is clear ed using the following procedure. <1> the icc register is read to confirm that both the tclr0 and tclr1 bits are cleared to 0. <2> the icc register is read to confi rm that the locki0 bit is cleared to 0. bit 13 of the icc register is always cleared to 0. <3> the tclr0 and tclr1 bits of the icc register are set as follows. cautions 1. perform operations <1> to <3> above (ta g clear) in an uncached area (the tag is not cleared from a cacheable area). ? to clear both ways 0 and 1 at the same time (a) set the tclr0 and tclr1 bits to 1. (b) read the tclr0 and tclr1 bits to confirm that they are cleared to 0. ? to clear ways 0 and 1 separately note (a) set the tclr0 bit to 1. (b) read the tclr0 bit to conf irm that it is cleared to 0. (c) set the tclr1 bit to 1. (d) read the tclr1 bit to conf irm that it is cleared to 0. note the ways can be cleared separately also in the orde r of (c) - (d) - (a) - (b). 2. the counter for clearing th e tag of ways 0 and 1 is shared. therefore, clear the tag (by setting the tclr0 or tclr1 bit of the icc register) when the counter for clearing the tag is stopped (when tclr0 = tclr1 = 0). when clearing the tags of ways 0 and 1 separately, th e counter stops while a tag is bei ng cleared if the tag of one other way is cleared while the tag of the other w ay is being cleared (tclr0 or tclr1 = 1). consequently, the tag ca nnot be cleared correctly because the tag of the other way is cleared with the counter indicating a midway value. be su re to clear the tag of one other way after confirming that the tag of the other way has been cleared (tclr0 or tclr1 = 0). there is no problem if both the bits are set at the same time as follows. mov 0x3, r2 lop0: ld.h icc[r0], r1 cmp r0, r1 bnz lop0 st.h r2, icc[r0] lop1: ld.h icc[r0], r1 cmp r0, r1 bnz lop1 3. do not perform other processing in parallel with clearing the tag until it is confirmed by reading the tclr0 and tclr1 bits of the icc re gister that the tag h as been cleared to 0. chapter 4 bus control function 160 user?s manual u16031ej3v0ud 4.9.6 auto fill function (way 0 only) the instruction of one way is automatically filled. the way that has been filled automatically is automatically locked and prohibit ed from being written, and performs the same operation as rom that can be accessed in one cyc le. after the way is unlocked, it operates as an instruction cache again. the instruction cache is automatically filled using the following procedure. <1> clear (invalidate) the tag of way 0 (see 4.9.5 tag clear function ). <2> set information on the tag corresponding to the memory area to be automatically filled to the icd register. <3> branch to the cacheable area corresponding to the tag information set to the icd register. <4> set the fill0 bit of the icc register to 1. <5> when auto fill is completed, the lock i0 bit of the icc register is automatic ally set to 1, and way 0 is locked. at this time, read the fill0 bit of the i cc register at the same time to conf irm that this bit is cleared to 0. caution perform the above opera tions in the fo llowing areas. <1>, <2>, <3> ........ uncached area <4> ........................ cachea ble area if the fill0 bit of the icc register is set to 1 from an uncached area, auto fill cannot be executed (is invalidated). <5> ........................ this can be done from both an uncached area and a cacheable area. remark to unlock the way, clear the locki0 bit of the icc register to 0. 4.9.7 cautions when a refill read cycle is activated by the occurrence of a cache miss, the instruction read in that bus cycle may be discarded without being registered in the instruction cache. when this oper ation occurs for a conditional branch instruction in a program loop, for exam ple, an illegal re fill read cycle occurs in the subsequent cache line each time the program loops, which degrades the system performance. th e effect of performance degradation is particularly large in a small-scale loop. however, program execution is performed normally even under this circumstance and the execution result is logically correct. in order to make up for performance degradation due to the uncertain operation by the instruction cache, an instruction ram is provided in the v850e/me2, which assu res certain instruction execution in a 1-clock pitch. therefore, execute a r outine that may cause this proble m using the instruction ram. chapter 4 bus control function 161 user?s manual u16031ej3v0ud 4.10 internal instruction ram control function the v850e/me2 has 128 kb of instruction ram (16 kb 32 bits 2 banks). while one bank is being read, the ot her bank can be written in parallel. 4.10.1 internal instruction ram mode register (iramm) (1) internal instruction ram mode register (iramm) this register specifies a mode in wh ich the instruction ram is accessed. this register can be read or written in 8-bit or 1-bit units. cautions 1. when the setting of a mode is change d, the next access (such as code fetching) to the internal instruction ram may be executed first because of th e pipeline operation of the cpu. when the setting of the iramm register is changed, therefore, be sure to read the iramm register to confirm that writing has been executed, and then execute an access to the internal instruction ram. 2. data can be written to the intern al instruction ram on ly by a word access. 3. address miss-align access to the inte rnal instruction ram is prohibited. 0 0 0 0 0 0 iramm1 iramm0 76543210 iramm address fffff80ah after reset 03h bit position bit name function 1 iramm1 specifies the access mode of instruction ram bank 1. 0: read mode 1: write mode 0 iramm0 specifies the access mode of instruction ram bank 0. 0: read mode 1: write mode figure 4-8. memory map of internal instruction ram 001ffffh 0010000h 000ffffh 0000000h instruction ram bank 1 (64 kb) instruction ram bank 0 (64 kb) chapter 4 bus control function 162 user?s manual u16031ej3v0ud 4.10.2 operation (1) read operation the internal instruction ram can be read by normal ram access without having to be aware of the banks if the read mode is selected by the iramm register. cautions 1. a bank in th e write mode cannot be read. 2. the internal instruction ram (i n the read mode) is accessed using the 1 internal system clock. (2) write operation the internal instruction ram can be written by normal ram access without having to be aware of the banks if the write mode is selected by the iramm register. cautions 1. a bank in the read mode cannot be written. 2. internal instruction ram bank 0 area is allocated to interrupt and exception tables. disable interrupts until writing an instruction code to bank 0 of the internal instruction ram is completed. similarly, disable interrupts when bank 0 of the internal instruction ram is set in the write mode. for disabling maskable interr upts, refer to interrupt mask re gisters 0 to 5 (imr0 to imr5) (7.3.5 interrupt mask registers 0 to 5 (imr0 to imr5)). to disable the non-maskable interrupt, set the np bit of the psw to 1 to disable multiple interrupts (see 3.2.2 (2) program status word (psw)). for the nmi mask operation when reset is cleared, refer to the nmi reset status register (nrs) (7.3 .6 nmi reset status register (nrs)). 3. when the internal instruction ram is accessed (in the write mode), programmable waits, address setup waits, and idle states can be inserted in the cs0 space. if none of the above states is set, the instruction ram is accessed using a 2 busclk frequency clock. chapter 4 bus control function 163 user?s manual u16031ej3v0ud 4.10.3 cautions (1) disable all interrupts from when reset is cleared until when program codes are completely transferred to the internal instruction ram. it is not necessary to disable maskable interrupts because they are masked by default. because the software exception and except ion trap cannot be masked, do not execute the trap and dbtrap instructions until transfer of program code s to the internal instruction ram is completed. (2) after reset has been cleared, the nmi input is ma sked by hardware. the nmi is unmasked as soon as the iramm0 bit of the iramm register has been cleared to 0. (3) to write data to instruction ram bank 0 of the internal instruction ram, set the np bit of the psw to 1 to disable the nmi and maskable interrupts and suppress o ccurrence of the software exception and exception trap. clear the np bit by setting the iramm0 bit of the iramm register to 1 and confirming that the read mode is set, after the program has been rewritten. (4) nmi or maskable interrupt requests that have been gener ated while the np bit of the psw is set to 1 are held pending. an nmi request is acknowledged immediately after the np bit has been cleared to 0. a maskable interrupt is acknowledged immediately after the np bit has been cleared to 0, if the interrupt request is not cleared (by clearing the xxifn bit of the interrupt control re gister (xxicn) to 0), if interrupts are not disabled (di status), and if the xxmkn bit of the inte rrupt control register is not set to 1 before the np bit is cleared to 0. however, only one interrupt request, nmi request or a maskable interrupt request, can be held pending per interrupt source. even if the same interrupt request is generated more than once, only the first interrupt request is acknowledged (xx: peripheral unit identification name (see table 7-2 ), n: peripheral unit number (see table 7-2 )). (5) when the internal instruction ram is accessed (in the write mode), the address bus and data bus output data. the external bus control signals other than uuwr, ulwr, luwr, llwr, and wr become active. if output of the iowr signal is enabled by setting the ioen bit of the bus cycle period control register (bcp) to 1, the iowr signal becomes inactive. chapter 4 bus control function 164 user?s manual u16031ej3v0ud 4.11 bus hold function 4.11.1 function outline if the pcm2 and pcm3 pins are specified in the contro l mode, the hldak and hldrq functions become valid. if it is determined that the hldrq pin has become active (low level) as a bus mastership request from another bus master, the external address/data bus and each strobe pin ar e shifted to high impedance and then released (bus hold state). if the hldrq pin becomes inactive (high level) an d the bus mastership request is canceled, driving of these pins begins again. during the bus hold period, the internal operations of the v850e/me2 continue until the external memory or a peripheral i/o register is accessed. the bus hold state can be known by the hldak pin becoming active (low level). the period from when the hldrq pin becomes active (low level) to when the hldak pin becomes acti ve (low level) is at least 2 clocks. in a multiprocessor configurati on, etc., a system with multiple bus masters can be configured. state data bus width access type timing at which bus hold request cannot be acknowledged between first and second accesses word access for 4n+1 address between second and third accesses word access for 4n+2 address between first and second accesses between first and second accesses word access for 4n+3 address between second and third accesses 32 bits halfword access for odd address between first and second accesses word access for even address between first and second accesses between first and second accesses word access for odd address between second and third accesses 16 bits halfword access for odd address between first and second accesses between first and second accesses between second and third accesses word access between third and forth accesses cpu bus lock 8 bits halfword access between first and second accesses read modify write access of bit manipulation instruction ? ? chapter 4 bus control function 165 user?s manual u16031ej3v0ud 4.11.2 bus hold procedure the procedure of the bus hold function is illustrated below. <1> hldrq = 0 acknowledged <2> all bus cycle start requests held pending <3> end of current bus cycle <4> transition to bus idle state <5> hldak = 0 <6> hldrq = 1 acknowledged <7> hldak = 1 <8> pending bus cycle start requests released <9> start of bus cycle normal state bus hold state normal state hldak (output) hldrq (input) <1> <2> <3><4> <5> <6> <7><8><9> 4.11.3 operation in power-save mode in the software stop or idle mode, the internal system clock is stopped. consequently , the bus hold state is not set since the hldrq pin cannot be acknow ledged even if it becomes active. in the halt mode, the hldak pin immediately becomes active when the hldrq pin becomes active, and the bus hold state is set. when the hldrq pin becomes inactive a fter that, the hldak pin also becomes inactive. as a result, the bus hold state is cleared and the halt mode is set again. chapter 4 bus control function 166 user?s manual u16031ej3v0ud 4.11.4 bus hold timing (1) if bus hold request is issued when bus cycle is not generated busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) note 3 (output) d0 to d31 (input) wait (input) rd (output) hldrq (input) hldak (output) th ti note 1 th t0 note 2 ti note 1 undefined undefined ti note 1 notes 1. this idle state (ti) is independ ent of the bcc register setting. 2. state (t0) inse rted between bus cycles 3. llwr/llbe/lldqm, uuwr/uu be/uudqm, luwr/lube/ludqm, ulwr/ulbe/uldqm, we/wr, iord, iowr, sdras, sdcas remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. chapter 4 bus control function 167 user?s manual u16031ej3v0ud 4.11.5 bus hold timing (sram) (1) sram (when read, without speculative re ad, no idle state insertion, busclk = f clk /2) notes 1. state (t0) insert ed between bus cycles 2. this idle state (ti) is independ ent of the bcc register setting. 3. when the ioen bit of the bcp register is set to 1. 4. uube, ulbe, lube, llbe remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. undefined undefined data address busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) note 4 (output) iord note 3 , rd (output) hldrq (input) hldak (output) d0 to d31 (input) wait (input) wr, iowr (output) t1 t0 note 1 t2 ti note 2 th th t0 note 1 chapter 4 bus control function 168 user?s manual u16031ej3v0ud (2) sram (when read, with speculative read, no idle state insertion, busclk = f clk /2) notes 1. this idle state (ti) is independ ent of the bcc register setting. 2. state (t0) insert ed between bus cycles 3. when the ioen bit of the bcp register is set to 1. 4. uube, ulbe, lube, llbe remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. t1 t2 th t2 undefined data data ti note 1 busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) note 4 (output) iord note 3 , rd (output) hldrq (input) hldak (output) d0 to d31 (input) wait (input) wr, iowr (output) address t1 th chapter 4 bus control function 169 user?s manual u16031ej3v0ud (3) sram (when written, two id le states inserted, busclk = f clk /2) notes 1. state (t0) insert ed between bus cycles 2. this idle state (ti) is inserted by means of a bcc register setting. 3. this idle state (ti) is independ ent of the bcc register setting. 4. when the ioen bit of the bcp register is set to 1. 5. uube, ulbe, lube, llbe remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. undefined undefined t1 data busclk (output) d0 to d31 (input) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) note 5 (output) iowr note 4 , wr (output) hldrq (input) hldak (output) wait (input) rd, iord (output) address t0 note 1 t2 ti note 2 ti note 2 ti note 3 th th t0 note 1 chapter 4 bus control function 170 user?s manual u16031ej3v0ud 4.11.6 bus hold timing (sdram) (1) sdram (when read, latency = 2, no idle state insertion) tread row tlate tlate tact busclk (output) a2 to a11 (output) csn (output) sdras (output) bcyst (output) we (output) sdcas (output) col . t0 note 1 row a12 note 4 (output) bnk . bank address (output) address note 5 (output) address h th th ti note 2 ti note 2 t0 note 1 tpre note 3 undefined undefined undefined undefined hldrq (input) hldak (output) undefined undefined undefined undefined d0 to d31 (input) data note 7 (output) h sdcke (output) note 6 (output) notes 1. state (t0) insert ed between bus cycles 2. this idle state (ti) is independ ent of the bcc register setting. 3. the all-bank precharge command is always executed. 4. this is the signal when the 32-bit external bus is used. read it as a11 when the 16-bit bus is used, and a10 when the 8-bit bus is used. 5. addresses other than the bank address, a12, and a2 to a11. 6. when xxwr output mode/xxdqm output mode is set (pfcctm bit of pfcct register = 0) 7. when xxbe output mode/xxdqm output mode is set (pfcctm bit of pfcct register = 1) remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 1, 3, 4, 6 m = 0 to 3 xx = uu, ul, lu, ll 4. bnk.: bank address col.: column address row: row address chapter 4 bus control function 171 user?s manual u16031ej3v0ud (2) sdram (when read, latency = 2, two idle states inserted, 32-bit bus width) tread row tlate tlate tact busclk (output) a2 to a11 (output) csn (output) sdras (output) bcyst (output) we (output) sdcas (output) col. t0 note 1 row a12 note 5 (output) bnk. bank address (output) address note 6 (output) address h th ti note 2 th ti note 3 t0 note 1 tpre note 4 undefined undefined undefined undefined hldrq (input) hldak (output) undefined undefined ti note 3 ti note 2 undefined undefined d0 to d31 (input) data note 7 (output) h sdcke (output) note 8 (output) notes 1. state (t0) insert ed between bus cycles 2. this idle state (ti) is inserted by means of a bcc register setting. 3. this idle state (ti) is independ ent of the bcc register setting. 4. the all-bank precharge command is always executed. 5. this is the signal when the 32-bit external bus is used. read it as a11 when the 16-bit bus is used, and a10 when the 8-bit bus is used. 6. addresses other than the bank address, a12, and a2 to a11. 7. when xxwr output mode/xxdqm out put mode is set (pfcctm bit of pfcct register = 0) 8. when xxbe output mode/xxdqm output mode is set (pfcctm bit of pfcct register = 1) remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 1, 3, 4, 6 m = 0 to 3 xx = uu, ul, lu, ll 4. bnk.: bank address col.: column address row: row address chapter 4 bus control function 172 user?s manual u16031ej3v0ud (3) sdram (when written) twr tact t0 note 1 busclk (output) a2 to a11 (output) csn (output) sdras (output) bcyst (output) we (output) sdcas (output) a12 note 4 (output) bank address (output) note 5 (output) address row col. bnk.a row address undefined undefined undefined undefined undefined undefined th th ti note 2 ti note 2 t0 note 1 tpre note 3 hldrq (input) hldak (output) undefined undefined note 7 (output) d0 to d31 (i/o) data h sdcke (output) note 6 (output) notes 1. state (t0) insert ed between bus cycles 2. this idle state (ti) is independ ent of the bcc register setting. 3. the all-bank precharge command is always executed. 4. this is the signal when the 32-bit external bus is used. read it as a11 when the 16-bit bus is used, and a10 when the 8-bit bus is used. 5. addresses other than the bank address, a12, and a2 to a11. 6. when xxwr output mode/xxdqm out put mode is set (pfcctm bit of pfcct register = 0) 7. when xxbe output mode/xxdqm output mode is set (pfcctm bit of pfcct register = 1) remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 1, 3, 4, 6 m = 0 to 3 xx = uu, ul, lu, ll 4. bnk.: bank address col.: column address row: row address chapter 4 bus control function 173 user?s manual u16031ej3v0ud (4) sdram (when written, when bus hold request ackno wledged during on-page access) notes 1. state (t0) insert ed between bus cycles 2. this idle state (ti) is independ ent of the bcc register setting. 3. the all-bank precharge command is always executed. 4. this is the signal when the 32-bit external bus is used. read it as a11 when the 16-bit bus is used, and a10 when the 8-bit bus is used. 5. addresses other than the bank address, a12, and a2 to a11. 6. uudqm, uldqm, ludqm, lldqm remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 1, 3, 4, 6 4. col.: column address busclk (output) a2 to a11 (output) csn (output) sdras (output) note 6 (output) bcyst (output) we (output) d0 to d31 (i/o) sdcas (output) a12 note 4 (output) bank address (output) note 5 (output) col. address data undefined undefined undefined undefined undefined undefined th ti note 2 t0 note 1 tpre note 3 hldrq (input) hldak (output) undefined undefined ti note 2 h sdcke (output) t0 note 1 twr ti note 2 th chapter 4 bus control function 174 user?s manual u16031ej3v0ud 4.12 bus priority order there are five external bus cycles: bus hold, instructio n fetch, operand data access, dma cycle, and refresh cycle. in order of priority, bus hold is t he highest, followed by the refresh cycle, dma cycle, operand data access, and instruction fetch, in that order. an instruction fetch may be inserted between a read acce ss and write access during a read modify write access. also, an instruction fetch may be inserted between bus accesses when the cpu bus clock is used. table 4-2. bus priority order priority order external bus cycle bus master bus hold external device refresh cycle sdram controller dma cycle dma controller operand data access cpu high low instruction fetch cpu 4.13 boundary operation conditions 4.13.1 program space branching to the on-chip peripheral i/o ar ea is prohibited. if the above is performed, undefined data is fetched, and fetching from the external memory is not performed. 4.13.2 data space the v850e/me2 is provided with an address misalign function. through this function, regardless of the data format (wor d or halfword), data can be allocated to all addresses. however, in the case of word data an d halfword data, if the data is not s ubject to boundary alignment, the bus cycle will be generated at least 2 times and bus efficiency will drop. (1) external bus width: 16 bits (a) in the case of halfword-length data access when the address?s lsb is 1, a byte-len gth bus cycle will be generated 2 times. (b) in the case of word-length data access (i) when the address?s lsb is 1, bus cycles will be generated in the order of byte-length bus cycle, halfword-length bus cycle, an d byte-length bus cycle. (ii) when the address?s lower 2 bits are 10, a halfword-length bus cycle will be generated 2 times. chapter 4 bus control function 175 user?s manual u16031ej3v0ud (2) external bus width: 32 bits (a) in the case of halfword-length data access when the address?s lower 2 bits are 11, a byte-length bus cycle will be generated 2 times. (b) in the case of word-length data access when the address?s lower 2 bits are 10, a ha lfword-length bus cycle will be generated 2 times. 4.14 timing at which t0 state is not inserted a t0 state is not inserted at the following timing. (1) read { during a refill operation when instruction cache is used (in t he second and subsequent cycles) { during speculative reading (in the second and subsequent cycles) { if a read request (including a read request by inst ruction fetch or dma) is generated before a write operation to the external device is completed when a read operation occurs immediately after a write operation { if a read request (including a read request by instructio n fetch or dma) that is greater than the bus width of the external device is generated (in the second and subsequent cycles) [example] ? 32-bit read access with 16-bit external bus width ? 32-bit or 16-bit read access with 8-bit external bus width (2) write { if a write request (including a write request by dma) is generated before a write operation to the external device is completed when a write operation occurs imm ediately after a write operat ion, and data is stored in the write buffer (a cycle in which the data stored in the write buffer is written to the external device) { if a write request (including a write request by dma) is generated during a speculative read operation (if data is stored in the write buffer) { if a write request (including a write request by dma) greater than the bus width of the external bus is generated (after the second and subsequent cycles) [example] ? 32-bit write access with external 16-bit bus width ? 32-bit or 16-bit write access with external 8-bit bus 176 user?s manual u16031ej3v0ud chapter 5 memory ac cess control function 5.1 sram, external rom, external i/o interface 5.1.1 features ? sram is accessed in a minimum of 2 states. ? up to 7 states of programmable data waits can be in serted by setting the dwc0 and dwc1 registers (dma flyby transfer: fwc register). ? data wait can be controlled via wait pin input. ? up to 3 idle states can be insert ed after a read/write cycle by setting the bcc register (dma flyby transfer: fic register). ? up to 3 address setup wait states can be inserted by setting the asc register. ? dma flyby transfer can be activated (sram external i/o, external i/o sram) chapter 5 memory access control function 177 user?s manual u16031ej3v0ud 5.1.2 sram connection examples of connection to sram are shown below. figure 5-1. examples of connection to sram (1/2) (a) when data bus width is 8 bits v850e/me2 a2 to a18 d24 to d31 csn rd uuwr d16 to d23 ulwr d8 to d15 luwr d0 to d7 llwr a0 to a16 i/o1 to i/o8 cs oe we a0 to a16 i/o1 to i/o8 cs oe we a0 to a16 i/o1 to i/o8 cs oe we a0 to a16 i/o1 to i/o8 cs oe we sram (128 kwords 8 bits) sram (128 kwords 8 bits) sram (128 kwords 8 bits) sram (128 kwords 8 bits) remark n = 0 to 7 chapter 5 memory access control function 178 user?s manual u16031ej3v0ud figure 5-1. examples of connection to sram (2/2) (b) when data bus width is 16 bits v850e/me2 a2 to a19 d16 to d31 csn rd uube ulbe wr d0 to d15 lube llbe a0 to a17 i/o1 to i/o16 cs oe hb lb we sram (256 kwords 16 bits) a0 to a17 i/o1 to i/o16 cs oe hb lb we sram (256 kwords 16 bits) remark n = 0 to 7 chapter 5 memory access control function 179 user?s manual u16031ej3v0ud 5.1.3 sram, external rom, external i/o access figure 5-2. sram, external rom, external i/o access timing (1/10) (a) when read (without speculative read) t2 tw t0 note 1 t0 note 1 t0 note 1 data data busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) note 2 (output) d0 to d31 (input) wait (input) rd (output) t1 t2 t1 address address notes 1. state (t0) insert ed between bus cycles 2. uube, ulbe, lube, llbe remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. chapter 5 memory access control function 180 user?s manual u16031ej3v0ud figure 5-2. sram, external rom, external i/o access timing (2/10) (b) when read (without sp eculative read, address setup wait, idle state insertion) t2 ti t0 note 1 data busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) note 2 (output) d0 to d31 (input) wait (input) rd (output) t1 tasw t0 note 1 address notes 1. state (t0) insert ed between bus cycles 2. uube, ulbe, lube, llbe remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. chapter 5 memory access control function 181 user?s manual u16031ej3v0ud figure 5-2. sram, external rom, external i/o access timing (3/10) (c) when read (with specula tive read, 32-bit bus width) data data data data t1 t2 t1 t2 t1 t2 t1 t2 busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) note 2 (output) d0 to d31 (input) wait (input) rd (output) t0 note 1 t0 note 1 address a address a+4 address a+c address a+8 notes 1. state (t0) insert ed between bus cycles 2. uube, ulbe, lube, llbe remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. chapter 5 memory access control function 182 user?s manual u16031ej3v0ud figure 5-2. sram, external rom, external i/o access timing (4/10) (d) when read (with specula tive read, access on another line) penalty cycle accompanying with another line access request address b address a data data data data t1 t2 t1 t2 t1 t2 t1 t2 t1 t2 speculative read cycle (fill cycle of speculative read buffer) speculative read cycle busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) note 2 (output) d0 to d31 (input) wait (input) rd (output) address a+4 address a+8 address a+c data t0 note 1 access by cpu read from address (a) read from address (b) notes 1. state (t0) insert ed between bus cycles 2. uube, ulbe, lube, llbe remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. chapter 5 memory access control function 183 user?s manual u16031ej3v0ud figure 5-2. sram, external rom, external i/o access timing (5/10) (e) when read (with speculative read, 32-bit bus width, address setup wait, idle state insertion) data t1 t2 tasw ti address a+c data t1 t2 tasw ti address a+8 data t1 t2 tasw ti address a+4 data t1 t2 tasw ti address a busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) note 2 (output) d0 to d31 (input) wait (input) rd (output) t0 note 1 t0 note 1 notes 1. state (t0) insert ed between bus cycles 2. uube, ulbe, lube, llbe remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. chapter 5 memory access control function 184 user?s manual u16031ej3v0ud figure 5-2. sram, external rom, external i/o access timing (6/10) (f) when written (1/2) access by cpu wr (output) busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) note 2 (output) d0 to d31 (output) wait (input) data t1 t2 t1 t0 note 1 address a write to address (a) write to address (b) data t2 tw address b t0 note 1 t0 note 1 (f) when written (2/2) access by cpu data wr (output) busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) note 2 (output) d0 to d31 (output) wait (input) data t1 t2 t1 t2 tw t0 note 1 address a address b write to address (a) write to address (b) t0 note 1 notes 1. state (t0) insert ed between bus cycles 2. uube, ulbe, lube, llbe remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. chapter 5 memory access control function 185 user?s manual u16031ej3v0ud figure 5-2. sram, external rom, external i/o access timing (7/10) (g) when written (address set up wait, idle state insertion) t1 t2 tasw ti t0 note 1 data wr (output) busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) note 2 (output) d0 to d31 (output) wait (input) address notes 1. state (t0) insert ed between bus cycles 2. uube, ulbe, lube, llbe remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. chapter 5 memory access control function 186 user?s manual u16031ej3v0ud figure 5-2. sram, external rom, external i/o access timing (8/10) (h) for read (without speculative read) write operation t1 t2 t1 t2 t0 note 1 t0 note 1 wr (output) data data busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) note 2 (output) d0 to d31 (input) wait (input) rd (output) address address notes 1. state (t0) insert ed between bus cycles 2. uube, ulbe, lube, llbe remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. chapter 5 memory access control function 187 user?s manual u16031ej3v0ud figure 5-2. sram, external rom, external i/o access timing (9/10) (i) for write read operation (1/2) access by cpu data data busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) note 2 (output) d0 to d31 (input) wait (input) rd (output) t1 t2 t1 t2 t0 note 1 address a address b t0 note 1 wr (output) write to address (a) read from address (b) notes 1. state (t0) insert ed between bus cycles 2. uube, ulbe, lube, llbe remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. chapter 5 memory access control function 188 user?s manual u16031ej3v0ud figure 5-2. sram, external rom, external i/o access timing (10/10) (i) for write read operation (2/2) wr (output) access by cpu write to address (a) read from address (b) data data busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) note 2 (output) d0 to d31 (input) wait (input) rd (output) t1 t2 t1 t2 t0 note 1 address a address b notes 1. state (t0) insert ed between bus cycles 2. uube, ulbe, lube, llbe remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. chapter 5 memory access control function 189 user?s manual u16031ej3v0ud 5.2 page rom controller (romc) the page rom controller (romc) is provided for a ccessing rom (page rom) with a page access function. addresses are compared with the immediately preceding bus cycle and wait control fo r normal access (off-page) and page access (on-page) is executed. this controll er can handle page widths from 8 to 128 bytes. 5.2.1 features ? ? ? ? ? ? ? ? ? chapter 5 memory access control function 190 user?s manual u16031ej3v0ud 5.2.2 page rom connection examples of connection to page rom are shown below. figure 5-3. examples of connection to page rom (a) when data bus width is 16 bits v850e/me2 a2 to a21 d16 to d31 csn rd d0 to d15 a0 to a19 o0 to o15 ce oe page rom (1 mword 16 bits) a0 to a19 o0 to o15 ce oe page rom (1 mword 16 bits) (b) when data bus width is 8 bits v850e/me2 a2 to a22 d24 to d31 csn rd d16 to d23 d8 to d15 d0 to d7 a0 to a20 o0 to o7 ce oe page rom (2 mwords 8 bits) a0 to a20 o0 to o7 ce oe page rom (2 mwords 8 bits) a0 to a20 o0 to o7 ce oe page rom (2 mwords 8 bits) a0 to a20 o0 to o7 ce oe page rom (2 mwords 8 bits) remark n = 0 to 7 chapter 5 memory access control function 191 user?s manual u16031ej3v0ud 5.2.3 on-page/off-page judgment whether a page rom cycle is on-page or off-page is jud ged by latching the address of the previous cycle and comparing it with the address of the current cycle. if no speculative reading is specified (rbn1 and rbn0 bits of the lbcm register = 00, 01) or us e of the instruction cache is not specified, an off-page cycle is always started, except in the following cases (m = 0, 1, n = 0 to 7). ? ? chapter 5 memory access control function 192 user?s manual u16031ej3v0ud 5.2.4 page rom configuration register (prc) the masking address (no comparison is made) out of t he addresses (a3 to a6) corresponding to the configuration of the connected page rom and the number of bits that can be read continuously , as well as the number of waits corresponding to the internal system clock, are set. this register can be read or written in 16-bit units. caution write to the prc register after reset, an d then do not change the set value. also, do not access an external memory area other than the one for this initializat ion routine until the initial setting of the prc register is comple te. however, it is possible to access external memory areas whose initiali zation settings are complete. 15 0 prc address fffff49ah after reset 7000h 14 prw2 13 prw1 12 prw0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 ma6 2 ma5 1 ma4 0 ma3 bit position bit name function sets the number of waits correspondi ng to the internal system clock. the number of waits set by these bits is in serted only for on-page access. for off-page access, the waits set by registers dwc0 and dwc1 are inserted. prw2 prw1 prw0 number of inserted wait cycles 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 14 to 12 prw2 to prw0 each respective address (a6 to a3) correspondi ng to ma6 to ma3 is masked (by 1). the masked address is not subject to compar ison during on/off-page judgment, and is set according to the number of continuously readable bits. ma6 ma5 ma4 ma3 number of continuously readable bits 0 0 0 0 2 32 bits, 4 16 bits, 8 8 bits 0 0 0 1 4 32 bits, 8 16 bits, 16 8 bits 0 0 1 1 8 32 bits, 16 16 bits, 32 8 bits 0 1 1 1 16 32 bits, 32 16 bits, 64 8 bits 1 1 1 1 32 32 bits, 64 16 bits, 128 8 bits other than above setting prohibited (the operation cannot be guaranteed if other bits are set.) 3 to 0 ma6 to ma3 chapter 5 memory access control function 193 user?s manual u16031ej3v0ud 5.2.5 page rom access figure 5-5. page rom access timing (1/6) (a) when read (without speculative read, 32- bit bus width, other than cache fill operation) t1 t2 t1 t2 t1 t2 t1 t2 t0 note 1 t0 note 1 t0 note 1 t0 note 1 data busclk (output) a0 to a25 (output) cs0 to cs7 (output) rd (output) wr (output) bcyst (output) note 2 (output) d0 to d31 (input) wait (input) off-page address off-page address h data data data off-page address off-page address t0 note 1 notes 1. state (t0) insert ed between bus cycles 2. uube, ulbe, lube, llbe remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. chapter 5 memory access control function 194 user?s manual u16031ej3v0ud figure 5-5. page rom access timing (2/6) (b) when read (without speculative read , 32-bit bus width, cache fill operation) busclk (output) a0 to a25 (output) cs0 to cs7 (output) rd (output) wr (output) bcyst (output) note 3 (output) d0 to d31 (input) wait (input) t1 t2 to1 to2 to1 to2 to1 to2 h address a address a+4 address a+8 address a+c data data data data t0 note 1 t0 note 1 tw note 2 on-page on-page on-page off-page notes 1. state (t0) insert ed between bus cycles 2. programmable wait = 1 wait insertion 3. uube, ulbe, lube, llbe remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. chapter 5 memory access control function 195 user?s manual u16031ej3v0ud figure 5-5. page rom access timing (3/6) (c) when read (with specu lative read, 32-bit bus width) data t1 tw tw tw t2 to1 tow to2 to1 tow to2 to1 tow to2 data data data address a+8 address a+c address a+4 busclk (output) a0 to a25 (output) cs0 to cs7 (output) rd (output) wr (output) bcyst (output) note 2 (output) d0 to d31 (input) wait (input) address a t0 note 1 h t0 note 1 on-page on-page on-page off-page notes 1. state (t0) insert ed between bus cycles 2. uube, ulbe, lube, llbe remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. chapter 5 memory access control function 196 user?s manual u16031ej3v0ud figure 5-5. page rom access timing (4/6) (d) when read (without specula tive read, address setup wait, idle state insertion, 32-bit bus wid th, other than cache fill operation) t0 note 1 t1 t2 tasw ti t0 note 1 t1 t2 tasw ti t1 t2 tasw ti t0 note 1 t1 t2 tasw ti t0 note 1 t0 note 1 busclk (output) a0 to a25 (output) cs0 to cs7 (output) rd (output) wr (output) bcyst (output) note 2 (output) d0 to d31 (input) wait (input) h off-page address data off-page address data off-page address data off-page address data notes 1. state (t0) insert ed between bus cycles 2. uube, ulbe, lube, llbe remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. chapter 5 memory access control function 197 user?s manual u16031ej3v0ud figure 5-5. page rom access timing (5/6) (e) when read (without speculative read, address setup wait, idle state insertion, 32-bit bus width, cache fill operation) on-page on-page on-page off-page data address a0 address a+4 address a+8 tasw t1 t2 to1 to2 to1 to2 to1 to2 ti address a+c data data data busclk (output) a0 to a25 (output) cs0 to cs7 (output) rd (output) wr (output) bcyst (output) note 2 (output) d0 to d31 (input) wait (input) t0 note 1 h notes 1. state (t0) insert ed between bus cycles 2. uube, ulbe, lube, llbe remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. chapter 5 memory access control function 198 user?s manual u16031ej3v0ud figure 5-5. page rom access timing (6/6) (f) when read (with speculative read, address setup wait, idle st ate insertion, 32-bit bus width) data tasw t1 tw tw tw t2 to1 tow to2 to1 tow to2 to1 tow to2 data data data address a+8 address a+c address a+4 busclk (output) a0 to a25 (output) cs0 to cs7 (output) rd (output) wr (output) bcyst (output) note 2 (output) d0 to d31 (input) wait (input) address a t0 note 1 ti h on-page on-page on-page off-page notes 1. state (t0) insert ed between bus cycles 2. uube, ulbe, lube, llbe remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. chapter 5 memory access control function 199 user?s manual u16031ej3v0ud 5.3 dram controller (sdram) 5.3.1 features ? burst length: 1 ? wrap type: sequential ? cas latency: 1, 2, and 3 supported (only 2 and 3 supported during dma flyby transfer) ? 4 types of sdram can be assigned to 4 memory blocks. ? row and column address multiplex widths can be changed. ? waits (0 to 3 waits) can be inserted between t he bank active command and the read/write command. ? supports cbr refresh and cbr self-refresh. ? dma flyby cycle (from external i/o to sdram) can be activated. 5.3.2 sdram connection an example of connection to sdram is shown below. figure 5-6. example of connection to sdram v850e/me2 a2 to a13 a22, a23 note d16 to d31 busclk sdcke csn sdras sdcas uudqm uldqm we d0 to d15 ludqm lldqm a0 to a11 a12, a13 dq0 to dq15 clk cke cs ras cas hdqm ldqm we sdram (1 mword 16 bits 4 banks) a0 to a11 a12, a13 dq0 to dq15 clk cke cs ras cas hdqm ldqm we sdram (1 mword 16 bits 4 banks) note the address signals to be used differ depending on the sdram product. remark n = 1, 3, 4, 6 chapter 5 memory access control function 200 user?s manual u16031ej3v0ud 5.3.3 address multiplex function depending on the value of the sawn0 and sawn1 bits in sdram configuration regi ster n (scrn), the row address output in the sdram cycle is multiplexed as shown in figure 5-7 (a) (n = 1, 3, 4, 6). depending on the value of the sson0 and sson1 bits, the column address output in the sdram cycle is multiplexed as shown in figure 5-7 (b) (n = 1, 3, 4, 6). in figures 5-7 (a) and (b), a0 to a25 indicate the addresses output from the cpu, and a0 to a25 indicate the address pins of the v850e/me2. figure 5-7. row address/co lumn address output (1/2) (a) row address output a14 a25 a13 a24 a12 a23 a2 a13 a3 a14 a4 a15 a5 a16 a6 a17 a7 a18 a8 a19 a9 a20 a10 a21 a11 a22 a15 a15 a16 a16 a17 a17 a25 to a18 a25 to a18 a1 a12 a0 a11 a17 a16 a25 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 to a18 a14 a13 a12 a11 a10 row address (sawn1, sawn0 = 11) address pin row address (sawn1, sawn0 = 10) a25 a24 a23 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a17 a25 to a18 a12 a11 a10 a9 a25 a24 a23 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a25 to a18 a12 a11 a10 a9 a8 row address (sawn1, sawn0 = 01) row address (sawn1, sawn0 = 00) remark n = 1, 3, 4, 6 (b) column address output (using all-bank precharge command) a14 a14 a13 a13 a12 a12 a2 a2 a3 a3 a4 a4 a5 a5 a6 a6 a7 a7 a8 a8 a9 a9 a10 1 a11 a11 a15 a15 a16 a16 a17 a17 a25 to a18 a25 to a18 a1 a1 a0 a0 a16 a15 a14 a4 a5 a6 a7 a8 a9 a10 1 a12 a13 a17 a25 to a18 a3 a2 a1 a0 column address (sson1, sson0 = 00) address pin column address (sson1, sson0 = 01) a16 a15 a14 a4 a5 a6 a7 a8 a9 a10 a11 1 a13 a17 a25 to a18 a3 a2 a1 a0 column address (sson1, sson0 = 10) remark n = 1, 3, 4, 6 (c) column address output (usi ng register write command) a14 0 a13 0 a12 0 a2 0 a3 0 a4 ltm0 a5 ltm1 a6 ltm2 a7 0 a8 0 a9 0 a10 0 a11 0 a15 0 a16 0 a17 0 a25 to a18 0 a1 0 a0 0 000 0 0 ltm0 ltm1 ltm2 0 0 0 0 0 0 0 0 00 0 column address (sson1, sson0 = 00) address pin column address (sson1, sson0 = 01) 000 0 0 0 ltm0 ltm1 ltm2 0 0 0 0 0 0 0 00 0 column address (sson1, sson0 = 10) remark n = 1, 3, 4, 6 chapter 5 memory access control function 201 user?s manual u16031ej3v0ud figure 5-7. row address/colu mn address output (2/2) (d) column address output (using read/write command) a14 a14 a13 a12 a12 a11 a2 a2 a3 a3 a4 a4 a5 a5 a6 a6 a7 a7 a8 a8 a9 a9 a10 0 a11 a10 a15 a15 a16 a16 a17 a17 a25 to a18 a25 to a18 a1 a1 a0 a0 a16 a15 a14 a4 a5 a6 a7 a8 a9 a10 0 a11 a12 a17 a25 to a18 a3 a2 a1 a0 column address (sson1, sson0 = 00) address pin column address (sson1, sson0 = 01) a16 a15 a14 a4 a5 a6 a7 a8 a9 a10 a11 0 a12 a17 a25 to a18 a3 a2 a1 a0 column address (sson1, sson0 = 10) remark n = 1, 3, 4, 6 chapter 5 memory access control function 202 user?s manual u16031ej3v0ud 5.3.4 sdram configuration registers 1, 3, 4, 6 (scr1, scr3, scr4, scr6) these registers specify the num ber of waits and the address multiplex width. scrn corresponds to csn (n = 1, 3, 4, 6). for example, to connect sdram to cs1, set scr1. these registers can be read or written in 16-bit units. cautions 1. an sdram read/write cycle is not genera ted prior to executing a register write operation. access sdram after reading the value of the s crn register and confirming that the wcfn bit is set to 1. 2. to write to the scrn register again foll owing access to sdram, clear the men bit of the bct0 and bct1 registers to 0, an d then set it to 1 again befo re performing access (n = 0 to 6). 3. do not execute continuous instructions to wr ite to the scrn register. be sure to insert another instruction between commands to write to the scrn register. 4. start accessing sdram after all the scrn registers have been set. (1/3) 14 ltm12 13 ltm11 12 ltm10 2 raw10 3 raw11 4 sso10 5 sso11 6 bcw10 7 bcw11 8 wcf1 9 0 10 0 11 0 15 0 1 saw11 0 saw10 ltm32 ltm31 ltm30 raw30 raw31 sso30 sso31 bcw30 bcw31 wcf3 0 0 0 0 saw31 saw30 ltm42 ltm41 ltm40 raw40 raw41 sso40 sso41 bcw40 bcw41 wcf4 0 0 0 0 saw41 saw40 ltm62 ltm61 ltm60 raw60 raw61 sso60 sso61 bcw60 bcw61 wcf6 0 0 0 0 saw61 saw60 scr1 scr3 scr4 scr6 address fffff4a4h fffff4ach fffff4b0h fffff4b8h after reset 30c0h 30c0h 30c0h 30c0h bit position bit name function sets the cas latency value for reading. ltmn2 ltmn1 ltmn0 latency 0 0 1 1 (setting prohibited during dma flyby transfer) 0 1 0 2 0 1 1 3 other than above setting prohibited 14 to 12 ltmn2 to ltmn0 8 wcfn indicates that execution of a register write command on sdram has been completed after the scrn register was set. this bit is set to 1 when a register write command is generated. this bit can only be read. 0: setting not completed 1. setting completed remark n = 1, 3, 4, 6 chapter 5 memory access control function 203 user?s manual u16031ej3v0ud (2/3) bit position bit name function specifies the number of wait states inserted from the bank active command to a read/write command, or from the precharge command to the bank active command. bcwn1 bcwn0 number of wait states inserted 0 0 setting prohibited 0 1 1 1 0 2 1 1 3 7, 6 bcwn1, bcwn0 specifies the address shift width during on-page judgment. if the external data bus width is set to 16 or 32 bits, the system does not use the lower address (a0 or a1, a0). set these bits in accordance with the contents of the lbs register corresponding to csn. sson1 sson0 address shift width 0 0 0 bits (external data bus width: 8 bits) 0 1 1 bit (external data bus width: 16 bits) note 1 0 2 bits (external data bus width: 32 bits) note 1 1 setting prohibited 5, 4 sson1, sson0 specifies the row address width. rawn1 rawn0 row address width 0 0 11 bits 0 1 12 bits note 1 0 13 bits note 1 1 setting prohibited 3, 2 rawn1, rawn0 specifies the address multiplex width (col umn address width) during sdram access. sawn1 sawn0 address multiple x width (column address width) 0 0 8 bits 0 1 9 bits 1 0 10 bits note 1 1 11 bits note 1, 0 sawn1, sawn0 remarks 1. the note is described on the next page. 2. n = 1, 3, 4, 6 chapter 5 memory access control function 204 user?s manual u16031ej3v0ud (3/3) note the following setting is prohibited because th e upper limit of the address is exceeded. sson1 sson0 rawn1 rawn0 sawn1 sawn0 setting 0 1 1 0 1 1 data bus width: 16 bits row address width: 13 bits column address width: 11 bits 1 0 0 1 1 1 data bus width: 32 bits row address width: 12 bits column address width: 11 bits 0 data bus width: 32 bits row address width: 13 bits column address width: 10 bits 1 0 1 0 1 1 data bus width: 32 bits row address width: 13 bits column address width: 11 bits remark n = 1, 3, 4, 6 chapter 5 memory access control function 205 user?s manual u16031ej3v0ud 5.3.5 sdram access during power-on or a refresh operation, the all-bank precharge command is always issued for sdram. when accessing sdram after that, therefore, the active command and read/write command are issued in that order (see <1> in figure 5-8). if a page change occurs following this, the prechar ge command, active command, and read/write command are issued in that order (see <2> in figure 5-8). if a bank change occurs, the active command and read/write command for the bank to be accessed next are issued in that order. following this read/write comma nd, the precharge command for the bank that was accessed before the bank currently being accessed will be issued (see <3> in figure 5-8). figure 5-8. state transition of sdram access <1> <3> <2> all-bank precharge command (power on/refresh) bank a active command bank a precharge command bank a active command bank a active command bank b active command bank b read/write command bank a read/write command bank a read/write command read/write command read/write command (on-page access) (page change) (bank change) (bank change) bank a precharge command chapter 5 memory access control function 206 user?s manual u16031ej3v0ud (1) sdram single read cycle the sdram single read cycle is a cycle for reading from sdram by executing a load instruction (ld) for the sdram area, by fetching an instruction, or by 2-cycle dma transfer. in the sdram single read cycle, the active command (act) and read command (rd) are issued to sdram in that order. during on-page access, however, on ly the read command is issued and the precharge command and active command are not issued. when a page change occurs in the same bank, the precharge command (pre) is issued before the active command. a one-state t0 cycle is always inserted immediately before all read commands activated by the cpu. the number of idle states (ti) set by the bus cycle control register (bcc) are inserted after the read cycle (no idle states are inserted, however, if bcn1 and bcn0 are 00) (n = 1, 3, 4, 6). the timing charts of the sdram single read cycle are shown below. caution when executing a write acces s to sram or external i/o afte r read accessing sdram, data conflict may occur depending on the sdram data output float delay time. in such a case, avoid data conflict by inserting an idle stat e in the sdram space via a setting in the bcc register. chapter 5 memory access control function 207 user?s manual u16031ej3v0ud figure 5-9. sdram single read cycle (1/5) (a) during off-page access (when latency = 2, bcw = 1) tread tlate tlate tact t0 note 1 t0 note 1 row busclk (output) a2 to a11 (output) csn (output) sdras (output) bcyst (output) we (output) sdcas (output) col. act rd row a12 note 2 (output) address bnk. bank address (output) address address note 3 (output) address h latency = 1 d0 to d31 (input) note 5 (output) data command note 4 (output) notes 1. state (t0) insert ed between bus cycles 2. addresses other than the bank address, a12, and a2 to a11. 3. this is the signal when the 32-bit external bus is used. read it as a11 when the 16-bit bus is used, and a10 when the 8-bit bus is used. 4. when xxwr output mode/xxdqm out put mode is set (pfcctm bi t of pfcct register = 0) 5. when xxbe output mode/xxdqm output mode is set (pfcctm bit of pfcct register = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 m = 0 to 3 xx = uu, ul, lu, ll 3. bnk.: bank address col.: column address row: row address chapter 5 memory access control function 208 user?s manual u16031ej3v0ud figure 5-9. sdram single read cycle (2/5) (b) during off-page access (laten cy = 2, idle state 2 insertion) tread row tlate tlate tact busclk (output) a2 to a11 (output) csn (output) sdras (output) bcyst (output) we (output) sdcas (output) col. t0 note 1 row a12 note 2 (output) address bnk. bank address (output) address address note 3 (output) address h latency = 2 d0 to d31 (input) note 5 (output) data ti ti t0 note 1 act rd command note 4 (output) notes 1. state (t0) insert ed between bus cycles 2. addresses other than the bank address, a12, and a2 to a11. 3. this is the signal when the 32-bit external bus is used. read it as a11 when the 16-bit bus is used, and a10 when the 8-bit bus is used. 4. when xxwr output mode/xxdqm out put mode is set (pfcctm bi t of pfcct register = 0) 5. when xxbe output mode/xxdqm output mode is set (pfcctm bit of pfcct register = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 m = 0 to 3 xx = uu, ul, lu, ll 3. bnk.: bank address col.: column address row: row address chapter 5 memory access control function 209 user?s manual u16031ej3v0ud figure 5-9. sdram single read cycle (3/5) (c) during off-page access (when late ncy = 2, page change, bcw = 1) tread row tlate tlate tact busclk (output) a2 to a11 (output) csn (output) sdras (output) bcyst (output) we (output) sdcas (output) col. t0 note 1 row a12 note 2 (output) address bnk. bank address (output) address address note 3 (output) address h row row col. address bnk. address address address act rd pre row latency = 2 d0 to d31 (input) data latency = 2 note 5 (output) data page change tact tread tlate tlate tprec t0 note 1 t0 note 1 act rd command note 4 (output) notes 1. state (t0) insert ed between bus cycles 2. addresses other than the bank address, a12, and a2 to a11. 3. this is the signal when the 32-bit external bus is used. read it as a11 when the 16-bit bus is used, and a10 when the 8-bit bus is used. 4. when xxwr output mode/xxdqm out put mode is set (pfcctm bi t of pfcct register = 0) 5. when xxbe output mode/xxdqm output mode is set (pfcctm bit of pfcct register = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 m = 0 to 3 xx = uu, ul, lu, ll 3. bnk.: bank address col.: column address row: row address chapter 5 memory access control function 210 user?s manual u16031ej3v0ud figure 5-9. sdram single read cycle (4/5) (d) during off-page access (latency = 2, bank change) tact tread tlate tlate row col. row address bnk.b address address address row bnk.a address address address address tread row tlate tlate tact busclk (output) a2 to a11 (output) csn (output) sdras (output) bcyst (output) we (output) sdcas (output) col. t0 note 1 act rd row a12 note 2 (output) address bnk.a bank address (output) address address note 3 (output) address h latency = 2 bank change data latency = 2 d0 to d31 (input) note 5 (output) data t0 note 1 t0 note 1 act(bnk.b) rd pre(bnk.a) command note 4 (output) notes 1. state (t0) insert ed between bus cycles 2. addresses other than the bank address, a12, and a2 to a11. 3. this is the signal when the 32-bit external bus is used. read it as a11 when the 16-bit bus is used, and a10 when the 8-bit bus is used. 4. when xxwr output mode/xxdqm out put mode is set (pfcctm bi t of pfcct register = 0) 5. when xxbe output mode/xxdqm output mode is set (pfcctm bit of pfcct register = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 m = 0 to 3 xx = uu, ul, lu, ll 3. bnk.: bank address col.: column address row: row address chapter 5 memory access control function 211 user?s manual u16031ej3v0ud figure 5-9. sdram single read cycle (5/5) (e) during on-page access (when latency = 2, 32-bit bus width) notes 1. state (t0) insert ed between bus cycles 2. addresses other than the bank address, a12, and a2 to a11. 3. this is the signal when the 32-bit external bus is used. read it as a11 when the 16-bit bus is used, and a10 when the 8-bit bus is used. 4. uudqm, uldqm, ludqm, lldqm remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 3. col.: column address tread tlate tlate latency = 2 t0 note 1 h h busclk (output) a2 to a11 (output) csn (output) sdras (output) note 4 (output) bcyst (output) we (output) d0 to d31 (input) sdcas (output) a12 note 2 (output) bank address (output) note 3 (output) col. col. address address address address rd address address data t0 note 1 command chapter 5 memory access control function 212 user?s manual u16031ej3v0ud (2) sdram single write cycle the sdram single write cycle is a cycle for writing to sdram by executi ng a write instruction (st) for the sdram area or by 2-cycle dma transfer. in the sdram single write cycle, the active command (act) and write command (wr) are issued to sdram in that order. during on-page access, however, on ly the write command is issued and the precharge command and active command are not issued. when a page change occurs in the same bank, the precharge command (pre) is issued before the active command. a one-state tw cycle is always inserted immediately before all write commands activated by the cpu. the timing charts of the sdram single write cycle are shown below. chapter 5 memory access control function 213 user?s manual u16031ej3v0ud figure 5-10. sdram single write cycle (1/6) (a) during off-page access twr tact t0 note 1 busclk (output) a2 to a11 (output) csn (output) sdras (output) bcyst (output) we (output) sdcas (output) a12 note 2 (output) bank address (output) note 3 (output) address row col. wr act(bnk.a) bnk.a row d0 to d31 (i/o) data note 5 (output) command note 4 (output) notes 1. state (t0) insert ed between bus cycles 2. addresses other than the bank address, a12, and a2 to a11. 3. this is the signal when the 32-bit external bus is used. read it as a11 when the 16-bit bus is used, and a10 when the 8-bit bus is used. 4. when xxwr output mode/xxdqm out put mode is set (pfcctm bi t of pfcct register = 0) 5. when xxbe output mode/xxdqm output mode is set (pfcctm bit of pfcct register = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 m = 0 to 3 xx = uu, ul, lu, ll 3. bnk.: bank address col.: column address row: row address chapter 5 memory access control function 214 user?s manual u16031ej3v0ud figure 5-10. sdram single write cycle (2/6) (b) page change (1/2) twr tact tw tact twr tprec t0 note 1 busclk (output) a2 to a11 (output) csn (output) sdras (output) bcyst (output) we (output) sdcas (output) a12 note 2 (output) bank address (output) note 3 (output) address row col.(a) wr act(bnk.a) address address act(bnk.a) pre(bnk.a) address address wr bnk.a row row row col.(b) bnk.a address address address address page change d0 to d31 (i/o) note 5 (output) data data access by cpu write to address (a) write to address (b) command note 4 (output) notes 1. state (t0) insert ed between bus cycles 2. addresses other than the bank address, a12, and a2 to a11. 3. this is the signal when the 32-bit external bus is used. read it as a11 when the 16-bit bus is used, and a10 when the 8-bit bus is used. 4. when xxwr output mode/xxdqm out put mode is set (pfcctm bi t of pfcct register = 0) 5. when xxbe output mode/xxdqm output mode is set (pfcctm bit of pfcct register = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 m = 0 to 3 xx = uu, ul, lu, ll 3. bnk.: bank address col.: column address row: row address chapter 5 memory access control function 215 user?s manual u16031ej3v0ud figure 5-10. sdram single write cycle (3/6) (b) page change (2/2) access by cpu write to address (a) write to address (b) twr tact t0 note 1 tact twr tprec t0 note 1 busclk (output) a2 to a11 (output) csn (output) sdras (output) bcyst (output) we (output) sdcas (output) a12 note 2 (output) bank address (output) note 3 (output) address row col.(a) wr act(bnk.a) address address act(bnk.a) pre(bnk.a) address wr bnk.a row row row col.(b) bnk.a address address address address page change d0 to d31 (i/o) note 5 (output) data data command note 4 (output) notes 1. state (t0) insert ed between bus cycles 2. addresses other than the bank address, a12, and a2 to a11. 3. this is the signal when the 32-bit external bus is used. read it as a11 when the 16-bit bus is used, and a10 when the 8-bit bus is used. 4. when xxwr output mode/xxdqm out put mode is set (pfcctm bi t of pfcct register = 0) 5. when xxbe output mode/xxdqm output mode is set (pfcctm bit of pfcct register = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 m = 0 to 3 xx = uu, ul, lu, ll 3. bnk.: bank address col.: column address row: row address chapter 5 memory access control function 216 user?s manual u16031ej3v0ud figure 5-10. sdram single write cycle (4/6) (c) bank change (1/2) access by cpu write to address (a) write to address (b) twr tact tw t0 note 1 busclk (output) a2 to a11 (output) csn (output) sdras (output) bcyst (output) we (output) sdcas (output) a12 note 2 (output) bank address (output) note 3 (output) address row col.(a) wr act(bnk.a) address address address bnk.a row address tact wpre wend twr wr act(bnk.b) pre(bnk.a) address row col.(b) bnk.b row address row bnk.a address address address address address address address bank change d0 to d31 (i/o) data note 5 (output) data command note 4 (output) notes 1. state (t0) insert ed between bus cycles 2. addresses other than the bank address, a12, and a2 to a11. 3. this is the signal when the 32-bit external bus is used. read it as a11 when the 16-bit bus is used, and a10 when the 8-bit bus is used. 4. when xxwr output mode/xxdqm out put mode is set (pfcctm bi t of pfcct register = 0) 5. when xxbe output mode/xxdqm output mode is set (pfcctm bit of pfcct register = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 m = 0 to 3 xx = uu, ul, lu, ll 3. bnk.: bank address col.: column address row: row address chapter 5 memory access control function 217 user?s manual u16031ej3v0ud figure 5-10. sdram single write cycle (5/6) (c) bank change (2/2) access by cpu twr tact t0 note 1 t0 note 1 busclk (output) a2 to a11 (output) csn (output) sdras (output) bcyst (output) we (output) sdcas (output) a12 note 2 (output) command note 3 (output) address row col.(a) wr act(bnk.a) address address address bnk.a row address tact wpre wend twr wr act(bnk.b) pre(bnk.a) address row col.(b) bnk.b row address row bnk.a address address address address address address address write to address (a) write to address (b) bank change d0 to d31 (i/o) data note 5 (output) data command note 4 (output) notes 1. state (t0) insert ed between bus cycles 2. addresses other than the bank address, a12, and a2 to a11. 3. this is the signal when the 32-bit external bus is used. read it as a11 when the 16-bit bus is used, and a10 when the 8-bit bus is used. 4. when xxwr output mode/xxdqm out put mode is set (pfcctm bi t of pfcct register = 0) 5. when xxbe output mode/xxdqm output mode is set (pfcctm bit of pfcct register = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 m = 0 to 3 xx = uu, ul, lu, ll 3. bnk.: bank address col.: column address row: row address chapter 5 memory access control function 218 user?s manual u16031ej3v0ud figure 5-10. sdram single write cycle (6/6) (d) during on-page access (32-bit bus width) twr h t0 note 1 busclk (output) a2 to a11 (output) csn (output) sdras (output) note 3 (output) bcyst (output) we (output) d0 to d31 (i/o) sdcas (output) a12 (output) bank address (output) note 2 (output) data wr col. (a) address address address command notes 1. state (t0) insert ed between bus cycles 2. addresses other than the bank address, a12, and a2 to a11. 3. uudqm, uldqm, ludqm, lldqm remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 3. col.: column address chapter 5 memory access control function 219 user?s manual u16031ej3v0ud (3) sdram access timing control the sdram access timing can be controlled by sdram config uration register n (scrn) (n = 1, 3, 4, 6). for details, see 5.3.4 sdram configuration registers 1, 3, 4, 6 (scr1, scr3, scr4, scr6) . caution wait control by the wait pi n is not available during sdram access. (a) number of waits from bank active command to read/write command the number of wait states from bank active comm and issue to read/write command issue can be set by setting the bcwn1 and bcwn0 bits of the scrn register. bcwn1, bcwn0 = 01b: 1 wait bcwn1, bcwn0 = 10b: 2 waits bcwn1, bcwn0 = 11b: 3 waits (b) number of waits from precharge command to bank active command the number of wait states from precharge command issue to bank active command issue can be set by setting the bcwn1 and bcwn0 bits of the scrn register. bcwn1, bcwn0 = 01b: 1 wait bcwn1, bcwn0 = 10b: 2 waits bcwn1, bcwn0 = 11b: 3 waits (c) cas latency setting when read the cas latency during a read operation can be set by setting the ltmn2 to lt mn0 bits of the scrn register. ltmn2 to ltmn0 = 001b: latency = 1 (setti ng prohibited during dma flyby transfer) ltmn2 to ltmn0 = 010b: latency = 2 ltmn2 to ltmn0 = 011b: latency = 3 (d) number of waits from refresh command to next command the number of wait states from refresh command i ssue to next command issue can be set by setting the bcwn1 and bcwn0 bits of the scrn register. the num ber of wait states becom es four times the value set by bcwn1 and bcwn0 bits. bcwn1, bcwn0 = 01b: 4 waits bcwn1, bcwn0 = 10b: 8 waits bcwn1, bcwn0 = 11b: 12 waits chapter 5 memory access control function 220 user?s manual u16031ej3v0ud figure 5-11. sdram access timing (1/9) (a) when read (with speculative read, 32- bit bus width, bcw = 2, latency = 2) act rd rd tread tread tread tact t0 note 1 tbcw tlate tlate tread row busclk (output) a2 to a11 (output) csn (output) sdras (output) bcyst (output) we (output) sdcas (output) col.(a) row a12 (output) address bnk bank address (output) address address note 2 (output) address h col.(a+4) address address address rd rd col.(a+8) col.(a+c) undefined undefined undefined undefined latency = 2 d0 to d31 (input) note 4 (output) data data data data latency = 2 latency = 2 latency = 2 command note 3 (output) notes 1. state (t0) insert ed between bus cycles 2. addresses other than the bank address, a12, and a2 to a11. 3. when xxwr output mode/xxdqm out put mode is set (pfcctm bi t of pfcct register = 0) 4. when xxbe output mode/xxdqm output mode is set (pfcctm bit of pfcct register = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 m = 0 to 3 xx = uu, ul, lu, ll 3. bnk.: bank address col.: column address row: row address chapter 5 memory access control function 221 user?s manual u16031ej3v0ud figure 5-11. sdram access timing (2/9) (b) when read (with speculative read, access on another line, 32-bit bus width, bcw = 2, latency = 2) rd rd rd rd rd tread row tread tread tact busclk (output) a2 to a11 (output) csn (output) sdras (output) bcyst (output) we (output) sdcas (output) col.(a) t0 note 1 act row a12 (output) address bnk. bank address (output) address address note 2 (outputs) address h tbcw col.(a+4) address address address tlate tlate tread col.(a+8) col.(a+c) undefined undefined undefined undefined address address address col.(b) tw tread access by cpu read from address (a) read from address (b) command latency = 2 d0 to d31 (input) note 4 (output) data data data data speculative r ead cycle (fill cycle of sp eculative read buffer) speculative read cycle latency = 2 latency = 2 latency = 2 note 3 (output) penalty cycle accompanying request to access another line notes 1. state (t0) insert ed between bus cycles 2. addresses other than the bank address, a12, and a2 to a11. 3. when xxwr output mode/xxdqm out put mode is set (pfcctm bi t of pfcct register = 0) 4. when xxbe output mode/xxdqm output mode is set (pfcctm bit of pfcct register = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 m = 0 to 3 xx = uu, ul, lu, ll 3. bnk.: bank address col.: column address row: row address chapter 5 memory access control function 222 user?s manual u16031ej3v0ud figure 5-11. sdram access timing (3/9) (c) when read (16-bit bus width , cache fill operation, latency = 3) tread tlate tread tread tread tread tread tread tread tlate tlate h h latency = 3 t0 note 1 busclk (output) a1 to a10 (output) csn (output) sdras (output) note 3 (output) bcyst (output) we (output) d0 to d15 (i/o) sdcas (output) a11 (output) bank address (output) note 2 (output) col. (a) col. (a+2) rd rd rd rd col. (a+4) undefined data data data data rd rd rd rd col. (a+6) col. (a+8) col. (a+a) col. (a+c) col. (a+e) address address address undefined address address address address address address address address undefined address address address address address address address address undefined address address address address address data data data data t0 note 1 latency = 3 latency = 3 latency = 3 latency = 3 latency = 3 latency = 3 latency = 3 command notes 1. state (t0) insert ed between bus cycles 2. addresses other than the bank address, a11, and a1 to a10. 3. uudqm, uldqm, ludqm, lldqm remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 3. col.: column address chapter 5 memory access control function 223 user?s manual u16031ej3v0ud figure 5-11. sdram access timing (4/9) (d) for read write operation (with speculative read, latency = 2, 32-bit bus width) (1/2) wr rd latency = 2 access by cpu read from address (a) note 4 note 5 write to address (a) data data address h data data speculative read cycle (fill cycle of speculative read buffer) write cycle tread tread tread tread tlate tlate tw twr t0 note 1 busclk (output) a2 to a11 (output) csn (output) sdras (output) note 3 (output) bcyst (output) we (output) d0 to d31 (i/o) sdcas (output) a12 (output) bank address (output) note 2 (output) col. (a) col. (a+4) rd address address rd rd col. (a+8) col. (a+c) col. (a) address address address data penalty cycle accompanying with another line access request latency = 2 latency = 2 latency = 2 command notes 1. state (t0) insert ed between bus cycles 2. addresses other than the bank address, a12, and a2 to a11. 3. uudqm, uldqm, ludqm, lldqm 4. read from address (a+4) 5. read from address (a+8) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 3. col.: column address chapter 5 memory access control function 224 user?s manual u16031ej3v0ud figure 5-11. sdram access timing (5/9) (d) for read write operation (with speculative read, latency = 2, 32-bit bus width) (2/2) wr rd latency = 2 speculative read cycle (fill cycle of speculative read buffer) write cycle access by cpu read from address (a) note 4 note 5 write to (a) note 6 data data address h data data tread tread tread tread tlate tlate t0 note 1 twr t0 note 1 busclk (output) a2 to a11 (output) csn (output) sdras (output) note 3 (output) bcyst (output) we (output) d0 to d31 (i/o) sdcas (output) a12 (output) bank address (output) note 2 (output) col. (a) col. (a+4) rd address address rd rd col. (a+8) col. (a+c) col. (a) address address address data latency = 2 latency = 2 latency = 2 command notes 1. state (t0) insert ed between bus cycles 2. addresses other than the bank address, a12, and a2 to a11. 3. uudqm, uldqm, ludqm, lldqm 4. read from address (a+4) 5. read from address (a+8) 6. read from address (a+c) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 3. col.: column address chapter 5 memory access control function 225 user?s manual u16031ej3v0ud figure 5-11. sdram access timing (6/9) (e) when read (without speculative read, 16-bit bus width word access, pa ge change, bcw = 2, latency = 2) tread tlate tlate tact tbcw tact tbcw tbcw tread tlate tlate tprec t0 note 1 tread row col. act(bnk.a) rd row address bnk.a address address address busclk (output) a 1 to a10 (output) csn (output) sdras (output) bcyst (output) we (output) sdcas (output) a11 (output) bank address (output) note 2 (output) rd col. address address address row col. row address bnk.a address address address col. address address address tread address address address address row row bnk.a address act(bnk.a) rd rd pre(bnk.a) t0 note 1 undefined undefined undefined undefined t0 note 1 undefined undefined undefined undefined bcw bcw bcw latency = 2 note 4 (output) d0 to d15 (input) data data data data latency = 2 page change latency = 2 latency = 2 command note 3 (output) notes 1. state (t0) insert ed between bus cycles 2. addresses other than the bank address, a11, and a1 to a10 3. when xxwr output mode/xxdqm out put mode is set (pfcctm bi t of pfcct register = 0) 4. when xxbe output mode/xxdqm output mode is set (pfcctm bit of pfcct register = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 m = 0 to 3 xx = uu, ul, lu, ll 3. bnk.: bank address col.: column address row: row address chapter 5 memory access control function 226 user?s manual u16031ej3v0ud figure 5-11. sdram access timing (7/9) (f) when read (without speculative read, 16-bit bus wid th word access, bank change, bcw = 2, latency = 2) tread tlate tlate tact tbcw tact tbcw tread tlate tlate t0 note 1 tread act(bnk.a) rd busclk (output) a1 to a10 (output) csn (output) sdras (output) bcyst (output) we (output) sdcas (output) a11 (output) bank address (output) note 2 (output) rd tread act(bnk.b) rd rd pre(bnk.a) t0 note 1 t0 note 1 d0 to d15 (input) bank change row col. row address bnk.a address address address col. address address address col. address address address col. address address address row row bnk.b address undefined bnk.a undefined undefined undefined undefined undefined undefined undefined undefined undefined bcw bcw latency = 2 data data data data latency = 2 latency = 2 latency = 2 command note 4 (output) note 3 (output) notes 1. state (t0) insert ed between bus cycles 2. addresses other than the bank address, a12, and a2 to a11. 3. when xxwr output mode/xxdqm out put mode is set (pfcctm bi t of pfcct register = 0) 4. when xxbe output mode/xxdqm output mode is set (pfcctm bit of pfcct register = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 m = 0 to 3 xx = uu, ul, lu, ll 3. bnk.: bank address col.: column address row: row address chapter 5 memory access control function 227 user?s manual u16031ej3v0ud figure 5-11. sdram access timing (8/9) (g) for write read operation twr tact tbcw tw tact tbcw tbcw twr tprec tw tact tbcw tlate tlate tread t0 note 1 address row col.(a) wr act(bnk.a) address address bnk.a row address wr act(bnk.a) pre(bnk.a) address address row address address address address address row address row bnk.a address bnk.a address busclk (output) a2 to a11 (output) csn (output) sdras (output) bcyst (output) we (output) sdcas (output) a12 note 2 (output) bank address (output) note 3 (output) act(bnk.b) rd pre(bnk.a) address address row address address address col.(c) address row bnk.b address col.(b) address address address address address address address address row bnk.a address bcw bcw bcw bcw page change bank change latency = 2 note 5 (output) d0 to d31 (i/o) data data data access by cpu write to (a) write to (b) read from (c) command note 4 (output) notes 1. state (t0) insert ed between bus cycles 2. addresses other than the bank address, a12, and a2 to a11. 3. this is the signal when the 32-bit external bus is used. read it as a11 when the 16-bit bus is used, and a10 when the 8-bit bus is used. 4. when xxwr output mode/xxdqm out put mode is set (pfcctm bi t of pfcct register = 0) 5. when xxbe output mode/xxdqm output mode is set (pfcctm bit of pfcct register = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 m = 0 to 3 xx = uu, ul, lu, ll 3. bnk.: bank address col.: column address row: row address chapter 5 memory access control function 228 user?s manual u16031ej3v0ud figure 5-11. sdram access timing (9/9) (h) when written (during on-page continuous access) notes 1. state (t0) insert ed between bus cycles 2. this is the signal when the 32-bit external bus is used. read it as a11 when the 16-bit bus is used, and a10 when the 8-bit bus is used. 3. addresses other than the bank address, a12, and a2 to a11. 4. uudqm, uldqm, ludqm, lldqm remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 3. col.: column address wr wr twr twr twr twr h t0 note 1 busclk (output) a2 to a11 (output) csn (output) sdras (output) note 4 (output) bcyst (output) we (output) d0 to d31 (i/o) sdcas (output) a12 note 2 (output) bank address (output) note 3 (output) address col. col. data t0 note 1 t0 note 1 t0 note 1 col. col. address address address address address address address address address address address address address address address address address address address address address address address wr wr data data data command chapter 5 memory access control function 229 user?s manual u16031ej3v0ud 5.3.6 refresh control function the v850e/me2 can generate a refresh cycle. the refresh cycle is set with sdram refresh control registers 1, 3, 4, and 6 (rfs1, rfs3, rfs4, rfs6). rfsn corresponds to cs n (n = 1, 3, 4, 6). for example, to connect sdram to cs1, set rfs1. when another bus master occupies the external bus, the dram controller cannot occupy the external bus. in this case, the dram controller issues a refresh request to the bus master by changing the refrq signal to active (low level). during a refresh operation, the address bus retains t he state it was in just before the refresh cycle. (1) sdram refresh control registers 1, 3, 4, 6 (rfs1, rfs3, rfs4, rfs6) these registers are used to enable or disable a refresh and set the refresh interval. the refresh interval is determined by the following calculation formula. refresh interval ( s) = refresh count clock (t rcy ) interval factor the refresh count clock and interval factor are de termined by the rccn1 and rccn0 bits and rin5n to rin0n bits, respectively, of the rfsn register. note that n corresponds to the register number (1, 3, 4, 6) of sdram configuration registers 1, 3, 4, 6 (scr1, scr3, scr4, scr6). these registers can be read or written in 16-bit units. caution write to the rfs1, rfs3, rfs4, and rfs6 registers after reset, and then do not change the set values. however, when the sdram refresh interval needs to be changed by changing the ckc register set value (internal system clock (f clk )), the set value of the rfs1, rfs3, rfs4, and rfs6 registers can be changed. for deta ils, refer to caution 2 in 8.3.1 clock control register (ckc). also, do not access an ex ternal memory area other than the one for this initialization routine until the initial settings of the rfs1, rfs3, rfs4, and rfs6 registers are complete. however, it is po ssible to access external memory areas whose initialization settings are complete. chapter 5 memory access control function 230 user?s manual u16031ej3v0ud 14 0 13 0 12 0 2 rin12 3 rin13 4 rin14 5 rin15 6 0 7 0 8 rcc10 9 rcc11 10 0 11 0 15 ren1 1 rin11 0 rin10 000 rin32 rin33 rin34 rin35 0 0 rcc30 rcc31 0 0 ren3 rin31 rin30 000 rin42 rin43 rin44 rin45 0 0 rcc40 rcc41 0 0 ren4 rin41 rin40 000 rin62 rin63 rin64 rin65 0 0 rcc60 rcc61 0 0 ren6 rin61 rin60 rfs1 rfs3 rfs4 rfs6 address fffff4a6h fffff4aeh fffff4b2h fffff4bah after reset 0000h 0000h 0000h 0000h bit position bit name function 15 renn specifies whether cbr refresh is enabled or disabled. 0: refresh disabled 1: refresh enabled specifies the refresh count clock (t rcy ). rccn1 rccn0 refresh count clock (t rcy ) 0 0 32/busclk 0 1 128/busclk 1 0 256/busclk 1 1 setting prohibited 9, 8 rccn1, rccn0 sets the interval factor of the interval ti mer for the generation of the refresh timing. rinn5 rinn4 rinn3 rinn2 rinn1 rinn0 interval factor 0 0 0 0 0 0 1 0 0 0 0 0 1 2 0 0 0 0 1 0 3 0 0 0 0 1 1 4 : : : : : : : 1 1 1 1 1 1 64 5 to 0 rinn5 to rinn0 remark n = 1, 3, 4, 6 chapter 5 memory access control function 231 user?s manual u16031ej3v0ud table 5-1. example of interval factor settings interval factor value notes 1, 2 specified refresh interval value ( s) refresh count clock (t rcy ) busclk = 66 mhz busclk = 50 mhz 32/busclk 32 (15.5) 24 (15.4) 128/busclk 8 (15.5) 6 (15.4) 15.6 256/busclk 4 (15.5) 3 (15.4) notes 1. the interval factor is set by bits rinn0 to rinn5 of the rfsn register (n = 1, 3, 4, 6). 2. the values in parentheses are the calc ulated values for the refresh interval ( s). refresh interval ( s) = refresh count clock (t rcy ) interval factor the v850e/me2 can automatica lly generate an auto-refresh cycle and a self-refresh cycle. chapter 5 memory access control function 232 user?s manual u16031ej3v0ud (2) auto-refresh cycle in the auto-refresh cycle, the auto-refresh command (r ef) is issued four clocks after the precharge command for all banks (pall) is issued. figure 5-12. auto-refresh cycle notes 1. this is the signal when the 32-bit external bus is used. read it as a11 when the 16-bit bus is used, and a10 when the 8-bit bus is used. 2. addresses other than the bank address, a12, and a2 to a11. 3 uudqm, uldqm, ludqm, lldqm remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 tabpw trefw trefw trefw tref sdcke (output) h h busclk (output) a2 to a11 (output) csn (output) sdras (output) note 3 (output) bcyst (output) we (output) sdcas (output) a12 note 1 (output) bank address (output) note 2 (output) h pall ref d0 to d31 (i/o) address address address auto-refresh cycle command chapter 5 memory access control function 233 user?s manual u16031ej3v0ud (3) refresh timing figure 5-13. cbr refresh timing (sdram) notes 1. state (t0) insert ed between bus cycles 2. this is the signal when the 32-bit external bus is used. read it as a11 when the 16-bit bus is used, and a10 when the 8-bit bus is used. 3. addresses other than the bank address, a12, and a2 to a11. 4. uudqm, uldqm, ludqm, lldqm remarks 1. the number of wait states set by the bc wn1 and bcwn0 bits of the scrn register chapter 5 memory access control function 234 user?s manual u16031ej3v0ud 5.3.7 self-refresh control function in the case of transition to the idle or software stop mode, or if the selfref signal becomes active, the dram controller generates t he self-refresh cycle. cautions 1. when the transition to the self-refresh cycle is cause d by selfref signa l input, releasing the self-refresh cycle is only possible by inputti ng an inactive level to the selfref pin. 2. the internal instruction ram (only in th e read mode) and internal data ram can be accessed even in the self-refresh cycle. however, access to an on-chip peripheral i/o register or external device is held pend ing until the self-refresh cycle is cleared. to release the self-refresh cycle, us e one of the three methods below. (1) release by nmi input (a) in the case of self-refresh cycle in idle mode to release the self-refresh cycle, make the sdr as and sdcas signals inactive immediately. (b) in the case of self-refresh cycle in software stop mode to release the self-refresh cycle, make the sdras and sdcas signals inactive after stabilizing oscillation. (2) release by intp0n0 and intp0n1 inputs (n = 0 to 3) (a) in the case of self-refresh cycle in idle mode to release the self-refresh cycle, make the sdr as and sdcas signals inactive immediately. (b) in the case of self-refresh cycle in software stop mode to release the self-refresh cycle, make the sdras and sdcas signals inactive after stabilizing oscillation. (3) release by reset input chapter 5 memory access control function 235 user?s manual u16031ej3v0ud figure 5-14. self-refresh timing (sdram) notes 1. shown above is the case when the self-refresh cycle is started in the idle or software stop mode. if the self-refresh cycle is started by i nputting the active level of the selfref signal, busclk does not stop (sdcke goes low). 2. state (t0) insert ed between bus cycles 3. this is the signal when the 32-bit external bus is used. read it as a11 when the 16-bit bus is used, and a10 when the 8-bit bus is used. 4. addresses other than the bank address, a12, and a2 to a11. 5. uudqm, uldqm, ludqm, lldqm remarks 1. the number of wait states set by the bc wn1 and bcwn0 bits of the scrn register chapter 5 memory access control function 236 user?s manual u16031ej3v0ud 5.3.8 sdram initialization sequence be sure to initialize sdram when applying power. (1) set the registers of sdram (other t han sdram configuration register n (scrn)). ? bus cycle type configuration r egisters 0 and 1 (bct0 and bct1) ? bus cycle control register (bcc) ? sdram refresh control registers 1, 3, 4, 6 (rfs1, rfs3, rfs4, rfs6) (2) set sdram configuration register s 1, 3, 4, 6 (scr1, scr3, scr4, scr6). when writing data to these registers, the following commands are issu ed for sdram in the order shown below. ? all-bank precharge command ? refresh command (8 times) ? command that is used to set a mode register cautions 1. to set the scr1, scr3, scr4, and scr6 registers, confirm that the lock bit of the lock register (lockr) is set to 1, set the ckssel bit of the clock source select register (cks) to 1, and change clock supply to the cpu to sscg output (see 3.4.10 initialization sequence). 2. if it is necessary to make the input levels of the uudqm, uldqm, ludqm, and lldqm pins high until initia lization of sdram is completed, do not change the set values of the pfcct3 to pfcct0 bits of the pfcct register and do not write the external device until initialization of sdram is completed. figures 5-15 and 5-16 show examples of the sdram mode register setting timing. chapter 5 memory access control function 237 user?s manual u16031ej3v0ud figure 5-15. sdram mode register setting cycle notes 1. this is the signal when the 32-bit external bus is used. read it as a11 when the 16-bit bus is used, and a10 when the 8-bit bus is used. 2. addresses other than the bank address, a12, and a2 to a11. 3. uudqm, uldqm, ludqm, lldqm remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 h tabpw trefw trefw trefw tref trefw tregw refresh command (ref) generated 8 times sdcke (output) busclk (output) a2 to a11 (output) csn (output) sdras (output) note 3 (output) bcyst (output) we (output) sdcas (output) a12 note 1 (output) bank address (output) note 2 (output) h h valid d0 to d31 (i/o) pall ref regwr mode register setting cycle command chapter 5 memory access control function 238 user?s manual u16031ej3v0ud figure 5-16. sdram register write operation timing notes 1. this is the signal when the 32-bit external bus is used. read it as a11 when the 16-bit bus is used, and a10 when the 8-bit bus is used. 2. addresses other than the bank address, a12, and a2 to a11. 3. uudqm, uldqm, ludqm, lldqm remark n = 1, 3, 4, 6 tw0 tw0 tw0 h tw0 tw0 tabpw trefw trefw trefw tref trefw trefw trefw trefw tref trefw trefw trefw tregw trpw trpw trpw trpw trpw refresh end (1st time) refresh command (2nd time) refresh 239 user?s manual u16031ej3v0ud chapter 6 dma functions (dma controller) the v850e/me2 includes a direct memory access (dma) controller (dmac) that ex ecutes and controls dma transfer. the dmac controls data transfer between memory and i/ o, or among memories, based on requests by interrupts from on-chip peripheral i/o (serial in terface, real-time pulse unit, and a/d c onverter) or dma requests issued by the dmarq0 to dmarq3 pins, software triggers, or usb. memory refers to the internal instruction ram, internal data ram, or external memory. however, the internal instruction ram can be used only as the transfer destination. 6.1 features 4 independent dma channels transfer unit: 8/16/32 bits maximum transfer count: 65,536 (2 16 ) two types of transfer flyby (1-cycle) transfer 2-cycle transfer three transfer modes single transfer mode single-step transfer mode block transfer mode transfer requests request by interrupts from on-chip peripheral i/o (s erial interface, real-time pulse unit, a/d converter) requests via dmarq0 to dmarq3 pin input requests by software trigger requests by usb (only in the single transfer mode) transfer targets memory ? i/o memory ? memory dma transfer end output signals (tc0 to tc3) next address setting function chapter 6 dma functions (dma controller) 240 user?s manual u16031ej3v0ud 6.2 configuration tcn cpu internal data ram on-chip peripheral io on-chip peripheral i/o bus internal bus data control address control count control channel control dmac v850e/me2 bus interface external bus external ram external rom external i/o dma source address register (dsanh/dsanl) dma transfer count register (dbcn) dma channel control register (dchcn) dma terminal count output control register (dtoc) dma destination address register (ddanh/ddanl) dmarqn dmaakn dma addressing control register (dadcn) dma interface control register (difc) dma trigger factor register (dtfrn) internal instruction ram remark n = 0 to 3 chapter 6 dma functions (dma controller) 241 user?s manual u16031ej3v0ud 6.3 control registers 6.3.1 dma source address registers 0 to 3 (dsa0 to dsa3) these registers are used to set the dma transfer source addr ess (28 bits) for dma channel n (n = 0 to 3). they are divided into two 16-bit registers, dsanh and dsanl. since these registers are configured as 2-stage fifo buffer registers, a ne w transfer source address for dma transfer can be specified during dma transfer (see 6.8 next address setting function ). in this case, the newly set value of the dsan register is transfe rred to the slave register and becomes valid only when dma transfer has been completed normally and the tcn bit of the dchcn register is se t to 1, or when the initn bit of the dchcn register is set to 1 (n = 0 to 3). however, the set value of the dsan register is invalid ev en when the enn bit of the dchcn register is cleared to 0 to disable dma transfer and then the dsan register is set. when flyby transfer is specified with t he ttypn bit of dma addressing control register n (dadcn), the external memory addresses are set by the dsan register, regardless of the transfer direction. at this time, the setting of dma destination address register n (ddan) is ignored (n = 0 to 3). (1) dma source address registers 0h to 3h (dsa0h to dsa3h) these registers can be read or written in 16-bit units. be sure to clear bits 14 to 12 to 0. if they are set to 1, the oper ation is not guaranteed. cautions 1. when setting an addres s of a peripheral i/o register for the source address, be sure to specify an address between ffff000h and ff fffffh. an address of the peripheral i/o register image (3fff000h to 3 ffffffh) must not be specified. 2. do not set the dsanh register while dma transfer is suspended. dsa0h dsa1h dsa2h dsa3h 15 irs0 irs1 irs2 irs3 14 0 0 0 0 13 0 0 0 0 12 0 0 0 0 11 sa027 sa127 sa227 sa327 10 sa026 sa126 sa226 sa326 9 sa025 sa125 sa225 sa325 8 sa024 sa124 sa224 sa324 7 sa023 sa123 sa223 sa323 6 sa022 sa122 sa222 sa322 5 sa021 sa121 sa221 sa321 4 sa020 sa120 sa220 sa320 3 sa019 sa119 sa219 sa319 2 sa018 sa118 sa218 sa318 1 sa017 sa117 sa217 sa317 0 sa016 sa116 sa216 sa316 address fffff082h fffff08ah fffff092h fffff09ah after reset undefined undefined undefined undefined bit position bit name function 15 irsn specifies the dma transfer source address. 0: external memory, on-chip peripheral i/o 1: internal data ram 11 to 0 san27 to san16 sets the dma transfer source address (a27 to a16). during dma transfer, it stores the next dma transfer source address. during flyby transfer, it stores an external memory address. remark n = 0 to 3 chapter 6 dma functions (dma controller) 242 user?s manual u16031ej3v0ud (2) dma source address registers 0l to 3l (dsa0l to dsa3l) these registers can be read or written in 16-bit units. dsa0l dsa1l dsa2l dsa3l 15 sa015 sa115 sa215 sa315 14 sa014 sa114 sa214 sa314 13 sa013 sa113 sa213 sa313 12 sa012 sa112 sa212 sa312 11 sa011 sa111 sa211 sa311 10 sa010 sa110 sa210 sa310 9 sa09 sa19 sa29 sa39 8 sa08 sa18 sa28 sa38 7 sa07 sa17 sa27 sa37 6 sa06 sa16 sa26 sa36 5 sa05 sa15 sa25 sa35 4 sa04 sa14 sa24 sa34 3 sa03 sa13 sa23 sa33 2 sa02 sa12 sa22 sa32 1 sa01 sa11 sa21 sa31 0 sa00 sa10 sa20 sa30 address fffff080h fffff088h fffff090h fffff098h after reset undefined undefined undefined undefined bit position bit name function 15 to 0 san15 to san0 sets the dma transfer source address (a15 to a0). during dma transfer, it stores the next dma transfer source address. during flyby transfer, it stores an external memory address. remark n = 0 to 3 chapter 6 dma functions (dma controller) 243 user?s manual u16031ej3v0ud 6.3.2 dma destination address regi sters 0 to 3 (dda0 to dda3) these registers are used to set the dma transfer destination address (28 bits) for dma channel n (n = 0 to 3). they are divided into two 16-bit registers, ddanh and ddanl. since these registers are configured as 2-stage fifo buffe r registers, a new transfer destination address for dma transfer can be specified during dma transfer (see 6.8 next address setting function ). in this case, the newly set value of the ddan register is transferred to the slave register and becomes valid only when dma transfer has been completed normally and the tcn bit of the dchcn register is se t to 1, or when the initn bit of the dchcn register is set to 1 (n = 0 to 3). however, the set value of the ddan register is invalid even when the enn bit of the dchcn register is cleared to 0 to disable dma transfer and then the ddan register is set. when flyby transfer is specified with the ttypn bit of dm a addressing control register n (dadcn), the setting of dma destination address register n (ddan) is i gnored, regardless of the transfer direction. (1) dma destination address register s 0h to 3h (dda0h to dda3h) these registers can be read or written in 16-bit units. be sure to clear bits 14 to 12 to 0. if they are set to 1, the oper ation is not guaranteed. cautions 1. when setting an address of a peripheral i/o register for the destination address, be sure to specify an address betw een ffff000h and fffffffh. an address of the peripheral i/o register image (3fff000h to 3 ffffffh) must not be specified. 2. do not set the ddanh register wh ile dma transfer is suspended. 3. when enabling the specula tive read function is selected for the cs space at the dma transfer destination, set th e dma transfer destination a ddress so that the address on which a speculative read is performed and the line address to which the last dma transfer data is written are not the same line address (the same line address means that a25 to a4 are the same in the same cs space). dda0h dda1h dda2h dda3h 15 ird0 ird1 ird2 ird3 14 0 0 0 0 13 0 0 0 0 12 0 0 0 0 11 da027 da127 da227 da327 10 da026 da126 da226 da326 9 da025 da125 da225 da325 8 da024 da124 da224 da324 7 da023 da123 da223 da323 6 da022 da122 da222 da322 5 da021 da121 da221 da321 4 da020 da120 da220 da320 3 da019 da119 da219 da319 2 da018 da118 da218 da318 1 da017 da117 da217 da317 0 da016 da116 da216 da316 address fffff086h fffff08eh fffff096h fffff09eh after reset undefined undefined undefined undefined bit position bit name function 15 irdn specifies the dma transfer destination address. 0: external memory, on-chip peripheral i/o, internal instruction ram 1: internal data ram 11 to 0 dan27 to dan16 sets the dma transfer destination address (a27 to a16). during dma transfer, it stores the next dma transfer destination address. this setting is ignored during flyby transfer. remark n = 0 to 3 chapter 6 dma functions (dma controller) 244 user?s manual u16031ej3v0ud (2) dma destination address regist ers 0l to 3l (dda0l to dda3l) these registers can be read or written in 16-bit units. dda0l dda1l dda2l dda3l 15 da015 da115 da215 da315 14 da014 da114 da214 da314 13 da013 da113 da213 da313 12 da012 da112 da212 da312 11 da011 da111 da211 da311 10 da010 da110 da210 da310 9 da09 da19 da29 da39 8 da08 da18 da28 da38 7 da07 da17 da27 da37 6 da06 da16 da26 da36 5 da05 da15 da25 da35 4 da04 da14 da24 da34 3 da03 da13 da23 da33 2 da02 da12 da22 da32 1 da01 da11 da21 da31 0 da00 da10 da20 da30 address fffff084h fffff08ch fffff094h fffff09ch after reset undefined undefined undefined undefined bit position bit name function 15 to 0 dan15 to dan0 sets the dma transfer destination address (a15 to a0). during dma transfer, it stores the next dma transfer destination address. this setting is ignored during flyby transfer. remark n = 0 to 3 chapter 6 dma functions (dma controller) 245 user?s manual u16031ej3v0ud 6.3.3 dma transfer count regi sters 0 to 3 (dbc0 to dbc3) these 16-bit registers are used to set the byte transfer c ount for dma channel n (n = 0 to 3). they store the remaining transfer count during dma transfer. since these registers are configured as 2-stage fifo buffer registers, a new dma byte transfer count for dma transfer can be specified during dma transfer (see 6.8 next address setting function ). in this case, the newly set value of the dbcn register is transferred to the slave register and becomes valid only when dma transfer has been completed normally and the tcn bit of the dchcn register is se t to 1, or when the initn bit of the dchcn register is set to 1 (n = 0 to 3). however, the set value of the dbcn register is invalid even when the enn bit of the dchcn register is cleared to 0 to disable dma transfer and then the dbcn register is set. these registers are decremented by 1 for each tr ansfer, and transfer ends when a borrow occurs. these registers can be read or written in 16-bit units. cautions 1. if the dbcn register is read durin g dma transfer after a terminal count has occurred without the register being overwritten, the value set immediately before the dma transfer will be read out (0000h will not be read, even if dma transfer has ended). 2. do not set the dbcn register while dma transfer is suspended. dbc0 dbc1 dbc2 dbc3 15 bc015 bc115 bc215 bc315 14 bc014 bc114 bc214 bc314 13 bc013 bc113 bc213 bc313 12 bc012 bc112 bc212 bc312 11 bc011 bc111 bc211 bc311 10 bc010 bc110 bc210 bc310 9 bc09 bc19 bc29 bc39 8 bc08 bc18 bc28 bc38 7 bc07 bc17 bc27 bc37 6 bc06 bc16 bc26 bc36 5 bc05 bc15 bc25 bc35 4 bc04 bc14 bc24 bc34 3 bc03 bc13 bc23 bc33 2 bc02 bc12 bc22 bc32 1 bc01 bc11 bc21 bc31 0 bc00 bc10 bc20 bc30 address fffff0c0h fffff0c2h fffff0c4h fffff0c6h after reset undefined undefined undefined undefined bit position bit name function sets the byte transfer count and stores the remaining byte transfer count during dma transfer. dbcn states 0000h byte transfer count 1 or remaining byte transfer count 0001h byte transfer count 2 or remaining byte transfer count : : ffffh byte transfer count 65,536 (2 16 ) or remaining byte transfer count 15 to 0 bcn15 to bcn0 remark n = 0 to 3 chapter 6 dma functions (dma controller) 246 user?s manual u16031ej3v0ud 6.3.4 dma addressing control registers 0 to 3 (dadc0 to dadc3) these 16-bit registers are used to co ntrol the dma transfer mode for dma channel n (n = 0 to 3). these registers cannot be accessed during dma operation. these registers can be read or written in 16-bit units. be sure to clear bits 13 to 8 to 0. if they are set to 1, the operat ion is not guaranteed. cautions 1. the dsn1 and dsn0 bits set how many bits of data ar e to be transferred. when 8-bit data is set (dsn1 and dsn0 bits = 00), the lower bytes of the data bus (d0 to d7) are not always used. if the transfer data size is set to 16 bits , transfer is always started from an address with the lowest bit of the address aligne d to ?0?. if the data size is set to 32 bits, transfer is started from an address with the lowest 2 bits of the address aligne d to ?0?. in this case, transfer cannot be st arted from an odd address. 2. set the dadcn register at the following timing while the target dma channel is in operation or is not suspended (the operation is not guaranteed if the register is set at any other timing). ? ? ? ? ? ? ? chapter 6 dma functions (dma controller) 247 user?s manual u16031ej3v0ud (1/2) dadc0 dadc1 dadc2 dadc3 15 ds01 ds11 ds21 ds31 14 ds00 ds10 ds20 ds30 13 0 0 0 0 12 0 0 0 0 11 0 0 0 0 10 0 0 0 0 9 0 0 0 0 8 0 0 0 0 7 sad01 sad11 sad21 sad31 6 sad00 sad10 sad20 sad30 5 dad01 dad11 dad21 dad31 4 dad00 dad10 dad20 dad30 3 tm01 tm11 tm21 tm31 2 tm00 tm10 tm20 tm30 1 ttyp0 ttyp1 ttyp2 ttyp3 0 tdir0 tdir1 tdir2 tdir3 address fffff0d0h fffff0d2h fffff0d4h fffff0d6h after reset 0000h 0000h 0000h 0000h bit position bit name function sets the transfer data size for dma transfer. dsn1 dsn0 transfer data size 0 0 8 bits 0 1 16 bits 1 0 32 bits 1 1 setting prohibited 15, 14 dsn1, dsn0 sets the count direction of the source address for dma channel n. sadn1 sadn0 count direction 0 0 increment 0 1 decrement 1 0 fixed 1 1 setting prohibited 7, 6 sadn1, sadn0 remark n = 0 to 3 chapter 6 dma functions (dma controller) 248 user?s manual u16031ej3v0ud (2/2) bit position bit name function sets the count direction of the de stination address for dma channel n. dadn1 dadn0 count direction 0 0 increment 0 1 decrement 1 0 fixed 1 1 setting prohibited 5, 4 dadn1, dadn0 sets the transfer mode during dma transfer. tmn1 tmn0 transfer mode 0 0 single transfer mode 0 1 single-step transfer mode 1 0 setting prohibited 1 1 block transfer mode 3, 2 tmn1, tmn0 1 ttypn sets the dma transfer type. 0: 2-cycle transfer 1: flyby transfer 0 tdirn sets the transfer direction during transfer between i/o and memory. the setting is valid during flyby transfer only and ignored during 2-cycle transfer. 0: memory i/o (read) 1: i/o memory (write) remark n = 0 to 3 chapter 6 dma functions (dma controller) 249 user?s manual u16031ej3v0ud 6.3.5 dma channel control regist ers 0 to 3 (dchc0 to dchc3) these 8-bit registers are used to c ontrol the dma transfer operating mode for dma channel n (n = 0 to 3). these registers can be read or written in 8-bit or 1-bit un its. (however, bit 7 is read only and bits 2 and 1 are write only. if bits 2 and 1 are read, the read value is always 0.) be sure to clear bits 6 to 4 to 0. if they are set to 1, the operation is not guaranteed. cautions 1. during a 2-cycle transf er that performs a write operation on the external device, the write operation on the external device may not be completed even if the tcn bit of the dchcn register is set to 1 (dma tr ansfer completion) by the writ e buffer function. recognize completion of the write operation on th e external device as fo llows, if necessary. ? ? ? ? ? chapter 6 dma functions (dma controller) 250 user?s manual u16031ej3v0ud cautions 7. the tcn bit does not have to be read (cleared to 0) on completion of dma transfer (on generation of the terminal count) only if the followin g two conditions are satisfied. if either of the conditions is not satisfied, be sure to re ad the tcn bit (cleared to 0) before the next dma transfer request is generated. ? if the mlen bit is set to 1 upon comple tion of dma transfer (at terminal count) ? if the source that starts the next dm a transfer is an external pin (dmarqn) if these two conditions are not satisfied, th e operation is not guaranteed if the next dma transfer request is generate d with the tcn bit set to 1. chapter 6 dma functions (dma controller) 251 user?s manual u16031ej3v0ud tc0 tc1 tc2 tc3 dchc0 dchc1 dchc2 dchc3 6 0 0 0 0 5 0 0 0 0 4 0 0 0 0 mle0 mle1 mle2 mle3 init0 init1 init2 init3 stg0 stg1 stg2 stg3 e00 e11 e22 e33 address fffff0e0h fffff0e2h fffff0e4h fffff0e6h after reset 00h 00h 00h 00h <7> <1> <2> <3> <0> bit position bit name function 7 tcn this status bit indicates whether dma transfer through dma channel n is complete or not. this bit is read-only. it is set to 1 during t he last dma transfer and cleared to 0 when it is read. 0: dma transfer is not complete. 1: dma transfer is complete. caution to read the tcn bit on completion of a dma transfer that transfers data to/from the internal data ram, first read the status in which the tcn bit was set to 1, and then insert two dummy reads of the dchcn register in a row. 3 mlen if this bit is set to 1 when dma transfer is complete (at terminal count output), the enn bit is not cleared to 0 and the dma transfer enable state is retained. if the next dma transfer startup factor is input from the dmarqn pin or is an interrupt from the on-chip peripheral i/o (hardwar e dma), the dma transfer request is acknowledged even if the tcn bit is not read. if the next dma transfer startup factor is input by setting the stgn bit to 1 (software dma), the dma transfer request is acknowledged if the tcn bit is read and cleared to 0. if this bit is cleared to 0 when dma transfer is complete (at terminal count output), the enn bit is cleared to 0 and the dma transfer disable state is entered. at the next dma request, the enn bit must be set to 1 and the tcn bit read. 2 initn if this bit is set to 1 during dma tr ansfer or while dma transfer is suspended, dma transfer is forcibly terminated. 1 stgn if this bit is set to 1 in the dma transfer enable state (tcn bit = 0, enn bit = 1), dma transfer is started. 0 enn specifies whether dma transfer through dma channel n is to be enabled or disabled. this bit is cleared to 0 when dma transfe r ends. it is also cleared to 0 when dma transfer is forcibly interrupted or forcibly terminated by setting the initn bit to 1 or by nmi input. 0: dma transfer disabled 1: dma transfer enabled caution if the enn bit is set to 1, forcibly terminate dma transfer using the initn bit after the number of dma transfers set by the dbcn register is complete or the enn bit is cleared to 0 (if the enn bit is cleared to 0 during dma transfer, do not re-set the enn bit to 1). remark n = 0 to 3 chapter 6 dma functions (dma controller) 252 user?s manual u16031ej3v0ud 6.3.6 dma terminal count output control register (dtoc) the dma terminal count output control register (dtoc) is an 8-bit register that contro ls the terminal count output from each dma channel and dma transfer during nmi input. terminal count signals from each dma channel can be brought together and output from the tc0 pin. this register can be read or written in 8-bit or 1-bit units. dtoc 7 dmstpm 6 dakebc 5 0 4 0 <3> tco3 <2> tco2 <1> tco1 <0> tco0 address fffff8a0h after reset 01h bit position bit name function 7 dmstpm controls dma transfer when nmi is input. 0: forcibly aborts dma transfer when nmi is input. 1: does not abort dma transfer when nmi is input. cautions 1. when dmstpm bit = 0, nmi servicing can be executed immediately after completion of the dma cycle currently under execution. before executing the aborted dma transfer, however, be sure to re-initialize it. 2. when dmstpm bit = 1, nmi servicing is held pending in the block transfer mode until dma transfer has been completed the preset number of times. in the single transfer mode and single-step transfer mode, nmi servicing is executed after the dma cycle currently under execution is completed. as necessary, forcibly terminate dma transfer by setting the initn bit of the dchcn register to 1 (n = 0 to 3). 3. be sure to change the value of the dmstpm bit when dma is not used. the operation is not guaranteed if the value of the dmstpm bit is changed after registers related to dmac have been set or during dma transfer. 6 dakebc specifies extension of the active width of the dmaakn signal while the daken bit of the difc register = 1. 0: active width extended by four internal system clocks. 1: active width extended by six to seven internal system clocks. remark for details of the function to extend the active width of the dmaakn signal, refer to 6.3.8 dma interface control register (difc) or 6.5.1 (2) dmaakn signal active width extension function . 3 to 0 tco3 to tco0 indicates the state of the tc0 pin. 0: channel n terminal count signal not output from tc0 pin. 1: channel n terminal count signal output from tc0 pin. chapter 6 dma functions (dma controller) 253 user?s manual u16031ej3v0ud the following shows an example of the case when the dtoc register is set to 03h. tc0 (output) tc2 (output) dma0 cpu dma0 dma1 dma1 cpu dma2 dma2 dma channel 2 terminal count dma channel 1 terminal count dma channel 0 terminal count 6.3.7 dma trigger factor registers 0 to 3 (dtfr0 to dtfr3) these 8-bit registers are used to control the dma transfe r start trigger through interrupt requests from on-chip peripheral i/o. the interrupt requests set by these register s serve as dma transfer startup factors. these registers can be read or written in 8-bit or 1-bit unit s. however, only bit 7 (dfn) can be read or written in 1- bit units. cautions 1. to change the setti ng of the dtfrn register, be su re to stop the dma operation. 2. an interrupt request input in the standby mode (idle or software stop mode) cannot be a dma transfer start factor. 3. if the factor of starting dma transfer is cha nged by using the ifcn6 to ifcn0 bits, be sure to clear the dfn bit to 0 using the instruction immediately after. 4. when a transmission comple tion interrupt request signal (ubt it0 or ubtit1) of uartb is used as the factor of starting dma transfer, th e factor of starting dma transfer that is triggered by the interrupt request signal generated when the last transmission was completed is retained. in this case, clear the dfn bit to 0 to clear the dma transfer request. chapter 6 dma functions (dma controller) 254 user?s manual u16031ej3v0ud (1/3) df0 df1 df2 df3 dtfr0 dtfr1 dtfr2 dtfr3 6 ifc06 ifc16 ifc26 ifc36 5 ifc05 ifc15 ifc25 ifc35 4 ifc04 ifc14 ifc24 ifc34 3 ifc03 ifc13 ifc23 ifc33 2 ifc02 ifc12 ifc22 ifc32 1 ifc01 ifc11 ifc21 ifc31 0 ifc00 ifc10 ifc20 ifc30 address fffff810h fffff812h fffff814h fffff816h after reset 00h 00h 00h 00h <7> bit position bit name function 7 dfn this is a dma transfer request flag. only 0 can be written to this flag. 0: dma transfer not requested 1: dma transfer requested if the interrupt specified as the dma transfer st artup trigger occurs and it is necessary to clear the dma transfer request while dma tr ansfer is disabled (i ncluding when it is aborted by nmi or forcibly terminated by software), stop the operation of the source causing the interrupt, and then clear the dfn bit to 0 (for example, disable reception in the case of serial reception). if it is clear that the interrupt will not occur until dma transfer is resumed next, it is not necessary to stop the operation of the source causing the interrupt. this code is used to set the interrupt sources serving as dma transfer startup factors. ifcn6 ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 interrupt source 0 0 0 0 0 0 0 level detection mode of dmarqn pin input (dma request from on- chip peripheral i/o disabled) 0 0 0 0 0 0 1 edge detection mode of dmarqn pin input (dma request from on- chip peripheral i/o disabled) 0 0 0 0 0 1 0 intp10 0 0 0 0 0 1 1 intp11 0 0 0 0 1 0 0 intp21 0 0 0 0 1 0 1 intp22 0 0 0 0 1 1 0 intp23 0 0 0 0 1 1 1 intp24 0 0 0 1 0 0 0 intp25 6 to 0 ifcn6 to ifcn0 remark n = 0 to 3 chapter 6 dma functions (dma controller) 255 user?s manual u16031ej3v0ud (2/3) bit position bit name function ifcn6 ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 interrupt source 0 0 0 1 0 0 1 intp50 0 0 0 1 0 1 0 intp51 0 0 0 1 0 1 1 intp52 0 0 0 1 1 0 0 intp65 0 0 0 1 1 0 1 intp66 0 0 0 1 1 1 0 intp67 0 0 0 1 1 1 1 intpd0 0 0 1 0 0 0 0 intpd1 0 0 1 0 0 0 1 intpd2 0 0 1 0 0 1 0 intpd3 0 0 1 0 0 1 1 intpd4 0 0 1 0 1 0 0 intpd5 0 0 1 0 1 0 1 intpd6 0 0 1 0 1 1 0 intpd7 0 0 1 0 1 1 1 intpd8 0 0 1 1 0 0 0 intpd9 0 0 1 1 0 0 1 intpd10 0 0 1 1 0 1 0 intpd11 0 0 1 1 0 1 1 intpd12 0 0 1 1 1 0 0 intpd13 0 0 1 1 1 0 1 intpd14 0 0 1 1 1 1 0 intpd15 0 0 1 1 1 1 1 intpl0 0 1 0 0 0 0 0 intpl1 0 1 0 0 0 0 1 intpc00/intccc00 0 1 0 0 0 1 0 intpc01/intccc01 0 1 0 0 0 1 1 intpc10/intccc10 0 1 0 0 1 0 0 intpc11/intccc11 0 1 0 0 1 0 1 intpc20/intccc20 0 1 0 0 1 1 0 intpc21/intccc21 0 1 0 0 1 1 1 intpc30/intccc30 0 1 0 1 0 0 0 intpc31/intccc31 6 to 0 ifcn6 to ifcn0 remark n = 0 to 3 chapter 6 dma functions (dma controller) 256 user?s manual u16031ej3v0ud (3/3) bit position bit name function ifcn6 ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 interrupt source 0 1 0 1 0 0 1 intccc40 0 1 0 1 0 1 0 intccc41 0 1 0 1 0 1 1 intccc50 0 1 0 1 1 0 0 intccc51 0 1 0 1 1 0 1 intcmd0 0 1 0 1 1 1 0 intcmd1 0 1 0 1 1 1 1 intcmd2 0 1 1 0 0 0 0 intcmd3 0 1 1 0 0 0 1 intcc100 0 1 1 0 0 1 0 intcc101 0 1 1 0 0 1 1 intcm100 0 1 1 0 1 0 0 intcm101 0 1 1 0 1 0 1 intcc110 0 1 1 0 1 1 0 intcc111 0 1 1 0 1 1 1 intcm110 0 1 1 1 0 0 0 intcm111 0 1 1 1 0 0 1 intcsi30 0 1 1 1 0 1 0 intcsi31 0 1 1 1 0 1 1 ubtir0 0 1 1 1 1 0 0 ubtit0 0 1 1 1 1 0 1 ubtir1 0 1 1 1 1 1 0 ubtit1 0 1 1 1 1 1 1 intad 1 1 1 1 1 1 1 ufdrqn other than above setting prohibited 6 to 0 ifcn6 to ifcn0 caution when using an external interrupt (when ifcn6 to ifcn0 bits = 0000010b to 0100000b) as a dma trigger source, be sure to specify an edge (do not use level detection). remark n = 0 to 3 chapter 6 dma functions (dma controller) 257 user?s manual u16031ej3v0ud the relationship between the dmarqn signa l and the interrupt source that serv es as a dma transfer trigger is as follows (n = 0 to 3). ifcn0 to ifcn6 internal dma request signal interrupt source dmarqn selector remark if an interrupt request is specified as the dma transfer start factor, an interrupt request will be generated if dma transfer starts. to prevent an inte rrupt from being generated, mask the interrupt by setting the interrupt request control register. dm a transfer starts even if an interrupt is masked. for the level detection mode (ifcn6 to ifcn0 bits = 0 000000) and edge detection mode (ifcn6 to ifcn0 bits = 0000001) of the dmarqn pin input, see figures 6-8 to 6-10 (n = 0 to 3). (1) dma request detection function the v850e/me2 has a level detection mode and an edge detection mode as functions to sample the dmarqn pin (n = 0 to 3). the level detection mode also has a mask mode in which sampling the dma request is masked. (a) level detection mode (ifc n6 to ifcn0 bits = 0000000) in this mode, handshaking of the dmarqn and dmaakn signals can be executed at high speeds. in the single transfer mode, deassert the dmarqn signal fo r the duration of twice t he internal system clock from the rising edge of the dmaakn signal, in order not to star t the dma transfer cycle next to that currently under execution. if the dmarqn signal is active for the dur ation of twice the internal system clock, the next dma request is recognized. in the 2-cycle transfer mode, however, the active period of the dmaakn signal may be shortened depending on the combination of the transfer source and transfer destination (min.: 2 internal system clock). consequently, if the inactive timing of the dmarqn signal is generated from the fall ing edge of the dmaakn sig nal, for example, the timing may be four times the internal system clock at the shortest. for the active width of the dmaakn si gnal for 2-cycle transfer, refer to table 6-4 minimum value of active width of dmaakn signal for 2-cycle transfer . <1> mask mode (ifcn6 to ifcn0 bits = 0000000 and drmkn bit of difc register = 1) this mode is used to establish handshaking of the dmarqn and dmaakn signals in synchronization with busclk in the level detectio n mode. in the single transfer mode, deassert the dmarqn signal within 3 busclk after sampling the rising edg e of the dmaakn signal, in order not to start the dma transfer cycle next to that cu rrently under execution. when the mask mode is set, sampling the dma request is always masked for the duration of 3 busclk period from the rising edge of the dmarqn signal, regardless of the division ratio of busclk (set by the bmc register). chapter 6 dma functions (dma controller) 258 user?s manual u16031ej3v0ud (b) edge detection mode (ifcn6 to ifcn0 bits = 0000001) this mode uses the falling edge of the dmarqn signal as a dma request. it rea lizes handshaking of the dmarqn and dmaakn signals at a speed much lowe r than that when the mask mode is used. however, note that the falling edge of the dmarqn signal is ignored, even if input, while the dmaakn signal is active. for the detailed timing in each mode, refer to chapter 17 electrical specifications . chapter 6 dma functions (dma controller) 259 user?s manual u16031ej3v0ud 6.3.8 dma interface control register (difc) this 8-bit register controls the active width of the dmaakn signal of each dma channel and controls the mask function (dma mask mode) of the dmarqn signal (n = 0 to 3). this register can be read or written in 8-bit or 1-bit units. dake3 6 dake2 5 dake1 4 dake0 3 drmk3 2 drmk2 1 drmk1 0 drmk0 address fffff8a8h after reset 00h 7 difc bit position bit name function 7 to 4 daken these bits specify the active width of the dmaakn signal. 0: active width of dmaakn signal output from dmac 1: active width of dmaakn signal + active extension width note output from dmac note the active width is extended by the daken bit as follows. ? ? ? ? chapter 6 dma functions (dma controller) 260 user?s manual u16031ej3v0ud 6.4 transfer modes 6.4.1 single transfer mode in single transfer mode, the dmac releas es the bus at each byte/halfword/word transfer. if there is a subsequent dma transfer request, transfer is performed again once. this operation continues until a terminal count occurs. when the dmac has released the bus, if another higher prio rity dma transfer request is issued, the higher priority dma request always takes precedence. if other dma transf er request with the lower priority occurs one clock after single transfer has been completed, however, this request does not take precedence even if the previous dma transfer request signal with the higher priority remains active. dma transfer with the lower priority newly request is executed after the cpu bus has been released. figures 6-1 to 6-4 show examples of single transfer. figure 6-1. single transfer example 1 cpu dmarq3 (input) cpu dma3 cpu dma3 cpu dma3 cpu cpu cpu cpu cpu cpu dma3 cpu dma3 cpu cpu cpu dma channel 3 terminal count note note note note note the bus is always released. figure 6-2 shows an example of a single transfer in which a higher priority dma request is issued. dma channels 0 to 2 are in the block transfer mode and channel 3 is in the single transfer mode. figure 6-2. single transfer example 2 cpu cpu cpu dma3 cpu dma0 dma0 cpu dma1 dma1 cpu dma2 dma2 cpu dma3 cpu dma3 dmarq3 (input) dmarq2 (input) dmarq1 (input) dmarq0 (input) dma channel 3 terminal count dma channel 0 terminal count dma channel 2 terminal count note note note note dma channel 1 terminal count note the bus is always released. chapter 6 dma functions (dma controller) 261 user?s manual u16031ej3v0ud figure 6-3 is an example of single transfer where a dma tr ansfer request with the lower priority is issued one clock after single transfer has been completed. dma channels 0 and 3 are used for single transfer. if two dma transfer request signals become active at the same time, tw o dma transfer operations are alternately executed. figure 6-3. single transfer example 3 cpu cpu cpu dma0 dma0 cpu dma0 cpu dma0 cpu dma0 cpu cpu cpu dma0 cpu dma3 cpu dma3 dma channel 3 terminal count dma channel 0 terminal count dmarq3 (input) dmarq0 (input) note note note note note note note note the bus is always released. figure 6-4 is an example of single transfer where two or more dma transfer requests with the lower priority are issued one clock after single transfer has been completed. dma channels 0, 2, and 3 are used for single transfer. if three or more dma transfer request signals become active at the same time, two dma transfer operations are alternately executed, always starting fr om the one with the highest priority. figure 6-4. single transfer example 4 cpu dma3 cpu dma3 cpu dma2 cpu dma2 cpu dma2 cpu dma2 cpu dma3 cpu cpu cpu dma3 cpu dma0 cpu dma0 dma channel 0 terminal count dma channel 2 terminal count dma channel 3 terminal count dmarq2 (input) dmarq3 (input) dmarq0 (input) note note note note note note note note note note the bus is always released. chapter 6 dma functions (dma controller) 262 user?s manual u16031ej3v0ud 6.4.2 single-step transfer mode in single-step transfer mode, the dmac releases the bus at each byte/halfword/word transfer. if there is a subsequent dma transfer request signal (dmarq0 to dm arq3), transfer is performed again. this operation continues until a terminal count occurs. when the dmac has released the bus, if another higher prio rity dma transfer request is issued, the higher priority dma request always takes precedence. the following shows an example of a single-step transfer. figure 6-6 shows an example of single-step transfer made in which a higher priority dma request is issued. dma channels 0 and 1 are in t he single-step transfer mode. figure 6-5. single-step transfer example 1 cpu cpu cpu dma1 cpu dma1 cpu dma1 cpu dma1 cpu cpu cpu cpu cpu cpu cpu dma channel 1 terminal count dmarq1 (input) note note note note the bus is always released. figure 6-6. single-step transfer example 2 cpu cpu cpu dma1 cpu dma1 cpu dma0 cpu dma0 cpu dma0 cpu dma1 cpu dma1 cpu dma channel 0 terminal count dma channel 1 terminal count dmarq1 (input) dmarq0 (input) note note note note note note note the bus is always released. chapter 6 dma functions (dma controller) 263 user?s manual u16031ej3v0ud 6.4.3 block transfer mode in the block transfer mode, once transfer starts, the dm ac continues the transfer oper ation without releasing the bus until a terminal count occurs. no other dma requests are acknowledged during block transfer. after the block transfer ends and the dmac releases t he bus, another dma transfer can be acknowledged. the bus cycle of the cpu is not inserted during block transfer, but bus hold and refresh cycles are inserted in between dma transfer operations. the following shows an example of block transfer in which a higher priority dma request is issued. dma channels 2 and 3 are in the block transfer mode. figure 6-7. block transfer example cpu cpu cpu dma3 dma3 dma3 dma3 dma3 dma3 dma3 dma3 cpu dma2 dma2 dma2 dma2 dma2 dma channel 3 terminal count the bus is always released. dmarq3 (input) dmarq2 (input) chapter 6 dma functions (dma controller) 264 user?s manual u16031ej3v0ud 6.5 transfer types 6.5.1 2-cycle transfer in 2-cycle transfer, data transfer is performed in two cycles, a read cycle (source to dmac) and a write cycle (dmac to destination). in the first cycle, the source address is output and readin g is performed from the source to the dmac. in the second cycle, the destination address is output and writi ng is performed from the dmac to the destination. cautions 1. an idle cycle of 1 to 2 clocks is always inserted betwee n a read cycle and a write cycle. 2. refer to appendix a notes for r estrictions on 2-cycle dma transfer. figure 6-8. timing of 2-cycle dma transfer (sram external i/o) (1/2) (a) single transfer mode (0 waits, bmc register = 00h, level detection mode) notes 1. this idle state (ti) is independ ent of the bcc register setting. 2. uube/uudqm, ulbe/uldqm, llbe/lldqm, lube/ludqm remarks 1. the broken lines indicate the high-impedance state. 2. n = 0 to 7, m = 0 to 7 (n m) x = 0 to 3 t2 ti note 1 ti t2 t1 h h h d0 to d31 (input) wr (output) csm (output) of sram area dmarqx (input) csn (output) of external i/o area dmaakx (output) note 2 (output) sdcke (output) busclk (output) rd (output) bcyst (output) sdras (output) sdcas (output) data data chapter 6 dma functions (dma controller) 265 user?s manual u16031ej3v0ud figure 6-8. timing of 2-cycle dma transfer (sram external i/o) (2/2) (b) single transfer mode (0 waits, bm c register = 00h, edge detection mode) notes 1. this idle state (ti) is independ ent of the bcc register setting. 2. uube/uudqm, ulbe/uldqm, llbe/lldqm, lube/ludqm remarks 1. the broken lines indicate the high-impedance state. 2. n = 0 to 7, m = 0 to 7 (n m) x = 0 to 3 t1 t2 ti note 1 t1 t2 h h h d0 to d31 (input) wr (output) csm (output) of sram area dmarqx (input) csn (output) of external i/o area dmaakx (output) note 2 (output) sdcke (output) busclk (output) rd (output) bcyst (output) sdras (output) sdcas (output) data data chapter 6 dma functions (dma controller) 266 user?s manual u16031ej3v0ud figure 6-9. timing of 2-cycle dma transfer (sdram sram): single transfer mode (sram data 1 wait, sdram latency = 2, bmc register = 00h, level detection mode) notes 1. this idle state (ti) is independ ent of the bcc register setting. 2. uube/uudqm, ulbe/uldqm, llbe/lldqm, lube/ludqm remarks 1. the broken lines indicate the high-impedance state. 2. m = 0 to 7 n = 1, 3, 4, 6 x = 0 to 3 tread tact tlate ti note 1 t1 tlate data h h data tw t2 csm (output) of sram area bcyst (output) dmaakx (output) dmarqx (input) busclk (output) csn (output) of external i/o area rd (output) wr (output) note 2 (output) sdcke (output) sdras (output) sdcas (output) d0 to d31 (input) chapter 6 dma functions (dma controller) 267 user?s manual u16031ej3v0ud figure 6-10. timing of 2-cycle dma transfer (sram sdram): single transfer mode (sram data 1 wait, bmc register = 00h, edge detection mode) notes 1. this idle state (ti) is independ ent of the bcc register setting. 2. uube/uudqm, ulbe/uldqm, llbe/lldqm, lube/ludqm remarks 1. the broken lines indicate the high-impedance state. 2. m = 0 to 7 n = 1, 3, 4, 6 x = 0 to 3 t1 tw t2 ti note 1 tact twr h d0 to d31 (input) wr (output) csm (output) of sram area dmarqx (input) csn (output) of external i/o area dmaakx (output) note 2 (output) sdcke (output) busclk (output) rd (output) bcyst (output) sdras (output) sdcas (output) data data chapter 6 dma functions (dma controller) 268 user?s manual u16031ej3v0ud figure 6-11. timing of 2-cycle dma transfer (sram external i/o): with out speculative read notes 1. state (t0) insert ed between bus cycles 2. this idle state (ti) is independ ent of the bcc register setting. 3. uube, ulbe, lube, llbe remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 0 to 7 t1 t2 t1 t2 t0 note 1 ti note 2 a0 to a25 (output) csn (output) of sram area bcyst (output) busclk (output) rd (output) wr (output) note 3 (output) d0 to d31 (i/o) wait (input) csn (output) of external i/o area data 1 data 1 address address chapter 6 dma functions (dma controller) 269 user?s manual u16031ej3v0ud figure 6-12. timing of 2-cycle dma transfer (sdram sram) (1/2) (a) without speculative read notes 1. state (t0) insert ed between bus cycles 2. this idle state (ti) is independ ent of the bcc register setting. 3. when xxwr output mode/xxdqm output mode is set (pfccta bit of pfcct register = 0) 4. when xxbe output mode/xxdqm output mode is set (pfccta bit of pfcct register = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 m = 0 to 7 a = 0 to 3 xx = uu, ul, lu, ll row col. tact tread tlate tlate t1 t2 t0 note 1 ti note 2 h h busclk (output) a0 to a25 (output) bcyst (output) csn (output) transfer source sdras (output) we (output) sdcas (output) sdcke (output) csm (output) transfer source note 4 (output) d0 to d31 (i/o) wr (output) note 3 (output) data data address chapter 6 dma functions (dma controller) 270 user?s manual u16031ej3v0ud figure 6-12. timing of 2-cycle dma transfer (sdram sram) (2/2) (b) with speculative r ead, speculative read hit notes 1. state (t0) insert ed between bus cycles 2. this idle state (ti) is independ ent of the bcc register setting. 3. uudqm, uldqm, lldqm, ludqm remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 m = 0 to 7 3. da.: data speculative read cycle ( fill c y cle of s p eculative read buffer ) da.1 row col. tact tread tlate t1 t2 da.2 da.3 da.4 t1 t2 h h tread tread tread tlate col.+4 col.+8 col.+c da.1 da.3 t0 note 1 t1 t2 da.2 t1 t2 da.4 ti note 2 ti note 2 ti note 2 ti note 2 ti note 2 ti note 2 ti note 2 ti note 2 ti note 2 ti note 2 ti note 2 busclk (output) a0 to a25 (output) sdras (output) we (output) bcyst (output) sdcas (output) sdcke (output) note 3 (output) d0 to d31 (i/o) wr (output) csm (output) transfer destination csn (output) transfer source address address address address chapter 6 dma functions (dma controller) 271 user?s manual u16031ej3v0ud (1) timing of dmarq n and dmaakn signals for 2-cycle transfer the targets of 2-cycle tr ansfer are as follows. table 6-1. targets of 2-cycle transfer transfer destination external i/o/external memory on-chip peripheral i/o internal data ram internal instruction ram external i/o/external memory on-chip peripheral i/o transfer source internal data ram remarks 1. : can be transferred, : cannot be transferred 2. for details, refer to table 6-4 minimum value of active width of dmaakn signal for 2-cycle transfer . the bus configuration is as shown below. figure 6-13. bus configuration <1> dma controller <3> internal data ram <2> internal instruction ram internal bus external bus <4> on-chip peripheral i/o <7> external i/o/external memory <5> speculative read buffer <6> write buffer caution the internal bus operate s in synchronization with the cpu clock, and the external bus operates in synchronization wit h the bus clock (busclk). chapter 6 dma functions (dma controller) 272 user?s manual u16031ej3v0ud the active width of the dmaakn signal output by the dma controller is from the beginning of a read operation by the dma controller to the end of a write operation (n = 0 to 3). the dmaakn signal is not asserted in a cycle used to write/read the internal data ram. the active width of the dmaakn signal for each dma transfer is shown below. table 6-2. active width of dm aakn signal for 2-cycle transfer transfer destination external i/o/external memory on-chip peripheral i/o internal data ram internal instruction ram external i/o/external memory <5> (<7>) ? ? ? ? ? ? ? ? ? ? ? ? ? chapter 6 dma functions (dma controller) 273 user?s manual u16031ej3v0ud (b): handshaking of the dmarqn and dmaakn signals may be completed if a read operation from the external i/o or external memo ry (dma access) has been comp leted before hands haking of the dmarqn and dmaakn signals is completed, or before a write operation to the external i/o or external memory is executed. the active state of the dmaakn signal ends as soon as data has been transferred to the write buffer (<5> <1> <6>). if speculative reading hits, data is re ad from the external i/o or external memory when speculative reading has been completed. therefore, a read oper ation from the external i/o or external memory (<7> <5>) is executed before the dmaakn signal. while data is being transferred from the speculative read buffer to the write buffer (<5> <1> <6>) after that, the dmaakn signal is asserted. for example, if dat a of three buffers has already be en stored in the write buffer, data transferred by dma is stored in the fourth buffer. after that, transfe r to the external i/o or external memory (<6> <7>) targeted by the last dmaakn signal is executed when a wr ite operati on of the stored data has taken place three times. (c): a read operation fr om the external i/o or external memory (dma access) may be completed before handshaking of the dmarqn and dmaakn signals is completed. if speculative reading hits, because the data has already been transferred from the external i/o or external memory to the speculative read buffer (<7> <5>), execution to the external i/o or external memory (dma access) will have al ready been completed while the dm aakn signal was asserted (<5> <1> (<2>, <3> or <4>)). (2) dmaakn signal active width extension function the dmaakn signal is output in synchronization with the internal bus cycle during 2-cycle transfer, and is not synchronized with the external bus cycl e (n = 0 to 3). the dma cycle di ffers depending on t he configuration subject to dma transfer (refer to 6.5.1 (1) timing of dmarqn and dm aakn signals for 2-cycle transfer ). depending on the target of dma transfer, the configuration may allo w the dmaakn signal to be asserted only for the duration of two internal syst em clocks. in this case, assert ion of the dmaakn signal may not be sampled with busclk if the internal system clock is divided and the bus cl ock (busclk) is used (e.g., bmc register = 02h: internal system clock divided by three). to sample assertion of the dmaakn signal with busclk , extend the active width of the dmaakn signal by using the dakebc bit of the dtoc regist er and daken bit of the difc register. chapter 6 dma functions (dma controller) 274 user?s manual u16031ej3v0ud the minimum value of the active width of the dmaakn during 2-cycle transfer is shown in the table below. table 6-4. minimum value of active widt h of dmaakn signal during 2-cycle transfer transfer destination speculative read function external i/o/ external memory on-chip peripheral i/o internal data ram internal instruction ram external i/o/external memory read cycle + 3 internal system clocks read cycle + (4+i) internal system clocks read cycle read cycle + internal instruction ram write cycle + 1 internal system clock on-chip peripheral i/o (6+i) internal system clocks (7+2i) internal system clocks (3+i) internal system clocks internal instruction ram write cycle + (4+i) internal system clocks internal data ram none 2 internal system clocks (3+i) internal system clocks ? internal instruction ram write cycle external i/o/external memory 5 internal system clocks (6+i) internal system clocks 2 internal system clocks internal instruction ram write cycle + 3 internal system clocks on-chip peripheral i/o (6+i) internal system clocks (7+2i) internal system clocks (3+i) internal system clocks internal instruction ram write cycle + (4+i) internal system clocks transfer source internal data ram provided 2 internal system clocks (3+i) internal system clocks ? internal instruction ram write cycle caution the function to extend the active width of the dmaakn signal can be used only during 2-cycle transfer (n = 0 to 3). it cannot be used during flyby transfer. the ope ration is not guaranteed if it is used during flyby transfer. du ring flyby transfer, the dmaakn signal synchronized with the bus cycle is output. remark i: number of wait cycles set by vswc register chapter 6 dma functions (dma controller) 275 user?s manual u16031ej3v0ud 6.5.2 flyby transfer since data is transferred in 1 cycle during a flyby transfer, a memory address is always ou tput irrespective whether it is a source address or a destinati on address, and read/write signals of the memory and peripheral i/o become active at the same time. theref ore, the external i/o is selected by the dmaak0 to dmaak3 signals. to perform a normal access to the external i/o by means other than dma transfer, externally and the csm and dmaakx signals (m = 0 to 7, x = 0 to 3), and connect the result ant signal to the chip select signal of the external i/o. a circuit example of a normal access, other than dma transfer, to external i/o is shown below. caution flyby transfer to sdram is possible only from external i/o. figure 6-14. circuit example when flyby transfer is performed between external i/o and sram ax to axx d0 to d7 oe we csn sram ax to axx d8 to d15 oe we csn sram external i/o d0 to d15 rd wr cs ax to axx d0 to d15 rd llwr, luwr csn ulwr, uuwr v850e/me2 iord csm iowr dmaakx remark n = 0 to 7, m = 0 to 7 (n m) x = 0 to 3 chapter 6 dma functions (dma controller) 276 user?s manual u16031ej3v0ud figure 6-15. timing of dma flyby transfer (external i/o sdram) (1/3) (a) single transfer mode tf note 3 twr tact twr tf note 3 t0 note 2 ti note 1 ti note 1 ti note 1 ti note 1 row h h col. a0 to a25 (output) csn (output) sdras (output) we (output) bcyst (output) iowr (ouptut) iord (ouptut) sdcas (output) sdcke (output) note 4 (ouptut) d0 to d15 (input) busclk (output) dmarqx (input) internal dma request signal dmaakx (output) tcx (output) ti note 1 ti note 1 ti note 1 ti note 1 t0 note 2 ti note 1 data data col. notes 1. this idle state (ti) is independ ent of the bcc register setting. 2. state (t0) insert ed between bus cycles 3. this wait (tf) is inserted by means of the fwc register setting. 4. uudqm, uldqm, lldqm, ludqm caution in the tf state during sdram flyby transfer, wait cycles of th e set value of the fwc register + 1 are always inserted (one wait cycle is inserte d when the set value is 0 (the case where the set value is 0 is shown above)). remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. x = 0 to 3 n = 1, 3, 4, 6 4. col.: column address row: row address chapter 6 dma functions (dma controller) 277 user?s manual u16031ej3v0ud figure 6-15. timing of dma flyby transfer (external i/o sdram) (2/3) (b) single-step transfer mode ti note 3 twr tact twr ti note 3 t0 note 2 a0 to a25 (output) csn (output) sdras (output) we (output) bcyst (output) iowr (output) iord (output) sdcas (output) sdcke (output) note 4 (output) d0 to d15 (input) busclk (output) ti note 1 ti note 1 ti note 1 ti note 1 row h h col. dmarqx (input) internal dma request signal dmaakx (output) tcx (output) ti note 1 t0 note 2 ti note 1 ti note 1 data data col. notes 1. this idle state (ti) is independ ent of the bcc register setting. 2. state (t0) insert ed between bus cycles 3. this wait (tf) is inserted by means of the fwc register setting. 4. uudqm, uldqm, lldqm, ludqm caution in the tf state during sdram flyby transfer, wait cycles of th e set value of the fwc register + 1 are always inserted (one wait cycle is inserte d when the set value is 0 (the case where the set value is 0 is shown above)). remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. x = 0 to 3 n = 1, 3, 4, 6 4. col.: column address row: row address chapter 6 dma functions (dma controller) 278 user?s manual u16031ej3v0ud figure 6-15. timing of dma flyby transfer (external i/o sdram) (3/3) (c) block transfer mode tact twr ti note 3 ti note 3 twr t0 note 2 t0 note 2 ti note 1 ti note 1 ti note 1 row h h col. a0 to a25 (output) csn (output) sdras (output) we (output) bcyst (output) iowr (output) iord (output) sdcas (output) sdcke (output) note 4 (output) d0 to d15 (input) busclk (output) dmarqx (input) internal dma request signal dmaakx (output) tcx (output) col. data data notes 1. this idle state (ti) is independ ent of the bcc register setting. 2. state (t0) insert ed between bus cycles 3. this wait (tf) is inserted by means of the fwc register setting. 4. uudqm, uldqm, lldqm, ludqm caution in the tf state during sdram flyby transfer, wait cycles of th e set value of the fwc register + 1 are always inserted (one wait cycle is inserte d when the set value is 0 (the case where the set value is 0 is shown above)). remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. 3. x = 0 to 3 n = 1, 3, 4, 6 4. col.: column address row: row address chapter 6 dma functions (dma controller) 279 user?s manual u16031ej3v0ud figure 6-16. timing of dma flyby transfer (sram external i/o) (1/2) (a) with speculative read/without speculative read, 32-bit bus width t1 t2 tw ti note 4 t1 tf note 2 t2 tasw note 3 t1 tf note 2 t2 busclk (output) a0 to a25 (output) cs0 to cs7 (output) rd (output) wr (output) bcyst (output) note 5 (output) d0 to d31 (input) wait (input) iowr (output) iord (output) h address address t0 note 1 h t0 note 1 t0 note 1 data data data address notes 1. state (t0) insert ed between bus cycles 2. this wait (tf) is inserted by means of the fwc register setting. 3. this address setup wait (tasw) is inserted by means of the asc register setting. 4. this idle state (ti) is inserted by means of the fic register setting. 5. uube, ulbe, lube, llbe remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. chapter 6 dma functions (dma controller) 280 user?s manual u16031ej3v0ud figure 6-16. timing of dma flyby transfer (sram external i/o) (2/2) (b) with speculative read/wit hout speculative read, 16-bit bus width, 32-bit data transfer address a+2 address a data t1 t2 tf note 2 ti note 4 t2 tasw note 3 t1 data t1 t2 data address b address b+2 tf note 2 ti note 4 t2 tasw note 3 t1 h t0 note 1 busclk (output) a0 to a25 (output) rd (output) wr (output) note 5 (output) d0 to d15 (input) wait (input) iowr (output) iord (output) h t0 note 1 bcyst (output) cs0 to cs7 (output) data notes 1. state (t0) insert ed between bus cycles 2. this wait (tf) is inserted by means of the fwc register setting. 3. this address setup wait (tasw) is inserted by means of the asc register setting. 4. this idle state (ti) is inserted by means of the fic register setting. 5. uube, ulbe, lube, llbe remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. chapter 6 dma functions (dma controller) 281 user?s manual u16031ej3v0ud figure 6-17. timing of dma flyby transfer (external i/o sram) (1/2) (a) with speculative read/without speculative read, 32-bit bus width t1 t2 tw ti note 4 t1 tf note 2 t2 tasw note 3 t1 tf note 2 t2 address h h address address t0 note 1 busclk (output) a0 to a25 (output) cs0 to cs7 (output) rd (output) wr (output) bcyst (output) note 5 (output) d0 to d31 (input) wait (input) iowr (output) iord (output) t0 note 1 t0 note 1 data data data notes 1. state (t0) insert ed between bus cycles 2. this wait (tf) is inserted by means of the fwc register setting. 3. this address setup wait (tasw) is inserted by means of the asc register setting. 4. this idle state (ti) is inserted by means of the fic register setting. 5. uube, ulbe, lube, llbe remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. chapter 6 dma functions (dma controller) 282 user?s manual u16031ej3v0ud figure 6-17. timing of dma flyby transfer (external i/o sram) (2/2) (b) with speculative read/wit hout speculative read, 16-bit bus width, 32-bit data transfer t1 t2 tf note 2 ti note 4 t2 tasw note 3 t1 t1 t2 tf note 2 ti note 4 t2 tasw note 3 t1 h h address a address a+2 t0 note 1 busclk (output) a0 to a25 (output) cs0 to cs7 (output) rd (output) wr (output) bcyst (output) note 5 (output) d0 to d15 (input) wait (input) iowr (output) iord (output) t0 note 1 address b address b+2 data data data data notes 1. state (t0) insert ed between bus cycles 2. this wait (tf) is inserted by means of the fwc register setting. 3. this address setup wait (tasw) is inserted by means of the asc register setting. 4. this idle state (ti) is inserted by means of the fic register setting. 5. uube, ulbe, lube, llbe remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. chapter 6 dma functions (dma controller) 283 user?s manual u16031ej3v0ud figure 6-18. timing of dma flyby transfer (page rom external i/o) (1/2) (a) with speculative read/without speculative read, 32-bit bus width t1 t2 tw ti note 4 t1 tf note 2 t2 tasw note 3 t1 tf note 2 t2 h address a2 t0 note 1 busclk (output) a0 to a25 (output) cs0 to cs7 (output) rd (output) wr (output) bcyst (output) note 5 (output) d0 to d31 (input) wait (input) iowr (output) iord (output) t0 note 1 t0 note 1 address data data data h notes 1. state (t0) insert ed between bus cycles 2. this wait (tf) is inserted by means of the fwc register setting. 3. this address setup wait (tasw) is inserted by means of the asc register setting. 4. this idle state (ti) is inserted by means of the fic register setting. 5. uube, ulbe, lube, llbe remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. chapter 6 dma functions (dma controller) 284 user?s manual u16031ej3v0ud figure 6-18. timing of dma flyby transfer (page rom external i/o) (2/2) (b) with speculative read/wit hout speculative read, 16-bit bus width, 32-bit data transfer t1 t2 tf note 2 t2 tasw note 3 t1 t1 t2 tf note 2 t2 t1 ti note 4 tf note 2 tf note 2 h address a address a+2 data data address b+2 t0 note 1 busclk (output) a0 to a25 (output) cs0 to cs7 (output) rd (output) wr (output) bcyst (output) note 5 (output) d0 to d15 (input) wait (input) iowr (output) iord (output) h t0 note 1 data data address b notes 1. state (t0) insert ed between bus cycles 2. this wait (tf) is inserted by means of the fwc register setting. 3. this address setup wait (tasw) is inserted by means of the asc register setting. 4. this idle state (ti) is inserted by means of the fic register setting. 5. uube, ulbe, lube, llbe remarks 1. the circle { indicates the sampling timing. 2. the broken lines indicate the high-impedance state. chapter 6 dma functions (dma controller) 285 user?s manual u16031ej3v0ud figure 6-19. timing of dma flyby transfer (external i/o sdram) (1/2) (a) with speculative read/without speculati ve read, 32-bit bus width, cas latency = 2 tact twr row tf note 2 tact twr row tf note 2 tf note 2 tf note 2 tf note 2 twr tf notw 2 col. twr ti note 3 h h col. col. col. t0 note 1 a0 to a25 (output) csn (output) sdras (output) we (output) bcyst (output) iowr (output) iord (output) sdcas (output) sdcke (output) note 4 (output) d0 to d15 (input) busclk (output) t0 note 1 t0 note 1 t0 note 1 data data data data notes 1. state (t0) insert ed between bus cycles 2. this wait (tf) is inserted by means of the fwc register setting. 3. this idle state (ti) is inserted by means of the fic register setting. 4. uudqm, uldqm, lldqm, ludqm caution in the tf state during sdram flyby transfer, wait cycles of th e set value of the fwc register + 1 are inserted (one wait cycle is inserted when the set value is 0). remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 3. col.: column address row: row address chapter 6 dma functions (dma controller) 286 user?s manual u16031ej3v0ud figure 6-19. timing of dma flyby transfer (external i/o sdram) (2/2) (b) with speculative read/without sp eculative read, 16-bit bus width, 32-bit data transfer, cas latency = 2 tact twr row tf note 2 tf note 2 twr twr tf note 2 tf note 2 twr h h col. col. t0 note 1 a0 to a25 (output) csn (output) sdras (output) we (output) bcyst (output) iowr (output) iord (output) sdcas (output) sdcke (output) note 3 (output) d0 to d15 (input) busclk (output) t0 note 1 col. col. data data data data notes 1. state (t0) insert ed between bus cycles 2. this wait (tf) is inserted by means of the fwc register setting. 3. uudqm, uldqm, lldqm, ludqm caution in the tf state during sdram flyby transfer, wait cycles of th e set value of the fwc register + 1 are inserted (one wait cycle is inserted when the set value is 0). remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 3. col.: column address row: row address chapter 6 dma functions (dma controller) 287 user?s manual u16031ej3v0ud 6.6 transfer target 6.6.1 transfer type and transfer target table 6-1 lists the relationships between tran sfer type and transfer target. the mark ? in the case of flyby transfer, make the da ta bus width the same for the source and destination. 3. addresses between 3fff000h and 3ffffffh ca nnot be specified for the source and destination address of dma transfer. be sure to specify an address between ffff000h and fffffffh. 4. do not use dma transfer to set on-chip periphe ral i/o registers and to read the set values. remarks 1. during 2-cycle dma transfer, if the data bus width of the transfer source and that of the transfer destination are different, the operation becomes as follows. if dma transfer is executed to transfer data of an on-chip peripheral i/o register (as a transfer source or destination), be sure to specify the same transfer size as the register size. for example, to execute dma transfer of an 8-bit register, be sure to specify byte (8-bit) transfer. <32-bit transfer> ? chapter 6 dma functions (dma controller) 288 user?s manual u16031ej3v0ud ? transfer from a 32-bit bus to an 8-bit bus a read cycle (32 bits) is generated and then a write cycle (8 bits) is generated 4 times consecutively. ? transfer from a 16-bit bus to an 8-bit bus a read cycle (16 bits) is generated twice consecutiv ely and then a write cycle (8 bits) is generated 4 times consecutively. ? transfer from a 16-bit bus to a 32-bit bus a read cycle (16 bits) is generated twice consec utively and then a write cycle (32 bits) is generated. for how to write data to the transfer destination, see remark 2 below. ? transfer from an 8-bit bus to a 32-bit bus a read cycle (8 bits) is generated 4 times cons ecutively and then a write cycle (32 bits) is generated. for how to write data to the transfer destination, see remark 2 below. ? transfer from an 8-bit bus to a 16-bit bus a read cycle (8 bits) is generated 4 times cons ecutively and then a write cycle (16 bits) is generated twice consecutively. for how to write data to the trans fer destination, see remark 2 below. <16-bit transfer> ? transfer from a 32-bit bus to a 16-bit bus a read cycle (the higher 16 bits are high impedance) is generated and then a write cycle (16 bits) is generated. ? transfer from a 32-bit bus to an 8-bit bus a read cycle (the higher 16 bits are high impedance) is generated and then a write cycle (8 bits) is generated twice c onsecutively. ? transfer from a 16-bit bus to an 8-bit bus a read cycle (16 bits) is generated and then a write cycle (8 bits) is generated twice consecutively. ? transfer from a 16-bit bus to a 32-bit bus a read cycle (16 bits) is generated and then a writ e cycle (the higher 16 bits are high impedance) is generated. for how to write dat a to the transfer destination, see remark 2 below. ? transfer from an 8-bit bus to a 32-bit bus a read cycle (8 bits) is generated twice consecutiv ely and then a write cycle (the higher 16 bits are high impedance) is generated. for how to write data to the transfer destination, see remark 2 below. ? transfer from an 8-bit bus to a 16-bit bus a read cycle (8 bits) is generated twice consecutivel y and then a write cycle (16 bits) is generated. for how to write data to the transfer destination, see remark 2 below. <8-bit transfer> ? transfer from a 32-bit bus to a 16-bit bus a read cycle (the higher 24 bits are high imped ance) is generated and then a write cycle (the higher 8 bits are high impedance) is generated. ? transfer from a 32-bit bus to an 8-bit bus a read cycle (the higher 24 bits are high impedance) is generated and then a write cycle (8 bits) is generated. ? transfer from a 16-bit bus to an 8-bit bus a read cycle (the higher 8 bits are high impedance) is generated and then a write cycle (8 bits) is generated. chapter 6 dma functions (dma controller) 289 user?s manual u16031ej3v0ud ? transfer from a 16-bit bus to a 32-bit bus a read cycle (the higher 8 bits are high impedance) is generated and then a write cycle (the higher 24 bits are high impedance) is generated. for how to write data to the transfer destination, see remark 2 below. ? transfer from an 8-bit bus to a 32-bit bus a read cycle (8 bits) is generated and then a write cycle (the higher 24 bits are high impedance) is generated. for how to write data to the transfer destination, see remark 2 below. ? transfer from an 8-bit bus to a 16-bit bus a read cycle (8 bits) is generated a nd then a write cycle (the higher 8 bits are high impedance) is generated. for how to write data to the transfer destination, see remark 2 below. remarks 2. under the following conditions, data is written to the lower byte and then the higher byte of the transfer destination in the little-endian mode, and to the higher byte and lower byte of the destination in the big-endian mode. ? transfer from a 16-bit bus to a 32-bit bus ? transfer from an 8-bit bus to a 32-bit bus ? transfer from an 8-bit bus to a 16-bit bus 6.6.2 external bus cycles during dma transfer the external bus cycles during dma transfer are shown below. table 6-6. external bus cycles during dma transfer transfer type transfer target external bus cycle on-chip peripheral i/o, internal data ram, internal instruction ram none ? external i/o yes sram cycle 2-cycle transfer external memory yes memory acce ss cycle set by the bct register flyby transfer between external memory and external i/o yes dma flyby transfer cycle accessing memory that is set as external memory by the bct register 6.7 dma channel priorities the dma channel priorities are fixed as follows. dma channel 0 > dma channel 1 > dma channel 2 > dma channel 3 in the block transfer mode, the channel used for transfer is never switched. in the single-step transfer mode, if a hi gher priority dma transfer request is issued while the bus is released, the higher priority dma transfer request is acknowledged. caution if dma is started by inputting the same signa l to more than one dmarqn pin (n = 0 to 3), a dma channel with a lower priority m ay be acknowledged before a dm a channel with a higher priority. chapter 6 dma functions (dma controller) 290 user?s manual u16031ej3v0ud 6.8 next address setting function the dma source address registers (dsanh, dsanl), dm a destination address registers (ddanh, ddanl), and dma transfer count register (dbcn) are buffer register s with a 2-stage fifo configuration (n = 0 to 3). when the terminal count is issued, thes e registers are automatically rewritten with the value that was set immediately before. therefore, during dma transfer, transfe r is automatically started when a new dma transfer setting is made for these registers and the enn bit of the dchcn register, a nd mlen bit is set to 1 (however, the dma transfer end interrupt may be issued even if dma transfer is automatically started). the configuration of the buffe r register is shown below. figure 6-20. buffer register configuration data read data write master register slave register address/ count controller internal bus the actual dma transfer is executed in accor dance with the contents of the slave register. the set values that are reflected in the master register and slave register differ as follows, depending on the timing (period) of setting the registers. (1) period from system reset to the be ginning of the first dma transfer the set value is reflected in both t he master register and slave register. (2) during dma transfer (period from the beginning to the end of dma transfer) the set value is reflected only in the master register and not in the slave re gister (the slave register holds the set value for the next dma transfer). however, the contents of the master register are automatically overwritten to the slave register after completion of dma transfer. if the value of each regist er is read during this period, the value of the slave register is read. (3) period from the end of dma transfer to the beginning of the next dma transfer the set value is reflected in both t he master register and slave register. remark ?the end of dma transfer? means either of the following. ? completion of dma transfer (terminal count) ? forced termination of dma transfer (setting the initn bit of the dma channel control register (dchcn) to 1) chapter 6 dma functions (dma controller) 291 user?s manual u16031ej3v0ud if the setting of a new dma transfer is made using th e dsanh, dsanl, ddanl, and dbcn registers during dma transfer, the values of the registers are aut omatically updated after completion of transfer note . note before setting a new dma transfer, confirm the start of the preceding dma transfer. if the setting of the new dma transfer is made befor e the start of the preced ing dma transfer, the new set value is overwritten to both the master register and slave register, and dma transfer according to the preceding set value cannot be executed. chapter 6 dma functions (dma controller) 292 user?s manual u16031ej3v0ud 6.9 dma transfer start factors there are 4 types of dma transfer start factors, as shown below. cautions 1. do not use two or more start factors ((1) to (4)) in combin ation for the same channel (if two or more start factors are generated at the same ti me, only one of them is valid, but the valid start factor cannot be identified). the operation is not guarant eed if two or more start fact ors are used in combination. 2. if dma transfer is started via software and if the software does not correctly detect whether the expected dma transfer opera tion has been completed through manipulation (setting to 1) of the stgn bit of the dchcn register, it cannot be guaranteed whether the next (second) manipulation of the stgn bit corresponds to the st art of ?the next dma transfer expected by software? (n = 0 to 3). for example, suppose single transfer is starte d by manipulating the stgn bit. even if the stgn bit is manipulated next (the second time) without checking by software whether the single transfer has actually b een executed, the next (second) dma transfer is not always executed. this is because the stgn bit may be manipulated th e second time before the first dma transfer is started or completed because , for example, dma transfer with a higher priority had already been started when the stgn bit was manipulated for the first time. it is therefore necessary to manipulate the stgn bit next time (the second time) after checking whether dma transfer started by the fi rst manipulation of th e stgn bit has been completed. completion of dma transfer can be checked in th e following ways. ? detecting the acknowledge signal (dmaakn) or terminal count signal (tcn) by using a peripheral port or interrupt ? checking the contents of the dbcn register chapter 6 dma functions (dma controller) 293 user?s manual u16031ej3v0ud (1) request from an external pin (dmarqn) requests from the dmarqn pin are sampled each time the busclk signal rises (n = 0 to 3). hold the request from dmarqn pin until the corresponding dmaakn si gnal becomes active. if a state whereby the enn bit of the dchcn register = 1 and the tcn bi t = 0 is set, the dmarqn signal becomes valid. if the dmarqn signal set by the dtfrn register becomes active in this status, dma transfer starts. (2) request from software if the stgn, enn, and tcn bits of t he dchcn register are set as follows, dma transfer starts (n = 0 to 3). ? stgn bit = 1 ? enn bit = 1 ? tcn bit = 0 (3) request from on-chip peripheral i/o if, when the enn and tcn bits of the dchcn register are set as shown below, an interrupt request is issued from the on-chip peripheral i/o that is set in the dtfrn register, dma transfer starts (n = 0 to 3). ? enn bit = 1 ? tcn bit = 0 (4) request by usb (enabled only in single transfer mode) if a request is generated from the usb set to the d tfrn register when the enn and tcn bits of the dchcn register are set as follows, dma transfer starts (n = 0 to 3). ? enn bit = 1 ? tcn bit = 0 remark since the dmarqn signal is level-sampled and no t edge-detected, to enable edge detection of a dma request, set an external interrupt request for the dma start trigger instead of using the dmarqn signal (n = 0 to 3). chapter 6 dma functions (dma controller) 294 user?s manual u16031ej3v0ud 6.10 terminal count output upon dma transfer end the terminal count signal (tcn) becomes active for one cl ock of busclk during the last dma transfer cycle (n = 3 to 0). figure 6-21. terminal count signal (tcn) timing example (1) cpu cpu dman dman dman cpu cpu dmarqn (input) tcn (output) dma channel n terminal count remark n = 0 to 3 the tcn signal becomes active for one clock in any clock, from which the dmaakn signal of the last dma transfer is output when 2-cycle transfer is executed. if the transfer destination is the in ternal data ram, however, the tcn signal is not output. when flyby transfer is executed, the tcn signal becomes active for one clock at the clock in which the bcyst signal of the last dma tr ansfer cycle becomes active. figure 6-22. terminal count signal (tcn) timing example (2) (1) 2-cycle transfer read cycle 2-cycle transfer (last) write cycle busclk (output) tcn (output) (2) flyby transfer flyby transfer cycle (last) busclk (output) tcn (output) remark n = 0 to 3 chapter 6 dma functions (dma controller) 295 user?s manual u16031ej3v0ud 6.11 forcible interruption dma transfer can be forcibly interrupted by nmi input during dma transfer. at such a time, the dmac resets the enn bit of the dc hcn register of all channels to 0 and the dma transfer disabled state is entered. an nmi request can then be ac knowledged after the dma transfer that was being executed when the nmi was input is complete (n = 0 to 3). chapter 6 dma functions (dma controller) 296 user?s manual u16031ej3v0ud 6.12 forcible termination dma transfer can be forcibly terminated by the initn bi t of the dchcn register, in addition to the forcible interruption operation by means of nmi input (n = 0 to 3). an example of forcible termination by the initn bit of the dchcn register is illustrated below (n = 0 to 3). figure 6-23. example of forcible termination of dma transfer (a) block transfer through dma channel 3 is starte d during single-step transf er through dma channel 2 cpu cpu cpu cpu dma2 cpu dma2 cpu dma2 cpu dma3 dma3 dma3 dma3 cpu cpu cpu dmarq2 (input) dmarq3 (input) dma channel 3 transfer start dma channel 3 terminal count forcible termination of dma channel 2 transfer dsa2, dda2, dbc2, dadc2, dchc2 register set dchc2 (init2 bit = 1) register set dsa3, dda3, dbc3, dadc3, dchc3 register set e22 bit = 1 tc2 bit = 0 e22 bit 0 tc2 bit = 0 e33 bit = 1 tc3 bit = 0 e33 bit 0 tc3 bit 1 (b) when transfer is aborted dur ing dma channel 1 single-step tran sfer, and transfer under another condition is executed cpu cpu cpu cpu cpu dma1 cpu dma1 cpu dma1 cpu cpu cpu cpu dma1 dma1 dma1 cpu dmarq1 (input) forcible termination of dma channel 1 transfer dma channel 1 terminal count dsa1, dda1, dbc1, dadc1, dchc1 register set dadc1, dchc1 register set dchc1 (init1 bit = 1) register set dsa1, dda1, dbc1 register set e11 bit = 1 tc1 bit = 0 e11 bit 0 tc1 bit = 0 e11 bit 1 tc1 bit = 0 e11 bit 0 tc1 bit 1 remark the values of the dsan, ddan, and dbcn regist ers (n = 0 to 3) are retained even when dma transfer is forcibly stopped, bec ause these registers are fifo-confi gured buffer registers. the next transfer condition can be set to these registers even while dma transfer is in progress. on the other hand, the setting of the dadcn and dchcn registers is invalid during dma transfer because these registers are not buffer registers (see 6.8 next address setting function , 6.3.4 dma addressing control registers 0 to 3 (dadc0 to dadc3) , and 6.3.5 dma channel control registers 0 to 3 (dchc0 to dchc3) ). chapter 6 dma functions (dma controller) 297 user?s manual u16031ej3v0ud 6.13 times related to dma transfer the overhead before and after dma transfer and minimum ex ecution clock for dma transfer are shown below. in the case of external memory access, the time depends on the type of external memory connected. table 6-7. number of minimu m execution clocks in dma cycle dma cycle number of minimum execution clocks <1> time to respond to dma request 4 clocks note 1 external memory access differs depending on the memory connected internal data ram or internal instruction ram (read mode) access 2 clocks note 2 <2> memory access peripheral i/o register access 3 clocks + number of wait cycles specified by vswc register notes 1. if an external interrupt (intpn) is specified as a fact or of starting dma transfer, noise elimination time is added (n = 10, 11, 21 to 25, 50 to 52, 65 to 67, d0 to d15, l0, or l1). 2. two clocks are required for the dma cycle. the minimum execution clock in the dma cycl e in each transfer mode is as follows. 2-cycle transfer ? ? chapter 6 dma functions (dma controller) 298 user?s manual u16031ej3v0ud 6.14 maximum response time for dma transfer request the response time for a dma transfer request becomes the longest under the following conditions (state in which all the refresh cycles for the sdram are enabled). caution the wait time caused by the fo llowing conditions is not included. ? ? ? ? chapter 6 dma functions (dma controller) 299 user?s manual u16031ej3v0ud 6.15 cautions (1) memory boundary the transfer operation is not guarant eed if the source or the destination address exceeds the area of dma objects (external memory, internal data ram, internal instruct ion ram, or peripheral i/o) during dma transfer. (2) transfer of misaligned data dma transfer of 32-/16-bit bus width misaligned data is not supported. if the source or the destination address is set to an odd address, the lsb of the address is forcibly handled as ?0?. (3) bus arbitration for cpu when dma transfer is executed to transfer data to/from an external device, the cpu can access internal data ram and internal instruction ram note not being used for dma transfer. because the dma controller has a priority higher than the cpu acquiring bus mastership, a cpu access that takes place during dma transfer is kept waiting until t he preceding dma transfer is completed and the bus is released to the cpu. if dma transfer is executed bet ween the external memory and on-chip peripheral i/o, however, the cpu can access the internal data ram and internal instruction ram note . note when the irammn bit of the iramm register = 0 (n = 0, 1) (4) holding dmarqn signal be sure to keep the dmarqn signal active until the dmaakn signal becomes active (n = 0 to 3). (5) dmaakn signal output when the transfer target is internal data ram, the dmaakn signal is not output during a dma cycle for internal data ram (for example, if 2-cycle transfer is performed from internal data ram to an external memory, the dmaakn signal is output only during a dma write cycle for the external memory). if the transfer target is the on-chip peripheral i/o or internal instructio n ram, the dmaakn signal is output even in the dma cycle executed on the on-chip pe ripheral i/o or internal instruction ram. the dmaakn signal maintains t he active state during the ti state of flyby transfer. (6) dma start factors do not start two or more dma channels with the same factor. if two or more dma channels are started with the same factor, the dma channel with the lower prio rity may be accepted before the dma channel with the higher priority. chapter 6 dma functions (dma controller) 300 user?s manual u16031ej3v0ud (7) read values of dsan and ddan registers if the values of the dsan and ddan registers are read during dma transfer, the values in the middle of being updated may be read (n = 0 to 3). for example, if the dsanh register and the dsanl regist er are read in that order when the value of the dma transfer source address (dsa n register) is ?0000ffffh? an d the counting direction is incremental (when the sadn1 and sadn0 bits of the dadcn register = 00), t he value of the dsanl register differs as follows depending on whether dma transfer is executed immedi ately after the dsanh register has been read. (a) if dma transfer does not occur while the dsan register is being read <1> reading dsanh register: dsanh = 0000h <2> reading dsanl register: dsanl = ffffh (b) if dma transfer occurs while the dsan register is being read <1> reading dsanh register: dsanh = 0000h <2> occurrence of dma transfer <3> incrementing dsan register : dsan = 00010000h <4> reading dsanl register: dsanl = 0000h 6.15.1 interrupt factors dma transfer is interrupted if the following factors are issued. ? bus hold ? refresh cycle if the factor that is interrupting dma transfer disappears, dma transfer promptly restarts. 6.16 dma transfer end when dma transfer ends and the tcn bit of the dchcn register is set to 1, a dma transfer end interrupt (intdman) is issued to the interrupt controller (intc) (n = 0 to 3). 301 user?s manual u16031ej3v0ud chapter 7 interrupt/exception processing function the v850e/me2 is provided with a dedica ted interrupt controller (intc) for interrupt servicing and can process a total of 91 interrupt requests. an interrupt is an event that occu rs independently of program execution, and an except ion is an event whose occurrence is dependent on program execution. the v850e/me2 can process interrupt requests from t he on-chip peripheral hardwar e and external sources. moreover, exception processing can be st arted by the trap instruction (softwar e exception) or by generation of an exception event (i.e. fetching of an illegal opcode) (exception trap). 7.1 features { interrupts non-maskable interrupts: 1 source maskable interrupts: 90 sources 8 levels of programmable priorities (maskable interrupts) multiple interrupt control according to priority masks can be specified for each maskable interrupt request. noise elimination note , edge detection, and valid edge specification for external interrupt request signals. note for details of the noise eliminator, see 14.6 noise eliminator . { exceptions software exceptions: 32 sources exception traps: 2 sources (illegal opcode exception and debug trap) interrupt/exception sources ar e listed in table 7-1. chapter 7 interrupt/exception processing function 302 user?s manual u16031ej3v0ud table 7-1. interrupt/exception source list (1/3) interrupt/exception source type classification name controlling register generating source generating unit default priority exception code handler address restored pc reset interrupt reset ? reset input ? ? 0000h 00100000h undefine d non-maskable interrupt nmi0 ? nmi input ? ? 0010h 00000010h nextpc exception trap0n note ? trap instruction ? ? 004nh note 00000040h nextpc software exception exception trap1n note ? trap instruction ? ? 005nh note 00000050h nextpc exception trap exception ilgop/ dbg0 ? illegal opcode/ dbtrap instruction ? ? 0060h 00000060h nextpc interrupt intp10 p1ic0 intp10 pin pin 0 0080h 00000080h nextpc interrupt intp11 p1ic1 intp11 pin pin 1 0090h 00000090h nextpc interrupt intp21 p2ic1 intp21 pin pin 2 00a0h 000000a0h nextpc interrupt intp22 p2ic2 intp22 pin pin 3 00b0h 000000b0h nextpc interrupt intp23 p2ic3 intp23 pi n pin 4 00c0h 000000c0h nextpc interrupt intp24 p2ic4 intp24 pi n pin 5 00d0h 000000d0h nextpc interrupt intp25 p2ic5 intp25 pin pin 6 00e0h 000000e0h nextpc interrupt intp50 p5ic0 intp50 pi n pin 7 00f0h 000000f0h nextpc interrupt intp51 p5ic1 intp51 pin pin 8 0100h 00000100h nextpc interrupt intp52 p5ic2 intp52 pin pin 9 0110h 00000110h nextpc interrupt intp65 p6ic5 intp65 pin pin 10 0120h 00000120h nextpc interrupt intp66 p6ic6 intp66 pin pin 11 0130h 00000130h nextpc interrupt intp67 p6ic7 intp67 pin pin 12 0140h 00000140h nextpc interrupt intpd0 pdic0 intpd0 pin pin 13 0150h 00000150h nextpc interrupt intpd1 pdic1 intpd1 pin pin 14 0160h 00000160h nextpc interrupt intpd2 pdic2 intpd2 pin pin 15 0170h 00000170h nextpc interrupt intpd3 pdic3 intpd3 pin pin 16 0180h 00000180h nextpc interrupt intpd4 pdic4 intpd4 pin pin 17 0190h 00000190h nextpc interrupt intpd5 pdic5 intpd5 pin pin 18 01a0h 000001a0h nextpc interrupt intpd6 pdic6 intpd6 pin pin 19 01b0h 000001b0h nextpc interrupt intpd7 pdic7 intpd7 pin pin 20 01c0h 000001c0h nextpc interrupt intpd8 pdic8 intpd8 pin pin 21 01d0h 000001d0h nextpc interrupt intpd9 pdic9 intpd9 pin pin 22 01e0h 000001e0h nextpc interrupt intpd10 pdic 10 intpd10 pin pin 23 01f0h 000001f0h nextpc interrupt intpd11 pdic11 intpd 11 pin pin 24 0200h 00000200h nextpc interrupt intpd12 pdic12 intpd 12 pin pin 25 0210h 00000210h nextpc interrupt intpd13 pdic13 intpd 13 pin pin 26 0220h 00000220h nextpc interrupt intpd14 pdic14 intpd 14 pin pin 27 0230h 00000230h nextpc interrupt intpd15 pdic15 intpd 15 pin pin 28 0240h 00000240h nextpc interrupt intpl0 plic0 intpl0 pin pin 29 0250h 00000250h nextpc interrupt intpl1 plic1 intpl1 pin pin 30 0260h 00000260h nextpc interrupt intovc0 ovcic0 timer c0 overflow rpu 31 0270h 00000270h nextpc interrupt intovc1 ovcic1 timer c1 overflow rpu 32 0280h 00000280h nextpc interrupt intovc2 ovcic2 timer c2 overflow rpu 33 0290h 00000290h nextpc maskable interrupt intovc3 ovcic3 timer c3 overflow rpu 34 02a0h 000002a0h nextpc note n = 0 to fh chapter 7 interrupt/exception processing function 303 user?s manual u16031ej3v0ud table 7-1. interrupt/exception source list (2/3) interrupt/exception source type classification name controlling register generating source generating unit default priority exception code handler address restored pc interrupt intovc4 ovcic4 timer c4 overflow rpu 35 02b0h 000002b0h nextpc interrupt intovc5 ovcic5 timer c5 overflow rpu 36 02c0h 000002c0h nextpc interrupt intpc00/ intccc00 ccc0ic0 match of intpc00 pin/ccc00 pin/rpu 37 02d0h 000002d0h nextpc interrupt intpc01/ intccc01 ccc0ic1 match of intpc01 pin/ccc01 pin/rpu 38 02e0h 000002e0h nextpc interrupt intpc10/ intccc10 ccc1ic0 match of intpc10 pin/ccc10 pin/rpu 39 02f0h 000002f0h nextpc interrupt intpc11/ intccc11 ccc1ic1 match of intpc11 pin/ccc11 pin/rpu 40 0300h 00000300h nextpc interrupt intpc20/ intccc20 ccc2ic0 match of intpc20 pin/ccc20 pin/rpu 41 0310h 00000310h nextpc interrupt intpc21/ intccc21 ccc2ic1 match of intpc21 pin/ccc21 pin/rpu 42 0320h 00000320h nextpc interrupt intpc30/ intccc30 ccc3ic0 match of intpc30 pin/ccc30 pin/rpu 43 0330h 00000330h nextpc interrupt intpc31/ intccc31 ccc3ic1 match of intpc31 pin/ccc31 pin/rpu 44 0340h 00000340h nextpc interrupt intccc40 ccc4ic0 ccc40 match rpu 45 0350h 00000350h nextpc interrupt intccc41 ccc4ic1 ccc41 match rpu 46 0360h 00000360h nextpc interrupt intccc50 ccc5ic0 ccc50 match rpu 47 0370h 00000370h nextpc interrupt intccc51 ccc5ic1 ccc51 match rpu 48 0380h 00000380h nextpc interrupt intcmd0 cmdic0 cmd0 match rpu 49 0390h 00000390h nextpc interrupt intcmd1 cmdic1 cmd1 match rpu 50 03a0h 000003a0h nextpc interrupt intcmd2 cmdic2 cmd2 match rpu 51 03b0h 000003b0h nextpc interrupt intcmd3 cmdic3 cmd3 match rpu 52 03c0h 000003c0h nextpc interrupt intcc100 cc10ic0 cc100 ma tch rpu 53 03d0h 000003d0h nextpc interrupt intcc101 cc10ic1 cc101 ma tch rpu 54 03e0h 000003e0h nextpc interrupt intcm100 cm10ic0 cm100 ma tch rpu 55 03f0h 000003f0h nextpc interrupt intcm101 cm10ic1 cm101 match rpu 56 0400h 00000400h nextpc interrupt intov10 ov1ic0 timer enc 10 overflow rpu 57 0410h 00000410h nextpc interrupt intud10 ud1ic0 timer enc 10 underflow rpu 58 0420h 00000420h nextpc interrupt intcc110 cc11ic0 cc110 match rpu 59 0430h 00000430h nextpc interrupt intcc111 cc11ic1 cc111 match rpu 60 0440h 00000440h nextpc interrupt intcm110 cm11ic0 cm110 match rpu 61 0450h 00000450h nextpc interrupt intcm111 cm11ic1 cm111 match rpu 62 0460h 00000460h nextpc interrupt intov11 ov1ic1 timer enc 11 overflow rpu 63 0470h 00000470h nextpc interrupt intud11 ud1ic1 timer enc 11 underflow rpu 64 0480h 00000480h nextpc interrupt intdma0 dmaic0 end of dm a0 transfer dma 65 0490h 00000490h nextpc interrupt intdma1 dmaic1 end of dma1 transfer dma 66 04a0h 000004a0h nextpc interrupt intdma2 dmaic2 end of dma2 transfer dma 67 04b0h 000004b0h nextpc interrupt intdma3 dmaic3 end of dma3 transfer dma 68 04c 0h 000004c0h nextpc interrupt intcsi30 csi3ic0 csi30 transmission/ reception completion sio 69 04d0h 000004d0h nextpc maskable interrupt intcovf30 covf3ic0 csi30buf overflow sio 70 04e0h 000004e0h nextpc chapter 7 interrupt/exception processing function 304 user?s manual u16031ej3v0ud table 7-1. interrupt/exception source list (3/3) interrupt/exception source type classification name controlling register generating source generating unit default priority exception code handler address restored pc interrupt intcsi31 csi3ic1 csi31 transmission/ reception completion sio 71 04f0h 000004f0h nextpc interrupt intcovf31 covf3ic1 csi31buf overflow sio 72 0500h 00000500h nextpc interrupt ubtire0 ureic0 uartb0 rec eption error sio 73 0510h 00000510h nextpc interrupt ubtir0 uric0 uartb0 reception completion sio 74 0520h 00000520h nextpc interrupt ubtit0 utic0 uartb0 transmission completion sio 75 0530h 00000530h nextpc interrupt ubtif0 uific0 uartb0 fifo transmission completion sio 76 0540h 00000540h nextpc interrupt ubtito0 utoi c0 uartb0 reception timeout sio 77 0550h 00000550h nextpc interrupt ubtire1 ureic1 uartb1 rec eption error sio 78 0560h 00000560h nextpc interrupt ubtir1 uric1 uartb1 reception completion sio 79 0570h 00000570h nextpc interrupt ubtit1 utic1 uartb1 transmission completion sio 80 0580h 00000580h nextpc interrupt ubtif1 uific1 uartb1 fifo transmission completion sio 81 0590h 00000590h nextpc interrupt ubtito1 utoi c1 uartb1 reception timeout sio 82 05a0h 000005a0h nextpc interrupt intad adic end of a/d c onversion adc 83 05b0h 000005b0h nextpc interrupt intusb0b us0bic usb function status 0 usbf 84 05c0h 000005c0h nextpc interrupt intusb1b us1bic usb function status 1 usbf 85 05d0h 000005d0h nextpc interrupt intusb2b us2bic usb function status 2 usbf 86 05e0h 000005e0h nextpc interrupt usbsp2b usp2ic forcible end of usb function ep2 dma usbf 87 05f0h 000005f0h nextpc interrupt usbsp4b usp4ic forcible end of usb function ep4 dma usbf 88 0600h 00000600h nextpc maskable interrupt intrsum rsumic usb resume signal detection sie 89 0610h 00000610h nextpc remarks 1. default priority: the priority order when two or more maskable interrupt requests occur at the same time. the highest priority is 0. restored pc: the value of the pc saved to eipc or fepc when interrupt/exception processing is started. however, t he value of the pc saved when an interrupt is acknowledged during divide instruction (div, divh, divu, divhu) execution is the value of the pc of the current instruction (div, divh, divu, divhu). nextpc: the pc value that starts the processing following interrupt/exception processing. 2. the execution address of the illegal instruction when an illegal opcode exception occurs is calculated by (restored pc ? 4). chapter 7 interrupt/exception processing function 305 user?s manual u16031ej3v0ud 7.2 non-maskable interrupts a non-maskable interrupt request is acknowledged unconditi onally, even when interrupts are in the interrupt disabled (di) status. an nmi is not subject to priority control and takes precedence over all the other interrupts. a non-maskable interrupt request is input from the nmi pi n. when the valid edge specif ied by bit 0 (nmir0) of external interrupt rising edge specificat ion register 2 (intr2) or bit 0 (nmi f0) of external interrupt falling edge specification register 2 (intf2) is detect ed at the nmi pin, the interrupt occurs. while the service program of the non-maskable interrupt is being execut ed, the acknowledgm ent of another non- maskable interrupt request is held pending. the pending nmi is acknowledged after the original service program of the non-maskable interrupt under execution has been terminated (by the reti instructi on). note that if two or more nmi requests are input during the exec ution of the service program for an nmi, the number of nmis that will be acknowledged after the reti instruction is executed is cleared to 0 is only one. chapter 7 interrupt/exception processing function 306 user?s manual u16031ej3v0ud 7.2.1 operation if a non-maskable interrupt is generated, the cpu performs the following proce ssing, and transfers control to the handler routine: <1> saves the restored pc to fepc. <2> saves the current psw to fepsw. <3> writes exception code 0010h to the higher halfword (fecc) of ecr. <4> sets the np and id bits of the psw and clears the ep bit. <5> sets the handler address (00000010h) corresponding to the non-maskable interrupt to the pc, and transfers control. the servicing configuration of a non-mask able interrupt is shown in figure 7-1. figure 7-1. servicing configurat ion of non-maskable interrupt psw.np fepc fepsw ecr.fecc psw.np psw.ep psw.id pc restored pc psw 0010h 1 0 1 00000010h 1 0 nmi input non-maskable interrupt request interrupt servicing interrupt request held pending intc acknowledged cpu processing chapter 7 interrupt/exception processing function 307 user?s manual u16031ej3v0ud figure 7-2. acknowledging non -maskable interrupt request (a) if a new nmi request is generated while an nmi ser vice program is being executed main routine nmi request nmi request (psw.np = 1) nmi request is held pending regardless of the value of the np bit of psw. pending nmi request serviced (b) if a new nmi request is generated twice while an nmi service program is being executed main routine nmi request nmi request held pending because nmi service program is being serviced only one nmi request is acknowledged even though two nmi requests are generated nmi request held pending because nmi service program is being serviced chapter 7 interrupt/exception processing function 308 user?s manual u16031ej3v0ud 7.2.2 restore execution is restored from the non-maskable inte rrupt servicing by the reti instruction. when the reti instruction is execut ed, the cpu performs the following proc essing, and transfers control to the address of the restored pc. <1> restores the values of the pc and the psw from fepc and fepsw, res pectively, because the ep bit of the psw is 0 and the np bit of the psw is 1. <2> transfers control back to the address of the restored pc and psw. figure 7-3 illustrates how the reti instruction is processed. figure 7-3. reti instruction processing psw.ep reti instruction psw.np original processing restored 1 1 0 0 pc psw eipc eipsw pc psw fepc fepsw caution when the psw.ep bit and psw.np bit ar e changed by the ldsr instruction during non- maskable interrupt servicing, in order to rest ore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 0 and psw.np back to 1 using the ldsr instruction immediately before the reti instruction. remark the solid line shows the cpu processing flow. chapter 7 interrupt/exception processing function 309 user?s manual u16031ej3v0ud 7.2.3 non-maskable interrupt status flag (np) the np flag is a status flag that i ndicates that non-maskable interrupt (nmi ) servicing is under execution. this flag is set when an nmi interrupt has been acknowl edged, and masks all interrupt requests and exceptions to prohibit multiple interrupts from being acknowledged. 31 0 psw after reset 00000020h 7 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit position bit name function 7 np nmi pending indicates whether nmi interrupt servicing is in progress. 0: no nmi interrupt servicing 1: nmi interrupt currently being serviced 7.2.4 edge detection function (1) external interrupt rising edge specification register 2 (intr2), external interrupt falling edge specification register 2 (intf2) these registers are used to specify the valid edge of the non-maskable interr upt (nmi). the nmir0 bit of the intr2 register and nmif0 bit of the intf2 register specify the rising edge, falli ng edge, or both the rising and falling edges of the nmi as the valid edge. these registers can be read or wr itten in 8-bit or 1-bit units. 7 0 intr2 6 0 5 intr25 4 intr24 3 intr23 2 intr22 1 intr21 0 nmir0 address fffffc24h after reset 3fh 0 intf2 0 intf25 intf24 intf23 intf22 intf21 nmif0 fffffc04h 00h bit position bit name function specify the nmi pin?s valid edge. nmif0 nmir0 operation 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges 0 nmir0 (intr2 register), nmif0 (intf2 register) remark for bits 5 to 1, see 7.3.9 (2) external interrupt rising e dge specification regi ster 2 (intr2), external interrupt falling edge sp ecification register 2 (intf2) . chapter 7 interrupt/exception processing function 310 user?s manual u16031ej3v0ud 7.3 maskable interrupts maskable interrupt requests can be ma sked by interrupt control register s. the v850e/me2 has 90 maskable interrupt sources. if two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority. in addition to the default priority, eight le vels of priorities can be spec ified by using the interrupt control registers (programmable priority control). when an interrupt request has been ackno wledged, the acknowledgment of other maskable interrupt requests is disabled and the interrupt disabled (di) status is set. when the ei instruction is ex ecuted in an interrupt service routine, the interrupt enabled (ei) status is set, which enables servicing of interrupts having a hi gher priority than the interrupt request in progress (specified by the interrupt control register). note that only in terrupts with a higher priority will have th is capability; interrupts with the same priority level cannot be nested. however, if multiple interrupts are exec uted, the following processing is necessary. <1> save eipc and eipsw in memory or a general-purpos e register before executi ng the ei instruction. <2> execute the di instruct ion before executing the reti instruction, then reset ei pc and eipsw with the values saved in <1>. 7.3.1 operation if a maskable interrupt occurs by int input, the cpu perfo rms the following processing, and transfers control to a handler routine: <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower halfword of ecr (eicc). <4> sets the id bit of the psw and clears the ep bit. <5> sets the handler address corresponding to each interrupt to the pc, and transfers control. the servicing configurati on of a maskable interrupt is shown in figure 7-4. chapter 7 interrupt/exception processing function 311 user?s manual u16031ej3v0ud figure 7-4. maskable interrupt servicing int input xxif = 1 no xxmk = 0 no is the interrupt mask released? yes yes no no no maskable interrupt request interrupt request held pending psw.np psw.id 1 1 interrupt request held pending 0 0 interrupt servicing cpu processing intc accepted yes yes yes priority higher than that of interrupt currently being serviced? priority higher than that of other interrupt request? highest default priority of interrupt requests with the same priority? eipc eipsw ecr.eicc psw.ep psw.id corresponding bit of ispr note pc restored pc psw exception code 0 1 1 handler address note for the ispr register, see 7.3.7 in-service prio rity register (ispr) . the int input masked by the interrupt controllers and the int input that o ccurs while another interrupt is being serviced (when psw.np = 1 or psw.id = 1) are held pending internally by the interrupt controller. in such case, if the interrupts are unmasked, or when psw.np = 0 and psw.id = 0 as set by the reti and ldsr instructions, input of the pending int starts the new ma skable interrupt servicing. chapter 7 interrupt/exception processing function 312 user?s manual u16031ej3v0ud 7.3.2 restore recovery from maskable interrupt servicing is carried out by the reti instruction. when the reti instruction is execut ed, the cpu performs the following steps , and transfers control to the address of the restored pc. <1> restores the values of the pc and the psw from eipc and eipsw bec ause the ep bit of the psw is 0 and the np bit of the psw is 0. <2> transfers control to the address of the restored pc and psw. figure 7-5 illustrates the processi ng of the reti instruction. figure 7-5. reti instruction processing psw.ep reti instruction psw.np restores original processing 1 1 0 0 pc psw corresponding bit of ispr note eipc eipsw 0 pc psw fepc fepsw note for the ispr register, see 7.3.7 in-service prio rity register (ispr) . caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during maskable interrupt servicing, in order to rest ore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 0 and psw.np back to 0 using the ldsr instruction immediately before the reti instruction. remark the solid line shows the cpu processing flow. chapter 7 interrupt/exception processing function 313 user?s manual u16031ej3v0ud 7.3.3 priorities of maskable interrupts the v850e/me2 provides multiple inte rrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. multiple interrupts can be controlled by priority levels. there are two types of priority leve l control: control based on the default priority leve ls, and control based on the programmable priority levels that are spec ified by the interrupt priority level s pecification bit (xxprn ) of the interrupt control register (xxicn). when two or more interrupts having the same priority level specified by the xxprn bit are generated at the same time, interrupts ar e serviced in order depending on the priority level allocated to each interrupt request type (default priority level) beforehand. for more information, see table 7-1 interrupt/exception source list . the programmable priority control cu stomizes interrupt requests into eight levels by setting the priority level specification flag. note that when an interrupt request is a cknowledged, the id flag of psw is automat ically set to 1. therefore, when multiple interrupts are to be used, clear the id flag to 0 beforehand (for example, by placing t he ei instruction in the interrupt service program) to set the interrupt enable mode. remark xx: identification name of each peripheral unit (see table 7-2 ) n: peripheral unit number (see table 7-2 ) chapter 7 interrupt/exception processing function 314 user?s manual u16031ej3v0ud figure 7-6. example of processing in which anot her interrupt request is issued while an interrupt is bei ng serviced (1/2) main routine ei ei interrupt request a (level 3) servicing of a servicing of b servicing of c interrupt request c (level 3) servicing of d servicing of e ei interrupt request e (level 2) servicing of f ei servicing of g interrupt request g (level 1) interrupt request h (level 1) servicing of h interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. interrupt request b (level 2) interrupt request d (level 2) interrupt request f (level 3) caution to perform multiple interrupt servicing, the values of the eipc and ei psw registers must be saved before executing the ei instru ction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. remarks 1. a to u in the figure are pseudo interrupt reques t names shown for the sake of explanation. 2. the default priority in the figure indicates the relative priority between two interrupt requests. chapter 7 interrupt/exception processing function 315 user?s manual u16031ej3v0ud figure 7-6. example of processing in which anot her interrupt request is issued while an interrupt is bei ng serviced (2/2) main routine ei interrupt request i (level 2) servicing of i servicing of k interrupt request j (level 3) servicing of j interrupt request l (level 2) ei ei ei interrupt request o (level 3) interrupt request s (level 1) interrupt request k (level 1) servicing of l servicing of n servicing of m servicing of s servicing of u servicing of t interrupt request m (level 3) interrupt request n (level 1) servicing of o interrupt request p (level 2) interrupt request q (level 1) interrupt request r (level 0) interrupt request u (level 2) note 2 interrupt request t (level 2) note 1 servicing of p servicing of q servicing of r ei if levels 3 to 0 are acknowledged interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. pending interrupt requests are acknowledged after servicing of interrupt request l. at this time, interrupt request n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. pending interrupt requests t and u are acknowledged after servicing of s. because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. caution to perform multiple interrupt servicing, the values of the eipc and ei psw registers must be saved before executing the ei instru ction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. notes 1. lower default priority 2. higher default priority chapter 7 interrupt/exception processing function 316 user?s manual u16031ej3v0ud figure 7-7. example of servicing inte rrupt requests simult aneously generated default priority a > b > c main routine ei interrupt request a (level 2) interrupt request b (level 1) interrupt request c (level 1) servicing of interrupt request b . . servicing of interrupt request c servicing of interrupt request a interrupt request b and c are acknowledged first according to their priorities. because the priorities of b and c are the same, b is acknowledged first according to the default priority. caution to perform multiple interrupt servicing, the values of the eipc and ei psw registers must be saved before executing the ei instru ction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. remark a to c in the figure are pseudo interrupt reques t names shown for the sake of explanation. chapter 7 interrupt/exception processing function 317 user?s manual u16031ej3v0ud 7.3.4 interrupt control register (xxicn) an interrupt control register is assigned to each in terrupt request (maskable inte rrupt) and sets the control conditions for each maskable interrupt request. this register can be read or written in 8-bit or 1-bit units. caution disable interrupts (di) to read the xxifn bit of the xxicn register. if the xxifn bit is read while interrupts are enabled (ei), the correct value m ay not be read if there is a conflict between acknowledging an interrupt and reading the bit. xxifn xxicn xxmkn 5 0 4 0 3 0 2 xxprn2 1 xxprn1 0 xxprn0 address fffff110h to fffff1c2h after reset 47h <6> <7> bit position bit name function 7 xxifn this is an interrupt request flag. 0: interrupt request not issued 1: interrupt request issued the flag xxlfn is reset automatically by the hardware if an interrupt request is acknowledged. 6 xxmkn this is an interrupt mask flag. 0: interrupt servicing enabled 1: interrupt servicing disabled (pending) 8 levels of priority order ar e specified for each interrupt. xxprn2 xxprn1 xxprn0 interrupt priority specification bit 0 0 0 specifies level 0 (highest). 0 0 1 specifies level 1. 0 1 0 specifies level 2. 0 1 1 specifies level 3. 1 0 0 specifies level 4. 1 0 1 specifies level 5. 1 1 0 specifies level 6. 1 1 1 specifies level 7 (lowest). 2 to 0 xxprn2 to xxprn0 remark xx: identification name of each peripheral unit (see table 7-2 ) n: peripheral unit number (see table 7-2 ) the addresses and bits of the interrupt control registers are as follows: chapter 7 interrupt/exception processing function 318 user?s manual u16031ej3v0ud table 7-2. addresses and bits of interrupt control registers (1/3) bit address register <7> <6> 5 4 3 2 1 0 fffff110h p1ic0 p1if0 p1mk0 0 0 0 p1pr02 p1pr01 p1pr00 fffff112h p1ic1 p1if1 p1mk1 0 0 0 p1pr12 p1pr11 p1pr10 fffff114h p2ic1 p2if1 p2mk1 0 0 0 p2pr12 p2pr11 p2pr10 fffff116h p2ic2 p2if2 p2mk2 0 0 0 p2pr22 p2pr21 p2pr20 fffff118h p2ic3 p2if3 p2mk3 0 0 0 p2pr32 p2pr31 p2pr30 fffff11ah p2ic4 p2if4 p2mk4 0 0 0 p2pr42 p2pr41 p2pr40 fffff11ch p2ic5 p2if5 p2mk5 0 0 0 p2pr52 p2pr51 p2pr50 fffff11eh p5ic0 p5if0 p5mk0 0 0 0 p5pr02 p5pr01 p5pr00 fffff120h p5ic1 p5if1 p5mk1 0 0 0 p5pr12 p5pr11 p5pr10 fffff122h p5ic2 p5if2 p5mk2 0 0 0 p5pr22 p5pr21 p5pr20 fffff124h p6ic5 p6if5 p6mk5 0 0 0 p6pr52 p6pr51 p6pr50 fffff126h p6ic6 p6if6 p6mk6 0 0 0 p6pr62 p6pr61 p6pr60 fffff128h p6ic7 p6if7 p6mk7 0 0 0 p6pr72 p6pr71 p6pr70 fffff12ah pdic0 pdif0 pdmk0 0 0 0 pdpr02 pdpr01 pdpr00 fffff12ch pdic1 pdif1 pdmk1 0 0 0 pdpr12 pdpr11 pdpr10 fffff12eh pdic2 pdif2 pdmk2 0 0 0 pdpr22 pdpr21 pdpr20 fffff130h pdic3 pdif3 pdmk3 0 0 0 pdpr32 pdpr31 pdpr30 fffff132h pdic4 pdif4 pdmk4 0 0 0 pdpr42 pdpr41 pdpr40 fffff134h pdic5 pdif5 pdmk5 0 0 0 pdpr52 pdpr51 pdpr50 fffff136h pdic6 pdif6 pdmk6 0 0 0 pdpr62 pdpr61 pdpr60 fffff138h pdic7 pdif7 pdmk7 0 0 0 pdpr72 pdpr71 pdpr70 fffff13ah pdic8 pdif8 pdmk8 0 0 0 pdpr82 pdpr81 pdpr80 fffff13ch pdic9 pdif9 pdmk9 0 0 0 pdpr92 pdpr91 pdpr90 fffff13eh pdic10 pdif10 pdmk10 0 0 0 pdpr102 pdpr101 pdpr100 fffff140h pdic11 pdif11 pdmk11 0 0 0 pdpr112 pdpr111 pdpr110 fffff142h pdic12 pdif12 pdmk12 0 0 0 pdpr122 pdpr121 pdpr120 fffff144h pdic13 pdif13 pdmk13 0 0 0 pdpr132 pdpr131 pdpr130 fffff146h pdic14 pdif14 pdmk14 0 0 0 pdpr142 pdpr141 pdpr140 fffff148h pdic15 pdif15 pdmk15 0 0 0 pdpr152 pdpr151 pdpr150 fffff14ah plic0 plif0 plmk0 0 0 0 plpr02 plpr01 plpr00 fffff14ch plic1 plif1 plmk1 0 0 0 plpr12 plpr11 plpr10 fffff14eh ovcic0 ovcif0 ovcmk0 0 0 0 ovcpr02 ovcpr01 ovcpr00 fffff150h ovcic1 ovcif1 ovcmk1 0 0 0 ovcpr12 ovcpr11 ovcpr10 fffff152h ovcic2 ovcif2 ovcmk2 0 0 0 ovcpr22 ovcpr21 ovcpr20 fffff154h ovcic3 ovcif3 ovcmk3 0 0 0 ovcpr32 ovcpr31 ovcpr30 fffff156h ovcic4 ovcif4 ovcmk4 0 0 0 ovcpr42 ovcpr41 ovcpr40 fffff158h ovcic5 ovcif5 ovcmk5 0 0 0 ovcpr52 ovcpr51 ovcpr50 fffff15ah ccc0ic0 ccc0if0 ccc0mk0 0 0 0 ccc0pr02 ccc0pr01 ccc0pr00 fffff15ch ccc0ic1 ccc0if1 ccc0mk1 0 0 0 ccc0pr12 ccc0pr11 ccc0pr10 fffff15eh ccc1ic0 ccc1if0 ccc1mk0 0 0 0 ccc1pr02 ccc1pr01 ccc1pr00 fffff160h ccc1ic1 ccc1if1 ccc1mk1 0 0 0 ccc1pr12 ccc1pr11 ccc1pr10 chapter 7 interrupt/exception processing function 319 user?s manual u16031ej3v0ud table 7-2. addresses and bits of interrupt control registers (2/3) bit address register <7> <6> 5 4 3 2 1 0 fffff162h ccc2ic0 ccc2if0 ccc2mk0 0 0 0 ccc2pr02 ccc2pr01 ccc2pr00 fffff164h ccc2ic1 ccc2if1 ccc2mk1 0 0 0 ccc2pr12 ccc2pr11 ccc2pr10 fffff166h ccc3ic0 ccc3if0 ccc3mk0 0 0 0 ccc3pr02 ccc3pr01 ccc3pr00 fffff168h ccc3ic1 ccc3if1 ccc3mk1 0 0 0 ccc3pr12 ccc3pr11 ccc3pr10 fffff16ah ccc4ic0 ccc4if0 ccc4mk0 0 0 0 ccc4pr02 ccc4pr01 ccc4pr00 fffff16ch ccc4ic1 ccc4if1 ccc4mk1 0 0 0 ccc4pr12 ccc4pr11 ccc4pr10 fffff16eh ccc5ic0 ccc5if0 ccc5mk0 0 0 0 ccc5pr02 ccc5pr01 ccc5pr00 fffff170h ccc5ic1 ccc5if1 ccc5mk1 0 0 0 ccc5pr12 ccc5pr11 ccc5pr10 fffff172h cmdic0 cmdif0 cmdmk0 0 0 0 cmdpr02 cmdpr01 cmdpr00 fffff174h cmdic1 cmdif1 cmdmk1 0 0 0 cmdpr12 cmdpr11 cmdpr10 fffff176h cmdic2 cmdif2 cmdmk2 0 0 0 cmdpr22 cmdpr21 cmdpr20 fffff178h cmdic3 cmdif3 cmdmk3 0 0 0 cmdpr32 cmdpr31 cmdpr30 fffff17ah cc10ic0 cc10if0 cc10mk0 0 0 0 cc10pr02 cc10pr01 cc10pr00 fffff17ch cc10ic1 cc10if1 cc10mk1 0 0 0 cc10pr12 cc10pr11 cc10pr10 fffff17eh cm10ic0 cm10if0 cm10mk0 0 0 0 cm10pr02 cm10pr01 cm10pr00 fffff180h cm10ic1 cm10if1 cm10mk1 0 0 0 cm10pr12 cm10pr11 cm10pr10 fffff182h ov1ic0 ov1if0 ov1mk0 0 0 0 ov1pr02 ov1pr01 ov1pr00 fffff184h ud1ic0 ud1if0 ud1mk0 0 0 0 ud1pr02 ud1pr01 ud1pr00 fffff186h cc11ic0 cc11if0 cc11mk0 0 0 0 cc11pr02 cc11pr01 cc11pr00 fffff188h cc11ic1 cc11if1 cc11mk1 0 0 0 cc11pr12 cc11pr11 cc11pr10 fffff18ah cm11ic0 cm11if0 cm11mk0 0 0 0 cm11pr02 cm11pr01 cm11pr00 fffff18ch cm11ic1 cm11if1 cm11mk1 0 0 0 cm11pr12 cm11pr11 cm11pr10 fffff18eh ov1ic1 ov1if1 ov1mk1 0 0 0 ov1pr12 ov1pr11 ov1pr10 fffff190h ud1ic1 ud1if1 ud1mk1 0 0 0 ud1pr12 ud1pr11 ud1pr10 fffff192h dmaic0 dmaif0 dmamk0 0 0 0 dmapr02 dmapr01 dmapr00 fffff194h dmaic1 dmaif1 dmamk1 0 0 0 dmapr12 dmapr11 dmapr10 fffff196h dmaic2 dmaif2 dmamk2 0 0 0 dmapr22 dmapr21 dmapr20 fffff198h dmaic3 dmaif3 dmamk3 0 0 0 dmapr32 dmapr31 dmapr30 fffff19ah csi3ic0 csi3if0 csi3mk0 0 0 0 csi3pr02 csi3pr01 csi3pr00 fffff19ch covf3ic0 covf3if0 covf3mk0 0 0 0 covf3pr0 2 covf3pr0 1 covf3pr00 fffff19eh csi3ic1 csi3if1 csi3mk1 0 0 0 csi3pr12 csi3pr11 csi3pr10 fffff1a0h covf3ic1 covf3if1 covf3mk1 0 0 0 covf3pr1 2 covf3pr1 1 covf3pr10 fffff1a2h ureic0 ureif0 uremk0 0 0 0 urepr02 urepr01 urepr00 fffff1a4h uric0 urif0 urmk0 0 0 0 urpr02 urpr01 urpr00 fffff1a6h utic0 utif0 utmk0 0 0 0 utpr02 utpr01 utpr00 fffff1a8h uific0 uifif0 uifmk0 0 0 0 uifpr02 uifpr01 uifpr00 fffff1aah utoic0 utoif0 utomk0 0 0 0 utopr02 utopr01 utopr00 fffff1ach ureic1 ureif1 uremk1 0 0 0 urepr12 urepr11 urepr10 fffff1aeh uric1 urif1 urmk1 0 0 0 urpr12 urpr11 urpr10 fffff1b0h utic1 utif1 utmk1 0 0 0 utpr12 utpr11 utpr10 fffff1b2h uific1 uifif1 uifmk1 0 0 0 uifpr12 uifpr11 uifpr10 chapter 7 interrupt/exception processing function 320 user?s manual u16031ej3v0ud table 7-2. addresses and bits of interrupt control registers (3/3) bit address register <7> <6> 5 4 3 2 1 0 fffff1b4h utoic1 utoif1 utomk1 0 0 0 utopr12 utopr11 utopr10 fffff1b6h adic adif admk 0 0 0 adpr2 adpr1 adpr0 fffff1b8h us0bic us0bif us0bmk 0 0 0 us0bpr2 us0bpr1 us0bpr0 fffff1bah us1bic us1bif us1bmk 0 0 0 us1bpr2 us1bpr1 us1bpr0 fffff1bch us2bic us2bif us2bmk 0 0 0 us2bpr2 us2bpr1 us2bpr0 fffff1beh usp2ic usp2if usp2mk 0 0 0 usp2pr2 usp2pr1 usp2pr0 fffff1c0h usp4ic usp4if usp4mk 0 0 0 usp4pr2 usp4pr1 usp4pr0 fffff1c2h rsumic rsumif rsummk 0 0 0 rsumpr2 rsumpr1 rsumpr0 7.3.5 interrupt mask register s 0 to 5 (imr0 to imr5) these registers set the interrupt mask state for the maskable interrupts. t he xxmkn bit of the imr0 to imr5 registers is equivalent to the xxm kn bit of the xxicn register. the imrm register (m = 0 to 5) c an be read or written in 16-bit units. if the higher 8 bits of the imrm regist er are used as an imrmh register and t he lower 8 bits as an imrml register, these registers can be read or wri tten in 8-bit or 1-bit units. bits 15 to 10 of the imr5 register (bit s 7 to 2 of the imr5h register) are fix ed to 1. if these bits are not 1, the operation cannot be guaranteed. caution the device file defines the xxmkn bit of th e xxicn register as a reser ved word. if a bit is manipulated using the name of xxmkn, the contents of the xxicn register , instead of the imrm register, are rewritten (as a result, the contents of the imrm register are also rewritten). chapter 7 interrupt/exception processing function 321 user?s manual u16031ej3v0ud pdmk2 p5mk0 imr0 pdmk1 p2mk5 pdmk0 p2mk4 p6mk7 p2mk3 p6mk6 p2mk2 p6mk5 p2mk1 p5mk2 p1mk1 p5mk1 p1mk0 address fffff100h after reset ffffh ovcmk0 pdmk10 imr1 plmk1 pdmk9 plmk0 pdmk8 pdmk15 pdmk7 pdmk14 pdmk6 pdmk13 pdmk5 pdmk12 pdmk4 pdmk11 pdmk3 address fffff102h after reset ffffh 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 ccc5mk0 ccc1mk0 imr2 ccc4mk1 ccc0mk1 ccc4mk0 ccc0mk0 ccc3mk1 ovcmk5 ccc3mk0 ovcmk4 ccc2mk1 ovcmk3 ccc2mk0 ovcmk2 ccc1mk1 ovcmk1 address fffff104h after reset ffffh 15 ov1mk1 7 cm10mk0 imr3 14 cm11mk1 6 cc10mk1 13 cm11mk0 5 cc10mk0 12 cc11mk1 4 cmdmk3 11 cc11mk0 3 cmdmk2 10 ud1mk0 2 cmdmk1 9 ov1mk0 1 cmdmk0 8 cm10mk1 ccc5mk1 address fffff106h after reset ffffh 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 0 urmk1 csi3mk1 imr4 uremk1 covf3mk0 utomk0 csi3mk0 uifmk0 dmamk3 utmk0 dmamk2 urmk0 dmamk1 uremk0 dmamk0 covf3mk1 ud1mk1 address fffff108h after reset ffffh 15 1 7 usp2mk imr5 14 1 6 us2bmk 13 1 5 us1bmk 12 1 4 us0bmk 11 1 3 admk 10 1 2 utomk1 9 rsummk 1 uifmk1 8 usp4mk utmk1 address fffff10ah after reset ffffh 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 0 bit position bit name function 15 to 0 xxmkn interrupt mask flag 0: interrupt servicing enabled 1: interrupt servicing disabled (pending) remark xx: identification name of each peripheral unit (see table 7-2 ) n: peripheral unit number (see table 7-2 ) chapter 7 interrupt/exception processing function 322 user?s manual u16031ej3v0ud 7.3.6 nmi reset status register (nrs) this register holds the valid edge input status of the nmi afte r the reset signal has been cleared. this register is read-only, in 8-bit or 1-bit units. cautions 1. the nmirs bit of the nrs register is set to 1 if an nmi occurs a fter the internal instruction ram has been set in th e read mode (iramm0 bit of iramm register = 0). in this case, the status of the nmirs bit does not have to be checked because execu tion automatically branches to the nmi servicing routine. 2. the mask function of nmi input is valid a fter the reset signal has b een cleared and before the internal instruction ram is set in the r ead mode (iramm0 bit of iramm register = 0). 0 0 0 0 0 0 0 nmirs 76543210 nrs address fffff80ch after reset 00h bit position bit name function 0 nmirs indicates the valid edge input status of nmi. 0: no nmi input 1: nmi input with the v850e/me2, the nmi is masked after the reset si gnal has been cleared. it is unm asked if the mode of the internal instruction ram is changed fr om the write mode (iramm0 bit of ir amm register = 1) to the read mode (iramm0 bit of iramm register = 0) after the program has been downloaded to internal in struction ram bank 0. (the nrs register is controlled to prohibit a jump to the interrupt vector before the program is stored in the interrupt vector table.) if the nmi valid edge is input while the nmi is masked, the nmi input can be rec ognized by reading the nrs register. chapter 7 interrupt/exception processing function 323 user?s manual u16031ej3v0ud 7.3.7 in-service priori ty register (ispr) this register holds the priority leve l of the maskable interrupt currently a cknowledged. when an interrupt request is acknowledged, the bit of this register co rresponding to the priority level of that interrupt request is set to 1 and remains set while the interrupt is serviced. when the reti instruction is executed, the bit corresponding to the inte rrupt request having the highest priority is automatically reset to 0 by hardware. however, it is not reset to 0 when execution is returned from non-maskable interrupt servicing or exception processing. this register is read-only, in 8-bit or 1-bit units. caution if an interrupt is acknowledge d while the ispr register is being read in the interrupt enabled (ei) status, the value of the ispr register after th e bits of the register have been set to 1 by acknowledging the interrupt may be read. to accura tely read the value of the ispr register before an interrupt is acknowledged, read the register while interrupts are disabled (di status). ispr7 ispr ispr6 ispr5 ispr4 ispr3 ispr2 ispr1 ispr0 address fffff1fah after reset 00h <1> <2> <3> <4> <5> <6> <7> <0> bit position bit name function 7 to 0 ispr7 to ispr0 indicates priority of interrupt currently acknowledged 0: interrupt request with priority n not acknowledged 1: interrupt request with priority n acknowledged remark n = 0 to 7 (priority level) 7.3.8 maskable interrupt status flag (id) the id flag is bit 5 of the psw and c ontrols the maskable interr upt?s operating state, and st ores control information regarding enabling or disabling of interrupt requests. 31 0 psw after reset 00000020h 7 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit position bit name function 5 id indicates whether maskable interrupt servicing is enabled or disabled. 0: maskable interrupt request acknowledgment enabled 1: maskable interrupt request acknowledgment disabled (pending) this bit is set to 1 by the di instruction and reset to 0 by the ei instruction. its value is also modified by the reti instruction or ldsr instruction when referencing the psw. non-maskable interrupt requests and excepti ons are acknowledged regardless of this flag. when a maskable interrupt is acknowledged, the id flag is automatically set to 1 by hardware. the interrupt request generated during the acknowledgment disabled period (id = 1) is acknowledged when the xxifn bit of xxicn is set to 1, and the id flag is reset to 0. chapter 7 interrupt/exception processing function 324 user?s manual u16031ej3v0ud 7.3.9 selecting interrupt trigger mode the valid edge of the intpn, intpcm, tic0 to tic3, intpx, tiud10, tiud11, t cud10, tcud11, tclr10, and tclr11 pins can be selected by program (n = 10, 11, 21 to 25, 50 to 52, 65 to 67, l0, l1, or d0 to d15, m = 00, 01, 10, 11, 20, 21, 30, or 31, x = 100, 101, 110, or 111). a trigger level can also be selected for the intpn pin. the following valid edges can be selected. ? rising edge ? falling edge ? both rising and falling edges the intpn, intpcm, tic0 to tic3, intpx, tiud10, tiud11, tcud10, tcud11, tclr10, and tclr11 signals detected by the edge are us ed as interrupt sources, to input a capture tr igger, or to input an external count signal to the timers. the valid edge of these signals is specified by external interrupt rising edge specification register s 1, 2, 5, 6, al, and dh (intr1, intr2, intr5, intr6, intral, and intrdh), external interrupt falling edge specification registers 1, 2, 5, 6, al, and dh (intf1, intf2 , intf5, intf6, intfal, and intfdh), valid edge select registers c0 to c3 (sesc0 to sesc3), and valid edge select registers 10 and 11 (sesa10 and sesa11). the trigger level is specified by external interrupt rising edge specific ation registers 1, 2, 5, 6, al, and dh (intr1, intr2, intr5, intr6, intral, and intrdh) and external interrupt falli ng edge specification regist ers 1, 2, 5, 6, al, and dh (intf1, intf2, intf5, intf6, intfal, and intfdh). (1) external interrupt rising e dge specification register 1 (intr1 ), external interrupt falling edge specification register 1 (intf1) these registers are used to specify the trigger mode of the external in terrupt requests (intp10 and intp11) input from external pins. the co rrespondence between each bit of this r egister and the external interrupt request controlled by that bit is as follows. ? intf10 and intr10 bits: intp10 ? intf11 and intr11 bits: intp11 the rising edge, falling edge, or both the rising and falling edges can be i ndependently specified as the valid edge. each of these registers can be read or written in 8-bit or 1-bit units. caution set the pmc1 register before setting the trigger mode of the intp10 and intp11 pins. if the pmc1 register is set after the intr 1 and intf1 registers have been set, an illegal interrupt may occur when th e pmc1 register is set. chapter 7 interrupt/exception processing function 325 user?s manual u16031ej3v0ud 7 0 intr1 6 0 5 0 4 0 3 0 2 0 1 intr11 0 intr10 address fffffc22h after reset 03h 0 intf1 00000 intf11 intf10 fffffc02h 00h bit position bit name function specify the trigger mode of the intp10 and intp11 pins. intf1n intr1n operation 0 0 falling edge 0 1 rising edge 1 0 level detection (low-level detection) notes 1, 2 1 1 both rising and falling edges 1, 0 intf1n, intr1n (n = 0, 1) notes 1. the level of the intp1n pin is sampled each time the main clock (f x ) is divided by four. when the low level of this pin is detect ed, an interrupt request is latched as the p1ifn bit (n = 0, 1). consequently, even when the cpu ack nowledges the interrupt and the p1ifn bit of the interrupt control register (p1icn) is autom atically cleared to 0, the p1ifn bit is immediately set to 1 and interrupts occur consecutively. to avoid this st atus, make the intp1n pin of the external device inactive in the interrupt servicing routi ne, and forcibly clear the p1ifn bit to 0. 2. if a level-detected interrupt reques t (intp1n) with a lower priority occurs while an interrupt is being serviced and if this level-detect ed interrupt request (intp1n) t hat has newly occurred becomes inactive before the current inte rrupt has been serviced, the interr upt request of the new interrupt (intp1n) is held pending (n = 0, 1). to not ack nowledge the interrupt reques t of intp1n, clear the p1ifn bit of the interrupt control register. chapter 7 interrupt/exception processing function 326 user?s manual u16031ej3v0ud (2) external interrupt rising edge specification register 2 (intr2), external interrupt falling edge specification register 2 (intf2) these registers are used to specify t he trigger mode of the external inte rrupt requests (intp2n) input from external pins and the non-maskable interrupt (nmi) (n = 1 to 5). for the trigger mode of the nmi, see 7.2.4 (1) external interrupt rising e dge specification register 2 (intr2 ), external interrupt falling edge specification register 2 (intf2) . the correspondence between each bit and t he external interrupt request and non-maskable interrupt that are controlled by that bit is as follows. ? ? ? ? ? chapter 7 interrupt/exception processing function 327 user?s manual u16031ej3v0ud 7 0 intr2 6 0 5 intr25 4 intr24 3 intr23 2 intr22 1 intr21 0 nmir0 address fffffc24h after reset 3fh 0 intf2 0 intf25 intf24 intf23 intf22 intf21 nmif0 fffffc04h 00h bit position bit name function specify the trigger mode of the intp2n pin. intf2n intr2n operation 0 0 falling edge 0 1 rising edge 1 0 level detection (low-level detection) notes 1, 2 1 1 both rising and falling edges 5 to 1 intf2n, intr2n (n = 1 to 5) notes 1. the level of the intp2n pin is sampled each time the main clock (f x ) is divided by four. when the low level of this pin is detect ed, an interrupt request is latched as the p2ifn bit (n = 1 to 5). consequently, even when the cpu ack nowledges the interrupt and the p2ifn bit of the interrupt control register (p2icn) is autom atically cleared to 0, the p2ifn bit is immediately set to 1 and interrupts occur consecutively. to avoid this st atus, make the intp2n pin of the external device inactive in the interrupt servicing routi ne, and forcibly clear the p2ifn bit to 0. 2. if a level-detected interrupt reques t (intp2n) with a lower priority occurs while an interrupt is being serviced and if this level-detect ed interrupt request (intp2n) t hat has newly occurred becomes inactive before the current inte rrupt has been serviced, the interr upt request of the new interrupt (intp2n) is held pending (n = 1 to 5). to not acknowledge the interrupt request of intp2n, clear the p2ifn bit of the inte rrupt control register. remark for the bit 0 (nmir0) of the intr2 register and bit 0 (nmif0) of the intf2 register, see 7.2.4 (1) external interrupt rising edge specification regi ster 2 (intr2), externa l interrupt falling edge specification register 2 (intf2) . chapter 7 interrupt/exception processing function 328 user?s manual u16031ej3v0ud (3) external interrupt rising edge specification register 5 (intr5), external interrupt falling edge specification register 5 (intf5) these registers are used to specify t he trigger mode of the external inte rrupt requests (intp5n) input from external pins (n = 0 to 2). the correspondence between each bit of this register and the external interrupt request controlled by that bit is as follows. ? intf50 and intr50 bits: intp50 ? intf51 and intr51 bits: intp51 ? intf52 and intr52 bits: intp52 the rising edge, falling edge, or both the rising and falling edges can be i ndependently specified as the valid edge. each of these registers can be read or written in 8-bit or 1-bit units. caution set the pmc5 register before setting the trigger mode. if the pmc5 register is set after the intr 5 and intf5 registers have been set, an illegal interrupt may occur when th e pmc5 register is set. chapter 7 interrupt/exception processing function 329 user?s manual u16031ej3v0ud 7 0 intr5 6 0 5 0 4 0 3 0 2 intr52 1 intr51 0 intr50 address fffffc2ah after reset 07h 0 intf5 0000 intf52 intf51 intf50 fffffc0ah 00h bit position bit name function specify the trigger mode of the intp5n pin. intf5n intr5n operation 0 0 falling edge 0 1 rising edge 1 0 level detection (low-level detection) notes 1, 2 1 1 both rising and falling edges 2 to 0 intf5n, intr5n (n = 0 to 2) notes 1. the level of the intp5n pin is sampled each time the main clock (f x ) is divided by four. when the low level of this pin is detect ed, an interrupt request is latched as the p5ifn bit (n = 0 to 2). consequently, even when the cpu ack nowledges the interrupt and the p5ifn bit of the interrupt control register (p5icn) is autom atically cleared to 0, the p5ifn bit is immediately set to 1 and interrupts occur consecutively. to avoid this st atus, make the intp5n pin of the external device inactive in the interrupt servicing routi ne, and forcibly clear the p5ifn bit to 0. 2. if a level-detected interrupt reques t (intp5n) with a lower priority occurs while an interrupt is being serviced and if this level-detect ed interrupt request (intp5n) t hat has newly occurred becomes inactive before the current inte rrupt has been serviced, the interr upt request of the new interrupt (intp5n) is held pending (n = 0 to 2). to not acknowledge the interrupt request of intp5n, clear the p5ifn bit of the inte rrupt control register. chapter 7 interrupt/exception processing function 330 user?s manual u16031ej3v0ud (4) external interrupt rising edge specification register 6 (intr6), external interrupt falling edge specification register 6 (intf6) these registers are used to specify t he trigger mode of the external inte rrupt requests (intp6n) input from external pins (n = 5 to 7). the correspondence between each bit of this register and the external interrupt request controlled by that bit is as follows. ? intf65 and intr65 bits: intp65 ? intf66 and intr66 bits: intp66 ? intf67 and intr67 bits: intp67 the rising edge, falling edge, or both the rising and falling edges can be i ndependently specified as the valid edge. each of these registers can be read or written in 8-bit or 1-bit units. caution set the pmc6 register before setting the trigger mode. if the pmc6 register is set after the intr 6 and intf6 registers have been set, an illegal interrupt may occur when th e pmc6 register is set. chapter 7 interrupt/exception processing function 331 user?s manual u16031ej3v0ud 7 intr67 intr6 6 intr66 5 intr65 4 0 3 0 2 0 1 0 0 0 address fffffc2ch after reset e0h intf67 intf6 intf66 intf65 00000 fffffc0ch 00h bit position bit name function specify the trigger mode of the intp6n pin. intf6n intr6n operation 0 0 falling edge 0 1 rising edge 1 0 level detection (low-level detection) notes 1, 2 1 1 both rising and falling edges 7 to 5 intf6n, intr6n (n = 7 to 5) notes 1. the level of the intp6n pin is sampled each time the main clock (f x ) is divided by four. when the low level of this pin is detect ed, an interrupt request is latched as the p6ifn bit (n = 5 to 7). consequently, even when the cpu ack nowledges the interrupt and the p6ifn bit of the interrupt control register (p6icn) is autom atically cleared to 0, the p6ifn bit is immediately set to 1 and interrupts occur consecutively. to avoid this st atus, make the intp6n pin of the external device inactive in the interrupt servicing routi ne, and forcibly clear the p6ifn bit to 0. 2. if a level-detected interrupt reques t (intp6n) with a lower priority occurs while an interrupt is being serviced and if this level-detect ed interrupt request (intp6n) t hat has newly occurred becomes inactive before the current inte rrupt has been serviced, the interr upt request of the new interrupt (intp6n) is held pending (n = 5 to 7). to not acknowledge the interrupt request of intp6n, clear the p6ifn bit of the inte rrupt control register. chapter 7 interrupt/exception processing function 332 user?s manual u16031ej3v0ud (5) external interrupt rising edge specification register al (intral), external interrupt falling edge specification register al (intfal) these registers are used to specify t he trigger mode of the external inte rrupt requests (intpln) input from external pins (n = 0, 1). the correspondence between each bit of this r egister and the external interrupt request controlled by that bit is as follows. ? intfal0 and intral0 bits: intpl0 ? intfal1 and intral1 bits: intpl1 the rising edge, falling edge, or both the rising and falling edges can be i ndependently specified as the valid edge. each of these registers can be read or written in 8-bit or 1-bit units. caution set the pmcal register before setting the trigger mode. if the pmcal register is set after the int ral and intfal registers have been set, an illegal interrupt may occur when th e pmcal register is set. 7 0 intral 6 0 5 0 4 0 3 0 2 0 1 intral1 0 intral0 address fffffc30h after reset 03h 0 intfal 00000 intfal1 intfal0 fffffc10h 00h bit position bit name function specify the trigger mode of the intpln pin. intfaln intraln operation 0 0 falling edge 0 1 rising edge 1 0 level detection (low-level detection) notes 1, 2 1 1 both rising and falling edges 1, 0 intfaln, intraln (n = 0, 1) notes 1. the level of the intpln pin is sampled each time the main clock (f x ) is divided by four. when the low level of this pin is detect ed, an interrupt request is latched as the plifn bit (n = 0, 1). consequently, even when the cpu ack nowledges the interrupt and the plifn bit of the interrupt control register (plicn) is autom atically cleared to 0, the plifn bit is immediately set to 1 and interrupts occur consecutively. to avoid this st atus, make the intpln pin of the external device inactive in the interrupt servicing routi ne, and forcibly clear the plifn bit to 0. 2. if a level-detected interrupt reques t (intpln) with a lower priority occurs while an interrupt is being serviced and if this level-detect ed interrupt request (intpln) t hat has newly occurred becomes inactive before the current inte rrupt has been serviced, the interr upt request of the new interrupt (intpln) is held pending (n = 0, 1). to not ack nowledge the interrupt reques t of intpln, clear the plifn bit of the interrupt control register. chapter 7 interrupt/exception processing function 333 user?s manual u16031ej3v0ud (6) external interrupt rising edge specification register dh (intrdh) , external interr upt falling edge specification register dh (intfdh) these registers are used to specify t he trigger mode of the external inte rrupt requests (intpdn) input from external pins (n = 0 to 15). the correspondence between each bit of this register and the external interrupt request controlled by that bit is as follows. ? intfdh0 and intrdh0 bits: intpd0 ? intfdh8 and intrdh8 bits: intpd8 ? intfdh1 and intrdh1 bits: intpd1 ? intfdh9 and intrdh9 bits: intpd9 ? intfdh2 and intrdh2 bits: intpd2 ? intfdh10 and intrdh10 bits: intpd10 ? intfdh3 and intrdh3 bits: intpd3 ? intfdh11 and intrdh11 bits: intpd11 ? intfdh4 and intrdh4 bits: intpd4 ? intfdh12 and intrdh12 bits: intpd12 ? intfdh5 and intrdh5 bits: intpd5 ? intfdh13 and intrdh13 bits: intpd13 ? intfdh6 and intrdh6 bits: intpd6 ? intfdh14 and intrdh14 bits: intpd14 ? intfdh7 and intrdh7 bits: intpd7 ? intfdh15 and intrdh15 bits: intpd15 the rising edge, falling edge, or both the rising and falling edges can be i ndependently specified as the valid edge. the intrdh and intfdh registers can be read or written in 16-bit units. if the higher 8 bits of the intrdh and intfdh regist ers are used as the int rdhh and intfdhh registers, and the lower 8 bits as the intrdhl and intfdhl registers, these registers can be read or written in 8-bit or 1-bit units. caution set the pmcdh register be fore setting the trigger mode. if the pmcdh register is set after the int rdh and intfdh registers have been set, an illegal interrupt may occur when the pmcdh register is set. chapter 7 interrupt/exception processing function 334 user?s manual u16031ej3v0ud 14 intr dh14 13 intr dh13 12 intr dh12 2 intr dh2 3 intr dh3 4 intr dh4 5 intr dh5 6 intr dh6 7 intr dh7 8 intr dh8 9 intr dh9 10 intr dh10 11 intr dh11 15 intr dh15 1 intr dh1 0 intr dh0 intrdh address fffffc36h after reset ffffh intf dh14 intf dh13 intf dh12 intf dh2 intf dh3 intf dh4 intf dh5 intf dh6 intf dh7 intf dh8 intf dh9 intf dh10 intf dh11 intf dh15 intf dh1 intf dh0 intfdh fffffc16h 0000h bit position bit name function specify the trigger mode of the intpdn pin. intfdhn intrdhn operation 0 0 falling edge 0 1 rising edge 1 0 level detection (low-level detection) notes 1, 2 1 1 both rising and falling edges 15 to 0 intfdhn, intrdhn (n = 0 to 15) notes 1. the level of the intpdn pin is sampled each time the main clock (f x ) is divided by four. when the low level of this pin is detect ed, an interrupt request is latched as the pdifn bit (n = 0 to 15). consequently, even when the cpu ack nowledges the interrupt and the pdifn bit of the interrupt control register (pdicn) is autom atically cleared to 0, the pdifn bit is immediately set to 1 and interrupts occur consecutively. to avoid this st atus, make the intpdn pin of the external device inactive in the interrupt servicing routi ne, and forcibly clear the pdifn bit to 0. 2. if a level-detected interrupt reques t (intpdn) with a lower priority occurs while an interrupt is being serviced and if this level-detect ed interrupt request (intpdn) t hat has newly occurred becomes inactive before the current inte rrupt has been serviced, the interr upt request of the new interrupt (intpdn) is held pending (n = 0 to 15). to not acknowledge the interrupt request of intpdn, clear the pdifn bit of the inte rrupt control register. chapter 7 interrupt/exception processing function 335 user?s manual u16031ej3v0ud (7) valid edge select register s c0 to c3 (sesc0 to sesc3) these registers are used to specify the valid edge of the external inte rrupt requests (intpc00, intpc01, intpc10, intpc11, intpc20, intpc21, intpc30, intpc 31, or tic0 to tic3) input from external pins to tmcn (n = 0 to 3). the rising edge, falling edge, or both the rising and falling edges can be i ndependently specified as the valid edge. each of these registers can be read or written in 8-bit units. be sure to clear bits 5 and 4 to 0. if they are set to 1, the oper ation is not guaranteed. cautions 1. do not change each bit of the sescn re gister while the timer is operating (n = 0 to 3). to change a bit, clear the cecn bit of the tmccn0 register to 0. the operation is not guaranteed if the sescn register is rewritten during timer operation. 2. even when the intpc00/tic0, intpc10/ti c1, intpc20/tic2, and in tpc30/tic3 pins are used as intpc00, intpc10, intpc20, and in tpc30, respectively, without using timer c, be sure to set the caecn and cecn bits of timer mode control registers c00 to c03 (tmcc00 to tmcc30) to 1. 3. set the pmcx register before setting the trigger mode of the intpc00, intpc01, intpc10, intpc11, intpc20, intpc21, intpc30, intpc31, and tic0 to tic3 pins (x = 5 to 7), then set the caecn and cecn bits of the tmccn0 register to 1 (n = 0 to 3). if the pmcx register is set after the sesc n register has been set, an illegal interrupt, incorrect count, or incorrect clear may occur depending on the timing of setting the pmcx register (n = 0 to 3, x = 5 to 7). chapter 7 interrupt/exception processing function 336 user?s manual u16031ej3v0ud 7 tesc01 tic0 sesc0 6 tesc00 5 0 4 0 3 iesc101 2 iesc100 1 iesc001 0 iesc000 address fffff609h after reset 00h intpc01 intpc00 7 tesc11 tic1 sesc1 6 tesc10 5 0 4 0 3 iesc111 2 iesc110 1 iesc011 0 iesc010 address fffff629h after reset 00h intpc11 intpc10 7 tesc21 tic2 sesc2 6 tesc20 5 0 4 0 3 iesc121 2 iesc120 1 iesc021 0 iesc020 address fffff649h after reset 00h intpc21 intpc20 7 tesc31 tic3 sesc3 6 tesc30 5 0 4 0 3 iesc131 2 iesc130 1 iesc031 0 iesc030 address fffff669h after reset 00h intpc31 intpc30 bit position bit name function specify the valid edge of the intpcm0, intpcm1, and ticm pins (m = 0 to 3). 7, 6 tescn1, tescn0 (n = 0 to 3) xescn1 xescn0 operation 0 0 falling edge 0 1 rising edge 3, 2 iescn1, iescn0 (n = 10 to 13) 1 0 setting prohibited 1 1 both rising and falling edges 1, 0 iescn1, iescn0 (n = 00 to 03) chapter 7 interrupt/exception processing function 337 user?s manual u16031ej3v0ud (8) valid edge select registers 10, 11 (sesa10, sesa11) these registers are used to specif y the valid edge of the external in terrupt requests (tiud10, tiud11, tcud10, tcud11, tclr10, or tclr11) input from external pins and the ex ternal capture trigger inputs to timer enc1 (intp100, intp101, intp110, or intp111). the rising edge, falling edge, or both the rising and falling edges can be i ndependently specified as the valid edge. each of these registers can be read or written in 8-bit or 1-bit units. cautions 1. changing each bit of the sesa1n re gister is prohibited wh ile tmenc1n is operating (ce1n1 bit = 1). 2. set the pmcdh register before setting the trigger mode of the intp100, intp101, intp110, intp111, tiud10, tiud 11, tcud10, tcud11, tclr10, and tclr11 pins. if the pmcdh register is set after the sesa1n regi ster has been set, an illegal interrupt, incorrect count, or incorrect clear may occur depending on the timing of setting the pmcdh register. (1/2) 7 tesud01 sesa10 6 tesud00 5 cesud01 4 cesud00 3 ies101 2 ies100 1 ies001 0 ies000 address fffff5adh after reset 00h tiud10, tcud10 tclr10 intp101 intp100 7 tesud11 sesa11 6 tesud10 5 cesud11 4 cesud10 3 ies111 2 ies110 1 ies011 0 ies010 address fffff5ddh after reset 00h tclr11 tiud11, tcud11 intp111 intp110 bit position bit name function specify the valid edge of the tiud1n and tcud1n pins. tesudn1 tesudn0 valid edge 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges 7, 6 tesudn1, tesudn0 cautions 1. the set values of the tesudn1 and tesudn0 bits are valid only in udc mode a and udc mode b. 2. if mode 4 is specified for the operation of tmenc1n (specified by the prm1n2 to prm1n0 bits of the prm1n register), specifying the valid edge for the tiud1n and tcud1n pins (tesudn1 and tesudn0 bits) is invalid. remark n = 0, 1 chapter 7 interrupt/exception processing function 338 user?s manual u16031ej3v0ud (2/2) bit position bit name function specify the valid edge of the tclr1n pin. cesudn1 cesudn0 valid edge 0 0 falling edge 0 1 rising edge 1 0 low-level 1 1 high-level 5, 4 cesudn1, cesudn0 the relationship between the set values of the cesudn1 and cesudn0 bits and the operation of tmenc1n is as follows. 00: tmenc1n cleared after the rising edge of tclr1n has been detected. 01: tmenc1n cleared after the falling edge of tclr1n has been detected. 10: tmenc1n stays cleared while tclr1n input is low. 11: tmenc1n stays cleared while tclr1n input is high. caution the set values of the cesudn1 and cesudn0 bits are valid only in udc mode a. specify the valid edge of the intp1n1 pin. ies1n1 ies1n0 valid edge 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges 3, 2 ies1n1, ies1n0 specify the valid edge of the intp1n0 pin. ies0n1 ies0n0 valid edge 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges 1, 0 ies0n1, ies0n0 remark n = 0, 1 chapter 7 interrupt/exception processing function 339 user?s manual u16031ej3v0ud 7.4 software exception a software exception is generated when the cpu ex ecutes the trap instru ction, and can always be acknowledged. 7.4.1 operation if a software exception occurs, the cpu performs the fo llowing processing, and transfe rs control to the handler routine: <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower 16 bits (eicc) of ecr (interrupt source). <4> sets the ep and id bits of the psw. <5> sets the handler address (00000040h or 00000050h) corre sponding to the software exception to the pc, and transfers control. figure 7-8 illustrates the processi ng of a software exception. figure 7-8. software exception processing trap instruction eipc eipsw ecr.eicc psw.ep psw.id pc restored pc psw exception code 1 1 handler address cpu processing exception processing note note trap instruction format: trap vector (the vector is a value from 00h to 1fh.) the handler address is determined by the trap instruction?s operand (vector). if the vector is 00h to 0fh, it becomes 00000040h, and if the vector is 10h to 1fh, it becomes 00000050h. chapter 7 interrupt/exception processing function 340 user?s manual u16031ej3v0ud 7.4.2 restore recovery from software exception processing is carried out by the reti instruction. by executing the reti instru ction, the cpu carries out the following pr ocessing and shifts control to the restored pc?s address. <1> loads the restored pc and psw from eipc and eipsw because the ep bit of the psw is 1. <2> transfers control to the address of the restored pc and psw. figure 7-9 illustrates the processi ng of the reti instruction. figure 7-9. reti instruction processing psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0 caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during the software exception processing, in or der to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 1 using the ldsr instruction immediately before th e reti instruction. remark the solid line shows the cpu processing flow. chapter 7 interrupt/exception processing function 341 user?s manual u16031ej3v0ud 7.4.3 exception status flag (ep) the ep flag is bit 6 of the psw, and is a st atus flag used to indicate that except ion processing is in progress. it is set when an exception occurs. 31 0 psw after reset 00000020h 7 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit position bit name function 6 ep shows that exception processing is in progress. 0: exception processing not in progress. 1: exception processing in progress. chapter 7 interrupt/exception processing function 342 user?s manual u16031ej3v0ud 7.5 exception trap an exception trap is an interrupt that is requested when the illegal execution of an instructi on takes place. in the v850e/me2, an illegal opcode exception (ilgop: illegal opcode trap) is considered as an exception trap. 7.5.1 illegal opcode definition the illegal instruction has an opcode (bits 10 to 5) of 111111b, a sub-opcode (bits 26 to 23) of 0111b to 1111b, and a sub-opcode (bit 16) of 0b. an exception trap is generated when an in struction applicable to this illegal instruction is executed. 15 16 23 22 0 1 1 1 1 1 1 27 26 31 0 4 5 10 11 1 1 1 1 1 1 0 1 to : arbitrary caution since it is possible to assign this instru ction to an illegal opcode in the future, it is recommended that it not be used. (1) operation if an exception trap occurs, the cpu performs the follo wing processing, and transfers control to the handler routine: <1> saves the restored pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the np, ep, and id bits of the psw. <4> sets the handler address (00000060h) corresponding to the exception trap to the pc, and transfers control. figure 7-10 illustrates the proce ssing of the exception trap. chapter 7 interrupt/exception processing function 343 user?s manual u16031ej3v0ud figure 7-10. exception trap processing exception trap (ilgop) occurs dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h exception processing cpu processing (2) restore recovery from an exception trap is carried out by the dbret instruction. by executing the dbret instruction, the cpu carries out the following processing and controls the address of the restored pc. <1> loads the restored pc and psw from dbpc and dbpsw. <2> transfers control to the address indicated by the restored pc and psw. figure 7-11 illustrates the restore pr ocessing from an exception trap. figure 7-11. restore processing from exception trap dbret instruction pc psw dbpc dbpsw jump to address of restored pc chapter 7 interrupt/exception processing function 344 user?s manual u16031ej3v0ud 7.5.2 debug trap the debug trap is an exception that can be acknowledged every time and is generated by exec ution of the dbtrap instruction. when the debug trap is generat ed, the cpu performs the following processing. (1) operation <1> saves the restored pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the np, ep and id bits of the psw. <4> sets the handler address (00000060h) corresponding to the debug trap to the pc and transfers control. figure 7-12 illustrates the pr ocessing of the debug trap. figure 7-12. debug trap processing dbtrap instruction dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h debug monitor routine processing cpu processing chapter 7 interrupt/exception processing function 345 user?s manual u16031ej3v0ud (2) restore recovery from a debug trap is carried out by the dbret in struction. by executi ng the dbret instruction, the cpu carries out the following processing and controls the address of the restored pc. <1> loads the restored pc and psw from dbpc and dbpsw. <2> transfers control to the address indicated by the restored pc and psw. figure 7-13 illustrates the restor e processing from a debug trap. figure 7-13. restore processing from debug trap dbret instruction pc psw dbpc dbpsw jump to address of restored pc chapter 7 interrupt/exception processing function 346 user?s manual u16031ej3v0ud 7.6 multiple interrupt servicing control multiple interrupt servicing control is a process by which an interrupt request that is currently being serviced can be interrupted during servicing if there is an interrupt request with a higher priority level, and the higher priority interrupt request is acknowledged and serviced first. if there is an interrupt request with a lower priority leve l than the interrupt request cu rrently being serviced, that interrupt request is held pending. multiple interrupt servicing control of maskable interr upts is executed when interrupt s are enabled (id = 0). thus, to execute multiple interrupts, it is necessary to set t he interrupt enabled state (id = 0) even for an interrupt service routine. if maskable interrupts are enabled or a software excepti on is generated in a maskable interrupt or software exception service program, it is necessary to save eipc and eipsw. this is accomplished by the following procedure. (1) acknowledgment of maskable interrupts in service program service program of maskable interrupt or exception ... ... ? eipc saved to memory or register ? eipsw saved to memory or register ? ei instruction (inte rrupt acknowledgment enabled) ... ... maskable interrupt acknowledgment ... ... ? di instruction (interr upt acknowledgment disabled) ? saved value restored to eipsw ? saved value restored to eipc ? reti instruction chapter 7 interrupt/exception processing function 347 user?s manual u16031ej3v0ud (2) generation of exception in service program service program of maskable interrupt or exception ... ... ? eipc saved to memory or register ? eipsw saved to memory or register ... ? trap instruction exception such as trap instruction acknowledged. ... ? saved value restored to eipsw ? saved value restored to eipc ? reti instruction the priority order for multiple interr upt servicing control has 8 levels, fr om 0 to 7 for each maskable interrupt request (0 is the highest priority), but it can be set as desired via software. the priority order is set using the xxprn0 to xxprn2 bits of the interr upt control request register (xxlcn), provided for each maskable interrupt request. after system reset, an interrupt request is masked by the xxmkn bit and the priority order is set to level 7 by the xxprn0 to xxprn2 bits. the priority order of maskable interrupts is as follows. (high) level 0 > level 1 > level 2 > level 3 > level 4 > level 5 > level 6 > level 7 (low) interrupt servicing that has been sus pended as a result of multiple servic ing control is resumed after the servicing of the higher priority interrupt has been co mpleted and the reti instru ction has been executed. a pending interrupt request is acknowledged after the cu rrent interrupt servici ng has been completed and the reti instruction has been executed. caution in a non-maskable interrupt service routin e (time until the reti instruction is executed), maskable interrupts are susp ended and not acknowledged. remark xx: identification name of each peripheral unit (see table 7-2 ) n: peripheral unit number (see table 7-2 ) chapter 7 interrupt/exception processing function 348 user?s manual u16031ej3v0ud 7.7 interrupt latency time the v850e/me2 interrupt latency time (f rom interrupt request generation to start of interrupt servicing) is described below. figure 7-14. pipeline operation at inte rrupt request acknowledgment (outline) (1) minimum interrupt response time if id ex internal clock instruction 1 instruction 2 interrupt acknowledgment operation instruction (first instruction of interrupt servicing routine) interrupt request if id ex mem wb ifx idx int1 int2 int3 int4 4 system clocks (2) maximum interrupt response time if id ex internal clock instruction 1 instruction 2 interrupt acknowledgment operation instruction (first instruction of interrupt servicing routine) interrupt request if id ex mem mem mem wb ifx idx int1 int2 int3 int3 int3 int4 6 system clocks remark int1 to int4: interrupt acknowledgment processing ifx: invalid instruction fetch idx: invalid instruction decode interrupt latency (internal system clock) external interrupt internal interrupt intpm intpn condition minimum 4 7 + digital delay time 4 + analog delay time maximum 6 note 9 + digital delay time 6 + analog delay time the following cases are exceptions. ? in idle/software stop mode ? external bus access ? two or more interrupt request non-sample instructions are executed in succession ? access to peripheral i/o register note the interrupt latency is the maximum value when executing any of t he following instructions. div instruction, prepare instruct ion, dispose instructi on, switch instruction, set1 instruction, clr1 instruction, not1 instruct ion, ld instruction for internal instruction ram, misalign access remark m = c00, c01, c10, c11, c20, c21, c30, c31 n = 10, 11, 21 to 25, 50 to 52, 65 to 67, l0, l1, d0 to d15 chapter 7 interrupt/exception processing function 349 user?s manual u16031ej3v0ud 7.8 periods in which interrupts are not acknowledged an interrupt is acknowledged while an instruction is being executed. however, no interrupt will be acknowledged between an interrupt request non-sample instruction and the next instruct ion (interrupt is held pending). the interrupt request non-sample instructions are as follows. ? ei instruction ? di instruction ? ldsr reg2, 0x5 instruction (for psw) ? the store instruction for the command register (prcmd) ? the load, store, or bit manipulation in structions for the following registers. ? interrupt-related registers: interrupt control register (xxicn), interrupt mask registers 0 to 5 (imr0 to imr5), in-service priority register (ispr), power-save control register (psc) remark xx: identification name of each peripheral unit (refer to table 7-2 ) n: peripheral unit number (refer to table 7-2 ) 350 user?s manual u16031ej3v0ud chapter 8 clock generation function the clock generator (cg) consists of a spread spectr um frequency synthesizer phase locked loop (sscg) and a divider circuit, and generates and controls the clock supp lied to the internal units as well as the cpu. the sscg is a spread spectrum clock generator used to suppress noise, and is effective in reducing the peak value of electromagnetic interference (emi) noise. 8.1 features ? sscg output is used fixed to 8. ? selection of sscg output by pllsel pin set the pllsel pin as follows according to the value of f x = input frequency to x1 and x2 pins (f x ) 8 pllsel pin sscg output (f x ) 0 96 mhz f x 150 mhz 1 80 mhz f x < 96 mhz ? selection of frequency modulation rate (f dit ) of sscg output the following two setting methods are available. ? selection by jit0 and jit1 pins ( without modulation (frequency fixed), ? 1%, ? 3%, ? 5%) ? selection by sscgc register ( without modulation (frequency fixed), ? 0.5%, ? 1%, ? 2%, ? 3%, ? 4%, ? 5%) ? mdl-selector table (modulation period) selection by sscgc register (13 to 27 khz, 23 to 37 khz, 32 to 48 khz) ? division function by register setting (1/1, 1/2, 1/4, 1/8) ? clock sources oscillation by connecting a resonator ? operation mode selection by register setting the clock to be supplied to each unit is selected from the following by register setting. ? clock output by sscg ? clock from osc without passing through sscg ? usb-dedicated clock input ? power-save control ? halt mode ? idle mode ? software stop mode chapter 8 clock generation function 351 user?s manual u16031ej3v0ud 8.2 configuration divider 1 x1 x2 f x 8 f x f u f clk f x , f x /2, f x /4, f x /8 halt control halt idle control idle idle control idle stop control stop internal system clock osc uck f x main clock clock to peripheral function bus clock (busclk) prescaler selector sscg pll lock (lockup time) divider 2 f usb 48 mhz clock to usb ssel1 ssel0 pllsel jit1 jit0 usb dedicated clock 48 mhz usb clock control register (uckc) clock control register (ckc) bus mode control register (bmc) osts1 osts0 osts2 clock source select register (cks) ckssel oscillation stabilization time select register (osts) ckdiv0 ckdiv1 ckm0 ckm1 lock register (lockr) lock uckcnt remark be sure to set the usb clock to 48 mhz. 8.3 control registers 8.3.1 clock control register (ckc) the clock control register is an 8-bit regist er that controls the internal system clock (f clk ) in pll mode. it can be written to only by a specific sequence so that it cannot eas ily be overwritten by mistake due to an inadvertent program loop. this register can be read or written in 8-bit units. be sure to clear bits 7 to 2 to 0. if they are set to 1, the operation is not guaranteed. chapter 8 clock generation function 352 user?s manual u16031ej3v0ud 7 0 ckc 6 0 5 0 4 0 3 0 2 0 1 ckdiv1 0 ckdiv0 address fffff822h after reset 03h bit position bit name function sets the internal system clock (f clk ) when pll mode is used. ckdiv1 ckdiv0 internal system clock (f clk ) 0 0 f x /8 0 1 f x /4 1 0 f x /2 1 1 f x 1, 0 ckdiv1, ckdiv0 to change the internal system clock frequency in the middle of an operation, be sure to set it to f x first, and then change the frequency as desired. remark f x : main clock cautions 1. note that if the internal system clock (f clk ) is changed, the fre quency of the bus clock (busclk) is also changed. 2. if it necessary to change the refresh inte rval of the sdram as a result of changing the internal system clock (f clk ), follow this procedure. <1> mask all interrupts. for how to disable maskable interrupts, refer to the descriptio n of interrupt mask registers 0 to 5 (imr0 to imr5) (7.3.5 interr upt mask registers 0 to 5 (imr0 to imr5)). for how to disable non-maskable interrupts, disable multip le interrupts by setting the np bit of the psw to 1 (refer to 3.2.2 (2) program status word (psw)). <2> clear the mea bit of the bctm re gister to 0 (m = 0, 1, a = 0 to 7). <3> clear the renn bit to 0 (n = 1, 3, 4, or 6). <4> set the mea bit of the bctm regi ster to 1 (m = 0, 1, a = 0 to 7). <5> set a new value to the rccn1, rccn0, and rinn5 to rinn0 bits, and set the renn bit to 1 (n = 1, 3, 4, or 6). <6> write the same value current ly set to the scrn register to the scrn register (n = 1, 3, 4, or 6). <7> confirm that the wcfn bit of the scrn register is set to 1, and access sdram (n = 1, 3, 4, or 6). to change the refresh interval, set a value at which refresh can be made in time even while the interval is changed. if the refres h interval is correctly secured, the processing in <1> above may be skipped. the rfsn a nd bctm registers are prohibited from being rewritten, but they can be rewritten when the refreshing interval is re-set by changing the value of the ckc register. a register write cycle of sdram is generate d as a result of rewriting the scrn register (processing in <6> above), but the value of s dram before the rfsn and scrn registers are re-set is retained. chapter 8 clock generation function 353 user?s manual u16031ej3v0ud set data in the clock control regist er (ckc) in the following sequence. <1> disable interrupts (set the np bit of psw to 1). <2> prepare data in any one of the general-purpose registers to set in the specific register. <3> write data to the command register (prcmd). <4> set the clock control register (c kc) (with the following instruction). ? store instruction (st/sst instruction) <5> insert the nop instructions (5 instructions (<5> to <9>)). <10> release the interrupt disabled st ate (clear the np bit of psw to 0). [sample coding] <1> ldsr rx, 5 <2> mov 0x02, r10 <3> st.b r10, prcmd[r0] <4> st.b r10, ckc[r0] <5> nop <6> nop <7> nop <8> nop <9> nop <10> ldsr ry, 5 remark rx: value written to psw ry: value returned to psw no special sequence is required to read the specific register. cautions 1. if an interrupt is acknowledged between the issuance of data to the prcmd (<3>) and writing to the specific register immediately after (<4>), the write operation to the specific register is not performed. therefore, set the np bit of the psw to 1 (<1>) to disable interrupt acknowledgment. also disable interrupt ack nowledgment when selecting a bit manipulation instruction for the speci fic register setting. 2. although the data written to the prcmd re gister is dummy data, use the same register as the general-purpose register used in specific register setting (<4>) for writing to the prcmd register (<3>). the same method should be applied when using a ge neral-purpose register for addressing. 3. be sure to terminate all dma transfers prior to the execution of the above sequence. chapter 8 clock generation function 354 user?s manual u16031ej3v0ud 8.3.2 clock source select register (cks) this 8-bit register controls supply of the main clock (f x ). it can be written to only by a specific sequence so that it cannot easily be overwritten by mistake due to an inadvertent program loop. this register can be read or written in 8-bit or 1-bit units. cautions 1. with the v850e/me2, it is not assu med that the cpu operates with the osc output always supplied as the main clock (ckssel bit = 0). therefore, be sure to confirm in the initialization sequence that the lock bit of th e lockr register is 0, and then supply the main clock from the sscg output (ckssel bit = 1); otherwise the operation will not be guaranteed. 2. if the software stop mode is released by a non-maskable interrupt request (nmi) or an unmasked maskable interrupt request, the system operates on the sscg output clock after pll frequency stabilization time (about 2 ms) after the count time (oscillation stabilization time set by the osts register) of the time b ase counter (tbc) has elap sed. therefore, it is not necessary to re-set the cks register. if the software stop mode is released by reset pin input, set the cks register in accordance with the initialization sequence (see 3.4.10 initialization sequence). 7 0 cks 6 0 5 0 4 0 3 0 2 0 1 0 <0> ckssel address fffff82ch after reset 00h bit position bit name function 0 ckssel controls supply of the main clock (f x ). 0: osc output clock (f x ) 1: sscg output clock (f x 8) chapter 8 clock generation function 355 user?s manual u16031ej3v0ud set data in the clock source select regi ster (cks) in the following sequence. <1> disable interrupts (set the np bit of psw to 1). <2> prepare data in any one of the general-purpose registers to set in the specific register. <3> write data to the command register (prcmd). <4> set the clock source select register (cks) (with the following instruction). ? store instruction (st/sst instruction) <5> insert the nop instructions (5 instructions (<5> to <9>)). <10> release the interrupt disabled st ate (clear the np bit of psw to 0). [sample coding] <1> ldsr rx, 5 <2> mov 0x01, r10 <3> st.b r10, prcmd[r0] <4> st.b r10, cks[r0] <5> nop <6> nop <7> nop <8> nop <9> nop <10> ldsr ry, 5 remark rx: value written to psw ry: value returned to psw no special sequence is required to read the specific register. cautions 1. if an interrupt is acknowledged between the issuance of data to the prcmd (<3>) and writing to the specific register immediately after (<4>), the write operation to the specific register is not performed. therefore, set the np bit of the psw to 1 (<1>) to disable interrupt acknowledgment. also disable interrupt ack nowledgment when selecting a bit manipulation instruction for the speci fic register setting. 2. although the data written to the prcmd re gister is dummy data, use the same register as the general-purpose register used in specific register setting (<4>) for writing to the prcmd register (<3>). the same method should be applied when using a ge neral-purpose register for addressing. 3. be sure to terminate all dma transfers prior to the execution of the above sequence. chapter 8 clock generation function 356 user?s manual u16031ej3v0ud 8.3.3 sscg control register (sscgc) this is an 8-bit register that cont rols the frequency modulation rate and modulation period of sscg output. it modulates the frequency by the frequency modulation rate (d own spread) set by the adj2 to adj0 bits within the modulation period set by the smdln bit. this is effective in reducing the peak value of emi noise. it can be written to only by a specific sequence so that it cannot easily be ov erwritten by mistake due to an inadvertent program loop. this register can be read or written in 8-bit units. caution the sscgc register can be set only when osc output is supplied as the main clock (ckssel bit of cks register = 0). if the setting of the sscgc register is changed, the sscg is unlocked (lock bit of lockr register = 1). be sure to confirm that the lock bit = 0 before starting to supply sscg output as the main clock (ckssel bi t = 1); otherwise the operation will not be guaranteed. (1/2) 7 0 sscgc 6 0 5 smdl1 4 smdl0 3 adjon 2 adj2 1 adj1 0 adj0 address fffff836h after reset note note the default value is as follows. smdl1 bit = 0, smdl0 bit = 1 the adjon and adj2 to adj0 bits are se t as follows by the jit1 and jit0 pins. reset value jit1 pin jit0 pin adjon bit adj2 bit adj1 bit adj0 bit 0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 1 1 1 1 1 0 1 bit position bit name function set the modulation period of sscg output. smdl1 smdl0 modulation period of sscg output 0 0 13 to 27 khz 0 1 23 to 37 khz 1 0 32 to 48 khz 1 1 setting prohibited 5, 4 smdl1, smdl0 chapter 8 clock generation function 357 user?s manual u16031ej3v0ud (2/2) bit position bit name function set the frequency modulation rate of sscg output. frequency modulation rate of sscg output adjon adj2 adj1 adj0 min. typ. max. 0 no modulation (frequency fixed) 1 0 0 0 ? 0.31% ? 0.50% ? 1.28% 1 0 0 1 ? 0.67% ? 1.00% ? 1.75% 1 0 1 0 ? 1.23% ? 2.00% ? 3.10% 1 0 1 1 ? 1.74% ? 3.00% ? 4.33% 1 1 0 0 ? 2.48% ? 4.00% ? 5.83% 1 1 0 1 ? 3.27% ? 5.00% ? 7.28% other than above setting prohibited 3 to 0 adjon, adj2 to adj0 cautions 1. if the frequency modulation rate of sscg output is set to other than ?no modulation (frequency fixed)? (adjon bit = 0), the internal system clock, bus clock (busclk), and clock supplied to the on-chip peripheral functions all operate at the frequency that accords with the frequency modulation rate set by the adj2 to adj0 bits (see 8.5 operating clock provisions). therefore, thoroughly evaluate and confirm the system. 2. an overshoot/undershoot of the frequency modulation rate occurs. set data in the sscg control register (sscgc) in the following sequence. <1> disable interrupts (set the np bit of psw to 1). <2> prepare data in any one of the general-purpose registers to set in the specific register. <3> write data to the command register (prcmd). <4> set the sscg control register (ssc gc) (with the following instruction). ? store instruction (st/sst instruction) <5> insert the nop instructions (5 instructions (<5> to <9>)). <10> release the interrupt disabled state (clear the np bit of psw to 0). [sample coding] <1> ldsr rx, 5 <2> mov 0x08, r10 <3> st.b r10, prcmd[r0] <4> st.b r10, sscgc[r0] <5> nop <6> nop <7> nop <8> nop <9> nop <10> ldsr ry, 5 chapter 8 clock generation function 358 user?s manual u16031ej3v0ud remark rx: value written to psw ry: value returned to psw no special sequence is required to read the specific register. cautions 1. if an interrupt is acknowledged between the issuance of data to the prcmd (<3>) and writing to the specific register immediately after (<4>), the write operation to the specific register is not performed. therefore, set the np bit of the psw to 1 (<1>) to disable interrupt acknowledgment. also disable interrupt ack nowledgment when selecting a bit manipulation instruction for the speci fic register setting. 2. although the data written to the prcmd re gister is dummy data, use the same register as the general-purpose register used in specific register setting (<4>) for writing to the prcmd register (<3>). the same method should be applied when using a ge neral-purpose register for addressing. 3. be sure to terminate all dma transfers prior to the execution of the above sequence. 8.3.4 usb clock cont rol register (uckc) this register is used to select the clock sour ce of the usb clock. be sure to input f usb at 48 mhz. this register can be read or written in 8-bit or 1-bit units. be sure to clear the bits of this register other than bit 7 to 0. if they are set to 1, the operation is not guaranteed. caution when using the usb function, be sure to set (1) the uckcnt bit. if the registers related to the usb function are read while the uckcnt bit is 0, 0 is read. <7> uckcnt uckc 6 0 5 0 4 0 3 0 2 0 1 0 0 0 address fffff82eh after reset 00h bit position bit name function 7 uckcnt controls clock supply to usb. 0: stops clock supply to usb. 1: supplies clock to usb. chapter 8 clock generation function 359 user?s manual u16031ej3v0ud 8.3.5 lock register (lockr) the lockup time (frequency stabilization time: approx. 2 ms) is the time from when the power is turned on or software stop mode is released until the phase locks at the prescribed frequency. the st ate until this stabilization occurs is called the lockup state, and the stabilized state is called the locked state. the lock register (lockr) has a lock flag that indi cates that the pll is in the lock wait state. this register is read-only, in 8-bit or 1-bit units. caution if the phase is locked, the lock flag is cleared to 0. if it is unlocked later because of a standby status, writing to sscgc register , or reset input, the lock flag is set to 1. if the phase is unlocked by a cause other than these, however, the lock flag is not affected (lock = 0). 7 0 lockr 6 0 5 0 4 0 3 0 2 0 1 0 <0> lock address fffff824h after reset 01h bit position bit name function 0 lock this is a read-only flag that indicates the pll lock wait state. this flag holds the value 0 as long as a lockup state is maintained. 0: indicates that the pll is locked. 1: indicates that the pll is waiting to be locked (unlock state). if some other factor operates to cause an unlock state to occur, for control processing that depends on software execution speed, such as real-time processing, be sure to judge the lock flag by software immediately after operation begins and start processing after the pll is locked. on the other hand, static proce ssing such as the setting of internal hardware or the initialization of register data or memory data can be executed without waiti ng for the lock flag to be reset to 0. chapter 8 clock generation function 360 user?s manual u16031ej3v0ud 8.3.6 oscillation stabilization time select register (osts) this is an 8-bit register that specif ies the oscillation stabilization time. the osts register is used to make sure that the osci llation stabilization time of the oscillator elapses when the software stop mode is released. after the software stop mode is released, the oscill ation stabilization time is counted by the time base counter (tbc), and progr am execution is started about 2 ms later. this register can be read or written in 8-bit units. 7 0 osts 6 0 5 0 4 0 3 0 2 osts2 1 osts1 0 osts0 address fffff6c0h after reset 04h bit position bit name function specify the oscillation stabilization time. osts2 osts1 osts0 oscillation stabilization time 0 0 0 f x /2 13 0 0 1 f x /2 15 0 1 0 f x /2 16 0 1 1 f x /2 17 1 0 0 f x /2 18 1 0 1 f x /2 19 1 1 0 f x /2 20 1 1 1 f x /2 21 2 to 0 osts2 to osts0 remark f x : osc output clock chapter 8 clock generation function 361 user?s manual u16031ej3v0ud 8.4 operation 8.4.1 operation status of each clock the following table shows the oper ation status of each clock. table 8-1. operation status of each clock main clock (f x ) clock source osc pll clock supply to on-chip peripheral function internal system clock (f clk ) usb clock (f usb ) busclk normal operation halt mode idle mode software stop mode oscillation stabilization period note 1 note 1 pll mode reset period note 2 note 2 remark : operates : stops notes 1. the system operates on the osc output clock at power application. it stops when the operation is restored from the software stop mode by an interrupt. 2. operates on the osc output clock. 8.4.2 setting of input clock (f x ) this table lists the frequencies supplied to the v850e/me2. table 8-2. frequency list multiple pllsel pin ssel1 pin ssel0 pin input frequency (mhz) (target values) main clock (f x ) frequency (mhz) 0 1 setting prohibited setting prohibited 1 0 10.00 to 10.19 80.00 to 81.59 1 1 1 10.20 to 11.99 81.60 to 95.99 0 0 12.00 to 14.39 96.00 to 115.19 0 1 14.40 to 17.39 115.20 to 139.19 1 0 17.40 to 18.75 139.20 to 150.00 8 0 1 1 setting prohibited setting prohibited caution the max. value of f clk of a 100 mhz version is 100 mhz, that of a 133 mhz version is 133 mhz, and that of a 150 mhz version is 150 mhz. the operation is not guaranteed if f clk (max.) < f x . make sure that f x does not exceed the guaranteed ope rating frequency of each product. chapter 8 clock generation function 362 user?s manual u16031ej3v0ud 8.5 operating clock provisions sscg consists of a multiplier that multiplies the osc clock by eight and a modulation circuit for frequency diffusion. the multiplier that multiplies the osc clock generates an output error of up to 150 ps in the output period because of its circuit characteristics. the modulation circuit adds the modulation error with re spect to the set modulation rate, which varies depending on the modulation rate. therefore, the output frequency (f clk ) of busclk, which outputs a clock via sscg, and the operating frequency of the on-chip peripheral i/o (main clock (f x ) of timers c, d, and enc1, pwm uni t, csi3, uartb, and a/d converter) are affected by this error. when calculatin g the frequency of each signal, therefore, be sure to take this error into consideration. the methods of calculating the out put period and output frequency at each modulation rate are shown below. (1) minimum value of operating frequency (f min ) modulation rate of sscg output (%) parameter output period: t max (ns) output frequency (mhz) no modulation 1.00000 (1/f x ) 10 3 + 0.15 (1/t max ) 10 3 ? 0.50 0.99890 {1/(0.99110 f x )} 10 3 +0.15 (1/t max ) 10 3 ? 1.00 0.99375 {1/(0.98625 f x )} 10 3 + 0.15 (1/t max ) 10 3 ? 2.00 0.98550 {1/(0.97450 f x )} 10 3 + 0.15 (1/t max ) 10 3 ? 3.00 0.97665 {1/(0.96335 f x )} 10 3 + 0.15 (1/t max ) 10 3 ? 4.00 0.96915 {1/(0.95085 f x )} 10 3 + 0.15 (1/t max ) 10 3 ? 5.00 0.96140 {1(0.93860 f x )} 10 3 + 0.15 (1/t max ) 10 3 (2) maximum value of operating frequency (f max ) modulation rate of sscg output (%) parameter output period: t max (ns) output frequency (mhz) no modulation 1.00000 (1/f x ) 10 3 ? 0.15 (1/t min ) 10 3 ? 0.50 1.00390 {1/(1.00390 f x )} 10 3 ? 0.15 (1/t min ) 10 3 ? 1.00 1.00375 {1/(1.00375 f x )} 10 3 ? 0.15 (1/t min ) 10 3 ? 2.00 1.00550 {1/(1.00550 f x )} 10 3 ? 0.15 (1/t min ) 10 3 ? 3.00 1.00665 {1/(1.00665 f x )} 10 3 ? 0.15 (1/t min ) 10 3 ? 4.00 1.00915 {1/(1.00915 f x )} 10 3 ? 0.15 (1/t min ) 10 3 ? 5.00 1.01140 {1/(1.01140 f x )} 10 3 ? 0.15 (1/t min ) 10 3 (3) average operating frequency (f ave ) the average operating frequency can be calculated by this expression. average operating frequency (f ave ) = (f min + f max )/2 the average operating frequency is in one period of the modulation period set by the smdl1 and smdl0 bits of the sscgc register. the aver age operating frequency in a period shorter than the modulation period may have a relatively larger error than the result of the above expression. chapter 8 clock generation function 363 user?s manual u16031ej3v0ud 8.5.1 calculating busclk frequency if the modulation function of sscg is used, the internal system clock frequency (f clk ) from which busclk is generated fluctuates. exercise care in calculating the frequency of busclk. the following table shows the frequency fluctuation of busclk. table 8-3. frequency fluctuation of busclk bmc register busclk frequency (mhz) ckm1 ckm1 min. typ. max. 0 0 f min f ave f max 0 1 f min /2 f ave /2 f max /2 1 0 f min /3 f ave /3 f max /3 1 1 f min /4 f ave /4 f max /4 8.5.2 calculating operating clock freque ncy of each on-chip peripheral function when the modulation function of sscg is used, the main clock (f x ) from which the operating clock of each on-chip peripheral function is generated fluctuates. note (1) to (8) below. (1) count period of timer c: period of count clock frequency (set by the cscn2 to cscn0 bits of the tmccn0 register) when input clock is specified (eticn bit of the tmccn1 register = 0) (n = 0 to 5) the count period can be calculated from the average operating frequency. however, the average operating frequency is in one per iod of the modulation period set by the smdl1 and smdl0 bits of the sscgc register. note that the average operating freq uency may have a relatively larger error than the result of calculation during a count op eration in a period shorter than the modulation period. if it is necessary to guarantee an absolute value for the count operation, it is recommended to set appropriate counts during operation at f min if the counting operation is performe d within a specific time and during operation at f max if the operation is performed for longer than a specific time. do not use the modulation function of sscg if a high-accuracy count operation is necessary. (2) count period of timer d: period of count clock frequency (set by csdn2 to cs dn0 bits of the tmcdn register) (n = 0 to 3) the count period can be calculated from the average operating frequency. however, the average operating frequency is in one per iod of the modulation period set by the smdl1 and smdl0 bits of the sscgc register. note that the average operating freq uency may have a relatively larger error than the result of calculation during a count op eration in a period shorter than the modulation period. if it is necessary to guarantee an absolute value for the count operation, it is recommended to set appropriate counts during operation at f min if the counting operation is performe d within a specific time and during operation at f max if the operation is performed for longer than a specific time. do not use the modulation function of sscg if a high-accuracy count operation is necessary. chapter 8 clock generation function 364 user?s manual u16031ej3v0ud (3) count period of timer enc1: period of count clock frequency (set by prm1n2 to prm1n0 bits of the prm1n register) when general- purpose timer mode is specified (t1cmdn bit of the tum1n register = 0) (n = 0, 1) the count period can be calculated from the average operating frequency. however, the average operating frequency is in one per iod of the modulation period set by the smdl1 and smdl0 bits of the sscgc register. note that the average operating freq uency may have a relatively larger error than the result of calculation during a count op eration in a period shorter than the modulation period. if it is necessary to guarantee an absolute value for the count operation, it is recommended to set appropriate counts during operation at f min if the counting operation is performe d within a specific time and during operation at f max if the operation is performed for longer t han a specific time. duty setting is guaranteed during either high level output or low leve l output when pwm output is performed. do not use the modulation function of sscg if a high-accuracy count operation is necessary. (4) pulse output period of pwm unit: period of operating clock frequency (set by the ckspn1 an d ckspn0 bits of the pwmcn register) (n = 0, 1) the pulse output period can be calculated from the average operating frequency. however, the average operating frequency is in one per iod of the modulation period set by the smdl1 and smdl0 bits of the sscgc register. note that the average operating freq uency may have a relatively larger error than the result of calculation when a pulse wit h a period shorter than the modulation period is output. if it is necessary to guarantee an absolute value for t he pulse output, it is recommended to set appropriate counts during operation at f min if the counting operation is performe d within a specific time and during operation at f max if the operation is performed for longer t han a specific time. duty setting is guaranteed during either high level output or low leve l output when pwm output is performed. do not use the modulation function of sscg if a high-accuracy pulse output is necessary. (5) serial communication (transmission, reception, or transmission/reception) transfer rate of csi3: period of base clock frequency (cks3n2 to cks3n0 of the csic3n register = other than 111) (n = 0, 1) with master mode specified the transfer rate can be calculated fr om the average operating frequency. however, the average operating frequency is in one per iod of the modulation period set by the smdl1 and smdl0 bits of the sscgc register. note that the average operating freq uency may have a relatively larger error than the result of calculation at a tr ansfer rate shorter than the modulation period. if it is necessary to guarantee an absolute value for the transfer rate, it is recommended to set an appropriate transfer rate during operation at f min for the minimum transfer rate and during operation at f max for the maximum transfer rate. chapter 8 clock generation function 365 user?s manual u16031ej3v0ud (6) serial communication (transmission or reception) transfer rate of uartb: period of serial transfer speed (set by the ubnbrs15 to ubnbrs0 bits of the ubnctl2 register) (n = 0, 1) set the value of the transfer rate (set value (k) of the ubnctl2 register) so that the permissible maximum and minimum baud rate errors are satisfied at both f min and f max . here is a calculation example. <1> determine the set value (k) of the ubnctl2 register from the calculation result of the expression ?target baud rate 2/f ave (hz)?. <2> calculate the actual baud rate value at f max and f min , by using the set value (k) calculated in <1> above. <3> check that the result of calculation in <2> a bove satisfies the allowable maximum/minimum baud rate error. <4> calculate the set value of the transfer rate using <1> to <3> (set value (k) of the ubnctl2 register). caution change the modulation rate of sscg if the set value (set value (k) of the ubnctl2 register) of the transfer rate that satisfies the above calculation method cannot be obtained. (example) f x = 150 mhz: setting of modulation rat es of 4% and 5% is prohibited. f x = 133 mhz: setting of modulation rat es of 4% and 5% is prohibited. f x = 100 mhz: setting of modulation rate of 5% is prohibited. (7) a/d converter: conversion time calculate the set value (2 to 10 s) of the a/d conversion time (set by the fr3 to fr0 bits of the adm1 register) by f ave (calculation by f min and f max is not necessary). (8) digital noise elimination time calculate the minimum noise elimination time set by the ncwcn and ncw1m registers at f max and the maximum noise elimination time at f min (n = 0 to 3, m = 0, 1). chapter 8 clock generation function 366 user?s manual u16031ej3v0ud 8.6 power-save control 8.6.1 overview the power-save function has the following three modes. (1) halt mode in this mode, the clock generator (oscillator (osc, ssc g) and pll synthesizer) continues to operate, but the cpu?s operation clock stops. since the supply of cl ocks to on-chip peripheral functions other than the cpu continues, operation continues. the power consumption of the overall system can be reduced by intermittent operation using a combination of the ha lt mode and the normal operation mode. the system is switched to halt mode by a specific instruct ion (the halt instruction). (2) idle mode in this mode, the clock generator (oscillator (osc, ssc g) and pll synthesizer) continues to operate, but the supply of internal system clocks is stopped, which causes the overall system to stop. when the system is released from idle mode, it can be switched to normal operation mode quickly because the oscillator?s oscillation stabilizat ion time does not need to be secured. the system is switched to idle mode by a psmr register setting. idle mode is located midway between software stop mode and halt mode in relation to the clock stabilization time and power consumption. it is used fo r situations in which a low-power-consumption mode is to be used and the clock stabilization time is to be eliminated after the mode is released. (3) software stop mode in this mode, the overall system is stopped by stopping the clock generator (oscillator (osc, sscg) and pll synthesizer). the system enters an ultr a-low-power-consumption state in whic h only leakage current is lost. the system is switched to software stop mode by a psmr register setting. the pll synthesizer?s clock output is stopped at the same time the oscillator is stopped. after software stop mode is released by reset input, the oscillator?s oscillat ion stabilization time must be secur ed until the system clock stabilizes. when the software stop mode is released by the no n-maskable interrupt request (nmi) or an unmasked maskable interrupt request, program execution is started about 2 ms after the count time of the time base counter (tbc) elapses. chapter 8 clock generation function 367 user?s manual u16031ej3v0ud figure 8-1 shows the operati on of the clock generator in normal operation mode, halt mode, idle mode, and software stop mode. an effective low power consumption system can be r ealized by combining these modes and switching modes according to the required use. figure 8-1. power-save mode state transition diagram normal operation mode software stop mode set stop mode release according to interrupt request note 1 idle mode set idle mode set halt mode halt mode release according to reset release according to reset or interrupt note 3 release according to reset or interrupt request note 2 wait for oscillation stabilization + wait for pll lockup notes 1. non-maskable interrupt request (nmi), unm asked external maskable interrupt request note 4 , or unmasked internal maskable interrupt request note 5 of peripheral function that can operate in software stop mode 2. non-maskable interrupt request (nmi), unm asked external maskable interrupt request note 4 , or unmasked internal maskable interrupt request note 5 of peripheral function that can operate in idle mode 3. non-maskable interrupt request (nmi) or unmasked maskable interrupt request 4. intpn (n = 10, 11, 21 to 25, 50 to 52, 65 to 67, d0 to d15, l0, l1) when level detection is specified for the intpn pin, software stop mode and idle mode cannot be released. 5. intrsum chapter 8 clock generation function 368 user?s manual u16031ej3v0ud 8.6.2 control registers (1) power-save mode register (psmr) this is an 8-bit register that controls power-save m ode. it is effective only when the stp bit of the psc register is set to 1. writing to the psmr register is exec uted by the store instruction (st/sst instruction) and a bit manipulation instruction (set1/clr1 /not1 instruction). this register can be read or written in 8-bit or 1-bit units. be sure to clear bits 7, 5, and 4 to 0. if they are set to 1, the operation is not guaranteed. 7 0 psmr 6 0 5 0 4 0 3 0 2 0 1 0 psm address fffff820h after reset 00h <0> bit position bit name function 0 psm specifies idle mode or software stop mode. 0: switches the system to idle mode 1: switches the system to software stop mode (2) command register (prcmd) this is an 8-bit register that is used to set protection for write operations to regi sters that can significantly affect the system so that the applic ation system is not halted unexpecte dly due to an inadvertent program loop. writing to the first specific register (power-save control register (psc), etc.) is only valid after first writing to the prcmd register. because of this, the register valu e can be overwritten only by the specified sequence, preventing an illegal write o peration from being performed. this register is write-only, in 8-bit units (when it is read, undefined data is read out). 7 rreg7 prcmd 6 rreg6 5 rreg5 4 rreg4 3 rreg3 2 rreg2 1 rreg1 0 rreg0 address fffff1fch after reset undefined bit position bit name function 7 to 0 rreg7 to rreg0 registration code (arbitrary 8-bit data) the specific register ta rgeted is as follows. ? power-save control register (psc) ? clock control register (ckc) ? clock source select register (cks) ? sscg control register (sscgc) chapter 8 clock generation function 369 user?s manual u16031ej3v0ud (3) power-save control register (psc) this is an 8-bit register that co ntrols the power-save function. if interrupts are enabled by the setting of the nmim and intm bits, the software stop mode can be released by an interrupt request (except when interrupt servicing is disabled by the interrupt mask registers (imr0 to imr5)). the software stop mode is specifie d by the setting of the stp bit. this register, which is one of the s pecific registers, is valid only when accessed in a specific sequence during a write operation. this register can be read or writt en in 8-bit or 1-bit units. be sure to clear bits 7 and 6 to 0. if they are set to 1, the oper ation is not guaranteed. cautions 1. it is impossible to set the stp bit and the nmim or intm bit at the same time. be sure to set the stp bit after setting the nmim or intm bit. 2. the software stop mode is not released by an interrupt request for which the nmim and intm bits are set to 1 because this in terrupt request is inva lid (it is not held pending). 7 0 psc 6 0 nmim intm 3 0 2 0 stp 0 0 address fffff1feh after reset 00h <1> <4> <5> bit position bit name function 5 nmim this is the enable/disable setting bit for standby mode release using the valid edge input of nmi. 0: release by nmi enabled 1: release by nmi disabled 4 intm this is the enable/disable setting fo r standby mode release using an unmasked maskable interrupt (intpn) (n = 10, 11, 21 to 25, 50 to 52, 65 to 67, d0 to d15, l0, l1). 0: release by maskable interrupt enabled 1: release by maskable interrupt disabled 1 stp indicates the standby mode status. if 1 is written to this bit, the system enters idle or software stop mode (set by the psm bit of the psmr register). when standby mode is released, this bit is automatically reset to 0. 0: standby mode is released 1: standby mode is in effect set data in the power-save control regist er (psc) in the following sequence. <1> set the power-save mode register (psm r) (with the following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) <2> prepare data in any one of the general-purpose registers to set to the specific register. <3> write data to the command register (prcmd). <4> set the power-save control register (psc) (with the following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) <5> insert the nop instructions (5 instructions (<5> to <9>). chapter 8 clock generation function 370 user?s manual u16031ej3v0ud sample coding <1> st.b r11, psmr[r0] ; set psmr register <2> mov 0x02, r10 <3> st.b r10, prcmd[r0] ; write prcmd register <4> st.b r10, psc[r0] ; set psc register <5> nop ; dummy instruction <6> nop ; dummy instruction <7> nop ; dummy instruction <8> nop ; dummy instruction <9> nop ; dummy instruction (next instruction) ; execution routine a fter software stop mode and idle mode release no special sequence is required to read the specific register. cautions 1. a store instruction for the command regi ster does not acknowledge in terrupts. this coding is made on assumption that <3> and <4> above are executed by the program with consecutive store instructions. if another instruction is set between <3> and <4>, the above sequence may become ineffecti ve when the interrupt is ackno wledged by that instruction, and a malfunction of the program may result. 2. although the data written to the prcmd re gister is dummy data, use the same register as the general-purpose register used in specific register setting (<4>) for writing to the prcmd register (<3>). the same method should be applied when using a ge neral-purpose register for addressing. 3. at least 5 nop instructions must be inserted after executi ng a store instruction to the psc register to set software stop or idle mode. 4. be sure to terminate all dma transfers prior to the execution of the above sequence. chapter 8 clock generation function 371 user?s manual u16031ej3v0ud 8.6.3 halt mode (1) setting and operation status in halt mode, the clock generator (oscillator (osc, sscg) and pll synthesizer) continues to operate, but the operation clock of the cpu is stopped. since the supply of clocks to on- chip peripheral functions other than the cpu continues, operation continues. the powe r consumption of the overall system can be reduced by setting the system to halt mode while the cpu is idle. the system is switched to halt mode by the halt instruction. although program execution stops in ha lt mode, the contents of all regist ers, internal data ram, internal instruction ram, and ports are maintain ed in the state they were in im mediately before halt mode began. also, operation continues for all on-chip peripheral f unctions (other than ports) that do not depend on cpu instruction processing. the following shows the status of each hardware unit in halt mode. cautions 1. if the halt instruction is executed wh ile an interrupt is bei ng held pending, the halt mode is set once but it is immediately released by th e pending interrupt request. 2. at least 5 nop instructions must be inserted after executing a halt instruction. chapter 8 clock generation function 372 user?s manual u16031ej3v0ud table 8-4. operation status in halt mode function operation status clock generator operating main clock (f x ) operating cpu stopped internal data all internal data such as cpu registers, statuses, data, and the contents of internal data ram and internal instruction ram are maintained in the state they were in immediately before halt mode began. dmac operating intc operating tmc0 to tmc5 operating tmd0 to tmd3 operating tmenc10, tmenc11 operating uartb0, uartb1 operating csi30, csi31 operating a/d converter operating ports maintained the state before halt mode set usb function controller operating d0 to d31 a0 to a25 rd, we/wr, bcyst ulwr, uuwr, llwr, luwr, iord, iowr lldqm, ludqm, uldqm, uudqm llbe, lube, ulbe, uube cs0 to cs7 sdras sdcas refrq hldak hldrq wait selfref sdcke operating busclk clock output chapter 8 clock generation function 373 user?s manual u16031ej3v0ud (2) release of halt mode halt mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request, or reset pin input. (a) release according to a non-maskable interr upt request or an unmasked maskable interrupt request halt mode is released by a non-maskable interrupt request or by an unmasked maskable interrupt request regardless of the priority. t he operation after release is as follows. table 8-5. operation after halt mode is released by interrupt request release source enable interrupt (ei) status disable interrupt (di) status non-maskable interrupt request branch to handler address maskable interrupt request branch to handler address or execute next instruction execute next instruction however, if the system is set to halt mode during an interrupt servicing routine, operation will differ as follows. (i) if an interrupt request is generated with a lower pr iority than that of the maskable interrupt request that is currently being serviced, halt mode is re leased, but the newly generated interrupt request is not acknowledged. the new inte rrupt request is held pending. (ii) if an interrupt request (including non-maskable interrupt requests) is generated with a higher priority than that of the maskable interrupt request that is currently being serviced, halt mode is released and the newly generated interrupt request is acknowledged. (b) release according to reset pin input this is the same as a normal reset operation. the busclk operation when the halt mo de is released is illustrated below. chapter 8 clock generation function 374 user?s manual u16031ej3v0ud figure 8-2. busclk operati on when halt mode is released (a) when halt mode is re leased by non-maskable interrupt request or unmasked external maskable interrupt request power supply voltage h osc output clock (f x ) osc output stabilized f x = f x 8 (sscg output), sscg output stabilized (lock = 0) internal system clock interrupt request busclk <1> remarks 1. <1>: interrupt signal (active) input 2. busclk is output normally in the halt mode. (b) when halt mode is released by reset pin input power supply voltage h osc output clock (f x ) osc output stabilized pll lockup time (2 ms or more) f x = f x 8 (sscg output) f x = f x (osc output) sscg output stabilized (lock = 0) internal system clock reset (input) busclk <1> <2> <3> <4> <5> remarks 1. <1>: reset input <2>: reset cleared (counting pll lockup time starts) <3>: pll lock status (lock bit of lockr register = 0) <4>: busclk = f clk /2 (ckm1 and ckm0 bits of bmc register = 01) <5>: f x = f x 8 (ckssel bit of cks register = 1) 2. the above operation is perform ed if busclk operates with hal f the period of the internal system clock (f clk ). chapter 8 clock generation function 375 user?s manual u16031ej3v0ud 8.6.4 idle mode (1) setting and operation status in this mode, the entire system is stopped with the clock generator (oscillator (osc, sscg) and pll synthesizer) continuing to operate and clock supply to the cpu and other on-chip peripheral functions stopped. when idle mode is released, the system can be s witched to normal operation mode quickly because the oscillator?s oscillation stabilization time or the pll lockup time does not need to be secured. the system is switched to idle mode by setting the psc or psmr register using a store instruction (st or sst instruction) or a bit manipulation instruct ion (set1, clr1, or not1 instruction) (see 8.6.2 control registers ). in idle mode, program execution is stopped, and the cont ents of all registers, inte rnal data ram, internal instruction ram, and ports are maintained in the state they were in immediately before execution stopped. the operation of cpu and other on-chip peripheral functions is stopped. however, the on-chip peripheral functions that can operate on the ex ternal clock continue operating. the following shows the status of each hardware unit in idle mode. caution insert at least 5 no p instructions after the instruction that stores data in the psc register to set the idle mode. chapter 8 clock generation function 376 user?s manual u16031ej3v0ud table 8-6. operation status in idle mode function operation status clock generator operating main clock (f x ) stopped cpu stopped internal data all internal data such as cpu registers, statuses, data, and the contents of internal data ram and internal instruction ram are maintained in the state they were in immediately before idle mode began. dmac stopped intc stopped tmc0 to tmc5 stopped tmd0 to tmd3 stopped tmenc10, tmenc11 stopped uartb0, uartb1 stopped csi30, csi31 stopped a/d converter stopped ports maintained the state before idle mode set usb function controller stopped (resume signal can only be received) d0 to d31 a0 to a25 high impedance rd, we/wr, bcyst ulwr, uuwr, llwr, luwr, iord, iowr lldqm, ludqm, uldqm, uudqm llbe, lube, ulbe, uube cs0 to cs7 high-level output sdras sdcas self-refresh status when connected to sdram refrq operating (outputs high level when sdram controller is not used) hldak high-level output hldrq wait selfref input (no sampling) sdcke low-level output (outputs high leve l when sdram controller is not used) busclk low-level output chapter 8 clock generation function 377 user?s manual u16031ej3v0ud (2) release of idle mode the idle mode is released by a non-maskable interrupt request, an unmasked external maskable interrupt request (intpn) note , an unmasked internal maskable interrupt request of a peripheral function that can operate in the idle mode (intrsum), and reset pin input (n = 10, 11, 21 to 25, 50 to 52, 65 to 67, d0 to d15, l0, or l1). note when level detection is set, the idle mode cannot be released. (a) release according to a non-maskable interr upt request or an unmasked maskable interrupt request idle mode can be released by an interrupt request only when it has been set with the intm and nmim bits of the psc register cleared to 0. idle mode is released by a non-maskable interrupt request, an unmasked external maskable interrupt request (intpn), or an unmasked internal maskable in terrupt request of a perip heral function that can operate in the idle mode (intrsum) r egardless of the priority (n = 10, 11, 21 to 25, 50 to 52, 65 to 67, d0 to d15, l0, or l1). the operation after release is as follows. table 8-7. operation after idle mode is released by interrupt request release source enable interrupt (ei) status disable interrupt (di) status non-maskable interrupt request branch to handler address maskable interrupt request branch to handler address or execute next instruction execute next instruction however, if the system is set to idle mode during an interrupt servicing routine, operation will differ as follows. (i) if an interrupt request is generated with a lower pr iority than that of the maskable interrupt request that is currently being serviced, idle mode is re leased, but the newly generated interrupt request is not acknowledged. the new inte rrupt request is held pending. (ii) if an interrupt request (including non-maskable interrupt requests) is generated with a higher priority than that of the maskable interrupt request that is currently being serviced, idle mode is released and the newly generated interrupt request is acknowledged. if the system is set to idle mode during an nmi se rvicing routine, idle mode is released, but the interrupt is not acknowledged (interrupt is held pending). interrupt servicing that is started when idle mode is released by nmi pin input is handled in the same way as normal nmi interrupt servicing that occu rs during an emergency (because the nmi interrupt handler address is unique). ther efore, when a program must be able to distinguish between these two situations, a software status must be prepared in advance and that status must be set before setting the psmr register using a store instructi on or a bit manipulation instruction. by checking for this status during nmi interrupt servicing, an ordinary nmi can be distinguished from the pr ocessing that is started when idle mode is released by nmi pin input. (b) release according to reset pin input this is the same as a normal reset operation. chapter 8 clock generation function 378 user?s manual u16031ej3v0ud the busclk operation when the idle mo de is released is illustrated below. figure 8-3. busclk operation when idle mode is released (a) when idle mode is released by non-maskable interrupt request or unmasked external maskable interrupt request power supply voltage h osc output clock (f x ) internal system clock interrupt request busclk osc output stabilized f x = f x 8 (sscg output), sscg output stabilized (lock = 0) <1> remark <1>: interrupt signal (active) input (b) when idle mode is released by reset pin input power supply voltage h osc output clock (f x ) osc output stabilized pll lockup time (2 ms or more) f x = f x 8 (sscg output) f x = f x (osc output) sscg output stabilized (lock = 0) internal system clock reset (input) busclk <1> <2> <3> <4> <5> remarks 1. <1>: reset input <2>: reset cleared (counting pll lockup time starts) <3>: pll lock status (lock bit of lockr register = 0) <4>: busclk = f clk /2 (ckm1 and ckm0 bits of bmc register = 01) <5>: f x = f x 8 (ckssel bit of cks register = 1) 2. the above operation is performed if busclk operates with half the period of the internal system clock (f clk ). chapter 8 clock generation function 379 user?s manual u16031ej3v0ud 8.6.5 software stop mode (1) setting and operation status in software stop mode, the clock generator (oscilla tor (osc, sscg) and pll synthesizer) is stopped. the overall system is stopped, and ultra-lo w power consumption is achieved in which only leakage current is lost. the system is switched to software st op mode by using a store instructi on (st or sst instruction) or bit manipulation instruction (set1, clr1, or not1 in struction) to set the psc and psmr registers (see 8.6.2 control registers ). the oscillator?s oscillation stabilization time and pl l frequency stabilization time must be secured after software stop mode is released. if the software stop mode is released by an unmasked maskable interrupt request note , program execution is started after the pll lockup time (about 2 ms) has el apsed after the count time of the time base counter (tbc) (time set by the osts register) elapses. although program execution stops in software stop mode, the contents of all registers, internal data ram, internal instruction ram, and ports are maintained in the state they were in i mmediately before software stop mode began. the operation of cpu and othe r on-chip peripheral functions is stopped. the following shows the status of each har dware unit in software stop mode. note intp10, intp11, intp21 to intp25, intp50 to in tp52, intp65 to intp67, intpd0 to intpd15, intpl0, intpl1, intrsum cautions 1. insert at least 5 nop instructions after the instruction that stores data in the psc register to set the software stop mode. 2. if the software stop mode is released by an unmasked maskable interrupt request, the external bus continues to operate in the same status as in the software stop mode during the count time (time set by the osts re gister) of the time base counter (tbc) and the pll lockup time. 3. before setting software stop mode, set (1 ) the xxicn interrupt mask flag corresponding to the interrupt that can be used as a release source for software stop mode but is not used for that purpose. if th e timing at which such an inte rrupt occurs and the shift to software stop mode conflict, the so ftware stop mode may be released. chapter 8 clock generation function 380 user?s manual u16031ej3v0ud table 8-8. operation stat us in software stop mode function operation status clock generator stopped main clock (f x ) stopped cpu stopped internal data all internal data such as cpu registers, statuses, data, and the contents of internal data ram and internal instruction ram are maintained in the state they were in immediately before software stop mode began. dmac stopped intc stopped tmc0 to tmc5 stopped tmd0 to tmd3 stopped tmenc10, tmenc11 stopped uartb0, uartb1 stopped csi30, csi31 stopped a/d converter stopped ports maintained the state before software stop mode set usb function controller stopped (resume signal can only be received) d0 to d31 a0 to a25 high impedance rd, we/wr, bcyst ulwr, uuwr, llwr, luwr, iord, iowr lldqm, ludqm, uldqm, uudqm llbe, lube, ulbe, uube cs0 to cs7 high-level output sdras sdcas self-refresh status when connected to sdram refrq operating (outputs high level when sdram controller is not used) hldak high-level output hldrq wait selfref input (no sampling) sdcke low-level output (outputs high leve l when sdram controller is not used) busclk low-level output chapter 8 clock generation function 381 user?s manual u16031ej3v0ud (2) release of software stop mode the software stop mode is released by a non-maska ble interrupt input, an unmasked external maskable interrupt request (intpn) note , an unmasked internal maskable interrupt request of a peripheral function that can operate in the software stop mode (intrsum), or reset pin input (n = 10, 11, 21 to 25, 50 to 52, 65 to 67, d0 to d15, l0, or l1). when the software stop mode is released by reset pin input, it is necessary to make sure that the oscillation stabilization time of the oscillator elapses. when the software stop mode is released by the non-maskable interrupt or an unmasked maskable interrupt request, program execution starts after about 2 ms after the count time of the time base counter (tbc) elapses. note when level detection is set, the software stop mode cannot be released. (a) release according to a non-maskable interr upt request or an unmasked maskable interrupt request the software stop mode can be released by an inte rrupt request only when it has been set with the intm and nmim bits of the pcs register cleared to 0. software stop mode is released by a non-maskable interrupt request, an unmasked external maskable interrupt request (intpn), or an unmasked internal maskable interrupt request of a peripheral function that can operate in the software stop mode (intrsum) regardless of the priority (n = 10, 11, 21 to 25, 50 to 52, 65 to 67, d0 to d15, l0, or l1). the operation after release is as follows. table 8-9. operation after software stop mode is released by interrupt request release source enable interrupt (ei) status disable interrupt (di) status non-maskable interrupt request branch to handler address maskable interrupt request branch to handler address or execute next instruction execute next instruction the operation is performed as shown below if the so ftware stop mode is set in an interrupt servicing routine. chapter 8 clock generation function 382 user?s manual u16031ej3v0ud table 8-10. operation if software stop m ode is set in interr upt servicing routine releasing cause type of interrupt servicing routine when software stop mode is set releasing source priority note 1 operation low same high (id = 1) note 2 only software stop mode is released and interrupt request is not acknowledged (is held pending). maskable interrupt request high (id = 0) note 3 maskable interrupt non-maskable interrupt request ? interrupt request is acknowledged when software stop mode is released. maskable interrupt request ? low same only software stop mode is released and interrupt request is not acknowledged (is held pending). non-maskable interrupt non-maskable interrupt request high interrupt request is acknowledged when software stop mode is released. notes 1. priority of interrupt (being serviced) when software stop mode is set 2. when the id bit of the psw is 1 (disabling acknowledging interrupt) 3. when the id bit of the psw is 0 (enabling acknowledging interrupt) remark the software stop mode is released by nmi regar dless of the value of the np bit of the psw. if the system is set to software stop mode during an nmi servicing routine, software stop mode is released, but the interrupt is not ackn owledged (interrupt is held pending). interrupt servicing that is start ed when software stop mode is released by nmi pin input is handled in the same way as normal nmi interrupt servicing t hat occurs during an emergency (because the nmi interrupt handler address is unique) . therefore, when a program must be able to distinguish between these two situations, a software status must be prepar ed in advance and that status must be set before setting the psmr register using a store instru ction or a bit manipulation instruction. by checking for this status during nmi interrupt servic ing, an ordinary nmi can be distinguished from the servicing that is started when software stop mode is released by nmi pin input. (b) release according to reset pin input this is the same as a normal reset operation. the busclk operation when the software stop mode is released is illustrated below. chapter 8 clock generation function 383 user?s manual u16031ej3v0ud figure 8-4. busclk operation when so ftware stop mode is released (1/2) (a) when software stop mode is releas ed by non-maskable interrupt request or unmasked external maskable interrupt request power supply voltage h osc output clock (f x ) osc output stabilized osc output undefined oscillation stabilization time pll lockup time (2 ms or more) f x = f x 8 (sscg output), sscg output stabilized (lock = 0) internal system clock interrupt request busclk <1> <2> <3> remark <1>: interrupt signal (active) input (c ounting the oscillation stabilization time starts) <2>: osc output oscillation stabilization (counting of the oscillation stabilization time/pll lockup time starts) <3>: operation starts in the status before the software stop mode is set after the pll lock status (counting the pll lockup time ends) chapter 8 clock generation function 384 user?s manual u16031ej3v0ud figure 8-4. busclk operation when so ftware stop mode is released (2/2) (b) when software stop mode is released by reset pin input power supply voltage h osc output clock (f x ) osc output undefined osc output stabilized pll lockup time (2 ms or more) secure oscillation stabilization time f x = f x 8 (sscg output) f x = f x (osc output) sscg output stabilized (lock = 0) internal system clock reset (input) busclk <1> <2> <3> <4> <5> <6> remarks 1. <1>: reset input <2>: osc output oscillation stabilization <3>: reset cleared (counting pll lockup time starts) <4>: pll lock status (lock bit of lockr register = 0) <5>: busclk = f clk /2 (ckm1 and ckm0 bits of bmc register = 01) <6>: f x = f x 8 (ckssel bit of cks register = 1) 2. the above operation is perform ed if busclk operates with hal f the period of the internal system clock (f clk ). chapter 8 clock generation function 385 user?s manual u16031ej3v0ud 8.7 securing oscillation stabilization time 8.7.1 oscillation stabilization time security specification when the software stop mode is released by a non-maskable interrupt request, an unmasked external maskable interrupt request (intpn) note (n = 10, 11, 21 to 25, 50 to 52, 65 to 67, d0 to d15, l0, or l1), or an unmasked internal maskable interrupt request of a peripher al function that can operate in t he software stop mode (intrsum), the oscillation stabilization time set by the osts register is secured (see figure 8-4 (a) ). about 2 ms after that, program execution is started. when the softwar e stop mode is released by reset pin input, the oscillation stabilization time does not elapse. therefore, secure the oscillation st abilization time by the low-active width of reset (see figure 8-4 (b) ). the internal time base counter (tbc) is used as a timer that counts and secures the oscillation stabilization time. oscillation stabilization time = count time of tbc note when level detection is set, the software stop mode cannot be released. 8.7.2 time base counter (tbc) the time base counter (tbc) is used to secure the oscill ator?s oscillation stabilization time when software stop mode is released. the tbc counts the oscillation stabilization time after software stop mode is released, and program execution begins after the count is completed. the tbc count clock is selected according to the osts2 to osts0 bits of the osts register, and the next counting time can be set. table 8-11. counting time examples counting time osts2 to osts0 bits oscillation stabilization time f x = 16.6 mhz f x = 12.5 mhz 0 0 0 f x /2 13 0.49 ms 0.66 ms 0 0 1 f x /2 15 1.97 ms 2.62 ms 0 1 0 f x /2 16 3.95 ms 5.24 ms 0 1 1 f x /2 17 7.90 ms 10.49 ms 1 0 0 f x /2 18 15.79 ms 20.97 ms 1 0 1 f x /2 19 31.58 ms 41.94 ms 1 1 0 f x /2 20 63.17 ms 83.89 ms 1 1 1 f x /2 21 126.33 ms 167.77 ms remark f x : osc output clock 386 user?s manual u16031ej3v0ud chapter 9 timer/counter function (real-time pulse unit) 9.1 timer c 9.1.1 features timer c is a 16-bit timer/counter t hat can perform the following operations. ? ? ? ? ? ? ? ? ? ? ? ? chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 387 9.1.3 basic configuration table 9-1. timer c configuration timer count clock register read/write generated interrupt signal capture trigger timer output s/r other functions tmc0 read intovc0 ? ? ccc00 read/write intccc00 intpc00 toc0 (s) ccc01 read/write intccc01 intpc01 toc0 (r) tmc1 read intovc1 ? ? ccc10 read/write intccc10 intpc10 toc1 (s) ccc11 read/write intccc11 intpc11 toc1 (r) tmc2 read intovc2 ? ? ccc20 read/write intccc20 intpc20 toc2 (s) ccc21 read/write intccc21 intpc21 toc2 (r) tmc3 read intovc3 ? ? ccc30 read/write intccc30 intpc30 toc3 (s) ccc31 read/write intccc31 intpc31 toc3 (r) tmc4 read intovc4 ? ? ccc40 read/write intccc40 ? toc4 (s) a/d conversion start trigger ccc41 read/write intccc41 ? toc4 (r) a/d conversion start trigger tmc5 read intovc5 ? ? ccc50 read/write intccc50 ? toc5 (s) a/d conversion start trigger timer c f x /8, f x /16, f x /32, f x /64, f x /128, f x /256, f x /512, f x /1,024 ccc51 read/write intccc51 ? toc5 (r) a/d conversion start trigger remark f x : main clock s/r: set/reset chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 388 (1) timer c (16-bit timer/counter) figure 9-1. timer c block diagram r note q sq tmcn (16 bits) cccn0 cccn1 intovcn intcccn0 intpcm1 1/2 1/4 1/8 1/16 1/32 1/64 1/128 1/256 f x /4 ticm/intpcm0 intcmd0 of tmd0 intcccn1 tocn clear & start selector selector selector selector edge detector edge detector edge detector noise filter noise filter ncccn1 ncccn0 noise elimination width setting register cn (ncwcn) internal bus note reset priority remarks 1. m = 0 to 3, n = 0 to 5 2. f x : main clock chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 389 9.1.4 timer c (1) timers c0 to c5 (tmc0 to tmc5) tmcn functions as a 16-bit free-running timer or as an event counter for an external signal. besides being mainly used for cycle measurement, tmcn can be used as pulse output (n = 0 to 5). tmcn is read-only, in 16-bit units. cautions 1. the tmcn register can only be read. if the tmcn register is written, the subsequent operation is undefined. 2. if the caecn bit of the tmccn0 register is cleared to 0, a reset is performed asynchronously. tmc1 fffff620h 0000h tmc2 fffff640h 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 tmc0 fffff600h 0000h address after reset 0 tmc4 fffff680h 0000h tmc5 fffff6a0h 0000h tmc3 fffff660h 0000h tmcn performs the count-up operations of an internal count clock or external count clock. timer start and stop are controlled by the cecn bit of timer mode cont rol register cn0 (tmccn0) (n = 0 to 5). the internal or external count clock is selected by the eticn bit of timer mode control register cn1 (tmccn1) (n = 0 to 5). chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 390 (a) selection of the external count clock tmcn operates as an event counter. when the eticn bit of timer mode control register c n1 (tmccn1) is set to 1, tmcm counts the valid edges of the external clock input (ticm), synchronized with the internal count clock. the valid edge is specified by valid edge select register cm (sescm) (m = 0 to 3, n = 0 to 5). caution when the intpcm0/ticm pin is used as ticm (external clock input pin), disable the intpcm0 interrupt or set cccm0 to compar e mode (m = 0 to 3, n = 0 to 5). (b) selection of the internal count clock tmcn operates as a free-running timer. when an internal clock is specified as the count cl ock by timer mode control register cn1 (tmccn1), tmcn is counted up for each input clock cycle spec ified by the cscn0 to cscn2 bits of the tmccn0 register (n = 0 to 5). division by the prescaler can be selected for the count clock from among f x /8, f x /16, f x /32, f x /64, f x /128, f x /256, f x /512, and f x /1,024 by the tmccn0 register (f x : main clock). an overflow interrupt can be generated if the timer overflows. also, the timer can be stopped following an overflow by setting the ostcn bit of the tmccn1 register to 1. caution the count clock cannot be ch anged while the timer is operating. the conditions when the tmcn register becomes 0000h are shown below. (a) asynchronous reset ? ? ? ? chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 391 (2) capture/compare registers cn0 and cn1 (cccn0 and cccn1) (n = 0 to 5) these capture/compare registers (cn0 and cn1) are 16-bit registers. they can be used as capture regi sters or compare registers accord ing to the cmscn0 and cmscn1 bit specifications of timer mode control re gister cn1 (tmccn1) (n = 0 to 5). these registers can be read or written in 16-bit units. (however, write operations can only be performed in compare mode.) caution the ccc40, ccc41, ccc50, and ccc51 regist ers can only be used as compare registers. they cannot be used as capture registers. ccc1n ccc2n 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ccc0n fffff602h, fffff604h fffff622h, fffff624h fffff642h, fffff644h fffff662h, fffff664h 0000h 0000h 0000h 0000h address after reset 0 ccc4n ccc5n fffff682h, fffff684h fffff6a2h, fffff6a4h 0000h 0000h ccc3n remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 392 (a) setting these registers as capture regist ers (cmscn0 and cmscn1 of tmccn1 = 0) when these registers are set as capture registers, the valid edges of the corresponding external interrupt signals intpcm0 and intpcm1 are detected as captur e triggers. the timer tmcm is synchronized with the capture trigger, and the value of tmcm is latched in the cccm0 and cccm1 registers (capture operation) (m = 0 to 3, n = 0 to 5). the valid edge of the intpcm0 pin is specified (rising edge, falling edge, or both rising and falling edges) according to the iesc0m1 and iesc0m0 bits of the sescm register, and the valid edge of the intpcm1 pin is specified according to the iesc1m 1 and iesc1m0 bits of the sescm register. the capture operation is per formed asynchronously to the count clo ck. the latched value is held in the capture register until another c apture operation is performed. when the caecn bit of timer mode control regi ster cn0 (tmccn0) is 0, 0000h is read. if these registers are specified as capture registers, an interrupt is generated by detecting the valid edge of signals intpcm0 and intpcm1. caution if the capture operation contends with the timing of disabling the tmcm register from counting (when the cecn bit of the tmccn0 register = 0), the captured data becomes undefined. in addition, the intcccm0 and intcccm1 interrupts do not occur (m = 0 to 3, n = 0 to 5). (b) setting these registers as compare regist ers (cmscn0 and cmscn1 of tmccn1 = 1) when these registers are set as compare registers, th e tmcn and register values are compared for each count clock, and an interrupt is generated by a match. if the cclrcn bit of timer mode control register cn1 (tmccn1) is set to 1, the tmcn value is clear ed to 0 at the same time as a match with the cccn0 register (it is not cleared to 0 by a match with the cccn1 register) (n = 0 to 5). a compare register is equipped with a set/reset functi on. the corresponding timer output (tocn) is set or reset, in synchronization with the generation of a match signal. the interrupt selection source differs accord ing to the function of the selected register. cautions 1. to write to capture /compare registers cn0 and cn1, always set the caecn bit to 1 first. if the caecn bit is 0, the data that is wri tten will be invalid. 2. write to capture/compare registers cn0 and cn1 after setting them as compare registers via tmccn0 and tmccn1 register settings. if they are set as capture registers (cmscn0 and cmscn1 bits of tm ccn1 register = 0), no data is written even if a write operation is performed to cccm0 and cccm1 (m = 0 to 3, n = 0 to 5). 3. when these registers ar e set as compare re gisters, intpcn0 and intpcn1 cannot be used (n = 0 to 5). when using these registers as an external interrupt input pin, use the intp65 and intp66 pins. chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 393 9.1.5 control registers (1) timer mode control registers c00 to c50 (tmcc00 to tmcc50) the tmccn0 registers control the oper ation of tmcn (n = 0 to 5). these registers can be read or wr itten in 8-bit or 1-bit units. be sure to clear bits 3 and 2 to 0. if they are set to 1, the oper ation is not guaranteed. cautions 1. the caecn and other bits cannot be set at the same time. the other bits and the registers of the other tmcn unit should alw ays be set after the caecn bit has been set. also, to use external pins rela ted to the timer function when timer c is used, be sure to set the caecn bit to 1 after setting the external pins to control mode. 2. when conflict occurs betw een an overflow and a tmccn0 register write, the ovfcn bit value becomes the value written during th e tmccn0 register write (n = 0 to 5). (1/2) ovfc0 ovfc1 ovfc2 ovfc3 tmcc00 tmcc10 tmcc20 tmcc30 6 csc02 csc12 csc22 csc32 5 csc01 csc11 csc21 csc31 4 csc00 csc10 csc20 csc30 3 0 0 0 0 2 0 0 0 0 cec0 cec1 cec2 cec3 caec0 caec1 caec2 caec3 address fffff606h fffff626h fffff646h fffff666h after reset 00h 00h 00h 00h <1> <7> <0> ovfc4 ovfc5 tmcc40 tmcc50 csc42 csc52 csc41 csc51 csc40 csc50 0 0 0 0 cec4 cec5 caec4 caec5 fffff686h fffff6a6h 00h 00h bit position bit name function 7 ovfcn this is a flag that indicates tmcn overflow. 0: no overflow occurs 1: overflow occurs when tmcn has counted up from ffffh to 0000h, the ovfcn bit becomes 1 and an overflow interrupt request (intovcn) is generated at the same time. however, if tmcn is cleared to 0000h after a match at ffffh when the cccn0 register is set to compare mode (cmscn0 bit of tmccn1 register = 1) and clearing is enabled for a match when tmcn and cccn0 are compared (cclrcn bit of tmccn1 register = 1), then tmcn is considered to be cleared and the ovfcn bit does not become 1. also, no intovcn interrupt is generated. the ovfcn bit retains the value 1 until 0 is written directly or until an asynchronous reset is performed because the caecn bit is 0. an interrupt operation due to an overflow is independent of the ovfcn bit, and the interrupt request flag (ovcifn) for intovcn is not affected even if the ovfcn bit is manipulated. if an overflow occurs while the ovfcn bit is being read, the flag value changes, and the change is reflected when the next read operation occurs. remark n = 0 to 5 chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 394 (2/2) bit position bit name function selects the tmcn internal count clock. cscn2 cscn1 cscn0 count cycle 0 0 0 f x /8 0 0 1 f x /16 0 1 0 f x /32 0 1 1 f x /64 1 0 0 f x /128 1 0 1 f x /256 1 1 0 f x /512 1 1 1 f x /1,024 6 to 4 cscn2 to cscn0 caution the cscn2 to cscn0 bits must not be changed during timer operation. if they are to be changed, they must be changed after setting the cecn bit to 0. if these bits are overwritten during timer operation, operation cannot be guaranteed. remark f x : main clock 1 cecn controls the operation of tmcn. 0: count disabled (stops at 0000h and does not operate) 1: counting operation is performed caution when cecn = 0, the external pulse output (tocn) becomes inactive (the active level of tocn output is set by the alvcn bit of the tmccn1 register). 0 caecn controls the internal count clock. 0: the entire tmcn unit is asynchronously re set. the supply of clocks to the tmcn unit stops. 1: clocks are supplied to the tmcn unit cautions 1. when the caecn bit is cleared to 0, the tmcn unit can be asynchronously reset. 2. when caecn = 0, the tmcn unit is in a reset state. therefore, to operate tmcn, the caecn bit must be set to 1. 3. when the caecn bit is changed from 1 to 0, all registers of the tmcn unit are initialized. when caecn is set to 1 again, the tmcn unit registers must be set again. remark n = 0 to 5 chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 395 (2) timer mode control registers c01 to c51 (tmcc01 to tmcc51) the tmccn1 registers control the oper ation of tmcn (n = 0 to 5). these registers can be read or written in 8-bit units. cautions 1. the various bits of the tmccn1 register must not be changed dur ing timer operation. if they are to be changed, they must be cha nged after setting the cecn bit of the tmccn0 register to 0. if these bits are overwri tten during timer operation, operation cannot be guaranteed (n = 0 to 5). 2. if the entocn and alvcn bits are cha nged at the same time, a glitch (spike shaped noise) may be generated in the tocn pin out put. either create a circuit configuration that will not malfunction even if a glitch is ge nerated or make sure that the entocn and alvcn bits do not change at the same time (n = 0 to 5). 3. tocn output is not changed by an exter nal interrupt signal (int pcm0 or intpcm1). to use the tocn signal, specify th at the capture/compare regi sters are compare registers (cmscn0 and cmscn1 bits of tmccn1 regist er = 1) (m = 0 to 3, n = 0 to 5). 4. the tmcc41 and tmcc51 registers can be used only when the ccc40, ccc41, ccc50, and ccc51 registers are used as compare regi sters. they cannot be used when the ccc40, ccc41, ccc50, and ccc51 registers are used as capture registers. 5. to clear the external interrupt signal by setting the eclrcn bit, be sure to make the following setting. count clock period of tmd0 > count clock period of tmcn if this setting is not made , the falling edge of the intcmd 0 interrupt signal may not be detected. correct example (if count clock of tmd0 is slow) csd02 to csd00 bits of tmcd0 register = 011: f x /64 cscn2 to cscn0 bits of tmcc0 register = 001: f x /16 remark resetting the flip-flop of the tocn output takes precedence (n = 0 to 5). chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 396 (1/2) 7 ostc0 ostc1 ostc2 ostc3 ostc4 ostc5 tmcc01 tmcc11 tmcc21 tmcc31 tmcc41 tmcc51 6 entoc0 entoc1 entoc2 entoc3 entoc4 entoc5 5 alvc0 alvc1 alvc2 alvc3 alvc4 alvc5 4 etic0 etic1 etic2 etic3 etic4 etic5 3 cclrc0 cclrc1 cclrc2 cclrc3 cclrc4 cclrc5 2 eclrc0 eclrc1 eclrc2 eclrc3 eclrc4 eclrc5 1 cmsc01 cmsc11 cmsc21 cmsc31 cmsc41 cmsc51 0 cmsc00 cmsc10 cmsc20 cmsc30 cmsc40 cmsc50 address fffff608h fffff628h fffff648h fffff668h fffff688h fffff6a8h after reset 20h 20h 20h 20h 20h 20h bit position bit name function 7 ostcn sets the operation when tmcn has overflowed. 0: after the overflow, counting continues (free-running mode) 1: after the overflow, the timer maintains the value 0000h, and counting stops (overflow stop mode). counting is resumed by the following operation. when eclrcn bit = 0: writing 1 to cecn bit when eclrcn bit = 1: inputting valid edge to intcmd0 6 entocn external pulse output is enabled/disabled (tocn). 0: external pulse output is disabled. output of the alvcn bit inactive level to the tocn pin is fixed. the tocn pin level is not changed even if a match signal from the corresponding compare register is generated. 1: external pulse output is enabled. a compare register match causes tocn output to change. however, if capture mode is set, tocn output does not change. the alvcn bit inactive level is output from the time when timer output is enabled until a match signal is first generated. caution if either cccn0 or cccn1 is specified as a capture register, the entocn bit must be cleared to 0. 5 alvcn specifies the active level for external pulse output (tocn). 0: active level is low level 1: active level is high level caution the initial value of the alvcn bit is 1. 4 eticn specifies a switch between the external and internal count clock. 0: specifies the input clock (internal). the count clock can be selected according to the cscn2 to cscn0 bits of tmccn0. 1: specifies the external clock (ticm). the valid edge can be selected according to the tescm1 and tescm0 bit specifications of sescm. remark m = 0 to 3 n = 0 to 5 chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 397 (2/2) bit position bit name function 3 cclrcn sets whether the clearing of tmcn is enabled or disabled during a compare operation. 0: clearing is disabled 1: clearing is enabled (if cccn0 and tmcn match during a compare operation, tmcn is cleared) 2 eclrcn enables/disables clearing tmcn by intcmd0 (tmd0). 0: disables clearing by intcmd0. 1: enables clearing by intcmd0. after tmcn has been cleared, it resumes counting. caution when eclrcn = 1, unless a compare match interrupt (intcmd0) is generated by tmd0, timer counting does not start (even if the cecn bit of the tmccn0 register is set (1)). 1 cmscn1 selects the operation mode of the capture/compare register (cccn1). 0: the register operates as a capture register (cccm1) 1: the register operates as a compare register (cccn1) 0 cmscn0 selects the operation mode of the capture/compare register (cccn0). 0: the register operates as a capture register (cccm0) 1: the register operates as a compare register (cccn0) remark m = 0 to 3 n = 0 to 5 chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 398 (3) valid edge select register s c0 to c3 (sesc0 to sesc3) these registers specify the valid edge of an extern al interrupt request (int pc00, intpc01, intpc10, intpc11, intpc20, intpc21, intpc30, intpc31, and ti c0 to tic3) from an external pin of tmcn (n = 0 to 3). the rising edge, the falling edge, or both rising and falling edges can be specified as the valid edge independently for each pin. each of these registers can be read or written in 8-bit units. be sure to clear bits 5 and 4 to 0. if they are set to 1, the oper ation is not guaranteed. cautions 1. the various bits of the sescn register must not be changed dur ing timer operation (n = 0 to 3). if they are to be changed, they mu st be changed after setting the cecn bit of the tmccn0 register to 0. if the sescn regist er is overwritten dur ing timer operation, operation cannot be guaranteed. 2. even when using the intpc00/tic0, in tpc10/tic1, intpc20/ti c2, and intpc30/tic3 pins as intpc00, intpc10, intpc20, and in tpc30, respectively, without using timer c, be sure to set the caecn and cecn bits of timer mode control registers c00 to c03 (tmcc00 to tmcc30) to 1. 3. set the pmcx register before setting the trigger mode of the inptc00, intpc01, intpc10, intpc11, intpc20, intpc21, intpc30, intpc31, and tic0 to tic3 pins (x = 5 to 7). then set the caecn and cecn bits of the tmccn0 register to 1 (n = 0 to 3). if the pmcx register is set after the se scn register has been set, an illegal interrupt, incorrect counting, and incorrect clearing m ay occur depending on the timing of setting the pmcx register (n = 0 to 3, x = 5 to 7). chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 399 7 tesc01 tic0 sesc0 6 tesc00 5 0 4 0 3 iesc101 2 iesc100 1 iesc001 0 iesc000 address fffff609h after reset 00h intpc01 intpc00 7 tesc11 tic1 sesc1 6 tesc10 5 0 4 0 3 iesc111 2 iesc110 1 iesc011 0 iesc010 address fffff629h after reset 00h intpc11 intpc10 7 tesc21 tic2 sesc2 6 tesc20 5 0 4 0 3 iesc121 2 iesc120 1 iesc021 0 iesc020 address fffff649h after reset 00h intpc21 intpc20 7 tesc31 tic3 sesc3 6 tesc30 5 0 4 0 3 iesc131 2 iesc130 1 iesc031 0 iesc030 address fffff669h after reset 00h intpc31 intpc30 bit position bit name function specifies the valid edge of the intpcm0, intpcm1, and ticm pins (m = 0 to 3). 7, 6 tescn1, tescn0 (n = 0 to 3) xescn1 xescn0 operation 0 0 falling edge 0 1 rising edge 3, 2 iescn1, iescn0 (n = 10 to 13) 1 0 setting prohibited 1 1 both rising and falling edges 1, 0 iescn1, iescn0 (n = 00 to 03) chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 400 (4) noise elimination width setting regi sters c0 to c3 (ncwc0 to ncwc3) the ncwcn registers are used to set the noise elimination width of the digital noise filter of the timer c input pin (n = 0 to 3). these registers can be read or written in 8-bit units. be sure to clear bits 7 to 2 to 0. if they are set to 1, the operation is not guaranteed. in addition, do not overwrite this register during timer operation. 7 0 0 0 0 ncwc0 ncwc1 ncwc2 ncwc3 6 0 0 0 0 5 0 0 0 0 4 0 0 0 0 3 0 0 0 0 2 0 0 0 0 1 nccc01 nccc11 nccc21 nccc31 0 nccc00 nccc10 nccc20 nccc30 address fffff610h fffff630h fffff650h fffff670h after reset 02h 02h 02h 02h bit position bit name function specifies the number of clocks by which noise is to be eliminated. ncccn1 ncccn0 number of clocks by which noise is to be eliminated 0 0 0 (through input) 0 1 2 1 0 3 1 1 5 1, 0 ncccn1, ncccn0 remark 1 clock = f x /4 f x : main clock remark n = 0 to 3 chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 401 9.1.6 operation (1) count operation timer c can function as a 16-bit free-running timer or as an external signal event counter. the setting for the type of operation is specified by ti mer mode control registers cn0 and cn1 (tmccn0 and tmccn1) (n = 0 to 5). when it operates as a free-running timer, if the cccn 0 or cccn1 register and the tmcn count value match, an interrupt signal is generated and the timer output si gnal (tocn) can be set or reset. also, a capture operation that holds the tmcm count value in the cccm0 or cccm1 register is performed, in synchronization with the valid edge that was detected from the external interrupt request input pin as an external trigger (m = 0 to 3). the capture value is held until the next capture trigger is generated. caution when using the intpcm0/ticm0 pin as ticm0 (external clock input pin) , be sure to disable the intpcm0 interrupt or set the cccm0 regi ster to compare mode (m = 0 to 3). figure 9-2. basic operation of timer c 0001h 0000h 0002h 0003h fbfeh fbffh 0001h 0002h 0000h tmcn count clock ? ? ? chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 402 (2) overflow when the tmcn register has counted the count clock from ffffh to 0000h, the ovfcn bit of the tmccn0 register is set to 1, and an overflow interrupt (intov cn) is generated at the same time. however, if the cccn0 register is set to compare mode (cmscn0 bit = 1) and to th e value ffffh when match clearing is enabled (cclrcn bit = 1), then the tmcn register is co nsidered to be cleared and the ovfcn bit is not set to 1 when the tmcn register changes from ffffh to 0000h. also, the overflow interrupt (intovcn) is not generated . when the tmcn register is changed from ffffh to 0000h because the cecn bit changes from 1 to 0, the tmcn register is considered to be cleared, but the ovfcn bit is not set to 1 and no intovcn interrupt is generated. also, timer operation can be stopped after an overflow by setting the ostcn bit of the tmccn1 register to 1. when the timer is stopped due to an overflow, the count operation is not restarted until the cecn bit of the tmccn0 register is set to 1. operation is not affected even if the cecn bit is set to 1 during a count operation. remark n = 0 to 5 figure 9-3. operation after overflow (when ostcn = 1) overflow count start overflow ffffh ffffh tmcn 0 intovcn ostcn chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 403 (3) capture operation the tmcn register has two capture/compare regist ers. these are the cccn0 register and the cccn1 register. a capture operation or a compare operation is performed according to the settings of both the cmscn1 and cmscn0 bits of the tmccn1 register. if the cmscn1 and cmscn0 bits of the tmccn1 register are cleared to 0, the regist er operates as a capture register. a capture operation that captures and holds the tmcm count value asyn chronously relative to the count clock is performed in synchronization with an external trigger. the valid edge that is detected from an external interrupt request input pin (intpcm0 or intpcm1) is used as an external trigger (capture trigger). the tmcm count value during counting is captured and held in the capture register, in synchronization with that capture trigger signal. the capture register value is held until the next capture trigger is generated. also, an interrupt request (intcccm0 or intcccm1) is generated by intpcm0 or intpcm1 signal input. the valid edge of the capture trigger is set by valid edge select register cm (sescm). if both the rising and falling edges are set as capture tr iggers, the input pulse width from an external source can be measured. also, if only one of the edges is set as the capture trigger, the input pulse cycle can be measured. remark m = 0 to 3 n = 0 to 5 figure 9-4. capture operation example tmc1 0 cec1 intpc11 ccc11 (capture register) n n (capture trigger) (capture trigger) remarks 1. when the cec1 bit is 0, no capture operat ion is performed even if intpc11 is input. 2. valid edge of intpc11: rising edge chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 404 figure 9-5. tmc1 capture operation e xample (when both edges are specified) tmc1 ? ? chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 405 (4) compare operation the tmcn register has two capture/compare regist ers. these are the cccn0 register and the cccn1 register. a capture operation or a compare operation is performed according to the settings of both the cmscn1 and cmscn0 bits of the tmccn1 register. if the cmscn1 and cmscn0 bits of the tmccn1 register are set to 1, the regist er operates as a compare register. a compare operation that compares t he value that was set in the compare register and the tmcn count value is performed. if the tmcn count value matches the value of the compare register, which had been set in advance, a match signal is sent to the output controlle r. the match signal causes the ti mer output pin (tocn) to change and an interrupt request signal (intcccn0 or intccc n1) to be generated at the same time. if the cccn0 or cccn1 registers are cleared to 0000h, the 0000h after the tmcn register counts up from ffffh to 0000h is judged as a match. in this case, the tm cn register value is clear ed to 0 at the next count timing, however, this 0000h is not judged as a matc h. also, the 0000h when the tmcn register begins counting is not judged as a match. if match clearing is enabled (cclrcn bit = 1) for the cccn0 register, the tmcn register is cleared when a match with the tmcn register o ccurs during a compare operation. remark n = 0 to 5 figure 9-6. compare operation example (1/2) (a) when cclrc0 bit = 1 and ccc00 is other than 0000h 0001h tmc0 count-up 0000h n n n ? chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 406 figure 9-6. compare operation example (2/2) (b) when cclrc0 bit = 1 and ccc00 is 0000h 0001h tmc0 count-up 0000h 0000h 0000h ffffh compare register (ccc00) intovc0 toc0 (output) match detection (intccc00) remark the match is detected immediately after the count-up, and the match detection signal is generated. chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 407 (5) external pulse output timer c has six timer output pins (tocn). an external pulse output (tocn) is generated when a match of the two compare registers (cccn0 and cccn1) and the tmcn register is detected. if a match is detected when the tmcn count value an d the cccn0 value are compared, the output level of the tocn pin is set. also, if a match is detect ed when the tmcn count value and the cccn1 value are compared, the output level of the tocn pin is reset. the output level of the tocn pin can be specified by the tmccn1 register. remark n = 0 to 5 table 9-2. tocn output control tocn output entocn alvcn external pulse output output level 0 0 disable high level 0 1 disable low level 1 0 enable when the cccn0 register is matched: low level when the cccn1 register is matched: high level 1 1 enable when the cccn0 register is matched: high level when the cccn1 register is matched: low level remark n = 0 to 5 figure 9-7. tmc1 compare operati on example (set/reset output mode) tmc1 count value 0 count start cec1 chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 408 9.1.7 application examples (1) interval timer by setting the tmccn0 and tmccn1 registers as shown in figure 9-8, timer c operates as an interval timer that repeatedly generates interrupt requests with the value that wa s preset in the cccn0 register as the interval. when the counter value of the tmcn register matches the setting value of the cccn0 register, the tmcn register is cleared to 0000h and an interrupt request si gnal (intcccn0) is generated at the same time that the count operation resumes. remark n = 0 to 5 figure 9-8. contents of register setting s when timer c is used as interval timer supply input clocks to internal units enable count operation 0 0/1 0/1 0/1 1 0/1 0/1 1 ostcn entocn alvcn eticn cclrcn cmscn1 cmscn0 0/1 0/1 0/1 0/1 0 0 1 1 ovfcn tmccn0 tmccn1 cscn2 cscn1 cscn0 cecn caecn use cccn0 register as compare register clear tmcn register due to match with cccn0 register continue counting after tmcn register overflows eclrcn remarks 1. 0/1: set to 0 or 1 as necessary 2. n = 0 to 5 chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 409 figure 9-9. interval time r operation timing example 0000h 0001h p 0000h 0001h pp p p p p 0000h 0001h t count start interval time interval time interval time count clock tmcn register cccn0 register intcccn0 interrupt clear clear remarks 1. p: setting value of cccn0 register (0000h to ffffh) t: count clock cycle interval time = (p + 1) chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 410 (2) pwm output by setting the tmccn0 and tmccn1 registers as shown in figure 9-10, timer c can output a pwm signal, whose frequency is determined according to the setting of the cscn2 to cscn0 bits of the tmccn0 register, with the values that were preset in the cccn0 and cccn1 registers determining the intervals. when the counter value of the tmcn register matches the setting value of the cccn0 register, the tocn output becomes active. then, when the counter value of the tmcn register matches the setting value of the cccn1 register, the tocn output becomes inactive. th e tmcn register continues counting. when it overflows, its count value is cleared to 0000h, and the re gister continues counting. in this way, a pwm signal whose frequency is determined according to the setting of the cscn2 to cscn0 bits of the tmccn0 register can be output. when the setting value of the cccn0 regi ster and the setting value of the cccn1 register are the same, the tocn output remain s inactive and does not change. the active level of the tocn output can be set by the alvcn bit of the tmccn1 register. remark n = 0 to 5 figure 9-10. contents of register settings when timer c is used for pwm output supply input clocks to internal units enable count operation 0 1 0/1 0/1 0 0/1 1 1 ostcn entocn alvcn eticn cclrcn cmscn1 cmscn0 0/1 0/1 0/1 0/1 0 0 1 1 ovfcn tmccn0 tmccn1 cscn2 cscn1 cscn0 cecn caecn use cccn0 register as compare register use cccn1 register as compare register disable clearing of tmcn register due to match with cccn0 register enable external pulse output (tocn) continue counting after tmcn register overflows eclrcn remarks 1. 0/1: set to 0 or 1 as necessary 2. n = 0 to 5 chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 411 figure 9-11. pwm output operation timing example 0000h 0001h p ppp p p qqq q q qpq 0000h ffffh 0001h count clock tmcn register cccn0 register cccn1 register intcccn0 interrupt intcccn1 interrupt tocn (output) count start clear t remarks 1. p: setting value of cccn0 register (0000h to ffffh) q: setting value of cccn1 register (0000h to ffffh) p ? = chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 412 (3) cycle measurement by setting the tmccn0 and tmccn1 regi sters as shown in figure 9-12, timer c can measure the cycle of signals input to the intpcm0 or intpcm1 pin. the valid edge of the intpcm0 pin is selected acco rding to the iesc0m1 and iesc0m0 bits of the sescm register, and the valid edge of the intpcm1 pin is se lected according to the iesc1m1 and iesc1m0 bits of the sescm register. either the rising edge, the fallin g edge, or both edges can be selected as the valid edges of both pins. if the cccm0 register is set as a capture register, th e valid edge input of the intpcm0 pin is set as the trigger for capturing the tmcm register value in t he cccm0 register. when this value is captured, an intcccm0 interrupt is generated. similarly, if the cccm1 register is se t as a capture register, the valid edge input of the intpcm1 pin is set as the trigger for capturing the tmcm r egister value in the cccm1 register. when this value is captured, an intcccm1 interrupt is generated. the cycle of signals input to the intpcm0 pin is calc ulated by obtaining the difference between the tmcm register?s count value (dx) that was captured in the cccm0 register according to the x-th valid edge input of the intpcm0 pin and the tmcm register?s count val ue (d(x+1)) that was captured in the cccm0 register according to the (x+1)-th valid edge input of the intpcm 0 pin and multiplying the value of this difference by the cycle of the clock control signal. the cycle of signals input to the intpcm1 pin is calc ulated by obtaining the difference between the tmcm register?s count value (dx) that was captured in the cccm1 register according to the x-th valid edge input of the intpcm1 pin and the tmcm register?s count val ue (d(x+1)) that was captured in the cccm1 register according to the (x+1)-th valid edge input of the intpcm 1 pin and multiplying the value of this difference by the cycle of the clock control signal. remark m = 0 to 3 n = 0 to 5 chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 413 figure 9-12. contents of register settings when timer c is used for cycle measurement supply input clocks to internal units enable count operation 0 0/1 0/1 0/1 0/1 0 0 0 ostcn entocn alvcn eticn cclrcn eclrcn cmscn1 cmscn0 0/1 0/1 0/1 0/1 0 0 1 1 ovfcn tmccn0 tmccn1 cscn2 cscn1 cscn0 cecn caecn use cccm0 register as capture register (when measuring the cycle of intpcm0 input) use cccm1 register as capture register (when measuring the cycle of intpcm1 input) continue counting after tmcm register overflows remarks 1. 0/1: set to 0 or 1 as necessary 2. m = 0 to 3 n = 0 to 5 chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 414 figure 9-13. cycle measurement operation timing example 0001h 0000h 0001h 0000h ffffh d0 d1 d2 d3 d3 d2 d1 d0 (d1 ? ? ? chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 415 9.1.8 cautions various cautions concerning timer c are shown below. (1) if a conflict occurs between the reading of the cccm0 register and a capture operation when the cccm0 register is used in capture mode, an external trig ger (intpcm0) valid edge is detected and an external interrupt request (intcccm0) is gener ated, however, the timer value is not stored in the cccm0 register. (2) if a conflict occurs between the reading of the cccm1 register and a capture operation when the cccm1 register is used in capture mode, an external trig ger (intpcm1) valid edge is detected and an external interrupt request (intcccm1) is gener ated, however, the timer value is not stored in the cccm1 register. (3) the following bits and registers must not be rewritten during operation (cecn = 1). ? ? ? chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 416 9.2 timer d 9.2.1 features timer d functions as a 16-bit interval timer. 9.2.2 function overview ? ? ? ? chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 417 9.2.4 timer d (1) timers d0 to d3 (tmd0 to tmd3) tmdn is a 16-bit timer. it is mainly used as an interval timer for software (n = 0 to 3). starting and stopping tmdn is controlled by the cedn bit of the timer mode control register dn (tmcdn) (n = 0 to 3). division by the prescaler can be sele cted for the count clock from among f x /8, f x /16, f x /32, f x /64, f x /128, f x /256, f x /512, and f x /1,024 by the csdn0 to csdn2 bits of the tmcdn register (f x : main clock). tmdn is read-only, in 16-bit units. tmd1 fffff550h 0000h tmd2 fffff560h 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 tmd0 fffff540h 0000h address after reset 0 tmd3 fffff570h 0000h the conditions for which the tmdn register becomes 0000h are shown below (n = 0 to 3). ? ? ? ? ? chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 418 (2) compare registers d0 to d3 (cmd0 to cmd3) cmdn and the tmdn register count value are comp ared, and an interrupt request signal (intcmdn) is generated when a match occurs. tmdn is cleared, in sy nchronization with this match. if the caedn bit of the tmcdn register is cleared to 0, a reset is perfo rmed asynchronously, and the registers are initialized (n = 0 to 3). the cmdn registers are configured with a master/slave configuration. when a cmdn register is written, data is first written to the master register and then the master register data is tr ansferred to the slave register. in a compare operation, the slave register value is compared with the count value of the tmdn register. when a cmdn register is read, data in the master side is read out. cmdn can be read or written in 16-bit units. cautions 1. a write operation to a cmdn register re quires 8 clocks until the value that was set in the cmdn register is transferred to internal units. when writing continuously to the cmdn register, be sure to reserve a time inter val of at least 8 clocks (1 cycle = 1/f x (f x : main clock)). 2. the cmdn register can be overwritten on ly once in a single tmdn register cycle (from 0000h until an intcmdn interrupt is generated due to a matc h of the tmdn register and cmdn register). if this cannot be secured by the application, make sure that the cmdn register is not overwritte n during timer operation. 3. note that an intcmdn interrupt will be ge nerated after an overflow if a value less than the counter value is written in the cmdn re gister during tmdn regi ster operation (figure 9-15). cmd1 fffff552h 0000h cmd2 fffff562h 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 cmd0 fffff542h 0000h address after reset 0 cmd3 fffff572h 0000h chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 419 figure 9-15. example of ti ming during tmdn operation (a) when tmdn < > chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 420 9.2.5 control registers (1) timer mode control register s d0 to d3 (tmcd0 to tmcd3) the tmcdn registers control the operation of timer dn (n = 0 to 3). these registers can be read or wr itten in 8-bit or 1-bit units. caution the caedn and other bits cannot be set at the same time. the other bits and the registers of the other tmdn units should always be set after the caedn bit has been set. (1/2) 7 0 0 0 0 tmcd0 tmcd1 tmcd2 tmcd3 6 csd02 csd12 csd22 csd32 5 csd01 csd11 csd21 csd31 4 csd00 csd10 csd20 csd30 3 0 0 0 0 2 0 0 0 0 ced0 ced1 ced2 ced3 caed0 caed1 caed2 caed3 address fffff544h fffff554h fffff564h fffff574h after reset 00h 00h 00h 00h <0> <1> bit position bit name function selects the tmdn internal count clock cycle. csdn2 csdn1 csdn0 count cycle 0 0 0 f x /8 0 0 1 f x /16 0 1 0 f x /32 0 1 1 f x /64 1 0 0 f x /128 1 0 1 f x /256 1 1 0 f x /512 1 1 1 f x /1,024 6 to 4 csdn2 to csdn0 caution the csdn2 to csdn0 bits must not be changed during timer operation. if they are to be changed, they must be changed after setting the cedn bit to 0. if these bits are overwritten during timer operation, operation cannot be guaranteed. remark f x : main clock 1 cedn controls the operation of tmdn. 0: count disabled (stops at 0000h and does not operate) 1: counting operation is performed caution the cedn bit is not cleared even if a match is detected by the compare operation. to stop the count operation, clear the cedn bit. remark n = 0 to 3 chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 421 (2/2) bit position bit name function 0 caedn controls the internal count clock. 0: the entire tmdn unit is reset asynchronously. the supply of input clocks to the tmdn unit stops. 1: input clocks are supplied to the tmdn unit. cautions 1. when the caedn bit is cleared to 0, the tmdn unit can be asynchronously reset. 2. when caedn = 0, the tmdn unit is in a reset state. therefore, to operate tmdn, the caedn bit must be set to 1. 3. if the caedn bit is cleared to 0, all the registers of the tmdn unit are initialized. if caedn is set to 1 again, be sure all the registers of the tmdn unit have been set again. remark n = 0 to 3 chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 422 9.2.6 operation (1) compare operation tmdn can be used for a compare operation in which the va lue that was set in a compare register (cmdn) is compared with the tmdn count value (n = 0 to 3). if a match is detected by the compare operation, an in terrupt (intcmdn) is generated. the generation of the interrupt causes tmdn to be cleared to 0 at the next co unt timing. this function enables timer d to be used as an interval timer. cmdn can also be cleared to 0. in this case, when an overflow occurs and tmdn becomes 0, a match is detected and intcmdn is generated. although the tmdn value is cleared to 0 at the next count timing, intcmdn is not generated by this match. figure 9-16. tmd0 compare operation example (1/2) (a) when cmd0 is set to n (non-zero) 1 0 n n tmd0 count clock cmd0 tmd0 clear match detected (intcmd0) count up clear remark interval time = (n + 1) chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 423 figure 9-16. tmd0 compare operation example (2/2) (b) when cmd0 is cleared to 0 1 0 0 0 ffffh overflow tmd0 count clock cmd0 tmd0 clear match detected (intcmd0) count up clear remark interval time = (ffffh + 2) chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 424 9.2.7 application examples (1) interval timer this section explains an example in which timer d is used as an interval timer with 16-bit precision. interrupt requests (intcmdn) are output at equal intervals (see figure 9-16 tmd0 compare operation example ). the setup procedure is shown below (n = 0 to 3). <1> set the caedn bit to 1. <2> set each register. ? ? chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 425 9.3 timer enc1 9.3.1 features timers enc10 and enc11 (tmenc10, tmenc11) are 16- bit up/down counters that perform the following operations. ? general-purpose timer mode free-running timer pwm output ? up/down counter mode udc mode a udc mode b 9.3.2 function overview ? 16-bit 2-phase encoder input up/down counter & gener al-purpose timer (tmenc10, tmenc11): 2 channels ? compare registers: 4 ? capture/compare registers: 4 ? interrupt request sources ? capture/compare match interrupt: 4 sources ? compare match interrupt request: 4 sources ? capture request signal: 4 sources ? the tmenc1n value can be latched using the valid edge of the intp1n0 and intp1n1 pins corresponding to the capture/compare register as the capture trigger. ? count clock selectable through division by prescaler ? timer/counter count clock sources: 2 types (selection of external pulse input or main clock division) ? 2-phase encoder input the 2-phase external encoder signal can be used as the c ount clock of the timer/counter by inputting it to the external clock input pins (tiud1n, tcud1n). t he counter mode can be selected from among the four following modes. ? mode 1: counts the input pulses of the count pulse input pin. up/down is specified by the le vel of the other input pin. ? mode 2: counts up/down using the respective input pulses of the up-count pulse input pin and down- count pulse input pin. ? mode 3: counts up/down using the phase relati onship of the pulses input to the 2 pins. ? mode 4: counts up/down using the phase relationship of the pulses input to the 2 pins. counting is done using the respective rising edges and the falling edges of the pulses. ? pwm output function in the general-purpose timer mode, 16-bit resolu tion pwm can be output from the to1n pin. chapter 9 timer/counter function (real-time pulse unit) 426 user?s manual u16031ej3v0ud ? timer clear the following timer clear operations are perform ed according to the mode that is used. (a) general-purpose timer mode: timer clear operatio n is possible upon occurrence of match with cm1n0 set value. (b) up/down counter mode: the timer clear operati on can be selected from among the following four conditions. (i) timer clear performed upon occurrence of ma tch with cm1n0 set value during tmenc1n up-count operation, and timer clear performed upon o ccurrence of match with cm1n1 set value during tmenc1n down-count operation. (ii) timer clear performed only by external input. (iii) timer clear performed upon occurrence of ma tch between tmenc1n count value and cm1n0 set value. (iv) timer clear performed upon occurrence of external input and match between tmenc1n count value and cm1n0 set value. ? external pulse output (to1n): 2 chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 427 9.3.3 basic configuration table 9-4. timer enc1 configuration timer count clock register read/write generated interrupt signal capture trigger tmenc10 read/write ? ? cm100 read/write intcm100 ? cm101 read/write intcm101 ? cc100 read/write intcc100 intp100 cc101 read/write intcc101 intp101 tmenc11 read/write ? ? cm110 read/write intcm110 ? cm111 read/write intcm111 ? cc110 read/write intcc110 intp110 timer enc1 f x /8, f x /16, f x /32, f x /64, f x /128, f x /256, f x /512 cc111 read/write intcc111 intp111 remark f x : main clock chapter 9 timer/counter function (real-time pulse unit) 428 user?s manual u16031ej3v0ud (1) timer enc1 (16-bit up/down counter) figure 9-17. timer enc1 block diagram r note q sq tmenc1n (16 bits) intp1n0/ intcc1n0 intp1n1/ intcc1n1 intov1n intud1n intcm1n0 intcm1n1 to1n clear tclr cm1n0 cm1n1 tiud1n intp1n0/ tcud1n intp1n1/ tclr1n cc1n0 cc1n1 selector selector selector selector selector selector clock division & selector tmenc1n clear controller ncc1n ncc0n internal bus internal bus f x /4 f x /32 f x /4 edge detector edge detector edge detector edge detector edge detector noise filter noise filter noise filter ce1n1 rlen1n enmd1n clr1n1 clr1n0 timer control register 1n (tmc1n) t1cmdn toe1n0 alvt1n0 mseln timer unit mode register 1n (tum1n) srtcn noise elimination width setting register 1n (ncw1n) srtin ncfn ncc1n ncc0n 1/2 1/4 1/8 1/16 1/32 1/64 1/128 note reset priority remark f x : main clock chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 429 9.3.4 timer enc1 (1) timers enc10, enc11 (tmenc10, tmenc11) tmenc1n is a 2-phase encoder input up/down counter and general-purpose timer. it can be read or written in 16-bit units. cautions 1. writing to tmenc1n is enabled only when the ce1n1 bit of the tmc1n register is 0 (count operation disabled). 2. continuous reading of tmenc1n is prohib ited. if tmenc1n is continuously read, the second read value may differ from the actual value. if tmenc1 n must be read twice, be sure to read another register between the first and the second read operation. 3. writing the same value to the tm enc1n register is prohibited. 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 tmenc10 address fffff5a0h after reset 0000h tmenc11 fffff5d0h 0000h tmenc1n start and stop is controlled by the ce1n1 bit of timer control register 1n (tmc1n). the tmenc1n operation consists of the following two modes. (a) general-purpose timer mode in the general-purpose timer mode, tmenc1n operates as a 16-bit interval timer, free-running timer, or pwm output. counting is performed based on the c ount clock selected by software. division by the prescaler can be selected for the count clock from among f x /8, f x /16, f x /32, f x /64, f x /128, f x /256, or f x /512 using the prm1n2 to prm1n0 bits of prescaler mode register 1n (prm1n) (f x : main clock). chapter 9 timer/counter function (real-time pulse unit) 430 user?s manual u16031ej3v0ud (b) up/down counter mode (udc mode) in the udc mode, tmenc1n functions as a 16-bit up /down counter that perf orms counting based on the tcud1n and tiud1n input signals. two operation modes can be set by the mseln bit of the tum1n register for this mode. (i) udc mode a (when t1cmdn bit = 1, mseln bit = 0) tmenc1n can be cleared by the condition specif ied by the clr1n1 and clr1n0 bits of the tmc1n register. (ii) udc mode b (when t1cmdn bit = 1, mseln bit = 1) tmenc1n is cleared upon a match with cm1n0 du ring a tmenc1n up-count operation. tmenc1n is cleared upon a match with cm1n1 du ring a tmenc1n down-count operation. when the ce1n1 bit of the tmc1n register is 1, tm enc1n counts up when the operation mode is the general-purpose mode, and counts up/down w hen the operation mode is the udc mode. cautions 1. the tcud1n and intp 1n0 pins function alte rnately. therefore, because the tcud1n pin is used in the udc mode, the external captur e function of the intp1n0 pin cannot be used. 2. the tclr1n and intp1n1 pins function al ternately. therefore, when the tclr1n input is used in udc mode a, the external capt ure function of the intp1n1 pin cannot be used. the conditions for clearing tmenc1n are as follows, depending on the operation mode. table 9-5. timer enc1 (tmenc1n) clear conditions tum1n register tmc1n register operation mode t1cmdn bit mseln bit enmd1n bit clr1n1 bit clr1n0 bit tmenc1n clear 0 clearing not performed general-purpose timer mode 0 0 1 cleared upon match with cm1n0 set value 0 0 cleared only by tclr1n input 0 1 cleared upon match with cm1n0 set value during up- count operation 1 0 cleared by tclr1n input or upon match with cm1n0 set value during up-count operation udc mode a 1 0 1 1 clearing not performed udc mode b 1 1 cleared upon match with cm1n0 set value during up- count operation or upon match with cm1n1 set value during down-count operation other than the above setting prohibited remark : indicates that the set value of that bit is ignored. chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 431 (2) compare registers 100, 110 (cm100, cm110) cm1n0 is a 16-bit register that alwa ys compares its value with the value of tmenc1n. when the value of a compare register matches the value of tmenc1n, an interrupt signal is generated. cm1n0 can be read or written in 16-bit units. the interrupt generation ti ming in the various modes is described below. ? in the general-purpose timer mode (t1cmdn bit of tum1n register = 0) and udc mode a (mseln bit of tum1n register = 0), an interrupt signal (intcm1n0) is always generated upon occurrence of a match. ? in udc mode b (mseln bit of tum1n register = 1), an interrupt signal (intcm 1n0) is generated only upon occurrence of a match during an up-count operation. cautions 1. when the ce1n1 bit of the tmc1n register is 1, it is pr ohibited to overwrite the value of the cm1n0 register. 2. writing the same value to the cm1n0 register is permitte d (writing the same value is guaranteed even during a count operation). cm110 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 cm100 fffff5a2h fffff5d2h 0000h 0000h address after reset 0 (3) compare registers 101, 111 (cm101, cm111) cm1n1 is a 16-bit register that alwa ys compares its value with the value of tmenc1n. when the value of the compare register matches the value of tmenc1n, an interrupt signal is generated. cm1n1 can be read or written in 16-bit units. the interrupt generation ti ming in the various modes is described below. ? in the general-purpose timer mode (t1cmdn bit of tum1n register = 0) and udc mode a (mseln bit of tum1n register = 0), an interrupt signal (intcm1n1) is always generated upon occurrence of a match. ? in udc mode b (mseln bit of tum1n register = 1), an interrupt signal (intcm 1n1) is generated only upon occurrence of a match during a down-count operation. cautions 1. when the ce1n1 bit of the tmc1n register is 1, it is pr ohibited to overwrite the value of the cm1n1 register. 2. writing the same value to the cm1n1 register is permitte d (writing the same value is guaranteed even during a count operation). cm111 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 cm101 fffff5a4h fffff5d4h 0000h 0000h address after reset 0 chapter 9 timer/counter function (real-time pulse unit) 432 user?s manual u16031ej3v0ud (4) capture/compare register s 100, 110 (cc100, cc110) cc1n0 is a 16-bit register. it can be specified as a capture register or as a compare register using capture/compare control register 1n (ccr1n). cc1n0 can be read or written in 16-bit units. cautions 1. when used as a cap ture register (cmsn0 bit of ccr1 n register = 0), write access from the cpu is prohibited. 2. when used as a compare re gister (cmsn0 bit of ccr1n register = 1) and the ce1n1 bit of the tmc1n register is 1, overwriting th e cc1n0 register valu es is prohibited. 3. when the ce1n1 bit of the tmc1n register is 0, the capture trigger is disabled. 4. when the operation mode is changed from capture register to compare register, set a new compare value. 5. continuous reading of cc1 n0 is prohibited. if cc1n0 is continuously read, the second read value may differ from the actual value. if cc1n0 must be read twice, be sure to read another register between the fi rst and the second read operation. 6. writing the same value to th e cc1n0 register is prohibited. cc110 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 cc100 fffff5a6h fffff5d6h 0000h 0000h address after reset 0 (a) when set as a capture register when cc1n0 is set as a capture register, the valid edge of the corresponding external interrupt intp1n0 signal is detected as the capture trigger. tmenc1n latches the count value in synchronization with the capture trigger (capture operation). the latched value is held in the c apture register until the next capture operation. the valid edge of external interrupts (rising edg e, falling edge, both edges) is selected by valid edge select register 1n (sesa1n). when the cc1n0 register is specif ied as a capture register, inte rrupts are generated upon detection of the valid edge of the intp1n0 signal. caution the tcud1n and intp1n0 pins function alternately. therefo re, because the tcud1n pin is used in the udc mode, the external capture function of the intp1n0 pin cannot be used. (b) when set as a compare register when cc1n0 is set as a compare register, it always co mpares its own value with the value of tmenc1n. if the value of cc1n0 matches the value of the tmenc1n, cc1n0 generates an interrupt signal (intcc1n0). chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 433 (5) capture/compare register s 101, 111 (cc101, cc111) cc1n1 is a 16-bit register. it can be specified as a capture register or as a compare register using capture/compare control register 1n (ccr1n). cc1n1 can be read or written in 16-bit units. cautions 1. when used as a cap ture register (cmsn1 bit of ccr1 n register = 0), write access from the cpu is prohibited. 2. when used as a compare re gister (cmsn1 bit of ccr1n register = 1) and the ce1n1 bit of the tmc1n register is 1, overwriting th e cc1n1 register valu es is prohibited. 3. when the ce1n1 bit of the tmc1n register is 0, the capture trigger is disabled. 4. when the operation mode is changed from capture register to co mpare register, newly set a compare value. 5. continuous reading of cc1 n1 is prohibited. if cc1n1 is continuously read, the second read value may differ from the actual value. if cc1n1 must be read twice, be sure to read another register between the fi rst and the second read operation. 6. writing the same value to th e cc1n1 register is prohibited. cc111 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 cc101 fffff5a8h fffff5d8h 0000h 0000h address after reset 0 (a) when set as a capture register when cc1n1 is set as a capture register, the valid edge of the corresponding external interrupt intp1n1 signal is detected as the capture trigger. tmenc1n latches the count value in synchronization with the capture trigger (capture operation). the latched value is held in the c apture register until the next capture operation. the valid edge of external interrupts (rising edg e, falling edge, both edges) is selected by valid edge select register 1n (sesa1n). when the cc1n1 register is specif ied as a capture register, inte rrupts are generated upon detection of the valid edge of the intp1n1 signal. caution the tclr1n and intp1n1 pi ns function alternately. ther efore, when the tclr1n input is used in udc mode a, the external capt ure function of the intp1n1 pin cannot be used. (b) when set as a compare register when cc1n1 is set as a compare register, it always co mpares its own value with the value of tmenc1n. if the value of cc1n1 matches the value of the tmenc1n, cc1n1 generates an interrupt signal (intcc1n1). chapter 9 timer/counter function (real-time pulse unit) 434 user?s manual u16031ej3v0ud 9.3.5 control registers (1) timer unit mode registers 10, 11 (tum10, tum11) the tum1n register is an 8-bit register used to s pecify the tmenc1n operation mode or to control the operation of the pwm output pin. tum1n can be read or written in 8-bit or 1-bit units. cautions 1. changing the value of the tum1n register during tmenc1 n operation (ce1n1 bit of tmc1n register = 1) is prohibited. 2. it is prohibited to set the t1cmdn bit (g eneral-purpose timer mode) and the mseln bit (udc mode b) of the tum1n register to 0 and 1, respectively. 3. writing the same value to the tum1n regi ster is permitted (writing the same value is guaranteed even during a count operation). 7 t1cmd0 tum10 6 0 5 0 4 0 3 toe100 2 alvt100 1 0 0 msel0 address fffff5abh after reset 00h t1cmd1 tum11 0 0 0 toe110 alvt110 0 msel1 fffff5dbh 00h bit position bit name function 7 t1cmdn specifies tmenc1n operation mode. 0: general-purpose timer mode (up count) 1: udc mode (up/down count) 3 toe1n0 specifies timer output (to1n) enable. 0: timer output disabled 1: timer output enabled caution when t1cmdn bit = 1 (udc mode), timer output is not performed regardless of the setting of the toe1n0 bit. at this time, timer output consists of the negative phase level of the level set by the alvt1n0 bit. 2 alvt1n0 specifies active level of timer output (to1n). 0: active level is high level 1: active level is low level caution when t1cmdn bit = 1 (udc mode), timer output is not performed regardless of the setting of the toe1n0 bit. at this time, timer output consists of the negative phase level of the level set by the alvt1n0 bit. 0 mseln specifies operation in udc mode (up/down count) 0: udc mode a tmenc1n can be cleared by setting the clr1n1 and clr1n0 bits of the tmc1n register. 1: udc mode b tmenc1n is cleared in the following cases. ? ? chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 435 (2) timer control registers 10, 11 (tmc10, tmc11) the tmc1n register is used to enable/disable tmen c1n operation and to set transfer and timer clear operations. tmc1n can be read or written in 8-bit or 1-bit units. cautions 1. changing the values of the tmc1n re gister bits other than the ce1n1 bit during tmenc1n operation (ce1n1 bit = 1) is prohibited. 2. writing the same value to the tmc1n regist er is permitted (writing the same value is guaranteed even during a count operation). (1/2) 7 0 tmc10 <6> ce101 5 0 4 0 3 rlen10 2 enmd10 1 clr101 0 clr100 address fffff5ach after reset 00h 0 tmc11 ce111 0 0 rlen11 enmd11 clr111 clr110 fffff5dch 00h bit position bit name function 6 ce1n1 enables/disables tmenc1n operation. 0: tmenc1n count operation disabled 1: tmenc1n count operation enabled 3 rlen1n enables/disables transfer from cm1n0 to tmenc1n in udc mode a. 0: transfer disabled 1: transfer enabled cautions 1. when rlen1n = 1, the value set to cm1n0 is transferred to tmenc1n upon occurrence of a tmenc1n underflow. 2. the rlen1n bit is valid only in udc mode a (tum1n register?s t1cmdn bit = 1, mseln bit = 0). in the general-purpose timer mode (t1cmdn bit = 0) and in udc mode b (t1cmdn bit = 1, mseln bit = 1), a transfer operation is not performed even the rlen1n bit is set to 1. 2 enmd1n enables/disables clearing of tmenc1n in general-purpose timer mode (t1cmdn bit of tum1n register = 0). 0: clear disabled (free-running mode) clearing is not performed even when tmenc1n and cm1n0 values match. 1: clear enabled clearing is performed when tmenc1n and cm1n0 values match. caution when the t1cmdn bit of the tum1n register = 1 (udc mode), the enmd1n bit setting becomes invalid. remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 436 user?s manual u16031ej3v0ud (2/2) bit position bit name function controls tmenc1n clear operation in udc mode a. clr1n1 clr1n0 specifies tmenc1n clear source 0 0 cleared only by external input (tclr1n) 0 1 cleared upon match of tmenc1n count value and cm1n0 set value 1 0 cleared by tclr1n input or upon match of tmenc1n count value and cm1n0 set value 1 1 not cleared 1, 0 clr1n1, clr1n0 cautions 1. clearing by match of the tmenc1n count value and cm1n0 set value is valid only during a tmenc1n up-count operation (tmenc1n is not cleared during a tmenc1n down-count operation). 2. when the t1cmdn bit of the tum1n register = 0 (general-purpose timer mode), the clr1n1 and clr1n0 bit settings are invalid. 3. when the mseln bit of the tum1n register = 1 (udc mode b), the clr1n1 and clr1n0 bit settings are invalid. 4. when clearing by tclr1n has been enabled by bits clr1n1 and clr1n0, clearing is performed whether the value of the ce1n1 bit is 1 or 0. remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 437 (3) capture/compare control re gisters 10, 11 (ccr10, ccr11) the ccr1n register specifies the operation mode of the capture/comp are registers (cc1n0, cc1n1). ccr1n can be read or written in 8-bit or 1-bit units. cautions 1. overwriting the ccr1n register during tmenc1n operation (c e1n1 bit = 1) is prohibited. 2. the tcud1n and intp1n0 pi ns function alternately. the refore, because the tcud1n pin is used in the udc mode, the external captur e function of the intp1n0 pin cannot be used. 3. the tclr1n and intp1n1 pins function al ternately. therefore, when the tclr1n input is used in udc mode a, the external capt ure function of the intp1n1 pin cannot be used. 4. writing the same value to the ccr1n regist er is permitted (writing the same value is guaranteed even during a count operation). 7 0 ccr10 6 0 5 0 4 0 3 0 2 0 1 cms01 0 cms00 address fffff5aah after reset 00h 0 ccr11 00000 cms11 cms10 fffff5dah 00h bit position bit name function 1 cmsn1 specifies operation mode of cc1n1. 0: capture register 1: compare register 0 cmsn0 specifies operation mode of cc1n0. 0: capture register 1: compare register remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 438 user?s manual u16031ej3v0ud (4) valid edge select regist ers 10, 11 (sesa10, sesa11) the sesa1n register is used to specif y the valid edge of external interr upt requests from external pins (intp100, intp101, intp110, intp111, tiud10, tiud11, tcud10, tcud11, tclr10, tclr11). the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified independently for each pin. sesa1n can be read or written in 8-bit or 1-bit units. cautions 1. changing the values of the sesa1n re gister bits during tme nc1n operation (ce1n1 bit = 1) is prohibited. 2. set the pmcdh register before setting th e trigger mode of the intp100, intp101, intp110, intp111, tiud10, tiud 11, tcud10, tcud11, tclr10, and tclr11 pins. if the pmcdh register is set after the sesa1n regi ster has been set, an illegal interrupt, incorrect counting, and incorrect clearing m ay occur depending on the timing of setting the pmcdh register. 3. writing the same value to the sesa1n regist er is permitted (writi ng the same value is guaranteed even during a count operation). (1/2) 7 tesud01 sesa10 6 tesud00 5 cesud01 4 cesud00 3 ies101 2 ies100 1 ies001 0 ies000 address fffff5adh after reset 00h tiud10, tcud10 tclr10 intp101 intp100 7 tesud11 sesa11 6 tesud10 5 cesud11 4 cesud10 3 ies111 2 ies110 1 ies011 0 ies010 address fffff5ddh after reset 00h tclr11 tiud11, tcud11 intp111 intp110 bit position bit name function specifies valid edge of pins tiud1n, tcud1n. tesudn1 tesudn0 valid edge 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges 7, 6 tesudn1, tesudn0 cautions 1. the set values of the tesudn1 and tesudn0 bits are only valid in udc mode a and udc mode b. 2. if mode 4 is specified as the operation mode of tmenc1n (specified by the prm1n2 to prm1n0 bits of the prm1n register), the valid edge specifications for the tiud1n and tcud1n pins (bits tesudn1 and tesudn0) are not valid. remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 439 (2/2) bit position bit name function specifies valid edge of tclr1n pin. cesudn1 cesudn0 valid edge 0 0 falling edge 0 1 rising edge 1 0 low level 1 1 high level 5, 4 cesudn1, cesudn0 the set values of bits cesudn1 and cesudn0 and the tmenc1n operation are related as follows. 00: tmenc1n cleared after detection of rising edge of tclr1n 01: tmenc1n cleared after detection of falling edge of tclr1n 10: tmenc1n cleared status held while tclr1n input is low level 11: tmenc1n cleared status held while tclr1n input is high level caution the set values of the cesudn1 and cesudn0 bits are valid only in udc mode a. specifies valid edge of intp1n1 pin. ies1n1 ies1n0 valid edge 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges 3, 2 ies1n1, ies1n0 specifies valid edge of intp1n0 pin. ies0n1 ies0n0 valid edge 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges 1, 0 ies0n1, ies0n0 remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 440 user?s manual u16031ej3v0ud (5) prescaler mode registers 10, 11 (prm10, prm11) the prm1n register is used to perform the following selections. ? selection of count clock in general-purpose ti mer mode (t1cmdn bit of tum1n register = 0) ? selection of count operation m ode in udc mode (t1cmdn bit = 1) prm1n can be read or written in 8-bit or 1-bit units. cautions 1. overwriting the prm1n register during tmenc1n operation (ce1 n1 bit = 1) is prohibited. 2. when the t1cmdn bit of the tum1n regi ster = 1 (udc mode), setting the values of the prm1n2 to prm1n0 to 000, 001, 010, and 011 bits is prohibited. 3. when tmenc1n is in mode 4, specifi cation of the valid edge for the tiud1n and tcud1n pins is invalid. 4. writing the same value to the prm1n regist er is permitted (writi ng the same value is guaranteed even during a count operation). 7 0 prm10 6 0 5 0 4 0 3 0 2 prm102 1 prm101 0 prm100 address fffff5aeh after reset 07h 0 prm11 0000 prm112 prm111 prm110 fffff5deh 07h bit position bit name function specifies the up-/down-count operation mode during input of the clock rate when the internal clock of the tmenc1n is used, or during external clock (tiud1n) input. t1cmdn = 0 t1cmdn = 1 prm1n2 prm1n1 prm1n0 count clock count clock up/down count 0 0 0 setting prohibited 0 0 1 f x /8 0 1 0 f x /16 0 1 1 f x /32 setting prohibited (mode 4) (at this time, sesa1n register is enabled.) 1 0 0 f x /64 mode 1 1 0 1 f x /128 mode 2 1 1 0 f x /256 mode 3 1 1 1 f x /512 tiud1n mode 4 2 to 0 prm1n2 to prm1n0 remark f x : main clock remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 441 (a) in general-purpose timer mode (t1c mdn bit of tum1n register = 0) the count clock is fixed to the internal clock. the clock rate of tmenc1n is specified by bits prm1n2 to prm1n0. (b) udc mode (t1cmdn bit of tum1n register = 1) the tmenc1n count triggers in the udc mode are as follows. operation mode tmenc1n operation mode 1 down count upon detection of valid edge of tiud1n input when tcud1n = high level up count upon detection of valid edge of tiud1n input when tcud1n = low level mode 2 up count upon detection of valid edge of tiud1n input down count upon detection of valid edge of tcud1n input mode 3 automatic judgment with tcud1n input level upon detection of valid edge of tiud1n input mode 4 automatic judgment upon detection of both edges of tiud1n input and both edges of tcud1n input chapter 9 timer/counter function (real-time pulse unit) 442 user?s manual u16031ej3v0ud (6) status registers 10, 11 (status10, status11) the status1n register indicates the operating status of tmenc1n. status1n is read-only, in 8-bit or 1-bit units. caution writing the same value to the status1n register is prohibited. 7 0 status10 6 0 5 0 4 0 3 0 <2> udf10 <1> ovf10 <0> ubd10 address fffff5afh after reset 00h 0 status11 0000 udf11 ovf11 ubd11 fffff5dfh 00h bit position bit name function 2 udf1n tmenc1n underflow flag 0: no tmenc1n count underflow 1: tmenc1n count underflow caution the udf1n bit is cleared to 0 upon completion of a read access to the status1n register from the cpu. 1 ovf1n tmenc1n overflow flag 0: no tmenc1n count overflow 1: tmenc1n count overflow caution the ovf1n bit is cleared to 0 upon completion of a read access to the status1n register from the cpu. 0 ubd1n indicates the operating status of tmenc1n up/down count. 0: tmenc1n up count in progress 1: tmenc1n down count in progress caution the state of the ubd1n bit differs according to the mode as follows. ? the ubd1n bit is fixed to 0 by hardware when the t1cmdn bit of the tum1n register = 0 (general-purpose timer mode). ? the ubd1n bit indicates the tmenc1n up-/down-count status when the t1cmdn bit of the tum1n register = 1 (udc mode). remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 443 (7) noise elimination width setti ng registers 10, 11 (ncw10, ncw11) the ncw1n register is used to set the noise elimination wi dth of the digital noise filter of the timer enc1 input pin. ncw1n can be read or written in 8-bit units. cautions 1. whether the signal is input thro ugh or inverted can be sp ecified for each of the intp1n0/tcud1n and tiud1n pins. the setti ng of the noise elimination width by the ncfn, ncc1n, and ncc0n bits is for each ti mer and cannot be changed for each pin. 2. the setting of the srtcn bit is valid even when the in tp1n0/tcud1n pin is used as a capture trigger (intp1n0). 7 0 ncw10 6 0 5 srtc0 4 srti0 3 0 2 ncf0 1 ncc10 0 ncc00 address fffff5c0h after reset 02h 0 ncw11 0 srtc1 srti1 0 ncf1 ncc11 ncc01 fffff5f0h 02h bit position bit name function 5 srtcn sets the input mode of the intp1n0/tcud1n pin. 0: through input 1: inverted this bit specifies whether the signal i nput from the intp1n0/tcud1n pin is input through to tmenc1n or inverted. 4 srtin sets the input mode of the tiud1n pin. 0: through input 1: inverted this bit specifies whether the signal input from the tiud1n pin is input through to tmenc1n or inverted. 2 ncfn specifies the clock freq uency for noise elimination. 0: f x /4 1: f x /32 this bit selects the clock source of the noise filter. specify the number of clocks by which noise is to be eliminated. ncc1n note 1 ncc0n note 1 number of clocks by which noise is to be eliminated 0 0 0 (through input) note 2 0 1 2 1 0 3 1 1 5 1, 0 ncc1n, ncc0n notes 1. do not overwrite this bit during a count operation. 2. clear the ncfn bit to 0 for through input. these bits select the number of clocks by which noise is to be eliminated. remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 444 user?s manual u16031ej3v0ud (a) relationship between ncw1n register set value and noise elimination width table 9-6. relationship between ncw1n regi ster set value and noise elimination width ncw1n register noise elimination width (ns) ncfn bit ncc1n bit ncc0n bit f x = 150 mhz f x = 133 mhz f x = 100 mhz remark 0 0 0 0 0 0 through 0 0 1 53.3 to 80.0 60.2 to 90.2 80 to 120 (1/(f x /4)) 2 0 1 0 80.0 to 106.7 90.2 to 120.3 120 to 160 (1/(f x /4)) 3 0 1 1 133.3 to 160.0 150.4 to 180.5 200 to 240 (1/(f x /4)) 5 1 0 1 426.7 to 640.0 481.2 to 721.8 640 to 960 (1/(f x /32)) 2 1 1 0 640.0 to 853.3 721.8 to 962.9 960 to 1,280 (1/(f x /32)) 3 1 1 1 1,066.7 to 1,280.0 1,203.0 to 1,443.6 1,600 to 1,920 (1/(f x /32)) 5 remarks 1. n = 0, 1 2. f x : main clock chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 445 9.3.6 operation (1) basic operation the following two operation modes can be selected for tmenc1n. (a) general-purpose timer mode (t1cmd n bit of tum1n register = 0) in the general-purpose timer mode, tmenc1n operates either as a 16-bit interval timer or as a pwm output timer (count operation is up count only). the count clock to tmenc1n is selected by presca ler mode register 1n (prm1n) (n = 0, 1). (b) up/down counter mode (udc mode) (t 1cmdn bit of tum1n register = 1) in the udc mode, tmenc1n operates as a 16-bit up/down counter. the external clock input (tiud1n, tcud1n pins) by prm1n register setting is used as the tmenc1n count clock. the udc mode is further divided into two modes ac cording to the tmenc1n clear conditions. ? udc mode a (tum1n register?s t1cmdn bit = 1, mseln bit = 0) the tmenc1n clear source can be selected as only external clear input (tclr1n), a match signal between the tmenc1n count value and the cm1n0 set va lue during up-count operation, or the logical sum (or) of the two signals, using bits clr 1n1 and clr1n0 of the tmc1n register. tmenc1n can transfer the value of cm1n0 upon occu rrence of a tmenc1n underflow. ? udc mode b (tum1n register?s t1cmdn bit = 1, mseln bit = 1) the status of tmenc1n after a match of the tm enc1n count value and cm1n0 set value is as follows. <1> in the case of an up-count operation, tmenc1n is cleared to 0000h, and the intcm1n0 interrupt is generated. <2> in the case of a down-count operation, the tmenc1n count value is decremented by 1. the status of tmenc1n after a match of the tm enc1n count value and cm1n1 set value is as follows. <1> in the case of an up-count operation, the tm enc1n count value is incremented by 1. <2> in the case of a down-count operation, tm enc1n is cleared to 0000h, and the intcm1n1 interrupt is generated. chapter 9 timer/counter function (real-time pulse unit) 446 user?s manual u16031ej3v0ud (2) operation in genera l-purpose timer mode tmenc1n can perform the following operations in the general-purpose timer mode. (a) interval operation tmenc1n and cm1n0 always compare their values and the intcm1n0 interrupt is generated upon occurrence of a match. tmenc1n is cleared to 0000h at the count clock following the match. furthermore, when one more count clock is input, tme nc1n counts up to 0001h. the interval time can be calculated with the following formula. interval time = (cm1n0 value + 1) tmenc1n count clock rate caution interval operation can be achieved by setting the enmd1n bit of the tmc1n register to 1. (b) free-running operation tmenc1n performs a full count operation from 0 000h to ffffh, and after the ovf1n bit of the status1n register is set to 1, tmenc1n is cleared and resumes counting. the free-running cycle can be calculated by the following formula. free-running cycle = 65,536 tmenc1n count clock rate caution the free-running operation can be achieved by setting th e enmd1n bit of the tmc1n register to 0. (c) compare function tmenc1n connects two compare register (cm1n0, cm 1n1) channels and two capture/compare register (cc1n0, cc1n1) channels. when the tmenc1n count value and the set value of one of the compare registers match, a match interrupt (intcm1n0, intcm1n1, intcc1n0 note , intcc1n1 note ) is output. particularly in the case of interval operation, tmenc1n is cleared upon generation of the intcm1n0 interrupt. note this match interrupt is generated when cc1n0 and cc 1n1 are set to the compare register mode. chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 447 (d) capture function tmenc1n connects two capture/compare register (cc1n0, cc1n1) channels. when cc1n0 and cc1n1 are set to the capture regist er mode, the value of tmenc1n is captured in synchronization with the corresponding captur e trigger signal (intp1n0, intp1n1). furthermore, an interrupt request (intcc1n0, in tcc1n1) is generated by the intp1n0, intp1n1 input signals. table 9-7. capture trigger signal (t menc1n) to 16-bit capture register capture register capture trigger signal cc1n0 intp1n0 cc1n1 intp1n1 remark cc1n0 and cc1n1 are capture/compare registers. which of these registers is used is specified by capture/compare c ontrol register 1n (ccr1n). the valid edge of the capture trigger is specified by valid edge select register 1n (sesa1n). if both the rising edge and the falling edge are selected as the capt ure triggers, it is possible to measure the input pulse width externally. if a single edge is selected as the capture trigger, the input pulse cycle can be measured. (e) pwm output operation pwm output operation is performed from the to1n pin by setting tmenc1n to the general-purpose timer mode (t1cmdn bit = 0) using timer unit mode register 1n (tum1n). the resolution is 16 bits, and the count clock can be selected from among seven internal clocks (f x /8, f x /16, f x /32, f x /64, f x /128, f x /256, f x /512). figure 9-18. tmenc1n block diagram (during pwm output operation) tmenc1n (16 bits) compare register (cm1n0) compare register (cm1n1) s intcm1n0 intcm1n1 alvt1n0 tum1n register clear to1n q r f x /8 f x /16 f x /32 f x /64 f x /128 f x /256 f x /512 16 remarks 1. f x : main clock 2. n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 448 user?s manual u16031ej3v0ud (i) description of operation the cm1n0 register is a compare register used to se t the pwm output cycle. when the value of this register matches the value of tmenc1n, the intc m1n0 interrupt is generat ed. the compare match is saved by hardware, and tmenc1n is cleared at the next count clock after the match. the cm1n1 register is a compare register used to set the pwm output duty. set the duty required for the pwm cycle. figure 9-19. pwm signal output exam ple (when alvt1n0 bit = 0 is set) cm1n0 set value cm1n1 set value tmenc1n to1n intcm1n0 intcm1n1 cautions 1. changing the values of the cm1n0 and cm1n1 registers is prohibited during tmenc1n operation (ce1n1 bit of tm c1n register = 1). 2. changing the value of the alvt1n0 bit of the tum1n register is prohibited during tmenc1n operation. 3. pwm signal output is performed from th e second pwm cycle after the ce1n1 bit is set to 1. remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 449 (3) operation in udc mode (a) overview of operation in udc mode the count clock input to tmenc1n in the udc mode (t1cmdn bit of tum1n register = 1) can only be externally input from the tiud1n and tcud1n pi ns. up-/down-count judgment in the udc mode is determined based on the phase difference of the tiud1n and tcud1n pin inputs according to the prm1n register setting (there is a total of four choices). table 9-8. list of count operations in udc mode prm1n register prm1n2 prm1n1 prm1n0 operation mode tmenc1n operation 1 0 0 mode 1 down count upon detection of valid edge of tiud1n input when tcud1n = high level up count upon detection of valid edge of tiud1n input when tcud1n = low level 1 0 1 mode 2 up count upon detection of valid edge of tiud1n input down count upon detection of valid edge of tcud1n input 1 1 0 mode 3 automatic judgment in tcud1n input level upon detection of valid edge of tiud1n input 1 1 1 mode 4 automatic judgment upon detection of both edges of tiud1n input and both edges of tcud1n input remark n = 0, 1 the udc mode is further divided into two modes according to the tmenc1n clear conditions (a count operation is performed only with tiud1n and tcud1n input in both modes). ? udc mode a (tum1n register?s t1cmdn bit = 1, mseln bit = 0) the tmenc1n clear source can be selected as only external clear input (tclr1n), a match signal between the tmenc1n count value and the cm1n0 set va lue during up-count operation, or the logical sum (or) of the two signals, using bits clr1n1 and clr1n0 of the tmc1n register. tmenc1n can transfer the value of cm1n0 upon occu rrence of a tmenc1n underflow. ? udc mode b (tum1n register?s t1cmdn bit = 1, mseln bit = 1) the status of tmenc1n after a match of the tm enc1n count value and cm1n0 set value is as follows. <1> in the case of an up-count operation, tmenc1n is cleared to 0000h, and the intcm1n0 interrupt is generated. <2> in the case of a down-count operation, the tmenc1n count value is decremented by 1. the status of tmenc1n after a match of the tm enc1n count value and cm1n1 set value is as follows. <1> in the case of an up-count operation, the tmenc1n count value is incremented by 1. <2> in the case of a down-count operation, tm enc1n is cleared to 0000h, and the intcm1n1 interrupt is generated. chapter 9 timer/counter function (real-time pulse unit) 450 user?s manual u16031ej3v0ud (b) up-/down-count operation in udc mode tmenc1n up-/down-count judgment in the udc mode is determined based on the phase difference of the tiud1n and tcud1n pin inputs accordin g to the prm1n register setting. (i) mode 1 (prm1n2 bit = 1, prm1n1 bit = 0, prm1n0 bit = 0) in mode 1, the following count operations are performed based on the level of t he tcud1n pin upon detection of the valid edge of the tiud1n pin. ? tmenc1n down-count operation when tcud1n pin = high level ? tmenc1n up-count operation when tcud1n pin = low level figure 9-20. mode 1 (when rising edge is specified as valid edge of tiud1n pin) tiud1n tcud1n tmenc1n 0006h 0007h down count up count 0005h 0004h 0005h 0006h 0007h remark n = 0, 1 figure 9-21. mode 1 (when rising edge is specified as valid edge of tiud1n pin): in case of simultaneous ti ud1n, tcud1n pin edge timing 0007h tiud1n tcud1n tmenc1n 0006h down count up count 0005h 0004h 0005h 0006h 0007h remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 451 (ii) mode 2 (prm1n2 bit = 1, prm1n1 bit = 0, prm1n0 bit = 1) the count conditions in mode 2 are as follows. ? tmenc1n up count upon detection of valid edge of tiud1n pin ? tmenc1n down count upon detecti on of valid edge of tcud1n pin caution if the count clock is simultaneously input to the ti ud1n pin and the tcud1n pin, count operation is not performed and th e immediately preceding value is held. figure 9-22. mode 2 (when rising edge is speci fied as valid edge of tiud1n, tcud1n pins) 0006h tiud1n tcud1n tmenc1n 0007h 0008h up count hold value down count 0007h 0006h 0005h remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 452 user?s manual u16031ej3v0ud (iii) mode 3 (prm1n2 = 1, prm1n1 = 1, prm1n0 = 0) in mode 3, when two signals 90 degrees out of phas e are input to the tiud1n and tcud1n pins, the level of the tcud1n pin is sampled at the input of the valid edge of the tiud1n pin (see figure 9- 23 ). if the tcud1n pin level sampled at the valid edge input to the tiud1n pin is low, tmenc1n counts down when the valid edge is input to the tiud1n pin. if the tcud1n pin level sampled at the valid edge in put to the tiud1n pin is high, tmenc1n counts up when the valid edge is input to the tiud1n pin. figure 9-23. mode 3 (when rising edge is specified as valid edge of tiud1n pin) 0007h tiud1n tcud1n tmenc1n 0008h up count down count 0009h 000ah 0009h 0008h 0007h remark n = 0, 1 figure 9-24. mode 3 (when rising edge is specified as valid edge of tiud1n pin): in case of simultaneous ti ud1n, tcud1n pin edge timing 0007h tiud1n tcud1n tmenc1n 0008h up count down count 0009h 000ah 0009h 0008h 0007h remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 453 (iv) mode 4 (prm1n2 = 1, prm1n1 = 1, prm1n0 = 1) in mode 4, when two signals out of phase are input to the tiud1n and tcud1n pins, up/down operation is automatically judged and counting is performed according to the timing shown in figure 9-25 . in mode 4, counting is executed at both the rising and falling edges of the two signals input to the tiud1n and tcud1n pins. therefore, tmenc1n coun ts four times per cycle of an input signal ( 4 count). figure 9-25. mode 4 up count tiud1n tcud1n tmenc1n 0004h 0003h 0006h 0005h 0008h 0007h 000ah 0009h 0008h 0009h 0006h 0007h 0005h down count cautions 1. when mode 4 is specified as th e operation mode of tmenc1n, the valid edge specifications for the tiud1n and tcud1n pins are not valid. 2. if the tiud1n pin edge and tcud1n pin e dge are input simultan eously in mode 4, tmenc1n continues the same count opera tion (up or down) it was performing immediately before the input. remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 454 user?s manual u16031ej3v0ud (c) operation in udc mode a (i) interval operation the operations at the count clock following a ma tch of the tmenc1n count value and the cm1n0 set value are as follows. ? in case of up-count operatio n: tmenc1n is cleared to 0000h and the intcm1n0 interrupt is generated. ? in case of down-count operation: the tm enc1n count value is decremented by 1 and the intcm1n0 interrupt is generated. remark the interval operation can be combin ed with the transfer operation. (ii) transfer operation the operations at the nex t count clock after the count value of tmenc1n becomes 0000h during a tmenc1n count down operation are as follows. ? in case of down-count operation: the data held in cm1n0 is transferred. ? in case of up-count operation: the tme nc1n count value is incremented by 1. remarks 1. transfer enable/disable can be set using the rlen1n bit of the tmc1n register. 2. the transfer operation can be combin ed with the interval operation. figure 9-26. example of tmenc1n oper ation when interval operation and transfer operation are combined tmenc1n and cm1n0 match & timer clear tmenc1n underflow & cm1n0 data transfer tmenc1n count value cm1n0 set value up count down count 0000h remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 455 (iii) compare function tmenc1n connects two compare register (c m1n0, cm1n1) channels and two capture/compare register (cc1n0, cc1n1) channels. when the tmenc1n count value and the set value of one of the compare registers match, a match interrupt (intcm1n0, intcm1n1, intcc1n0 note , intcc1n1 note ) is output. note this match interrupt is generated when cc1n0 and cc1n1 are set to the compare register mode. (iv) capture function tmenc1n connects two capture/compare register (cc1n0, cc1n1) channels. when cc1n0 and cc1n1 are set to the capture register mode, the value of tmenc1n is captured in synchronization with the corresponding capture trigger signal. when cc1n0 and cc1n1 are set to the capture re gister mode, a capture interrupt (intcc1n0, intcc1n1) is generated upon detec tion of the valid edge. chapter 9 timer/counter function (real-time pulse unit) 456 user?s manual u16031ej3v0ud (d) operation in udc mode b (i) basic operation the operations at the nex t count clock after the count value of tmenc1n and the cm1n0 set value match when tmenc1n is in udc mode b are as follows. ? in case of up-count operatio n: tmenc1n is cleared to 0000h and the intcm1n0 interrupt is generated. ? in case of down-count operation: the tme nc1n count value is decremented by 1. the operations at the nex t count clock after the count value of tmenc1n and the cm1n1 set value match when tmenc1n is in udc mode b are as follows. ? in case of up-count operation: the tm enc1n count value is incremented by 1. ? in case of down-count operation: tmenc1n is cleared to 0000h and the intcm1n1 interrupt is generated. figure 9-27. example of tmenc1n operation in udc mode cm1n0 set value cm1n1 set value tmenc1n count value clear tmenc1n not cleared if count clock counts down following match clear tmenc1n not cleared if count clock counts up following match remark n = 0, 1 (ii) compare function tmenc1n connects two compare register (c m1n0, cm1n1) channels and two capture/compare register (cc1n0, cc1n1) channels. when the tmenc1n count value and the set value of one of the compare registers match, a match interrupt (intcm1n0 (only during up-count op eration), intcm1n1 (only during down-count operation), intcc1n0 note , intcc1n1 note ) is output. note this match interrupt is generated when cc1n0 and cc1n1 are set to the compare register mode. (iii) capture function tmenc1n connects two capture/compare register (cc1n0, cc1n1) channels. when cc1n0 and cc1n1 are set to the capture register mode, the value of tmenc1n is captured in synchronization with the corresponding capture trigger signal. when cc1n0 and cc1n1 are set to the capture re gister mode, a capture interrupt (intcc1n0, intcc1n1) is generated upon detec tion of the valid edge. chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 457 9.3.7 supplementary descripti on of internal operation (1) clearing of count value in udc mode b when tmenc1n is in udc mode b, the count value clear operation is as follows. ? in case of tmenc1n up-count operation: tmenc1n is cleared upon match with cm1n0 ? in case of tmenc1n down-count operation: tmenc1n is cleared upon match with cm1n1 figure 9-28. clear operation upon match wit h cm1n0 during tmenc1n up-count operation count clock (rising edge set as valid edge) cm1n0 fffeh tmenc1n cleared (tmenc1n not cleared) tmenc1n ffffh 0000h (fffeh) 0001h (fffdh) ffffh up count up count (down count) remarks 1. n = 0, 1 2. the items in parentheses in the above figure apply to down-count operations. figure 9-29. clear operation upon match with cm1n1 during tmenc1n down-count operation count clock (rising edge set as valid edge) cm1n1 00ffh tmenc1n cleared (tmenc1n not cleared) tmenc1n 00feh 0000h (00ffh) ffffh (0100h) 00feh up count down count (up count) remarks 1. n = 0, 1 2. the items in parentheses in the above figure apply to up-count operations. chapter 9 timer/counter function (real-time pulse unit) 458 user?s manual u16031ej3v0ud (2) clearing of count value upon occurrence of compare match the internal operation during a tmenc 1n clear operation upon occurrence of a compare match is as follows. figure 9-30. count value clear operation upon compare match count clock (rising edge set as valid edge) cm1n0 fffeh tmenc1n cleared (tmenc1n not cleared) tmenc1n ffffh 0000h (fffeh) 0001h (fffdh) ffffh up count up count (down count) caution the operations at the next count clock a fter the count value of tmenc1n and the cm1n0 set value match are as follows. ? in case of up count: clear operation is performed. ? in case of down count: clear operation is not performed. remarks 1. n = 0, 1 2. the items in parentheses in the abov e figure apply to down-count operations. (3) transfer operation the internal operation during tmenc1n transfer operation is as follows. figure 9-31. internal operat ion during transfer operation count clock (rising edge set as valid edge) cm1n0 0001h transfer operation performed (transfer operation not performed) tmenc1n 0000h ffffh (0001h) fffeh (0002h) ffffh down count down count (up count) caution the count operations a fter the tmenc1n count value beco mes 0000h are as follows. ? in case of down count: transfer operation is performed. ? in case of up count: transfer ope ration is not performed. remarks 1. n = 0, 1 2. the items in parentheses in the abov e figure apply to up-count operations. chapter 9 timer/counter function (real-time pulse unit) user?s manual u16031ej3v0ud 459 (4) interrupt signal outpu t upon compare match an interrupt signal is output when the count value of tmenc1n matches the set value of the cm1n0, cm1n1, cc1n0 note , or cc1n1 note register. the interrupt generation timing is as follows. note when cc1n0 and cc1n1 are set to the compare register mode. figure 9-32. interrupt output upon compare match (cm1n1 with operation mode se t to general-purpose timer m ode and count clock set to f x /8) count clock f x /4 cm1n1 0007h tmenc1n internal match signal intcm1n1 0008h 000bh 0009h 0009h 000ah remark n = 0, 1 an interrupt signal such as the one illustrated in figur e 9-32 is output at the nex t count following a match of the tmenc1n count value and the set value of the corresponding compare register. (5) ubd1n flag (bit 0 of status1n register) operation in the udc mode (t1cmdn bit of tum1n register = 1), the ubd1n flag changes as follows during tmenc1n up-/down-count operation at every internal operation clock. figure 9-33. ubd1n flag operation count clock ubd1n 0001h 0000h tmenc1n 0000h 0001h 0001h 0000h remark n = 0, 1 chapter 9 timer/counter function (real-time pulse unit) 460 user?s manual u16031ej3v0ud (6) overflow interrupt signal (intov1n) and underflow interrupt signal (intud1n) (a) the overflow interrupt signal (intov1n) is gener ated when the count value of tmenc1n has reached ffffh and the next count oper ation is an up-count. (b) the underflow interrupt signal (intud1n) is gen erated when the count value of tmenc1n has reached 0000h and the next count operation is a down-count. (c) tmenc1n continues counting even after occurrence of an overflow or underflow, if a count edge is detected. if the condition of the underflow (0000h ffffh) is satisfied when the rlen1n bit of the tmc1n register is 1 (enabling transfer), howev er, the set value of cm1n0 is transferred. (d) if the condition of the underflow (0000h ffffh) is satisfied with cm1n0 = ffffh when the rlen1n bit of the tmc1n register is cleared to 0 (dis abling transfer), the intcm1n0 interrupt and intud1n interrupt occur simultaneously. user?s manual u16031ej3v0ud 461 chapter 10 serial interface function 10.1 features the serial interface function provides three types of seri al interfaces equipped with five transmit/receive channels of which four channels can be used simultaneously. the following three interface formats are available. (1) asynchronous serial interfaces b0 and b1 (uartb0 and uartb1): 2 channels (2) clocked serial interfaces 30 and 31 (csi30 and csi31): 2 channels (3) usb function controller (usbf): 1 channel remark for details of the usb function, see chapter 11 usb function controller (usbf) . uartb0 and uartb1, which use the method of transmitting/rece iving one byte of serial data following a start bit, enable full-duplex communication to be performed. csi30 and csi31 transfer data according to three types of signals (3-wire serial i/o). these signals are the serial clock (sck0 and sck1), serial input (si0 an d si1), and serial output (so0 and so1) signals. the usb supports full-speed transfer of 12 mbps and consists of seven endpoints. 10.1.1 switching between uartb0 and csi30 modes in the v850e/me2, since uartb0 and cs i30 are alternate function pins, they cannot be used at the same time. the registers must be set in advance. chapter 10 serial interface function 462 user?s manual u16031ej3v0ud 10.2 asynchronous serial interfaces b0, b1 (uartb0, uartb1) 10.2.1 features ? transfer rate: maximum 1.5 mbps (using a dedicated baud rate generator) ? full-duplex communications ? single mode and fifo mode selectable ? single mode: 8-bit 1-stage data register (ubntx register or ubnrx register) is used for each of transmission and reception. ? fifo mode transmit fifon: ubntx register (8 bits 16 stages). receive fifon: ubnr xap register (16 bits 16 stages) 2 bits of the higher 8 bits of the ubnrxap register are for an error flag. ? two-pin configuration txdn: transmit data output pin rxdn: receive data input pin ? reception error detection function ? overflow error (fifo mode only) ? parity error ? framing error ? overrun error (single mode only) ? interrupt sources: 5 types ? reception error interrupt (ubtiren) ? reception completion interrupt (ubtirn) ? transmission completion interrupt (ubtitn) ? fifo transmission completion inte rrupt (ubtifn) (fifo mode only) ? reception timeout interrupt (ubtiton) (fifo mode only) ? the character length of transmit/receive data is specified according to the ubnctl0 register ? character length: 7 or 8 bits ? parity functions: odd, even, 0, or none ? transmission stop bits: 1 or 2 bits ? msb first/lsb first selectable for transfer data ? on-chip dedicated baud rate generator remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 463 10.2.2 configuration uartbn is controlled by uartbn cont rol register 0 (ubnctl0), the uartbn status register (ubnstr), uartbn control register 2 (ubnctl2), uartbn fifo control register 0 (ubnfic0), uartbn fifo control register 1 (ubnfic1), uartbn fifo cont rol register 2 (ubnfic2), uartbn fifo st atus register 0 (ubnfis0), and uartbn fifo status register 1 (ubnfis1) (n = 0, 1). receive data is stored in a receiv e data register (the ubnrx register in the single mode or receive fifon in the fifo mode (the ubnrxap register)) and tr ansmit data is written to a transmit data register (the ubntx register in the single mode or transmit fifon in t he fifo mode). if a reception error (such as a parity error or a framing error) occurs in the fifo mode, the error data can be identified by reading uartbn receive data register ap (ubnrxap) in 16-bit (halfword) units. figure 10-1 shows the configuration of the asynchronous serial interface. (1) uartbn control register 0 (ubnctl0) (n = 0, 1) this register controls the transfer operation of uartbn. (2) uartbn status register (ubnstr) (n = 0, 1) this register indicates the transfer status during tr ansmission and the contents of a reception error. the status flag of this register, which indicates the transfe r status during transmission, indicates the data retention status of transmit shift register n and transmit data r egister n (the ubntx register in the single mode or transmit fifon in the fifo mode). each reception e rror flag is set to 1 when a reception error occurs, and cleared to 0 when 0 is written to the ubnstr register. (3) uartbn control register 2 (ubnctl2) (n = 0, 1) this register is used to specify the division rate by wh ich to control the baud rate (serial transfer speed) of uartbn. (4) uartbn fifo control regist er 0 (ubnfic0) (n = 0, 1) this register is used to select the operation mode of uartbn, clear t he transmit fifon/receive fifon that becomes valid in the fifo mode, and specify the timing mode in which the transmission completion interrupt (ubtitn)/reception completion interrupt (ubtirn) occurs. (5) uartbn fifo control regist er 1 (ubnfic1) (n = 0, 1) this register is valid in the fifo mode. it generates a reception timeout interrupt request (ubtiton) if data is stored in the receive fifon when t he next data does not come (start bi t is not detected) even after the reception wait time of the next data has elapsed. (6) uartbn fifo control regist er 2 (ubnfic2) (n = 0, 1) this register is valid in the fifo mode. it is used to set the timing to generate the transmission completion interrupt (ubtitn)/reception completi on interrupt (ubtirn), using the num ber of data transmitted or received as a trigger. (7) uartbn fifo status regist er 0 (ubnfis0) (n = 0, 1) this register is valid in the fifo mode. the number of bytes of data stored in the receive fifo can be read from this register. (8) uartbn fifo status regist er 1 (ubnfis1) (n = 0, 1) this register is valid in the fifo mode. the number of vacant bytes of the transmit fifon can be read from this register. chapter 10 serial interface function 464 user?s manual u16031ej3v0ud (9) receive shift register n (n = 0, 1) this is a shift register that converts the serial data that was input to the rxdn pin into parallel data. one byte of data is received, and if a stop bit is detected, the received data is tr ansferred to receive data register n. this register cannot be directly manipulated. (10) uartbn receive data register ap (ubnrxap), uartbn receive data register (ubnrx) (n = 0, 1) receive data register n holds receive dat a. in the single mode, the 8-bit 1-stage ubnrx register is used. the 16-bit 16-stage receive fifon (ubnrxap regist er) is used in the fifo mode. the receive data is stored in the lower 8 bits of the receive fifon (ubnrxap register) and the error information of the received data is stor ed in the higher 8 bits (bit 8 and bit 9). if a reception error (such as a parity error or a framing error) occurs in the fifo mode, the error data can be identified by reading the ubnrxap register in 16-bit (halfword) units (error information is appended as ubnpef bit = 1 or ubnfef bit = 1). when the lower 8 bits of the ubnrxap register are read in 8-bit (b yte) units, the higher 8 bits are discarded. therefore, if no error has occurred, the receive data of the ubnrxap register can be read consecutively by being read in 8-bit (byte) un its in the same way as the ubnrx register. when 7-bit length data is received with the lsb first, the re ceived data is transferred to bits 6 to 0 of receive data register n from the lsb (bit 0), with the msb (bit 7) always being 0. when data is received with the msb first, the received data is transferred to bits 7 to 1 of re ceive data register n from the msb (bit 7), with the lsb (bit 0) always being 0. if an overrun error occurs, the receive data at that time is not transferred to receive data register n. while reception is enabled, the received data is trans ferred from receive shift register n to receive data register n, in synchronization with the shift-in processing of one frame. a reception completion interrupt request (ubtirn) is generated by transferring the data to the ubnrx register in the single mode, or transferring the number of receive data set as the trigger by the ubnrt3 to ubnrt0 bits of the ubnfic2 register to receive fifon in the fifo mode. if data is stored in receive fifon when the next data does not come (start bit is not detec ted) after the next data reception wait time specified by the ubntc4 to ubntc0 bits of the ubnfic1 register has elapsed in the fifo mode, a reception timeout interrupt request (ubtiton) is generated. (11) transmit shift register n (n = 0, 1) this is a shift register that converts the parallel data that was transferred from transmit data register n into serial data. when one byte of data is transferred from transmit data regi ster n, transmit shift register n data is output from the txdn pin. this register cannot be directly manipulated. chapter 10 serial interface function user?s manual u16031ej3v0ud 465 (12) uartbn transmit data register n (ubntx) (n = 0, 1) transmit data register n is a buffe r for transmit data. the 8-bit 1-stage ubntx register is used as this buffer in the single mode. in the fifo mode, the 8-bit 16-stage transmit fifon is used. when 7-bit length data is transmitted with the lsb first, bi ts 6 to 0 of transmit dat a register n are transmitted as the transmit data from the lsb (bit 0) with the msb (bit 7) always bei ng 0. when data is transmitted with the msb first, bits 7 to 1 of transmit data register n ar e transmitted as the transmit data from the msb (bit 7) with the lsb (bit 0) always being 0. in the single mode, transmission is st arted by writing transmit data to t he ubntx register while transmission is enabled (ubntxe bit = 1 in the ubnctl0 register). when writing the transmit data to the ubntx register is enabled (when 1-byte data is transferred from t he ubntx register to transmit shift register n), a transmission completion interrupt request (ubtitn) is generated. in the fifo mode, transmission is star ted by writing at least the number of transmit data set as the trigger by the ubntt3 to ubntt0 bits of the ubnfic2 register and 16 bytes or less to transmit fifon and then enabling transmission (ubntxe bit = 1). when the number of transmit data set as the trigger by the ubntt3 to ubntt0 bits of the ubnfic2 register have been transf erred from transmit fifon to transmit shift register n (transmit data of the number set as the trigger can be written), a transmission completion interrupt request (ubtitn) is generated. in the fifo mode, a fifo transmission completion interrupt request (ubtifn) is generated when there is no more data in transmit fi fon and transmit shift register n (when fifon and the register become empty). (13) timeout counter this counter is used to recognize that data exists (remains) in rece ive fifon when the number of received data does not reach the number set as the trigger by th e ubnrt3 to ubnrt0 bits of the ubnfic2 register, and is valid only in the fifo mode. if data is stored in receive fifon w hen the next data does not come (start bit is not detected) after the next data reception wait time specified by the ubntc4 to ubntc0 bits of t he ubnfic1 register has elapsed after the stop bit has been received, a reception tim eout interrupt request (ubtiton) is generated. chapter 10 serial interface function 466 user?s manual u16031ej3v0ud (14) sampling block this block samples the rxdn signal at the rising edge of the input clock (f x /4) (f x : main clock). if the same sampling value is detected two time s, output of the match detector ch anges, and the value is sampled as input data. data of less than one clock width is judged as noise and is not transmitted to the internal circuitry. figure 10-1. block diagra m of asynchronous serial interfaces b0 and b1 rxdn internal bus receive shift register n uartbn control register 0 (ubnctl0) uartbn control register 2 (ubnctl2) uartbn status register (ubnstr) uartbnfifo control register 0 (ubnfic0) uartbnfifo control register 1 (ubnfic1) uartbnfifo control register 2 (ubnfic2) uartbnfifo status register 0 (ubnfis0) uartbnfifo status register 1 (ubnfis1) ubnrx receive fifon timeout counter sampling block receive controller transmit controller baud rate generator n reception unit transmission unit baud rate generator n transmit shift register n ubntx transmit fifon ubtiton txdn ubtifn ubtitn ubtirn ubtiren f x /4 remarks 1. n = 0, 1 2. f x : main clock chapter 10 serial interface function user?s manual u16031ej3v0ud 467 10.2.3 control registers (1) uartbn control register 0 (ubnctl0) (n = 0, 1) the ubnctl0 register controls t he transfer operations of uartbn. this register can be read or written in 8-bit or 1-bit units. cautions 1. when using uartbn, set the external pins related to the uartbn function in the control mode, set uartbn control register 2 (ubnctl2). then set the ubnpwr bit to 1 before setting the other bits. 2. be sure to input a high level to the rxdn pin when se tting the external pins related to the uartbn function in the cont rol mode. if a low level is input, it is judged that a falling edge is input after the ubnrxe bit has been set to 1, and reception may be started. (1/3) ub0pwr ub1pwr ub0ctl0 ub1ctl0 ub0txe ub1txe 5 ub0rxe ub1rxe ub0dir ub1dir 3 ub0ps1 ub1ps1 2 ub0ps0 ub1ps0 1 ub0cl ub1cl ub0sl ub1sl address fffffa00h fffffa20h after reset 10h 10h 0 4 6 7 bit position bit name function 7 ubnpwr controls the operation clock. 0: stops supply of clocks to uartbn 1: supplies clocks to uartbn cautions 1. when the ubnpwr bit is cleared to 0, the uartbn can be asynchronously reset. 2. when ubnpwr = 0, the uartbn is in a reset state. therefore, to operate uartbn, the ubnpwr bit must be set to 1. 3. when the ubnpwr bit is changed from 1 to 0, all registers of the uartbn are initialized. when the ubnpwr is set to 1 again, the uartbn registers must be set again. the txdn pin output is high level when the ubnpwr bit is cleared to 0. 6 ubntxe specifies whether transmission is enabled or disabled. 0: transmission is disabled 1: transmission is enabled cautions 1. on startup, set ubnpwr to 1 and then set ubntxe to 1. to stop transmission, clear ubntxe to 0 and then ubnpwr to 0. 2. when the transmission unit status is to be initialized, the transmission status may not be able to be initialized unless the ubntxe bit is set to 1 again after an interval of two cycles of f x /4 (f x : main clock) has elapsed since the ubntxe bit was cleared to 0. remark n = 0, 1 chapter 10 serial interface function 468 user?s manual u16031ej3v0ud (2/3) bit position bit name function 5 ubnrxe specifies whether reception is enabled or disabled. 0: reception is disabled 1: reception is enabled cautions 1. on startup, set ubnpwr to 1 and then set ubnrxe to 1. to stop reception, clear ubnrxe to 0 and then ubnpwr to 0. 2. when the reception unit status is to be initialized, the reception status may not be able to be initialized unless the ubnrxe bit is set to 1 again after an interval of two cycles of f x /4 (f x : main clock) has elapsed since the ubnrxe bit was cleared to 0. 4 ubndir specifies the transfer direction mode (msb/lsb). 0: the first bit of transfer data is the msb. 1: the first bit of transfer data is the lsb. caution clear the ubnpwr bit or ubntxe and ubnrxe bits to 0 before changing the setting of the ubndir bit. controls the parity bit. ubnps1 ubnps0 transmit operation receive operation 0 0 do not output a parity bit receive with no parity 0 1 output 0 parity receive as 0 parity 1 0 output odd parity judge as odd parity 1 1 output even parity judge as even parity 3, 2 ubnps1, ubnps0 cautions 1. clear the ubntxe and ubnrxe bits to 0 before overwriting the ubnps1 and ubnps0 bits. 2. if ?0 parity? is selected for reception, no parity judgment is made. therefore, no error interrupt is generated because the ubnpe bit of the ubnstr register is not set to 1. ? ? chapter 10 serial interface function user?s manual u16031ej3v0ud 469 (3/3) bit position bit name function 3, 2 ubnps1, ubnps0 ? 0 parity during transmission, the parity bit is clear ed to 0 regardless of the transmit data. during reception, no parity error is generated because no parity bit is checked. ? no parity no parity bit is added to transmit data. during reception, the receive data is considered to have no parity bit. no parity error is generated because there is no parity bit. 1 ubncl specifies the character length of the transmit/receive data. 0: 7 bits 1: 8 bits caution clear the ubntxe and ubnrxe bits to 0 before overwriting the ubncl bit. 0 ubnsl specifies the stop bit length of the transmit data. 0: 1 bit 1: 2 bits cautions 1. clear the ubntxe bit to 0 before overwriting the ubnsl bit. 2. since reception always operates by using a single stop bit length, the ubnsl bit setting does not affect receive operations. remarks 1. when reception is disabled, receive shift regist er n does not detect a start bit. no shift-in processing or transfer processing to receive dat a register n is performed, and the contents of receive data register n are retained. when reception is enabled, the receive shi ft operation starts, in sy nchronization with the detection of the start bit, and when the receptio n of one frame is comple ted, the contents of receive shift register n are transferred to rece ive data register n. a reception completion interrupt (ubtirn) is also generated, in synchroni zation with the transfer to receive data register n (in fifo mode, transfer triggered by reaching set number of receive data). if data is stored in receive fifon when the nex t data does not come (start bit is not detected) after the next data reception wait time specifi ed by the ubntc4 to ubntc0 bits of the ubnfic1 register has elapsed in the fifo mode, a rece ption timeout interrupt request (ubtiton) is generated. 2. n = 0, 1 chapter 10 serial interface function 470 user?s manual u16031ej3v0ud (2) uartbn status register (ubnstr) (n = 0, 1) the ubnstr register indicates the transfer status and reception error contents while uartbn is transmitting data. the status flag that indicates the transfer status during transmission indi cates the data retention status of transmit shift register n and transmit data register n (t he ubntx register in the single mode or transmit fifon in the fifo mode). the status flag t hat indicates a reception error holds it s status until it is cleared to 0. this register can be read or written in 8-bit or 1-bit units. caution when the ubnpwr bit or ubn rxe bit of the ubnctl0 register is cleared to 0, or when 0 is written to the ubnstr register, the ubno vf, ubnpe, ubnfe, and ubnove bits of the ubnstr register are cleared to 0. (1/2) ub0tsf ub1tsf ub0str ub1str 0 0 5 0 0 0 0 3 ub0ovf ub1ovf 2 ub0pe ub1pe 1 ub0fe ub1fe ub0ove ub1ove address fffffa04h fffffa24h after reset 00h 00h 0 4 6 7 bit position bit name function 7 ubntsf this is a status flag indicating the transfer status. ? in single mode (ubnmod bit = 0 in the ubnfic0 register) 0: data to be transferred to transmit shi ft register n and ubntx register does not exist (cleared (0) when ubnpwr bit = 0 or ub ntxe bit = 0 in the ubnctl0 register). 1: data to be transferred to transmit shift register n or ubntx register exists (transmission in progress). ? in fifo mode (ubnmod bit = 1 in the ubnfic0 register) 0: data to be transferred to transmit shift register n and transmit fifon does not exist (cleared (0) when ubnpwr bit = 0 or ub ntxe bit = 0 in the ubnctl0 register). 1: data to be transferred to transmit shift register n and transmit fifon exists (transmission in progress). caution the value of the ubntsf bit is reflected after two periods of f x /4 (f x : main clock) have elapsed, after the transmit data is written to the ubntx register. therefore, exercise care when referencing the ubntsf bit after transmit data has been written to the ubntx register. 3 ubnovf this is a status flag indicating an overflow . the setting of this flag is valid only in the fifo mode (when ubnmod bit = 1 in the ubnfic0 register), and invalid in the single mode (when ubnmod bit = 0 in the ubnfic0 register). 0: overflow did not occur. 1: overflow occurred (during reception). caution if an overflow occurs, the received data is not written to receive fifon but discarded. remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 471 (2/2) bit position bit name function 2 ubnpe this is a status flag that indicates a parit y error. the setting of this flag is valid only in the single mode (when ubnmod bit = 0 in the ubnfic0 register), and invalid in the fifo mode (when ubnmod bit = 1 in the ubnfic0 register). 0: parity error did not occur. 1: parity error occurred (during reception). caution the operation of the ubnpe bit differs according to the settings of the ubnps1 and ubnps0 bits of the ubnctl0 register. 1 ubnfe this is a status flag that indicates a frami ng error. the setting of this flag is valid only in the single mode (when ubnmod bit = 0 in the ubnfic0 register), and invalid in the fifo mode (when ubnmod bit = 1 in the ubnfic0 register). 0: framing error did not occur. 1: framing error occurred (during reception). caution only the first bit of the stop bits of the receive data is checked, regardless of the stop bit length. 0 ubnove this is a status flag that indicates an overr un error. the setting of this flag is valid only in the single mode (when ubnmod bit = 0 in the ubnfic0 register), and invalid in the fifo mode (when ubnmod bit = 1 in the ubnfic0 register). 0: overrun error did not occur. 1: overrun error occurred (during reception). caution when an overrun error occurs, the next receive data value is not written to the ubnrx register and the data is discarded. remark n = 0, 1 chapter 10 serial interface function 472 user?s manual u16031ej3v0ud (3) uartbn control register 2 (ubnctl2) (n = 0, 1) the ubnctl2 register is used to specify the division ra tio by which to control the baud rate (serial transfer speed) of uartbn. this register can be read or written in 16-bit units. caution when rewriting the ubn brs15 to ubnbrs0 bits of this register, clear the ubntxe and ubnrxe bits of the ubnctl0 register to 0 or clear the ubnpwr bit (n = 0, 1). 14 ub0 brs 14 13 ub0 brs 13 12 ub0 brs 12 2 ub0 brs 2 3 ub0 brs 3 4 ub0 brs 4 5 ub0 brs 5 6 ub0 brs 6 7 ub0 brs 7 8 ub0 brs 8 9 ub0 brs 9 10 ub0 brs 10 11 ub0 brs 11 15 ub0 brs 15 1 ub0 brs 1 0 ub0 brs 0 ub0ctl2 address fffffa02h after reset ffffh ub1 brs 14 ub1 brs 13 ub1 brs 12 ub1 brs 2 ub1 brs 3 ub1 brs 4 ub1 brs 5 ub1 brs 6 ub1 brs 7 ub1 brs 8 ub1 brs 9 ub1 brs 10 ub1 brs 11 ub1 brs 15 ub1 brs 1 ub1 brs 0 ub1ctl2 fffffa22h ffffh bit position bit name function 15 to 0 ubnbrs15 to ubnbrs0 specify the division value of the 16-bit counter (see table 10-1 ). remark n = 0, 1 table 10-1. division value of 16-bit counter ubnb rs15 ubnb rs14 ubnb rs13 ubnb rs12 ubnb rs11 ubnb rs10 ubnb rs9 ubnb rs8 ubnb rs7 ubnb rs6 ubnb rs5 ubnb rs4 ubnb rs3 ubnb rs2 ubnb rs1 ubnb rs0 k output clock selected 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 4 f x /(4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? chapter 10 serial interface function user?s manual u16031ej3v0ud 473 (4) uartbn transmit data re gister (ubntx) (n = 0, 1) the ubntx register is used to set transmit data. it functions as the 8-bit 1-stage ubntx register, in the single mode (ubnmod bit = 0 in the ubnfic0 register), and as the 8-bit 16-stage transmit fifon in the fifo mode (ubnmod bit = 1 in the ubnfic0 register). in the single mode, transmission is started by writing transmit data to the ubntx register when transmission is enabled (the ubntxe bit = 1 in the ubnctl0 register). when data can be written to the ubntx register (when 1 byte of data is transferred from the ubntx register to transmit shift register n), a transmission completion interrupt request (ubtitn) is generated. in the fifo mode, transmission is st arted by enabling transmission (ubntxe bi t = 1) after writing at least the number of transmit data set as the trigger by the ubnt t3 to ubntt0 bits of the ubnfic2 register and 16 bytes or less to transmit fifon. when the number of transmit data set as the trigger by the ubntt3 to ubntt0 bits of the ubnfic2 register have been transferr ed from transmit fifon to transmit shift register n (transmit data of the number set as the trigger can be written to transmit fifon), a transmission completion interrupt request (ubtitn) is generated. in the fifo mode, a fifo transmission completion interrupt request (ubtifn) is generated when there is no more data in transmit fifon and transmit shift register n (when the fifon and register become empty). for the generation timing of the interrupt, see 10.2.4 interrupt requests . when 7-bit length data is transmitted with the lsb first, bi ts 6 to 0 of transmit dat a register n are transmitted as the transmit data from the lsb (bit 0) with the msb (bit 7) always bei ng 0. when data is transmitted with the msb first, bits 7 to 1 of transmit data register n ar e transmitted as the transmit data from the msb (bit 7) with the lsb (bit 0) always being 0. this register is write-only, in 8-bit units. data is written to transmit data register n. ub0td7 ub1td7 ub0tx ub1tx ub0td6 ub1td6 5 ub0td5 ub1td5 ub0td4 ub1td4 3 ub0td3 ub1td3 2 ub0td2 ub1td2 1 ub0td1 ub1td1 ub0td0 ub1td0 address fffffa08h fffffa28h after reset ffh ffh 0 4 6 7 bit position bit name function 7 to 0 ubntd7 to ubntd0 write transmit data. remark n = 0, 1 chapter 10 serial interface function 474 user?s manual u16031ej3v0ud (5) uartbn receive data register ap (ubnrxap), uartbn receive data regist er (ubnrx) (n = 0, 1) these registers store parallel data converted by rece ive shift register n. they function as the 8-bit 1-stage ubnrx register, in the single mode (ubnmod bit = 0 in the ubnfic0 regist er), and as the 16-bit 16-stage receive fifon (ubnrxap register) in the fifo mode (ubnmod bit = 1 in the ubnfic0 register). the receive data is stored in the lower 8 bits of the receive fifon (ubnrxap register) and the error information of the received data is stor ed in the higher 8 bits (bit 8 and bit 9). if a reception error (such as a parity error or a framing error) occurs in the fifo m ode, the ubnrxap register is read in 16-bit (halfword) units. in this way, the flag of the data stored in re ceive fifon can be checked (error information is appended as ubnpef bit = 1 or ubnfef bit = 1), so that the erro r data can be recognized (when the lower 8 bits of the ubnrxap register are read in 8-bit (byt e) units, the higher 8 bits are disc arded. therefore, if no error has occurred, the receive data of the ub nrxap register can be read consecutivel y by being read in 8-bit (byte) units in the same way as the ubnrx register). if reception is enabled (ubnrxe bit = 1 in the ubnctl0 regi ster), the receive data is transferred from receive shift register n to receive data register n, in synchroni zation with the completion of the shift-in processing of one frame. by transferring the receive data to the ubnrx register in the single mode or by transferring the number of receive data set as the trigger by the ubnrt3 to ubnrt0 bits of the ubnfic2 register to the receive fifon in the fifo mode, a reception completion interrupt reques t (ubtirn) is generated. if data is stored in receive fifon when the next data does not come (start bit is not detected) even after the next data reception wait time specified by the ubntc4 to ubntc0 bits of the ubnfic1 regist er has elapsed in the fifo mode, a reception timeout interrupt request (ubtiton) is generated. for information about the timing for gener ating these interrupt requests, see 10.2.4 interrupt requests . if data is received with the lsb first when the data l ength is specified as 7 bits, the received data is transferred to bits 6 to 0 of receive data register n from the lsb (bit 0), with the msb (bit 7) always being 0. if data is received with the msb first, it is transferred to bits 7 to 1 of receive data register n from the msb (bit 7) with the lsb (bit 0) always being 0. however, if an overrun error occurs, t he receive data at that time is not transferred to receive data register n. the ubnrxap register is read-only, in 16-bit units. however, the lower 8 bits of the ubnrxap register are read-only, in 8-bit units. the ubnrx register is read-only, in 8-bit units. in addition to reset input, the value of these registers can be set to ffh in the single mode or to 00ffh in the fifo mode, by clearing the ubnpwr bi t of the ubnctl0 register to 0. cautions 1. the ubnpef and ubnfef bits cannot be read because these regi sters serve as 8-bit registers in the single mode. 2. when no reception error has occurred in the fifo mode , the receive data of the ubnrxap register can be re ad consecutively by reading the lower 8 bits of the ubnrxap register in 8-bit (byte) units. an 8- bit access to the higher 8 bits is prohibited. if they are accessed, the operation is not guaranteed. 3. do not set a break to the instruction immediately after r eading the ubnrx register when debugging a system that uses single mode; ot herwise an overrun error may occur in subsequent receptions. chapter 10 serial interface function user?s manual u16031ej3v0ud 475 14 0 13 0 12 0 2 ub0 rd2 3 ub0 rd3 4 ub0 rd4 5 ub0 rd5 6 ub0 rd6 7 ub0 rd7 8 ub0 fef 9 ub0 pef 10 0 11 0 15 0 1 ub0 rd1 0 ub0 rd0 ub0rxap address fffffa06h after reset 00ffh 000 ub1 rd2 ub1 rd3 ub1 rd4 ub1 rd5 ub1 rd6 ub1 rd7 ub1 fef ub1 pef 0 0 0 ub1 rd1 ub1 rd0 ub1rxap fffffa26h 00ffh [uartbn receive data register ap] [uartbn receive data register] 2 ub0 rd2 3 ub0 rd3 4 ub0 rd4 5 ub0 rd5 6 ub0 rd6 7 ub0 rd7 1 ub0 rd1 0 ub0 rd0 ub0rx address fffffa06h after reset ffh ub1 rd2 ub1 rd3 ub1 rd4 ub1 rd5 ub1 rd6 ub1 rd7 ub1 rd1 ub1 rd0 ub1rx fffffa26h ffh bit position bit name function 9 (ubnrxap) ubnpef this is a status flag that indicates a parity error. status is valid only in the fifo mode (ubnmod bit = 1 in the ubnfic0 register), and is invalid in the single mode (ubnmod bit = 0 in the ubnfic0 register). 0: no parity error 1: parity error occurs (during reception). caution the operation of the ubnpef bit differs depending on the set values of the ubnps1 and ubnps0 bits of the ubnctl0 register. 8 (ubnrxap) ubnfef this is a status flag indicating a framing error. status is valid only in the fifo mode (ubnmod bit = 1 in the ubnfic0 register), and is invalid in the single mode (ubnmod bit = 0 in the ubnfic0 register). 0: no framing error 1: framing error occurs (during reception). caution only the first bit of the stop bits of the receive data is checked, regardless of the stop bit length. 7 to 0 ubnrd7 to ubnrd0 stores receive data. remark n = 0, 1 chapter 10 serial interface function 476 user?s manual u16031ej3v0ud (6) uartbn fifo control regist er 0 (ubnfic0) (n = 0, 1) the ubnfic0 register is used to sele ct the operation mode of uartbn and the functions that become valid in the fifo mode (ubnmod bit = 1). in the fifo mode, it clears transmit fifon/ receive fifon and specifies the timing mode in which the transmission completion interrupt (ubtitn)/reception completion interrupt (ubtirn) is generated. this register can be read or written in 8-bit or 1-bit units. (1/2) ub0mod ub1mod ub0fic0 ub1fic0 5 0 0 0 0 3 ub0tfc ub1tfc 2 ub0rfc ub1rfc 1 ub0itm ub1itm ub0irm ub1irm address fffffa0ah fffffa2ah after reset 00h 00h 0 4 6 0 0 7 bit position bit name function 7 ubnmod specifies an operation mode of uartbn. 0: single mode 1: fifo mode 3 ubntfc this is a transmit fifon clear trigger bit. the setting of this bit is valid only in the fifo mode (ubnmod bit = 1) and invalid in the single mode (ubnmod bit = 0). 0: normal status 1: clear (this bit automatically returns to 0 after transmit fifon is cleared.) when 1 is written to the ubntfc bit, the pointer to transmit fifon is cleared to 0. in the pending mode (ubnitm bit = 0), the interr upt request (ubtitn) held pending is cleared note . however, bit 7 (utifn) of the interrupt control register (uticn) is not cleared to 0. clear this bit to 0 as necessary. when 0 is written to the ubntfc bit, the status is retained. no operation, such as clearing or setting, is executed. note after transmit fifon is cleared (ubntfc bit = 1), accessing the registers related to uartb is prohibited for the duration of four cycles of f x /4 (f x : main clock) or until clearing the ubntfc bit (automatic re covery) is confirmed by reading the ubnfic0 register. if these register s are accessed, the operation is not guaranteed. caution when writing 1 to the ubntfc bit, be sure to clear the ubntxe bit of the ubnctl0 register to 0 (disabling transmission). if 1 is written to the ubntfc bit when the ubntxe bit is 1 (transmission enabled), the operation is not guaranteed. remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 477 (2/2) bit position bit name function 2 ubnrfc this is a receive fifon (ubnrxap) clear tr igger bit. the setting of this bit is valid only in the fifo mode (ubnmod bit = 1) and invalid in the single mode (ubnmod bit = 0). 0: normal status 1: clear (this bit automatically return s to 0 after receive fifon is cleared.) when 1 is written to the ubnrfc bit, the pointer to receive fifon is cleared to 0. in the pending mode (ubnirm bit = 0), the interr upt request (ubtirn) held pending is cleared note . however, bit 7 (urifn) of the interrupt control register (uricn) is not cleared to 0. clear this bit to 0 as necessary. when 0 is written to the ubnrfc bit, the status is retained. no operation, such as clearing or setting, is executed. note after receive fifon (ubnrxap) is cleared (ubnrfc bit = 1), accessing the registers related to uartb is prohibited for the duration of four cycles of f x /4 (f x : main clock) or until clearing the ubnrfc bit (automatic recovery) is confirmed by reading the ubnfic0 register. if these regi sters are accessed, the operation is not guaranteed. caution when writing 1 to the ubnrfc bit, be sure to clear the ubnrxe bit of the ubnctl0 register to 0 (disabling recep tion). if 1 is written to the ubnrfc bit when the ubnrxe bit is 1 (reception enabled), the operation is not guaranteed. 1 ubnitm this bit specifies the timing mode in wh ich the ubtitn interrupt is generated in fifo mode. 0: pending mode 1: pointer mode in the fifo mode, the ubtitn interrupt is generated as soon as transmit data of the number set as the trigger by the ubntt3 to ubntt0 bits of the ubnfic2 register have been transferred from transmit fifon to transm it shift register n. after the ubtitn interrupt request has been generated, specify the timing of actually generating the ubtitn interrupt as the pending mode or pointer mode. for details, refer to 10.2.5 (2) pending mode/pointer mode . 0 ubnirm this bit specifies the timing mode in wh ich the ubtirn interrupt is generated in fifo mode. 0: pending mode 1: pointer mode in the fifo mode, the ubtirn interrupt is generated as soon as receive data of the number set as the trigger by the ubnrt3 to ubnrt0 bits of the ubnfic2 register have been transferred from receive shift register n to receive fifon. after the ubtirn interrupt request has been generated, specify the timing of actually generating the ubtirn interrupt as the pending mode or pointer mode. for details, refer to 10.2.5 (2) pending mode/pointer mode . remark n = 0, 1 chapter 10 serial interface function 478 user?s manual u16031ej3v0ud (7) uartbn fifo control regist er 1 (ubnfic1) (n = 0, 1) the ubnfic1 register is valid in t he fifo mode (ubnmod bit = 1 in the ubnfic0 register). it generates a reception timeout interrupt request (ubtiton) if data is stored in receive fifon when the next data does not come (start bit is not detected) after the lapse of t he time set by the ubntc4 to ubntc0 bits (next data reception wait time), after the stop bit has been received. this register can be read or written in 8-bit or 1-bit units. ub0tce ub1tce ub0fic1 ub1fic1 5 0 0 ub0tc4 ub1tc4 3 ub0tc3 ub1tc3 2 ub0tc2 ub1tc2 1 ub0tc1 ub1tc1 ub0tc0 ub1tc0 address fffffa0bh fffffa2bh after reset 00h 00h 0 4 6 0 0 7 bit position bit name function 7 ubntce specifies the timeout counter function. 0: disable use of timeout counter function. 1: enable use of timeout counter function. specify the time to wait for the next data reception. ubn tc4 ubn tc3 ubn tc2 ubn tc1 ubn tc0 next data reception wait time 0 0 0 0 0 32 bytes (32 8 / baud rate) 0 0 0 0 1 31 bytes (31 8 / baud rate) 0 0 0 1 0 30 bytes (30 8 / baud rate) 0 0 0 1 1 29 bytes (29 8 / baud rate) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 1 0 0 4 bytes (4 8 / baud rate) 1 1 1 0 1 3 bytes (3 8 / baud rate) 1 1 1 1 0 2 bytes (2 8 / baud rate) 1 1 1 1 1 1 byte (1 8 / baud rate) 4 to 0 ubntc4 to ubntc0 caution when the count set by the ubntc4 to ubntc0 bits is up, the count value of the timeout counter is cleared to 0, regardless of the status of the data stored in receive fifon. when the next start bit is later detected, counting is started again from the stop bit of that data. remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 479 (8) uartbn fifo control regist er 2 (ubnfic2) (n = 0, 1) the ubnfic2 register is valid in the fifo mode (ubnmod bit = 1 in the ubnf ic0 register). it sets the timing of generating an interrupt, using the number of transmit/r eceive data as a trigger. when data is transmitted, the number of data transferred from transmit fifon is specified as the condition of generating the interrupt. when data is received, the number of data stored in receive fifon is specified as the interrupt generation condition. this register can be read or written in 16-bit units. when the higher 8 bits of the ubnfic 2 register can be used as the ubnfic 2h register and the lower 8 bits, as the ubnfic2l register, these registers can be read or written in 8-bit units. caution be sure to clear the ubntxe bit (to disable transmission) and ubnrxe bit (to disable reception) of the ubnctl0 register to 0 before writing data to the ubnfi c2 register. if data is written to the ubnfic2 register with the ub ntxe or ubnrxe bit set to 1, the operation is not guaranteed. chapter 10 serial interface function 480 user?s manual u16031ej3v0ud (1/2) 14 0 13 0 12 0 2 ub0 rt2 3 ub0 rt3 4 0 5 0 6 0 7 0 8 ub0 tt0 9 ub0 tt1 10 ub0 tt2 11 ub0 tt3 15 0 1 ub0 rt1 0 ub0 rt0 ub0fic2 address fffffa0ch after reset 0000h 000 ub1 rt2 ub1 rt3 0 0 0 0 ub1 tt0 ub1 tt1 ub1 tt2 ub1 tt3 0 ub1 rt1 ub1 rt0 ub1fic2 fffffa2ch 0000h bit position bit name function set the number of transmit fifon transmit data to be the trigger. each time data of the specified number has shifted out from transmit fifon to transmit shift register n, the ubtitn interrupt is generated. in the pending mode (ubnitm bit = 0 in the ubnfic0 register), the ubtitn interrupt is generated under the conditions of the pending mode. ubn tt3 ubn tt2 ubn tt1 ubn tt0 number of data of transmit fifon set as trigger pointer mode pending mode 0 0 0 0 1 byte settable 0 0 0 1 2 bytes 0 0 1 0 3 bytes 0 0 1 1 4 bytes 0 1 0 0 5 bytes 0 1 0 1 6 bytes 0 1 1 0 7 bytes 0 1 1 1 8 bytes 1 0 0 0 9 bytes 1 0 0 1 10 bytes 1 0 1 0 11 bytes 1 0 1 1 12 bytes 1 1 0 0 13 bytes 1 1 0 1 14 bytes 1 1 1 0 15 bytes 1 1 1 1 16 bytes setting prohibited settable 11 to 8 ubntt3 to ubntt0 caution in the pointer mode (ubnitm bit = 1 in the ubnfic0 register), the number of transmit data set as the trigger can be only 1 byte (ubntt3 to ubntt0 bits = 0000), and other settings are prohibited. if a setting of other than 1 byte is made, the operation is not guaranteed. remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 481 (2/2) bit position bit name function set the number of receive fifon receive data to be the trigger. each time data of the specified number has been stored from receive shift register n to receive fifon, the ubtir interrupt is generated. in the pending mode (ubnitm bit = 0 in the ubnfic0 register), the ubtirn interrupt is generated under the conditions of the pending mode. ubn rt3 ubn rt2 ubn rt1 ubn rt0 number of data of receive fifon set as trigger pointer mode pending mode 0 0 0 0 1 byte settable 0 0 0 1 2 bytes 0 0 1 0 3 bytes 0 0 1 1 4 bytes 0 1 0 0 5 bytes 0 1 0 1 6 bytes 0 1 1 0 7 bytes 0 1 1 1 8 bytes 1 0 0 0 9 bytes 1 0 0 1 10 bytes 1 0 1 0 11 bytes 1 0 1 1 12 bytes 1 1 0 0 13 bytes 1 1 0 1 14 bytes 1 1 1 0 15 bytes 1 1 1 1 16 bytes setting prohibited settable 3 to 0 ubnrt3 to ubnrt0 caution in the pointer mode (ubnirm bit = 1 in the ubnfic0 register), the number of receive data set as the trigger can be only 1 byte (ubnrt3 to ubnrt0 bits = 0000), and other settings are prohibited. if a setting of other than 1 byte is made, the operation is not guaranteed. remark n = 0, 1 chapter 10 serial interface function 482 user?s manual u16031ej3v0ud (9) uartbn fifo status regist er 0 (ubnfis0) (n = 0, 1) the ubnfis0 register is valid in t he fifo mode (ubnmod bit = 1 in the ubnfic0 register). it is used to read the number of bytes of the da ta stored in receive fifon. this register is read-only, in 8-bit units. 0 0 ub0fis0 ub1fis0 5 0 0 ub0rb4 ub1rb4 3 ub0rb3 ub1rb3 2 ub0rb2 ub1rb2 1 ub0rb1 ub1rb1 ub0rb0 ub1rb0 address fffffa0eh fffffa2eh after reset 00h 00h 0 4 6 0 0 7 bit position bit name function indicates the number of bytes (readable bytes) of the data stored in receive fifon as a receive fifon pointer. ubn rb4 ubn rb3 ubn rb2 ubn rb1 ubn rb0 receive fifon pointer 0 0 0 0 0 0 bytes 0 0 0 0 1 1 byte 0 0 0 1 0 2 bytes 0 0 0 1 1 3 bytes 0 0 1 0 0 4 bytes 0 0 1 0 1 5 bytes 0 0 1 1 0 6 bytes 0 0 1 1 1 7 bytes 0 1 0 0 0 8 bytes 0 1 0 0 1 9 bytes 0 1 0 1 0 10 bytes 0 1 0 1 1 11 bytes 0 1 1 0 0 12 bytes 0 1 1 0 1 13 bytes 0 1 1 1 0 14 bytes 0 1 1 1 1 15 bytes 1 0 0 0 0 16 bytes other than above invalid 4 to 0 ubnrb4 to ubnrb0 remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 483 (10) uartbn fifo status register 1 (ubnfis1) (n = 0, 1) the ubnfis1 register is valid in the fifo mode (ubnmod bit = 1 in the ubnfic0 register). this register can be used to read the number of vacant bytes of transmit fifon. this register is read-only, in 8-bit units. caution the values of the ubntb4 to ubntb0 bits are reflected after transmit data has been written to the ubntx register and th en time of two cycles of f x /4 (f x : main clock) has passed. therefore, care must be exerci sed when referencing the ubnfi s1 register after transmit data has been written to the ubntx register. 0 0 ub0fis1 ub1fis1 5 0 0 ub0tb4 ub1tb4 3 ub0tb3 ub1tb3 2 ub0tb2 ub1tb2 1 ub0tb1 ub1tb1 ub0tb0 ub1tb0 address fffffa0fh fffffa2fh after reset 10h 10h 0 4 6 0 0 7 bit position bit name function indicates the number of vacant bytes of transmit fifon (bytes that can be written) as a transmit fifon pointer. ubn tb4 ubn tb3 ubn tb2 ubn tb1 ubn tb0 transmit fifon pointer 0 0 0 0 0 0 bytes 0 0 0 0 1 1 byte 0 0 0 1 0 2 bytes 0 0 0 1 1 3 bytes 0 0 1 0 0 4 bytes 0 0 1 0 1 5 bytes 0 0 1 1 0 6 bytes 0 0 1 1 1 7 bytes 0 1 0 0 0 8 bytes 0 1 0 0 1 9 bytes 0 1 0 1 0 10 bytes 0 1 0 1 1 11 bytes 0 1 1 0 0 12 bytes 0 1 1 0 1 13 bytes 0 1 1 1 0 14 bytes 0 1 1 1 1 15 bytes 1 0 0 0 0 16 bytes other than above invalid 4 to 0 ubntb4 to ubntb0 remark n = 0, 1 chapter 10 serial interface function 484 user?s manual u16031ej3v0ud 10.2.4 interrupt requests the following five types of interrupt requests are generated from uartbn (n = 0, 1). ? reception error interrupt (ubtiren) ? reception completion interrupt (ubtirn) ? transmission completion interrupt (ubtitn) ? fifo transmission completi on interrupt (ubtifn) ? reception timeout interrupt (ubtiton) the default priorities among these five types of interrupt requests is, from high to low, reception error interrupt, reception completion interrupt, transmission completion interrupt, fifo transmission completion interrupt, and reception timeout interrupt. table 10-2. generated inte rrupts and default priorities interrupt priority reception error 1 reception completion 2 transmission completion 3 fifo transmission completion 4 reception timeout 5 (1) reception error interrupt (ubtiren) (a) single mode when reception is enabled, a reception error interrupt is generated according to the logical or of the three types of reception errors (parity error, fram ing error, overrun error) explained for the ubnstr register. when reception is disabled, no rec eption error interrupt is generated. (b) fifo mode when reception is enabled, a reception error interrupt is generated according to the logical or of the three types of reception errors (parity error, fram ing error, overflow error) explained for the ubnstr register. when reception is disabled, no rec eption error interrupt is generated. chapter 10 serial interface function user?s manual u16031ej3v0ud 485 (2) reception completion interrupt (ubtirn) (a) single mode when reception is enabled, a reception completion inte rrupt is generated if data is shifted into receive shift register n and stored in the ubnrx r egister (if the receive data can be read). when reception is disabled, no reception completion interrupt is generated. (b) fifo mode when reception is enabled, a reception completion inte rrupt is generated if data is shifted into receive shift register n and receive data of the number set as the trigger by the ubnrt3 to ubnrt0 bits of the ubnfic2 register is transferred to receive fifon (i f receive data of the spec ified number can be read). when reception is disabled, no reception completion interrupt is generated. (3) transmission completion interrupt (ubtitn) (a) single mode the transmission completion interrupt is generated if transmit data of one frame, including 7 or 8 bits of characters, is shifted out from transmit shift regi ster n and the ubntx register becomes vacant (if transmit data can be written). (b) fifo mode the transmission completion interrupt is generated if transmit data of the number set as the trigger by the ubntt3 to ubntt0 bits of the ubnfic2 register is transferred to transmit shift register n from transmit fifon (if transmit data of the s pecified number can be written). (4) fifo transmission completion interrupt (ubtifn) (a) single mode cannot be used. (b) fifo mode the fifo transmission completion interrupt is generat ed when no more data is in transmit fifon and transmit shift register n (when the fifo and regi ster become empty). after the fifo transmission completion interrupt has occurred, clear the interr upt held pending (ubtitn) in the pending mode (ubnitm bit = 0 in the ubnfic0 register) by clearing the fifo (ubntfc bit = 1 in the ubnfic0 register). caution if the fifo transmission completion inte rrupt is generated (all transmit data are not transmitted) because writing the next transmit data to transmit fi fon is delayed, do not clear the fifo. chapter 10 serial interface function 486 user?s manual u16031ej3v0ud (5) reception timeout interrupt (ubtiton) (a) single mode cannot be used. (b) fifo mode the reception timeout interrupt is generated if data is stored in receiv e fifon when the next data does not come (start bit is not detected) even after the next data reception wa it time specified by the ubntc4 to ubntc0 bits of the ubnfic1 register has el apsed, when the timeout counter function is used (ubntce bit = 1 in the ubnfic1 register). the reception timeout interrupt is not generated while reception is disabled. if receive data of the number set as the trigger by the ubnrt3 to ubnrt0 bits of the ubnfic2 register is not received, the timing of reading the number of receive data less th an the specified number can be set by the reception timeout interrupt. since the timeout counter starts count ing at start bit detection, a receive timeout interrupt does not occur if data of 1 character has not been received. chapter 10 serial interface function user?s manual u16031ej3v0ud 487 10.2.5 control method (1) single mode/fifo mode the single mode or fifo mode can be selected by using the ubnmod bit of the ubnfic0 register. (a) single mode ? each of the ubnrx and ubntx registers consists of 8 bits 1 stage. ? when 1 byte of data is received, the ubtirn interrupt is generated. ? if the next reception operation of uartbn is co mpleted before the receive data of the ubnrx register is read after the ubtirn interrupt has been gen erated, the ubtiren inte rrupt is generated and an overrun error occurs. (b) fifo mode ? receive fifon (ubnrxap register) consists of 16 bits 16 stages and transmit fifon consists of 8 bits 16 stages. ? receive fifon can recognize error data by reading the 16-bit ubnrxap register only when a reception error (parity error or framing error) occurs. ? transmission is started when transmission is enabled (ubntxe bit = 1 in the ubnctl0 register) after transmit data of at least the number set as the trig ger by the ubntt3 to ubntt0 bits of the ubnfic2 register and 16 bytes or less are written to transmit fifon. ? the pending mode or pointer mode can be select ed for the generation timing of the ubtitn and ubtirn interrupts. chapter 10 serial interface function 488 user?s manual u16031ej3v0ud (2) pending mode/pointer mode the pending mode or pointer mode can be selected by using the ubnitm and ubnirm bits of the ubnfic0 register in the fifo mode (ubnmod bit = 1 in the ubnfic0 register). if transmission is started by writing da ta of more than double the amount se t as the trigger by the ubntt3 to ubntt0 bits of the ubnfic2 register to transmit fifo n, the transmission completion interrupt (ubtitn) may occur more than once. the reception completion interru pt (ubtirn) may also occur more than once if the number of receive data set as the trigger by the ubnrt3 to ubnrt0 bits of the ubnfic2 register is 8 bytes or less in receive fifon. in the pending or pointer m ode, it can be specified how an interrupt is handled after it has been held pending. (a) pending mode (i) during transmission (wri ting to transmit fifon) ? if the data of the first transmission completion inte rrupt (ubtitn) is not written to transmit fifon after the interrupt has occurred, the second ubti tn interrupt does not occur (is held pending) even if the generation condition of the second ubtitn interrupt is satisfied (when transmit data of the number set as the trigger by the ubntt3 to ubn tt0 bits of the ubnfic2 register is transferred from transmit fifon to the transmit shift register). when data for the first ubtitn interrupt is la ter written to transmit fifon, the pending ubtitn interrupt is generated note . note the number of pending interrupts is as follows. when trigger is set to 1 byte (ubntt3 to ubntt0 bits of ubnfic2 register = 0000): 15 times max. when trigger is set to 2 bytes (ubntt3 to ubntt0 bits of ubnfic2 register = 0001): 7 times max. : when trigger is set to 6 bytes (ubntt3 to ubntt0 bits of ubnfic2 register = 0101): 1 time max. when trigger is set to 7 bytes (ubntt3 to ubntt0 bits of ubnfic2 register = 0110): 1 time max. when trigger is set to 8 bytes (ubntt3 to ubntt0 bits of ubnfic2 register = 0111): 1 time max. ? in the pending mode, transmit data of the number se t as the trigger by the ubntt3 to ubntt0 bits of the ubnfic2 register is always written to transmit fifon when the transmission completion interrupt (ubtitn) occurs. writing data to transmi t fifon is prohibited if the data is more or less than the specified number. if data more or less t han the specified number is written, the operation is not guaranteed. ? fix the ubntt3 to ubntt0 bits of the ubnfic 2 register to 0000 (set number of transmit data: 1 byte) to write transmit data to transmit fifon by dma. if any other setting is made, the operation is not guaranteed. chapter 10 serial interface function user?s manual u16031ej3v0ud 489 (ii) during reception (reading from receive fifon) ? if data for the first reception completion interrupt (ubtirn) is not read from receive fifon, the second ubtirn interrupt does not occur (is held pending) even if the generation condition of the second ubtirn is satisfied (if receive data of the number set as the trigger by the ubnrt3 to ubnrt0 bits of the ubnfic2 register can be r ead from receive fifon). when data for the first ubtirn interrupt is later read from the rece ive fifon, the pending ubtirn interrupt is generated note . note the number of pending interrupts is as follows. when trigger is set to 1 byte (ubnrt3 to ubnrt0 bits of ubnfic2 register = 0000): 15 times max. when trigger is set to 2 bytes (u bnrt3 to ubnrt0 bits of ubnfic2 register = 0001): 7 times max. : when trigger is set to 6 bytes (ubnrt3 to ubnrt0 bits of ubnfic2 register = 0101): 1 time max. when trigger is set to 7 bytes (u bnrt3 to ubnrt0 bits of ubnfic2 register = 0110): 1 time max. when trigger is set to 8 bytes (u bnrt3 to ubnrt0 bits of ubnfic2 register = 0111): 1 time max. ? in the pending mode, receive dat a of the number set as the trigger by the ubnrt3 to ubnrt0 bits of the ubnfic2 register is always read from receive fifon when the reception completion interrupt (ubtirn) occurs. reading data from receiv e fifon is prohibited if the data is more or less than the specified number. if data more or less than the specified number is read, the operation is not guaranteed. ? fix the ubnrt3 to ubnrt0 bits of the ubnfic2 register to 0000 (set number of receive data: 1 byte) to read receive data from receive fifon by dma. if any other setting is made, the operation is not guaranteed. (b) pointer mode (i) during transmission (wri ting to transmit fifon) ? each time the data of 1 byte is transferred to transmit shift register n from transmit fifon, a transmission completion interrupt (ubtitn) occurs. ? in the pointer mode, be sure to fix the ubntt3 to ubntt0 bits of the ubnfic2 register to 0000 (set number of transmit data: 1 byte) as the number of transmit data set as the trigger for transmit fifon when the transmission completion interrupt (u btitn) occurs. if any other setting is made, the operation is not guaranteed. ? writing transmit data to transmit fifon by dma is prohibited. the operat ion is not guaranteed if dma control is used. ? after the transmission completion interrupt (u btitn) has been acknowle dged, data of the number of vacant bytes of transmit fifon can be writt en to transmit fifon by referencing the ubnfis1 register. chapter 10 serial interface function 490 user?s manual u16031ej3v0ud (ii) during reception (reading from receive fifon) ? each time the data of 1 byte is transferred to receive fifon from receive shift register n, a reception completion inte rrupt (ubtirn) occurs. ? in the pointer mode, be sure to fix the ubnrt3 to ubnrt0 bits of the ubnfic2 register to 0000 (set number of receive data: 1 by te) as the number of receive data set as the trigger for receive fifon when the reception completion interrupt (ubt irn) occurs. if any other setting is made, the operation is not guaranteed. ? reading receive data from receive fifon by dma is prohibited. the operat ion is not guaranteed if dma control is used. ? after the reception completion interrupt (ubtir n) has been acknowledged, data of the number of bytes stored in receive fifon can be read from receive fifon by referencing the ubnfis0 register. in some cases, however, data is not stored in receive fifon even though the ubtirn interrupt is generated (ubnrb4 to ubnrb0 bits = 00000 in the ubnfis0 registe r). in these cases, do not read data from receive fifon. always r ead data from receive fifon when the number of bytes stored in receive fifon is 1 byte or more (ubnrb4 to ubnrb0 bits = other than 00000). 10.2.6 operation (1) data format full-duplex serial data transmission and reception can be performed. the transmit/receive data format consis ts of one data frame containing a start bit, character bits, a parity bit, and stop bits as shown in figure 10-2. the character bit length within one data frame, the type of parity, and the stop bit length are specified by the uartbn control register 0 (ubnctl0) (n = 0, 1). also, data is transferred with lsb first/msb first. figure 10-2. asynchronous serial interface tran smit/receive data format (lsb-first transfer) 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bits character bits ? start bit 1 bit ? character bits 7 bits or 8 bits ? parity bit even parity, odd parity, 0 parity, or no parity ? stop bits 1 bit or 2 bits chapter 10 serial interface function user?s manual u16031ej3v0ud 491 (2) transmit operation in the single mode (ubnmod bit = 0 in the ubnfic0 register), transmission is enabled when the ubntxe bit of the ubnctl0 register is set to 1, and transmissi on is started when transmit data is written to the ubntx register (n = 0, 1). in the fifo mode (ubnmod bit = 1 in the ubnfic0 registe r), transmission is started when transmit data of at least the number set as the trigger by the ubntt3 to ubntt0 bits of the ubnfic2 register and 16 bytes or less is written to transmit fifon and then the ubntxe bit is set to 1. caution setting the ubntxe bit of the ubnctl0 register to 1 before writing tran smit data to transmit fifon in the fifo mode is prohibited. the operation is not guarant eed if this setting is made. (a) transmission enabled state this state is set by the ubntxe bit in the ubnctl0 register (n = 0, 1). ? ubntxe = 1: transmission enabled state ? ubntxe = 0: transmission disabled state however, when the transmission enabled state is se t, to use uartb0, which shares pins with clocked serial interface 30 (csi30), the csicae0 bit of clocked serial interface mode register 30 (csim30) should be cleared to 0. since uartbn does not have a cts (transmission enab led signal) input pin, a port should be used to confirm whether the destination is in the reception enabled state. (b) starting a transmit operation ? in single mode (ubnmod bit = 0 in ubnfic0 register) in the single mode, transmission is started when tr ansmit data is written to the ubntx register while transmission is enabled (n = 0, 1). ? in fifo mode (ubnmod bit = 1 in ubnfic0 register) in the fifo mode, transmission is started when trans mit data of at least the number set as the trigger by the ubntt3 to ubntt0 bits of the ubnfic2 regi ster and 16 bytes or less is written to transmit fifon and then transmission is enabled (ubntxe bit = 1). data in transmit data register n (ubntx register in single mode or transmit fi fon in the fifo mode) is transferred to transmit shift register n when transmission is started. then, transmit shift register n outputs data to the txdn pin sequentially beginning with t he lsb (the transmit data is transferred sequentially starting with the start bit). the start bit, parity bi t, and stop bits are added automatically (n = 0, 1). chapter 10 serial interface function 492 user?s manual u16031ej3v0ud (c) transmission interrupt request (i) transmission completion interrupt (ubtitn) ? in single mode (ubnmod bit = 0 in ubnfic0 register) in the single mode, the transmission completion in terrupt (ubtitn) occurs when transmit data can be written to the ubntx register (when 1 byte of data is transferred from the ubntx register to transmit shift register n) (n = 0, 1). ? in fifo mode (ubnmod bit = 1 in ubnfic0 register) in the fifo mode, the ubtitn interrupt occurs wh en transmit data of the number set as the trigger specified by the ubntt3 to ubntt0 bits of t he ubnfic2 register is transferred from transmit fifon to transmit shift register n (if transmit data of the number set as the trigger can be written) (n = 0, 1). ? if pending mode is specified (ubnitm bi t = 0 in ubnfic0 register) in fifo mode if the pending mode is specified in the fifo mode, the second ubtitn interrupt is held pending after the first ubtitn interrupt has occurred, unt il as many transmit data as the number set as the trigger by the ubntt3 to ubntt0 bits of the ubnf ic2 register are written to transmit fifon, even if the generation condition of the second ubtitn interrupt is satisfied. when as many transmit data as the number set as the trigger are written to transmit fifon in response to the first ubtitn interrupt, the second pending ubtitn interrupt is generated (n = 0, 1). ? if pointer mode is specified (ubnitm bi t = 1 in ubnfic0 register) in fifo mode if the pointer mode is specified in the fifo mode, the second ubtitn interrupt occurs when the generation condition of the second ubtitn interrupt is satisfied even if as many transmit data as the number set as the trigger by the ubntt3 to ubntt0 bits of the ubnfic2 register are not written to transmit fifon when the first ubtitn interrupt occurs (n = 0, 1). (ii) fifo transmission completion interrupt (ubtifn) the fifo transmission completion interrupt (ubtifn) occurs when no more data is in transmit fifon and transmit shift register n in the fifo mode (ubnmo d bit = 1 in the ubnfic0 register) (n = 0, 1). after the ubtifn interrupt has occurred, clear t he pending ubtitn interrupt in the pending mode (ubnitm bit = 0 in the ubnfic0 register) by cl earing the fifo (ubntfc bit = 1 in the ubnfic0 register). if the ubtifn interrupt occurs because writing the next transmit dat a to transmit fifon is delayed (if all transmit data have not been transmitted), do not clear the fifo. if the data to be transmitted next has not been written to transmit data regi ster n, the transmit operation is suspended. caution in the single mode, th e transmission completion interrupt (ubtitn) occurs when the ubntx register becomes empty (when 1 byte of data is transfe rred from the ubntx register to transmit shift register n). in the fifo mode, the fifo transmission completion interrupt (ubtifn) occurs when data is no longer in transmit fifon and transmit shift register n (when the fifo a nd register are vacant). however, the ubtitn interrupt or ubtifn interrupt is not generated if transmit da ta register n becomes empty due to reset input. chapter 10 serial interface function user?s manual u16031ej3v0ud 493 figure 10-3. timing of asynchronous serial interf ace transmission completion interrupt (ubtitn) start stop d0 d1 d2 d6 d7 parity txdn (output) ubtitn (output) remarks 1. in the fifo mode, the ubtitn interrupt occurs at the above timing when as many transmit data as the number set as the trigger by the ubntt3 to ubntt0 bits of the ubnfic2 register are serially transferred. 2. n = 0, 1 figure 10-4. timing of asynchronous serial interface fifo transmission completion interrupt (ubtifn) start stop d0 d1 d2 d6 d7 parity txdn (output) ubtifn (output) remarks 1. the ubtifn interrupt occurs at the above timi ng when data is no longer in transmit fifon and transmit shift register n (when t he fifo and register are vacant). 2. n = 0, 1 chapter 10 serial interface function 494 user?s manual u16031ej3v0ud (3) continuous transmission operation ? in single mode (ubnmod bit = 0 in ubnfic0 register) in the single mode, the next data can be written to t he ubntx register as soon as transmit shift register n has started a shift operation (n = 0, 1). the timi ng of transfer can be identified by the transmission completion interrupt (ubtitn). by writing the next transmit data to the ubntx register via the ubtitn interrupt within one data frame transmission period, data can be transmitted without an interval and an efficient communication rate can be realized. caution confirm that the ubntsf bit of the ubnst r register is 0 before executing initialization during transmission processing. if initializati on is executed while the ubntsf bit is 1, the transmit data is not guaranteed. ? if pending mode is specified (ubnitm bi t = 0 in ubnfic0 register) in fifo mode if transmit data of at least the number set as the tr ansmit trigger by ubntt3 to ubntt0 bits of the ubnfic2 register and 16 bytes or less is wri tten to transmit fifon, transmission starts. if the pending mode is specified in th e fifo mode, as many of the next transmit data as the number set as the trigger by the ubntt3 to ubntt0 bits of the ubnfic2 register can be written to transmit fifon as soon as transmit shift register n has started shifting the last data of the specif ied number of data. the timing of transfer can be identified by the ubtitn interr upt. by writing as many of the next transmit data as the number set as the trigger to transmit fifon or writing the data to the fifo within the transmission period of the data in transmit fi fon via the ubtitn interrupt, data c an be transmitted without an interval and an efficient communication rate can be realized. caution confirm that the ubntsf bit of the ubnst r register is 0 before executing initialization during transmission processing (this can also be done by the fifo transmission completion interrupt (ubtifn)). if initialization is executed while the ubntsf bit is 1, the transmit data is not guaranteed. to write transm it data to transmit fifon by dma, set the number of transmit data specified as the tr igger by the ubntt3 to ubntt0 bits of the ubnfic2 register to 1 byte; otherwi se the operation will not be guaranteed. ? if pointer mode is specified (ubnitm bi t = 1 in ubnfic0 register) in fifo mode if the pointer mode is specified in the fifo mode, a ubtitn interrupt occurs and the next data can be written to transmit fifon as soon as transmit shift r egister n has started shifting the number of transmit data set as the trigger. at this time, as many data as the number of vacant bytes of transmit fifon can be written by referencing the ubnfis1 register. the ti ming of transfer can be identified by the ubtitn interrupt. by writing as many of the next transmit dat a as the number specified as the trigger to transmit fifon (= 1 byte) or writin g the data to the fifo withi n the transmission period of the data in transmit fifon via the ubtitn interrupt, data can be transmitted witho ut an interval and an efficient communication rate can be realized. caution confirm that the ubntsf bit of the ubnst r register is 0 before executing initialization during transmission processing (this can also be done by the fifo transmission completion interrupt (ubtifn)). if initialization is executed while the ubntsf bit is 1, the transmit data is not guaranteed. chapter 10 serial interface function user?s manual u16031ej3v0ud 495 (4) receive operation the awaiting reception state is set by setting the ubnp wr bit to 1 in the ubnctl0 register and then setting ubnrxe to 1 in the ubnctl0 register (n = 0, 1). rx dn pin sampling begins and a start bit is detected. when the start bit is detected, the receive operation be gins, and data is stored sequentially in receive shift register n according to the baud rate that was set. in the single mode (ubnmod bit = 0 in the ubnfic0 regi ster), a reception completion interrupt (ubtirn) is generated each time the reception of one frame of da ta is completed. normall y, the receive data is transferred from the ubnrx register to memory by this interrupt servicing. in the fifo mode (ubnmod bit = 1 in the ubnfic0 regi ster), the ubtirn interrupt occurs when as many receive data as the number set as the trigger by the ubnrt3 to ubnrt0 bits of the ubnfic2 register are transferred to receive fifon. if the pending mode is specified (ubnirm bit = 0 in the ub nfic0 register) in the fifo mode, as many receive data as the number set as the trigger by the ubnrt3 to ubnrt0 bits of the ubnfic2 register can be read from receive fifon. if the pointer mode is specified (ubnirm bit = 1 in the ub nfic0 register) in the fifo mode, as many data as the number of bytes stored in receive fifon (0 bytes or more) can be read from receive fifon by referencing the number of receive data specified as the tr igger by the ubnrt3 to ubnrt0 bits (1 byte) or the ubnfis0 register. caution if the pointer mode is specified in the fifo mode and if as many data as the number of bytes stored in receive fifon are read by refe rencing the ubnfis0 register, no data may be stored in receive fifon (ubnrb4 to ubnrb0 bits = 00000 in the ubnfis0 register) even though the reception completion interrupt (ubtirn) has occurred. in this case, do not read data from receive fifon. be sure to read da ta from receive fifon a fter confirming that the number of bytes stored in receive fifon = 1 by te or more (ubnrb4 to ubnrb0 bits = other than 00000). (a) reception enabled state this state is set by the ubnrxe bit in the ubnctl0 register (n = 0, 1). ? ubnrxe = 1: reception enabled state ? ubnrxe = 0: reception disabled state however, when the reception enabled state is set, to use uartb0, which shares pins with clocked serial interface 30 (csi30), the operation of csi30 must be disabled by clearing the csicae0 bit of clocked serial interface mode register 30 (csim30) to 0 (n = 0, 1). in the reception disabled state, the reception hardware stands by in the in itial state. at this time, the reception completion interrupt or reception error in terrupt does not occur, and the contents of receive data register n (ubnrx register in the single m ode or receive fifon in the fifo mode (ubnrxap register)) are retained. (b) starting a receive operation a receive operation is started by the detection of a start bit. the rxdn pin is sampled using the serial clock from uartbn control register 2 (ubnctl2) (n = 0, 1). chapter 10 serial interface function 496 user?s manual u16031ej3v0ud (c) reception completion interrupt (i) reception completion interrupt (ubtirn) ? in single mode (ubnmod bi t = 0 in ubnfic0 register) when ubnrxe bit = 1 in the ubnctl0 register and the reception of one frame of data is completed (the stop bit is detected) in the singl e mode, a reception completion interrupt request (ubtirn) is generated and the receive data in rece ive shift register n is transferred to the ubnrx register at the same time (n = 0, 1). also, if an overrun error occurs, the receive data at that time is not tr ansferred to the ubnrx register, and a reception error in terrupt (ubtiren) is generated. if a parity error or framing error occurs during t he reception operation, the reception operation continues up to the position at wh ich the stop bit is received. after completion of reception, an ubtiren interrupt occurs (the receive data in rece ive shift register n is transferred to the ubnrx register). if the ubnrxe bit is reset (0) during a receive operation, the receive operation is immediately stopped. at this time, the cont ents of the ubnrx register remain unchanged, the contents of the uartbn status register (ubnstr) are clear ed, and the ubtirn and ubtiren interrupts do not occur. no ubtirn interrupt is generated wh en ubnrxe = 0 (reception is disabled). ? in fifo mode (ubnmod bit = 1 in ubnfic0 register) in the fifo mode, the reception completion inte rrupt (ubtirn) occurs when data of one frame has been received (stop bit is detected) and when as many receive data as the number specified as the trigger by the ubnrt3 to ubnrt0 bits of the ubnfic2 register are transferred from receive shift register n to receive fifon (n = 0, 1). if an overflow error occurs, the receive data is not transferred to receive fifon and the recept ion error interrupt (ubtiren) occurs. if a parity error or framing error occurs during rece ption, reception continues up to the reception position of the stop bit. after re ception has been completed, the ub tiren interrupt occurs and the receive data in receive shift register n is trans ferred to receive fifon. at this time, error information is appended as the ubnpef or ub nfef bit = 1 in the ubnrxap register. if the ubtiren interrupt occurs, the error data can be re cognized by reading receive fifon as a 16-bit register, ubnrxap. chapter 10 serial interface function user?s manual u16031ej3v0ud 497 (ii) reception timeout interrupt (ubtiton) (in fifo mode only) when the timeout counter function (ubntce bit = 1 in the ubnfic1 register) is used in the fifo mode, the reception timeout interrupt (ubtiton) occu rs if the next data does not come even after the next data reception wait time s pecified by the ubntc4 to ubntc0 bits of the ubnfic1 register has elapsed and if data is stored in receive fifon (n = 0, 1). the ubtiton interrupt does not occur while reception is disabled. if as many receive data as the number set as the trigger by the ubnrt3 to ubnrt0 bits of the ubnfic2 register are not received, the timing of reading less receive data than the specified number can be set by the ubtiton interrupt. since the timeout counter starts counting at start bit detection, a receive timeout interrupt does not occur if data of 1 character has not been received. figure 10-5. timing of asynchronous serial inte rface reception completion interrupt (ubtirn) start d0 d1 d2 d6 d7 rxdn (input) ubtirn (output) receive data register n parity stop cautions 1. be sure to read all the data (the number of data indi cated by the ubnrb4 to ubnrb0 bits of the ubnfis0 register) stored in receive data register n (ubnrx register in the single mode or receive fifon in the fifo mode (ubnrxap register)) even when a reception error occurs. unless receive data register n is read, an overrun error occurs wh en the next data is received, causing the reception error status to persist. if the pending mode is speci fied in the fifo mode, however , be sure to clear the fifo (ubnrfc bit = 1 in the ubnfic0 register) after reading th e data stored in receive fifon. in the fifo mode, the fifo can be clear ed even without reading the data stored in receive fifon. if a parity error or framing error occurs in the fifo mode, the ubnrxap register can be read in 16-bit (halfword) units. 2. data is always rece ived with one stop bit. a second stop bit is ignored. remark n = 0, 1 chapter 10 serial interface function 498 user?s manual u16031ej3v0ud (5) reception error in the single mode (ubnmod bit = 0 in the ubnfic0 regist er), the three types of e rrors that can occur during a receive operation are a parity error, framing error, and overrun error. in the fifo mode (ubnmod bit = 1 in the ubnfic0 register), the three types of errors that can occur during a re ceive operation are a parity error, framing error, and overflow error. as a result of data recepti on, the ubnpe, ubnfe, or ub nove bit of the ubnstr register is set to 1 if a parity error, framing error, or overrun error occurs in the si ngle mode. the ubnovf bit of the ubnstr register is set to 1 if an overflow error occurs in the fifo mode. the ubnpef or ubnfef bit of the ubnrxap register is set to 1 if a parity error or framing error occurs in the fifo mode. at the same time, a reception error interrupt (ubtiren) occurs. the contents of the er ror can be detected by r eading the contents of the ubnstr or ubnrxap register. the contents of the ubnstr register are reset wh en 0 is written to the ub novf, ubnpe, ubnfe, or ubnove bit, or the ubnpwr or ubnrxe bit of the ubnctl0 register. the contents of the ubnrxap register are reset when 0 is written to the ubnpwr bit of the ubnctl0 register. table 10-3. reception error causes error flag valid operation mode error flag reception error cause ubnpe ubnpe parity error the parity specification during transmission does not match the parity of the receive data ubnfe ubnfe framing error no stop bit detected ubnove single mode ubnove overrun error the reception of the next data is completed before data is read from the ubnrx register ubnovf ubnovf overflow error the recept ion of the next data is completed while receive fifon is full and before data is read. ubnpef ubnpef parity error the parit y specification during transmission does not match the parity of the data to be received. ubnfef fifo mode ubnfef framing error the stop bit is not detected when the target data is loaded. remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 499 (6) parity types and co rresponding operation a parity bit is used to detect a bit error in communication data. normally, the same type of parity bit is used at the transmission and reception sides. (a) even parity (i) during transmission the parity bit is controlled so t hat the number of bits with the value ?1? within the transmit data including the parity bit is even. the parity bit value is as follows. ? if the number of bits with the value ?1? within the transmit data is odd: 1 ? if the number of bits with the value ?1 ? within the transmit data is even: 0 (ii) during reception the number of bits with the value ?1? within the receive data including the parity bit is counted, and a parity error is generated if this number is odd. (b) odd parity (i) during transmission in contrast to even parity, the parity bit is contro lled so that the number of bits with the value ?1? within the transmit data including the parity bit is odd. the parity bit value is as follows. ? if the number of bits with the value ?1? within the transmit data is odd: 0 ? if the number of bits with the value ?1 ? within the transmit data is even: 1 (ii) during reception the number of bits with the value ?1? within the receive data including the parity bit is counted, and a parity error is generated if this number is even. (c) 0 parity during transmission the parity bit is set to ?0? regardless of the transmit data. during reception, no parity bit check is performed. therefore, no parity error is generated regardless of whether the parity bit is ?0? or ?1?. (d) no parity no parity bit is added to the transmit data. during reception, the receive operation is performed as if there were no parity bit. since there is no parity bit, no parity error is generated. chapter 10 serial interface function 500 user?s manual u16031ej3v0ud (7) receive data noise filter the rxdn signal is sampled at the rising edge of the input clock (f x /4) (f x : main clock). if the same sampling value is obtained twice, the match detector output c hanges, and this output is sampled as input data. therefore, data not exceeding one clock width is judged to be noise and is not delivered to the internal circuit (see figure 10-7 ). also, since the circuit is configured as shown in figure 10-6, internal processing during a receive operation is delayed by up to 2 clocks accordin g to the external signal status. figure 10-6. noise filter circuit rxdn q f x /4 in ld_en q in internal signal a internal signal b match detector remarks 1. n = 0, 1 2. f x : main clock figure 10-7. timing of rx dn signal ju dged as noise internal signal a f x /4 rxdn (input) internal signal b match mismatch (judged as noise) mismatch (judged as noise) match remarks 1. n = 0, 1 2. f x : main clock chapter 10 serial interface function user?s manual u16031ej3v0ud 501 10.2.7 dedicated baud rate gene rators 0, 1 (brg0, brg1) a dedicated baud rate generator, which consists of a 16 -bit programmable counter, generates serial clocks during transmission/reception in uartbn. the dedicated baud rate generator output can be selected as the serial clock for each channel. separate 16-bit counters exist for transmission and for recept ion. the baud rate for transmission/reception is the same at the same channel. (1) baud rate genera tor configuration figure 10-8. baud rate generator configuration clock 16-bit counter match detector baud rate ubnctl2: ubnbrs15 to ubnbrs0 1/2 ubnpwr, ubntxe (or ubnrxe) f x /4 remarks 1 . n = 0, 1 2. f x : main clock (a) base clock (clock) when ubnpwr bit = 1 in the ubnctl0 register, the input clock (f x /4) is supplied to the transmission/reception unit (f x : main clock). this clock is called the base clock. when ubnpwr = 0, the clock signal is fixed at low level. chapter 10 serial interface function 502 user?s manual u16031ej3v0ud (2) serial clock generation a serial clock can be generated according to the settings of the ubnctl2 register (n = 0, 1). the 16-bit counter divisor value can be selected ac cording to the ubnbrs15 to ubnbrs0 bits of the ubnctl2 register. (a) baud rate the baud rate is the value obtained according to the following formula. [bps] k 2 frequency clock base rate baud = base clock frequency = f x /4 (f x : main clock) k = value set according to ubnbrs15 to ubnbrs0 bits of ubnctl2 register (k = 4, 5, 6, ..., 65,535) (b) baud rate error the baud rate error is obtained according to the following formula. [%] 100 1 rate) baud (normal rate baud desired error) with rate (baud rate baud actual (%) error ? = ? ? ? ? ? ? ? ? cautions 1. make sure that the baud rate error during transmission does not exceed the allowable error of the reception destination. 2. make sure that the baud rate error duri ng reception is within th e allowable baud rate range during reception, which is described in paragraph (4). example: main clock (f x ) = 150 mhz = 150,000,000 hz settings of ubnbrs15 to ubnbrs0 bits in ubnctl2 register = 0000000001111010b (k = 122) target baud rate = 153,600 bps baud rate = 150 m/4/(2 122) = 150,000,000/4/(2 122) = 153,689 [bps] error = (153,689/153,600 ? 1) 100 = 0.058 [%] chapter 10 serial interface function user?s manual u16031ej3v0ud 503 (3) baud rate setting example table 10-4. baud rate generator setting data f x = 150 mhz f x = 133 mhz f x = 100 mhz f x = 80 mhz baud rate (bps) k err k err k err k err 300 62,500 0.000 55,417 ? 0.001 41,667 ? 0.001 33,333 0.001 600 31,250 0.000 27,708 0.001 20,833 0.002 16,667 ? 0.002 1,200 15,625 0.000 13,854 0.001 10,417 ? 0.003 8,333 0.004 2,400 7,813 ? 0.006 6,927 0.001 5,208 0.006 4,167 ? 0.008 4,800 3,906 0.006 3,464 ? 0.013 2,604 0.006 2,083 0.016 9,600 1,953 0.006 1,732 ? 0.013 1,302 0.006 1,042 ? 0.032 19,200 977 ? 0.045 866 ? 0.013 651 0.006 521 ? 0.032 31,250 600 0.000 532 0.000 400 0.000 320 0.000 38,400 488 0.058 433 ? 0.013 326 ? 0.147 260 0.160 76,800 244 0.058 216 0.218 163 ? 0.147 130 0.160 153,600 122 0.058 108 0.218 81 0.469 65 0.160 312,500 60 0.000 53 0.377 40 0.000 32 0.000 caution the maximum allowable fr equency of the main clock (f x ) is 150 mhz. remark f x : main clock k: settings of ubnbrs15 to ubnbrs0 bits in ubnctl2 register (n = 0, 1) err: baud rate error [%] chapter 10 serial interface function 504 user?s manual u16031ej3v0ud (4) allowable baud rate range during reception the degree to which a discrepancy from the transmission destination?s baud rate is allowed during reception is shown below. caution the equations described be low should be used to set the baud rate error during reception so that it always is withi n the allowable error range. figure 10-9. allowable baud rate range during reception fl 1 data frame (11 fl) flmin flmax uartbn latch timing start bit bit 0 bit 1 bit 7 parity bit minimum allowable value maximum allowable value stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit remark n = 0, 1 as shown in figure 10-9, after the start bit is detected, the receive data latch timing is determined according to the counter that was set by the ubnctl2 register. if all data up to the final data (stop bit) is in time for this latch timing, the data can be received normally. applying this to 11-bit reception is, theoretically, as follows. fl = (brate) ? 1 brate: uartbn baud rate (n = 0, 1) k: ubnctl2 setting value (n = 0, 1) fl: 1-bit data length latch timing margin: 2 clocks minimum allowable value: fl k 2 2 k 21 fl k 2 2 k fl 11 flmin + = ? ? = chapter 10 serial interface function user?s manual u16031ej3v0ud 505 therefore, the maximum baud rate that can be re ceived at the transfer destination is as follows. brate 2 21k k 22 (flmin/11) brmax 1 + = = ? similarly, the maximum allowable value can be obtained as follows. fl k 2 2 k 21 fl k 2 2 k fl 11 flmax 11 10 ? = + ? = 11 fl k 20 2 k 21 flmax ? = therefore, the minimum baud rate that can be received at the transfer destination is as follows. brate 2 21k k 20 (flmax/11) brmin 1 ? = = ? the allowable baud rate error of uartbn and the transfer destination can be obtained as follows from the expressions described above for computing the minimum and maximum baud rate values. table 10-5. maximum and mini mum allowable baud rate error division ratio (k) maximum allowable baud rate error minimum allowable baud rate error 4 +2.33 % ? 2.44 8 +3.53 % ? 3.61 16 +4.14 % ? 4.19 32 +4.45 % ? 4.48 64 +4.61 % ? 4.62 128 +4.68 % ? 4.69 256 +4.72 % ? 4.73 512 +4.74 % ? 4.74 1,024 +4.75 % ? 4.75 2,048 +4.76 % ? 4.76 4,096 +4.76 % ? 4.76 8,192 +4.76 % ? 4.76 16,384 +4.76 % ? 4.76 32,768 +4.76 % ? 4.76 65,535 +4.76 % ? 4.76 remarks 1. the reception precision depends on the number of bits in one frame, the base clock frequency, and the division ratio (k). the higher the base clock frequency and the larger the division ratio (k), the higher the precision. 2. k: ubnctl2 setting value (n = 0, 1) chapter 10 serial interface function 506 user?s manual u16031ej3v0ud (5) transfer rate durin g continuous transmission during continuous transmission, the transfer rate from a stop bit to the next start bit is extended two clocks longer than normal. however, on the reception side, the transfer result is not affected since the timing is initialized by the detection of the start bit. figure 10-10. transfer rate during continuous transmission start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame bit 0 fl fl fl fl fl fl flstp start bit of second byte start bit representing the 1-bit data length by fl, the stop bit length by flstp, and the base clock frequency by f x /4 (f x : main clock) yields the following equation. flstp = fl + 2/(f x /4) therefore, the transfer rate during continuous transmission is as follows. transfer rate = 11 fl + 2/(f x /4) chapter 10 serial interface function user?s manual u16031ej3v0ud 507 10.2.8 control flow (1) example of continuous tr ansmission processing flow in single mode (cpu control) figure 10-11. example of continuo us transmission processing flow in single mode (cpu control) set uartb-related registers yes ubntsf = 0? (ubnstr) no start ubntxe = 1 (ubnctl0) : enable transmission write ubntx register : write transmit data ubntxe = 0 (ubnctl0) : disable transmission yes ubtitn interrupt = 1? : ubntx register can be written? no yes end of transmission? : all transmit data written? : transmission completed? no end remark n = 0, 1 chapter 10 serial interface function 508 user?s manual u16031ej3v0ud (2) example of continuous r eception processing flow in si ngle mode (cpu control) figure 10-12. example of continuous reception processing flow in single mode (cpu control) set uartb-related registers start ubnrxe = 1 (ubnctl0) : enable reception error processing in single mode yes ubtiren interrupt = 1? : reception error occurred? yes ubtirn interrupt = 1? : 1-byte reception completed? no yes reception completed? : reception completed? no no end read ubnrx register : read receive data ubnrxe= 0 (ubnctl0) : disable reception remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 509 (3) example of continuous tr ansmission processing flow in single mode (dma control) figure 10-13. example of continuo us transmission processing flow in single mode (dma control) set uartb/dmac-related registers note start dtfrm register = 3ch : assign dma transfer destination (in the case of ubtit0) yes dma completed? : dma transfer completed? no yes ubntsf = 0? (ubnstr) : transmission completed? no ubntxe = 0 (ubnctl0) : disable transmission end dtfrm register = 3ch : clear dfm bit emm = 1 (dchcm) : enable dma transfer ubntxe = 1 (ubnctl0) : enable transmission write ubntx register : write transmit data note in this control flow example, transmission of the first byte of the data is executed by a cpu write operation. exercise care in setting the number of data for dma transfer (dbcm register) and the source address (dsamh and dsaml registers). remark n = 0, 1 m = 0 to 3 chapter 10 serial interface function 510 user?s manual u16031ej3v0ud (4) example of continuous r eception processing flow in si ngle mode (dma control) figure 10-14. example of continuous reception processing flow in single mode (dma control) set uartb/dmac-related registers start dtfrm register = 3bh : assign dma transfer destination (in the case of ubtir0) yes dma completed? : dma transfer (reception) completed? no ubnrxe = 0 (ubnctl0) : disable reception end dtfrm register = 3bh : clear dfm bit emm = 1 (dchcm) : enable dma transfer ubnrxe = 1 (ubnctl0) : enable reception remark n = 0, 1 m = 0 to 3 chapter 10 serial interface function user?s manual u16031ej3v0ud 511 (5) example of continuous tr ansmission processing flow in fifo mode (cpu control) figure 10-15. example of continuous transmissi on processing flow in fifo mode (cpu control) set uartb-related registers start write transmit fifon note 1 : write transmit data yes ubtifn interrupt = 1? : transmission completed? note 2 yes ubtitn interrupt = 1? : writing to transmit fifon enabled? no yes transmission completed? : writing all transmit data completed? no : transmission completed? no end ubntxe = 0 (ubnctl0) write transmit fifon note 3 : disable transmission clear transmit fifon ubntxe = 1 (ubnctl0) : enable transmission yes ubtifn interrupt = 1? no notes 1. write more transmit data than the number set as the trigger by the ubntt3 to ubntt0 bits of the ubnfic2 register to transmit fifon. 2. this is the case where transmission is completed (transmit fifon and transmit shift register n become empty) before the next transmit data is wr itten. to continue data transmission, clear the ubtifn and ubtitn interrupts and write the next data to transmit fifon. 3. in the pending mode (ubnitm bit of the ubnfic0 regi ster = 0), write as many transmit data as the number set as the trigger by the ubntt3 to ubntt0 bits of the ubnfic2 register to transmit fifon. in the pointer mode (ubnitm bit = 1), reference the ubntb4 to ubntb0 bits of the ubnfis1 register and write as many data as t he number of vacant bytes in transmit fifon to transmit fifon. write 16-byte data to fully use the 8-bit 16-stage fifo function. remark n = 0, 1 chapter 10 serial interface function 512 user?s manual u16031ej3v0ud (6) example of continuous reception processing in fi fo mode (cpu control) figure 10-16. example of continuous recepti on processing in fifo mode (cpu control) set uartb-related registers start ubnrxe = 1 (ubnctl0) : enable reception yes ubtiton interrupt = 1? : reception timeout occurred? yes ubtirn interrupt = 1? : reading from receive fifon enabled? no yes reception completed? : reading all receive data completed? no no no ubtiren interrupt = 1? : reception error occurred? yes end read receive fifon note 1 : read receive data error processing in fifo mode ubnrxe= 0 (ubnctl0) : disable reception check ubnfis0 register read receive fifon note 2 : read receive data remaining in receive fifon clear receive fifon notes 1. read as many receive data as the number set as the trigger by the ubnrt3 to ubnrt0 bits of the ubnfic2 register from receive fifon in the pending mode (ubnitm bit of the ubnfic0 register = 0). in the pointer mode (ubnitm bit = 1), refer ence the ubnrb4 to ubnrb0 bits of the ubnfis0 register and read as many data as the number of bytes stored in receive fifon from receive fifon. 2. read as many data (remaining receive data less than the number set as the trigger) as the number of bytes stored in receive fifon from receive fifon by referencing the ubnrb4 to ubnrb0 bits of the ubnfis0 register. remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 513 (7) example of continuous tran smission (pending mode) processing in fifo mode (dma control) figure 10-17. example of continuous transmission (pe nding mode) processing in fifo mode (dma control) set uartb/dmac-related registers note 1 start dtfrm register = 3ch : assign dma transfer destination (in the case of ubtit0) yes dma completed? : dma transfer completed? no yes ubtifn interrupt = 1? : transmission completed? no ubntxe = 0 (ubnctl0) : disable transmission end dtfrm register = 3ch : clear dfm bit emm = 1 (dchcm) : enable dma transfer ubntxe = 1 (ubnctl0) : enable transmission clear transmit fifon write transmit fifon note 2 : write transmit data notes 1. in this control flow example, transmission of the data described in note 2 is executed by a cpu write operation. exercise care in setting the number of data for dma transfer (dbcm register) and the source address (dsamh and dsaml registers). 2. write as many transmit data as the number set as the trigger by the ubntt3 to ubntt0 bits of the ubnfic2 register (= 1 byte) to transmit fifon. remark n = 0, 1, m = 0 to 3 chapter 10 serial interface function 514 user?s manual u16031ej3v0ud (8) example of continuous recepti on (pending mode) processing flow in fifo mode (dma control) figure 10-18. example of continuous r eception (pending mode) processing flow in fifo mode (dma control) set uartb/dmac-related registers start dtfrm register = 3bh : assign dma transfer destination (in the case of ubtir0) yes dma completed? : dma transfer (reception) completed? no ubnrxe = 0 (ubnctl0) : disable reception end dtfrm register = 3bh : clear dfm bit emm = 1 (dchcm) : enable dma transfer ubnrxe = 1 (ubnctl0) : enable reception clear receive fifon remark n = 0, 1 m = 0 to 3 chapter 10 serial interface function user?s manual u16031ej3v0ud 515 (9) example of reception erro r processing in single mode figure 10-19. example of reception error processing in single mode start read ubnrx register : extract receive data (error data) end clear error flag read ubnstr register : check error flag caution reception can be continued by completing th is control flow before reception of the next data is completed. if the next data is recei ved before this control flow is completed, a reception error interrupt (ubtir en) may occur even if the data has been received correctly. remark n = 0, 1 chapter 10 serial interface function 516 user?s manual u16031ej3v0ud (10) example of reception error pr ocessing flow in fifo mode (1) figure 10-20. example of reception erro r processing flow in fifo mode (1) start ubnrxe = 0 (ubnctl0) note : stop reception end read ubnfis0 register : check receive fifon pointer read ubnrxap register : extract receive data and check error ubnrfc = 1 (ubnfic0) : clear receive fifon clear error flag read ubnstr register : check error flag note if the error flag is cleared when ubnrxe bit = 0, the ubnctl0 register does not have to be set. remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 517 (11) example of reception error pr ocessing flow in fifo mode (2) figure 10-21. example of reception erro r processing flow in fifo mode (2) start end read ubnfis0 register : check receive fifon pointer read ubnrxap register : extract receive data and check error clear error flag read ubnstr register : check error flag note reception can be continued by completing this control flow before reception of the next data is completed. extract the receive data and check if a reception error has occurred before receive fifon becomes empty. note that this control flow is valid only when a parity error or a framing error occurs. if an overflow error occurs, receive fifon must be cl eared (ubnrfc bit of the ubnfic0 register = 1). if the next data is received before this control flow is completed, a reception error interrupt (ubtiren) may occur even if the data has been received correctly. remark n = 0, 1 10.2.9 cautions when the supply of clocks to uartbn is stopped (for example, idle or stop mode), operation stops with each register retaining the value it had immediately before the supply of clocks was stopped. the txdn pin output also holds and outputs the value it had immediately before the supply of clocks was stopped. however, operation is not guaranteed after the supply of clocks is rest arted. therefore, after the supply of clocks is restarted, the circuits should be initialized by setting ubnpwr = 0, ubnrxe = 0, and ubntxe = 0. chapter 10 serial interface function user?s manual u16031ej3v0ud 518 10.3 clocked serial interf aces 30, 31 (csi30, csi31) 10.3.1 features ? transfer rate: master mode/slave mode: maximum 5.5 mbps ? half-duplex communications ? master mode and slave mode can be selected ? transmission data length: 8 to 16 bits (selectable in 1-bit units) ? transfer data direction can be swit ched between msb first and lsb first ? 3-wire mode son: serial data output sin: serial data input sckn: serial clock i/o ? bit rate in master mode: brg output (selected by the cks3n2 to cks3n0 bits and mdln2 to mdln0 bits of clocked serial interface clock select register n (csic3n)) in slave mode: clock input from master (when c ks3n2 to cks3n0 bits = 111 in the csic3n register) ? interrupt sources: 2 types ? transmission/reception completion interrupt (intcsi3n) ? csibufn overflow interrupt (intcovf3n) ? transmission mode, reception mode, or tr ansmission/reception mode can be selected ? transmission mode: transmission is started by writing transmit data to transmit data csi buffer register 3n (sfdb3n) while transmission is enabled (refer to 10.3.5 (11) transmission mode ). ? reception mode: reception is started by using processing that writes dummy data to transmit data csi buffer register 3n (sfdb3n) as a trigger while reception is enabled (refer to 10.3.5 (12) reception mode ). ? transmission/reception mode: transmission/reception is started by using processing that writes transmit data to transmit data csi buffer register 3n (sfdb3n) while transmission/reception is enabled (refer to 10.3.5 (13) transm ission/reception mode ). ? sixteen on-chip 16-bit transmit/receive buffers (csibufn) ? on-chip dedicated baud rate generator remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 519 10.3.2 configuration csi3n is controlled by the clocked serial inte rface mode register 3n (csim3n) (n = 0, 1). (1) clocked serial interface mode re gisters 30, 31 (csim30, csim31) the csim3n register is an 8-bit register for specifying the operation of csi3n. (2) clocked serial interface clock select registers 30, 31 (csic30, csic31) the csic3n register is an 8-bit register for controlli ng the operation clock and operating mode of csi3n. (3) serial i/o shift registers 0, 1 (sio0, sio1) the sion register is an 8-bit register for converting between serial data and parallel data. sion is used for both transmission and reception. data is shifted in (reception) or shifted out (transmissi on) beginning at either the msb side or the lsb side. (4) receive data buffer registers 30, 31 (sirb30, sirb31) the sirb3n register is a 16-bit buffer register that stores receive data. th is register is also divided into two registers: the higher 8 bits (sirb3nh) and lower 8 bits (sirb3nl). (5) transmit data csi buffer re gisters 30, 31 (sfdb30, sfdb31) the sfdb3n register is a 16-bit buffer regi ster that stores transmit data. this register is also divided into two registers: the higher 8 bits (sfdb3nh) and lower 8 bits (sfdb3nl). (6) csibuf status registers 30, 31 (sfa30, sfa31) the sfa3n register is an 8-bi t register that indicates t he status of csi data buffer r egister n (csibufn) or the transfer status. (7) transfer data length select registers 30, 31 (csil30, csil31) the csil3n register is an 8-bit register t hat selects the csi3n transfer data length. (8) transfer data number specificat ion registers 30, 31 (sfn30, sfn31) the sfn3n register is an 8-bit regi ster that sets the number of csi 3n transfer data in continuous mode. (9) csi data buffer register s 0, 1 (csibuf0, csibuf1) by consecutively writing transmit dat a to the sfdb3n register from where it is transferred, the data can be stored in the csibufn register wh ile the csibufn pointer for writing is automatically incremented (csibufn). the csibufn is a 16-bit buffer register. in the continuous mode, the data received in the csib ufn register can be sequentially read while the read csibufn pointer is automatically in cremented, by continuously readi ng the receive data from the sirb3n register. chapter 10 serial interface function user?s manual u16031ej3v0ud 520 figure 10-22. block diagram of cl ocked serial interfaces 30 and 31 son sckn intcsi3n sin sckn transfer control csi data buffer register n (csibufn) brgn prescaler output f x /4 receive data buffer register 3n (sirb3n) 15 0 intcovf3n transfer data control csibuf status register 3n (sfa3n) transmit data csi buffer register 3n (sfdb3n) selector note 1 note 2 f xclk clocked serial interface clock select register 3n (csic3n) mdln1 mdln0 cks3n2 cks3n1 cks3n0 mdln2 internal bus internal bus shift register n (sion) notes 1. in single mode 2. in continuous mode remarks 1. n = 0, 1 2. f x : main clock f xclk : base clock selected by cks3n2 to cks3n0 bits of csic3n register chapter 10 serial interface function user?s manual u16031ej3v0ud 521 10.3.3 control registers because csi30 shares pins with uartb0, the csi30 mode must be set in advance by using the pmc1 and pfc1 registers (see 10.1.1 switching between uartb0 and csi30 modes ). (1) clocked serial interface mode re gisters 30, 31 (csim30, csim31) the csim3n register controls the operation of csi3n (n = 0, 1). these registers can be read or wr itten in 8-bit or 1-bit units. be sure to clear bit 0 to 0. if it is set to 1, the operation is not guaranteed. cautions 1. writing the trmdn, dirn, csitn, an d cswen bits is enabled only when ctxen bit = 0 and crxen bit = 0. 2 be sure to set the external pins related to the csi3n function to control the mode before using csi3n. then set the csicaen bi t to 1 before setting the other bits. (1/2) csicae0 csicae1 csim30 csim31 ctxe0 ctxe1 5 crxe0 crxe1 trmd0 trmd1 3 dir0 dir1 2 csit0 csit1 1 cswe0 cswe1 0 0 address fffffd00h fffffd20h after reset 00h 00h 0 4 6 7 bit position bit name function 7 csicaen controls the operating clock. 0: stop clock supply to csi3n. 1: supply clock to csi3n. cautions 1. the csi3n unit is reset when the csicaen bit = 0, and csi3n is stopped. to operate csi3n, first set the csicaen bit to 1. 2. when rewriting the csicaen bit from 0 to 1 or from 1 to 0, simultaneously rewriting the bits other than the csicaen bit of the csim3n register is prohibited. when the csicaen bit = 0, rewriting the bits other than the csicaen bit of the csim3n register, and the sfdb3n, sfdb3nl, and sfa3n registers is prohibited. 6 ctxen enables or disables transmission. 1: disables transmission. 0: enables transmission. caution the ctxen bit is reset when the csicaen bit is cleared to 0. remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 522 (2/2) bit position bit name function 5 crxen enables or disables reception. 1: disables reception. 0: enables reception. caution the crxen bit is reset when the csicaen bit is cleared to 0. 4 trmdn specifies the transfer mode. 0: single mode 1: continuous mode 3 dirn specifies the transfer direction when data is written from the sfdb3n register to the csibufn register or read from the sirb3n and csibufn registers. 0: the first bit of transfer data is the msb. 1: the first bit of transfer data is the lsb. 2 csitn controls delay of the transmission completion interrupt signal (intcsi3n) (see 10.3.5 (14) delay control of transmission/reception completion interrupt (intcsi3n) ) . 0: no delay 1: delay mode (in the continuous mode (trmdn = 1), the next data transfer is delayed half a cycle because a delay of half a cycle is inserted when transfer of 1- bit data is complete.) cautions 1. the delay mode (csit bit = 1) is valid only in the master mode (when the cks3n2 to cks3n0 bits of the csic3n register are other than 111). in the slave mode (when the cks3n2 to cks3n0 bits are 111), do not set the delay mode. even if the delay mode is set, intcsi3n is not affected by the csitn bit. 2. if the csitn bit is set to 1 in the continuous mode (trmdn bit = 1), the intcsi3n interrupt is not output except when the last data set by the sfnn3 to sfnn0 bits of the sfn3n register is transferred, but a delay of half a clock can be inserted between each data transfer. 1 cswen enables or disables transfer wait. 0: disables transfer wait (1 wait cycle not inserted on starting transfer). 1: enables transfer wait (1 wait cycle inserted on starting transfer). caution inserting a transfer wait cycle (cswen bit = 1) is valid only in the master mode (cks3n2 to cks3n0 bits = other than 111 in the csic3n register). in the slave mode (cks3n2 to cks3n0 bits = 111), do not insert a transfer wait cycle. even if set, a transfer wait cycle is not inserted. remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 523 (2) clocked serial interface clock select registers 30, 31 (csic30, csic31) the csic3n register is an 8-bit regi ster that controls the operation clock and operating mode of csi3n. these registers can be read or wr itten in 8-bit or 1-bit units. caution data can be written to th e csic3n register only when the ct xen bit = 0 and crxen bit = 0 in the csim3n register. (1/3) mdl02 mdl12 csic30 csic31 mdl01 mdl11 5 mdl00 mdl10 ckp0 ckp1 3 dap0 dap1 2 cks302 cks312 1 cks301 cks311 cks300 cks310 address fffffd01h fffffd21h after reset 07h 07h 0 4 6 7 bit position bit name function specify the transfer clock (brgn output signal). mdln2 mdln1 mdln0 set value (n) transfer clock (brgn output signal) 0 0 0 ? brgn stop mode (power save) 0 0 1 1 f xclk /2 0 1 0 2 f xclk /4 0 1 1 3 f xclk /6 1 0 0 4 f xclk /8 1 0 1 5 f xclk /10 1 1 0 6 f xclk /12 1 1 1 7 f xclk /14 7 to 5 mdln2 to mdln0 caution in the slave mode (cks3n2 to cks3n0 bits = 111), it is recommended to clear the mdln2 to mdln0 bits to 000 (brgn stop mode). remark f xclk : base clock selected by cks3n2 to cks3n0 bits remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 524 (2/3) bit position bit name function specify the data transmission/ reception timing for sckn. ckpn dapn operation mode 0 0 d7 d6 d5 d4 d3 d2 d1 d0 sckn (i/o) sin capture son (output) 0 1 d7 d6 d5 d4 d3 d2 d1 d0 sckn (i/o) sin capture son (output) 1 note 0 d7 d6 d5 d4 d3 d2 d1 d0 sckn (i/o) sin capture son (output) 1 note 1 d7 d6 d5 d4 d3 d2 d1 d0 sckn (i/o) sin capture son (output) 4, 3 ckpn, dapn note if the ckpn bit is set to 1 in the master mode (cks3n2 to cks3n0 bits are other than 111), the sckn pin outputs a low level when it is inactive. if the ctxen bit of the csim3n register is cleared to 0 (disabling transmission) and crxen bit is cleared to 0 (disabling reception), the sckn pin outputs a high level. therefore, take the following meas ures to fix the sckn pin to low level when csi3n is not used. [sck0 pin (sck1 pin)] <1> clearing the p11 bit of the p1 register to 0 (clearing the p23 bit of the p2 register to 0): the port output level is set to low. <2> clearing the pm11 bit of the pm1 register to 0 (clearing the pm23 bit of the pm2 register to 0): the port is set in the output mode. <3> clearing the pmc11 bit of the pmc1 register to 0 (clearing the pmc23 bit of the pmc2 register to 0): the pin is set in the port mode (fixed to low-level output). <4> clearing the ctxe0 and crxe0 bits of the csim30 register to 0 (clearing the ctxe1 and crxe1 bits of the csim31 register to 0): transmission and reception are disabled. <5> setting the ctxe0 or crxe0 bit of the csim30 register to 1 (setting the ctxe1 or crxe1 bit of the csim31 register to 1): transmission or reception is enabled (both transmission and reception can also be enabled). <6> setting the pmc11 bit of the pmc1 register to 1 (setting the pmc23 bit of the pmc2 register to 1): the pin is set in the control mode (sck0 and sck1 pin output). because the register set values <1> and <2> ar e retained, control can be performed only by <3> to <6> once they have been set. remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 525 (3/3) bit position bit name function specify the base clock (prescaler output). cks3n2 cks3n1 cks3n0 set value (k) base clock (f xclk ) mode 0 0 0 0 f x /4 master mode 0 0 1 1 f x /8 master mode 0 1 0 2 f x /16 master mode 0 1 1 3 f x /32 master mode 1 0 0 4 f x /64 master mode 1 0 1 5 f x /128 master mode 1 1 0 6 f x /256 master mode 1 1 1 7 external clock (sckn) slave mode 2 to 0 cks3n2 to csk3n0 caution if the cks3n2 to cks3n0 bits of the csic3n register are cleared to 000, setting the mdln2 to mdln0 bits of the csic3n register to 001 is prohibited. remark f x : main clock remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 526 (3) receive data buffer registers 30, 31 (sirb30, sirb31) the sirb3n register is a 16-bit buffer register that stores receive data. by consecutively reading this register in the continu ous mode (trmdn bit = 1 in the csim3n register), the received data in the csibufn register can be sequent ially read while the csibufn pointer for reading is incremented. in the single mode (trmdn bit = 0 in the csim3n regi ster), received data is read by reading the sirb3n register and it is judged that t he sirb3n register has become empty. the sirb3n register is read-only, in 16-bit units. when the higher 8 bits of the sirb3n register are used as the sirb3nh register and the lower 8 bits as the sirb3nl register, these registers are read-only, in 8-bi t units. when reading in 8-bit units, be sure to read the sirb3nh register and sirb 3nl register in that order. 14 sirb 014 13 sirb 013 12 sirb 012 2 sirb 02 3 sirb 03 4 sirb 04 5 sirb 05 6 sirb 06 7 sirb 07 8 sirb 08 9 sirb 09 10 sirb 010 11 sirb 011 15 sirb 015 1 sirb 01 0 sirb 00 sirb30 address fffffd02h after reset note 0000h sirb 114 sirb 113 sirb 112 sirb 12 sirb 13 sirb 14 sirb 15 sirb 16 sirb 17 sirb 18 sirb 19 sirb 110 sirb 111 sirb 115 sirb 11 sirb 10 sirb31 fffffd22h 0000h note in continuous mode (trmdn bit = 1 in the csim3n register): undefined bit position bit name function 15 to 0 sirbn15 to sirbn0 store receive data. remarks 1. n = 0, 1 2. the sirb3n register is cleared to 0000h when the csicaen bit of the csim3n register is cleared to 0. chapter 10 serial interface function user?s manual u16031ej3v0ud 527 (4) transmit data csi buffer re gisters 30, 31 (sfdb30, sfdb31) the sfdb3n register is a 16-bit buffer register that stores transmit data. when transmit data is written to this register, the data is sequentially stored in the csibufn register while the csibufn pointer for writ ing is incremented. when the data of this register is read, the va lue of the transmit data written last is read. the sfdb3n register can be read or written in 16-bit units. when the higher 8 bits of the sfdb3n register are used as the sfdb3nh register, and the lower 8 bits as the sfdb3nl register, these registers can be read or written in 8-bit units. when reading in 8-bit units, be sure to read the sfdb3nh register and sf db3nl register in that order. 14 sfdb 014 13 sfdb 013 12 sfdb 012 2 sfdb 02 3 sfdb 03 4 sfdb 04 5 sfdb 05 6 sfdb 06 7 sfdb 07 8 sfdb 08 9 sfdb 09 10 sfdb 010 11 sfdb 011 15 sfdb 015 1 sfdb 01 0 sfdb 00 sfdb30 address fffffd06h after reset 0000h sfdb 114 sfdb 113 sfdb 112 sfdb 12 sfdb 13 sfdb 14 sfdb 15 sfdb 16 sfdb 17 sfdb 18 sfdb 19 sfdb 110 sfdb 111 sfdb 115 sfdb 11 sfdb 10 sfdb31 fffffd26h 0000h bit position bit name function 15 to 0 sfdbn15 to sfdbn0 store transmit data. remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 528 (5) csibuf status registers 30, 31 (sfa30, sfa31) these registers indicate the status of t he csibufn register or the transfer status. these registers can be read or written in 8-bit or 1-bit units (however, bits 6 to 0 can only be read. they do not change even if they are written). cautions 1. reading the sfa3n register is prohib ited when the csicaen bit of the csim3n register is 1 and when the main clock (f x ) is stopped. 2. because the values of the sffuln, sfem pn, csotn, and sfpn3 to sfpn0 bits may change at any time during tr ansfer, their values during tr ansfer may differ from the actual values. especially, use the csotn bi t independently (do not use this bit in relation with the other bits). to detect the end of transfer by th e sfa3n register, check to see if the sfempn bit is 1 after the data to be transferred has been written to the csibufn register. 3. if the sfa3n register is read immediatel y after data has been wr itten to the sfdb3n and sfdb3nl registers when the main clock (f x ) is 84 mhz or lower, the values of the sffuln, sfempn, and sfpn3 to sfpn0 bits do not change in time. 4. if the sfa3n register is read before the sffuln bit is set to 1 and the 17th data is written, the csibufn overflow inte rrupt (intcovf3n) is generated. (1/3) fpclr0 fpclr1 sfa30 sfa31 sfful0 sfful1 5 sfemp0 sfemp1 csot0 csot1 3 sfp03 sfp13 2 sfp02 sfp12 1 sfp01 sfp11 sfp00 sfp10 address fffffd08h fffffd28h after reset 20h 20h 0 4 6 7 bit position bit name function 7 fpclrn specifies clearing of the csibufn pointer. 0: no operation 1: clear all csibufn pointers to 0. cautions 1. this bit is always 0 when it is read. 2. if 1 is written to the fpclrn bit in the middle of transfer, transfer is aborted. because all the csibufn pointers are cleared to 0, the remaining data in the csibufn register is ignored. if 1 is written to the fpclrn bit, be sure to read the sfa3n register to check to see if all the csibufn pointers have been correctly cleared to 0 (sffuln bit = 0, sfempn bit = 1, sfpn3 to sfpn0 bits = 0000). nothing happens even if 0 is written to the fpclrn bit. remarks 1. n = 0, 1 2. the sfa3n register is set to 20h when the csic aen bit of the csim3n register is cleared to 0. chapter 10 serial interface function user?s manual u16031ej3v0ud 529 (2/3) bit position bit name function 6 sffuln this flag indicates the full status of the csibufn register. 0: csibufn register has a vacancy. 1: csibufn register is full. cautions 1. this bit is cleared to 0 when the csicaen bit of the csim3n register is cleared to 0 and the fpclr bit is set to 1. 2. if transfer of 16 data is specified in the continuous mode (trmdn bit = 1 in the csim3n register) (sfnn3 to sfnn0 bits = 0000 in the sfn3n register), the sffuln bit is set to 1 in the same way as in the single mode (trmdn bit = 0 in the csim3n register) when 16 data are in the csibufn register. if even one of the data has been completely transferred, the sffuln bit is cleared to 0. however, this does not mean that the csibufn register has a vacancy. 5 sfempn this flag indicates the empt y status of the csibufn register. 0: data is in csibufn register. 1: csibufn register is empty. cautions 1. this flag is set to 1 when the csicaen bit of the csim3n register is cleared to 0 and the fpclr bit is set to 1. 2. if the data written to the csibufn register has been transferred, the sfempn bit is set to 1 (even if receive data is stored in the csibufn register). 4 csotn this flag indicates transfer status. 0: idle status 1: transfer or transfer start processing in progress cautions 1. this flag is cleared to 0 when the csicaen bit of the csim3n register is cleared to 0 and the fpclrn bit is set to 1, or when the ctxen and crxen bits of the csim3n register are cleared to 0. 2. this flag is ?1? from when transfer is started until there is no more transfer data in the csibufn register in the single mode (trmdn bit = 0 in the csim3n register) or until the specified number of data has been transferred in the continuous mode (trmdn bit = 1 in the csim3n register). remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 530 (3/3) bit position bit name function 3 to 0 sfpn3 to sfpn0 ? in the single mode (trmdn bit = 0 in t he csim3n register), the ?number of transfer data remaining in csibufn register (csibufn pointer value for writing ? csibufn pointer value for sion loading)? can be read. ? in the continuous mode (trmdn bit = 1 in the csim3n register), the ?number of data completely transferred (value of csibufn pointer for sion loading/storing)? can be read. if the sfpn3 to sfpn0 bits are 0h, however, the number of transferred data is as follows, depending on the setting of the sfempn bit. when sfempn bit = 0: number of transferred data = 0 when sfempn bit = 1: number of transferred data = 16 or status before starting transfer (before writing transfer data) caution these bits are cleared to 0 in synchronization with the operating clock when the fpclrn bit = 1. however, the values of these bits are held until the csicaen bit of the csim3n register is cleared to 0 or the fpclrn bit is set to 1. remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 531 (6) transfer data length select registers 30, 31 (csil30, csil31) the csil3n register is used to select the transfer data length of csi3n. these registers can be read or wr itten in 8-bit or 1-bit units. be sure to clear bits 7 to 4 to 0. if they are set to 1, the operation is not guaranteed. caution the csil3n register may be transferring da ta when the ctxen or cr xen bit of the csim3n register is 1. be sure to clear the ctxen and crxen bits to 0 before writing data to the csil3n register. 0 0 csil30 csil31 0 0 5 0 0 0 0 3 ccl03 ccl13 2 ccl02 ccl12 1 ccl01 ccl11 ccl00 ccl10 address fffffd09h fffffd29h after reset 00h 00h 0 4 6 7 bit position bit name function specifies a transfer data length. ccln3 ccln2 ccln1 ccln0 transfer data length 0 0 0 0 16 bits 1 0 0 0 8 bits 1 0 0 1 9 bits 1 0 1 0 10 bits 1 0 1 1 11 bits 1 1 0 0 12 bits 1 1 0 1 13 bits 1 1 1 0 14 bits 1 1 1 1 15 bits other than above setting prohibited 3 to 0 ccln3 to ccln0 caution if a transfer data length other than 16 bits is specified (ccln3 to ccln0 bits = 0000), an undefined value is read to the higher excess bits of the sirb3n and csibufn registers (see 10.3.5 (3) data transfer direction specification function). remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 532 (7) transfer data number specificat ion registers 30, 31 (sfn30, sfn31) the sfn3n register is used to set the number of transfe r data of csi3n in the continuous mode (trmdn bit = 1 in the csim3n register). these registers can be read or wr itten in 8-bit or 1-bit units. ? ? sfn30 sfn31 ? ? 5 ? ? ? ? 3 sfn03 sfn13 2 sfn02 sfn12 1 sfn01 sfn11 sfn00 sfn10 address fffffd0ch fffffd2ch after reset 00h 00h 0 4 6 7 bit position bit name function specify the number of transfer data. sfnn3 sfnn2 sfnn1 sfnn0 number of transfer data 0 0 0 0 16 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 10 1 0 1 1 11 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15 3 to 0 sfnn3 to sfnn0 caution writing data exceeding the value set by the sfnn3 to sfnn0 bits (number of csi3n transfer data) to the csibufn register is prohibited (data is ignored even if written). remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 533 10.3.4 dedicated baud rate gene rators 0, 1 (brg0, brg1) the transfer clock of csi3n can be sele cted from the output of a dedicated baud rate generator or external clock (n = 0, 1). the serial clock source is specified by the csic3n register. in the master mode (cks3n2 to cks3n0 bits = other than 111 in the csic3n register), brgn is selected as the clock source. (1) transfer clock figure 10-23. transfer clock of csi3n clocked serial interface clock select register 3n (csic3n) selector prescaler (1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64) brgn (1/2, 1/4, 1/6, 1/8, 1/10, 1/12, 1/14) transfer clock f x /4 sckn mdln1 mdln0 cks3n2 cks3n1 cks3n0 mdln2 f xclk remarks 1. n = 0, 1 2. f x : main clock f xclk : base clock selected by cks3n2 to cks3n0 bits of csic3n register chapter 10 serial interface function user?s manual u16031ej3v0ud 534 (2) baud rate the baud rate is calculated by the following expression. [bps] 2 n f rate baud 1) (k + = f = f x /4 (f x : main clock) k = value set by cks3n2 to cks3n0 bits of csic3n register (k = 0, 1, 2, ?, 6) n = value set by mdln2 to mdln0 bits of csic3n register (n = 1, 2, 3, ?, 7) cautions 1. if the cks3n2 to cks3n0 bits of the csic3n regist er are cleared to 000, setting the mdln2 to mdln0 bits of the csic3n register to 001 is prohibited. 2. because the maximum transfer rate in the master mode (cks3n2 to cks3n0 bits = other than 111 in the csic3n register) is 5.5 mbps, do not exceed this value. example: when csi3n operates at 133 mhz, the maximum transfer rate is set when the cks3n2 to cks3n0 bits = 000 and th e mdln2 to mdln0 bits = 011, and at 150 mhz, when the cks3n2 to cks 3n0 bits = 000 and mdln2 to mdln0 bits = 100, in the csic3n register. chapter 10 serial interface function user?s manual u16031ej3v0ud 535 10.3.5 operation (1) operation modes table 10-6. operation modes trmdn bit cks3n2 to cks3n0 bits ctxen and crxen bits dirn bit csitn bit cswen bit disables transfer wait master mode enables/disables intcsi3n delay mode enables transfer wait single mode slave mode ? ? disables transfer wait master mode enables/disables intcsi3n delay mode enables transfer wait consecutive mode slave mode transmission/reception/ transmission and reception msb/lsb first ? ? remarks 1. ctxen bit: bit 6 of csim3n register crxen bit: bit 5 of csim3n register trmdn bit: bit 4 of csim3n register dirn bit: bit 3 of csim3n register csitn bit: bit 2 of csim3n register cswen bit: bit 1 of csim3n register cks3n2 to cks3n0 bits: bits 2 to 0 of csic3n register 2. n = 0, 1 (2) function of csi data buffer re gisters 0, 1 (csi buf0, csibuf1) by consecutively writing the transmit data to the sfdb3n register from where it is transferred, the data can be stored in the csibufn register whil e the csibufn pointer for writing is automatically incremented (the csibufn register size is 16 bits 16) (n = 0, 1). the condition under which transfer is to be started (sfempn bit = 0 in the sfa3n register) is satisfied when data is written to the lower 8 bits (sfdb3nl register) of the sfdb3n register. if a transfer data length of 9 bits or more is specified (ccln3 to ccln0 bits = 0000 or 1001 to 1111 in the csil3n register), data must be written to the sfdb3n register in 16-bit units or to t he sfdb3nh and sfdb3nl registers, in that order, in 8-bit units. if the transfer data length is set to 8 bits (ccln3 to ccln0 bits = 1000 in the csil3n register), data must be written to the sfdb3nl register in 8-bit units or to the sfdb3n register in 16-bit units. (if data is written to the sfdb3nl register in 16-bit units, however, the higher 8 bits of the data (of the sfdb3nh register) are ignored and not transferred). the sffuln bit of the sfa3n register is set to 1 when 16 data exist in the csibufn register and outputs a csibufn overflow interrupt (int covf3n) when the sffuln bit = 1 a nd when the 17th transfer data is written (17th transfer data is not written and ignored). sixteen data exist in the csibufn regi ster in the single mode (trmdn bi t = 0 in the csim3n register) when ?csibufn pointer value for writing = csibufn pointe r value for sion loading, and sffuln bit = 1 in the sfa3n register?. when the csibufn pointer for sion loading is incremented after completion of transfer, the csibufn register has a vacancy of one data (in th e continuous mode (trmdn bit = 1 in the csim3n register), the csibufn register does not have a vacancy even if one data has been transferred). chapter 10 serial interface function user?s manual u16031ej3v0ud 536 figure 10-24. function of csi da ta buffer register n (csibufn) csi data buffer register n (csibufn) 15 15 0 0 transfer data 0 transfer data 1 transfer data 2 transfer data 3 transfer data 4 transmit data csi buffer register 3n (sfdb3n) sfpn3 to sfpn0 70 3 4 csibuf status register 3n (sfa3n) incremented sion load csibufn pointer incremented write csibufn pointer sfdb3nh sfdb3nl 15 8 7 0 remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 537 (3) data transfer dir ection specification function the data transfer direction can be changed by using t he dirn bit of the csim3n register (n = 0, 1). (a) msb first (dirn bit = 0) figure 10-25. transfer data length: 8 bits (ccln3 to ccln0 bits = 1000 in csil3n register), transfer direction: msb first (dirn bit = 0 in csim3n register) (1/2) (i) transfer direction: msb first di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 sckn (i/o) sin (input) son (output) (ii) writing from sfdb3n re gister to csibufn register sfdb3n csibufn data 00h sion 15 8 7 0 son sin remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 538 figure 10-25. transfer data length: 8 bits (cc ln3 to ccln0 bits = 1000 in csil3n register), transfer direction: msb first (dirn bit = 0 in csim3n register) (2/2) ( iii) reading from sirb3n register (in single mode (trmdn bit of csim3n register = 0)) sirb3n (read value) undefined value data sion 15 8 7 0 son sin ( iv) reading from sirb3n register (in continuous mode (trmdn bit of csim3n register = 1)) sirb3n (read value) csibufn undefined value data sion 15 8 7 0 son sin remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 539 (b) lsb first (dirn bit = 1) figure 10-26. transfer data length: 8 bits (ccln3 to ccln0 bits = 1000 in csil3n register), transfer direction: lsb first (dirn bit = 1 in csim3n register) (1/2) (i) transfer direction: lsb first di0 di1 di2 di3 di4 di5 di6 di7 do0 do1 do2 do3 do4 do5 do6 do7 sckn (i/o) sin (input) son (output) (ii) writing from sfdb3n re gister to csibufn register sfdb3n csibufn data 00h sion 15 8 7 0 son sin remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 540 figure 10-26. transfer data length: 8 bits (ccln3 to ccln0 bits = 1000 in csil3n register), transfer direction: lsb first (dirn bit = 1 in csim3n register) (2/2) (iii) reading from sirb3n register (in single mode (trmdn bit of csim3n register = 0)) sirb3n (read value) 00h data sion 15 8 7 0 son sin (iv) reading from sirb3n register (in continu ous mode (trmdn bit of csim3n register = 1)) sirb3n (read value) csibufn 00h data sion 15 8 7 0 son sin remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 541 (4) transfer data length changing function the transfer data length can be set from 8 to 16 bits in 1-bit units, by using the ccln3 to ccln0 bits of the csil3n register (n = 1, 0). figure 10-27. transfer data length: 16 bits (ccln3 to ccln0 bits = 0000 in csil3n register), transfer direction: msb first (dirn bit = 0 in csim3n register) di15 di14 di13 di12 di2 di1 di0 do15 do14 do13 do12 do2 do1 do0 sckn (i/o) sin (input) son (output) remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 542 (5) function to select se rial clock and data phase the serial clock and data phase can be changed by using the ckpn and dapn bits of the csic3n register (n = 0, 1). figure 10-28. clock timing (a) when ckpn bit = 0, dapn bit = 0 intcsi3n interrupt sin capture sckn son d7 d6 d5 d4 d3 d2 d1 d0 (b) when ckpn bit = 0, dapn bit = 1 intcsi3n interrupt sin capture sckn son d7 d6 d5 d4 d3 d2 d1 d0 (c) when ckpn bit = 1, dapn bit = 0 intcsi3n interrupt sin capture sckn son d7 d6 d5 d4 d3 d2 d1 d0 (d) when ckpn bit = 1, dapn bit = 1 intcsi3n interrupt sin capture sckn son d7 d6 d5 d4 d3 d2 d1 d0 remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 543 (6) master mode the master mode is set and data is transferred with the transfer clock output to the sckn pin when the cks3n2 to cks3n0 bits of the csic3n register are set to a value other than 111 (sckn pin input is invalid) (n = 0, 1). the default output level of the sckn pin is high when th e ckpn bit of the csic3n register is 0, and low when the ckpn bit is 1. figure 10-29. master mode (ckpn and dapn bits = 00 in csic3n register, ccln3 to ccln0 bits = 1000 in csil3n re gister (transfer data length: 8 bits)) di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 sckn (output) sin (input) son (output) remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 544 (7) slave mode the slave mode is set when the cks3n2 to cks3n0 bits of the csic3n register are set to 111, and data is transferred with the transfer clock input to the sckn pi n (in the slave mode, it is recommended to set the mdln2 to mdln0 bits of the csic3n register to 000 and set the brgn stop mode) (n = 0, 1). figure 10-30. slave mode (ckpn and dapn bits = 00 in csic3n register, ccln3 to ccln0 bits = 1000 in csil3n re gister (transfer data length: 8 bits)) di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 sckn (input) sin (input) son (output) remark n = 0, 1 the conditions under which data can be transferred in the slave mode are listed in the table below. table 10-7. conditions under which da ta can be transferred in slave mode transfer mode ctxen bit crxen bit csibufn register sirb3n register and sion register transmission mode 1 0 data is in csibufn register (sfempn bit = 0). ? ? ? ? chapter 10 serial interface function user?s manual u16031ej3v0ud 545 (8) transfer clock selection function in the master mode (cks3n2 to cks3n0 bits = other than 111 in the csic3n register), the bit transfer rate can be selected by setting the cks3n2 to cks3n0 and mdln2 to mdln0 bits of the csic3n register (see 10.3.3 (2) clocked serial interface clock select regi sters 30, 31 (csic30, csic31) ). (9) single mode the single mode is set when the trmdn bit of the csim3n register is 0 (n = 0, 1). in this mode, transfer is started when the ctxen bit or crxen bit is set to 1 and when data is in the csibufn register (sfempn bit = 0 in the sfa3n register). if no data is in the csibufn register (sfempn bit = 1) , transfer is kept waiting until transmit data or dummy data is written to the sfdb3n register. when data is transferred to the csib ufn register while transmission or reception is enabled (ctxen or crxen bit is 1), the csotn bit of the sf a3n register (transfer status flag) is set to 1. if transfer is not in the wait status, the transfer data indicated by the sion load csibufn pointer is loaded from the csibufn register to the sion register, and transfer processing is started. if the sirb3n register is empty when one data has been transferred in the reception mode or transmission/reception mode, the received data is stored from the sion register to the sirb3n register, the transmission/reception completion interrupt (intcsi3n) is output, and the sion load csibufn pointer is incremented. if transmit data or du mmy data is stored in the csibufn r egister, the next transfer processing is started. however, st oring the receive data in the sirb3n regi ster, outputting the intcsi3n interrupt, and incrementing the sion load csibufn pointer are held pe nding, until the previously received data is read from the sirb3n register and the si rb3n register becomes empty. in the transmission mode, the intcsi3n interrupt is out put and the sion load pointer is incremented when transfer processing of one data has been completed (the sirb3n register is always empty because no data is stored from the sion register to the sirb3n register). in all modes (transmission, reception, and transmission/ reception modes), if the cs ibufn register is empty (write csibufn pointer value = sion load csibufn pointer value) when transfer processing of one data has been completed, the csotn bit is cleared to 0. the value of the ?number of remaining data in the csibufn register (write csibufn pointer ? sion load pointer)? can always be read from the sfpn3 to sfpn0 bits of the sfa3n register. caution be sure to confirm that the sffuln bit of the sfa3n register is 0 when writing data to the sfdb3n register. even if data is written to this register when sffuln bit is 1, the csibufn overflow interrupt (intcovf3n) is out put, and the written data is ignored. chapter 10 serial interface function user?s manual u16031ej3v0ud 546 figure 10-31. single mode sion sirb3n son sin csi data buffer register n (csibufn) 15 15 0 0 transfer data 0 transfer data 1 transfer data 2 transfer data 3 transfer data 4 transmit data csi buffer register 3n (sfdb3n) sfpn3 to sfpn0 70 3 4 csibuf status register 3n (sfa3n) incremented sion load csibufn pointer incremented write csibufn pointer sfdb3nh sfdb3nl 15 8 7 0 difference remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 547 (10) continuous mode the continuous mode is set when the trmdn bit of the csim3n register is 1 (n = 0, 1). in this mode, transfer is started when the ctxen bit or crxen bit is 1 and when data is in the csibufn register (sfempn bit = 0 in the sfa3n register). at th is time, set the number of transfer data in advance by using the sfnn3 to sfnn0 bits of the sfn3n regist er. if data exceeding the number of transfer data specified by the sfnn3 to sfnn0 bits of the sfn3n register are written to the csibufn register, the excess data are ignored and not transferred. if no data is in the csibufn register (sfempn bit = 1) , transfer is kept waiting until transmit data or dummy data is written to the sfdb3n register. if data is transferred to the csibufn register when tr ansmission or reception is enabled (ctxen or crxen bit is 1), the csotn bit (transfer stat us flag) of the sfa3n register is set to 1 and the transfer data indicated by the sion load/store csibufn pointer is loaded from t he csibufn register to sion register. then transfer processing is started. when transfer processing of one data is completed in the reception mode or transmission/reception mode, the received data is overwritten from the sion register to the transfer data in the csibufn register indicated by the sion load/store csibufn pointer , and then the pointer is increment ed. by consecutively reading the transfer data from the sirb3n register after all data in the csibufn regi ster have been transferred (when the intcsi3n interrupt has occurred), the receive data can be sequentially read while the read csibufn pointer is incremented. in the transmission mode, the sion load/store csibufn pointer is incremented when transfer processing of one data has been completed. in all modes (transmission, reception, and transmissi on/reception modes), when data has been transferred by the value set by the sfnn3 to sfnn0 bits of the sf n3n register, the csotn bit is cleared to 0 and the transmission/reception completion in terrupt (intcsi3n) is output. to transfer the next data, be sure to write 1 to t he fpclrn bit of the sfa3n register and clear all the csibufn pointers to 0. the ?number of transferred data (sion load/store cs ibufn pointer value)? can always be read from the sfpn3 to sfpn0 bits of the sfa3n register. caution the sfa3n register is in the same status when transfer data is written (before start of transfer) after the csibufn pointer is cleare d (fpclrn bit = 1 in the sfa3n register) and when 16 data have been transferred (sffuln bit = 0, sfempn bit = 1, sfpn3 to sfpn0 bits = 0000 in the sfa3n register). chapter 10 serial interface function user?s manual u16031ej3v0ud 548 figure 10-32. continuous mode transfer data 0 sirb3n son sin csi data buffer register n (csibufn) 15 15 0 0 transfer data 1 transfer data 2 transfer data 3 transmit data csi buffer register 3n (sfdb3n) sfpn3 to sfpn0 70 3 4 csibuf status register 3n (sfa3n) incremented read csibufn pointer incremented sion load/store csibufn pointer incremented write csibufn pointer sfdb3nh sfdb3nl 15 8 7 0 sion note 1 note 2 note 1 notes 1. reception 2. transmission remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 549 (11) transmission mode the transmission mode is set when the ctxen bit of the csim3n register is set to 1 and the crxen bit is cleared to 0. in this mode, transmission is started by a trigger that writes transmit data to the sfdb3n register or sets the ctxen bit to 1 when transmit data is in the csibufn register (n = 0, 1). even in the single mode (trmdn bit = 0 in the csim3n register), whether the sirb3n or sion register is empty has nothing to do with starting transmission. the value inpu t to the sin pin during transmission is latched in the shift register (sion) but is not transferred to the si rb3n and csibufn registers at the end of transmission. the transmission/reception completion in terrupt (intcsi3n) occurs immediat ely after data is sent out from the sion register. (12) reception mode the reception mode is set when the ctxen bit of the csim 3n register is cleared to 0 and crxen bit is set to 1. in this mode, reception is star ted by using the processing of writi ng dummy data to the sfdb3n register as a trigger (n = 0, 1). in the single mode (trmdn bit = 0 in the csim3n register), however, the condition of starting reception includes that the sirb 3n or sion register is empty. (if reception to the sion register is completed when the previously received data is held in the sirb3n register without being read, the previously received data is read from the sirb 3n register and the wait status c ontinues until the sirb3n register becomes empty.) in the continuous mode, reception starts by writing dummy data of the number of receive data to the sfdb3n register wit h the first dummy data write processing taken as a trigger. the son pin outputs a low level. the transmission/reception completi on interrupt (intcsi3n) occurs immediately after receive data is transferred from the sion register to the sirb3n register. (13) transmission/reception mode the transmission/reception mode is set when both the ct xen and crxen bits of the csim3n register are set to 1. in this mode, transmission/reception is start ed by using the processing to write transmit data to the sfdb3n register as a trigger (n = 0, 1). in the single mode (trmdn bit = 0 in the csim3n register), however, the condition of starting transmission /reception includes that the sirb3n or sion register is empty. (if reception to the sion register is completed when the pr eviously received data is held in the sirb3n register without being read, the previously received data is read from the sirb3n register and the wait status continues until the sirb3n register becomes empty.) chapter 10 serial interface function user?s manual u16031ej3v0ud 550 (14) delay control of transmission/r eception completion interrupt (intcsi3n) in the master mode (cks3n2 to cks3n0 bits = other than 111 in the csic3n register), occurrence of the transmission/reception completion interrupt (intcsi3n) ca n be delayed by half a clock (1/2 serial clock), depending on the setting (1) of the csitn bit of the csim3n r egister. the csitn bit is valid only in the master mode. in the slave mode (cks3n2 to cks3n0 bits = 111 in the csic3n register), setting the csitn bit to 1 is prohibited (even if set, the intcsi3n interrupt is not affected). caution if the csitn bit of the csim 3n register is set to 1 in the continuous mode (trmdn bit = 1 in the csim3n register), the intcsi3n interrupt is not output at the end of data other than the last data set by the sfnn3 to sfnn0 bits of the sfn3n register, but a delay of half a clock can be inserted between each data transfer. figure 10-33. delay control of transmission/ reception completion interrupt (intcsi3n): csitn bit = 1 in csic3n register, cswen bit = 0, ckpn and dapn bits = 00, ccln3 to ccln0 bits = 1000 in csil3n re gister (transfer data length: 8 bits) di7 di7 di6 di5 di4 di3 di2 di1 di0 delay do7 do6 do5 do4 do3 do2 do1 do0 do7 sckn (output) sin (input) son (output) intcsi3n interrupt delay note note if the csitn bit of the csim3n register is set to 1 in the continuous mode (trmdn bit = 1 in the csim3n register), the intcsi3n interrupt is not output at the end of data other than the last data set by the sfnn3 to sfnn0 bits of the sfn3n register, but a delay of hal f a clock can be inserted between each data transfer. remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 551 (15) enabling/disabling transfer wait in the master mode (cks3n2 to cks3n0 bits = other t han 111 in the csic3n register), starting transfer can be delayed by one clock for each time 1-bit data transf er is started, depending on the setting (1) of the cswen bit of the csim3n register (cswen bit = 1 (trans fer wait inserted)). the cswen bit is valid only in the master mode. in the slave mode (cks3n2 to cks 3n0 bits = 111 in the csic3n register), setting the cswen bit to 1 is prohibited (even if set, transfer wait is not inserted). figure 10-34. enabling/disabling transfer wait (a) csitn bit = 0, cswen bit = 1, ckpn and dapn bits = 00, ccln3 to ccln0 bits = 1000 (tr ansfer data length: 8 bits) di7 di6 di5 do7 do6 do5 sckn (output) sin (input) son (output) di7 di1 di0 wait do1 do0 do7 (b) csitn bit = 1, cswen bit = 1, ckpn and dapn bits = 00, ccln3 to ccln0 bits = 1000 (tr ansfer data length: 8 bits) di7 di6 di5 do7 do6 do5 sckn (output) sin (input) son (output) intcsi3n interrupt di7 di1 di0 wait delay do1 do0 do7 delay remark n = 0, 1 chapter 10 serial interface function user?s manual u16031ej3v0ud 552 (16) output pins (a) sckn pin the sckn pin outputs a high level when both the ctxen and crxen bits of the csim3n register are 0 (n = 0, 1). in the master mode (cks3n2 to cks3n0 bits = other than 111 in the csic3n register), this pin outputs the default level when the fpclrn bit of the sfa3n register is set to 1. table 10-8. default output level of sckn pin ckpn bit cks3n2 to cks3n0 bits default output level of sckn pin 111 (slave mode) high level note 0 other than 111 (master mode) high level 111 (slave mode) ? (input) 1 other than 111 (master mode) low level note default value after reset or value when csicaen bit = 0 in the csim3n register remarks 1. the output of the sckn pin changes if the ckpn bit is rewritten in the master mode. 2. n = 0, 1 (b) son pin the son pin outputs a low level when both the ctxen and crxen bits of the csim3n register are 0 (n = 0, 1). this pin outputs a low level when the fpclrn bit of the sfa3n register is 1 (the previous value is retained only in the slave mode (cks3n2 to cks3n0 bits = 111 in the csic3n register) and when the dapn bit = 0 in the csic3n register). table 10-9. default output level of son pin default output level of son pin low level note note default value after reset or value when csicaen bit = 0 in the csim3n register remark n = 0, 1 (17) csibufn overflow in terrupt signal (intcovf3n) the intcovf3n interrupt is output when 16 data exist in the csibufn register and when the 17th data is written (to the sfdb3n or sf db3nl register) (the 17th data is not written but ignored). in the single mode (trmdn bit = 0 in the csim3n register), 16 data exist in the csibufn register when ?write csibufn pointer value = sion load csibufn pointer value and sffuln bit = 1 in the sfa3n register?. when transfer is completed and the sion load csibufn pointer is incremented, the csibufn register has one vacancy (the csibufn register has no vacancy even when transfer of one data has been completed in the continuous mode (trmdn bit = 1 in the csim3n register)). chapter 10 serial interface function user?s manual u16031ej3v0ud 553 10.3.6 usage (1) single mode (in master mode and transmission mode) <1> set the external pins related to the csi3n function to control mode. <2> when the csicaen bit of the csim3n register is se t to 1, supplying the operating clock is enabled. <3> specify the transfer mode by se tting the csic3n and csil3n registers. <4> write 1 to the fpclrn bit of the sfa3n regi ster to clear all the csibufn pointers to 0. <5> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bits = 0000 in the sfa3n register. <6> specify the transfer mode by using the trmdn, dirn, csitn, and cswen bits of the csim3n register and, at the same time, enable transmission by setting the ctxen bit to 1. <7> confirm that the sffuln bit of the sfa3n regist er is 0, and then write transfer data to the sfdb3n register. if it is clearly known that the sffuln bit is 0 because transfer da ta is written to that bit by the interrupt servicing routine of intcsi 3n, it is not always necessary to confirm that the sffuln bit is 0. <8> confirm that the intcsi3n interrupt has occurred a nd the sfempn bit of the sf a3n register is 1, and disable transmission by clearing the ctxen bit of the csim3n register to 0 (end of transmission). caution to execute further transfer, repeat <7> before <8>. (2) single mode (in master mode and reception mode) <1> set the external pins related to the csi3n function to control mode. <2> when the csicaen bit of the csim3n register is se t to 1, supplying the operating clock is enabled. <3> specify the transfer mode by se tting the csic3n and csil3n registers. <4> write 1 to the fpclrn bit of the sfa3n regi ster to clear all the csibufn pointers to 0. <5> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bits = 0000 in the sfa3n register. <6> specify the transfer mode by using the trmdn, dirn, csitn, and cswen bits of the csim3n register and, at the same time, enable reception by setting the crxen bit to 1. <7> confirm that the sffuln bit of the sfa3n register is 0, and then write dummy transfer data to the sfdb3n register (reception start trigger). if it is clearly known that the sffuln bit is 0 because dummy transfer data is written to that bit by the interrupt servicing rout ine of intcsi3n, it is not always necessary to confirm that the sffuln bit is 0. <8> confirm that the intcsi3n interrupt has occurred, and then r ead the sirb3n register. <9> confirm that the intcsi3n interrupt has occurred and the sfempn bit is 1, and disable reception by clearing the crxen bit of the csim3n register to 0 (end of reception). cautions 1. to execute further tran sfer, repeat <7> and <8> before <9>. 2. the son pin outputs a lo w level but this is invalid. chapter 10 serial interface function user?s manual u16031ej3v0ud 554 (3) single mode (in master mode and transmission/reception mode) <1> set the external pins related to the csi3n function to control mode. <2> when the csicaen bit of the csim3n register is se t to 1, supplying the operating clock is enabled. <3> specify the transfer mode by se tting the csic3n and csil3n registers. <4> write 1 to the fpclrn bit of the sfa3n regi ster to clear all the csibufn pointers to 0. <5> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bits = 0000 in the sfa3n register. <6> specify the transfer mode by using the trmdn, dirn, csitn, and cswen bits of the csim3n register and, at the same time, enable transmission/recept ion by setting the ctxen and crxen bits to 1. <7> confirm that the sffuln bit of the sfa3n regist er is 0, and then write transfer data to the sfdb3n register. if it is clearly known that the sffuln bit is 0 because transfer da ta is written to that bit by the interrupt servicing routine of intcsi 3n, it is not always necessary to confirm that the sffuln bit is 0. <8> confirm that the intcsi3n interrupt has occurred, and then r ead the sirb3n register. <9> confirm that the intcsi3n interrupt has occurred and the sfempn bit is 1, and disable transmission/reception by clearing the ctxen and cr xen bits of the csim3n register to 0 (end of transmission/reception). caution to execute further transfer, repeat <7> and <8> before <9>. (4) single mode (in slave m ode and transmission mode) <1> set the external pins related to the csi3n function to control mode. <2> when the csicaen bit of the csim3n register is se t to 1, supplying the operating clock is enabled. <3> specify the transfer mode by se tting the csic3n and csil3n registers. <4> write 1 to the fpclrn bit of the sfa3n regi ster to clear all the csibufn pointers to 0. <5> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bits = 0000 in the sfa3n register. <6> specify the transfer mode by using the trmdn, dirn, csitn, and cswen bits of the csim3n register and, at the same time, enable transmission by setting the ctxen bit to 1. <7> confirm that the sffuln bit of the sfa3n regist er is 0, and then write transfer data to the sfdb3n register. if it is clearly known that the sffuln bit is 0 because transfer da ta is written to that bit by the interrupt servicing routine of intcsi 3n, it is not always necessary to confirm that the sffuln bit is 0. <8> confirm that the intcsi3n interrupt has occurred and the sfempn bit is 1, and disable transmission by clearing the ctxen bit of the csim3n register to 0 (end of transmission). caution to execute further transfer, repeat <7> before <8>. chapter 10 serial interface function user?s manual u16031ej3v0ud 555 (5) single mode (in slave mode and reception mode) <1> set the external pins related to the csi3n function to control mode. <2> when the csicaen bit of the csim3n register is se t to 1, supplying the operating clock is enabled. <3> specify the transfer mode by se tting the csic3n and csil3n registers. <4> write 1 to the fpclrn bit of the sfa3n regi ster to clear all the csibufn pointers to 0. <5> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bits = 0000 in the sfa3n register. <6> specify the transfer mode by using the trmdn, dirn, csitn, and cswen bits of the csim3n register and, at the same time, enable reception by setting the crxen bit to 1. <7> confirm that the sffuln bit of the sfa3n register is 0, and then write dummy transfer data to the sfdb3n register (reception start trigger). if it is clearly known that the sffuln bit is 0 because dummy transfer data is written to that bit by the interrupt servicing rout ine of intcsi3n, it is not always necessary to confirm that the sffuln bit is 0. <8> confirm that the intcsi3n interrupt has occurred, and then r ead the sirb3n register. <9> confirm that the intcsi3n interrupt has occurred and the sfempn bit is 1, and disable reception by clearing the crxen bit of the csim3n register to 0 (end of reception). cautions 1. to execute further tran sfer, repeat <7> and <8> before <9>. 2. the son pin outputs a lo w level but this is invalid. (6) single mode (in slave mode and transmission/reception mode) <1> set the external pins related to the csi3n function to control mode. <2> when the csicaen bit of the csim3n register is se t to 1, supplying the operating clock is enabled. <3> specify the transfer mode by se tting the csic3n and csil3n registers. <4> write 1 to the fpclrn bit of the sfa3n regi ster to clear all the csibufn pointers to 0. <5> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bits = 0000 in the sfa3n register. <6> specify the transfer mode by using the trmdn, dirn, csitn, and cswen bits of the csim3n register and, at the same time, enable transmission/recept ion by setting the ctxen and crxen bits to 1. <7> confirm that the sffuln bit of the sfa3n regist er is 0, and then write transfer data to the sfdb3n register. if it is clearly known that the sffuln bit is 0 because transfer da ta is written to that bit by the interrupt servicing routine of intcsi 3n, it is not always necessary to confirm that the sffuln bit is 0. <8> confirm that the intcsi3n interrupt has occurred, and then r ead the sirb3n register. <9> confirm that the intcsi3n interrupt has occurred and the sfempn bit is 1, and disable transmission/reception by clearing the ctxen and cr xen bits of the csim3n register to 0 (end of transmission/reception). caution to execute further transfer, repeat <7> and <8> before <9>. chapter 10 serial interface function user?s manual u16031ej3v0ud 556 (7) continuous mode (in mast er mode and transmission mode) <1> set the external pins related to the csi3n function to control mode. <2> when the csicaen bit of the csim3n register is se t to 1, supplying the operating clock is enabled. <3> specify the transfer mode by se tting the csic3n and csil3n registers. <4> write 1 to the fpclrn bit of the sfa3n regi ster to clear all the csibufn pointers to 0. <5> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bits = 0000 in the sfa3n register. <6> specify the transfer mode by using the trmdn, dirn, csitn, and cswen bits of the csim3n register and, at the same time, enable transmission by setting the ctxen bit to 1. <7> set the amount of data to be transmitted by usi ng the sfnn3 to sfnn0 bits of the sfn3n register. <8> write the amount of data to be transmitted to t he sfdb3n register as transfer data. writing data exceeding the set value of the sfn3n register is prohibited. <9> confirm that the intcsi3n interrupt has occurred and the sfempn bit is 1. then write 1 to the fpclrn bit of the sfa3n register, and clear all the csibufn pointers to 0 in preparation for the next transfer. <10> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bi ts = 0000 in the sfa3n register. <11> disable transmission by clearing the ctxen bit of the csim3n register to 0 (end of transmission). caution to execute further transfer, re peat <7> to <10> before <11>. (8) continuous mode (in m aster mode and reception mode) <1> set the external pins related to the csi3n function to control mode. <2> when the csicaen bit of the csim3n register is se t to 1, supplying the operating clock is enabled. <3> specify the transfer mode by se tting the csic3n and csil3n registers. <4> write 1 to the fpclrn bit of the sfa3n regi ster to clear all the csibufn pointers to 0. <5> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bits = 0000 in the sfa3n register. <6> specify the transfer mode by using the trmdn, dirn, csitn, and cswen bits of the csim3n register and, at the same time, enable reception by setting the crxen bit to 1. <7> set the amount of data to be received by usi ng the sfnn3 to sfnn0 bits of the sfn3n register. <8> write dummy transfer data of the number of re ceive data to the sfdb3n register. the first dummy transfer data write is the trigger to start reception. writing dummy data exceeding the set value of the sfn3n register is prohibited. <9> confirm that the intcsi3n interrupt has occurred an d the sfempn bit is 1. then read the receive data from the sirb3n register (seque ntially read the receive data stor ed in the csibufn register). <10> write 1 to the fpclrn bit of the sfa3n register, and clear all the cs ibufn pointers to 0 in preparation for the next transfer. <11> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bi ts = 0000 in the sfa3n register. <12> disable reception by clearing the crxen bit of the csim3n register to 0 (end of reception). cautions 1. to execute further transf er, repeat <7> to <11> before <12>. 2. the son pin outputs a low level. chapter 10 serial interface function user?s manual u16031ej3v0ud 557 (9) continuous mode (in master m ode and transmission/reception mode) <1> set the external pins related to the csi3n function to control mode. <2> when the csicaen bit of the csim3n register is set to 1, supplying the operating clock is enabled. <3> specify the transfer mode by se tting the csic3n and csil3n registers. <4> write 1 to the fpclrn bit of the sfa3n regi ster to clear all the csibufn pointers to 0. <5> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bi ts = 0000 in the sfa3n register. <6> specify the transfer mode by using the trmdn, dirn, csitn, and cswen bits of the csim3n register and, at the same time, enable transmission/recepti on by setting both the ctxen and crxen bits to 1. <7> set the amount of data to be transmitted/received by using the sfnn3 to sf nn0 bits of the sfn3n register. <8> write the amount of data to be transmitted to the sfdb3n register as transfer data. writing data exceeding the set value of the sfn3n register is prohibited. <9> confirm that the intcsi3n interrupt has occurred an d the sfempn bit is 1. then read the receive data from the sirb3n register (seque ntially read the receive data stor ed in the csibufn register). <10> write 1 to the fpclrn bit of the sfa3n register, and clear all the cs ibufn pointers to 0 in preparation for the next transfer. <11> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bi ts = 0000 in the sfa3n register. <12> disable transmission/reception by clearing the ctxen and crxen bits of the csim3n register to 0 (end of transmission/reception). caution to execute further transfer, re peat <7> to <11> before <12>. (10) continuous mode (in sl ave mode and transmission mode) <1> set the external pins related to the csi3n function to control mode. <2> when the csicaen bit of the csim3n register is set to 1, supplying the operating clock is enabled. <3> specify the transfer mode by se tting the csic3n and csil3n registers. <4> write 1 to the fpclrn bit of the sfa3n regi ster to clear all the csibufn pointers to 0. <5> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bi ts = 0000 in the sfa3n register. <6> specify the transfer mode by using the trmdn, dirn, csitn, and cswen bits of the csim3n register and, at the same time, enable transmission by setting the ctxen bit to 1. <7> set the amount of data to be transmitted by usi ng the sfnn3 to sfnn0 bits of the sfn3n register. <8> write the amount of data to be transmitted to the sfdb3n register as transfer data. writing data exceeding the set value of the sfn3n register is prohibited. <9> confirm that the intcsi3n interrupt has occurred and the sfempn bit is 1. then write 1 to the fpclrn bit of the sfa3n register, and clear all the csibufn pointers to 0 in preparation for the next transfer. <10> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bi ts = 0000 in the sfa3n register. <11> disable transmission by clearing the ctxen bit of the csim3n register to 0 (end of transmission). caution to execute further transfer, re peat <7> to <10> before <11>. chapter 10 serial interface function user?s manual u16031ej3v0ud 558 (11) continuous mode (in slave mode and reception mode) <1> set the external pins related to the csi3n function to control mode. <2> when the csicaen bit of the csim3n register is set to 1, supplying the operating clock is enabled. <3> specify the transfer mode by se tting the csic3n and csil3n registers. <4> write 1 to the fpclrn bit of the sfa3n regi ster to clear all the csibufn pointers to 0. <5> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bi ts = 0000 in the sfa3n register. <6> specify the transfer mode by using the trmdn, dirn, csitn, and cswen bits of the csim3n register and, at the same time, enable reception by setting the crxen bit to 1. <7> set the amount of data to be received by usi ng the sfnn3 to sfnn0 bits of the sfn3n register. <8> write dummy transfer data of the number of re ceive data to the sfdb3n register. the first dummy transfer data write is the trigger to start reception. writing dummy data exceeding the set value of the sfn3n register is prohibited. <9> confirm that the intcsi3n interrupt has occurred an d the sfempn bit is 1. then read the receive data from the sirb3n register (seque ntially read the receive data stor ed in the csibufn register). <10> write 1 to the fpclrn bit of the sfa3n register, and clear all the cs ibufn pointers to 0 in preparation for the next transfer. <11> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bi ts = 0000 in the sfa3n register. <12> disable reception by clearing the crxen bit of the csim3n register to 0 (end of reception). cautions 1. to execute further transf er, repeat <7> to <11> before <12>. 2. the son pin outputs a low level. (12) continuous mode (in slave mode and transmission/reception mode) <1> set the external pins related to the csi3n function to control mode. <2> when the csicaen bit of the csim3n register is set to 1, supplying the operating clock is enabled. <3> specify the transfer mode by se tting the csic3n and csil3n registers. <4> write 1 to the fpclrn bit of the sfa3n regi ster to clear all the csibufn pointers to 0. <5> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bi ts = 0000 in the sfa3n register. <6> specify the transfer mode by using the trmdn, dirn, csitn, and cswen bits of the csim3n register and, at the same time, enable transmission/recepti on by setting both the ctxen and crxen bits to 1. <7> set the number of data to be transmitted/receiv ed by using the sfnn3 to sfnn0 bits of the sfn3n register. <8> write the amount of data to be transmitted to the sfdb3n register as transfer data. writing data exceeding the set value of the sfn3n register is prohibited. <9> confirm that the intcsi3n interrupt has occurred an d the sfempn bit is 1. then read the receive data from the sirb3n register (seque ntially read the receive data stor ed in the csibufn register). <10> write 1 to the fpclrn bit of the sfa3n register, and clear all the cs ibufn pointers to 0 in preparation for the next transfer. <11> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bi ts = 0000 in the sfa3n register. <12> disable transmission/reception by clearing the ctxen and crxen bits of the csim3n register to 0 (end of transmission/reception). caution to execute further transfer, re peat <7 to <11> before <12>. chapter 10 serial interface function user?s manual u16031ej3v0ud 559 10.3.7 cautions the following points must be not ed when using csi3n (n = 0, 1). (1) the csi3n unit is reset and csi3n is stopped when the csicaen bit of the csim3n register is cleared to 0. to operate csi3n, first set the csicaen bit to 1. usually, before clearing the csicaen bit to 0, clear both the ctxen and crxen bits to 0 (after the end of transfer). (2) be sure to write 1 to the fpclrn bit of the sfa 3n register to clear all the csibufn pointers to 0 before enabling transfer by setting the ctxen or crxen bit of th e csim3n register to 1. if the ctxen or crxen bit is set to 1 without clearing the pointers, and if t he previously transferred dat a remains in the csibufn register, transferring that dat a is immediately started. if transfer data is set to the csibufn register before tran sfer is enabled, transfer is started as soon as the ctxen or crxen bit is set to 1. (3) if the sfa3n register is read immediately after data has been written to the sfdb3n and sfdb3nl registers when the main clock (f x ) is used at 84 mhz or lower, the sffuln, sfempn, and sfpn3 to sfpn0 bits of the sfa3n register may not change their values in time. if the sfa3n register is read before the sffuln bit is set to 1 and a 17th data is written, the csibufn overflow interrupt (intcovf3n) occurs. user?s manual u16031ej3v0ud 560 chapter 11 usb function controller (usbf) the v850e/me2 has an internal usb function controller (usbf) conforming to the universal serial bus specification. 11.1 overview ? conforms to the universal serial bus specification. ? supports 12 mbps (full-speed) transfer ? endpoint for transfer incorporated endpoint name fifo size (bytes) transfer type remark endpoint0 read 64 control transfer ? endpoint0 write 64 control transfer ? endpoint1 64 2 bulk 1 transfer (in) 2-buffer configuration endpoint2 64 2 bulk 1 transfer (out) 2-buffer configuration endpoint3 64 2 bulk 2 transfer (in) 2-buffer configuration endpoint4 64 2 bulk 2 transfer (out) 2-buffer configuration endpoint7 8 interrupt 1 transfer ? endpoint8 8 interrupt 2 transfer ? ? clock: clock input from uck pin (f usb = 48 mhz) caution when using the usb functi on, be sure to set (1) the uckcnt bit of the uckc register. if the registers related to the usb functi on while the uckcnt bit is 0, 0 is read. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 561 11.2 configuration usb sie i/o buffer endpoint endpoint0r (64 bytes) endpoint0w (64 bytes) endpoint1 (64 bytes 2) endpoint2 (64 bytes 2) endpoint3 (64 bytes 2) endpoint4 (64 bytes 2) endpoint7 (64 bytes) endpoint8 (64 bytes) selector usbsp2b intusb2b intrsum f usb (48 mhz) intusb1b intusb0b usbsp4b ufdrqn dmaakn tcn udm udp usb function 0 dma channel select register (uf0cs) usb function 0 buffer control register (uf0bc) remark n = 0 to 3 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 562 11.3 requests 11.3.1 automatic requests (1) decode the following tables show the request formats and correspondence between requests and decoded values. table 11-1. request format offset field name 0 bmrequesttype 1 brequest 2 lower side 3 wvalue higher side 4 lower side 5 windex higher side 6 lower side 7 wlength higher side chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 563 table 11-2. correspondence between requests and decoded values decoded value response bmrequesttype brequest w value windex wlength offset request 0 1 3 2 5 4 7 6 df ad cf data stage get_interface 81h 0ah 00h 00h 00h 0nh 00h 01h stall stall ack nak get_configuration 80h 08h 00h 00h 00h 00h 00h 01h ack nak ack nak ack nak get_descriptor device 80h 06h 01h 00h 00h 00h xxh xxh note 1 ack nak ack nak ack nak get_descriptor configuration 80h 06h 02h 00h 00h 00h xxh xxh note 1 ack nak ack nak ack nak get_status device 80h 00h 00h 00h 00h 00h 00h 02h ack nak ack nak ack nak get_status endpoint 0 82h 00h 00h 00h 00h 00h 80h 00h 02h ack nak ack nak ack nak get_status endpoint x 82h 00h 00h 00h 00h $$h 00h 02h stall stall ack nak clear_feature device note 2 00h 01h 00h 01h 00h 00h 00h 00h ack nak ack nak ack nak clear_feature endpoint 0 note 2 02h 01h 00h 00h 00h 00h 80h 00h 00h ack nak ack nak ack nak clear_feature endpoint x note 2 02h 01h 00h 00h 00h $$h 00h 00h stall stall ack nak set_feature device note 3 00h 03h 00h 01h 00h 00h 00h 00h ack nak ack nak ack nak set_feature endpoint 0 note 3 02h 03h 00h 00h 00h 00h 80h 00h 00h ack nak ack nak ack nak set_feature endpoint x note 3 02h 03h 00h 00h 00h $$h 00h 00h stall stall ack nak set_interface 01h 0bh 00h 0#h 00h 0?h 00h 00h stall stall ack nak set_configuration note 4 00h 09h 00h 00h 01h 00h 00h 00h 00h ack nak ack nak ack nak set_address 00h 05h xxh xxh 00h 00h 00h 00h ack nak ack nak ack nak notes 1. if the wlength value is less than the prepared value, the wlength value is retur ned; if the wlength value is greater than the prepared value, the prepared value is returned. 2. the clear_feature request clears uf0 device status register l (uf0dstl) and uf0 epn status register l (uf0ensl) (n = 0 to 4, 7, 8) when ack is received in the status stage. remark : data stage is provided : data stage is not provided chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 564 notes 3. the set_feature request sets the uf0 device status register l (uf0dstl) and uf0 epn status register l (uf0ensl) (n = 0 to 4, 7, 8) when ack is received in the status stage. if the e0halt bit of the uf0e0sl register is set, a stall response is made in the status stage or data stage of control transfer for a request other than the get_status endpoint0 request, set_feature endpoint0 request, and a request generated by the cpudec interrupt request, until the clear_feature endpoint0 request is received. a stall response to an unsupported request does not set the e0halt bit of the uf0e0sl register to 1, and the stall response is cleared as soon as the next setup token has been received. 4. if the wvalue is not the default value, an automatic stall response is made. cautions 1. the sequence of control transfer defi ned by the universal serial bus specification is not satisfied under the following conditions. the operation is not guaranteed under these conditions. ? if an in/out token is suddenly received without a setup stage ? if data pid1 is sent in the data phase of the setup stage ? if a token of 128 addresses or more is received ? if the request data transmitted in th e setup stage is of less than 8 bytes 2. an ack response is made even when the hos t transmits data other than a null packet in the status stage. 3. if the wlength value is 00 h during control transfer (read) of fw processing, a null packet is automatically transmitted for c ontrol transfer (without data). the fw request does not automatically transmit a null packet. remarks 1. df: default state, ad: addres sed state, cf: configured state 2. n = 0 to 4 it is determined by the setting of the uf0 acti ve interface number register (uf0aifn) whether a request with interface number 1 to 4 is correctly responded to, depending on whether the interface number of the target is valid or not. 3. $$: valid endpoint number including transfer direction the valid endpoint is determined by the currently set alternate setting number (see 11.4.1 (36) uf0 active alternative setting register (uf0aas) , (38) uf0 endpoint 1 interface mapping register (uf0e1im) to (43) uf0 endpoint 8 interf ace mapping register (uf0e8im) ). 4. ? and #: value transmitted from host (information on interface numbers 0 to 4) it is determined by the uf0 active interface nu mber register (uf0aifn) and uf0 active alternative setting register (uf0aas) whether an alternate setting request co rresponding to each interface number is correctly responded to or not, depending on whether the interface number and alternate setting of the target are valid or not. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 565 (2) processing the processing of an automat ic request in the default state, addr essed state, and configured state is described below. remark default state: state in which an opera tion is performed with the default address addressed state: state afte r an address has been allocated configured state: state a fter set_configuration wvalue = 1 has been correctly received (a) clear_feature() request a stall response is made in the status stage if t he clear_feature() request cannot be cleared, if feature does not exist, or if the target is an interf ace or an endpoint that does not exist. a stall response is also made if the wlength value is other than 0. ? default state: the correct response is made when the clear_feature() request has been received only if the target is a device or a request for endpoint0; otherwise a stall response is made in the status stage. ? addressed state: the correct response is made when the clear_feature() request has been received only if the target is a device or a request for endpoint0; otherwise a stall response is made in the status stage. ? configured state: the correct response is made when the clear_feature() request has been received only if the target is a device or a request for an endpoint that exists; otherwise a stall response is made in the status stage. when the clear_feature() request has been correctly processed, the corresponding bit of the uf0 clr request register (uf0clr) is set to 1, the enhalt bit of the uf0 epn status register l (uf0ensl) is cleared to 0, and an interrupt is issued (n = 0 to 4, 7, 8). if the clear_feature() request is received when the subject is an endpoint, the toggle bit (that c ontrols switching between data0 and data1) of the corresponding endpoint is always re-set to data0. (b) get_configuration() request a stall response is made in the data stage if any of wvalue, windex, or wlengt h is other than the values shown in table 11-2. ? default state: the value stored in the uf0 configuration register (uf0cnf) is returned when the get_configuration() request has been received. ? addressed state: the value stored in the uf0cnf register is returned when the get_configuration() request has been received. ? configured state: the value stored in the uf0cnf register is returned when the get_configuration() request has been received. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 566 (c) get_descriptor() request if the subject descriptor has a length that is a multiple of wmaxpacketsize, a null packet is returned to indicate the end of the data stage. if the length of the descriptor at this time is less than the wlength value, the entire descriptor is returned; if the length of the descriptor is greater than the wlength value, the descriptor up to the wlength value is returned. ? default state: the value stored in uf0 de vice descriptor register n (uf0ddn) and uf0 configuration/interface/endpoint descriptor re gister m (uf0ciem) is returned (n = 0 to 17, m = 0 to 255) when the get_descriptor() request has been received. ? addressed state: the value stor ed in the uf0ddn register and uf0c iem register is returned when the get_descriptor() request has been received. ? configured state: the value stor ed in the uf0ddn register and uf0c iem register is returned when the get_descriptor() request has been received. a descriptor of up to 256 bytes can be stored in the uf 0ciem register. to return a descriptor of more than 256 bytes, set the cdcgdst bit of the uf0modc r egister to 1 and process the get_descriptor() request by fw. store the value of the total number of bytes of the descriptor set by the uf0ciem register ? 1 in the uf0 descriptor length register (uf0dscl). the transfer dat a is controlled by the value of this data + 1 and wlength. (d) get_interface() request if either of wvalue and wlength is other than that shown in table 11-2, or if windex is other than that set by the uf0 active interface number register (uf0ai fn), a stall response is made in the data stage. ? default state: a stall response is made in the data stage when the get_interface() request has been received. ? addressed state: a stall response is made in the data stage when the get_interface() request has been received. ? configured state: the value stored in the uf0 interf ace n register (uf0ifn) corresponding to the windex value is returned (n = 0 to 4) when the get_interface() request has been received. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 567 (e) get_status() request a stall response is made in the data stage if any of wvalue, windex, or wlengt h is other than the values shown in table 11-2. a stall response is also made in the data stage if the target is an interface or an endpoint that does not exist. ? default state: the value stor ed in the target status register note is returned only when the get_status() request has been received and when the request is for a device or endpoint0; otherwise a stall response is made in the data stage. ? addressed state: the value stor ed in the target status register note is returned only when the get_status() request has been received and when the request is for a device or endpoint0; otherwise a stall response is made in the data stage. ? configured state: the value st ored in the target status register note is returned only when the get_status() request has been received and when the request is for a device or an endpoint that exists; otherwise a stall response is made in the data stage. note the target status register is as follows. ? if the target is a device: uf0 de vice status register l (uf0dstl) ? if the target is endpoint 0: uf0 ep0 status register l (uf0e0sl) ? if the target is endpoint n: uf0 epn status register l (uf0ensl) (n = 1 to 4, 7, 8) (f) set_address() request a stall response is made in the status stage if eith er of windex or wlength is other than the values shown in table 11-2. a stall response is also made if the specified device address is greater than 127. ? default state: the device enters the address ed state and changes the usb address value to be input to sie into a specified address value if the specified address is other than 0 when the set_address() request has been received. if the specified address is 0, the device remains in the default state. ? addressed state: the device enters the default state and returns the usb address value to be input to sie to the default address if the spec ified address is 0 when the set_address() request has been received. if the specifi ed address is other than 0, the device remains in the addressed state, and changes the usb address value to be input to sie into a specified new address value. ? configured state: the device remains in the c onfigured state and returns the usb address value to be input to sie to the default address if the specified address is 0 when the set_address() request has been received. in this case, the endpoints other than endpoint 0 remain valid, and control transfer (in), control transfer (out), bulk transfer and interrupt transfer for an endpoint other than endpoint 0 are also acknowledged. if the specified address is other than 0, the device remains in the configured state and changes the usb address value to be input to sie into a specified new address value. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 568 (g) set_configuration() request if any of wvalue, windex, or wlength is other than th e values shown in table 11-2, a stall response is made in the status stage. ? default state: the conf bit of the uf0 mode status register (uf0mods) and the uf0 configuration register (uf0cnf) are set to 1 if the s pecified configuration value is 1 when the set_configuration() request has been receiv ed. if the specified configuration value is 0, the conf bit of the uf0mods register and uf 0cnf register are cleared to 0. in other words, the device ski ps the addressed state and moves to the configured state in which it re sponds to the default address. ? addressed state: the conf bit of the uf0mods register and uf0cnf register are set to 1 and the device enters the configured state if the specified config uration value is 1 when the set_configuration() request has been receiv ed. if the specified configuration value is 0, the device remains in the addressed state. ? configured state: the conf bi t of the uf0mods register and uf0c nf register are set to 1 and the device returns to the addressed state if th e specified configuration value is 0 when the set_configuration() request has been receiv ed. if the specified configuration value is 1, the device rema ins in the configured state. if the set_configuration() request has been correctl y processed, the target bit of the uf0 set request register (uf0set) is set to 1, and an interrupt is issued. all halt features are cleared after the set_configuration() request has been completed even if the specified confi guration value is the same as the current configuration value. if the set_configuration() request has been correctly processed, the data toggle of all endpoints is always initialized to data0 again (it is defined that the default status, alternative setting 0, is set from when the set_configuration request is received to when the set_interface request is received). (h) set_feature() request a stall response is made in the status stage if t he set_feature() request is fo r a feature that cannot be set or does not exist, or if the target is an inte rface or an endpoint that does not exist. a stall response is also made if the wlength value is other than 0. ? default state: the correct response is made when the set_feature() request has been received, only if the request is for a device or endpoint0; otherwise a stall response is made in the status stage. ? addressed state: the correct response is made when the set_feature() request has been received, only if the request is for a device or endpoint0; otherwise a stall response is made in the status stage. ? configured state: the correct response is ma de when the set_feature() request has been received, only if the request is for a device or an endpoint that exists; otherwise a stall response is made in the status stage. when the set_feature() request has been correctly proc essed, the target bit of the uf0 set request register (uf0set) and the enhalt bit of the uf0 epn status register l (uf0ensl) are set to 1, and an interrupt is issued (n = 0 to 4, 7, 8). chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 569 (i) set_interface() request if wlength is other than the values shown in table 11-2 , if windex is other than the value set to the uf0 active interface number register (uf0aifn), or if wvalue is other than the value set to the uf0 active alternative setting register (uf0aas), a sta ll response is made in the status stage. ? default state: a stall response is made in the status stage when the set_interface() request has been received. ? addressed state: a stall response is made in the status stage when the set_interface() request has been received. ? configured state: null packet is transmitted in the status stage when the set_interface() request has been received. when the set_interface() request has been correctly pr ocessed, an interrupt is issued. all the halt features of the endpoint linked to the target in terface are cleared after the set_interface() request has been cleared. the data toggle of all the endpoi nts related to the target interface number is always initialized again to data0. when the currently selected alternative setting is to be changed by correctly processing the set_interface() reques t, the fifo of the endpoint t hat is affected is completely cleared, and all the related interrupt sources are also initialized. when the set_interface() request has been completed, the fifo of all the endpoints linked to the target interface are cleared. at the same time, halt feature and data pid are initialized, and the related uf0 int status n register (uf0isn) is cleared to 0 (n = 0 to 4). (only halt feature and data pid are cleared when the set_configuration request has been completed.) chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 570 11.3.2 other requests (1) response and processing the following table shows how other req uests are responded to and processed. table 11-3. response and processing of other requests request response and processing get_descriptor string generation of cpudec interrupt request get_status interface automatic stall response clear_feature interface automatic stall response set_feature interface automatic stall response all set_descriptor generation of cpudec interrupt request all other requests generation of cpudec interrupt request chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 571 11.4 register configuration 11.4.1 control registers (1) uf0 ep0nak register (uf0e0n) this register controls nak of endpoint0 (except an automatically executed request). this register can be read or written in 8-bit units (however, bit 0 can only be read). it takes five usb clocks to reflect the status on this register after the uf0fic0 and uf0fic1 registers have been set. if it is necessary to read the status correctly, therefore, separa te a write signal that accesses the uf0fic0 and uf0fic1 registers from a read signal that accesse s the uf0eps0, uf0eps1, uf0eps2, uf0e0n, and uf0en registers by at least four usb clocks. while nak is being transmitted to endpoint0 read, en dpoint2, and endpoint4, a write access to the ep0nkr bit is ignored. 0 uf0e0n 0 5 00 3 0 2 0 1 ep0nkr ep0nkw address fffffe00h after reset 00h 0 4 6 7 bit position bit name function 1 ep0nkr this bit controls nak to the out toke n to endpoint0 (except an automatically executed request). it is automatically set to 1 by hardware when endpoint0 has correctly received data. it is also cleared to 0 by hardware when the data of the uf0e0r register has been read by fw (counter value = 0). 1: transmit nak. 0: do not transmit nak (default value). set this bit to 1 by fw when data should not be received from the usb bus for some reason even when usbf is ready for receiv ing data. in this case, usbf continues transmitting nak until this bit is cleared to 0 by fw. this bit is also cleared to 0 as soon as the uf0e0r register has been cleared. 0 ep0nkw this bit indicates how nak to the in token to endpoint0 is controlled (except an automatically executed request). this bit is automatically cleared to 0 by hardware when the data of endpoint0 is transmitted and the host correctly receives the transmitted data. the data of the uf0e0w register is retained until this bit is cleared. therefore, it is not necessary to rewrite this bit even in the case of a retransmission re quest that is made if the host could not receive data correctly. to send a short packet, be sure to set the e0ded bit of the uf0dend register to 1. this bit is automatically set to 1 when the fifo is full. as soon as the e0ded bit of the uf0dend register is set to 1, the ep0nkw bit is automatically set to 1 at the same time. 1: do not transmit nak. 0: transmit nak (default value). if control transfer enters the status stage while ack cannot be correctly received in the data stage, this bit is cleared to 0 as soon as t he uf0e0w register is cleared. this bit is also cleared to 0 when uf0e0w is cleared by fw. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 572 next, the procedure of a setup transaction t hat uses in/out tokens is explained below. (a) when in token is used (except a re quest automatically executed by hardware) fw should be used to clear the prot bit of the uf0is1 register to 0 after receiving the cpudec interrupt and before reading data from the uf0e0st register. next, perform processing in accordance with the request and, if it is necessary to return data by an in token, write data to the uf0e0w register. confirm that the prot bit of the uf0is1 register is 0 after writing has been completed, and set the e0ded bit of the uf0dend register to 1. the hardware sends out data at the first in token after the ep0nkw bit has been set to 1. if the prot bit of the uf0is1 regist er is 1, it indicates that a setup transaction has occurred again before completion of control transfer. in this case, clear the protc bit of the uf0ic1 register to 0 and clear the prot bit of the uf0is1 register to 0, and then read data from the uf0e0st register again. a request received later can be read. (b) when out token is used (except a re quest automatically executed by hardware) fw should be used to clear the prot bit of the uf0is1 register after receiving the cpudec interrupt and before reading data from the uf0e0st register. confir m that the prot bit of t he uf0is1 register is 0 before reading data from the uf0e0r regi ster. if the prot bit is 1, it me ans that invalid data is retained. clear the fifo by fw (the ep0nkr bi t is automatically cleared to 0). if the prot bit of the uf0is1 register is 0, read the data of t he uf0e0l register and read as many data from the uf0e0r register as set. when reading data from the uf0e0r register ha s been completed (when the counter of the uf0e0r register has been cleared to 0), the hardwar e automatically clears the ep0nkr bit to 0. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 573 (2) uf0 ep0nakall register (uf0e0na) this register controls nak to all the requests of endpoint 0. it is also valid for automatically executed requests. this register can be read or written in 8-bit units. 0 uf0e0na 0 5 00 3 0 2 0 1 0 ep0nka address fffffe01h after reset 00h 0 4 6 7 bit position bit name function 0 ep0nka this bit controls nak to a transaction other than a setup transaction to endpoint0 (including an automatically executed request ). this bit is manipulated by fw. 1: transmit nak. 0: do not transmit nak (default value). this register is used to prevent a conflict between a write access by fw and a read access from sie when the data used for an automatically executed request is to be changed. it postpones reflecting a write access on this bit from fw while an access from sie is being made. before rewriting the request data register from fw, confirm that this bit has been correctly set to 1. setting this bit to 1 is reflected only in the following cases. ? immediately after usbf has been reset and a setup token has never been received ? immediately after reception of bus reset and a setup token has never been received ? pid of a setup token has been detected ? the stage has been changed to the status stage clearing this bit to 0 is reflected immediatel y, except while an in token is being received and a nak response is being made. setting the ep0nka bit to 1 is reflected in the above four cases during endpoint0 transfer, but it is reflected immediately after data has been written to the bit while endpoint0 is transferring no data. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 574 (3) uf0 epnak register (uf0en) this register controls nak of endpoints other than endpoint0. this register can be read or written in 8-bit units (however, bits 5, 4, 1, and 0 can only be read). the bko2nk bit can be written only when the bko2nkm bi t of the uf0enm register is 1 and the bko1nk bit can be written only when the bko1nkm bi t of the uf0enm register is 1. the related bits are invalid if each endpoint is not suppor ted by the setting of the uf0enim register (n = 1 to 4, 7, 8) and the current setting of the interface. it takes five usb clocks to reflect the status on this register after the uf0fic0 and uf0fic1 registers have been set. if it is necessary to read the status correctly, therefore, separa te a write signal that accesses the uf0fic0 and uf0fic1 registers from a read signal that accesse s the uf0eps0, uf0eps1, uf0eps2, uf0e0n, and uf0en registers by at least four usb clocks. while nak is being transmitted to endpoint0 read, e ndpoint2, and endpoint4, a write access to the bko1nk and bko2nk bits is ignored. be sure to clear bits 7 and 6 to 0. if it is set to 1, the operation is not guaranteed. (1/4) 0 uf0en 0 5 it2nk it1nk 3 bko2nk 2 bko1nk 1 bki2nk bki1nk address fffffe02h after reset 00h 0 4 6 7 bit position bit name function 5 it2nk this bit controls nak to endpoint8 (interrupt 2 transfer). it is automatically set to 1 and transmission is started when the uf0int2 register has become full as a result of writing data to it. to send a short packet that does not make the fifo full, set the it2dend bit of the uf0dend register to 1. as soon as the it2dend bit has been set to 1, this bit is automatically set to 1. 1: do not transmit nak. 0: transmit nak (default value). this bit is also cleared to 0 when the uf0int2 register has been cleared. 4 it1nk this bit controls nak to endpoint7 (interrupt 1 transfer). it is automatically set to 1 and transmission is started when the uf0int1 register has become full as a result of writing data to it. to send a short packet that does not make the fifo full, set the it1dend bit of the uf0dend register to 1. as soon as the it1dend bit has been set to 1, this bit is automatically set to 1. 1: do not transmit nak. 0: transmit nak (default value). this bit is also cleared to 0 when the uf0int1 register has been cleared. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 575 (2/4) bit position bit name function 3 bko2nk this bit controls nak to endpoint4 (bulk 2 transfer (out)). 1: transmit nak. 0: do not transmit nak (default value). this bit is set to 1 only when the fifo connected to the sie side of the uf0bo2 register (64-byte fifo of bank configuration) cannot receive data. it is cleared to 0 when a toggle operation is performed. the bank is changed (toggle operation) when the following conditions are satisfied. ? data correctly received is stored in the fifo connected to the sie side. ? the value of the fifo counter connect ed to the cpu side is 0 (completion of reading). fw should be used to read data of the uf0bo2l register when it has received the blko2dt interrupt request and read as many data from the uf0bo2 register as the value of that data. to not receive data from the usb bus for some reason even if usbf is ready to receive data, set this bit to 1 by fw. in this case, usbf keeps transmitting nak until the fw clears this bit to 0. this bi t is also cleared to 0 as soon as the uf0bo2 register has been cleared. 2 bko1nk this bit controls nak to endpoint2 (bulk 1 transfer (out)). 1: transmit nak. 0: do not transmit nak (default value). this bit is set to 1 only when the fifo connected to the sie side of the uf0bo1 register (64-byte fifo of bank configuration) cannot receive data. it is cleared to 0 when a toggle operation is performed. the bank is changed (toggle operation) when the following conditions are satisfied. ? data correctly received is stored in the fifo connected to the sie side. ? the value of the fifo counter connect ed to the cpu side is 0 (completion of reading). fw should be used to read data of the uf0bo1l register when it has received the blko1dt interrupt request and read as many data from the uf0bo1 register as the value of that data. to not receive data from the usb bus for some reason even if usbf is ready to receive data, set this bit to 1 by fw. in this case, usbf keeps transmitting nak until the fw clears this bit to 0. this bi t is also cleared to 0 as soon as the uf0bo1 register has been cleared. cautions 1. if dma is enabled while data is bein g read from the uf0bo2 re gister in the pio mode, a dma request is immediately issued. 2. if the last data of the fifo on the cpu side is read in the dma transfer mode, the dma request signal becomes inactive. 3. if the tc signal is received in the dma transfer mode, the dma request signal becomes inactive. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 576 (3/4) bit position bit name function 1 bki2nk this bit controls nak to endpoint3 (bulk 2 transfer (in)). 1: do not transmit nak. 0: transmit nak (default value). this bit is cleared to 0 only when the fifo connected to the sie side of the uf0bi2 register (64-byte fifo of bank configuration) cannot receive data. it is set to 1 when a toggle operation is performed (the data of the uf0bi2 register is retained until transmission has been correctly completed) . the bank is changed (toggle operation) when the following conditions are satisfied. ? data is correctly written to the fifo connected to the cpu bus side (writing has been completed and the fifo is full or the uf0dend register is set). ? the value of the fifo counter connected to the sie side is 0. this bit is automatically set to 1 and data transmission is started when the fifo on the cpu side becomes full and a fifo toggle operation is performed as a result of writing data to the fifo. however, if the fifo on the cpu side becomes full as a result of writing data to it by dma while the bki2t bit of the uf0dend register is cleared to 0, the toggle operation is not performed because the condition of the toggle operation is not satisfied until the bki2ded bit of the uf0dend register is set to 1. to send a short packet that does not make the fifo on the cpu side full, set the bki2ded bit to 1 after completing writing data. when the bki2ded bit is set to 1, a toggle operation is performed and at the same time, this bit is automat ically set to 1. this bit is also cleared to 0 as soon as the uf0bi2 register has been cleared. cautions 1. if dma is enabled wh ile data is being writte n to the uf0bi2 register in the pio mode, a dma request is immediately issued. 2. if 64-byte data is written in the dm a transfer mode, the dma request signal becomes inactive. if the bki2nk bit is then set to 1, da ta is transmitted in synchronization with an in token. the dma request signal becomes acti ve again as long as the dma request is not masked as soon as the fifo is toggled. if the bki2nk bit is not set, data is not transmitted even if an in token has been received. in this case, set the bki2ded bit of the uf0dend register to 1. 3. if the tc signal is received in the dma transfer mode, the dma request signal becomes inactive. at the same time, the dma request is masked. if the bki2nk bit is not set to 1, data is not transmitted even if an in token is received. when the bki2ded bit of the uf0dend register is set to 1 by fw, data is transmitted in synchronization with the in token. to execute dma transfer again, unmask the dma request. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 577 (4/4) bit position bit name function 0 bki1nk this bit controls nak to endpoint1 (bulk 1 transfer (in)). 1: do not transmit nak. 0: transmit nak (default value). this bit is cleared to 0 only when the fifo connected to the sie side of the uf0bi1 register (64-byte fifo of bank configuration) cannot receive data. it is set to 1 when a toggle operation is performed (the data of the uf0bi1 register is retained until transmission has been correctly completed) . the bank is changed (toggle operation) when the following conditions are satisfied. ? data is correctly written to the fifo connected to the cpu bus side (writing has been completed and the fifo is full or the uf0dend register is set). ? the value of the fifo counter connected to the sie side is 0. this bit is automatically set to 1 and data transmission is started when the fifo on the cpu side becomes full and a fifo toggle operation is performed as a result of writing data to the fifo. however, if the fifo on the cpu side becomes full as a result of writing data to it by dma while the bki1t bit of the uf0dend register is cleared to 0, the toggle operation is not performed because the condition of the toggle operation is not satisfied until the bki1ded bit of the uf0dend register is set to 1. to send a short packet that does not make the fifo on the cpu side full, set the bki1ded bit to 1 after completing writing data. when the bki1ded bit is set to 1, a toggle operation is performed and at the same time, this bit is automat ically set to 1. this bit is also cleared to 0 as soon as the uf0bi1 register has been cleared. cautions 1. if dma is enabled wh ile data is being writte n to the uf0bi1 register in the pio mode, a dma request is immediately issued. 2. if 64-byte data is written in the dm a transfer mode, the dma request signal becomes inactive. if the bki1nk bit is then set to 1, da ta is transmitted in synchronization with an in token. the dma request signal becomes acti ve again as long as the dma request is not masked as soon as the fifo is toggled. if the bki1nk bit is not set, data is not transmitted even if an in token has been received. in this case, set the bki1ded bit of the uf0dend register to 1. 3. if the tc signal is received in the dma transfer mode, the dma request signal becomes inactive. at the same time, the dma request is masked. if the bki1nk bit is not set to 1, data is not transmitted even if an in token is received. when the bki1ded bit of the uf0dend register is set to 1 by fw, data is transmitted in synchronization with the in token. to execute dma transfer again, unmask the dma request. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 578 (4) uf0 epnak mask register (uf0enm) this register controls masking a wr ite access to the uf0en register. this register can be read or written in 8-bit units. be sure to clear bits 7 to 4, 1, and 0. if it is set to 1, the operation is not guaranteed. 0 uf0enm 0 5 00 3 bko2nkm 2 bko1nkm 1 00 address fffffe03h after reset 00h 0 4 6 7 bit position bit name function 3 bko2nkm this bit specifies whether a write access to bit 3 (bko2nk) of the uf0en register is masked or not. 1: do not mask. 0: mask (default value). 2 bko1nkm this bit specifies whether a write access to bit 2 (bko1nk) of the uf0en register is masked or not. 1: do not mask. 0: mask (default value). chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 579 (5) uf0 sndsie register (uf0sds) this register performs manipulation such as no handsha ke. it can directly manipulate the pins of sie. this register can be read or written in 8-bit units. be sure to clear bit 2 to 0. if it is set to 1, the operation is not guaranteed. 0 uf0sds 0 5 00 3 sndstl 2 0 1 0 rsumin address fffffe04h after reset 00h 0 4 6 7 bit position bit name function 3 sndstl this bit makes endpoint0 issue a stall hand shake. setting this bit to 1 if a request for cpudec processing is not supported by the system results in a stall handshake response. if an unsupported wvalue is sent by the set_configuration or set_interface request, the hardware sets this bit to 1. if a problem occurs in endpoint0 due to overrun of an automatically exec uted request, this bit is also set to 1. however, the e0halt bit of the uf0e0sl register is not set to 1. 1: respond with stall handshake. 0: do not respond with stall handshake (default value). this bit is cleared to 0 and the handshake re sponse to the bus is other than stall when the next setup token is received. to set the sndstl bit to 1 by fw, do not write data to the uf0e0w register. depending on the ti ming of setting this bit, the stall response is not made in time, and it may be made to the next transfer after a nak response has been made. setting this bit is valid only while an fw-e xecuted request is under execution when this bit is set to 1. it is automatically cleared to 0 when the next setup token is received. remark the sndstl bit is valid only for an fw-executed request. 0 rsumin this bit outputs the resume signal onto t he usb bus. writing this bit is invalid unless the rmwk bit of the uf0dstl register is set to 1. 1: generate the resume signal. 0: do not generate the resume signal (default value). while this bit is set to 1, the resume signal continues to be generated. clear this bit to 0 by fw after a specific time has elapsed. be cause the signal is internally sampled at the clock, the operation is guaranteed only while cl k is supplied. care must be exercised when clk of the system is stopped. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 580 (6) uf0 clr request register (uf0clr) this register indicates the target of the received clear_feature request. this register is read-only, in 8-bit units. this register is meaningful only when an interrupt request is generated. each bit is set to 1 after completion of the status stage, and automat ically cleared to 0 when this register is read. the related bits are invalid if each endpoint is not suppor ted by the setting of the uf0enim register (n = 1 to 4, 7, 8) and the current setting of the interface. clrep8 uf0clr clrep7 5 clrep4 clrep3 3 clrep2 2 clrep1 1 clrep0 clrdev address fffffe05h after reset 00h 0 4 6 7 bit position bit name function 7 to 1 clrepn these bits indicate that a cl ear_feature endpoint n request is received and automatically processed. 1: automatically processed 0: not automatically processed (default value) 0 clrdev this bit indicates that a clear_feature device request is received and automatically processed. 1: automatically processed 0: not automatically processed (default value) remark n = 0 to 4, 7, 8 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 581 (7) uf0 set request register (uf0set) this register indicates the tar get of the automatically proce ssed set_xxxx (except set_interface) request. this register is read-only, in 8-bit units. this register is meaningful only when an interrupt request is generated. each bit is set to 1 after completion of the status stage, and automat ically cleared to 0 when this register is read. setcon uf0set 0 5 00 3 0 2 setep 1 0 setdev address fffffe06h after reset 00h 0 4 6 7 bit position bit name function 7 setcon this bit indicates that a set_config uration request is received and automatically processed. 1: automatically processed 0: not automatically processed (default value) 2 setep this bit indicates that a set_feature endpoint n request (n = 0 to 4, 7, 8) is received and automatically processed. 1: automatically processed 0: not automatically processed (default value) 0 setdev this bit indicates that a set_feature device request is received and automatically processed. 1: automatically processed 0: not automatically processed (default value) chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 582 (8) uf0 ep status 0 register (uf0eps0) this register indicates the usb bus status a nd the presence or absence of register data. this register is read-only, in 8-bit units. the related bits are invalid if each endpoint is not suppor ted by the setting of the uf0enim register (n = 1 to 4, 7, 8) and the current setting of the interface. it takes five usb clocks to reflect the status on this register after the uf0fic0 and uf0fic1 registers have been set. if it is necessary to read the status co rrectly, therefore, separate writing to the uf0fic0 and uf0fic1 registers from reading from the uf0eps0, uf0eps1, uf0eps2, uf0e0n , and uf0en registers by at least four usb clocks. (1/2) it2 uf0eps0 it1 5 bkout2 bkout1 3 bkin2 2 bkin1 1 ep0w ep0r address fffffe07h after reset 00h 0 4 6 7 bit position bit name function 7, 6 itn these bits indicate that data is in t he uf0intn register (fifo). by setting the itnded bit of the uf0dend register to 1, the status in which data is in the uf0intn register can be created even if data is not written to the regi ster (null data transmission). as soon as the itnded bit of the uf0dend register is set to 1 even when the counter of the uf0intn register is 0, this bit is set to 1 by hardware. it is cleared to 0 after correct transmission. 1: data is in the register. 0: no data is in the register (default value). 5, 4 bkoutn these bits indicate that data is in the uf0bon register (fifo) connected to the cpu side. when the fifo configuring the uf0bon re gister is toggled, this bit is automatically set to 1 by hardware. it is automatically cleared to 0 by hardware when reading the uf0bon register (fifo) connected to the cpu side has been completed (counter value = 0). it is not set to 1 when null data is received (toggling the fifo does not take place either). 1: data is in the register. 0: no data is in the register (default value). 3, 2 bkinn these bits indicate that data is in the uf0bin register (fifo) connected to the cpu side. by setting the bkinded bit of the uf0dend register to 1, the status in which data is in the uf0bin register can be created even if data is not written to the register (null data transmission). as soon as the bkinded bit of the uf0dend register has been set to 1 while the counter of the uf0bin register is 0, th is bit is set to 1 by hardware. it is cleared to 0 when a toggle operation is performed. 1: data is in the register. 0: no data is in the register (default value). remark n = 1, 2 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 583 (2/2) bit position bit name function 1 ep0w this bit indicates that data is in the uf0e 0w register (fifo). by setting the e0ded bit of the uf0dend register to 1, the status in which data is in the uf0e0w register can be created even if data is not written to the regi ster (null data transmission). as soon as the e0ded bit of the uf0dend register is set to 1 even when the counter of the uf0e0w register is 0, this bit is set to 1 by hardwar e. it is cleared to 0 after correct transmission. 1: data is in the register. 0: no data is in the register (default value). 0 ep0r this bit indicates that data is in the uf0e 0r register (fifo). it is automatically cleared to 0 by hardware when reading the uf0e0r register (fifo) has been completed (counter value = 0). it is not set to 1 if null data is received. 1: data is in the register. 0: no data is in the register (default value). chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 584 (9) uf0 ep status 1 register (uf0eps1) this register indicates the usb bus status a nd the presence or absence of register data. this register is read-only, in 8-bit units. rsum uf0eps1 0 5 00 3 0 2 0 1 00 address fffffe08h after reset 00h 0 4 6 7 bit position bit name function 7 rsum this bit indicates that the usb bus is in the resume status. this bit is meaningful only when an interrupt request is generated. 1: suspend status 0: resume status (default value) because sampling is internally performed with the clock, the operation is guaranteed only when clk is supplied. care must be exer cised when clk of the system is stopped. the intrsum signal of sie operates even w hen clk is stopped. it can therefore be supported by making the interrupt control r egister (rsumic) valid or lowering the frequency of clk to the usbf. this bit is automatically cl eared to 0 when it is read. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 585 (10) uf0 ep status 2 register (uf0eps2) this register indicates the usb bus status a nd the presence or absence of register data. this register is read-only, in 8-bit units. the related bits are invalid if each endpoint is not supporte d by the setting of the uf0enim register (n = 1 to 4, 7, 8) and the current setting of the interface. 0 uf0eps2 halt8 5 halt7 halt4 3 halt3 2 halt2 1 halt1 halt0 address fffffe09h after reset 00h 0 4 6 7 bit position bit name function 6 to 0 haltn these bits indicate that endpoint n is currently stalled. they are set to 1 when a stall condition, such as occurrence of an over run and reception of an undefined request, is satisfied. these bits are automatically set to 1 by hardware. 1: endpoint is stalled. 0: endpoint is not stalled (default value). the sndstl bit is set to 1 as soon as the halt0 bit has been set to 1 as a result of occurrence of an overrun or reception of an undefined request. if the next setup token is received in this status, the sndstl bit is cleared to 0 and, therefore, the halt0 bit is also cleared to 0. if endpoint0 is stalled by the set_feature endpoint0 request, this bit is not cleared to 0 until the clear_feat ure endpoint0 request is received or halt feature is cleared by fw. if the get_status endpoint0, clear_feature endpoint0, or set_feature endpoint0 request is received, or if a request to be processed by fw is received due to the cp udec interrupt request, the halt0 bit is masked and cleared to 0, until the next setup token is received. the haltn bit is not cleared to 0 until endpoint n receives the clear_feature endpoint request, halt feature is cleared by the set_interface or set_configuration request to the interface to which the endpoint is linked, or halt feature is cleared by fw. when the set_interface or set_configuration request is correctly processed, the halt f eature of all the target endpoints, except endpoint0, is cleared after the request has been processed, even if the wvalue is the same as the currently set value, and these bits are also cleared to 0. halt feature of endpoint0 cannot be cleared if it is set because the stall response is made in response to the set_interface and set_configuration requests. remark n = 0 to 4, 7, 8 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 586 (11) uf0 int status 0 register (uf0is0) this register indicates the interrupt source. if the cont ents of this register are changed, the intusb0b signal becomes active. this register is read-only, in 8-bit units. if an interrupt request (intusb0b) is generated from us bf, the fw must read this register to identify the interrupt source. each bit of this register is forcibly cleared to 0 wh en 0 is written to the corresponding bit of the uf0ic0 register. (1/2) uf0is0 rsuspd 5 0 3 dmaed 2 setrq 1 clrrq address fffffe10h after reset 00h 0 ephalt 4 short 6 7 busrst bit position bit name function 7 busrst this bit indicates that bus reset has occurred. 1: bus reset has occurred (interrupt request is generated). 0: not bus reset status (default value) 6 rsuspd this bit indicates that the resume or suspend status has occurred. reference bit 7 of the uf0eps1 register by fw. 1: resume or suspend status has occurred (interrupt request is generated). 0: resume or suspend status has not occurred (default value). 4 short this bit indicates that data is read fr om the fifo of either the uf0bo1 or uf0bo2 register and that the usbspnb signal (n = 2, 4) is active. it is valid only when the fifo is full in the dma mode. 1: usbspnb signal is active (interrupt request is generated). 0: usbspnb signal is not active (default value). identify on which endpoint the operation is performed, by using the uf0dms1 register. this bit is not automatically cleared to 0 even when the uf0dms1 register is read by fw. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 587 (2/2) bit position bit name function 3 dmaed this bit indicates that the dma end (tc) si gnal for endpoint n (n = 1 to 4, 7, 8) is active. 1: dma end signal for endpoint n has been i nput (interrupt request is generated). 0: dma end signal for endpoint n ha s not been input (default value). when this bit is set to 1, the dma request signal for endpoint n becomes inactive. the dma request signal for endpoint n does no t become active unless fw enables dma transfer. use the uf0dms0 register to confirm on which endpoint the operation is actually performed. however, this bit is not autom atically cleared to 0 even if the uf0dms0 register is read by fw. 2 setrq this bit indicates that the set_xxxx request to be automatically processed has been received and automatically processed (xxxx = configuration or feature). 1: set_xxxx request to be automatically processed has been received (interrupt request is generated). 0: set_xxxx request to be automatically processed has not been received (default value). this bit is set to 1 after completion of the status stage. reference the uf0set register to identify what is the target of the request. this bit is not automatically cleared to 0 even if the uf0set register is read by fw. the ephalt bit is also set to 1 when the set_feature endpoint request has been received. 1 clrrq this bit indicates that the clear_feature request has been received and automatically processed. 1: clear_feature request has been received (interrupt request is generated). 0: clear_feature request has not been received (default value). this bit is set to 1 after completion of the status stage. reference the uf0clr register to identify what is the target of the request. this bit is not automatically cleared to 0 even if the uf0clr register is read by fw. 0 ephalt this bit indicates that an endpoint has stalled. 1: endpoint has stalled (interrupt request is generated). 0: endpoint has not stalled (default value). this bit is also set to 1 when an endpoint has stalled by setting fw. identify the endpoint that has stalled, by referencing the uf0eps2 register. this bit is not automatically cleared to 0 even when the clear_feature endpoint, set_interface, or set_configuration request is received. it is not automatically cleared to 0, either, if the next setup token is received in case of overrun of endpoint0. caution even if halt feature of endpoint0 is set and this interrupt request is generated, bit 0 of the uf0eps2 register is masked and cleared to 0 between when a set_feature endpoint0, clear_feature endpoint0, or get_status endpoint0 request, or fw-processed request is received and when a setup token other than the above is received. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 588 (12) uf0 int status 1 register (uf0is1) this register indicates the interrupt source. if the cont ents of this register are changed, the intusb0b signal becomes active. this register is read-only, in 8-bit units. if an interrupt request (intusb0b) is generated from us bf, the fw must read this register to identify the interrupt source. each bit of this register is forcibly cleared to 0 wh en 0 is written to the corresponding bit of the uf0ic1 register. however, the suces and stg bits of the uf0is1 register are automatically cleared to 0 when the next setup token has been received. (1/2) uf0is1 cpu dec 5 e0indt 3 suces 2 stg 1 prot address fffffe11h after reset 00h 0 4 e0odt 6 e0in 7 0 bit position bit name function 6 e0in this bit indicates that an in token for endpoint0 has been received and that the hardware has automatically transmitted nak. 1: in token is received and nak is trans mitted (interrupt request is generated). 0: in token is not received (default value). 5 e0indt this bit indicates that data has been co rrectly transmitted from the uf0e0w register. 1: transmission from uf0e0w register is completed (interrupt request is generated). 0: transmission from uf0e0w register is not completed (default value). data is transmitted in synchronization with the in token next to the one that set the ep0nkw bit of the uf0e0n register to 1. this bit is automatically set to 1 by hardware when the host correctly receives that data. it is also set to 1 even if the data is a null packet. this bit is automatically cleared to 0 by hardware when the first write access is made to the uf0e0w register. 4 e0odt this bit indicates that data has been correctly received in the uf0e0r register. 1: data is in uf0e0r register (interrupt request is generated). 0: data is not in uf0e0r register (default value). this bit is automatically set to 1 by hardw are when data has been correctly received. at the same time, bit 0 of the uf0eps0 register is also set to 1. if a null packet has been received, this bit is not set to 1. it is automatically cleared to 0 by hardware when the fw reads the uf0e0r register and the va lue of the uf0e0l register becomes 0. 3 suces this bit indicates that either an fw -processed or hardware-processed request has been received and that the status stage has been correctly completed. 1: control transfer has been correctly processed (interrupt request is generated). 0: control transfer has not been processed correctly (default value). this bit is set to 1 upon completion of the status stage. it is automatically cleared to 0 by hardware when the next setup token is received. this bit is also set to 1 when data with data pid of 0 (null data) is received in the status stage of control transfer. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 589 (2/2) bit position bit name function 2 stg this bit is set to 1 when the stage of control transfer has changed to the status stage. it is valid for both fw-processed and hardware-proc essed requests. this bit is also set to 1 when the stage of control transfer (without data) has changed to the status stage. 1: status stage (interrupt request is generated) 0: not status stage (default value) this bit is automatically cleared to 0 by hardware when the next setup token is received. it is also set to 1 when the stage of control transfer has changed to the status stage while ack cannot be correctly received in the data stage. in this case, the ep0nkw bit of the uf0e0n register is also cleared to 0 as soon as the uf0e0w register has been cleared, if the fw is proc essing control transfer (read). 1 prot this bit indicates that a setup token has been received. it is valid for both fw- processed and hardware-processed requests. 1: setup token is correctly received (interrupt request is generated). 0: setup token is not received (default value). this bit is set to 1 when data has been correctly received in the uf0e0st register. clear this bit to 0 by fw when the first re ad access is made to the uf0e0st register. if it is not cleared to 0 by fw, reception of the next setup token cannot be correctly recognized. this bit is used to accurately recognize that a setup transaction has been executed again during control transfer. if the setup transaction is re-executed during control transfer and if a second request is executed by hardware, the cpudec bit is not set to 1, but the prot bit can be used for recognition of the re-execution. 0 cpudec this bit indicates that the uf0e0st regi ster has a request that is to be decoded by fw. 1: data is in uf0e0st register (interrupt request is generated). 0: data is not in uf0e0st register (default value). this bit is automatically cleared to 0 by hardware when all the data of the uf0e0st register is read. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 590 (13) uf0 int status 2 register (uf0is2) this register indicates the interrupt source. if the cont ents of this register are changed, the intusb1b signal becomes active. this register is read-only, in 8-bit units. if an interrupt request (intusb1b) is generated from us bf, the fw must read this register to identify the interrupt source. each bit of this register is forcibly cleared to 0 wh en 0 is written to the corresponding bit of the uf0ic2 register. the related bits are invalid if each en dpoint is not supported by the setting of the uf0enim register (n = 1, 3, 7, 8) and the current setting of the interface. bki2in uf0is2 bki2dt 5 bki1in bki1dt 3 0 2 0 1 it2dt it1dt address fffffe12h after reset 00h 0 4 6 7 bit position bit name function 7, 5 bkinin these bits indicate that an in token has been received in the uf0bin register (endpoint m) and that nak has been returned. 1: in token is received and nak is trans mitted (interrupt request is generated). 0: in token is not received (default value). 6, 4 bkindt these bits indicate that the fifo of the uf0bin register (endpoint m) has been toggled. this means that data can be written to endpoint m. 1: fifo has been toggled (interrupt request is generated). 0: fifo has not been toggled (default value). the data written to endpoint m is transmitted in synchronization with the in token next to the one that set the bkinnk bit of the uf0en register to 1. when the fifo has been toggled and then data can be written from the cpu, this bit is automatically set to 1 by hardware. it is also set to 1 when the fifo has been toggled, even if the data is a null packet. this bit is automatically cleared to 0 by hardware when the first write access is made to the uf0bin register. 1, 0 itndt these bits indicate that data has been correctly received from the uf0intn register (endpoint x). 1: transmission is completed (interrupt request is generated). 0: transmission is not completed (default value). data is transmitted in synchronization with the in token next to the one that set the itnnk bit of the uf0en register to 1. this bit is automatically set to 1 by hardware when the host has correctly received that data. it is automatically cleared to 0 by hardware when the first write access is made to the uf0int n register. this bit is also set to 1 even when the data is a null packet. remark n = 1, 2 m = 1 and x = 7 where n = 1 m = 3 and x = 8 where n = 2 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 591 (14) uf0 int status 3 register (uf0is3) this register indicates the interrupt source. if the cont ents of this register are changed, the intusb1b signal becomes active. this register is read-only, in 8-bit units. if an interrupt request (intusb1b) is generated from us bf, the fw must read this register to identify the interrupt source. each bit of this register is forcibly cleared to 0 wh en 0 is written to the corresponding bit of the uf0ic3 register. the related bits are invalid if each end point is not supported by the setting of the uf0enim regi ster (n = 2, 4) and the current setting of the interface. (1/2) uf0is3 bko1dt 5 bko2 nak 3 bko1fl 2 bko1nl 1 bko1 nak address fffffe13h after reset 00h 0 4 bko2dt 6 bko2nl 7 bko2fl bit position bit name function 7, 3 bkonfl these bits indicate that data ha s been correctly received in the uf0bon register (endpoint m) and that both the fifos of the cpu and sie hold the data. 1: received data is in both the fifos of the uf0bon register (interrupt request is generated). 0: received data is not in the fifo on the sie side of the uf0bon register (default value). if data is held in both the fifos of the cpu and sie, these bits are automatically set to 1 by hardware. they are automatically cleared to 0 by hardware when the fifo is toggled. 6, 2 bkonnl these bits indicate that a null packet (packet with a length of 0) has been received in the uf0bon register (endpoint m). 1: null packet is received (interrupt request is generated). 0: null packet is not received (default value). these bits are set to 1 immediately after reception of a null packet when the fifo is empty. they are set to 1 when the fifo on the cpu side has been completely read if data is in that fifo. 5, 1 bkonnak these bits indicate that an out token has been received to the uf0bon register (endpoint m) and that nak has been returned. 1: out token is received and nak is transmitted (interrupt request is generated). 0: out token is not received (default value). remark n = 1, 2 m = 2 where n = 1 m = 4 where n = 2 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 592 (2/2) bit position bit name function 4, 0 bkondt these bits indicate that data ha s been correctly received in the uf0bon register (endpoint m). 1: reception has been completed correctly (interrupt request is generated). 0: reception has not been completed (default value). these bits are automatically set to 1 by hardware when data has been correctly received and the fifo has been toggled. at the same time, the corresponding bits of the uf0eps0 register are also set to 1. they are not set to 1 when the data is a null packet. these bits are automatically cleared to 0 by hardware when the value of the uf0bonl register becomes 0 as a result of reading the uf0bon register by fw. these bits are automatically cleared to 0 when all the contents of the fifo on the cpu side have been read. however, the interrupt request is not cleared if data is in the fifo on the sie side at this time, and the intusb1 b signal does not become inactive. the signal is kept active if data is successively received. remark n = 1, 2 m = 2 where n = 1 m = 4 where n = 2 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 593 (15) uf0 int status 4 register (uf0is4) this register indicates the interrupt source. if the cont ents of this register are changed, the intusb2b signal becomes active. this register is read-only, in 8-bit units. if an interrupt request (intusb2b) is generated from us bf, the fw must read this register to identify the interrupt source. each bit of this register is forcibly cleared to 0 wh en 0 is written to the corresponding bit of the uf0ic4 register. the related bits are invalid if each endpoint is not supporte d by the setting of the uf0enim register (n = 1 to 4, 7, 8) and the current setting of the interface. 0 uf0is4 0 5 setint 0 3 0 2 0 1 00 address fffffe14h after reset 00h 0 4 6 7 bit position bit name function 5 setint this bit indicates that the set_interface request has been received and automatically processed. 1: the request has been automatically pr ocessed (interrupt request is generated). 0: the request has not been automat ically processed (default value). the current setting of this bit can be i dentified by reading the uf0ass or uf0ifn register (n = 0 to 4). chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 594 (16) uf0 int mask 0 register (uf0im0) this register controls masking of the interr upt sources indicated by the uf0is0 register. this register can be read or written in 8-bit units. fw can mask occurrence of an interrupt request from us bf (intusb0b) by writing 1 to the corresponding bit of this register. bus rstm uf0im0 rsu spdm 5 0 3 dma edm 2 set rqm 1 clr rqm ep haltm address fffffe17h after reset 00h 0 4 shortm 6 7 bit position bit name function 7 busrstm this bit masks the bus reset interrupt. 1: mask 0: do not mask (default value) 6 rsuspdm this bit masks the resume/suspend interrupt. 1: mask 0: do not mask (default value) 4 shortm this bit masks the short interrupt. 1: mask 0: do not mask (default value) 3 dmaedm this bit masks the dma_end interrupt. 1: mask 0: do not mask (default value) 2 setrqm this bit masks the set_rq interrupt. 1: mask 0: do not mask (default value) 1 clrrqm this bit masks the clr_rq interrupt. 1: mask 0: do not mask (default value) 0 ephaltm this bit masks the ep_halt interrupt. 1: mask 0: do not mask (default value) chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 595 (17) uf0 int mask 1 register (uf0im1) this register controls masking of the interr upt sources indicated by the uf0is1 register. this register can be read or written in 8-bit units. fw can mask occurrence of an interrupt request from us bf (intusb0b) by writing 1 to the corresponding bit of this register. uf0im1 5 e0 indtm 3 sucesm 2 stgm 1 protm cpu decm address fffffe18h after reset 00h 0 4 e0 odtm 6 e0inm 7 0 bit position bit name function 6 e0inm this bit masks the ep0in interrupt. 1: mask 0: do not mask (default value) 5 e0indtm this bit masks the ep0indt interrupt. 1: mask 0: do not mask (default value) 4 e0odtm this bit masks the ep0outdt interrupt. 1: mask 0: do not mask (default value) 3 sucesm this bit masks the success interrupt. 1: mask 0: do not mask (default value) 2 stgm this bit masks the stg interrupt. 1: mask 0: do not mask (default value) 1 protm this bit masks the protect interrupt. 1: mask 0: do not mask (default value) 0 cpudecm this bit masks the cpudec interrupt. 1: mask 0: do not mask (default value) chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 596 (18) uf0 int mask 2 register (uf0im2) this register controls masking of the interr upt sources indicated by the uf0is2 register. this register can be read or written in 8-bit units. fw can mask occurrence of an interrupt request from us bf (intusb1b) by writing 1 to the corresponding bit of this register. the related bits are invalid if each en dpoint is not supported by the setting of the uf0enim register (n = 1, 3, 7, 8) and the current setting of the interface. uf0im2 5 bki1inm 3 0 2 0 1 it2dtm address fffffe19h after reset 00h 0 it1dtm 4 bki1 dtm 6 bki2 dtm 7 bki2inm bit position bit name function 7, 5 bkininm these bits mask the blkinin interrupt. 1: mask 0: do not mask (default value) 6, 4 bkindtm these bits mask the blkindt interrupt. 1: mask 0: do not mask (default value) 1, 0 itndtm these bits mask the intndt interrupt. 1: mask 0: do not mask (default value) remark n = 1, 2 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 597 (19) uf0 int mask 3 register (uf0im3) this register controls masking of the interr upt sources indicated by the uf0is3 register. this register can be read or written in 8-bit units. fw can mask occurrence of an interrupt request from us bf (intusb1b) by writing 1 to the corresponding bit of this register. the related bits are invalid if each end point is not supported by the setting of the uf0enim regi ster (n = 2, 4) and the current setting of the interface. bko2 flm uf0im3 bko2 nlm 5 bko2 nakm 3 bko1 flm 2 bko1 nlm 1 bko1 nakm bko1 dtm address fffffe1ah after reset 00h 0 4 bko2 dtm 6 7 bit position bit name function 7, 3 bkonflm these bits mask the blkonfl interrupt. 1: mask 0: do not mask (default value) 6, 2 bkonnlm these bits mask the blkonnl interrupt. 1: mask 0: do not mask (default value) 5, 1 bkonnakm these bits mask the blkonnk interrupt. 1: mask 0: do not mask (default value) 4, 0 bkondtm these bits mask the blkondt interrupt. 1: mask 0: do not mask (default value) remark n = 1, 2 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 598 (20) uf0 int mask 4 register (uf0im4) this register controls masking of the interr upt sources indicated by the uf0is4 register. this register can be read or written in 8-bit units. fw can mask occurrence of an interrupt request from us bf (intusb2b) by writing 1 to the corresponding bit of this register. the related bits are invalid if each endpoint is not supporte d by the setting of the uf0enim register (n = 1 to 4, 7, 8) and the current setting of the interface. 0 uf0im4 0 5 setintm 0 3 0 2 0 1 00 address fffffe1bh after reset 00h 0 4 6 7 bit position bit name function 5 setintm this bit masks the set_int interrupt. 1: mask 0: do not mask (default value) chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 599 (21) uf0 int clear 0 register (uf0ic0) this register controls clearing the interrup t sources indicated by the uf0is0 register. this register is write-only, in 8-bit units. if this register is read, the value ffh is read. fw can clear an interrupt source by writing 0 to the co rresponding bit of this register. even a bit that is automatically cleared to 0 by hardware can be cleared by fw before it is cleared by hardware. writing 0 to a bit of this register automatically sets the bit to 1. writing 1 is invalid. bus rstc uf0ic0 rsu spdc 5 1 3 dma edc 2 set rqc 1 clr rqc ep haltc address fffffe1eh after reset ffh 0 4 shortc 6 7 bit position bit name function 7 busrstc this bit clears the bus reset interrupt. 0: clear 6 rsuspdc this bit clears the resume/suspend interrupt. 0: clear 4 shortc this bit clears the short interrupt. 0: clear 3 dmaedc this bit clears the dma_end interrupt. 0: clear 2 setrqc this bit clears the set_rq interrupt. 0: clear 1 clrrqc this bit clears the clr_rq interrupt. 0: clear 0 ephaltc this bit clears the ep_halt interrupt. 0: clear chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 600 (22) uf0 int clear 1 register (uf0ic1) this register controls clearing the interrup t sources indicated by the uf0is1 register. this register is write-only, in 8-bit units. if this register is read, the value ffh is read. fw can clear an interrupt source by writing 0 to the co rresponding bit of this register. even a bit that is automatically cleared to 0 by hardware can be cleared by fw before it is cleared by hardware. writing 0 to a bit of this register automatically sets the bit to 1. writing 1 is invalid. uf0ic1 5 e0 indtc 3 sucesc 2 stgc 1 protc cpu decc address fffffe1fh after reset ffh 0 4 e0odtc 6 e0inc 7 1 bit position bit name function 6 e0inc this bit clears the ep0in interrupt. 0: clear 5 e0indtc this bit clears the ep0indt interrupt. 0: clear 4 e0odtc this bit clears the ep0outdt interrupt. 0: clear 3 sucesc this bit clears the success interrupt. 0: clear 2 stgc this bit clears the stg interrupt. 0: clear 1 protc this bit clears the protect interrupt. 0: clear 0 cpudecc this bit clears the cpudec interrupt. 0: clear chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 601 (23) uf0 int clear 2 register (uf0ic2) this register controls clearing the interrup t sources indicated by the uf0is2 register. this register is write-only, in 8-bit units. if this register is read, the value ffh is read. fw can clear an interrupt source by writing 0 to the co rresponding bit of this register. even a bit that is automatically cleared to 0 by hardware can be cleared by fw before it is cleared by hardware. writing 0 to a bit of this register automatically sets the bit to 1. writing 1 is invalid. the related bits are invalid if each en dpoint is not supported by the setting of the uf0enim register (n = 1, 3, 7, 8) and the current setting of the interface. uf0ic2 5 bki1inc 3 1 2 1 1 it2dtc address fffffe20h after reset ffh 0 it1dtc 4 bki1 dtc 6 bki2 dtc 7 bki2inc bit position bit name function 7, 5 bkininc these bits clear the blkinin interrupt. 0: clear 6, 4 bkindtc these bits clear the blkindt interrupt. 0: clear 1, 0 itndtc these bits clear the intndt interrupt. 0: clear remark n = 1, 2 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 602 (24) uf0 int clear 3 register (uf0ic3) this register controls clearing the interrup t sources indicated by the uf0is3 register. this register is write-only, in 8-bit units. if this register is read, the value ffh is read. fw can clear an interrupt source by writing 0 to the co rresponding bit of this register. even a bit that is automatically cleared to 0 by hardware can be cleared by fw before it is cleared by hardware. writing 0 to a bit of this register automatically sets the bit to 1. writing 1 is invalid. the related bits are invalid if each end point is not supported by the setting of the uf0enim regi ster (n = 2, 4) and the current setting of the interface. bko2 flc uf0ic3 bko2 nlc 5 bko2 nakc bko2 dtc 3 bko1 flc 2 bko1 nlc 1 bko1 nakc bko1 dtc address fffffe21h after reset ffh 0 4 6 7 bit position bit name function 7, 3 bkonflc these bits clear the blkonfl interrupt. 0: clear 6, 2 bkonnlc these bits clear the blkonnl interrupt. 0: clear 5, 1 bkonnakc these bits clear the blkonnk interrupt. 0: clear 4, 0 bkondtc these bits clear the blkondt interrupt. 0: clear remark n = 1, 2 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 603 (25) uf0 int clear 4 register (uf0ic4) this register controls clearing the interrup t sources indicated by the uf0is4 register. this register is write-only, in 8-bit units. if this register is read, the value ffh is read. fw can clear an interrupt source by writing 0 to the co rresponding bit of this register. even a bit that is automatically cleared to 0 by hardware can be cleared by fw before it is cleared by hardware. writing 0 to a bit of this register automatically sets the bit to 1. writing 1 is invalid. the related bits are invalid if each endpoint is not supporte d by the setting of the uf0enim register (n = 1 to 4, 7, 8) and the current setting of the interface. 1 uf0ic4 1 5 setintc 1 3 1 2 1 1 11 address fffffe22h after reset ffh 0 4 6 7 bit position bit name function 5 setintc this bit clears the set_int interrupt. 0: clear chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 604 (26) uf0 int & dmarq register (uf0idr) this register selects reporting via an interrupt request or starting dma. this register can be read or written in 8-bit units. if data exists in either the uf0bo1 or uf0bo1 register , or if data can be written to the uf0bi1 or uf0bi2 register, this register selects whether it is reported to the fw by an interrupt request, or whether starting dma is requested. if starting dma is requested, the dma tr ansfer mode can be selected according to the setting of bits 0 and 1. the related bits are invalid if each endpoint is not suppor ted by the setting of the uf0enim register (n = 1 to 4) and the current setting of the interface. be sure to clear bits 3 and 2 to 0. if they are set to 1, the operation is not guaranteed. caution if the target endpoint is not supported by the set_interface request under dma transfer, the dma request signal becomes inactive im mediately, and the corresponding bit is automatically cleared to 0 by hardware. (1/2) dqbi2 ms uf0idr dqbi1 ms 5 dqbo2 ms dqbo1 ms 3 0 2 0 1 mode1 address fffffe26h after reset 00h 0 mode0 4 6 7 bit position bit name function 7, 6 dqbinms these bits enable (mask) a write dma transfer request (dma request signal for endpoint m) to the uf0bin register. when these bi ts are set to 1, the dma request signal for endpoint m becomes active while writing data can be acknowledged. if the dma end signal for endpoint m is input (if the dma controller issues tc), these bits are automatically cleared to 0 by hardware. to c ontinue dma transfer, re-set these bits to 1 by fw. 1: enables active dma request signal for endpoint m (masks bkindt interrupt). 0: disables active dma request signal for endpoint m (default value). 5, 4 dqbonms these bits enable (mask) a read dma transfer request (dma request signal for endpoint x) to the uf0bon register. when these bi ts are set to 1, the dma request signal for endpoint x becomes active if the data to be read is prepared in the uf0bon register. if the dma end signal for endpoint x is input (if the dma controller issues tc), these bits are automatically cleared to 0 by hardware. they are also cleared to 0 when the usbspxb signal is active. to continue dma transfer, re-set these bits to 1 by fw. 1: enables active dma request signal for endpoint x (masks bkondt interrupt). 0: disables active dma request signal for endpoint x (default value). remark n = 1, 2 m = 1 and x = 2 where n = 1 m = 3 and x = 4 where n = 2 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 605 (2/2) bit position bit name function these bits select the dma transfer mode. mode1 mode2 mode remark 1 1 setting prohibited operation cannot be guaranteed. 1 0 demand mode dma request signal becomes active as long as there is data. it becomes inactive if there is no more data. 0 x single mode dma request signal becomes inactive each time dma transfer has been executed. 1, 0 mode1, mode0 remark x: don?t care chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 606 (27) uf0 dma status 0 register (uf0dms0) this register indicates the dma st atus of endpoint1 to endpoint4. this register is read-only, in 8-bit units. the related bits are invalid if each endpoint is not suppor ted by the setting of the uf0enim register (n = 1 to 4) and the current setting of the interface. 0 uf0dms0 0 5 dqe4 dqe3 3 dqe2 2 dqe1 1 00 address fffffe27h after reset 00h 0 4 6 7 bit position bit name function 5 dqe4 this bit indicates that a dma read r equest is being issued from endpoint4 to memory. 1: dma read request from endpoint4 is being issued. 0: dma read request from endpoint4 is not being issued (default value). 4 dqe3 this bit indicates that a dma write reque st is being issued from memory to endpoint3. note that, even if data is in endpoint3 (when the fifo is not full and after the bki2ded bit has been set to 1), the dma request si gnal becomes active immediately and dma transfer is started when the dqbi2ms bit of the uf0idr register is set to 1. 1: dma write request for endpoint3 is being issued. 0: dma write request for endpoint3 is not being issued (default value). 3 dqe2 this bit indicates that a dma read r equest is being issued from endpoint2 to memory. 1: dma read request from endpoint2 is being issued. 0: dma read request from endpoint2 is not being issued (default value). 2 dqe1 this bit indicates that a dma write reque st is being issued from memory to endpoint1. note that, even if data is in endpoint1 (when the fifo is not full and after the bki1ded bit has been set to 1), the dma request si gnal becomes active immediately and dma transfer is started when the dqbi1ms bit of the uf0idr register is set to 1. 1: dma write request for endpoint1 is being issued. 0: dma write request for endpoint1 is not being issued (default value). chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 607 (28) uf0 dma status 1 register (uf0dms1) this register indicates the dma st atus of endpoint1 to endpoint4. this register is read-only, in 8-bit units. the related bits are invalid if each endpoint is not suppor ted by the setting of the uf0enim register (n = 1 to 4) and the current setting of the interface. each bit is automatically cleared to 0 when this register is read. even when this register is read, however, bits 4 and 3 of the uf0is0 register are not cleared to 0. if the target endpoint is no longer supported by the set_interface request, each bit is automatically cleared to 0 by hardware (however, the dma_end interrupt request and short interrupt request are not cleared). dede4 uf0dms1 dspe4 5 dede3 dede2 3 dspe2 2 dede1 1 00 address fffffe28h after reset 00h 0 4 6 7 bit position bit name function 7, 5, 4, 2 deden these bits indicate that the dma end (tc) signal for endpoint n becomes active and dma is stopped while a dma read request is being issued from endpoint n to memory. 1: dma end signal for endpoint n is active. 0: dma end signal for endpoint n is inactive (default value). 6, 3 dspem these bits indicate that, although a dma read request was being issued from endpoint m to memory, dma has been stopped because the received data is a short packet and there is no more data to be transferred. 1: usbspmb signal is active. 0: usbspmb signal is inactive (default value). remark n = 1 to 4 m = 2, 4 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 608 (29) uf0 fifo clear 0 register (uf0fic0) this register clears each fifo. this register is write-only, in 8-bit units . if this register is read, 00h is read. fw can clear the target fifo by writing 1 to the corresp onding bit of this register. the bit to which 1 has been written is automatically cleared to 0. writing 0 to the bit is invalid. the related bits are invalid if each en dpoint is not supported by the setting of the uf0enim register (n = 1, 3, 7, 8) and the current setting of the interface. bki2sc uf0fic0 bki2cc 5 bki1sc bki1cc 3 itr2c 2 itr1c 1 ep0wc ep0rc address fffffe30h after reset 00h 0 4 6 7 bit position bit name function 7, 5 bkinsc these bits clear only the fifo on the si e side of the uf0bin register (reset the counter). 1: clear writing these bits is invalid while an in tok en for endpoint m is being processed with the bkinnk bit set to 1. the bkinnk bit is automatically cleared to 0 by clearing the fifo. make sure that the fifo on the cpu side is empty when these bits are used. 6, 4 bkincc these bits clear only the fifo on t he cpu side of the uf0bin register (reset the counter). 1: clear 3, 2 itrnc these bits clear the uf 0intn register (reset the counter). 1: clear writing these bits is invalid while an in to ken for endpoint x is being processed with the itnnk bit set to 1. the itnnk bit is automatically cleared to 0 by clearing the fifo. 1 ep0wc this bit clears the uf0e0w register (resets the counter). 1: clear writing this bit is invalid while an in tok en for endpoint0 is being processed with the ep0nkw bit set to 1. the ep0nkw bit is automatically cleared to 0 by clearing the fifo. 0 ep0rc this bit clears the uf0e0r register (resets the counter). 1: clear when the ep0nkr bit is set to 1 (except when it has been set by fw), the ep0nkr bit is automatically cleared to 0 by clearing the fifo. remark n = 1, 2 m = 1 and x = 7 where n = 1 m = 3 and x = 8 where n = 2 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 609 (30) uf0 fifo clear 1 register (uf0fic1) this register clears each fifo. this register is write-only, in 8-bit units . if this register is read, 00h is read. fw can clear the target fifo by writing 1 to the corresp onding bit of this register. the bit to which 1 has been written is automatically cleared to 0. writing 0 to the bit is invalid. the related bits are invalid if each end point is not supported by the setting of the uf0enim regi ster (n = 2, 4) and the current setting of the interface. 0 uf0fic1 0 5 00 3 bko2c 2 bko2cc 1 bko1c bko1cc address fffffe31h after reset 00h 0 4 6 7 bit position bit name function 3, 1 bkonc these bits clear the fifos on both the sie and cpu sides of the uf0bon register (reset the counter). 1: clear when the bkonnk bit is set to 1 (except when it has been set by fw), the bkonnk bit is automatically cleared to 0 by clearing the fifo. 2, 0 bkoncc these bits clear only the fifo on the cpu side of the uf0bon register (reset the counter). 1: clear when the bkonnk bit is set to 1 (except when it has been set by fw), the bkonnk bit is automatically cleared to 0 by clearing the fifo. remark n = 1, 2 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 610 (31) uf0 data end register (uf0dend) this register reports the end of writing to the transmission system. this register is write-only, in 8-bit units (however, bits 7 and 6 can be read and written). if this register is read, 00h is read. fw can start data transfer of the target endpoint by writ ing 1 to the corresponding bit of this register. the bit to which 1 has been written is automatically clear ed to 0. writing 0 to the bit is invalid. the related bits are invalid if each en dpoint is not supported by the setting of the uf0enim register (n = 1, 3, 7, 8) and the current setting of the interface. (1/2) bki2t uf0dend bki1t 5 0 it2dend 3 it1dend 2 bki2ded 1 bki1ded e0ded address fffffe35h after reset 00h 0 4 6 7 bit position bit name function 7, 6 bkint these bits specify whether toggling the fifo is automatically executed if the fifo on the cpu side of the uf0bin register becomes full as a result of dma. 1: automatically execute a toggle operation of the fifo as soon as the fifo has become full. 0: do not automatically execute a toggle operation of the fifo even if the fifo becomes full (default value). 4, 3 itndend set these bits to 1 to transmit the dat a of the uf0intn register. when these bits are set to 1, the itnnk bit is set to 1 and data transfer is executed. 1: transmit a short packet. 0: do not transmit a short packet (default value). if the itrnc bit of the uf0fic0 register is set to 1 and then these bits are set to 1 (counter of uf0intn register = 0 and the corresponding bit of the uf0eps0 register = 1), a null packet (with a data length of 0) is transmitted. if data exists in the uf0intn register and if these bits are set to 1 (counter of uf0intn register 0 and the corresponding bit of the uf0eps0 register = 1), a short packet is transmitted. these bits are automatically controlled by hardware when the fifo is full. remark n = 1, 2 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 611 (2/2) bit position bit name function 2, 1 bkinded set these bits to 1 when writi ng transmit data to the uf0bin register has been completed. when these bits are set to 1, the fifo is toggled as soon as possible, the bkinnk bit is set to 1, and data is transferred. 1: transmit a short packet. 0: do not transmit a short packet (default value). these bits control the fifo on the cpu side. if the bkincc bit of the uf0fic0 register is set to 1 and then these bits are set to 1 (counter of uf0bin register = 0), a null packet (with a data length of 0) is transmitted. if data exists in the uf0bin register and if th ese bits are set to 1 (counter of uf0bin register 0), and if the fifo is not full, a short packet is transmitted. if the fifo on the cpu side of the uf0bin regi ster becomes full as a result of dma, with the pio or bkint bit set to 1, the hardware starts data transmission even if these bits are not set to 1. if the fifo on the cpu side of the uf0bin regi ster becomes full as a result of dma, with the bkint bit cleared to 0, be sure to set these bits to 1 (see 11.4.1 (3) uf0 epnak register (uf0en) ). 0 e0ded set this bit to 1 to transmit data of the uf 0e0w register. when this bit is set to 1, the ep0nkw bit is set to 1 and data is transferred. 1: transmit a short packet. 0: do not transmit a short packet (default value). if the ep0wc bit of the uf0fic0 register is set to 1 and if this bit is set to 1 (counter of uf0e0w register = 0 and bit 1 of uf0eps0 register = 1), a null packet (with a data length of 0) is transmitted. if data exists in the uf0e0w register and if this bit is set to 1 (counter of uf0e0w register 0 and bit 1 of the uf0eps0 register = 1), and if the fifo is not full, a short packet is transmitted. remark n = 1, 2 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 612 (32) uf0 gpr register (uf0gpr) this register controls usbf and the usb interface. this register is write-only, in 8-bit units. if this register is read, 00h is read. be sure to clear bits 7 to 1 to 0. fw can reset the usbf by writing 1 to bit 0 of this regi ster. this bit is automatically cleared to 0 after 1 has been written to it. writing 0 to this bit is invalid. 0 uf0gpr 0 5 00 3 0 2 0 1 0 mrst address fffffe37h after reset 00h 0 4 6 7 bit position bit name function 0 mrst set this bit to 1 to reset usbf. 1: reset actually, usbf is reset two usb clocks after this bit has been set to 1 by fw and the write signal has become inactive. while the system clock is operating, usbf is reset by this bit in the same manner as by the reset pin (hardware reset). chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 613 (33) uf0 mode control register (uf0modc) this register controls cpudec processing. this register can be read or written in 8-bit units. by setting each bit of this register, the setting of the uf0mods register can be changed. the bit of this register is automatically cleared to 0 only at hardwar e reset and when the mrst bit of the uf0grp register has been set to 1. even if the bit of this register has automatically been set to 1 by hardware, the setting by fw takes precedence. be sure to clear bits 7 and 5 to 2 to 0. if th ey are set to 1, the operation is not guaranteed. caution this register is provided for debugging pur poses. usually, do not set this register except for verifying the operation or when a special mode is used. uf0modc 5 0 3 0 2 0 1 0 address fffffe3ah after reset 00h 0 0 4 0 6 cdc gdst 7 0 bit position bit name function 6 cdcgdst set this bit to 1 to switch the get_descriptor configuration request to cpudec processing. by setting this bit to 1, the cdcgd bit of the uf0mods register can be forcibly set to 1. 1: forcibly change the get_descriptor configuration request to cpudec processing (sets the cdcgd bit of the uf0mods register to 1). 0: automatically process the get_des criptor configuration request (default value). chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 614 (34) uf0 mode status register (uf0mods) this register indicates the configuration status. this register is read-only, in 8-bit units. 0 uf0mods cdcgd 5 0mpack 3 dflt 2 conf 1 00 address fffffe3ch after reset 00h 0 4 6 7 bit position bit name function 6 cdcgd this bit specifies whether cpudec proc essing is performed for the get_descriptor configuration request. 1: forcibly change the get_descriptor configuration request to cpudec processing. 0: automatically process the get_des criptor configuration request (default value). 4 mpack this bit indicates the transmit packet size of endpoint0. 1: transmit a packet of other than 8 bytes. 0: transmit a packet of 8 bytes (default value). this bit is automatically set to 1 by hardware after the get_descriptor device request has been processed (on normal completion of the status stage). it is not cleared to 0 until the usbf has been reset (it is not cleared to 0 by bus reset). if this bit is not set to 1, the hardware transfers only the automatically-executed request in 8-byte units. therefore, even if data of more than 8 bytes is sent by the out token to be processed by fw before completion of the get_descriptor device request, the data is correctly received. this bit is ignored if the size of endpoint0 is 8 bytes. 3 dflt this bit indicates the default status (dflt bit = 1). 1: enables response. 0: disables response (always no response) (default value). this bit is automatically set to 1 by bus reset. the transaction for all the endpoints is not responded to until this bit is set to 1. 2 conf this bit indicates whether the set_configuration request has been completed. 1: set_configuration request has been completed. 0: set_configuration request has not been completed (default value). this bit is set to 1 when configuration value = 1 is received by the set_configuration request. unless this bit is set to 1, access to an endpoint other than endpoint0 is ignored. this bit is cleared to 0 when configuration value = 0 is received by the set_configuration request. it is also cleared to 0 when bus reset is detected. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 615 (35) uf0 active interface number register (uf0aifn) this register sets the valid interface number that co rrectly responds to the get/set_interface request. because interface 0 is always valid, interfaces 1 to 4 can be selected. this register can be read or written in 8-bit units. addif uf0aifn 0 5 00 3 0 2 0 1 ifno1 ifno0 address fffffe40h after reset 00h 0 4 6 7 bit position bit name function 7 addif this bit allows use of interfaces numbered other than 0. 1: support up to the interface number specified by the ifno1 and ifno0 bits. 0: support only interface 0 (default value). setting bits 1 and 0 of this register is invalid when this bit is not set to 1. these bits specify the range of in terface numbers to be supported. ifno1 ifno0 valid interface no. 1 1 0, 1, 2, 3, 4 1 0 0, 1, 2, 3 0 1 0, 1, 2 0 0 0, 1 1, 0 ifno1, ifno0 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 616 (36) uf0 active alternati ve setting register (uf0aas) this register specifies a link between the interface number and alternative setting. this register can be read or written in 8-bit units. usbf of the v850e/me2 can set a five-series alternat ive setting (alternate setting 0, 1, 2, 3, and 4 can be defined) and a two-series alternative setting (alter native setting 0 and 1 can be defined) for one interface. alt2 uf0aas ifal21 5 ifal20 alt2en 3 alt5 2 ifal51 1 ifal50 alt5en address fffffe41h after reset 00h 0 4 6 7 bit position bit name function 7, 3 altn these bits specify whether an n-series alternative setting is linked with interface 0. when these bits are set to 1, the setting of the ifaln1 and ifaln0 bits is invalid. 1: link n-series alternative setting with interface 0. 0: do not link n-series alternative se tting with interface 0 (default value). these bits specify the interface number to be lin ked with the n-series alternative setting. if the linked interface number is outside the range specified by the uf0aifn register, the n-series alternative setting is invalid (altnen bit = 0). ifaln1 ifaln0 interface number to be linked 1 1 links interface 4. 1 0 links interface 3. 0 1 links interface 2. 0 0 links interface 1. 6, 5, 2, 1 ifaln1, ifaln0 do not link a five-series alternative setting and a two-series alternative setting with the same interface number. 4, 0 altnen these bits validate the n-series alternat ive setting. unless these bits are set to 1, the setting of the altn, ifaln1, and ifaln0 bits is invalid. 1: validate the n-series alternative setting. 0: do not validate the n-series alternative setting (default value). remark n = 2, 5 for example, when the uf0aifn register is set to 82h an d the uf0aas register is set to 15h, interfaces 0, 1, 2, and 3 are valid. interfaces 0 and 2 support only alternative setting 0. interface 1 supports alternative setting 0 and 1, and interface 3 supports alternative setti ng 0, 1, 2, 3, and 4. with this setting, requests get_interface windex = 0/1/2/3, set_interface wvalue = 0 & windex = 0/2, set_interface wvalue = 0/1 & windex = 1, and set_interfa ce wvalue = 0/1/2/3/4 & windex = 3 are automatically responded to, and a stall response is made to the other get/set_interface requests. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 617 (37) uf0 alternative setting status register (uf0ass) this register indicates the current status of the alternative setting. this register is read-only, in 8-bit units. check this register when the set_int interrupt req uest has been issued. the value received by the set_interface request is reflected on the uf0ifn r egister (n = 0 to 4) as well as on this register. 0 uf0ass 0 5 00 3 al5st3 2 al5st2 1 al5st1 al2st address fffffe42h after reset 00h 0 4 6 7 bit position bit name function these bits indicate the current status of the five-series alternative setting. al5st3 al5st2 al5st1 selected alternative setting number 1 0 0 alternative setting 4 0 1 1 alternative setting 3 0 1 0 alternative setting 2 0 0 1 alternative setting 1 0 0 0 alternative setting 0 3 to 1 al5st3 to al5st1 0 al2st this bit indicates the current status of the two-series alternative setting (selected alternative setting number). 1: alternative setting 1 0: alternative setting 0 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 618 (38) uf0 endpoint 1 interface mapping register (uf0e1im) this register specifies for which interface and alternative setting endpoint1 is valid. this register can be read or written in 8-bit units. the setting of this register and the alternative setti ng selected by the set_interface request indicate whether endpoint1 is currently valid, and the hardware determines how the get_status/clear_feature/set_feature endpoint1 request and the in transaction to endpoint1 are responded to, and whether the related bits are valid or invalid. e1en2 uf0e1im e1en1 5 e1en0 e12al1 3 e15al4 2 e15al3 1 e15al2 e15al1 address fffffe43h after reset 00h 0 4 6 7 bit position bit name function these bits set a link between the interface of endpoint1 and the two-/five-series alternative setting. the endpoint is linked with alternative setting 0. the endpoint linked with alternative setting 0 cannot be excluded from alternative setting 1 to 4. e1en2 e1en1 e1en0 link status 1 1 1 1 1 0 not linked with interface 1 0 1 linked with interface 4 and alternative setting 0 1 0 0 linked with interface 3 and alternative setting 0 0 1 1 linked with interface 2 and alternative setting 0 0 1 0 linked with interface 1 and alternative setting 0 0 0 1 linked with interface 0 and alternative setting 0 0 0 0 not linked with interface (default value) 7 to 5 e1en2 to e1en0 when these bits are set to 110 or 111, they ar e invalid even if the e12al1 bit is cleared to 0. if the endpoint is linked, setting of the conf bi t of the uf0mods register to 1 indicates that endpoint1 is valid. 4 e12al1 this bit validates endpoint1 when the tw o-series alternative setting and the alternative setting of the linked interface are set to 1. 1: validate the endpoint when alternative setting 1 is set with conf bit = 1. 0: do not validate the endpoint even when alternative setting 1 is set with conf bit = 1 (default value). this bit is valid when the e15al4 to e15al1 bits are 0000. 3 to 0 e15aln these bits validate endpoint1 wh en the five-series alternative setting and the alternative setting of the linked interface are set to n. 1: validate the endpoint when alternative setting n is set with conf bit = 1. 0: do not validate the endpoint even when alternative setting n is set with conf bit = 1 (default value). remark n = 1 to 4 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 619 (39) uf0 endpoint 2 interface mapping register (uf0e2im) this register specifies for which interface and alternative setting endpoint2 is valid. this register can be read or written in 8-bit units. the setting of this register and the alternative setti ng selected by the set_interface request indicate whether endpoint2 is currently valid, and the hardware determines how the get_status/clear_feature/set_feature endpoint 2 request and the out transaction to endpoint2 are responded to, and whether the related bits are valid or invalid. e2en2 uf0e2im e2en1 5 e2en0 e22al1 3 e25al4 2 e25al3 1 e25al2 e25al1 address fffffe44h after reset 00h 0 4 6 7 bit position bit name function these bits set a link between the interface of endpoint2 and the two-/five-series alternative setting. the endpoint is linked with alternative setting 0. the endpoint linked with alternative setting 0 cannot be excluded from alternative setting 1 to 4. e2en2 e2en1 e2en0 link status 1 1 1 1 1 0 not linked with interface 1 0 1 linked with interface 4 and alternative setting 0 1 0 0 linked with interface 3 and alternative setting 0 0 1 1 linked with interface 2 and alternative setting 0 0 1 0 linked with interface 1 and alternative setting 0 0 0 1 linked with interface 0 and alternative setting 0 0 0 0 not linked with interface (default value) 7 to 5 e2en2 to e2en0 when these bits are set to 110 or 111, they ar e invalid even if the e22al1 bit is cleared to 0. if the endpoint is linked, setting of the conf bi t of the uf0mods register to 1 indicates that endpoint2 is valid. 4 e22al1 this bit validates endpoint2 when the tw o-series alternative setting and the alternative setting of the linked interface are set to 1. 1: validate the endpoint when alternative setting 1 is set with conf bit = 1. 0: do not validate the endpoint even when alternative setting 1 is set with conf bit = 1 (default value). this bit is valid when the e25al4 to e25al1 bits are 0000. 3 to 0 e25aln these bits validate endpoint2 wh en the five-series alternative setting and the alternative setting of the linked interface are set to n. 1: validate the endpoint when alternative setting n is set with conf bit = 1. 0: do not validate the endpoint even when alternative setting n is set with conf bit = 1 (default value). remark n = 1 to 4 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 620 (40) uf0 endpoint 3 interface mapping register (uf0e3im) this register specifies for which interface and alternative setting endpoint3 is valid. this register can be read or written in 8-bit units. the setting of this register and the alternative setti ng selected by the set_interface request indicate whether endpoint3 is currently valid, and the hardware determines how the get_status/clear_feature/set_feature endpoint3 request and the in transaction to endpoint3 are responded to, and whether the related bits are valid or invalid. e3en2 uf0e3im e3en1 5 e3en0 e32al1 3 e35al4 2 e35al3 1 e35al2 e35al1 address fffffe45h after reset 00h 0 4 6 7 bit position bit name function these bits set a link between the interface of endpoint3 and the two-/five-series alternative setting. the endpoint is linked with alternative setting 0. the endpoint linked with alternative setting 0 cannot be excluded from alternative setting 1 to 4. e3en2 e3en1 e3en0 link status 1 1 1 1 1 0 not linked with interface 1 0 1 linked with interface 4 and alternative setting 0 1 0 0 linked with interface 3 and alternative setting 0 0 1 1 linked with interface 2 and alternative setting 0 0 1 0 linked with interface 1 and alternative setting 0 0 0 1 linked with interface 0 and alternative setting 0 0 0 0 not linked with interface (default value) 7 to 5 e3en2 to e3en0 when these bits are set to 110 or 111, they ar e invalid even if the e32al1 bit is cleared to 0. if the endpoint is linked, setting of the conf bi t of the uf0mods register to 1 indicates that endpoint3 is valid. 4 e32al1 this bit validates endpoint3 when the tw o-series alternative setting and the alternative setting of the linked interface are set to 1. 1: validate the endpoint when alternative setting 1 is set with conf bit = 1. 0: do not validate the endpoint even when alternative setting 1 is set with conf bit = 1 (default value). this bit is valid when the e35al4 to e35al1 bits are 0000. 3 to 0 e35aln these bits validate endpoint3 wh en the five-series alternative setting and the alternative setting of the linked interface are set to n. 1: validate the endpoint when alternative setting n is set with conf bit = 1. 0: do not validate the endpoint even when alternative setting n is set with conf bit = 1 (default value). remark n = 1 to 4 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 621 (41) uf0 endpoint 4 interface mapping register (uf0e4im) this register specifies for which interface and alternative setting endpoint4 is valid. this register can be read or written in 8-bit units. the setting of this register and the alternative setti ng selected by the set_interface request indicate whether endpoint4 is currently valid, and the hardware determines how the get_status/clear_feature/set_feature endpoint 4 request and the out transaction to endpoint4 are responded to, and whether the related bits are valid or invalid. e4en2 uf0e4im e4en1 5 e4en0 e42al1 3 e45al4 2 e45al3 1 e45al2 e45al1 address fffffe46h after reset 00h 0 4 6 7 bit position bit name function these bits set a link between the interface of endpoint4 and the two-/five-series alternative setting. the endpoint is linked with alternative setting 0. the endpoint linked with alternative setting 0 cannot be excluded from alternative setting 1 to 4. e4en2 e4en1 e4en0 link status 1 1 1 1 1 0 not linked with interface 1 0 1 linked with interface 4 and alternative setting 0 1 0 0 linked with interface 3 and alternative setting 0 0 1 1 linked with interface 2 and alternative setting 0 0 1 0 linked with interface 1 and alternative setting 0 0 0 1 linked with interface 0 and alternative setting 0 0 0 0 not linked with interface (default value) 7 to 5 e4en2 to e4en0 when these bits are set to 110 or 111, they ar e invalid even if the e42al1 bit is cleared to 0. if the endpoint is linked, setting of the conf bi t of the uf0mods register to 1 indicates that endpoint4 is valid. 4 e42al1 this bit validates endpoint4 when the tw o-series alternative setting and the alternative setting of the linked interface are set to 1. 1: validate the endpoint when alternative setting 1 is set with conf bit = 1. 0: do not validate the endpoint even when alternative setting 1 is set with conf bit = 1 (default value). this bit is valid when the e45al4 to e45al1 bits are 0000. 3 to 0 e45aln these bits validate endpoint4 wh en the five-series alternative setting and the alternative setting of the linked interface are set to n. 1: validate the endpoint when alternative setting n is set with conf bit = 1. 0: do not validate the endpoint even when alternative setting n is set with conf bit = 1 (default value). remark n = 1 to 4 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 622 (42) uf0 endpoint 7 interface mapping register (uf0e7im) this register specifies for which interface and alternative setting endpoint7 is valid. this register can be read or written in 8-bit units. the setting of this register and the alternative setti ng selected by the set_interface request indicate whether endpoint7 is currently valid, and the hardware determines how the get_status/clear_feature/set_feature endpoint7 request and the in transaction to endpoint7 are responded to, and whether the related bits are valid or invalid. e7en2 uf0e7im e7en1 5 e7en0 e72al1 3 e75al4 2 e75al3 1 e75al2 e75al1 address fffffe49h after reset 00h 0 4 6 7 bit position bit name function these bits set a link between the interface of endpoint7 and the two-/five-series alternative setting. the endpoint is linked with alternative setting 0. the endpoint linked with alternative setting 0 cannot be excluded from alternative setting 1 to 4. e7en2 e7en1 e7en0 link status 1 1 1 1 1 0 not linked with interface 1 0 1 linked with interface 4 and alternative setting 0 1 0 0 linked with interface 3 and alternative setting 0 0 1 1 linked with interface 2 and alternative setting 0 0 1 0 linked with interface 1 and alternative setting 0 0 0 1 linked with interface 0 and alternative setting 0 0 0 0 not linked with interface (default value) 7 to 5 e7en2 to e7en0 when these bits are set to 110 or 111, they ar e invalid even if the e72al1 bit is cleared to 0. if the endpoint is linked, setting of the conf bi t of the uf0mods register to 1 indicates that endpoint7 is valid. 4 e72al1 this bit validates endpoint7 when the tw o-series alternative setting and the alternative setting of the linked interface are set to 1. 1: validate the endpoint when alternative setting 1 is set with conf bit = 1. 0: do not validate the endpoint even when alternative setting 1 is set with conf bit = 1 (default value). this bit is valid when the e75al4 to e75al1 bits are 0000. 3 to 0 e75aln these bits validate endpoint7 wh en the five-series alternative setting and the alternative setting of the linked interface are set to n. 1: validate the endpoint when alternative setting n is set with conf bit = 1. 0: do not validate the endpoint even when alternative setting n is set with conf bit = 1 (default value). remark n = 1 to 4 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 623 (43) uf0 endpoint 8 interface mapping register (uf0e8im) this register specifies for which interface and alternative setting endpoint8 is valid. this register can be read or written in 8-bit units. the setting of this register and the alternative setti ng selected by the set_interface request indicate whether endpoint8 is currently valid, and the hardware determines how the get_status/clear_feature/set_feature endpoint8 request and the in transaction to endpoint8 are responded to, and whether the related bits are valid or invalid. e8en2 uf0e8im e8en1 5 e8en0 e82al1 3 e85al4 2 e85al3 1 e85al2 e85al1 address fffffe4ah after reset 00h 0 4 6 7 bit position bit name function these bits set a link between the interface of endpoint8 and the two-/five-series alternative setting. the endpoint is linked with alternative setting 0. the endpoint linked with alternative setting 0 cannot be excluded from alternative setting 1 to 4. e8en2 e8en1 e8en0 link status 1 1 1 1 1 0 not linked with interface 1 0 1 linked with interface 4 and alternative setting 0 1 0 0 linked with interface 3 and alternative setting 0 0 1 1 linked with interface 2 and alternative setting 0 0 1 0 linked with interface 1 and alternative setting 0 0 0 1 linked with interface 0 and alternative setting 0 0 0 0 not linked with interface (default value) 7 to 5 e8en2 to e8en0 when these bits are set to 110 or 111, they ar e invalid even if the e82al1 bit is cleared to 0. if the endpoint is linked, setting of the conf bi t of the uf0mods register to 1 indicates that endpoint8 is valid. 4 e82al1 this bit validates endpoint8 when the tw o-series alternative setting and the alternative setting of the linked interface are set to 1. 1: validate the endpoint when alternative setting 1 is set with conf bit = 1. 0: do not validate the endpoint even when alternative setting 1 is set with conf bit = 1 (default value). this bit is valid when the e85al4 to e85al1 bits are 0000. 3 to 0 e85aln these bits validate endpoint8 wh en the five-series alternative setting and the alternative setting of the linked interface are set to n. 1: validate the endpoint when alternative setting n is set with conf bit = 1. 0: do not validate the endpoint even when alternative setting n is set with conf bit = 1 (default value). remark n = 1 to 4 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 624 11.4.2 data hold registers (1) uf0 ep0 read register (uf0e0r) the uf0e0r register is a 64-byte fifo that stores the out data sent from the host in the data stage of control transfer to/from endpoint0. this register is read-only, in 8-bit units. a write access to this register is ignored. the hardware automatically trans fers data to the uf0e0r register when it has received the data from the host. when the data has been correctly received, the e0odt bit of the uf0is1 register is set to 1. the uf0e0l register holds the quantity of the received data, and an interrupt request (intusb0b) is issued. the uf0e0l register always updates the length of t he received data while it is receiving data. if the final transfer is correct reception, the interrupt request is gen erated. if the reception is abnormal, the uf0e0l register is cleared to 0 and the interrupt request is not generated. the data held by the uf0e0r register must be read by fw up to the value of the amount of data read by the uf0e0l register. check that all data has been read by using the ep0r bit of the uf0eps0 register (ep0r = 0 when all data has been read). if the val ue of the uf0e0l register is 0, the ep0nkr bit of the uf0e0n register is cleared to 0, and the uf0e0r register is ready for rec eption. the uf0e0r register is cleared when the next setup token has been received. caution read all the data stored. clear the fifo to discard some data. e0r7 uf0e0r e0r6 5 e0r5 e0r4 3 e0r3 2 e0r2 1 e0r1 e0r0 address fffffe80h after reset undefined 0 4 6 7 bit position bit name function 7 to 0 e0r7 to e0r0 these bits store the out data sent from the host in the data stage of control transfer to/from endpoint0. the operation of the uf0e0r r egister is illustrated below. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 625 figure 11-1. operation of uf0e0r register status of uf0e0r register normal completion of reception normal completion of reception abnormal reception fifo hard- ware clear ep0nkr bit of uf0e0n register ep0r bit of uf0eps0 register e0odt bit of uf0is1 register hardware clear hardware clear reading fifo starts reading fifo completed (2) uf0 ep0 length register (uf0e0l) the uf0e0l register stores the data length held by the uf0e0r register. this register is read-only, in 8-bit units. a write access to this register is ignored. the uf0e0l register always updates the length of the received data while it is receiving data. if the final transfer is abnormal reception, the uf0e0l register is cleared to 0 and the interrupt request is not generated. the interrupt request is generated only when the recept ion is normal, and the fw can read as many data from the uf0e0r register as the value read from the uf0e0l register. the value of the uf0e0l register is decremented each time the uf0e0r register has been read. e0l7 uf0e0l e0l6 5 e0l5 e0l4 3 e0l3 2 e0l2 1 e0l1 e0l0 address fffffe81h after reset 00h 0 4 6 7 bit position bit name function 7 to 0 e0l7 to e0l0 these bits store the data length held by the uf0e0r register. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 626 (3) uf0 ep0 setup register (uf0e0st) the uf0e0st register holds the setup data sent from the host. this register is read-only, in 8-bit units. a write access to this register is ignored. the uf0e0st register always writes data when a set up transaction has been received. the hardware sets the prot bit of the uf0is1 register when it has co rrectly received the setup transaction. it sets the cpudec bit of the uf0is1 register in the case of an fw-processed request. then an interrupt request (intusb0b) is issued. in the case of an fw-processed re quest, be sure to read the request in 8-byte units. if it is not read in 8-byte units, t he subsequent requests cannot be correc tly decoded. the read counter of the uf0e0st register is not cleared even when bus reset is received. always read this counter in 8-byte units regardless of whether bus reset is received or not. because the uf0e0st register always enables writing, the hardware overwrites data to this register even if a setup transaction is received while the data of the regi ster is being read. even if the setup transaction cannot be correctly received, the cpudec interrupt reque st and protect interrupt request are not generated, but the previous data is discarded. if a setup token of less than 8 bytes is received, however, the received setup token is discarded, and the previously received setup data is retained. if the setup token is received more than once when control transfer is executed once, be sure to check the prot bit of the uf0is1 register under the conditions below. if prot bit = 1, read the uf0e0st regist er again because the setup transaction has been received more than once. <1> if a request is decoded by fw and the uf0e0r regi ster is read or the uf0e0w register is written <2> when preparing for a stall response for the request to which the decode result does not correspond caution be sure to read all the st ored data. the uf0e0st register is always updated by the request in the setup transaction. e0s7 uf0e0st e0s6 5 e0s5 e0s4 3 e0s3 2 e0s2 1 e0s1 e0s0 address fffffe82h after reset 00h 0 4 6 7 bit position bit name function 7 to 0 e0s7 to e0s0 these bits hold the setup data sent from the host. the operation of the uf0e0st r egister is illustrated below. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 627 figure 11-2. operation of uf0e0st register (a) normal status of uf0e0st register completion of normal reception of setup token completion of normal reception of setup token cpudec bit of uf0is1 register prot bit of uf0is1 register hardware clear fw processing int clear (fw clear) completion of decoding request completion of reading fifo completion of decoding request completion of reading fifo int clear (fw clear) hardware processing (b) when setup transaction is received more than once status of uf0e0st register completion of normal reception of setup token start of reception of second setup token completion of normal reception of second setup token cpudec bit of uf0is1 register prot bit of uf0is1 register hardware clear int clear (fw clear) int clear (fw clear) completion of decoding request completion of decoding request completion of reading fifo hardware clear on completion of reading 8 bytes chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 628 (4) uf0 ep0 write register (uf0e0w) the uf0e0w register is a 64-byte fifo that stores the in data (passes it to sie) sent to the host in the data stage to endpoint0. this register is write-only, in 8-bit units. when this register is read, 00h is read. the hardware transmits data to the usb bus in synchro nization with an in token only when the ep0nkw bit of the uf0e0n register is set to 1 (when nak is not transmitted). when data is transmitted and when the host correctly receives the data, the ep0nkw bit of the uf0e0n regist er is automatically cleared to 0 by hardware. a short packet is transmitted when data is written to the uf0e0w register and the e0ded bit of the uf0dend register is set to 1 (ep0w bit of the uf0eps0 register = 1 (data exists)). a null packet is transmitted when the uf0e0w register is cleared and the e0ded bit of the uf 0dend register is set to 1 (ep0w bit of the uf0eps0 register = 1 (data exists)). the uf0e0w register is cleared to 0 when the next setup token is received while transmission has not been completed yet. if the stage of control transfer (read ) changes to the status stage while ack has not been correctly received in the data stage, the uf0e0w register is automatically cleared to 0. at the same time, it is also cleared to 0 if the ep0nkw bit of the uf0e0n register is 1. if the uf0e0w register is read while no data is in it, 00h is read. e0w7 uf0e0w e0w6 5 e0w5 e0w4 3 e0w3 2 e0w2 1 e0w1 e0w0 address fffffe83h after reset undefined 0 4 6 7 bit position bit name function 7 to 0 e0w7 to e0w0 these bits store the in data sent to the host in the data stage to endpoint0. the operation of the uf0e0w r egister is illustrated below. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 629 figure 11-3. operation of uf0e0w register (a) 16-byte transmission status of uf0e0w register trans- mission starts trans- mission completed ack reception trans- mission starts trans- mission completed re- trans- mission starts ack reception ack cannot be received ep0nkw bit of uf0en register ep0w bit of uf0eps0 register e0indt bit of uf0is1 register fifo full hardware clear fifo full 16-byte transfer 16-byte transfer re-transfer int clear (fw clear) writing fifo starts writing fifo completed writing fifo starts writing fifo completed counter reloaded (b) when null packet or short packet is transmitted status of uf0e0w register transmission starts trans- mission completed ack reception transmission starts trans- mission completed ack reception ep0nkw bit of uf0en register ep0w bit of uf0eps0 register e0indt bit of uf0is1 register hardware clear e0ded bit of uf0dend register is set. e0ded bit of uf0dend register is set. short packet transfer transfer of null packet int clear (fw clear) writing fifo starts writing fifo completed fifo fw clear chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 630 (5) uf0 bulk out 1 register (uf0bo1) the uf0bo1 register is a 64-byte 2 fifo that stores data for endpoint2. this register consists of two banks of 64-byte fifos each of which perfo rms a toggle operation and repeatedly connects the buses on the sie and cpu sides. the toggle operation takes place when data is in the fifo on the sie side and when no data is in the fifo on the cpu side (counter value = 0). this register is read-only, in 8-bit units. a write access to this register is ignored. when the hardware receives data for endpoint2 from t he host, it automatically transfers the data to the uf0bo1 register. when the register correctly receives the data, a fifo toggle operat ion occurs. as a result, the bko1dt bit of the uf0is3 register is set to 1, the quantity of the received data is held by the uf0bo1l register, and an interrupt request or dma request is issu ed to the cpu. whether the interrupt request or dma request is issued can be selected by usin g the dqbo1ms bit of the uf0idr register. read the data held by the uf0bo1 register by fw, up to the value of the am ount of data read by the uf0bo1l register. when the correct received data is held by the fifo connected to the sie side and the value of the uf0bo1l register reache s 0, the toggle operation of the fi fo occurs, and the bko1nk bit of the uf0en register is automatically cleared to 0. if data gr eater than the value of the uf0bo1l register is read and if the fifo toggle condition is satisfied, the toggl e operation of the fifo occurs. as a result, the next packet may be read by mistake. note that, if the toggle condition is not satisfied, the first data is repeatedly read. if overrun data is received while data is held by the fi fo connected to the cpu side, endpoint2 stalls, and the fifo on the cpu side is cleared. when the uf0bo1 register is read while no data is in it, an undefined value is read. caution be sure to read all the data stored in this register. bko17 uf0bo1 bko16 5 bko15 bko14 3 bko13 2 bko12 1 bko11 bko10 address fffffe84h after reset undefined 0 4 6 7 bit position bit name function 7 to 0 bko17 to bko10 these bits store data for endpoint2. the operation of the uf0bo1 r egister is illustrated below. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 631 figure 11-4. operation of uf0bo1 register (1/2) (a) operation example 1 sie side cpu side status of uf0bo1 register reception completed fifo toggle fifo toggle ack transmission transmission starts transmission completed ack transmission bko1nk bit of uf0en register bko1fl bit of uf0is3 register bkout1 bit of uf0eps0 register bko1dt bit of uf0is3 register transfer of data less than 64 bytes 64-byte transfer 64-byte transfer fifo_0 fifo_1 fifo_1 fifo_0 reading fifo starts reading fifo completed reading fifo starts reading fifo completed f w clear fifo_0 fifo_1 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 632 figure 11-4. operation of uf0bo1 register (2/2) (b) operation example 2 sie side cpu side status of uf0bo1 register reception completed transmission starts null reception completed null reception completed fifo toggle fifo toggle ack transmission transmission starts reception completed ack transmission bko1nl bit of uf0is3 register bkout1 bit of uf0eps0 register bko1dt bit of uf0is3 register transfer of data less than 64 bytes 0-byte transfer 0-byte transfer 64-byte transfer 64-byte transfer fifo_0 fifo_1 fifo_1 fifo_0 reading fifo starts reading fifo completed fw clear fw clear fifo_0 fifo_1 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 633 (6) uf0 bulk out 1 length register (uf0bo1l) the uf0bo1l register stores the length of the data held by the uf0bo1 register. this register is read-only, in 8-bit units. a write access to this register is ignored. the uf0bo1l register always updates the received data length while it is receiving data. if the final transfer is abnormal reception, the uf0bo 1l register is cleared to 00h, and an interrupt request is not generated. only if the reception is normal, the interrupt request is gener ated, and fw can read as much data from the uf0bo1 register as the value read from t he uf0bo1l register. the value of the uf0bo1l register is decremented each time the uf0bo1 register has been read. bko1l7 uf0bo1l bko1l6 5 bko1l5 bko1l4 3 bko1l3 2 bko1l2 1 bko1l1 bko1l0 address fffffe85h after reset 00h 0 4 6 7 bit position bit name function 7 to 0 bko1l7 to bko1l0 these bits store the length of the data held by the uf0bo1 register. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 634 (7) uf0 bulk out 2 register (uf0bo2) the uf0bo2 register is a 64-byte 2 fifo that stores data for endpoint4. this register consists of two banks of 64-byte fifos each of which perfo rms a toggle operation and repeatedly connects the buses on the sie and cpu sides. the toggle operation takes place when data is in the fifo on the sie side and when no data is in the fifo on the cpu side (counter value = 0). this register is read-only, in 8-bit units. a write access to this register is ignored. when the hardware receives data for endpoint4 from t he host, it automatically transfers the data to the uf0bo2 register. when the register correctly receives the data, a fifo toggle operat ion occurs. as a result, the bko2dt bit of the uf0is3 register is set to 1, the quantity of the received data is held by the uf0bo2l register, and an interrupt request or dma request is issu ed to the cpu. whether the interrupt request or dma request is issued can be selected by usin g the dqbo2ms bit of the uf0idr register. read the data held by the uf0bo2 register by fw, up to the value of the am ount of data read by the uf0bo2l register. when the correct received data is held by the fifo connected to the sie side and the value of the uf0bo2l register reache s 0, the toggle operation of the fi fo occurs, and the bko2nk bit of the uf0en register is automatically cleared to 0. if data gr eater than the value of the uf0bo2l register is read and if the fifo toggle condition is satisfied, the toggl e operation of the fifo occurs. as a result, the next packet may be read by mistake. note that, if the toggle condition is not satisfied, the first data is repeatedly read. if overrun data is received while data is held by the fi fo connected to the cpu side, endpoint4 stalls, and the fifo on the cpu side is cleared. when the uf0bo2 register is read while no data is in it, an undefined value is read. caution be sure to read all the data stored in this register. bko27 uf0bo2 bko26 5 bko25 bko24 3 bko23 2 bko22 1 bko21 bko20 address fffffe86h after reset undefined 0 4 6 7 bit position bit name function 7 to 0 bko27 to bko20 these bits store data for endpoint4. the operation of the uf0bo2 r egister is illustrated below. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 635 figure 11-5. operation of uf0bo2 register (1/2) (a) operation example 1 sie side cpu side status of uf0bo2 register reception completed fifo toggle fifo toggle ack transmission transmission starts reception completed ack transmission bko2nk bit of uf0en register bko2fl bit of uf0is3 register bkout2 bit of uf0eps0 register bko2dt bit of uf0is3 register 64-byte transfer 64-byte transfer fifo_0 fifo_1 fifo_1 fifo_0 reading fifo starts reading fifo completed reading fifo starts reading fifo completed f w clear fifo_0 fifo_1 transfer of data less than 64 bytes chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 636 figure 11-5. operation of uf0bo2 register (2/2) (b) operation example 2 sie side cpu side status of uf0bo2 register reception completed transmission starts null reception completed null reception completed fifo toggle fifo toggle ack transmission transmission starts reception completed ack transmission bko2nl bit of uf0is3 register bkout2 bit of uf0eps0 register bko2dt bit of uf0is3 register transfer of data less than 64 bytes 0-byte transfer 0-byte transfer 64-byte transfer fifo_0 fifo_1 fifo_1 fifo_0 reading fifo starts reading fifo completed f w clear f w clear fifo_0 fifo_1 64-byte transfer chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 637 (8) uf0 bulk out 2 length register (uf0bo2l) the uf0bo2l register stores the length of the data held by the uf0bo2 register. this register is read-only, in 8-bit units. a write access to this register is ignored. the uf0bo2l register always updates the received data length while it is receiving data. if the final transfer is abnormal reception, the uf0bo 2l register is cleared to 00h, and an interrupt request is not generated. only if the reception is normal, the interrupt request is gener ated, and fw can read as much data from the uf0bo2 register as the value read from t he uf0bo2l register. the value of the uf0bo2l register is decremented each time the uf0bo2 register has been read. bko2l7 uf0bo2l bko2l6 5 bko2l5 bko2l4 3 bko2l3 2 bko2l2 1 bko2l1 bko2l0 address fffffe87h after reset 00h 0 4 6 7 bit position bit name function 7 to 0 bko2l7 to bko2l0 these bits store the length of the data held by the uf0bo2 register. (9) uf0 bulk in 1 register (uf0bi1) the uf0bi1 register is a 64-byte 2 fifo that stores data for endpoint1. this register consists of two banks of 64-byte fifos each of which perfo rms a toggle operation and repeatedly connects the buses on the sie and cpu sides. the toggle operation takes place when no data is in the fifo on the sie side (counter value = 0) and when the fifo on the cpu side is correctl y written (fifo full or bki1ded bit = 1). this register is write-only, in 8-bit units. when this register is read, 00h is read. the hardware transmits data to the usb bus in synchronization with the in token for endpoint1 only when the bki1nk bit of the uf0en register is set to 1 (when nak is not transmitted). the addr ess at which data is to be written or read is managed by the har dware. therefore, fw can transmit data to the host only by writing the data to the uf0bi1 register sequentially. a short packet is transmitted when data is written to the uf0bi1 register and the bki1ded bit of the uf0dend register is set to 1 ( bkin1 bit of uf0eps0 register = 1 (data exists)). a null packet is transmitted when the uf0b i1 register is cleared and the bki1ded bit of the uf0dend register is set to 1 (bkin1 bit of the uf0eps0 regist er = 1 (data exists)). an interrupt request or dma request can be selected by using t he dqbi1ms bit of the uf0idr register. bki17 uf0bi1 bki16 5 bki15 bki14 3 bki13 2 bki12 1 bki11 bki10 address fffffe88h after reset undefined 0 4 6 7 bit position bit name function 7 to 0 bki17 to bki10 these bits store data for endpoint1. the operation of the uf0bi1 regi ster is illustrated below. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 638 figure 11-6. operation of uf0bi1 register (1/3) (a) operation example 1 sie side cpu side status of uf0bo1 register transmission completed fifo toggle fifo toggle ack reception transmission starts transmission completed ack reception bki1nk bit of uf0en register 64-byte transfer 64-byte transfer fifo_0 fifo_1 fifo_1 fifo_0 writing fifo starts writing fifo completed writing fifo starts writing fifo completed bki1dt bit of uf0is2 register hardware clear int clear (fw clear) bki1ded bit of uf0dend register is set or hardware set bki1ded bit of uf0dend register is set or hardware set fifo_0 fifo_1 64-byte transfer chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 639 figure 11-6. operation of uf0bi1 register (2/3) (b) operation example 2 sie side cpu side status of uf0bo1 register transmission completed fifo toggle ack reception transmission starts transmission completed ack reception re- transmission starts ack cannot be received bki1nk bit of uf0en register 64-byte transfer re-transfer 64-byte transfer fifo_0 fifo_1 fifo_1 fifo_0 writing fifo starts writing fifo completed writing fifo starts writing fifo completed bki1dt bit of uf0is2 register hardware clear int clear (fw clear) chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 640 figure 11-6. operation of uf0bi1 register (3/3) (c) operation example 3 sie side cpu side status of uf0bo1 register transmission completed fifo toggle fifo toggle ack reception transmission starts transmission completed ack reception bki1nk bit of uf0en register transfer of null packet short packet transfer 64-byte transfer fifo_0 fifo_1 fifo_1 fifo_0 fifo clear writing fifo starts writing fifo completed bki1dt bit of uf0is2 register hardware clear int clear (fw clear) bki1ded bit of uf0dend register is set. bki1ded bit of uf0dend register is set. fifo_0 fifo_1 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 641 (10) uf0 bulk in 2 register (uf0bi2) the uf0bi2 register is a 64-byte 2 fifo that stores data for endpoint3. this register consists of two banks of 64-byte fifos each of which performs a toggle oper ation and repeatedly connects the buses on the sie and cpu sides. the toggle operation takes place when no data is in the fifo on the sie side (counter value = 0) and when the fifo on the cpu side is corre ctly written (fifo full or bki2ded bit = 1). this register is write-only, in 8-bit units. when this register is read, 00h is read. the hardware transmits data to the usb bus in synchronization with the in token for endpoint3 only when the bki2nk bit of the uf0en register is set to 1 (when nak is not transmitted). the address at which data is to be written or read is managed by the hardware. therefore, fw can trans mit data to the host only by writing the data to the uf0bi2 regist er sequentially. a short packet is trans mitted when data is written to the uf0bi2 register and the bki2ded bit of the uf0dend register is set to 1 (bkin2 bit of uf0eps0 register = 1 (data exists)). a null packet is transmitted when the uf0bi2 register is cleared and the bki2ded bit of the uf0dend register is set to 1 (bkin2 bit of the uf0eps0 register = 1 (data exists)). an interrupt request or dma request can be selected by using t he dqbi2ms bit of the uf0idr register. bki27 uf0bi2 bki26 5 bki25 bki24 3 bki23 2 bki22 1 bki21 bki20 address fffffe89h after reset undefined 0 4 6 7 bit position bit name function 7 to 0 bki27 to bki20 these bits store data for endpoint3. the operation of the uf0bi2 regi ster is illustrated below. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 642 figure 11-7. operation of uf0bi2 register (1/3) (a) operation example 1 sie side cpu side status of uf0bi2 register transmission completed fifo toggle fifo toggle ack reception transmission starts transmission completed ack reception bki2nk bit of uf0en register 64-byte transfer 64-byte transfer fifo_0 fifo_1 fifo_1 fifo_0 writing fifo starts writing fifo completed writing fifo starts writing fifo completed bki2dt bit of uf0is2 register hardware clear int clear (fw clear) bki2ded bit of uf0dend register is set or hardware set. bki2ded bit of uf0dend register is set or hardware set. fifo_0 fifo_1 64-byte transfer chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 643 figure 11-7. operation of uf0bi2 register (2/3) (b) operation example 2 sie side cpu side status of uf0bi2 register transmission completed fifo toggle ack reception transmission starts transmission completed ack reception re- transmission starts ack cannot be received bki2nk bit of uf0en register 64-byte transfer re-transfer 64-byte transfer fifo_0 fifo_1 fifo_1 fifo_0 writing fifo starts writing fifo completed writing fifo starts writing fifo completed bki2dt bit of uf0is2 register hardware clear int clear (fw clear) chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 644 figure 11-7. operation of uf0bi2 register (3/3) (c) operation example 3 sie side cpu side status of uf0bi2 register transmission completed fifo toggle fifo toggle ack reception transmission starts transmission completed ack reception bki2nk bit of uf0en register short packet transfer 64-byte transfer fifo_0 fifo_1 fifo_1 fifo_0 fifo clear writing fifo starts writing fifo completed bki2dt bit of uf0is2 register hardware clear int clear (fw clear) bki2ded bit of uf0dend register is set. bki2ded bit of uf0dend register is set. fifo_0 fifo_1 transfer of null packet chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 645 (11) uf0 interrupt 1 register (uf0int1) the uf0int1 register is an 8-by te fifo that stores data for e ndpoint7 (to be passed to sie). this register is write-only, in 8-bit units. when this register is read, 00h is read. the hardware transmits data to the usb bus in synchronization with the in token for endpoint7 only when the it1nk bit of the uf0en register is set to 1 (when n ak is not transmitted). when the data is transmitted and the host correctly receives it, the it1n k bit of the uf0en register is automatically cleared to 0 by hardware. a short packet is transmitted when data is written to the uf0int1 register and the it1dend bit of the uf0dend register is set to 1 (it1 bi t of the uf0eps0 register = 1 (data exists)). a null packet is transmitted when the uf0int1 register is cleared a nd the it1dend bit of the uf0dend regi ster is set to 1 (it1 bit of the uf0eps0 register = 1 (data exists)). it17 uf0int1 it16 5 it15 it14 3 it13 2 it12 1 it11 it10 address fffffe8ah after reset undefined 0 4 6 7 bit position bit name function 7 to 0 it17 to it10 these bits store data for endpoint7. the operation of the uf 0int1 register is illustrated below. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 646 figure 11-8. operation of uf0int1 register (a) 8-byte transfer status of uf0int1 register transmission starts transmission completed ack reception transmission starts transmission completed re-transmission starts ack reception ack cannot be received it1nk bit of uf0en register it1 bit of uf0eps0 register it1dt bit of uf0is2 register fifo full hardware clear fifo full 8-byte transfer 8-byte transfer re-transfer int clear (fw clear) writing fifo starts writing fifo completed writing fifo starts writing fifo completed counter reloaded (b) when null packet or short packet is transmitted status of uf0int1 register transmission starts transmission completed ack reception transmission starts transmission completed ack reception it1nk bit of uf0en register it1 bit of uf0eps0 register it1dt bit of uf0is2 register hardware clear it1dend bit of uf0dend register is set. it1dend bit of uf0dend register is set. short packet transfer transfer of null packet int clear (fw clear) writing fifo starts writing fifo completed fifo fw clear chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 647 (12) uf0 interrupt 2 register (uf0int2) the uf0int2 register is an 8-by te fifo that stores data for e ndpoint8 (to be passed to sie). this register is write-only, in 8-bit units. when this register is read, 00h is read. the hardware transmits data to the usb bus in synchronization with the in token for endpoint8 only when the it2nk bit of the uf0en register is set to 1 (when n ak is not transmitted). when the data is transmitted and the host correctly receives it, the it2n k bit of the uf0en register is automatically cleared to 0 by hardware. a short packet is transmitted when data is written to the uf0int2 register and the it2dend bit of the uf0dend register is set to 1 (it2 bi t of the uf0eps0 register = 1 (data exists)). a null packet is transmitted when the uf0int2 register is cleared a nd the it2dend bit of the uf0dend regi ster is set to 1 (it2 bit of the uf0eps0 register = 1 (data exists)). it27 uf0int2 it26 5 it25 it24 3 it23 2 it22 1 it21 it20 address fffffe8bh after reset undefined 0 4 6 7 bit position bit name function 7 to 0 it27 to it20 these bits store data for endpoint8. the operation of the uf 0int2 register is illustrated below. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 648 figure 11-9. operation of uf0int2 register (a) 8-byte transfer status of uf0int2 register transmission starts transmission completed ack reception transmission starts transmission completed re- transmission starts ack reception ack cannot be received it2nk bit of uf0en register it2 bit of uf0eps0 register it2dt bit of uf0is2 register fi fo full hardware clear fi fo full 8-byte transfer re-transfer int clear (fw clear) writing fifo starts writing fifo completed writing fifo starts writing fifo completed counter reloaded 8-byte transfer (b) when null packet or short packet is transmitted status of uf0int2 register transmission starts transmission completed ack reception transmission starts transmission completed ack reception it2nk bit of uf0en register it2 bit of uf0eps0 register it2dt bit of uf0is2 register hardware clear it1dend bit of uf0dend register is set. it1dend bit of uf0dend register is set. short packet transfer transfer of null packet int clear (fw clear) writing fifo starts writing fifo completed fifo fw clear chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 649 11.4.3 request data register area (1) uf0 device status register l (uf0dstl) this register stores the value that is to be retu rned in response to the get_status device request. this register can be read or written in 8-bit units. the hardware automatically transmits the contents of this register to the host when it has received the get_status device request. caution to rewrite this register, set the ep0nka bi t to 1 before reading the register contents, and rewrite the register contents after confirming th at the bit has been set , in order to prevent conflict between a read access and a write access. 0 uf0dstl 0 5 00 3 0 2 0 1 rmwk sfpw address fffffea2h after reset 00h 0 4 6 7 bit position bit name function 1 rmwk this bit specifies whether the remo te wakeup function of the device is used. 1: enabled 0: disabled if the device supports a remote wakeup function, this bit is set to 1 by hardware when the set_feature device request has been received, and is cleared to 0 by hardware when the clear_feature device request has been received. if the device does not support a remote wakeup function, make sure that the set_feature device request is not issued from the host. 0 sfpw this bit indicates whether the de vice is self-powered or bus-powered. 1: self-powered 0: bus-powered chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 650 (2) uf0 ep0 status register l (uf0e0sl) this register stores the value that is to be retur ned in response to the get_status endpoint0 request. this register can be read or written in 8-bit units. note, however, that data can be written to this register only when the ep0nka bit is set to 1. if an error occurs in usbf, the e0halt bit is set to 1 by fw. a write access to this register is ignored while a usb-side access to endpoint0 is being received. when the e0halt bit is set to 1 by fw, it is not reflected until the next setup token is received if the control transfer immediately before is for the set_feature endpoint0, clear_feature endpoint0, get_status endpoint0 request, or an fw-processed request. the hardware automatically transmits the contents of this register to the host when it has received the get_status endpoint0 request. if endpoint0 has st alled, the uf0e0w and uf0e 0r registers are cleared, and the ep0nkw and ep0nkr bits of the uf 0e0n register are cleared to 0. caution to rewrite this register, set the ep0nka bi t to 1 before reading the register contents, and rewrite the register contents after confirming th at the bit has been set , in order to prevent conflict between a read access and a write access. 0 uf0e0sl 0 5 00 3 0 2 0 1 0 e0halt address fffffea6h after reset 00h 0 4 6 7 bit position bit name function 0 e0halt this bit indicates the status of endpoint0. 1: stalled 0: not stalled this bit is set to 1 by hardware when the set_feature endpoint0 request has been received, and cleared to 0 by hardware when the clear_feature endpoint0 request has been received. data pid is initialized to data0. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 651 (3) uf0 ep1 status register l (uf0e1sl) this register stores the value that is to be retur ned in response to the get_status endpoint1 request. this register can be read or written in 8-bit units. note, however, that data can be written to this register only when the ep0nka bit is set to 1. if an error occurs in endpoint1, the e1halt bit is set to 1. a write access to this register is ignored while a usb-side access to endpoint1 is being received. the hardware automatically transmits the contents of this register to the host when it has received the get_status endpoint1 request. if endpoint1 has stalled, the uf0bi1 register is cleared and the bki1nk bit is cleared to 0. because writing this register is always masked when transfer to endpoint1, rather than control transfer, is executed, be sure to check this register to see if data has been correctly written to it. caution to rewrite this register, set the ep0nka bi t to 1 before reading the register contents, and rewrite the register contents after confirming th at the bit has been set , in order to prevent conflict between a read access and a write access. 0 uf0e1sl 0 5 00 3 0 2 0 1 0 e1halt address fffffea8h after reset 00h 0 4 6 7 bit position bit name function 0 e1halt this bit indicates the status of endpoint1. 1: stalled 0: not stalled this bit is set to 1 by hardware when the set_feature endpoint1 request has been received. it is cleared to 0 by hardware when the clear_feature endpoint1 request, set_configuration request, or the set_interface request for the interface to which endpoint1 is linked has correctly been received. data pid is initialized to data0. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 652 (4) uf0 ep2 status register l (uf0e2sl) this register stores the value that is to be retur ned in response to the get_status endpoint2 request. this register can be read or written in 8-bit units. note, however, that data can be written to this register only when the ep0nka bit is set to 1. if an error occurs in endpoint2, the e2halt bit is set to 1. a write access to this register is ignored while a usb-side access to endpoint2 is being received. the hardware automatically transmits the contents of this register to the host when it has received the get_status endpoint2 request. if endpoint2 has stall ed, the uf0bo1 register is cleared and the bko1nk bit is cleared to 0. because writing this register is always masked when transfer to endpoint2, rather than control transfer, is executed, be sure to check this register to see if data has been correctly written to it. caution to rewrite this register, set the ep0nka bi t to 1 before reading the register contents, and rewrite the register contents after confirming th at the bit has been set , in order to prevent conflict between a read access and a write access. 0 uf0e2sl 0 5 00 3 0 2 0 1 0 e2halt address fffffeaah after reset 00h 0 4 6 7 bit position bit name function 0 e2halt this bit indicates the status of endpoint2. 1: stalled 0: not stalled this bit is set to 1 by hardware when the set_feature endpoint2 request has been received. it is cleared to 0 by hardware when the clear_feature endpoint2 request, set_configuration request, or the set_interface request for the interface to which endpoint2 is linked has correctly been received. data pid is initialized to data0. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 653 (5) uf0 ep3 status register l (uf0e3sl) this register stores the value that is to be retur ned in response to the get_status endpoint3 request. this register can be read or written in 8-bit units. note, however, that data can be written to this register only when the ep0nka bit is set to 1. if an error occurs in endpoint3, the e3halt bit is set to 1. a write access to this register is ignored while a usb-side access to endpoint3 is being received. the hardware automatically transmits the contents of this register to the host when it has received the get_status endpoint3 request. if endpoint3 has stalled, the uf0bi2 register is cleared and the bki2nk bit is cleared to 0. because writing this register is always masked when transfer to endpoint3, rather than control transfer, is executed, be sure to check this register to see if data has been correctly written to it. caution to rewrite this register, set the ep0nka bi t to 1 before reading the register contents, and rewrite the register contents after confirming th at the bit has been set , in order to prevent conflict between a read access and a write access. 0 uf0e3sl 0 5 00 3 0 2 0 1 0 e3halt address fffffeach after reset 00h 0 4 6 7 bit position bit name function 0 e3halt this bit indicates the status of endpoint3. 1: stalled 0: not stalled this bit is set to 1 by hardware when the set_feature endpoint3 request has been received. it is cleared to 0 by hardware when the clear_feature endpoint3 request, set_configuration request, or the set_interface request for the interface to which endpoint3 is linked has correctly been received. data pid is initialized to data0. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 654 (6) uf0 ep4 status register l (uf0e4sl) this register stores the value that is to be retur ned in response to the get_status endpoint4 request. this register can be read or written in 8-bit units. note, however, that data can be written to this register only when the ep0nka bit is set to 1. if an error occurs in endpoint4, the e4halt bit is set to 1. a write access to this register is ignored while a usb-side access to endpoint4 is being received. the hardware automatically transmits the contents of this register to the host when it has received the get_status endpoint4 request. if endpoint4 has stall ed, the uf0bo2 register is cleared and the bko2nk bit is cleared to 0. because writing this register is always masked when transfer to endpoint4, rather than control transfer, is executed, be sure to check this register to see if data has been correctly written to it. caution to rewrite this register, set the ep0nka bi t to 1 before reading the register contents, and rewrite the register contents after confirming th at the bit has been set , in order to prevent conflict between a read access and a write access. 0 uf0e4sl 0 5 00 3 0 2 0 1 0 e4halt address fffffeaeh after reset 00h 0 4 6 7 bit position bit name function 0 e4halt this bit indicates the status of endpoint4. 1: stalled 0: not stalled this bit is set to 1 by hardware when the set_feature endpoint4 request has been received. it is cleared to 0 by hardware when the clear_feature endpoint4 request, set_configuration request, or the set_interface request for the interface to which endpoint4 is linked has correctly been received. data pid is initialized to data0. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 655 (7) uf0 ep7 status register l (uf0e7sl) this register stores the value that is to be retur ned in response to the get_status endpoint7 request. this register can be read or written in 8-bit units. note, however, that data can be written to this register only when the ep0nka bit is set to 1. if an error occurs in endpoint7, the e7halt bit is set to 1. a write access to this register is ignored while a usb-side access to endpoint7 is being received. the hardware automatically transmits the contents of this register to the host when it has received the get_status endpoint7 request. if endpoint7 has stall ed, the uf0int1 r egister is cleared and the it1nk bit is cleared to 0. because writing this register is always masked when transfer to endpoint7, rather than control transfer, is executed, be sure to check this register to see if data has been correctly written to it. caution to rewrite this register, set the ep0nka bi t to 1 before reading the register contents, and rewrite the register contents after confirming th at the bit has been set , in order to prevent conflict between a read access and a write access. 0 uf0e7sl 0 5 00 3 0 2 0 1 0 e7halt address fffffeb4h after reset 00h 0 4 6 7 bit position bit name function 0 e7halt this bit indicates the status of endpoint7. 1: stalled 0: not stalled this bit is set to 1 by hardware when the set_feature endpoint7 request has been received. it is cleared to 0 by hardware when the clear_feature endpoint7 request, set_configuration request, or the set_interface request for the interface to which endpoint7 is linked has correctly been received. data pid is initialized to data0. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 656 (8) uf0 ep8 status register l (uf0e8sl) this register stores the value that is to be retur ned in response to the get_status endpoint8 request. this register can be read or written in 8-bit units. note, however, that data can be written to this register only when the ep0nka bit is set to 1. if an error occurs in endpoint8, the e8halt bit is set to 1. a write access to this register is ignored while a usb-side access to endpoint8 is being received. the hardware automatically transmits the contents of this register to the host when it has received the get_status endpoint8 request. if endpoint8 has stall ed, the uf0int2 r egister is cleared and the it2nk bit is cleared to 0. because writing this register is always masked when transfer to endpoint8, rather than control transfer, is executed, be sure to check this register to see if data has been correctly written to it. caution to rewrite this register, set the ep0nka bi t to 1 before reading the register contents, and rewrite the register contents after confirming th at the bit has been set , in order to prevent conflict between a read access and a write access. 0 uf0e8sl 0 5 00 3 0 2 0 1 0 e8halt address fffffeb6h after reset 00h 0 4 6 7 bit position bit name function 0 e8halt this bit indicates the status of endpoint8. 1: stalled 0: not stalled this bit is set to 1 by hardware when the set_feature endpoint8 request has been received. it is cleared to 0 by hardware when the clear_feature endpoint8 request, set_configuration request, or the set_interface request for the interface to which endpoint8 is linked has correctly been received. data pid is initialized to data0. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 657 (9) uf0 address register (uf0adrs) this register stores the device address. this register is read-only, in 8-bit units. the device address sent by the set_address request is analyzed and the resultant value is automatically written to this register. if the set_address request is proc essed by fw, the value of this register is reflected as the device address when the success signal is received in the status stage. caution to rewrite this register, set the ep0nka bi t to 1 before reading the register contents, and rewrite the register contents after confirming th at the bit has been set , in order to prevent conflict between a read access and a write access. 0 uf0adrs adrs6 5 adrs5 adrs4 3 adrs3 2 adrs2 1 adrs1 adrs0 address fffffec0h after reset 00h 0 4 6 7 bit position bit name function 6 to 0 adrs6 to adrs0 these bits hold the device address of sie. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 658 (10) uf0 configuration register (uf0cnf) this register stores the value that is to be re turned in response to the get_configuration request. this register is read-only, in 8-bit units. when the set_configuration request is received, its wval ue is automatically written to this register. to change the value of this register by fw after a value other than 00h has been written to the register, write 00h once and then write the desired valu e. when a change of the value of this register from 00h to other than 00h is detected, the conf bits are set to 1. if the set_configuration request is processed by fw, the status of this register is immediat ely reflected on the uf0mods register as soon as data has been written to this register (conf bits = 1 before completion of the status stage). caution to rewrite this register, set the ep0nka bi t to 1 before reading the register contents, and rewrite the register contents after confirming th at the bit has been set , in order to prevent conflict between a read access and a write access. 0 uf0cnf 0 5 00 3 0 2 0 1 conf1 conf0 address fffffec1h after reset 00h 0 4 6 7 bit position bit name function 1, 0 conf1, conf0 these bits hold the data to be returned in response to the get_configuration request. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 659 (11) uf0 interface 0 register (uf0if0) this register stores the value that is to be retur ned in response to the get_interface windex = 0 request. this register is read-only, in 8-bit units. when the set_interface request is received, its wval ue is automatically written to this register. if the set_interface request is processed by fw, windex and wvalue are decoded, and the setting of endpoint is automatically changed. at this time, t he status bit of the target endpoint and dpid are automatically cleared to 0, depending on the se tting. the fifo is not cleared automatically. caution to rewrite this register, set the ep0nka bi t to 1 before reading the register contents, and rewrite the register contents after confirming th at the bit has been set , in order to prevent conflict between a read access and a write access. 0 uf0if0 0 5 00 3 0 2 if02 1 if01 if00 address fffffec2h after reset 00h 0 4 6 7 bit position bit name function 2 to 0 if02 to if00 these bits hold the data to be returned in response to get_interface windex = 0 request. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 660 (12) uf0 interface 1 to 4 re gisters (uf0if1 to uf0if4) these registers store the value that is to be returned in response to the get_interface windex = n request (n = 1 to 4). these registers are read-only, in 8-bit units. when the set_interface request is received, its wval ue is automatically written to these registers. these registers are invalidated according to t he setting of the uf0aifn and uf0aas registers. if the set_interface request is processed by fw, windex and wvalue are decoded, and the setting of endpoint is automatically changed. at this time, t he status bit of the target endpoint and dpid are automatically cleared to 0, depending on the se tting. the fifo is not cleared automatically. caution to rewrite these registers, set the ep0nka bi t to 1 before reading the register contents, and rewrite the register contents after confirming th at the bit has been set , in order to prevent conflict between a read access and a write access. 0 0 0 0 uf0if1 uf0if2 uf0if3 uf0if4 0 0 0 0 5 0 0 0 0 0 0 0 0 3 0 0 0 0 2 if12 if22 if32 if42 1 if11 if21 if31 if41 if10 if20 if30 if40 address fffffec3h fffffec4h fffffec5h fffffec6h after reset 00h 00h 00h 00h 0 4 6 7 bit position bit name function 2 to 0 ifn2 to ifn0 these bits hold the data to be returned in response to get_interface windex = n request. remark n = 1 to 4 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 661 (13) uf0 descriptor length register (uf0dscl) this register stores the length of the value that is to be returned in response to the get_descriptor configuration request. the value of this register is the number of bytes of all the descriptors set by the uf0cien register minus 1 (n = 0 to 255). the total descriptor length that is to be returned in response to the get_descriptor configuration request is determine d according to the value of this register. this register can be read or written in 8-bit units. howe ver, data can be written to this register only when the ep0nka bit is set to 1. processing of wlength is automatically controlled. if this register is set to 00h, it means that the descriptor to be returned is 1 byte long. if the register is set to ffh , a descriptor length of 256 bytes is returned. when a descriptor exceeding 256 bytes in length is used, se t the cdcgdst bit of the uf 0modc register to 1 and process the get_descriptor request by fw (at this ti me, the cdcgd bit of the uf0mods register is also set to 1). caution to rewrite this register, set the ep0nka bi t to 1 before reading the register contents, and rewrite the register contents after confirming th at the bit has been set , in order to prevent conflict between a read access and a write access. dpl7 uf0dscl dpl6 5 dpl5 dpl4 3 dpl3 2 dpl2 1 dpl1 dpl0 address fffffed0h after reset 00h 0 4 6 7 bit position bit name function 7 to 0 dpl7 to dpl0 these bits set the value of the number of bytes of all the descriptors to be returned in response to the get_descriptor configuration request minus 1. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 662 (14) uf0 device descriptor regist ers 0 to 17 (uf0dd0 to uf0dd17) these registers store the value to be returned in response to the get_descriptor device request. these registers can be read or written in 8-bit units. however, data can be written to these registers only when the ep0nka bit is set to 1. cautions 1. to rewrite these registers, set the ep0 nka bit to 1 before reading the register contents, and rewrite the register contents after confi rming that the bit has been set, in order to prevent conflict between a read access and a write access. 2. use the value defined by usb specification ver. 2.0 and the latest class specification as the set value. uf0ddn (n = 0 to 17) 5 3 2 1 after reset 0 4 6 7 undefined address see table 11-4 . table 11-4. mapping and data of uf0 device descriptor registers symbol address field name contents uf0dd0 fffffed1h blength size of this descriptor uf0dd1 fffffed2h bdescriptortype device descriptor type uf0dd2 fffffed3h value below decimal point of rev. number of usb specification uf0dd3 fffffed4h bcdusb value above decimal point of rev. number of usb specification uf0dd4 fffffed5h bdeviceclass class code uf0dd5 fffffed6h bdevicesubclass subclass code uf0dd6 fffffed7h bdeviceprotocol protocol code uf0dd7 fffffed8h bmaxpacketsize0 maximum packet size of endpoint0 uf0dd8 fffffed9h lower value of vendor id uf0dd9 fffffedah idvendor higher value of vendor id uf0dd10 fffffedbh lower value of product id uf0dd11 fffffedch idproduct higher value of product id uf0dd12 fffffeddh lower value of device release number uf0dd13 fffffedeh bcddevice higher value of device release number uf0dd14 fffffedfh imanufacturer index of string descriptor describing manufacturer uf0dd15 fffffee0h iproduct index of string descriptor describing product uf0dd16 fffffee1h lserialnumber index of string de scriptor describing device serial number uf0dd17 fffffee2h bnumconfigurations number of settable configurations chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 663 (15) uf0 configuration/interf ace/endpoint descriptor registers 0 to 255 (uf0cie0 to uf0cie255) these registers store the value to be returned in re sponse to the get_descriptor configuration request. these registers can be read or written in 8-bit units. however, data can be written to these registers only when the ep0nka bit is set to 1. descriptor information of up to 256 bytes can be stored in these registers. store each descriptor in the order of configuration, interface, and endpoint (see table 11-5 ). if there are two or more interfaces, repeatedly store the data following the interface descriptor. table 11-5. mapping of uf0cien register address descriptor stored fffffee3h configuration descriptor (9 bytes) fffffeech interface descriptor (9 bytes) fffffef5h endpoint1 descriptor (7 bytes) fffffefch endpoint2 descriptor (7 bytes) ffffff03h endpoint3 descriptor (7 bytes) : : ffffffxxh interface descriptor (9 bytes) ffffffxxh+9 endpoint1 descriptor (7 bytes) ffffffxxh+16 endpoint2 descriptor (7 bytes) ffffffxxh+23 endpoint3 descriptor (7 bytes) : : the range of the valid data t hat can be set to these registers varies according to the setting of the uf0dscl register. in addition to the descriptors listed in ta ble 11-6, descriptors peculiar to classes and vendors can also be stored. if all the values are fixed, they can be stored in rom. cautions 1. to rewrite these registers, set the ep0 nka bit to 1 before reading the register contents, and rewrite the register contents after confi rming that the bit has been set, in order to prevent conflict between a read access and a write access. 2. use the value defined by usb specification ver. 2.0 and the latest class specification as the set value. uf0cien (n = 0 to 255) 5 3 2 1 after reset 0 4 6 7 fffffee3h to ffffffe2h undefined address chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 664 table 11-6. data of uf0cien register (a) configuration descriptor (9 bytes) offset field name contents 0 blength size of this descriptor 1 bdescriptortype descriptor type 2 lower value of the total number of bytes of configuration, all interface, and all endpoint descriptors 3 wtotallength higher value of the total number of bytes of configuration, all interface, and all endpoint descriptors 4 bnuminterface number of interfaces 5 bconfigurationvalue value to select this configuration 6 iconfiguration index of string descriptor describing this configuration 7 bmattributes features of this configuration (self-powered, without remote wakeup) 8 maxpower maximum power consumption of this configuration (unit: ma) (b) interface descriptor (9 bytes) offset field name contents 0 blength size of this descriptor 1 bdescriptortype descriptor type 2 binterfacenumber value of this interface 3 balternatesetting value to select alternative setting of interface 4 bnumendpoints number of usable endpoints 5 binterfaceclass class code 6 binterfacesubclass subclass code 7 binterfaceprotocol protocol code 8 interface index of string descriptor describing this interface (c) endpoint descriptor (7 bytes) offset field name contents 0 blength size of this descriptor 1 bdescriptortype descriptor type 2 bendpointaddress address/transfer direction of this endpoint 3 bmattributes transfer type 4 lower value of maximum number of transfer data 5 wmaxpaketsize higher value of maximum number of transfer data 6 binterval transfer interval chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 665 11.4.4 peripheral control registers (1) usb function 0 dma channel select register (uf0cs) this register allocates each dma service of the usb function to a dma channel. this register can be read or written in 16-bit units. to allocate the service of a usb function to a dma channel by using this register, set this register in advance, set the dtfrn register (n = 0 to 3) of the dma controller to 7fh, and enable usb_dma in advance. caution setting the same dma service to different dma channels and setting different dma services to the same dma channel are prohibited. 14 ufd c32 13 ufd c31 12 ufd c30 2 ufd c02 3 0 4 ufd c10 5 ufd c11 6 ufd c12 7 0 8 ufd c20 9 ufd c21 10 ufd c22 11 0 15 0 1 ufd c01 0 ufd c00 uf0cs fffffdf0h, fffffdf1h after reset 0000h address bit position bit name function these bits set the dma service of a usb function to be allocated to dma channel n. ufdcn2 ufdcn1 ufdcn0 service to be allocated 1 1 1 ep4_dma 1 1 0 ep3_dma 1 0 1 ep2_dma 1 0 0 ep1_dma 0 x x no allocation (dma not used) 14 to 12, 10 to 8, 6 to 4, 2 to 0 ufdcn2 to ufdcn0 remark x: don?t care remark n = 0 to 3 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 666 (2) usb function 0 buffer control register (uf0bc) this register performs enable control and floating control on the input buffer of the usb function. this register can be read or written in 8-bit or 1-bit units. 0 uf0bc 0 5 00 3 0 2 0 1 ubfien ubfior address fffffedf2h after reset 00h 0 4 6 7 bit position bit name function 1 ubfien this bit controls use of the usb buffer. 1: buffer valid 0: buffer invalid caution clear this bit to 0 when the usb is not used. if this bit is set to 1, a current of 3 ma (typ.) constantly flows, regardless of whether the usb is used or not. 0 ubfior this bit controls use of floating measures of the usb buffer. 1: disables floating measures 0: enables floating measures this bit prevents erroneous recognition of bus reset, suspend, and resume due to an undefined value when a cable is not connecte d (when data input is floated). when this bit is set to 1, control the processing for floating by the vbus si gnal (which recognizes cable connection). chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 667 11.5 stall handshake or no handshake errors of usbf are defined to be handled as follows. transfer type transaction target packet error type function response processing endpoint not supported no response none endpoint transfer direction mismatch no response none crc error no response none control transfer/ bulk transfer/ interrupt transfer in/out/setup token bit stuffing error no response none timeout no response none pid check error no response none unsupported pid (other than data pid) no response none crc error no response discard received data out/setup data bit stuffing error no response discard received data control transfer/ bulk transfer out data data pid mismatch ack discard received data control transfer (setup stage) setup data overrun no response discard received data control transfer (data stage) out data overrun no response note 1 set sndstl bit of uf0sds register to 1 and discard received data control transfer (status stage) out data overrun ack or no response note 2 set sndstl bit of uf0sds register to 1 and discard received data bulk transfer out data overrun no response note 1 set enhalt bit of uf0ensl register (n = 0 to 4, 7, 8) to 1 pid check error ? hold transferred data and re-transfer data note 3 unsupported pid (other than ack pid) ? hold transferred data and re-transfer data note 3 control transfer/ bulk transfer/ interrupt transfer in handshake timeout ? hold transferred data and re-transfer data note 3 notes 1. a stall response is made to re-transfer by the host. 2. an ack response is made if the transfer data is of less than maxpacketsize and the data received in the status stage is discarded. if maxpacketsize is e xceeded, no response is made, the sndstl bit of the uf0sds register is set to 1, and the received data is discarded. 3. if an out transaction indicating a change from the data stage to the status stage is received during control transfer, an error is not handled and it is assumed that reception has been correctly completed. cautions 1. it is judged by the alternative setti ng number currently set whether the target endpoint is valid or invalid. 2. for the response to the request included in control transfer to/from endpoint0, see 11.3 requests. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 668 11.6 register values in specific status table 11-7. register values in specific status (1/2) register name after cpu reset (reset) after bus reset uf0e0n register 00h value is held. uf0e0na register 00h value is held. uf0en register 00h value is held. uf0enm register 00h value is held. uf0sds register 00h value is held. uf0clr register 00h value is held. uf0set register 00h value is held. uf0eps0 register 00h value is held. uf0eps1 register 00h value is held. uf0eps2 register 00h value is held. uf0is0 register 00h value is held. uf0is1 register 00h value is held. uf0is2 register 00h value is held. uf0is3 register 00h value is held. uf0is4 register 00h value is held. uf0im0 register 00h value is held. uf0im1 register 00h value is held. uf0im2 register 00h value is held. uf0im3 register 00h value is held. uf0im4 register 00h value is held. uf0ic0 register ffh value is held. uf0ic1 register ffh value is held. uf0ic2 register ffh value is held. uf0ic3 register ffh value is held. uf0ic4 register ffh value is held. uf0idr register 00h value is held. uf0dms0 register 00h value is held. uf0dms1 register 00h value is held. uf0fic0 register 00h value is held. uf0fic1 register 00h value is held. uf0dend register 00h value is held. uf0gpr register 00h value is held. uf0modc register 00h value is held. uf0mods register 00h bit 2 (conf): cleared (0), other bits: value is held. uf0aifn register 00h value is held. uf0aas register 00h value is held. uf0ass register 00h 00h uf0e1im register 00h value is held. uf0e2im register 00h value is held. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 669 table 11-7. register values in specific status (2/2) register name after cpu reset (reset) after bus reset uf0e3im register 00h value is held. uf0e4im register 00h value is held. uf0e7im register 00h value is held. uf0e8im register 00h value is held. uf0e0r register undefined note 1 value is held. uf0e0l register 00h value is held. uf0e0st register 00h 00h uf0e0w register undefined note 1 value is held. uf0bo1 register undefined note 1 value is held. uf0bo1l register 00h value is held. uf0bo2 register undefined note 1 value is held. uf0bo2l register 00h value is held. uf0bi1 register undefined note 1 value is held. uf0bi2 register undefined note 1 value is held. uf0int1 register undefined value is held. uf0int2 register undefined value is held. uf0dstl register 00h 00h uf0e0sl register 00h 00h uf0e1sl register 00h 00h uf0e2sl register 00h 00h uf0e3sl register 00h 00h uf0e4sl register 00h 00h uf0e7sl register 00h 00h uf0e8sl register 00h 00h uf0adrs register 00h 00h uf0cnf register 00h 00h uf0if0 register 00h 00h uf0if1 register 00h 00h uf0if2 register 00h 00h uf0if3 register 00h 00h uf0if4 register 00h 00h uf0dscl register 00h value is held. uf0ddn register (n = 0 to 17) note 2 note 2 uf0cien register (n = 0 to 255) note 2 note 2 notes 1. this register can be cleared to 0 by the reset signal because its write pointer, counter, and read pointer are cleared to 0 when the reset signal becomes active, in the same manner as clearing by the uf0ficn register, as the register is controlled by fifo. 2. this register cannot be cleared to 0. because data can be written to it by fw, however, any value can be written to the register (before doing so, however, be sure to set the ep0nka bit of the uf0e0na register to 1). chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 670 11.7 fw processing the following fw processing is performed. ? setting processing on device side for the set_c onfiguration, set_interface, set_feature, and clear_feature requests during enumeration processing ? analysis and processing of xxxxstandard, xxxxclass, and xxxxvendor requests not subject to automatic processing ? reading data following bulk-transferred out token from receive buffer ? writing data to be returned in response to bulk-transferred in token ? writing data to be returned in response to interrupt-transferred token the following table lists the requests supported by fw. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 671 table 11-8. fw-supported standard requests request reception side processing/ frequency explanation clear_feature interface automatic stall response it is considered that this request does not come to interface because there is no function selector value, though it is reserved for bmrequesttype. when this request is received, the hardware makes an automatic stall response. set_feature interface automatic stall response it is considered that this request does not come to interface because there is no function selector value, though it is reserved for bmrequesttype. when this request is received, the hardware makes an automatic stall response. get_descriptor string fw returns the string descriptor. when this request is received by the setup token, the hardware generates the cpudec interrupt request for fw. fw decodes the contents of the request from the cpudec interrupt request, and writes the data to be returned to the host, to the uf0e0w register. set_descriptor device fw rewrites the device descriptor. when this request is received by the setup token, the hardware generates the cpudec interrupt request for fw. fw decodes the contents of the request from the cpudec interrupt request, and the writes the data for the next control transfer (out) to the uf0ddn register (n = 0 to 17). set_descriptor configuration fw rewrites the configuration descriptor. when this request is received by the setup token, the hardware generates the cpudec interrupt request for fw. fw decodes the contents of the request from the cpudec interrupt request, and the writes the data for the next control transfer (out) to the uf0cien register (n = 0 to 255). set_descriptor string fw rewrites the string descriptor. when this request is received by the setup token, the hardware generates the cpudec interrupt request for fw. fw decodes the contents of the request from the cpudec interrupt request, and loads the data for the next control transfer (out). other na fw when this request is received by the setup token, the hardware generates the cpudec interrupt request for fw. fw decodes the contents of the request from the cpudec interrupt request, and performs the necessary processing. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 672 11.7.1 initialization processing initialization processing is executed in the following two ways. ? initialization of request data register area ? setting of interrupt when the request data register area is initialized, data for the get_xxxx request to which a value is to be automatically returned is written and an endpoint is allocat ed to an interface. in the interrupt settings, the interrupt sources that do not have to be checked can be mask ed by using the uf0imn register (n = 0 to 4). the following flowcharts illus trate the above processing. figure 11-10. initializing re quest data register area start end ep0nka = 1? (uf0e0na) cancels nak response to endpoint0. uf0e0na register = 01h initialization of request data register area uf0modc register = 40h or 00h yes no : see figure 11-11 initialization of request data register area . setting of interface and endpoint uf0e0na register = 00h : see figure 11-12 setting of interface and endpoint . if the total number of bytes of the uf0cien register exceeds 256, set the uf0modc register to 40h. no data has to be written to the uf0cien register. remark n = 0 to 255 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 673 figure 11-11. initialization of request data register area the value of 0xh depends on the power supply method. ? sfpw = 1: self-powered ? sfpw = 0: bus-powered n = 0 to 4, 7, or 8. setting is unnecessary if the target endpoint is not used. if the total number of bytes of the uf0ciea register exceeds 256, set the uf0modc register to 40h. no data has to be written to the uf0ciea register. input the total number of bytes of the uf0ciea register. uf0dstl register = 0xh uf0ensl register = 00h setting of uf0dscl register inputting uf0ddm register inputting uf0ciea register remark m = 0 to 17 a = 0 to 255 figure 11-12. setting of interface and endpoint addif, ifno1, ifno2 = 000: interface number 0 is valid. addif, ifno1, ifno2 = 100: interface numbers 0 and 1 are valid. addif, ifno1, ifno2 = 101: interface numbers 0 to 2 are valid. addif, ifno1, ifno2 = 110: interface numbers 0 to 3 are valid. addif, ifno1, ifno2 = 111: interface numbers 0 to 4 are valid. set a link between the target interface of endpoint n and alternative setting. set 00h if the target endpoint is not used. set interface number(s) and a link with the 5- or 2-series alternative setting. setting of uf0aifn register setting of uf0aas register setting of uf0enim register remark n = 1 to 4, 7, 8 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 674 figure 11-13. setting of interrupt start end mask the interrupt source to avoid issuance of an unnecessary interrupt request (intusbmb). setting of uf0imn register remark n = 0 to 4 m = 0 where n = 0, 1 m = 1 where n = 2, 3 m = 2 where n = 4 chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 675 11.7.2 interrupt servicing the following flowchart illustrates how an interrupt is serviced. figure 11-14. interrupt servicing start end intusb2b = 0? intusb0b = 0? intusbab active yes yes (n = 0, 1) (a = 0 to 2) (m = 2, 3) no no reading uf0is4 register setintc of uf0ic4 register = 0 reading uf0isn register target bit of uf0icn register = 0 reading uf0ism register target bit of uf0icm register = 0 servicing interrupt masking id bit remark ? : processing by hardware the following bits of the uf0isn regist er are automatically cleared by hardwar e when a given condition is satisfied (n = 1 to 4). ? e0indt, e0odt, suces, stg, and cpudec bits of uf0is1 register ? bki2dt, bki1dt, it2dt, and it 1dt bits of uf0is2 register ? bko2fl, bko2dt, bko1fl, and bko1dt bits of uf0is3 register because clearing an interrupt source by the uf0icn register is given a lower priority than setting an interrupt source by hardware, the interrupt source may not be cleared depending on the timing (n = 0 to 4). chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 676 11.7.3 usb main processing usb main processing involves processing usb transaction s. the types of transactions to be processed are as follows. ? fully automatically processed request for control transfer ? automatically processed requests for control transfer (set_configuration, set_interface, set_feature, clear_feature) ? cpudec request for control transfer ? processing for bulk transfer (in) ? processing for bulk transfer (out) ? processing for interrupt transfer (in) processing for endpoint n involves writing or reading for data transfer. the flowchart shown below is for pio. (1) fully automatically processed request for control transfer because the fully automatically processed request for cont rol transfer is executed by hardware, it cannot be referenced by fw. therefore, fw does not have to perform any special processing for this request. (2) automatically processed requests for control transfer (set_configuration, set_interface, set_feature, clear_feature) processing to write a register for automatically processed requests for control transfer, such as set_configuration, set_interface, set_fea ture, and clear_feature requests, is automatically executed by hardware, but an interrupt reques t is issued for recognition on the device side. this processing may be ignored if there is no special processing to be executed. the flowcharts are shown below. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 677 figure 11-15. automatically proces sed requests for control transfer start end clear_feature? set_feature? receiving setup token clear_featur e processing set_feature processing set_configuration? set_configuration processing set_interface? set_interface processing intusb0b/intusb2b active decoding request (n = 0, 1) yes no yes no yes no yes no other automatically processed request? cpudec processing illegal processing illegal processing yes no intusb2b = 1? reading uf0isn register reading uf0is4 register reading uf0set register fw processing for each request yes yes no no clrrq = 1? (uf0is0) setrq = 1? (uf0is0) reading uf0clr register fw processing for each request yes no yes no setint = 1? (uf0is4) end end end automatic processing end setintc = 0 (uf0ic4) fw processing for set_interface : see figure 11-16 clear_feature processing . : see figure 11-17 set_feature processing . : see figure 11-18 set_configuration processing . : see figure 11-19 set_interface processing . remark ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 678 figure 11-16. clear_feature processing set the corresponding bit for the value of 0xh. the ephalt bit of the uf0is0 register is cleared to 0 only when all halt features are cleared. uf0clr register = 0xh clrrq = 1 (uf0is0) haltn = 0 (uf0eps2) clearing uf0dstl register clearing uf0ensl register remarks 1. n = 0 to 4, 7, 8 2. ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 679 figure 11-17. set_feature processing set the corresponding bit for the value of 0xh. the ephalt bit of the uf0is0 register is not set to 1 by setting the uf0dstl register. uf0set register = 0xh setrq = 1 (uf0is0) haltn = 1 (uf0eps2) ephalt = 1 (uf0is0) setting uf0dstl register setting uf0ensl register remarks 1. n = 0 to 4, 7, 8 2. ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 680 figure 11-18. set_configuration processing setcon = 1 (uf0set) setrq = 1 (uf0is0) conf = 1 (uf0mods) setting uf0cnf register remark ? : processing by hardware figure 11-19. set_interface processing setint = 1 (uf0is4) setting uf0ass register setting uf0ifn register remarks 1. n = 0 to 4 2. ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 681 (3) cpudec request for control transfer the cpudec request can be classified into three types of processing: control transfer (write), control transfer (read), and control transfer (without data). control tran sfer (write) indicates a request that uses the out transaction in the data stage (e.g., set_descriptor), and control transfer (read) indicates a request that uses the in transaction in the data stage (e.g., get_des criptor). control transfer (without data) indicates a request that has no data st age (e.g., set_configuration). the flowcharts are shown below. figure 11-20. cpudec request for control transfer (1/12) (a) token phase (1/2) start cpudec = 1? (uf0is1) intusb0b active appropriate interrupt servicing cpudec = 0 (uf0is1) reading uf0isn register protc = 0 (uf0ic1) stgm = 0 (uf0im1) cpudecm = 1 (uf0im1) reading uf0e0st register 8 times decoding fw request yes no g e a remarks 1. n = 0, 1 2. ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 682 figure 11-20. cpudec request for control transfer (2/12) (a) token phase (2/2) supported request? prot = 1? (uf0is1) control transfer (read)? control transfer (write)? reading uf0isn register sndstl = 1 (uf0sds) sndstl = 0 (uf0sds) ep0rc = 1 (uf0fic0) stgm = 1 (uf0im1) cpudecm = 0 (uf0im1) b yes no yes no yes no yes no setup token received? yes no stall handshake response end e c d a in the case of an unsupported request for control transfer (write), clear the fifo because data may be written to the fifo as a result of out transfer before the stall response is made. it is judged whether the request decoded by the device is supported. request that uses control transfer (in), such as get_descriptor string request that uses control transfer (out), such as set_descriptor string remarks 1. n = 0, 1 2. ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 683 figure 11-20. cpudec request for control transfer (3/12) (b) control transfer (read) (1/4) in token received? e0in = 1? (uf0is1) transmitting nak e0in = 1 (uf0is1) writing uf0e0w register e0inm = 1 (uf0im1) yes no yes no b if return data greater than the fifo size exists, it is divided into fifo size units and sequentially written, starting from the lowest data byte. intusb0b active reading uf0isn register i f illegal processing remarks 1. n = 0, 1 2. ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 684 figure 11-20. cpudec request for control transfer (4/12) (b) control transfer (read) (2/4) fifo full? e0ded = 1 (uf0dend) ep0nkw = 1 (uf0e0n) transmitting data of uf0e0w register yes no in token received? yes no prot = 1? (uf0is1) no yes g h ack received? yes no ep0wc = 1 (uf0fic0) f remark ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 685 figure 11-20. cpudec request for control transfer (5/12) (b) control transfer (read) (3/4) i j no transmit data? e0indt = 1 (uf0is1) ep0nkw = 0 (uf0e0n) e0indtc = 0 (uf0ic1) stg = 1 (uf0is1) yes yes no h intusb0b active reading uf0isn register e0indt = 1? (uf0is1) no yes data of null packet received? no illegal processing remarks 1. n = 0, 1 2. ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 686 figure 11-20. cpudec request for control transfer (6/12) (b) control transfer (read) (4/4) intusb0b active reading uf0isn register reading uf0isn register transmitting ack intusb0b active cpudecm = 0 (uf0im1) e0inm = 0 (uf0im1) yes stg = 1? (uf0is1) no yes suces = 1? (uf0is1) no stgm = 1 (uf0im1) suces = 1 (uf0is1) sucesc = 0 (uf0ic1) e0inc = 0 (uf0ic1) end j illegal processing illegal processing remarks 1. n = 0, 1 2. ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 687 figure 11-20. cpudec request for control transfer (7/12) (c) control transfer (write) (1/4) clearing uf0e0r register c k g intusb0b active yes normal reception? no ep0rc = 1 (uf0fic0) no prot = 1? (uf0is1) yes yes out token received? no writing uf0e0r register e0odt = 1 (uf0is1) ep0r = 1 (uf0eps0) ep0nkr = 1 (uf0e0n) reading uf0isn register remarks 1. n = 0, 1 2. ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 688 figure 11-20. cpudec request for control transfer (8/12) (c) control transfer (write) (2/4) c out token received? no yes l e0odt = 0 (uf0is1) ep0r = 0 (uf0eps0) ep0nkr = 0 (uf0e0n) yes in token received? no yes e0odt = 1? (uf0is1) no reading uf0e0r register data length = data length ? 1 no data length other than 0? yes updating data length of uf0e0l register updating data length of uf0e0l register uf0e0l register data is read up to the value read by the uf0e0r register. k illegal processing remark ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 689 figure 11-20. cpudec request for control transfer (9/12) (c) control transfer (write) (3/4) l intusb0b active yes stg = 1? (uf0is1) no stg = 1 (uf0is1) e0in = 1 (uf0is1) reading uf0isn register g clearing read data no prot = 1? (uf0is1) yes request processing ep0wc = 1 (uf0fic0) e0ded = 1 (uf0dend) m illegal processing remarks 1. n = 0, 1 2. ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 690 figure 11-20. cpudec request for control transfer (10/12) (c) control transfer (write) (4/4) yes yes in token received? no yes suces = 1? (uf0is1) no intusb0b active transmitting data of null packet reading uf0isn register suces = 1 (uf0is1) e0indt = 1 (uf0is1) sucesc = 0 (uf0ic1) e0indtc = 0 (uf0ic1) cpudecm = 0 (uf0im1) stgm = 1 (uf0im1) e0inm = 1 (uf0im1) ack received? no end m illegal processing remarks 1. n = 0, 1 2. ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 691 figure 11-20. cpudec request for control transfer (11/12) (d) control transfer (without data stage) (1/2) d yes stg = 1? (uf0is1) no yes in token received? no e0ded = 1 (uf0dend) e0in = 1 (uf0is1) stg = 1 (uf0is1) intusb0b active reading uf0isn register ep0wc = 1 (uf0fic0) g request processing aborted no prot = 1? (uf0is1) yes in token of status phase n illegal processing remarks 1. n = 0, 1 2. ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 692 figure 11-20. cpudec request for control transfer (12/12) (d) control transfer (without data stage) (2/2) yes yes in token received? no yes suces = 1? (uf0is1) no intusb0b active transmitting data of null packet reading uf0isn register suces = 1 (uf0is1) e0indt = 1 (uf0is1) sucesc = 0 (uf0ic1) e0inc = 0 (uf0ic1) e0indtc = 0 (uf0ic1) e0inm = 1 (uf0im1) cpudecm = 0 (uf0im1) e0inm = 1 (uf0im1) stgm = 1 (uf0im1) ack received? no end request processing n illegal processing remarks 1. n = 0, 1 2. ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 693 (4) processing for bulk transfer (in) bulk transfer (in) is allocated to endpoint1 and e ndpoint3. the flowchart shown below illustrates how endpoint1 is controlled. endpoint3 can also be controlled in the same sequence. to use this flowchart as the control flow of endpoint3, therefore, read the bit names of endpoint1 in the flowchart as those of endpoint3. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 694 figure 11-21. processing for bulk transfer (in) (endpoint1) yes bki1in = 1? (uf0is2) no yes bki1dt = 1? (uf0is2) no yes no transmit data? no yes in token received? no parallel processing by hardware end end start bki1in = 1 (uf0is2) returning nak intusb1b active bki1ded = 1 (uf0dend) no yes bki1cc = 1 (uf0fic0) intusb1b active reading uf0isn register bki1inc = 0 (uf0ic2) bki1dtc = 0 (uf0ic2) data error? reading uf0isn register writing uf0bi1 register bki1nk = 1 (uf0en) bki1dt = 1 (uf0is2) bki1inm = 1 (uf0im2) if return data greater than the fifo size exists, it is divided into fifo size units and sequentially written, starting from the lowest data byte. the timing of the bit value varies depending on the situation on the sie side. illegal processing illegal processing : see figure 11-22 parallel processing by hardware . fifo full? no yes remarks 1. n = 2, 3 2. ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 695 figure 11-22. parallel processing by hardware yes yes in token received? no transmitting data of uf0bi1 register ack received? no yes no transmit data? no bki1nk = 0 (uf0en) remark ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 696 (5) processing for bulk transfer (out) bulk transfer (out) is allocated to endpoint2 and en dpoint4. the flowchart shown below illustrates how endpoint2 is controlled. endpoint4 can also be controlled in the same sequence. to use this flowchart as the control flow of endpoint4, therefore, read the bit names of endpoint2 in the flowchart as those of endpoint4. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 697 figure 11-23. normal processing for bulk transfer (out) (endpoint2) yes out token received? no yes bko1dt = 1? (uf0is3) no yes data length = 0? no no out token received? yes end start writing uf0bo1 register bko1dt = 1 (uf0is3) bkout1 = 1 (uf0eps0) clearing uf0bo1 register yes no normal reception? intusb1b active reading uf0isn register bko1dt = 0 (uf0is3) bkout1 = 0 (uf0eps0) updating data length of uf0bo1l register reading uf0bo1 register data length = data length ? 1 updating data length of uf0bo1 register no data length other than 0? yes uf0bo1 register data is read up to the value read by the uf0bo1l register. illegal processing illegal processing remarks 1. n = 2, 3 2. ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 698 during bulk transfer (out), more data may be transmi tted from the host than expected by the system. endpoint2 and endpoint4 for bulk transfe r (out) of the v850e/me2 consist of two 64-byte buffers so that nak responses are suppressed as much as possible and data can be read from the cpu side even while the bus side is being accessed as the transfer rate of the usb bus increases. consequently, if the host sends more data than expected by the system, up to 128 bytes of extra data may be automatically received in the worst case. in this case, change the cont rol flow from that of the normal processing of endpoint2 and endpoint4 to the flow illustrated below when the quantity of data expected by the system has decreased to two packets. this flowchart illustrates how endpoint2 is controlled. endpoint4 can also be controlled in the same sequence. to use this flowchart as the control flow of endpoint 4, therefore, read the bit names of endpoint2 in the flowchart as those of endpoint4. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 699 figure 11-24. processing if more data than expect ed by system is transm itted (endpoint2) (1/2) yes out token received? no yes out token received? no yes bko1fl = 1? (uf0is3) no start writing uf0bo1 register bko1dt = 1 (uf0is3) bkout1 = 1 (uf0eps0) intusb1b active clearing uf0bo1 register yes normal reception? no writing uf0bo1 register reading uf0isn register bko1nkm = 1 (uf0enm) bko1fl = 1 (uf0is3) bko1nk = 1 (uf0en) clearing uf0bo1 register yes normal reception? no i updating data length of uf0bo1l register bko1nk = 1 (uf0en) illegal processing remarks 1. n = 2, 3 2. ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 700 figure 11-24. processing if more data than expect ed by system is transm itted (endpoint2) (2/2) yes out token received? no yes next system sequence? no bko1nak = 1 (uf0is3) nak response intusb1b active bko1nkm = 0 (uf0enm) bko1nk = 0 (uf0en) expected system sequence processing expected processing such as endpoint stall bko1nkm = 0 (uf0enm) bko1nk = 0 (uf0en) bko1nakc = 0 (uf0ic3) yes bko1nak = 1? (uf0is3) no end end reading uf0bo1 register bko1fl = 0 (uf0is3) reading uf0bo1 register data length = data length ? 1 no data length other than 0? yes uf0bo1 register data is read up to the value read by the uf0bo1l register. uf0bo1 register data is read up to the value read by the uf0bo1l register. updating data length of uf0bo1l register bko1dt= 0 (uf0is3) bkout1 = 0 (uf0eps0) data length = data length ? 1 no data length other than 0? yes i illegal processing remark ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 701 (6) processing for interrupt transfer (in) interrupt transfer (in) is allocated to endpoint7 and endpoint8. the flowchart sh own below illustrates how endpoint7 is controlled. endpoint8 can also be controlled in the same sequence. to use this flowchart as the control flow of endpoint8, therefore, read the bit names of endpoint7 in the flowchart as those of endpoint8. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 702 figure 11-25. processing for interrupt transfer (in) (endpoint7) reading uf0eps0 register writing uf0int1 register transmitting data of uf0int1 register it1nk = 1 (uf0en) fif o full? no no data error? yes it1dend = 1 (uf0dend) itr1c = 1 (uf0fic0) yes in token received? no yes it1dt = 1? (uf0is2) no yes ac k received? no yes yes it1 = 0? (uf0eps0) no end start it1dt = 1 (uf0is2) it1 = 0 (uf0eps0) it1nk = 0 (uf0en) intusb1b active reading uf0isn register it1dtc = 0 (uf0ic2) yes no transmit data? no illegal processing remarks 1. n = 2, 3 2. ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 703 11.7.4 suspend/resume processing how suspend/resume processing is performed differs d epending on the configurat ion of the system. one example is given below. figure 11-26. example of suspend/resume processing (1/3) (a) example of suspend processing rsuspd = 1 (uf0is0) rsum = 1 (uf0eps1) yes suspend detected? no yes rsuspd = 1? (uf0is0) no yes rsum = 1? (uf0eps1) no start end intusb0b active reading uf0isn register reading uf0eps1 register fw suspend processing rsuspdc = 0 (uf0ic0) illegal processing illegal processing remarks 1. n = 0, 1 2. ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 704 figure 11-26. example of suspend/resume processing (2/3) (b) example of resume processing rsuspd = 1 (uf0is0) rsum = 0 (uf0eps1) yes resume detected? no yes rsuspd = 1? (uf0is0) no yes rsum = 0? (uf0eps1) no start end intusb0b active reading uf0isn register reading uf0eps1 register fw resume processing rsuspdc = 0 (uf0ic0) illegal processing illegal processing remarks 1. n = 0, 1 2. ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 705 figure 11-26. example of suspend/resume processing (3/3) (c) example of resume processing (when supply of usb clock to usbf is stopped) intrsum active yes resum e detected? no start end executing interrupt servicing supplying usb clock fw resum e processing remark ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 706 11.7.5 processing after power application the processing to be performed after power application differs depending on the co nfiguration of the system. one example is given below. figure 11-27. example of processing after power application/power failure (1/3) (a) processing after power application (1/2) yes resume detected? no start start controlling port note 2 pull-up processing of d+ inactive note 1 pull-up processing of d+ active note 1 connection controlling port note 2 busrst = 1 (uf0is0) dflt = 1 (uf0mods) initialization of request data register area initialization of request data register area : see figure 11-11 initialization of request data register area . : see figure 11-11 initialization of request data register area . (a) notes 1. use one general-purpose port pin for the signal that controls switching of the pull-up resistor of the usb bus. 2. the input mode or control mode of the general-purpose port pin allocated in note 1 may be selected as the default value. note the active level of pull-up processing of d+ on power application. remark ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 707 figure 11-27. example of processing after power application/power failure (2/3) (a) processing after power application (2/2) receiving get_descriptor device request mpack = 1 (uf0mods) receiving set_address request setting uf0adrs register receiving set_configuration 1 request receiving set_interface request processing continues setcon = 1 (uf0set) setrq = 1 (uf0is0) conf = 1 (uf0mods) uf0cnf register = 03h valid endpoint = data0 setint = 1 (uf0is4) setting of uf0ass register setting of uf0ifm register valid endpoint = data0 (a) remarks 1. m = 0 to 4 2. ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 708 figure 11-27. example of processing after power application/power failure (3/3) (b) processing on power failure yes intpxx active note ? no interrupt servicing processing such as clearing fifo or mrst = 1 (uf0gpr) start end power failure note intpxx means an external interrupt pin of the v8 50e/me2 (intp10, intp11, intp21 to intp25, intp50 to intp52, intp65 to intp67, intpd0 to intpd15, intpl0, intpl1, intpc00, intpc01, intpc10, intpc11, intpc20, intpc21, intpc30, and intpc31). allocate one external interrupt pin to the following applications. (a) detecting disconnection of the connector in t he case of self-powered mode (sfpw bit of uf0dstl register = 1). in this case, monitor the vdd line of the usb connector, and input the result to the external interrupt pin at the edge. for the noise elimination time, see table 14-1 noise elimination time of interrupt input pins and table 14-3 noise elimination ti me of timer c and timer enc1 input pins . (b) detecting turning off power from a hub chip when the device is mounted on the same board as a hub. remark ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 709 11.7.6 receiving data for bulk transfer (out) in dma mode bulk transfer (out) is allocated to endpoint2 and endpoint4. the flowchart shown below illustrates how endpoint2 is controlled when dma is used. endpoint 4 can also be controlled in the same sequence. to use this flowchart as the control flow of endpoint4, therefore, read the bit names of endpoint2 in the flowchart as those of endpoint4. the control flowchart shown below illustrates how remaining data is read by the cpu. if data for bulk transfer (out) has been correctly received by setting the dqbo1ms bit of the uf0idr register to 1, the dma request signal for endpoint2, instead of an interrupt request (int usb1b), becomes active. this dma request signal for endpoint2 operates according to the setting of the moden bit of the uf0i dr register (n = 0, 1). if all the data stored in the uf0bo1 register has been read by dma, the dma request signal for endpoint2 becomes inactive. in this status, if data for the next bulk trans fer (out) has been correctly received, the dma request signal for endpoint2 becomes active again. if the data for bulk transfer (out) that has been received is equal to or less than the fifo size, a short interrupt request is issued and the usbsp2b signal becomes active, as soon as reading the data by dma is completed. as a result, the dqbo1ms bit of the uf0idr register is cleared to 0, and the dma request signal for endpoint2 becomes inactive. to read data by dm a again, set the dqbo1ms bit to 1 again. if dma is completed by the dma end signal for endpoint2, the dqbo1m s bit of the uf0idr register is cleared to 0, and the dma request signal for endpoint2 becomes inactive. at the same time, the dma_end interrupt request is issued. if data remains in the uf0bo1 register at this time, dma can be started again by setti ng the dqbo1ms bit of the uf0idr register again. however, the data for bulk transfer (out) is always equal to or less than the fifo size. consequently, a short interrupt request is issued, the us bsp2b signal becomes active, the dqbo1ms bit is cleared, and the dma request signal for endpoint2 becomes i nactive, as soon as the data is read by dma. cautions 1. the dma request signal for endpoint n (n = 2, 4) becomes active in the demand mode (mode1 and mode0 bits of the uf0idr regist er = 10), as long as there is data to be transferred. 2. the dma request signal for endpoint n (n = 2, 4) becomes active in the single mode (mode1 and mode0 bits of the uf0idr register = 0x (x: don ?t care)) if there is data to be transferred, but this signal becomes inactive each time one by te has been transferred. this operation is repeated until there is no more data to be transferred. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 710 figure 11-28. dma processing by bulk transfer (out) (1/3) yes how many times is data length? no start no tc signal received? yes clearing uf0bo1 register yes normal reception? no setting of modex (uf0idr) dqbo1ms = 1 (uf0idr) bko1dt = 1 (uf0is3) bkout1 = 1 (uf0eps0) dqe2 = 1 (uf0dms0) bko1dt = 0 (uf0is3) bkout1 = 0 (uf0eps0) dqe2 = 0 (uf0dms0) writing uf0bo1 register dma request for endpoint2 active reading all data in uf0bo1 register by dma yes out token received? no (4) (3) no maxpacket? yes mode1, mode0 = 1 0: demand mode mode1, mode0 = 0 x: single mode (x = don?t care) uf0bo1 register data is read up to the value read by the uf0bo1l register. (1) (2) remark ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 711 figure 11-28. dma processing by bulk transfer (out) (2/3) yes short = 1? (uf0is0) no intusb0b active dma request for endpoint2 inactive reading uf0isn register reading uf0dmsn register yes dspe2 = 1? (uf0dms1) no shortc = 0 (uf0ic0) correct processing dede2 = 1 (uf0dms1) short = 1 (uf0is0) dqbo1ms = 0 (uf0idr) (2) (3) illegal processing illegal processing remarks 1. n = 0, 1 2. ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 712 figure 11-28. dma processing by bulk transfer (out) (3/3) (1) (4) intusb0b active dma request for endpoint2 inactive yes dmaed = 1? (uf0is0) no yes dede2 = 1? (uf0dms1) no yes bko1dt = 1? (uf0is3) no dqe2 = 0 (uf0dms0) dede2 = 1 (uf0dms1) dmaed = 1 (uf0is0) dqbo1ms = 0 (uf0idr) reading uf0isn register reading uf0dmsn register reading uf0ism register updating data length of uf0bo1l register reading uf0bo1 register data length = data length ? 1 no data length other than 0? yes uf0bo1 register data is read up to the value read by the uf0bo1l register. bko1dt = 0 (uf0is3) bkout1 = 0 (uf0eps0) dmaedc = 0 (uf0ic0) illegal processing illegal processing remarks 1. n = 0, 1 m = 2, 3 2. ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 713 11.7.7 transmitting data for bulk transfer (in) in dma mode bulk transfer (in) is allocated to endpoint1 and endpoint3 . the flowchart shown below illustrates how endpoint1 is controlled when dma is used. endpoint3 can also be controlle d in the same sequence. to use this flowchart as the control flow of endpoint3, therefore, read the bit names of endpoint1 in the flowchart as those of endpoint3. if data for bulk transfer (in) can be written by setting the dqbi1ms bit of the uf0idr register to 1, the dma request signal for endpoint1, instead of an interrupt requ est (intusb1b), becomes active. this dma request signal for endpoint1 operates according to the setting of the moden bi t of the uf0idr register (n = 0, 1). if all the data that can be written to the uf0bi1 register has been writt en by dma, the dma request signal for endpoint1 becomes inactive. in this status, the toggle oper ation of the fifo takes plac e and, if data for bulk transfer (in) can be written, the dma request signal for endpoint1 becomes active again. the automatic toggle operation of the fifo is not executed even if the fifo has become fu ll as a result of dma transfer, unless the bki1t bit of t he uf0dend register is set to 1. therefore, be sure to set the bki1ded bit of the uf0dend register to 1 to transfer data. if dma is completed by the dma end signal for endpoint1, the dqbi1m s bit of the uf0idr register is cleared to 0, and the dma request signal for endpoint1 becomes inactive. at the same time, the dma_end interrupt request is issued. to transmit a short packet at this time when the fifo is not full, set the bki1ded bit of the uf0dend register to 1. cautions 1. the dma request signal for endpoint n (n = 1, 3) becomes active in the demand mode (mode1 and mode0 bits of the uf0idr register = 10), as long as data can be transferred. 2. the dma request signal for endpoint n (n = 1, 3) becomes active in the single mode (mode1 and mode0 bits of the uf0idr register = 0x (x: don? t care)) if data can be transferred, but this signal becomes inactive each time one byte has b een transferred. this operation is repeated until there is no more da ta to be transferred. chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 714 figure 11-29. dma processing by bulk transfer (in) (1/4) start setting of modex (uf0idr) dqbi1ms = 1 (uf0idr) dqe1 = 1 (uf0dms0) no fifo on cpu side full? yes mode1, mode0 = 1 0: demand mode mode1, mode0 = 0 x: single mode (x = don?t care) yes fifo full? no no tc signal received? yes dma request for endpoint1 active writing uf0bi1 register by dma if return data greater than the fifo size exists, it is divided into fifo size units, and sequentially written, starting from the lowest data byte. (3) (5) (1) yes bki1t = 1? (uf0dend) no (2) remark ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 715 figure 11-29. dma processing by bulk transfer (in) (2/4) end bki1nk = 1 (uf0en) note bki1dt = 1 (uf0is2) note dqe1 = 0 (uf0dms0) dma request for endpoint1 inactive parallel processing by hardware (3) (2) : see figure 11-22 parallel processing by hardware . note the timing of the bit value changes depending on the status on the sie side. remark ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 716 figure 11-29. dma processing by bulk transfer (in) (3/4) (1) intusb0b active dma request for endpoint1 inactive bki1nk = 1 (uf0en) note bki1dt = 1 (uf0is2) note dqe1 = 0 (uf0dms0) dede1 = 1 (uf0dms1) dmaed = 1 (uf0is0) dqbi1ms = 0 (uf0idr) dqe1 = 0 (uf0dms0) dede1 = 1 (uf0dms1) dmaed = 1 (uf0is0) dqbi1ms = 0 (uf0idr) yes dmaed = 1? (uf0is0) no yes dede1 = 1? (uf0dms1) no no yes yes bki1t = 1? (uf0dend) fifo full? no reading uf0isn register reading uf0dmsn register (4) illegal processing illegal processing note the timing of the bit value changes depending on the status on the sie side. remarks 1. n = 0, 1 2. ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 717 figure 11-29. dma processing by bulk transfer (in) (4/4) (5) end dmaedc = 0 (uf0ic0) (5) no yes yes bki1t = 1? (uf0dend) fifo full? no bki1ded = 1 (uf0dend) bki1nk = 1 (uf0en) note bki1dt = 1 (uf0is2) note bki1cc = 1 (uf0fic0) dmaedc = 0 (uf0ic0) no data error? yes (4) parallel processing by hardware : see figure 11-22 parallel processing by hardware . note the timing of the bit value changes depending on the status on the sie side. remark ? : processing by hardware chapter 11 usb function controller (usbf) user?s manual u16031ej3v0ud 718 11.7.8 usb connection example figure 11-30. usb connection example v850e/me2 uv dd ic1 ic2 uv dd p50 intp51 udp udm d+ vbus d ? ? ? ? 719 user?s manual u16031ej3v0ud chapter 12 a/d converter 12.1 features ? analog input: 8 channels ? 10-bit a/d converter ? on-chip a/d conversion result register (adcr0 to adcr7) 10 bits 8 ? a/d conversion trigger mode a/d trigger mode timer trigger mode external trigger mode ? successive approximation method chapter 12 a/d converter 720 user?s manual u16031ej3v0ud 12.2 configuration the a/d converter of the v850e/me2 adopts the successive ap proximation method, and uses a/d converter mode registers 0, 1, 2 (adm0, adm1, adm2 ), and the a/d conversion result regi ster (adcr0 to adcr7) to perform a/d conversion operations. (1) input circuit the input circuit selects the analog input (ani0 to an i7) according to the mode set by the adm0, adm1, and adm2 registers. (2) c-array holds the charge of the differential voltage between the voltage input from the analog input pins (ani0 to ani7) and the reference voltage (1/2 av dd ), and redistributes the sampled charges. (3) c-dummy this block holds the reference voltage (1/2 av dd ) and assigns the reference of the comparator input. (4) voltage comparator the voltage comparator compares the c-array comparison potential with the c-dummy reference potential. (5) a/d conversion result register n (adcrn), a/d conversion result register nh (adcrnh) adcrn is a 10-bit register that hold s a/d conversion results. each ti me a/d conversion is completed, the conversion results are loaded from the su ccessive approximation register (sar). reset input makes this register undefined. (6) ani0 to ani7 pins these are 8-channel analog input pins for the a/d c onverter. they input the analog signals to be a/d converted. caution make sure that the voltag es input to ani0 to ani7 do not exceed the rated values. if a voltage higher than av dd or lower than av ss (even within the range of the absolute maximum ratings) is input to a channel, the c onversion value of the ch annel is undefined, and the conversion values of the othe r channels may also be affected. (7) av refm and av refp pins this is the pin for inputting the reference voltage of the a/ d converter. it converts signals input to the ani0 to ani7 pins to digital signals based on the voltage applied between av refm and av refp . (8) av ss pin this is the ground pin of the a/d c onverter. always use this pin at t he same potential as that of the ev ss pin even when the a/d converter is not used. (9) av dd pin this is the analog power supply pin of the a/d converter. always use this pin at the same potential as that of the ev dd pin even when the a/d converter is not used. chapter 12 a/d converter 721 user?s manual u16031ej3v0ud figure 12-1. block diag ram of a/d converter comparator av refm av refp av dd av ss intad c-dummy c-array controller f x /8 adtrg adtrg ttrg successive approximation register (sar) a/d conversion result register (adcrn, adcrnh) ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 intccc40 intccc41 intccc50 intccc51 trigger selector edge detection input circuit remarks 1. f x : main clock 2. n = 0 to 7 cautions 1. if there is noise at the analog input pins (ani0 to ani7) or at the reference voltage input pin (av refp , av refm ), that noise may generate an illegal conversion result. software processing will be needed to avoid a negative effect on the system from this illegal conversion result. an example of this softwar e processing is shown below. ? take the average result of a number of a/d conversions and use that as the a/d conversion result. ? execute a number of a/d conversions con secutively and use those results, omitting any exceptional results that may have been obtained. 2. do not apply a voltage outside the av refm to av refp range to the pins that are used as a/d converter input pins. chapter 12 a/d converter 722 user?s manual u16031ej3v0ud 12.3 control registers (1) a/d converter mode register 0 (adm0) the adm0 register is an 8-bit regist er that specifies the operation mode, and executes conversion operations. this register can be read or written in 8-bit or 1-bit units . however, bit 6 can only be read. writing this bit is ignored. cautions 1. when the adce bit is 1 in the timer trigger mode and external trigger mode, the trigger signal standby state is set. to clear the adce bit, write 0 or reset. in the a/d trigger mode, the conversion trigge r is set by writing 1 to the adce bit. after the operation, when the mode is changed to the timer trigger mode or external trigger mode without clearing the adce bit, the trigge r input standby state is set immediately after changing the register. 2. changing the setting of the bs and ms bits is prohibited while a/d conversion is enabled (adce bit = 1). 3. when data is written to the adm0 register during an a/d conversion operation, the conversion operation is initia lized and conversion is executed from the beginning. adce adm0 adcs 5 bs 4 ms 3 0 2 0 1 0 0 0 address fffff200h after reset 00h <6> <7> bit position bit name function 7 adce enables or disables a/d conversion operation. 0: disabled 1: enabled 6 adcs indicates the status of a/d converter. this bit is read only. 0: stopped 1: operating 5 bs specifies buffer mode in the select mode. 0: 1-buffer mode 1: 4-buffer mode 4 ms specifies operation mode of a/d converter. 0: scan mode 1: select mode chapter 12 a/d converter 723 user?s manual u16031ej3v0ud (2) a/d converter mode register 1 (adm1) the adm1 register is an 8-bit register that spec ifies the conversion operation time and trigger mode. this register can be read or written in 8-bit or 1-bit units. cautions 1. changing the setting of the ega1, ega0, and fr3 to fr0 bits is prohibited while a/d conversion is enabled (adce bi t = 1 in the adm0 register). 2. when data is written to the adm1 register during an a/d conversion operation, the conversion operation is initia lized and conversion is executed from the beginning. 7 ega1 adm1 6 ega0 5 trg1 4 trg0 3 fr3 2 fr2 1 fr1 0 fr0 address fffff201h after reset 00h bit position bit name function specify valid edge of adtrg. ega1 ega0 adtrg valid edge specification 0 0 no edge detected (does not operate as external trigger) 0 1 falling edge detected 1 0 rising edge detected 1 1 both edges detected 7, 6 ega1, ega0 specify the trigger mode. trg1 trg0 trigger mode 0 0 a/d trigger mode 0 1 timer trigger mode 1 0 external trigger mode 1 1 setting prohibited 5, 4 trg1, trg0 remark sets a/d conversion operation time by using bits fr3 to fr0. for details, see table 12-1 . chapter 12 a/d converter 724 user?s manual u16031ej3v0ud table 12-1. setting of a/d conversion operation time conversion operation time note 1 fr3 fr2 fr1 fr0 number of conversion clocks f x = 150 mhz f x = 133 mhz f x = 100 mhz f x = 80 mhz a/d stabilization time note 2 0 0 0 0 128 setting prohibited setting prohibit ed setting prohibited setting prohibited 64/f x 0 0 0 1 256 setting prohibited setting prohibited 2.56 s 3.20 s 128/f x 0 0 1 0 384 2.56 s 2.89 s 3.84 s 4.80 s 160/f x 0 0 1 1 512 3.42 s 3.85 s 5.12 s 6.40 s 160/f x 0 1 0 0 640 4.27 s 4.82 s 6.40 s 8.00 s 160/f x 0 1 0 1 768 5.12 s 5.78 s 7.68 s 9.60 s 160/f x 0 1 1 0 896 5.98 s 6.74 s 8.96 s setting prohibited 160/f x 0 1 1 1 1,024 6.83 s 7.70 s setting prohibited setting prohibited 160/f x 1 0 0 0 1,152 7.68 s 8.67 s setting prohibited setting prohibited 160/f x 1 0 0 1 1,280 8.54 s 9.63 s setting prohibited setting prohibited 160/f x 1 0 1 0 1,408 9.39 s setting prohibited setting prohibited setting prohibited 160/f x 1 0 1 1 1,536 setting prohibited setting prohi bited setting prohibited setting prohibited ? 1 1 0 0 1,664 setting prohibited setting prohi bited setting prohibited setting prohibited ? 1 1 0 1 1,792 setting prohibited setting prohi bited setting prohibited setting prohibited ? 1 1 1 0 1,920 setting prohibited setting prohi bited setting prohibited setting prohibited ? 1 1 1 1 2,048 setting prohibited setting prohi bited setting prohibited setting prohibited ? notes 1. set the conversion operation time in the range of 2 to 10 s (target value). 2. after the adce bit is set to ?1? from ?0? to secure the stabilization time of the a/d converter, conversion is started after the a/d stabilization time has elapsed only before the first a/d conversion is executed. cautions 1. do not change the set value of th e a/d conversion time (fr3 to fr0 bits) during an a/d conversion operation (adce bit = 1). to ch ange the value, clear the adce bit to 0. 2. when the trigger mode (trg1 and tgr0 bits) is changed midway, a/d conversion can be started immediately without havi ng to secure the a/d stabilizat ion time by re-setting the adce bit to ?1?. remark f x : main clock chapter 12 a/d converter 725 user?s manual u16031ej3v0ud (3) a/d converter mode register 2 (adm2) the adm2 register is an 8-bit register that specif ies the analog input pin of the a/d converter. this register can be read or written in 8-bit or 1-bit units. cautions 1. if a channel for which no analog input pin exists is specified, the result of a/d conversion is undefined. 2. changing the setting of the anis2 to anis 0 bits is prohibited while a/d conversion is enabled (adce bit = 1 in the adm0 register). 3. when data is written to the adm2 register during an a/d conversion operation, the conversion operation is initia lized and conversion is executed from the beginning. 7 0 adm2 6 0 5 0 4 0 3 0 2 anis2 1 anis1 anis0 address fffff202h after reset 00h 0 bit position bit name function specify the analog input pin for a/d conversion. specification of pin for a/d conversion anis2 anis1 anis0 select mode scan mode 0 0 0 ani0 ani0 0 0 1 ani1 ani0, ani1 0 1 0 ani2 ani0 to ani2 0 1 1 ani3 ani0 to ani3 1 0 0 ani4 ani0 to ani4 1 0 1 ani5 ani0 to ani5 1 1 0 ani6 ani0 to ani6 1 1 1 ani7 ani0 to ani7 2 to 0 anis2 to anis0 chapter 12 a/d converter 726 user?s manual u16031ej3v0ud (4) adc trigger select register (adts) this is an 8-bit register that specifies the ti mer trigger signal in the timer trigger mode. this register can be read or written in 8-bit units. be sure to clear bits 7 to 4 to 0. if they are set to 1, the operation is not guaranteed. caution stop the a/d conversion operation (by clear ing the adce bit of the adm0 register to 0) before changing the setting of the adts regist er. the operation is not guaranteed if the setting of the adts register is changed while a/d conversion is enabled (adce bit = 1). 7 0 adts 6 0 5 0 4 0 <3> tms3 <2> tms2 <1> tms1 tms0 address fffff220h after reset 00h <0> bit position bit name function 3 tms3 controls connection of a timer trigger signal (intccc51). 0: timer trigger of adc is invalid. 1: timer trigger of adc is valid. 2 tms2 controls connection of a timer trigger signal (intccc50). 0: timer trigger of adc is invalid. 1: timer trigger of adc is valid. 1 tms1 controls connection of a timer trigger signal (intccc41). 0: timer trigger of adc is invalid. 1: timer trigger of adc is valid. 0 tms0 controls connection of a timer trigger signal (intccc40). 0: timer trigger of adc is invalid. 1: timer trigger of adc is valid. chapter 12 a/d converter 727 user?s manual u16031ej3v0ud (5) a/d conversion result registers 0 to 7, 0h to 7h (adcr0 to adcr7, adcr0h to adcr7h) the adcrn register is a 10-bit regist er holding the a/d conversion results. there are eight 10-bit registers. these registers are read-only, in 16-bit or 8-bit units. during 16-bit access, the adcrn register is specified, and during higher 8-bit access, the adcrnh register is specified (n = 0 to 7). when reading the 10-bit data of the a/ d conversion results from the adcrn register, only the higher 10 bits are valid and the lower 6 bits are always read as 0. 15 adn9 14 adn8 13 adn7 12 adn6 11 adn5 10 adn4 9 adn3 8 adn2 7 adn1 6 adn0 5 0 4 0 3 0 2 0 1 0 0 0 adcrn address fffff210h to fffff21eh after reset undefined 7 adn9 6 adn8 5 adn7 4 adn6 3 adn5 2 adn4 1 adn3 0 adn2 adcrnh address fffff211h to fffff21fh after reset undefined remark n = 0 to 7 the correspondence between each analog input pi n and the adcrn register is shown below. adcrn register analog input pin select 1 buffer mode/ scan mode select 4 buffer mode ani0 adcr0, adcr0h ani1 adcr1, adcr1h ani2 adcr2, adcr2h ani3 adcr3, adcr3h adcr0 to adcr3, adcr0h to adcr3h ani4 adcr4, adcr4h ani5 adcr5, adcr5h ani6 adcr6, adcr6h ani7 adcr7, adcr7h adcr4 to adcr7, adcr4h to adcr7h chapter 12 a/d converter 728 user?s manual u16031ej3v0ud the relationship between the analog voltage input to the analog input pins (ani0 to ani7) and the a/d conversion result (of the a/d conversion re sult register n (adcrn)) is as follows: sar 0.5) 1,024 av v ( int ref in + = adcr note = sar 64 or, (sar ? 0.5) 1,024 av ref v in < (sar + 0.5) 1,024 av ref int( ): function that returns the integer of the value in ( ) v in : analog input voltage av ref : av refm , av refp pin voltage adcr: value of a/d conversion result register n (adcrn) note the lower 6 bits of the adcr n registers are fixed to 0. figure 12-2 shows the relationship between the anal og input voltage and the a/d conversion results. figure 12-2. relationship between analog input voltage and a/d conversion results 1,023 1,022 1,021 3 2 1 0 sar adcrn 1 2,048 1 1,024 3 2,048 2 1,024 5 2,048 3 1,024 2,043 2,048 1,022 1,024 2,045 2,048 1,023 1,024 2,047 2,048 1 input voltage/av refp , av refm a/d conversion results (adcrn) ffc0h ff80h ff40h 00c0h 0080h 0040h 0000h remark n = 0 to 7 chapter 12 a/d converter 729 user?s manual u16031ej3v0ud 12.4 operation 12.4.1 basic operation a/d conversion is executed by the following procedure. (1) the selection of the analog input and specification of the operation mode, trigger mode, etc. should be specified using the admn register note 1 (n = 0 to 2). when the adce bit of the adm0 register is set to 1, a/ d conversion starts in the a/d trigger mode. in the timer trigger mode and external trig ger mode, the trigger standby state note 2 is set. (2) when a/d conversion is started, the c array voltage on the analog input side and the c array voltage on the reference side are compared by the comparator. (3) when the comparison of the 10 bits ends, the conver sion results are stored in the adcrn register. when a/d conversion has been performed the specified number of times, the a/ d conversion end interrupt (intad) is generated (n = 0 to 7). notes 1. if the setting of the admn register (n = 0 to 2) is changed during a/d conversion, the operation immediately before is stopped, and the result of the conversion is not stored in the adcrn register (n = 0 to 7). the a/d conversion operation is then initia lized, and conversion is executed from the beginning again. 2. during the timer trigger mode and external trigger mode, if the adce bit of the adm0 register is set to 1, the mode changes to the trigger standby state. the a/d conversi on operation is started by the trigger signal (adcs bit = 1 in the adm0 register), and the trigger standby state (adcs bit = 0) is returned when the a/d conversion operation ends. chapter 12 a/d converter 730 user?s manual u16031ej3v0ud 12.4.2 operation mode and trigger mode various conversion operations can be specified for the a/ d converter by specifying t he operation mode and trigger mode. the operation mode and trigger mode are set by the adm0 to adm2 registers. the following shows the relationship betwe en the operation mode and trigger mode. table 12-2. relationship between operation mode and trigger mode set value trigger mode operation mode adm0 adm1 adm2 analog input 1 buffer xx010000b 00000xxxb ani0 to ani7 select 4 buffers xx110000b 00000xxxb ani0 to ani7 a/d trigger scan xxx00000b 00000xxxb 00000xxxb ani0 to ani7 1 buffer xx010000b 00000xxxb ani0 to ani7 select 4 buffers xx110000b 00000xxxb ani0 to ani7 timer trigger scan xxx00000b 00001xxxb 00000xxxb ani0 to ani7 1 buffer xx010000b 00000xxxb ani0 to ani7 select 4 buffers xx110000b 00000xxxb ani0 to ani7 external trigger scan xxx00000b xx10xxxxb 00000xxxb ani0 to ani7 (1) trigger mode there are three types of trigger modes that serve as the start timing of a/d conversion processing: a/d trigger mode, timer trigger mode, and external trigger mode. these trigger modes are set by the trg1 and trg0 bits of the adm1 register. (a) a/d trigger mode this mode starts the conversion timing of the analog input set to the ani0 to ani7 pins, and by setting the adce bit of the adm0 register to 1, starts a/d conversion. unless the adce bit is cleared to 0 after conversion, the next conversion operat ion is repeated. if data is writt en to the adm0 to adm2 registers during conversion, conversion is stopped an d then executed from the beginning again. (b) timer trigger mode this mode specifies the conversion timing of the an alog input set for the ani0 to ani7 pins using the values set to the timer c capture/compare register. this register creates the analog input conversion timing by generating the compare match interrupts of the four capture/compare register s (ccc40, ccc41, ccc50, ccc51) connected to the 16-bit timer c (tmc4, tmc5). if the adce bit of the adm0 regist er is set to 1, the a/d converter waits for an interrupt (intccc40, intccc41, intccc50, or intccc51), and starts conversion when intccc40, intccc41, intccc50, or intccc51 occurs (adcs bit = 1 in the adm0 regi ster). when conversion has finished, the converter waits for an interrupt again (adcs = 0). if data is written to the adm0 to adm2 registers during conversion, conversion is stopped and th en executed from the beginning again. chapter 12 a/d converter 731 user?s manual u16031ej3v0ud (c) external trigger mode this mode specifies the conversion timing of the analog input to the ani0 to ani7 pins using the adtrg pin. the ega1 and ega0 bits of the ad m1 register are used to specify the valid edge to be input to the adtrg pin. when the adce bit of the adm0 register is set to 1, the a/d converter waits for an external trigger (adtrg), and starts conversion when the valid edge of adtrg is detected (adcs bit = 1 in the adm0 register). when the converter has completed its conversion operation, it waits for an external trigger again (adcs bit = 0). if the valid edge is detected at the adtrg pin duri ng conversion, conversion is executed from the beginning again. if data is written to the adm0 to adm2 register s during conversion, conversion is stopped and then executed from the beginning again. (2) operation mode there are two operation modes that set the ani0 to ani7 pins: select mode and scan mode. the select mode has sub-modes that consist of 1-buffer mode and 4-buffer mode. these modes are set by the bs and ms bits of the adm0 register. (a) select mode in this mode, one analog input specified by the adm2 register is a/d converted. the conversion results are stored in the adcrn register corresponding to the analog input (anin). for this mode, the 1-buffer mode and 4-buffer mode are provided for storing the a/d conversion results (n = 0 to 7). ? 1-buffer mode in this mode, one analog input specified by the adm2 register is a/d converted. the conversion results are stored in the adcrn register correspondi ng to the analog input (anin) (n = 0 to 7). the anin and adcrn register correspond one to one, and an a/d conversion end interrupt (intad) is generated each time one a/d conversion ends. after conversion has finished, the next conversion operation is repeated, unless the adce bit of the adm0 register is cleared to 0. chapter 12 a/d converter 732 user?s manual u16031ej3v0ud figure 12-3. select mode operat ion timing: 1-buffer mode (ani1) ani1 (input) a/d conversion data 1 (ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) data 5 (ani1) data 6 (ani1) data 1 data 2 data 3 data 4 data 5 data 6 data 1 (ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) data 5 (ani1) adcr1 register intad interrupt conversion start (adm0 register setting) adce bit set adce bit set adce bit set adce bit set conversion start (adm0 register setting) ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter adcrn register analog input chapter 12 a/d converter 733 user?s manual u16031ej3v0ud ? 4-buffer mode in this mode, one analog input is a/d converted f our times and the results are stored in the adcrn register. the a/d conversion end interrupt (intad ) is generated when the four a/d conversions end (n = 0 to 3 when the lower analog input channel is specified and n = 4 to 7 when the higher analog input channel is specified). after conversion has finished, the next conversion operation is repeated, unless the adce bit of the adm0 register is cleared to 0. figure 12-4. select mode operat ion timing: 4-buffer mode (ani2) ani2 (input) a/d conversion data 1 (ani2) data 2 (ani2) data 3 (ani2) data 4 (ani2) data 5 (ani2) data 6 (ani2) data 1 data 2 data 3 data 4 data 5 data 6 data 1 (ani2) adcr0 data 2 (ani2) adcr1 data 3 (ani2) adcr2 data 4 (ani2) adcr3 data 5 (ani2) adcr0 adcrn register intad interrupt conversion start (adm0 register setting) conversion start (adm0 register setting) ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter adcrn register analog input chapter 12 a/d converter 734 user?s manual u16031ej3v0ud (b) scan mode in this mode, the analog inputs specified by the ad m2 register are selected sequentially from the ani0 pin, and a/d conversion is execut ed. the a/d conversion results ar e stored in the adcrn register corresponding to the analog input (n = 0 to 7). w hen the conversion of the s pecified analog input ends, the a/d conversion end interrupt (intad) is generated. after conversion has finished, the next conversion operation is repeated, unless the adce bit of the adm0 register is cleared to 0. figure 12-5. scan mode operation ti ming: 4-channel scan (ani0 to ani3) ani3 (input) ani0 (input) ani1 (input) ani2 (input) a/d conversion data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) data 5 (ani0) data 6 (ani1) data 1 data 2 data 3 data 4 data 5 data 6 data 1 (ani0) adcr0 data 2 (ani1) adcr1 data 3 (ani2) adcr2 data 4 (ani3) adcr3 data 5 (ani0) adcr0 adcrn register intad interrupt conversion start (adm0 register setting) conversion start (adm0 register setting) ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter adcrn register analog input chapter 12 a/d converter 735 user?s manual u16031ej3v0ud 12.5 operation in a/d trigger mode when the adce bit of the adm0 register is set to 1, a/d conversion is started. 12.5.1 select mode operation in this mode, the analog input specified by the adm2 regi ster is a/d converted. the conversion results are stored in the adcrn register corresponding to the analog input. in the select mode, the 1-buffer mode and 4-buffer mode are supported according to the storing method of the a/d conversion results (n = 0 to 7). (1) 1-buffer mode (a/d trigger select: 1 buffer) in this mode, one analog input is a/d converted once. the conversion results are stored in one adcrn register. the analog input and adcrn register correspond one to one. each time an a/d conversion is executed, an a/d c onversion end interrupt (intad) is generated and a/d conversion ends. the next conversion operation is repeated, unless the a dce bit of the adm0 register is cleared to 0. analog input a/d conversion result register anin adcrn this mode is most appropriate for applications in which the results of each first-ti me a/d conversion are read. figure 12-6. example of 1-buffer mode op eration (a/d trigger select: 1 buffer) ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter adm2 (1) the adce bit of adm0 is set to 1 (enable) (2) ani2 is a/d converted (3) the conversion result is stored in adcr2 (4) the intad interrupt is generated chapter 12 a/d converter 736 user?s manual u16031ej3v0ud (2) 4-buffer mode (a/d trigger select: 4 buffers) in this mode, one analog input is a/d converted four times and the result s are stored in the adcrn register. when the 4th a/d conversion ends , an a/d conversion end interrupt (intad) is generated and the a/d conversion is stopped. the next conv ersion operation is repeated, unless the adce bit of the adm0 register is cleared to 0. analog input a/d conversion result register adcr0 (1st time) adcr1 (2nd time) adcr2 (3rd time) ani0 to ani3 adcr3 (4th time) adcr4 (1st time) adcr5 (2nd time) adcr6 (3rd time) ani4 to ani7 adcr7 (4th time) this mode is suitable for applications in which the av erage of the a/d conversi on results is calculated. figure 12-7. example of 4-buffer mode op eration (a/d trigger select: 4 buffers) ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter adm2 ( 4) (1) the adce bit of adm0 is set to 1 (enable) (6) ani3 is a/d converted (2) ani3 is a/d converted (7) the conversion result is stored in adcr2 (3) the conversion result is stored in adcr0 (8) ani3 is a/d converted (4) ani3 is a/d converted (9) the conversion result is stored in adcr3 (5) the conversion result is stored in adcr1 (10) the intad interrupt is generated chapter 12 a/d converter 737 user?s manual u16031ej3v0ud 12.5.2 scan mode operations in this mode, the analog inputs specified by the adm2 re gister are selected sequentially from the ani0 pin, and a/d conversion is executed. the a/d conversion results are stored in the adcrn register corresponding to the analog input (n = 0 to 7). when conversion of all the specified analog input ends , the a/d conversion end interr upt (intad) is generated, and a/d conversion is stopped. the next conversion operati on is repeated, unless the adce bit of the adm0 register is cleared to 0. analog input a/d conversion result register ani0 adcr0 anin note adcrn note set by the anis2 to anis0 bits of the adm2 register. this mode is most appropriate for applications in whic h multiple analog inputs are constantly monitored. figure 12-8. example of scan m ode operation (a/d trigger scan) ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter adm2 (1) the adce bit of adm0 is set to 1 (enable) (8) ani3 is a/d converted (2) ani0 is a/d converted (9) the conversion result is stored in adcr3 (3) the conversion result is stored in adcr0 (10) ani4 is a/d converted (4) ani1 is a/d converted (11) the conversion result is stored in adcr4 (5) the conversion result is stored in adcr1 (12) ani5 is a/d converted (6) ani2 is a/d converted (13) the conversion result is stored in adcr5 (7) the conversion result is stored in adcr2 (14) the intad interrupt is generated . . . . . . chapter 12 a/d converter 738 user?s manual u16031ej3v0ud 12.6 operation in timer trigger mode in this mode, the conversion timing of t he analog input signal set by the ani0 to ani7 pins is defined by the value set to the capture/compare registers of timers c4 and c5. the analog input conversion timing is generated when a compare match interrupt (intccc40, intccc41, intccc50, or intccc51) is gener ated by the capture/compare register connected to 16-bit timer c4 or c5 (tmc4 or tmc5). when the adce bit of the adm0 register is set to 1, the a/d converter waits for the interrupt (intccc40, intccc41, intccc50, or intccc51) , and starts conversion when intccc40, intccc41, intccc50, or intccc51 occurs (adcs bit = 1 in the adm0 register). when conversion is finished, the converter waits for an interrupt again (adcs bit = 0). if intccc40, intccc41, intccc50, or intccc51 occurs during conversion, the conversion operation is executed from the beginning again. if data is written to the adm0 to adm2 registers dur ing conversion, the conversion operation is stopped and executed from the beginning again. chapter 12 a/d converter 739 user?s manual u16031ej3v0ud 12.6.1 select mode operation in this mode, an analog input (ani0 to ani7) specified by the adm2 register is a/d c onverted. the conversion results are stored in the adcrn register corresponding to the analog input. in the select mode, the 1-buffer mode and 4-buffer mode are provided according to the st oring method of the a/d conversion results. (1) 1-buffer mode (timer trigger select: 1 buffer) in this mode, one analog input is a/d converted once and the conversion results are stored in one adcrn register. one analog input is a/d converted once using the trigger of the matc h interrupt signals (intccc40, intccc41, intccc50, intccc51) and the results are st ored in one adcrn register. an a/d conversion end interrupt (intad) is genera ted for each a/d conversion. unless the adce bit of the adm0 register is cleared to 0, a/d conversion is repeated each time a timer match interrupt is generated. table 12-3. correspondence between an alog input pins and adcrn register (1-buffer mode (timer tr igger select: 1 buffer)) trigger analog input a/d conversion result register intcccn interrupt ani0 adcr0 intcccn interrupt ani1 adcr1 intcccn interrupt ani2 adcr2 intcccn interrupt ani3 adcr3 intcccn interrupt ani4 adcr4 intcccn interrupt ani5 adcr5 intcccn interrupt ani6 adcr6 intcccn interrupt ani7 adcr7 remark n = 40, 41, 50, 51 figure 12-9. example of 1-buffer mode operat ion (timer trigger select: 1 buffer) (ani1) ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter intccc40 (1) the adce bit of adm0 is set to 1 (enable) (2) the ccc40 compare is generated (3) ani1 is a/d converted (4) the conversion result is stored in adcr1 (5) the intad interrupt is generated chapter 12 a/d converter 740 user?s manual u16031ej3v0ud (2) 4-buffer mode (timer trigger select: 4 buffers) in this mode, a/d conversion of one analog input is executed four times, and the results are stored in the adcrn register. one analog input is a/d converted four times usin g the match interrupt signals (intccc40, intccc41, intccc50, intccc51) as a trigger, and the results are stored in four adcrn regist ers. the a/d conversion end interrupt (intad) is generated wh en the four a/d conversions end. after conversion has finished, the next conversion is re peated, unless the adce bit of the adm0 register is cleared to 0. this mode is suitable for applications in which the av erage of the a/d conversi on results is calculated. table 12-4. correspondence between an alog input pins and adcrn register (4-buffer mode (timer tr igger select: 4 buffers)) trigger analog input a/d conversion result register ani0 to ani3 adcr0 (1st time) adcr1 (2nd time) adcr2 (3rd time) adcr3 (4th time) intcccn interrupt ani4 to ani7 adcr4 (1st time) adcr5 (2nd time) adcr6 (3rd time) adcr7 (4th time) remark n = 40, 41, 50, 51 figure 12-10. example of 4-buffer mode operat ion (timer trigger sel ect: 4 buffers) (ani3) ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter intcc40 ( 4) ( 4) (1) the adce bit of adm0 is set to 1 ( enable) (8) the ccc40 compare is generated (2) the ccc40 compare is generated (9) ani3 is a/d converted (3) ani3 is a/d converted (10) the conversion result is stored in adcr2 (4) the conversion result is stored in a dcr0 (11) the ccc40 compare is generated (5) the ccc40 compare is generated (12) ani3 is a/d converted (6) ani3 is a/d converted (13) the conversion result is stored in adcr3 (7) the conversion result is stored in adcr1 (14) the intad interrupt is generated chapter 12 a/d converter 741 user?s manual u16031ej3v0ud 12.6.2 scan mode operation in this mode, the analog inputs specifi ed by the adm2 register are selected sequentially from the ani0 pin and are a/d converted the specifi ed number of times using the timer match interrupt signal as a trigger. the result of conversion is stored in the adcrn register corresponding to the analog input. when all the specified analog input signals have been converted, an a/ d conversion end interrupt (intad) occurs. after conversion has finished, the a/d converter waits for a trigger unless the adce bi t of the adm0 register is cleared to 0. when a timer match interrupt occurs again, t he converter starts a/d conversi on again, starting from the ani0 input. this mode is most appropriate for applications in whic h multiple analog inputs are constantly monitored. table 12-5. correspondence between an alog input pins and adcrn register (scan mode (timer trigger scan)) trigger analog input a/d conversion result register ani0 adcr0 ani1 adcr1 ani2 adcr2 ani3 adcr3 ani4 adcr4 ani5 adcr5 ani6 adcr6 intcccn interrupt ani7 adcr7 remark n = 40, 41, 50, 51 figure 12-11. example of scan mode operat ion (timer trigger scan) (ani0 to ani4) ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter intccc40 (1) the adce bit of adm0 is set to 1 (enable) (8) the conversion result is stored in adcr2 (2) the ccc40 compare is generated (9) ani3 is a/d converted (3) ani0 is a/d converted (10) the conversion result is stored in adcr3 (4) the conversion result is stored in adcr0 (11) ani4 is a/d converted (5) ani1 is a/d converted (12) the conversion result is stored in adcr4 (6) the conversion result is stored in adcr1 (13) the intad interrupt is generated (7) ani2 is a/d converted chapter 12 a/d converter 742 user?s manual u16031ej3v0ud 12.7 operation in external trigger mode in this mode, the conversion timing of the analog signals input to the ani0 to ani7 pins is specified by the adtrg pin. detection of the valid edge at the adtrg input pin is s pecified by using the ega1 and ega0 bits of the adm1 register. when the adce bit of the adm0 register is set to 1, th e a/d converter waits for an external trigger (adtrg), and starts conversion when the valid edge of adtrg is detected (adcs bit = 1 in the adm0 register). when the converter has ended conversion, it waits for the external trigger again (adcs bit = 0). if the valid edge is detected at the adtrg pin during c onversion, conversion is exec uted from the beginning again. if data is written to the adm0 to adm2 registers during conversion, conversion is st opped and executed from the beginning again. 12.7.1 select mode operations in this mode, one analog input (ani0 to ani7) specified by the adm2 register is a/d converted. the conversion results are stored in the adcrn register corresponding to t he analog input. in the select mode, there are two select modes: 1-buffer mode and 4-buffer mode, according to the storing method of the conversion results. (1) 1-buffer mode (externa l trigger select: 1-buffer) in this mode, one analog input is a/d converted using the adtrg signal as a trigger. the conversion results are stored in one adcrn register. the analog input and the a/d conversi on results register correspond one to one. the a/d conversion end in terrupt (intad) is generated for each a/d conversion, and a/d conversion is stopped. trigger analog input a/d conversion result register adtrg signal anin adcrn while the adce bit of the adm0 regist er is 1, a/d conversion is repeated every time a trigger is input from the adtrg pin. this mode is most appropriate for applications in wh ich the results are read after each a/d conversion. chapter 12 a/d converter 743 user?s manual u16031ej3v0ud figure 12-12. example of 1-buffer mode operati on (external trigger select: 1 buffer) (ani1) ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter adtrg (1) the adce bit of adm0 is set to 1 (enable) (2) the external trigger is generated (3) ani1 is a/d converted (4) the conversion result is stored in adcr1 (5) the intad interrupt is generated chapter 12 a/d converter 744 user?s manual u16031ej3v0ud (2) 4-buffer mode (externa l trigger select: 4 buffers) in this mode, one analog input is a/ d converted four times using the adtrg signal as a trigger and the results are stored in the adcrn regi ster. the a/d conversion end inte rrupt (intad) is generated and a/d conversion is stopped after the 4th a/d conversion. trigger analog input a/d conversion result register adcr0 (1st time) adcr1 (2nd time) adcr2 (3rd time) ani0 to ani3 adcr3 (4th time) adcr4 (1st time) adcr5 (2nd time) adcr6 (3rd time) adtrg signal ani4 to ani7 adcr7 (4th time) while the adce bit of the adm0 regist er is 1, a/d conversion is repeated every time a trigger is input from the adtrg pin. this mode is suitable for applications in which the av erage of the a/d conversi on results is calculated. figure 12-13. example of 4-buffer mode operati on (external trigger select: 4 buffers) (ani2) ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter ( 4) ( 4) adtrg (1) the adce bit of adm0 is set to 1 (enabl e) (8) the external trigger is generated (2) the external trigger is generated (9) ani2 is a/d converted (3) ani2 is a/d converted (10) the conversion result is stored in adcr2 (4) the conversion result is stored in adcr0 (11) the external trigger is generated (5) the external trigger is generat ed (12) ani2 is a/d converted (6) ani2 is a/d converted (13) the conversion result is stored in adcr3 (7) the conversion result is stored in adcr1 (14) the intad interrupt is generated chapter 12 a/d converter 745 user?s manual u16031ej3v0ud 12.7.2 scan mode operation in this mode, the analog inputs specified by the adm2 re gister are selected sequentially from the ani0 pin using the adtrg signal as a trigger, and a/d converted. the a/d conversion resu lts are stored in the adcrn register corresponding to the analog input (n = 0 to 7). when conversion of all the specified analog inputs has ended, the a/d conversion end interrupt (intad) is generated. unless the adce bit of the adm0 register is cleared to 0 after end of conversion, the a/d converter waits for a trigger. the converter starts a/d conversion from the ani0 input when a trigger is input to the adtrg pin again. trigger analog input a/d conversion result register ani0 adcr0 ani1 adcr1 ani2 adcr2 ani3 adcr3 ani4 adcr4 ani5 adcr5 ani6 adcr6 adtrg signal ani7 adcr7 when a trigger is input to the adtrg pin while the adce bit of the adm0 register is 1, a/d conversion is started again. this is most appropriate for applications in whic h multiple analog inputs are constantly monitored. figure 12-14. example of scan mode operat ion (external trigger scan) (ani0 to ani3) ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter adtrg (1) the adce bit of adm0 is set to 1 (enable) (7) ani2 is a/d converted (2) the external trigger is generated (8) the conversion result is stored in adcr2 (3) ani0 is a/d converted (9) ani3 is a/d converted (4) the conversion result is stored in adcr0 ( 10) the conversion result is stored in adcr3 (5) ani1 is a/d converted (11) the intad interrupt is generated (6) the conversion result is stored in adcr1 chapter 12 a/d converter 746 user?s manual u16031ej3v0ud 12.8 notes on operation (1) stopping conversion operation when the adce bit of the adm0 register is cleared to 0 during a conversion operation, the conversion operation stops and the conversion results are not stored in the adcrn register (n = 0 to 7). (2) external/timer trigger interval set the interval (input time interval) of the trigger in the external or timer trigger mode longer than the conversion time specified by the fr3 to fr0 bits of the adm1 register. when 0 < interval conversion operation time when the following external trigger or timer trigger is input during a conversion operation, the conversion operation is aborted and the conversion starts according to the last external trigger input or timer trigger input. when conversion operations are abort ed, the conversion results are not stored in the adcrn register (n = 0 to 7). however, the number of times the tr igger has been input is counted. when an interrupt occurs, the values that have been conver ted are stored in the adcrn register. (3) operation in standby mode <1> halt mode in this mode, a/d conversion continues. when this mode is released by nmi input or unmasked maskable interrupt input (see 8.6.3 (2) release of halt mode ), the adm0, adm1, and adm2 registers and adcrn register hold the value (n = 0 to 7). <2> idle mode, so ftware stop mode as clock supply to the a/d converter is stop ped, no conversion operations are performed. when these modes are released by nmi input, the adm0, adm1, and adm2 registers and the adcrn register hold the value (n = 0 to 7). however, when the idle or software stop mode is set during a conversion operation, the conversion operation is stopp ed. at this time, if the mode released by nmi input or unmasked maskable interrupt input (see 8.6.4 (2) release of idle mode , 8.6.5 (2) release of software stop mode ), the conversion operation resumes, but the conversion result written to the adcrn register will become undefined. (4) compare match interrupt in timer trigger mode the compare register?s match interrupt becomes an a/ d conversion start trigger and starts the conversion operation. when this happens, the co mpare register?s match interrupt also functions as a compare register match interrupt for the cpu. in order to prevent ma tch interrupts from the compare register for the cpu, disable interrupts using the interrupt mask bits (ccc4mk0, ccc4mk1, ccc5mk0, ccc5mk1) of the interrupt control register (ccc4ic0, ccc4ic1, ccc5ic0, ccc5ic1). (5) input range of ani0 to ani7 use the input voltage at ani0 to ani7 within the specified range. if a volta ge outside the range of av refp and av refm is input to any of these pins (even within the absolute maximum rating range), the converted value of the channel is undefined. in addition, the converted value of the other channels may also be affected. chapter 12 a/d converter 747 user?s manual u16031ej3v0ud (6) conflict <1> conflict between writing a/d conversion result registers (adcrn , adcrnh) at end of conversion and reading adcrn and adcrnh registers by instruction reading the adcrn and adcrnh registers takes precedence. after these registers have been read, the new conversion result is written to the adcrn and adcrnh registers. <2> conflict between writing adcrn and adcrnh at end of conversion and input of external trigger signal the external trigger signal is not accepted during a/ d conversion. therefore, it is not accepted while adcrn and adcrnh are being written. <3> conflict between writing adcrn and adcrnh at e nd of conversion and writing a/d converter mode register 1 (adm1) or a/d converter mode register 2 (adm2) if adm1 or adm2 is written immediately after adcrn and adcrnh have been written on completion of a/d conversion, the conversion result is written to the adcrn and adcrnh registers, but the a/d conversion end interrupt (intad) ma y not occur depending on the timing. chapter 12 a/d converter 748 user?s manual u16031ej3v0ud 12.9 how to read a/d converter characteristics table here, special terms unique to the a/d converter are explained. (1) resolution this is the minimum analog input voltage that can be identified. that is, the per centage of the analog input voltage per bit of digital output is called 1lsb (least si gnificant bit). the percentage of 1lsb with respect to the full scale is expressed by %fsr (full scale range). %fsr indicates the ratio of analog input voltage that can be converted as a percentage, and is always represented by the following formula regardless of the resolution. 1%fsr = (max. value of analog input voltage that can be converted ? min. value of analog input voltage that can be converted)/100 = (av refp ? av refm )/100 1lsb is as follows when the resolution is 10 bits. 1lsb = 1/2 10 = 1/1024 = 0.098%fsr accuracy has no relation to resolution, but is determined by overall error. (2) overall error this shows the maximum error value between the actual measured value and the theoretical value. zero-scale error, full-scale error, linearity error and erro rs that are combinations of these express the overall error. note that the quantization error is not included in the overall erro r in the characteristics table. figure 12-15. overall error ideal line 0 ?? 0 1 ?? 1 digital output overall error analog input av refp av refm chapter 12 a/d converter 749 user?s manual u16031ej3v0ud (3) quantization error when analog values are converted to digital values, a 1/2lsb error naturally occurs. in an a/d converter, an analog input voltage in a range of 1 /2lsb is converted to the same di gital code, so a quantization error cannot be avoided. note that the quantization erro r is not included in the overall error, zero -scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. figure 12-16. quan tization error 0 ?? 0 1 ?? 1 digital output quantization error 1/2lsb 1/2lsb analog input av refm av refp (4) zero-scale error this shows the difference between the actual meas urement value of the analog input voltage and the theoretical value (1/2 lsb) when the digital output changes from 0??000 to 0??001. figure 12-17. zero-scale error 111 011 010 001 zero-scale error ideal line 000 0 1 2 3 1023 digital output (lower 3 bits) analog input (lsb) ?1 100 chapter 12 a/d converter 750 user?s manual u16031ej3v0ud (5) full-scale error this shows the difference between the actual meas urement value of the analog input voltage and the theoretical value (3/2lsb) when the digital output changes from 1??110 to 1??111. figure 12-18. full-scale error 100 011 010 000 ?0 1024 1023 1022 1021 digital output (lower 3 bits) analog input (lsb) full-scale error 111 (6) differential linearity error while the ideal width of code output is 1lsb, this in dicates the difference between the actual measurement value and the ideal value. figure 12-19. differential linearity error av refm av refp digital output analog input differential linearity error 1 ?? 1 0 ?? 0 ideal 1lsb width chapter 12 a/d converter 751 user?s manual u16031ej3v0ud (7) integral linearity error this shows the degree to which the conversion characte ristics deviate from the ideal linear relationship. it expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. figure 12-20. integral linearity error av refm av refp digital output analog input integral linearity error ideal line 1 ?? 1 0 ?? 0 (8) conversion time this expresses the time from when a trigger was generat ed to the time when the digital output was obtained. the sampling time is included in the conv ersion time in the characteristics table. (9) sampling time this is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. figure 12-21. sampling time sampling time conversion time user?s manual u16031ej3v0ud 752 chapter 13 pwm unit 13.1 features ? pwmn: 2 channels ? 12- to 16-bit accuracy selectable ? minimization of low-pass filter size due to main pulse + ancillary pulse configuration main pulse 4/5/6/7/8 bits ancillary pulse 8 bits ? repeat frequency: 129 khz to 2 mhz (f pwmc = 33 mhz) ? selecting pulse width rewrite period: every 1 pulse/256 pulses ? active level of pwm output pulse selectable ? pwm operating clock (f pwmc ): f x /4, f x /8, f x /16, or f x /32 selectable remarks 1. n = 0, 1 2. f pwmc : pwm operating clock f x : main clock 13.2 configuration pwmn has a pwm output configuration of 256 main pul ses and sets the active-level width using modulo h register n. (1) prescaler the prescaler divides f x to generate the pwm operating clock (f pwmc ). the output frequency of the prescaler can be selected from f x /4, f x /8, f x /16, and f x /32, by using the ckspn1 and cksp n0 bits of the pwmcn register (n = 0, 1). (2) reload controller the reload controller controls reloading of the modulo register value. the reload timing (pwm pulse width rewrite period) can be selected from 2 x /f pwmc or 2 x+8 /f pwmc by using the synn bit of the pwmcn register (n = 0, 1, x = 4 to 8 (main pulse bit length)). (3) main pulse generator/output controller this circuit controls the output timing of the main pulse. it generates the main pulse from the reload signal generat ed by the reload controller, according to the value of modulo h register n (n = 0, 1). (4) ancillary pulse generator/output controller this circuit controls the output timing of the ancillary pulse. it generates an ancillary pulse from the reload signal gen erated by the reload controller, according to the value of modulo l register n (n = 0, 1). chapter 13 pwm unit user?s manual u16031ej3v0ud 753 (5) pulse synthesizer/output controller this circuit controls the timing of the pwm pulse sig nal output by synthesizing the main pulse and ancillary pulse. figure 13-1. block diagram of pwm unit internal bus 16 15 8 7 0 modulo h register n modulo l register n 8 prescaler f pwmc 8 selector reload control pwm control register n (pwmcn) ancillary pulse generator/ output controller main pulse generator/output controller pulse synthesizer/ output controller pwmn main pulse ancillary pulse 2 x /f pwmc 2 x +8 /f pwmc f x /4 pwmen pmpn2 pmpn1 pmpn0 alvn synn ckspn1 ckspn0 x remarks 1. n = 0, 1 x = 4 to 8 (specified by pmpn2 to pmpn0 bits) 2. f pwmc : pwm operating clock f x : main clock chapter 13 pwm unit user?s manual u16031ej3v0ud 754 13.3 control registers (1) pwm control registers 0 and 1 (pwmc0 and pwmc1) pwmcn is a register that controls pwmn (n = 0, 1). these registers can be read or written in 8-bit or 1-bit units. cautions 1. do not change the setting of the pm pn2 to pmpn0, synn, ckspn 1, and ckspn0 bits during pwm operation (when pwmen bit = 1); othe rwise the operation can not be guaranteed. 2. note that, if the setting of the alvn bi t is changed during pwm operation (when pwmen bit = 1), noise may be generated. chapter 13 pwm unit user?s manual u16031ej3v0ud 755 7 pwme0 pwme1 pwmc0 pwmc1 6 pmp02 pmp12 5 pmp01 pmp11 4 pmp00 pmp10 3 alv0 alv1 2 syn0 syn1 cksp01 cksp11 cksp00 cksp10 address fffffb00h fffffb10h 0 1 after reset 08h 08h bit position bit name function 7 pwmen this bit enables or disables the operation of pwmn. 0: disables pwm operation. outputs the inactive level as pwm output (pwmn). 1: enables pwm operation. these bits specify the number of main pulse length specification bits and the main pulse length. pmpn2 pmpn1 pmpn0 number of main pulse length specification bits main pulse bit length 0 0 0 8 bits 2 8 (256 bits) 0 0 1 7 bits 2 7 (128 bits) 0 1 0 6 bits 2 6 (64 bits) 0 1 1 5 bits 2 5 (32 bits) 1 0 0 4 bits 2 4 (16 bits) other than above setting prohibited 6 to 4 pmpn2 to pmpn0 3 alvn this bit specifies the active level of pwmn. 0: active low 1: active high at reset, the inactive level of the alvn bit (low level) is output as pwm output. 2 synn this bit specifies the period during which the pulse width of pwmn is to be rewritten. 0: long period (every 256 pwm cycles (2 x+8 /f pwmc )) 1: short period (every 1 pwm cycle (2 x /f pwmc )) these bits specify the operating clock of pwmn (f pwmc ). ckspn1 ckspn0 operating clock (f pwmc ) 0 0 f x /4 0 1 f x /8 1 0 f x /16 1 1 f x /32 1, 0 ckspn1, ckspn0 remarks 1. n = 0, 1 x = 4 to 8 (specified by pmpn2 to pmpn0 bits) 2. f x : main clock chapter 13 pwm unit user?s manual u16031ej3v0ud 756 (2) pwm modulo registers 0 and 1 (pwm0 and pwm1) these 16-bit registers determine t he pulse width of the pwm pulse. these registers can be read or written in 16-bit units. if the higher 8 bits of the pwmn register are used as a pwmhn register and the lower 8 bits are used as a pwmln register, these registers can be read or written in 8-bit units. <1> modulo h register n (pwmhn): bits 15 to 8 this register specifies the active level of the main pulse. the data of the active level width of only the bit length specified by the pmpn2 to pmpn0 bits of the pwmcn register is valid. if the counter length is set to 4 to 7 bits by the pmpn2 to pmpn0 bits, data input to the higher bits is invalid. <2> modulo l register n (pwmln): bits 7 to 0 this register adjusts the timing of t he ancillary pulse for fine tuning (see figure 13-2 ). a value of 0000h to ffffh can be set to the pwmn re gister, and the pwm output changed linearly. if a value of 0000h is set, the inactive level is held. if the value is ffffh, the pwm output bec omes inactive for one ancillary pulse (1/f pwmc ) in one rewrite cycle (2 16 /f pwmc ) (see figure 13-3 ). after reset 0000h 15 14 13 12 11 modulo h register n (for generating main pulse) 109876543210 pwmn address pwm0: fffffb02h pwm1: fffffb12h modulo l register n (for generating ancillary pulse) chapter 13 pwm unit user?s manual u16031ej3v0ud 757 13.4 operation 13.4.1 pwm basic operation pwmn is divided into 256 parts, each of which is called a main pulse. each main pulse has 4- to 8-bit accuracy. pwmn realizes a signal with an accuracy of 12 to 16 bits by synthesizing the required num ber of main pulses and an ancillary pulse with a pulse width of one clock. the main pulse is set by the pmpn2 to pmpn0 bits of pwm control register n (pwmcn), and the pulse width is determined by the value of modulo h register n (valid number of bits). the repeat cycle of the pwm pulse output is the operating clock cycle (f pwmc ) of pwmn specified by the ckspn1 and c kspn0 bits of the pwmcn register divided by 2 x (f pwmc /2 x ). of the 256 main pulses, the ancillary pulses are generated onl y for the main pulses of the set number specified by modulo l register n. the pulse width is 1/f pwmc . the logical sum of the main pulse and the ancillary pulse is output as the pwm pulse signal. therefore, the average value of 256 pwm pulse signals is the pwm pulse signal with a resolution of 12 to 16 bits. the duty factor of the output pwm pulse is determined as follows, by the value set to modulo h register n of pwm modulo register n (pwm0 or pwm1). (1) if ancillary pulse is not generated 2 n) register h modulo of (value pulse pwm output of duty x = (2) if ancillary pulse is generated 2 1 n) register h modulo of (value pulse pwm output of duty x + = remark x = 4 to 8 (bit length of main pulse) chapter 13 pwm unit user?s manual u16031ej3v0ud 758 figure 13-2. example of pwm output with main pulse a nd ancillary pulse 0 1 2 3 4 5 6 7 8 9 10 11 12 13 254 255 main pulse pwmn = xx40h ancillary pulse (modulo l = 40h) ancillary pulse (modulo l = c0h) pw m output main pulse pw m output 1/f pwmc t x 1/f pwmc 2 x 1/f pwmc 16-bit accuracy when 256 output pulses are averaged pwmn = xxc0h remarks 1. n = 0, 1 2. f pwmc : pwm operating clock tx: value of modulo h register n x: number of valid bits of modulo h regist er n (specified by pmpn2 to pmpn0 bits of pwmcn register) active level: high chapter 13 pwm unit user?s manual u16031ej3v0ud 759 figure 13-3. example of pwm output operation l 0123 456 78 ... 126 127 128 ... 254 255 l l l l main pulse pwmn = 0000h ancillary pulse (modulo l = 00h) ancillary pulse (modulo l = 01h) pw m output main pulse pw m output ancillary pulse (modulo l = 00h) main pulse pw m output 16-bit accuracy when 256 output pulses are averaged pwmn = 0001h pwmn = ff00h ancillary pulse (modulo l = ffh) main pulse pw m output pwmn = ffffh remarks 1. n = 0, 1 2. condition: number of valid bits of modulo h register n = 8 16-bit accuracy active level: high chapter 13 pwm unit user?s manual u16031ej3v0ud 760 13.4.2 starting/stopping pwm operation to output a pwm pulse, set data to pwm modulo register n (pwmn) and then set the pwmen bit of pwm control register n (pwmcn) to 1 (n = 0, 1). as a result, the pwm output pin outputs a pwm pulse of the active level specified by the alvn bit of the pwmcn register. when the pwmen bit of the pwmcn register is cleared to 0, the pwm output unit immediately stops the pwm output operation, and the pwm output pin becomes inactive. (1) setting for starting pwm operation before starting the operation of pwmn (when pwmen bit of pwmcn register = 0), be sure to initialize the following registers. ? pmcdh, pfcdh registers: set the control mode. ? pwmn register: set the pulse width. ? pwmcn register: ckspn1 and ckspn0 bits: specify the operating clock (f pwmc ) (f x /4, f x /8, f x /16, f x /32) pmpn2 to pmpn0 bits: specify the bit length (x) of the main pulse. alvn bit: specify the active level of the pwm pulse. synn bit: specify the pwm pulse width rewrite period. cautions 1. do not change the setting of th e pmpn2 to pmpn0, synn, ckspn1, and ckspn0 bits when pwmen bit of the pwmcn register = 1; otherwise the operation cannot be guaranteed. 2. note that, if the setting of the alvn bit is changed during pwm operation (when pwmen bit = 1), noise may be generated. remark n = 0, 1 when the pwmen bit of the pwmcn register is set, pwmn starts operating. immediately after pwmn has started operating, however, the pwm pin maintains the stat us of the port mode (inactive level) until the reload signal of the pwmn register is generated. after t he operation has been start ed, the pwm output becomes active when the reload signal is generated, regardle ss of the setting of the synn bit (pwmn = other than 00xxh). if the timing of rewriti ng the pulse width is set to 2 x+8 (long period: synn bit = 0), the operation is started up to 2 x+8 /f pwmc after the pwmen bit has been set. the pwmn register can be rewritten even during pwm output. chapter 13 pwm unit user?s manual u16031ej3v0ud 761 (2) setting for stopping pwm operation when the pwmen bit of the pwmcn register (n = 0, 1) is cleared to 0, the pwm operation is immediately stopped, and the pwm output becomes inactive immediately. figure 13-4. pwm operation timing pwmn operation starts (pwmen = 1) operation setting 2 x /f pwmc 2 x /f pwmc 2 x /f pwmc pw m output reload signal pwmen bit pwmn operation stops (pwmen = 0) remarks 1. n = 0, 1 x = 4 to 8 (specified by pmpn2 to pmpn0 bits of pwmcn register) 2. f pwmc : pwm operating clock chapter 13 pwm unit user?s manual u16031ej3v0ud 762 13.4.3 setting active level of pwm pulse the alvn bit of pwm control register n (pwmcn) specifies the active level of the pwm pulse output from the pwm output pin (n = 0, 1). if the alvn bit is set to 1, an active-high pulse is output; if it is cleared to 0, an active-low pulse is output. if the alvn bit is rewritten, the active level of pwm out put is immediately changed. the figure below shows the setting of the active level of pwm output and pin status. regardless of the setting of the pwmen bit (which enables or disables pwm), the active level of pwm output can be changed by manipulating the alvn bit. figure 13-5. setting active level of pwm output alvn pwmn (active-high) (active-low) (rewriting alvn bit) remark n = 0, 1 chapter 13 pwm unit user?s manual u16031ej3v0ud 763 13.4.4 specifying pwm pul se width rewrite period pwm output is started and the pulse width is changed ever y 256 cycles of the pwm pulse (2 x+8 /f pwmc ) or every one pwm cycle (2 x /f pwmc ). this pwm pulse width rewrite period is spec ified by the synn bit of the pwmcn register (n = 0, 1). when the synn bit is cleared to 0, the pulse width is changed every 256 pwm pulse cycles (2 x+8 /f pwmc ) (long period). therefore, it takes up to 2 x+8 clocks to output a pulse of the width co rresponding to the data written to the pwmn register. an example of the pwm output timing at this time is shown in figure 13-6. when the synn bit is set to 1, the pulse width is changed every one pwm pulse cycle (2 x /f pwmc ) (short period). in this case, it takes up to 2 x clocks to output a pulse of the width correspondi ng to the data written to the pwmn register. if the pwm pulse rewrite period is specified to be every 2 x /f pwmc (if the synn bit is set to 1), the accuracy of the pwm pulse is x bits or more and (x+8) bits or less, or is lower than the accuracy when the rewrite cycle is set to 2 x+8 /f pwmc . however, the response speed improv es because the repeat cycle increases. figure 13-7 shows an example of the pwm out put timing where the rewrite timing is 2 x /f pwmc . figure 13-6. pwm output timing example 1 (pwm pulse width rewrite period: 2 x+8 /f pwmc ) pwmn output pin contents of pwmn register pwm pulse width rewriting timing rewriting pwmn register pwm pulse width rewriting timing pwm pulse width rewriting timing pwm pulse 2 x+8 cycles pwm pulse 2 x+8 cycles pwm output enabled (pwmen = 1) m l cautions 1. the pulse width is re written every 256 cycles of the pwm pulse 2. the accuracy of the pwm pulse is (x+8) bits. remark n = 0, 1 chapter 13 pwm unit user?s manual u16031ej3v0ud 764 figure 13-7. pwm output timing example 2 (pwm pulse width rewrite period: 2 x /f pwmc ) 1 pwm pulse cycle pwmn output pin contents of pwmn register pwm output enabled (pwmen = 1) rewriting pwmn register rewriting pwmn register pwm pulse width changing timing rewriting pwmn register m kl m cautions 1. the pulse width is rewritten every one pwm pulse cycle. 2. the accuracy of the pwm pulse is x bits or more and (x+8) bits or less. remarks 1. k, l, and m indicate the c ontents of the pwmn register. 2. n = 0, 1 13.4.5 repeat cycle the following table shows the repeat cycle of pwmn (n = 0, 1). table 13-1. repeat cycle of pwmn pulse width rewrite period main pulse accuracy ancillary pulse accuracy repeat cycle long period (synn bit = 0) short period (synn bit = 1) 4 bits 8 bits 16/f pwmc 2 12 /f pwmc 2 4 /f pwmc 5 bits 8 bits 32/f pwmc 2 13 /f pwmc 2 5 /f pwmc 6 bits 8 bits 64/f pwmc 2 14 /f pwmc 2 6 /f pwmc 7 bits 8 bits 128/f pwmc 2 15 /f pwmc 2 7 /f pwmc 8 bits 8 bits 256/f pwmc 2 16 /f pwmc 2 8 /f pwmc remarks 1. n = 0, 1 2. f pwmc : pwm operating clock user?s manual u16031ej3v0ud 765 chapter 14 port functions 14.1 features ? input-only ports: 1 i/o ports: 77 ? function alternately as other peripheral i/o pins. ? it is possible to specify input and output in 1-bit units. 14.2 port configuration the v850e/me2 incorporates a total of 78 input/output ports (including 1 input-onl y port) labeled ports 1, 2, 5 to 7, al, ah, dh, cs, ct, cm, and cd. the port configuration is shown below. port 1 p10 p13 port 2 p21 p25 p20 port 5 p50 p55 port 6 p65 p67 port 7 p72 p77 port al port ah pal0 pal1 pah0 pah9 port dh port cs port ct port cm pdh0 pdh15 pcs0 pcs7 pct0 pct5 pct7 pcm0 pcm5 port cd pcd0 pcd3 chapter 14 port functions user?s manual u16031ej3v0ud 766 (1) function of each port the port functions of this product are shown below. 8-bit and 1-bit operations are possible on all ports, allo wing various kinds of control to be performed. in addition to their port functions, these pins also functi on as on-chip peripheral i/o input/output pins in the control mode. for the block types of each port, see (3) block diagram of port . port name pin name port function function in control mode block type port 1 p10 to p13 4-bit i/o serial interface i/o (csi30, uartb0) external interrupt input usb clock signal input f-1, f-3, h-1, j-1 port 2 p20 to p25 1-bit input, 5-bit i/o nmi input serial interface i/o (csi31, uartb1) external interrupt input a-1, f-4, g-2, h-1 port 5 p50 to p55 6-bit i/o dma controller i/o external interrupt input real-time pulse unit (rpu) i/o f-2, f-3, g-1, g-2, j-1 port 6 p65 to p67 3-bit i/o real-time pulse unit (rpu) i/o external interrupt input l-3, l-5 port 7 p72 to p77 6-bit i/o dma controller i/o real-time pulse unit (rpu) i/o external interrupt input l-1, l-2, l-4 port al pal0, pal1 2-bit i/o external address bus (a0, a1) external interrupt input g-3 port ah pah0 to pah9 10-bit input external address bus (a16 to a25) d-2 port dh pdh0 to pdh15 16-bit i/o external data bus (d16 to d31) external interrupt input pwm output real-time pulse unit (rpu) i/o m-1, m-2, m-3 port cs pcs0 to pcs7 8-bit i/o external bus interface control signal output d-2, j-2 port ct pct0 to pct5, pct7 7-bit i/o external bus interface control signal output d-2, j-3 port cm pcm0 to pcm5 6-bit i/o wait insertion signal input external bus interface control signal i/o self-refresh request signal input a/d converter external trigger input c-1, d-1, d-2, f-5 port cd pcd0 to pcd3 4-bit i/o exter nal bus interface control signal output bus clock output d-1, d-2 chapter 14 port functions user?s manual u16031ej3v0ud 767 cautions 1. when switching the mode of a port that functions as an output or i /o pin to control mode, be sure to follow the procedure below. <1> set the inactive level of the signals output in control mode to the appr opriate bits in port n (n = 1, 2, 5 to 7, al, ah, dh, cs, ct, cm, and cd). <2> the mode is switched to control mode by the port n mo de control register (pmcn). if <1> above is not performed, the contents of port n may be output for a moment when the mode is switched from por t mode to control mode. 2. to manipulate a port by using a bit manipulati on instruction (set1, clr1, or not1), read the port in byte units, process the data of only the bit to be manipulated, and then write back the byte data to the port after con version. in the case of a port havi ng a mixture of input and output pins, the contents of the output latch are written over bits other than the bit to be manipulated. consequently, the output latch of the input pin is undefined (in the input mode, however, the pin status does not change because th e output buffer is turned off). to change the port mode from the input to the output mode, ther efore, set an expected output value to the corresponding bits, and then cha nge the mode to the output mode. the same applies to a port that has both a control mode and an output mode. chapter 14 port functions user?s manual u16031ej3v0ud 768 (2) function when each port?s pins are reset a nd registers that set the port/control mode (1/2) port name pin name pin function after reset register that sets the mode p10/intp10/uclk p10 (input mode) p11/intp11/sck0 p11 (input mode) p12/si0/rxd0 p12 (input mode) port 1 p13/so0/txd0 p13 (input mode) pmc1, pfc1 p20/nmi nmi ? p21/intp21/rxd1 p21 (input mode) p22/intp22/txd1 p22 (input mode) p23/intp23/sck1 p23 (input mode) p24/intp24/si1 p24 (input mode) port 2 p25/intp25/so1 p25 (input mode) pmc2, pfc2 p50/intp50/dmarq0 p50 (input mode) p51/intp51/dmaak0 p51 (input mode) p52/intp52/tc0 p52 (input mode) p53/intpc00/tic0/dmarq1 p53 (input mode) p54/intpc01/dmaak1 p54 (input mode) port 5 p55/toc0/tc1 p55 (input mode) pmc5, pfc5 p65/intp65/intpc10/tic1 p65 (input mode) p66/intp66/intpc11 p66 (input mode) port 6 p67/intp67/toc1 p67 (input mode) pmc6, pfc6 p72/intpc20/tic2/dmarq2 p72 (input mode) p73/intpc21/dmaak2 p73 (input mode) p74/toc2/tc2 p74 (input mode) p75/intpc30/tic3/dmarq3 p75 (input mode) p76/intpc31/dmaak3 p76 (input mode) port 7 p77/toc3/tc3 p77 (input mode) pmc7, pfc7 pal0/intpl0/a0 pal0 (input mode) intpl0/a0 port al pal1/intpl1/a1 pal1 (input mode) intpl1/a1 pmcal, pfcall port ah pah0/a16 to pah9/a25 pah0 to pah9 (input mode) a16 to a25 pmcah pcs0/cs0 pcs0 (input mode) cs0 pcs1/cs1 pcs1 (input mode) cs1 pmccs pcs2/cs2/iowr pcs2 (input mode) cs2/iowr pmccs, pfccs pcs3/cs3 pcs3 (input mode) cs3 pcs4/cs4 pcs4 (input mode) cs4 pmccs pcs5/cs5/iord pcs5 (input mode) cs5/iord pmccs, pfccs pcs6/cs6 pcs6 (input mode) cs6 port cs pcs7/cs7 pcs7 (input mode) cs7 pmccs chapter 14 port functions user?s manual u16031ej3v0ud 769 (2/2) port name pin name pin function after reset register that sets the mode pct0/llwr/llbe/lldqm pct0 (input mode) llwr/llbe/lldqm pct1/luwr/lube/ludqm pct1 (input mode) luwr/lube/ludqm pct2/ulwr/ulbe/uldqm pct2 (input mode) ulwr/ulbe/uldqm pct3/uuwr/uube/uudqm pct3 (i nput mode) uuwr/uube/uudqm pmcct, pfcct pct4/rd pct4 (input mode) rd pct5/we/wr pct5 (input mode) we/wr port ct pct7/bcyst pct7 (input mode) bcyst pmcct pcm0/wait pcm0 (input mode) wait pmccm pcm1 pcm1 (input mode) ? ? pcm2/hldak pcm2 (input mode) hldak pcm3/hldrq pcm3 (input mode) hldrq pcm4/refrq pcm4 (input mode) refrq pmccm port cm pcm5/selfref/adtrg pcm5 (input mode) selfref/adtrg pmccm, pfccm pcd0/sdcke pcd0 (input mode) sdcke pcd1/busclk pcd1 (input mode) busclk pcd2/sdcas pcd2 (input mode) sdcas port cd pcd3/sdras pcd3 (input mode) sdras pmccd pdh0/d16/intpd0 pdh0 (input mode) d16/intpd0 pdh1/d17/intpd1 pdh1 (input mode) d17/intpd1 pmcdh pdh2/d18/intpd2/toc4 pdh2 (input mode) d18/intpd2/toc4 pmcdh, pfcdh pdh3/d19/intpd3 pdh3 (input mode) d19/intpd3 pdh4/d20/intpd4 pdh4 (input mode) d20/intpd4 pmcdh pdh5/d21/intpd5/toc5 pdh5 (input mode) d21/intpd5/toc5 pdh6/d22/intpd6/intp100/tcud10 pdh6 (input mode) d22/intpd6/intp100/tcud10 pdh7/d23/intpd7/intp101/tclr10 pdh7 (input mode) d23/intpd7/intp101/tclr10 pdh8/d24/intpd8/to10 pdh8 (input mode) d24/intpd8/to10 pdh9/d25/intpd9/tiud10 pdh9 (input mode) d25/intpd9/tiud10 pdh10/d26/intpd10/intp110/tcud11 pdh10 (input mode) d26/intpd10/intp110/tcud11 pdh11/d27/intpd11/intp111/tclr11 pdh11 (input mode) d27/intpd11/intp111/tclr11 pdh12/d28/intpd12/to11 pdh12 (input mode) d28/intpd12/to11 pdh13/d29/intpd13/tiud11 pdh13 (input mode) d29/intpd13/tiud11 pdh14/d30/intpd14/pwm0 pdh14 (input mode) d30/intpd14/pwm0 port dh pdh15/d31/intpd15/pwm1 pdh15 (input mode) d31/intpd15/pwm1 pmcdh, pfcdh chapter 14 port functions user?s manual u16031ej3v0ud 770 (3) block diagram of port figure 14-1. block diagram of type a-1 internal bus wr intr rd address p20 nmir0 selector wr intf nmif0 0 1 a noise elimination edge detection nmi remark a: masked in cycles other than read cycles chapter 14 port functions user?s manual u16031ej3v0ud 771 figure 14-2. block diagram of type c-1 internal bus wr pmc rd address wr port a b c pcmn pmccmn pcmn selector selector wr pm pmcmn input signal in control mode remarks 1. n = 0, 3 2. a: active in output port mode b: active in read cycle of port mode or in control mode c: masked in port mode chapter 14 port functions user?s manual u16031ej3v0ud 772 figure 14-3. block diagram of type d-1 internal bus wr pmc rd address wr port pmn b a pmcmn pmn selector selector selector wr pm pmmn output signal in control mode remarks 1. mn = cm1, cd1 2. a: active in output port mode or control mode b: masked in cycles other than read cycles chapter 14 port functions user?s manual u16031ej3v0ud 773 figure 14-4. block diagram of type d-2 internal bus wr pmc rd address output signal in control mode output buffer off signal note wr port pmn b a pmcmn pmn selector selector selector wr pm pmmn note pah0 to pah9: these signals become active in the idle mode and software stop mode, and by bus hold and reset. pcs0, pcs1, pcs3, pcs4 , pcs6, pcs7, pcd2, p cd3, pct4, pct5, pct7: these signals become active by bus hold and reset. pcm2, pcm4, pcd0: these signals become active at reset. remarks 1. mn = ah0 to ah9, cs0, cs1, cs3, cs4, cs6, cs7, ct4, ct5, ct7, cm2, cm4, cd0, cd2, cd3 2. a: active in output port mode or control mode b: masked in cycles other than read cycles chapter 14 port functions user?s manual u16031ej3v0ud 774 figure 14-5. block diagram of type f-1 wr pmc rd address wr port p pmc12 p12 wr pfc pfc12 wr pm pm12 internal bus wr pmc rd wr port p12 selector selector wr pm selector a b c input signal in control mode remark a: active in output port mode b: active in read cycle of port mode or in control mode c: masked in port mode chapter 14 port functions user?s manual u16031ej3v0ud 775 figure 14-6. block diagram of type f-2 wr pmc rd address wr port p pmc53 p53 wr pfc pfc53 wr pm pm53 internal bus wr pmc rd wr port p53 selector selector wr pm selector a b c input signal in control mode remark a: active in output port mode b: active in read cycle of port mode or in control mode c: masked in port mode chapter 14 port functions user?s manual u16031ej3v0ud 776 figure 14-7. block diagram of type f-3 internal bus wr pmc rd noise elimination edge detection address input signal in control mode wr port pmn c b a pmcmn wr pfc pfcmn selector selector selector wr intr intrmn wr pm pmmn pmn wr intf intfmn remarks 1. mn = 10, 50 2. a: active in output port mode b: active in read cycle of port mode or in control mode c: masked in port mode chapter 14 port functions user?s manual u16031ej3v0ud 777 figure 14-8. block diagram of type f-4 internal bus wr pmc rd noise elimination edge detection address input signal in control mode wr port p2n c b a pmc2n wr pfc pfc2n selector selector selector wr intr intr2n wr pm pm2n p2n wr intf intf2n remarks 1. n = 1, 4 2. a: active in output port mode b: active in read cycle of port mode or in control mode c: masked in port mode chapter 14 port functions user?s manual u16031ej3v0ud 778 figure 14-9. block diagram of type f-5 internal bus wr pmc rd address wr port pmccm5 wr pfc pfccm5 selector selector selector wr pm pmcm5 pcm5 pcm5 input signal in control mode a b c remark a: active in output port mode b: active in read cycle of port mode or in control mode c: masked in port mode chapter 14 port functions user?s manual u16031ej3v0ud 779 figure 14-10. block diagram of type g-1 internal bus wr pmc rd address wr port pmc54 p54 selector selector selector wr pfc pfc54 wr pm pm54 output signal in control mode input signal in control mode a b c d p54 remark a: active in output control mode b: active in output port mode c: active in read cycle of port mode or in input control mode d: masked in port mode or output control mode chapter 14 port functions user?s manual u16031ej3v0ud 780 figure 14-11. block diagram of type g-2 internal bus wr pmc rd noise elimination edge detection address output signal in control mode input signal in control mode wr port pmn d c b pmcmn wr pfc pfcmn selector selector selector wr intr intrmn wr pm pmmn pmn wr intf intfmn a remarks 1. mn = 22, 25, 51, 52 2. a: active in output control mode b: active in output port mode c: active in read cycle of port mode or in input control mode d: masked in port mode or output control mode chapter 14 port functions user?s manual u16031ej3v0ud 781 figure 14-12. block diagram of type g-3 internal bus wr pmc rd noise elimination edge detection address output signal in control mode input signal in control mode wr port paln d c b pmcmn wr pfc pfcmn selector selector selector wr intr intrmn wr pm pmmn pmn wr intf intfmn a output buffer off signal note note signal that becomes active in idle mode and software stop mode, and by bus hold and reset remarks 1. n = 0, 1 2. a: active in output control mode b: active in output port mode c: active in read cycle of port mode or in input control mode d: masked in port mode or output control mode chapter 14 port functions user?s manual u16031ej3v0ud 782 figure 14-13. block diagram of type h-1 internal bus wr pmc rd noise elimination edge detection address output signal in control mode output enable signal in control mode input signal in control mode wr port pmn d c b pmcmn wr pfc pfcmn selector selector selector selector wr intr intrmn wr pm pmmn pmn wr intf intfmn a remarks 1. mn = 11, 23 2. a: active in output port mode b: bidirectional control mode (dir control): active in output direction c: active in read cycle of port mode or in input control mode d: masked in port mode chapter 14 port functions user?s manual u16031ej3v0ud 783 figure 14-14. block diagram of type j-1 internal bus wr pmc wr pfc rd address output signal in control mode wr port pmn b a pmcmn pfcmn pmn selector selector selector selector wr pm pmmn remarks 1. mn = 13, 55 2. a: active in output port mode or control mode b: masked in cycles other than read cycles chapter 14 port functions user?s manual u16031ej3v0ud 784 figure 14-15. block diagram of type j-2 internal bus wr pmc wr pfc rd address output signal in control mode output buffer off signal note wr port pcsn b a pmccsn pfccsn pcsn selector selector selector selector wr pm pmcsn note signal that becomes active by bus hold and reset remarks 1. n = 2, 5 2. a: active in output port mode or control mode b: masked in cycles other than read cycles chapter 14 port functions user?s manual u16031ej3v0ud 785 figure 14-16. block diagram of type j-3 internal bus wr pmc wr pfc rd address output signal in control mode output buffer off signal note wr port pctn b a pmcctn pfcctn pctn selector selector selector selector wr pm pmctn note signal that becomes active by bus hold and reset remarks 1. n = 0 to 3 2. a: active in output port mode or control mode b: masked in cycles other than read cycles chapter 14 port functions user?s manual u16031ej3v0ud 786 figure 14-17. block diagram of type l-1 internal bus wr pm rd address wr port pm7n p7n selector selector selector selector wr pfc pfc7n wr pmc pmc7n output signal in control mode a b p7n remarks 1. n = 4, 7 2. a: active in output port mode or control mode b: masked in cycles other than read cycles chapter 14 port functions user?s manual u16031ej3v0ud 787 figure 14-18. block diagram of type l-2 internal bus wr pfc rd address wr port pfc7n p7n selector selector selector wr pm pm7n wr pmc pmc7n p7n a output signal in control mode input signal in control mode b c remarks 1. n = 3, 6 2. a: active in output control mode b: active in output port mode c: masked in port mode or output control mode chapter 14 port functions user?s manual u16031ej3v0ud 788 figure 14-19. block diagram of type l-3 internal bus wr pmc rd noise elimination edge detection address output signal in control mode input signal in control mode wr port p67 c b a pmc67 wr pfc pfc67 selector selector selector wr intr intr67 wr pm pm67 p67 wr intf intf67 remark a: active in output control mode b: active in output port mode c: masked in port mode or output control mode chapter 14 port functions user?s manual u16031ej3v0ud 789 figure 14-20. block diagram of type l-4 internal bus wr pmc rd address input signal in control mode wr port p7n pmc7n p7n b selector selector selector wr pfc pfc7n wr pm pm7n a remarks 1. n = 2, 5 2. a: active in output port mode b: masked in port mode chapter 14 port functions user?s manual u16031ej3v0ud 790 figure 14-21. block diagram of type l-5 internal bus wr pmc rd noise elimination edge detection address input signal in control mode wr port p6n b a pmc6n wr pfc pfc6n selector selector selector wr intr intr6n wr pm pm6n p6n wr intf intf6n remarks 1. n = 5, 6 2. a: active in output port mode b: masked in port mode chapter 14 port functions user?s manual u16031ej3v0ud 791 figure 14-22. block diagram of type m-1 internal bus wr pmc rd noise elimination edge detection address output signal in 32-bit mode 32-bit mode select signal input signal in 32-bit mode output enable signal in 32-bit mode 32-bit mode select signal output enable signal in 32-bit mode output buffer off signal note input signal in control mode wr port pdhn c b a pmcdhn selector selector selector wr intr intrdhn wr pm pmdhn pdhn wr intf intfdhn note signal that becomes active in idle mode and software stop mode, and by bus hold and reset remarks 1. n = 0, 1, 3, 4 2. a: active in output port mode b: active in read cycle of port mode, or in control mode or 32-bit mode c: masked in port mode or 32-bit mode chapter 14 port functions user?s manual u16031ej3v0ud 792 figure 14-23. block diagram of type m-2 internal bus wr pmc rd noise elimination edge detection address output signal in control mode output signal in 32-bit mode 32-bit mode select signal input signal in 32-bit mode output enable signal in 32-bit mode select signal in 32-bit mode output enable signal in 32-bit mode output buffer off signal note input signal in control mode wr port pdhn d c b a pmcdhn wr pfc pfcdhn selector selector selector selector wr intr intrdhn wr pm pmdhn pdhn wr intf intfdhn note signal that becomes active in idle mode and software stop mode, and by bus hold and reset remarks 1. n = 2, 5, 8, 12, 14, 15 2. a: active in output control mode b: active in output port mode c: active in read cycle of port mode, or in input control mode or 32-bit mode d: masked in port mode, input control mode, or 32-bit mode chapter 14 port functions user?s manual u16031ej3v0ud 793 figure 14-24. block diagram of type m-3 internal bus wr pmc rd noise elimination edge detection address output signal in control mode output signal in 32-bit mode 32-bit mode select signal input signal in 32-bit mode output enable signal in 32-bit mode output signal in 32-bit mode output enable signal in 32-bit mode output buffer off signal note input signal in control mode wr port pdhn c b a pmcmn wr pfc pfcdhn selector selector selector selector selector wr intr intrdhn wr pm pmmn pmn wr intf intfdhn note signal that becomes active in idle mode and software stop mode, and by bus hold and reset remarks 1. n = 6, 7, 9, 10, 11, 13 2. a: active in output port mode b: active in read cycle of port mode, or in control mode or 32-bit mode c: masked in port mode or 32-bit mode chapter 14 port functions user?s manual u16031ej3v0ud 794 14.3 port pin functions 14.3.1 port 1 port 1 is a 4-bit i/o port that can be set to the input or output mode in 1-bit units. 7 0 p1 6 0 5 0 4 0 3 p13 2 p12 1 p11 0 p10 address fffff402h after reset undefined bit position bit name function 3 to 0 p1n (n = 3 to 0) i/o port remark for reading/writing of the i/o port, see 14.5 operation of port function . in addition to their function as port pins, the port 1 pins can also operate as serial interface i/o (csi30, uartb0), usb clock signal input, and external interr upt request input in the control mode. (1) operation in control mode port alternate function remark block type p10 intp10/uclk external interrupt input/usb clock signal input f-3 p11 intp11/sck0 external interrupt request input/ serial interface (csi30) i/o h-1 p12 si0/rxd0 f-1 port 1 p13 so0/txd0 serial interface (csi30) i/o/ serial interface (uartb0) i/o j-1 chapter 14 port functions user?s manual u16031ej3v0ud 795 (2) i/o mode/control mode setting the port 1 i/o mode setting is performed by the port 1 mode register (pm1), and t he control mode setting is performed by the port 1 mode control register (pmc 1) and port 1 function control register (pfc1). (a) port 1 mode register (pm1) this register can be read or written in 8-bit or 1-bit units. 7 1 pm1 6 1 5 1 4 1 3 pm13 2 pm12 1 pm11 0 pm10 address fffff422h after reset ffh bit position bit name function 3 to 0 pm1n (n = 3 to 0) specifies input/output mode for p1n pin. 0: output mode (output buffer on) 1: input mode (output buffer off) (b) port 1 mode control register (pmc1) this register can be read or written in 8-bit or 1-bit units. 7 0 pmc1 6 0 5 0 4 0 3 pmc13 2 pmc12 1 pmc11 0 pmc10 address fffff442h after reset 00h bit position bit name function 3 pmc13 specifies operation mode of p13 pin in combination with the pfc1 register. 0: i/o port mode 1: so0 output mode/txd0 output mode 2 pmc12 specifies operation mode of p12 pin in combination with the pfc1 register. 0: i/o port mode 1: si0 input mode/rxd0 input mode 1 pmc11 specifies operation mode of p11 pin in combination with the pfc1 register. 0: i/o port mode 1: external interrupt request (intp11) input mode/sck0 i/o mode 0 pmc10 specifies operation mode of p10 pin in combination with the pfc1 register. 0: i/o port mode 1: external interrupt request (intp10) input mode/uclk input mode chapter 14 port functions user?s manual u16031ej3v0ud 796 (c) port 1 function control register (pfc1) this register can be read or written in 8-bit or 1-bit units. caution when the port mode is sp ecified by the port 1 mode cont rol register (pmc1), the setting of this register becomes invalid. 7 0 pfc1 6 0 5 0 4 0 3 pfc13 2 pfc12 1 pfc11 0 pfc10 address fffff462h after reset 00h bit position bit name function 3 pfc13 specifies operation mode of p13 pin in control mode. 0: so0 output mode 1: txd0 output mode 2 pfc12 specifies operation mode of p12 pin in control mode. 0: si0 input mode 1: rxd0 input mode 1 pfc11 specifies operation mode of p11 pin in control mode. 0: external interrupt request (intp11) input mode 1: sck0 i/o mode 0 pfc10 specifies operation mode of p10 pin in control mode. 0: external interrupt request (inpt10) input mode 1: uclk input mode chapter 14 port functions user?s manual u16031ej3v0ud 797 (3) selecting interrupt trigger mode the valid edges of the intp10 and intp11 pins can be selected by program. the levels to be detected can also be selected. external interrupt rising edge specific ation register 1 (intr1) and external interrupt falling edge specification register 1 (intf1) are used to specif y the valid edge and level detection. (a) external interrupt rising ed ge specification register 1 (intr1) and external interr upt falling edge specification register 1 (intf1) these registers are used to specif y the trigger mode of the external interrupt requests (intp10 and intp11) from external pins. the correspondence between each bit of this register an d the external interrupt request controlled by that bit is as follows. ? intf10 and intr10 bits: intp10 ? intf11 and intr11 bits: intp11 the valid edge can be independently selected from the rising edge, falling edge, and both rising and falling edges. both the registers can be read or written in 8-bit or 1-bit units. caution set the pmc1 register before setting th e trigger mode of the intp10 and intp11 pins. if the pmc1 register is set after the intr 1 and intf1 registers have been set, an illegal interrupt may occur when the pmc1 register is set. chapter 14 port functions user?s manual u16031ej3v0ud 798 7 0 intr1 6 0 5 0 4 0 3 0 2 0 1 intr11 0 intr10 address fffffc22h after reset 03h 0 intf1 00000 intf11 intf10 fffffc02h 00h bit position bit name function specify trigger mode of intp10 and intp11 pins. intf1n intr1n operation 0 0 falling edge 0 1 rising edge 1 0 level detection (low-level detection) notes 1, 2 1 1 both rising and falling edges 1, 0 intf1n, intr1n (n = 0, 1) notes 1. the level of the intp1n pin is sampled each time the main clock (f x ) is divided by four. when the low level of this pin is detected, an interrupt request is latched as the p1ifn bit (n = 0, 1). consequently, even when the cpu acknowledges t he interrupt and the p1ifn bit of the interrupt control register (p1icn) is automatically cleared to 0, the p1ifn bit is immediately set to 1 and interrupts occur consecutively. to avoid this stat us, make the intp1n pin of the external device inactive in the interrupt servicing routine, and forcibly clear the p1ifn bit to 0. 2. if a level-detected interrupt request (intp1n) with a lower priority occurs while an interrupt is being serviced and if this level-detected interrupt requ est (intp1n) that has newly occurred becomes inactive before the current interrupt has been serv iced, the interrupt request of the new interrupt (intp1n) is held pending (n = 0, 1). to not ack nowledge the interrupt request of intp1n, clear the p1ifn bit of the interrupt control register. chapter 14 port functions user?s manual u16031ej3v0ud 799 14.3.2 port 2 port 2 is an i/o port that can be set to the input or output mode in 1-bit units except for p20, which is an input-only pin. 7 0 p2 6 0 5 p25 4 p24 3 p23 2 p22 1 p21 0 p20 address fffff404h after reset undefined bit position bit name function 5 to 0 p2n (n = 5 to 0) i/o port remark for reading/writing of the i/o port, see 14.5 operation of port function . in addition to their function as port pins, the port 2 pins can also operate as the seri al interface (csi31, uartb1) i/o and external interrupt reques t input in the control mode. (1) operation in control mode port alternate function remark block type p20 nmi non-maskable interrupt request input a-1 p21 intp21/rxd1 f-4 p22 intp22/txd1 external interrupt request input/ serial interface (uartb1) i/o g-2 p23 intp23/sck1 h-1 p24 intp24/si1 f-4 port 2 p25 intp25/so1 external interrupt request input/ serial interface (csi31) i/o g-2 chapter 14 port functions user?s manual u16031ej3v0ud 800 (2) i/o mode/control mode setting the port 2 i/o mode setting is performed by the port 2 mode register (pm2), and t he control mode setting is performed by the port 2 mode control register (pmc2) and the port 2 function control register (pfc2). (a) port 2 mode register (pm2) this register can be read or written in 8-bit or 1-bit units. 7 1 pm2 6 1 5 pm25 4 pm24 3 pm23 2 pm22 1 pm21 0 1 address fffff424h after reset ffh bit position bit name function 5 to 1 pm2n (n = 5 to 1) specifies input/output mode for p2n pin. 0: output mode (output buffer on) 1: input mode (output buffer off) (b) port 2 mode control register (pmc2) this register can be read or written in 8-bit or 1-bit units. 7 0 pmc2 6 0 5 pmc25 4 pmc24 3 pmc23 2 pmc22 1 pmc21 0 1 address fffff444h after reset 01h bit position bit name function 5 pmc25 specifies operation mode of p25 pin in combination with the pfc2 register. 0: i/o port mode 1: external interrupt request (intp25) input mode/so1 output mode 4 pmc24 specifies operation mode of p24 pin in combination with the pfc2 register. 0: i/o port mode 1: external interrupt request (intp24) input mode/si1 input mode 3 pmc23 specifies operation mode of p23 pin in combination with the pfc2 register. 0: i/o port mode 1: external interrupt request (intp23) input mode/sck1 i/o mode 2 pmc22 specifies operation mode of p22 pin in combination with the pfc2 register. 0: i/o port mode 1: external interrupt request (intp22) input mode/txd1 output mode 1 pmc21 specifies operation mode of p21 pin in combination with the pfc2 register. 0: i/o port mode 1: external interrupt request (intp21) input mode/rxd1 input mode chapter 14 port functions user?s manual u16031ej3v0ud 801 (c) port 2 function control register (pfc2) this register can be read or written in 8-bit or 1-bit units. caution when the port mode is specified by the port 2 mode control register (pmc2), the pfc2 setting becomes invalid. 7 0 pfc2 6 0 5 pfc25 4 pfc24 3 pfc23 2 pfc22 1 pfc21 0 0 address fffff464h after reset 00h bit position bit name function 5 pfc25 specifies operation mode of p25 pin in control mode. 0: external interrupt request (intp25) input mode 1: so1 output mode 4 pfc24 specifies operation mode of p24 pin in control mode. 0: external interrupt request (intp24) input mode 1: si1 input mode 3 pfc23 specifies operation mode of p23 pin in control mode. 0: external interrupt request (intp23) input mode 1: sck1 i/o mode 2 pfc22 specifies operation mode of p22 pin in control mode. 0: external interrupt request (intp22) input mode 1: txd1 output mode 1 pfc21 specifies operation mode of p21 pin in control mode. 0: external interrupt request (intp21) input mode 1: rxd1 input mode chapter 14 port functions user?s manual u16031ej3v0ud 802 (3) selecting interrupt trigger mode the valid edges of the intp2n and nmi pins can be select ed by program (n = 1 to 5). the level detection of the intp2n pin can also be selected. external interrupt rising edge specific ation register 2 (intr2) and external interrupt falling edge specification register 2 (intf2) are used to specif y the valid edge and level detection. (a) external interrupt rising ed ge specification register 2 (intr2) and external interr upt falling edge specification register 2 (intf2) these registers are used to specify the trigger mode of an external interrupt request (intp2n) from an external pin and the non-maskable interrupt (nmi) (n = 1 to 5). the correspondence between each bit of this register and the external in terrupt request and non-maskable interr upt controlled by that bit is as follows. ? ? ? ? ? ? chapter 14 port functions user?s manual u16031ej3v0ud 803 7 0 intr2 6 0 5 intr25 4 intr24 3 intr23 2 intr22 1 intr21 0 nmir0 address fffffc24h after reset 3fh 0 intf2 0 intf25 intf24 intf23 intf22 intf21 nmif0 fffffc04h 00h bit position bit name function specify trigger mode of intp2n pin. intf2n intr2n operation 0 0 falling edge 0 1 rising edge 1 0 level detection (low-level detection) notes 1, 2 1 1 both rising and falling edges 5 to 1 intf2n, intr2n (n = 1 to 5) specify trigger mode of nmi pin. nmif0 nmir0 operation 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges 0 nmif0, nmir0 notes 1. the level of the intp2n pin is sampled each time the main clock (f x ) is divided by four. when the low level of this pin is detected, an interrupt re quest is latched as the p2ifn bit (n = 1 to 5). consequently, even when the cpu acknowledges t he interrupt and the p2ifn bit of the interrupt control register (p2icn) is automatically cleared to 0, the p2ifn bit is immediately set to 1 and interrupts occur consecutively. to avoid this stat us, make the intp2n pin of the external device inactive in the interrupt servicing routine, and forcibly clear the p2ifn bit to 0. 2. if a level-detected interrupt request (intp2n) with a lo wer priority occurs while an interrupt is being serviced and if this level-detected interrupt requ est (intp2n) that has newly occurred becomes inactive before the current interrupt has been serv iced, the interrupt request of the new interrupt (intp2n) is held pending (n = 1 to 5). to not acknowledge the interrupt request of intp2n, clear the p2ifn bit of the inte rrupt control register. chapter 14 port functions user?s manual u16031ej3v0ud 804 14.3.3 port 5 port 5 is a 6-bit i/o port that can be set to the input or output mode in 1-bit units. 7 0 p5 6 0 5 p55 4 p54 3 p53 2 p52 1 p51 0 p50 address fffff40ah after reset undefined bit position bit name function 5 to 0 p5n (n = 5 to 0) i/o port remark for reading/writing of the i/o port, see 14.5 operation of port function . in addition to their function as port pins, the port 5 pins can also operate as the dma controller i/o, real-time pulse unit (rpu) i/o, and external interrupt request input in the control mode. (1) operation in control mode port alternate function remark block type p50 intp50/dmarq0 external interrupt request input/dma request input f-3 p51 intp51/dmaak0 external interrupt request input/ dma acknowledge signal output p52 intp52/tc0 external interrupt request input/dma end signal output g-2 p53 intpc00/tic0/ dmarq1 external interrupt request and timer c0 external capture trigger input/real-time pulse unit (rpu) input/ dma request input f-2 p54 intpc01/dmaak1 external interrupt request and timer c0 external capture trigger input/dma acknowledge signal output g-1 port 5 p55 toc0/tc1 real-time pulse unit (rpu) output/ dma end signal output j-1 chapter 14 port functions user?s manual u16031ej3v0ud 805 (2) i/o mode/control mode setting the port 5 i/o mode setting is performed by the port 5 mode register (pm5), and t he control mode setting is performed by the port 5 mode control register (pmc 5) and port 5 function control register (pfc5). (a) port 5 mode register (pm5) this register can be read or written in 8-bit or 1-bit units. 7 1 pm5 6 1 5 pm55 4 pm54 3 pm53 2 pm52 1 pm51 0 pm50 address fffff42ah after reset ffh bit position bit name function 5 to 0 pm5n (n = 5 to 0) specifies input/output mode for p5n pin. 0: output mode (output buffer on) 1: input mode (output buffer off) (b) port 5 mode control register (pmc5) this register can be read or written in 8-bit or 1-bit units. 7 0 pmc5 6 0 5 pmc55 4 pmc54 3 pmc53 2 pmc52 1 pmc51 0 pmc50 address fffff44ah after reset 00h bit position bit name function 5 pmc55 specifies operation mode of p55 pin in combination with the pfc5 register. 0: i/o port mode 1: toc0 output mode/dma end signal (tc1) output mode 4 pmc54 specifies operation mode of p54 pin in combination with the pfc5 register. 0: i/o port mode 1: external interrupt request and timer c0 external capture trigger (intpc01) input mode/dma acknowledge signal (dmaak1) output mode 3 pmc53 specifies operation mode of p53 pin in combination with the pfc5 register. 0: i/o port mode 1: external interrupt request and timer c0 external capture trigger (intpc00) input mode/tic0 input mode/dma request (dmarq1) input mode 2 pmc52 specifies operation mode of p52 pin in combination with the pfc5 register. 0: i/o port mode 1: external interrupt request (intp52) input mode/dma end signal (tc0) output mode 1 pmc51 specifies operation mode of p51 pin in combination with the pfc5 register. 0: i/o port mode 1: external interrupt request (intp51) input mode/dma acknowledge signal (dmaak0) output mode 0 pmc50 specifies operation mode of p50 pin in combination with the pfc5 register. 0: i/o port mode 1: external interrupt request (intp50) input mode/dma request (dmarq0) input mode chapter 14 port functions user?s manual u16031ej3v0ud 806 (c) port 5 function control register (pfc5) this register can be read or written in 8-bit or 1-bit units. caution when the port mode is sp ecified by the port 5 mode cont rol register (pmc5), the setting of this register becomes invalid. 7 0 pfc5 6 0 5 pfc55 4 pfc54 3 pfc53 2 pfc52 1 pfc51 0 pfc50 address fffff46ah after reset 00h bit position bit name function 5 pfc55 specifies operation mode of p55 pin in control mode. 0: toc0 output mode 1: dma end signal (tc1) output mode 4 pfc54 specifies operation mode of p54 pin in control mode. 0: external interrupt request and timer c0 external capture trigger (intpc01) input mode 1: dma acknowledge signal (dmaak1) output 3 pfc53 specifies operation mode of p53 pin in control mode. 0: external interrupt request and timer c0 external capture trigger (intpc01) input mode/tic0 input mode 1: dma request (dmarq1) input mode there is no register that selects an external interrupt request and timer c0 external capture trigger (intpc00) input mode or tic0 input mode. ? to use tic0 input mode: mask the external interrupt request and external capture trigger (intpc00) of timer c0, or use the ccc00 register as a compare register. ? to use external interrupt request and external capture trigger (intpc00) of timer c0: clear the etic0 bit of the tmcc01 register to 0. 2 pfc52 specifies operation mode of p52 pin. 0: external interrupt request (intp52) input mode 1: dma end signal (tc0) output mode 1 pfc51 specifies operation mode of p51 pin. 0: external interrupt request (intp51) input mode 1: dma acknowledge signal (dmaak0) output 0 pfc50 specifies operation mode of p50 pin in control mode. 0: external interrupt request (intp50) input mode 1: dma request (dmarq0) input mode chapter 14 port functions user?s manual u16031ej3v0ud 807 (3) selecting interrupt trigger mode the valid edges of the intp5n pin can be selected by program (n = 0 to 2). the level detection of the intp5n pin can also be selected. external interrupt rising edge specific ation register 5 (intr5) and external interrupt falling edge specification register 5 (intf5) are used to specif y the valid edge and level detection. (a) external interrupt rising ed ge specification register 5 (intr5) and external interr upt falling edge specification register 5 (intf5) these registers are used to specify the trigger mode of an external interrupt request (intp5n) from an external pin (n = 0 to 2). the correspondence between each bit of this register and the external interrupt request controlled by that bit is as follows. ? intf50 and intr50 bits: intp50 ? intf51 and intr51 bits: intp51 ? intf52 and intr52 bits: intp52 the rising edge, falling edge, or both the rising and fa lling edges can be specified as the valid edge of the intp5n pin, independently for each pin. both the registers can be read or written in 8-bit or 1-bit units. caution set the pmc5 register before setting the trigger mode. if the pmc5 register is set after the intr 5 and intf5 registers have been set, an illegal interrupt may occur when the pmc5 register is set. chapter 14 port functions user?s manual u16031ej3v0ud 808 7 0 intr5 6 0 5 0 4 0 3 0 2 intr52 1 intr51 0 intr50 address fffffc2ah after reset 07h 0 intf5 0000 intf52 intf51 intf50 fffffc0ah 00h bit position bit name function specify trigger mode of intp5n pin. intf5n intr5n operation 0 0 falling edge 0 1 rising edge 1 0 level detection (low-level detection) notes 1, 2 1 1 both rising and falling edges 2 to 0 intf5n, intr5n (n = 0 to 2) notes 1. the level of the intp5n pin is sampled each time the main clock (f x ) is divided by four. when the low level of this pin is detected, an interrupt re quest is latched as the p5ifn bit (n = 0 to 2). consequently, even when the cpu acknowledges t he interrupt and the p5ifn bit of the interrupt control register (p5icn) is automatically cleared to 0, the p5ifn bit is immediately set to 1 and interrupts occur consecutively. to avoid this stat us, make the intp5n pin of the external device inactive in the interrupt servicing routine, and forcibly clear the p5ifn bit to 0. 2. if a level-detected interrupt request (intp5n) with a lo wer priority occurs while an interrupt is being serviced and if this level-detected interrupt requ est (intp5n) that has newly occurred becomes inactive before the current interrupt has been serv iced, the interrupt request of the new interrupt (intp5n) is held pending (n = 0 to 2). to not acknowledge the interrupt request of intp5n, clear the p5ifn bit of the inte rrupt control register. chapter 14 port functions user?s manual u16031ej3v0ud 809 14.3.4 port 6 port 6 is a 3-bit i/o port that can be set to the input or output mode in 1-bit units. 7 p67 p6 6 p66 5 p65 4 0 3 0 2 0 1 0 0 0 address fffff40ch after reset undefined bit position bit name function 7 to 5 p6n (n = 7 to 5) i/o port remark for reading/writing of the i/o port, see 14.5 operation of port function . in addition to their function as port pins, the port 6 pins can also operate as the real-time puls e unit (rpu) i/o and external interrupt request input in the control mode. (1) operation in control mode port alternate function remark block type p65 intp65/intpc10/ tic1 external interrupt request and timer c1 external capture trigger input/real-time pulse unit (rpu) input p66 intp66/intpc11 external interrupt request and timer c1 external capture trigger input l-5 port 6 p67 intp67/toc1 external interrupt request input/ real-time pulse unit (pru) output l-3 chapter 14 port functions user?s manual u16031ej3v0ud 810 (2) i/o mode/control mode setting the port 6 i/o mode setting is performed by the port 6 mode register (pm6), and t he control mode setting is performed by the port 6 mode control register (pmc 6) and port 6 function control register (pfc6). (a) port 6 mode register (pm6) this register can be read or written in 8-bit or 1-bit units. 7 pm67 pm6 6 pm66 5 pm65 4 1 3 1 2 1 1 1 0 1 address fffff42ch after reset ffh bit position bit name function 7 to 5 pm6n (n = 7 to 5) specifies input/output mode for p6n pin. 0: output mode (output buffer on) 1: input mode (output buffer off) (b) port 6 mode control register (pmc6) this register can be read or written in 8-bit or 1-bit units. 7 pmc67 pmc6 6 pmc66 5 pmc65 4 0 3 0 2 0 1 0 0 0 address fffff44ch after reset 00h bit position bit name function 7 pmc67 specifies operation mode of p67 pin. 0: i/o port mode 1: external interrupt request (intp67) input mode/toc1 output mode 6 pmc66 specifies operation mode of p66 pin. 0: i/o port mode 1: external interrupt request (intp66) input mode/external interrupt request and timer c1 external capture trigger (intpc11) input mode 5 pmc65 specifies operation mode of p65 pin. 0: i/o port mode 1: external interrupt request (intp65) input mode/external interrupt request and timer c1 external capture trigger (intpc10) input mode/tic1 input mode chapter 14 port functions user?s manual u16031ej3v0ud 811 (c) port 6 function control register (pfc6) this register can be read or written in 8-bit or 1-bit units. caution when the port mode is sp ecified by the port 6 mode cont rol register (pmc6), the setting of this register becomes invalid. 7 pfc67 pfc6 6 pfc66 5 pfc65 4 0 3 0 2 0 1 0 0 0 address fffff46ch after reset 00h bit position bit name function 7 pfc67 specifies operation mode of p67 pin in control mode. 0: external interrupt request (intp67) input mode 1: toc1 output mode 6 pfc66 specifies operation mode of p66 pin in control mode. 0: external interrupt request (intp66) input mode 1: external interrupt request and timer c1 external capture trigger (intpc11) input mode 5 pfc65 specifies operation mode of p65 pin in control mode. 0: external interrupt request (intp65) input mode 1: external interrupt request and timer c1 external capture trigger (intpc10) input mode/tic1 input mode there is no register that selects an external interrupt request and timer c1 external capture trigger (intpc10) input mode or tic1 input mode. ? to use tic1 input mode: mask the external interrupt request and external capture trigger (intpc10) of timer c1, or use the ccc10 register as a compare register. ? to use external interrupt request and external capture trigger (intpc10) of timer c1: clear the etic1 bit of the tmcc11 register to 0. chapter 14 port functions user?s manual u16031ej3v0ud 812 (3) selecting interrupt trigger mode the valid edges of the intp6n pin can be selected by program (n = 5 to 7). the level detection of the intp6n pin can also be selected. external interrupt rising edge specific ation register 6 (intr6) and external interrupt falling edge specification register 6 (intf6) are used to specif y the valid edge and level detection. (a) external interrupt rising ed ge specification register 6 (intr6) and external interr upt falling edge specification register 6 (intf6) these registers are used to specify the trigger mode of an external interrupt request (intp6n) from an external pin (n = 5 to 7). the correspondence between each bit of this register and the external interrupt request controlled by that bit is as follows. ? intf65 and intr65 bits: intp65 ? intf66 and intr66 bits: intp66 ? intf67 and intr67 bits: intp67 the rising edge, falling edge, or both the rising and fa lling edges can be specified as the valid edge of the intp6n pin, independently for each pin. both the registers can be read or written in 8-bit or 1-bit units. caution set the pmc6 register before setting the trigger mode. if the pmc6 register is set after the intr 6 and intf6 registers have been set, an illegal interrupt may occur when the pmc6 register is set. chapter 14 port functions user?s manual u16031ej3v0ud 813 7 intr67 intr6 6 intr66 5 intr65 4 0 3 0 2 0 1 0 0 0 address fffffc2ch after reset e0h intf67 intf6 intf66 intf65 00000 fffffc0ch 00h bit position bit name function specify trigger mode of intp6n pin. intf6n intr6n operation 0 0 falling edge 0 1 rising edge 1 0 level detection (low-level detection) notes 1, 2 1 1 both rising and falling edges 7 to 5 intf6n, intr6n (n = 7 to 5) notes 1. the level of the intp6n pin is sampled each time the main clock (f x ) is divided by four. when the low level of this pin is detected, an interrupt re quest is latched as the p6ifn bit (n = 5 to 7). consequently, even when the cpu acknowledges t he interrupt and the p6ifn bit of the interrupt control register (p6icn) is automatically cleared to 0, the p6ifn bit is immediately set to 1 and interrupts occur consecutively. to avoid this stat us, make the intp6n pin of the external device inactive in the interrupt servicing routine, and forcibly clear the p6ifn bit to 0. 2. if a level-detected interrupt request (intp6n) with a lower priority occurs while an interrupt is being serviced and if this level-detected interrupt requ est (intp6n) that has newly occurred becomes inactive before the current interrupt has been serv iced, the interrupt request of the new interrupt (intp6n) is held pending (n = 5 to 7). to not acknowledge the interrupt request of intp6n, clear the p6ifn bit of the inte rrupt control register. chapter 14 port functions user?s manual u16031ej3v0ud 814 14.3.5 port 7 port 7 is a 6-bit i/o port that can be set to the input or output mode in 1-bit units. 7 p77 p7 6 p76 5 p75 4 p74 3 p73 2 p72 1 0 0 0 address fffff40eh after reset undefined bit position bit name function 7 to 2 p7n (n = 7 to 2) i/o port remark for reading/writing of the i/o port, see 14.5 operation of port function . in addition to their function as port pins, the port 7 pins can also operate as the dma controller i/o, real-time pulse unit (rpu) i/o, and external interrupt request input in the control mode. (1) operation in control mode port alternate function remark block type p72 intpc20/tic2/ dmarq2 external interrupt request and timer c2 external capture trigger input/real-rime pulse unit (rpu) input/ dma request input l-4 p73 intpc21/dmaak2 external interrupt request and timer c2 external capture trigger input/dma acknowledge signal output l-2 p74 toc2/tc2 real-time pulse unit (rpu) output/ dma end signal output l-1 p75 intpc30/tic3/ dmarq3 external interrupt request and timer c3 external capture trigger input/real-time pulse unit (rpu) input/ dma request input l-4 p76 intpc31/dmaak3 external interrupt request and timer c3 external capture trigger input/dma acknowledge signal output l-2 port 7 p77 toc3/tc3 real-time pulse unit (rpu) output/ dma end signal output l-1 chapter 14 port functions user?s manual u16031ej3v0ud 815 (2) i/o mode/control mode setting the port 7 i/o mode setting is performed by the port 7 mode register (pm7), and t he control mode setting is performed by the port 7 mode control register (pmc 7) and port 7 function control register (pfc7). (a) port 7 mode register (pm7) this register can be read or written in 8-bit or 1-bit units. 7 pm77 pm7 6 pm76 5 pm75 4 pm74 3 pm73 2 pm72 1 1 0 1 address fffff42eh after reset ffh bit position bit name function 7 to 2 pm7n (n = 7 to 2) specifies input/output mode for p7n pin. 0: output mode (output buffer on) 1: input mode (output buffer off) (b) port 7 mode control register (pmc7) this register can be read or written in 8-bit or 1-bit units. 7 pmc77 pmc7 6 pmc76 5 pmc75 4 pmc74 3 pmc73 2 pmc72 1 0 0 0 address fffff44eh after reset 00h bit position bit name function 7 pmc77 specifies operation mode of p77 pin in combination with the pfc7 register. 0: i/o port mode 1: toc3 output mode/dma end signal (tc3) output mode 6 pmc76 specifies operation mode of p76 pin in combination with the pfc7 register. 0: i/o port mode 1: external interrupt request and time c3 external capture trigger (intpc31) input mode/dma acknowledge signal (dmaak3) output mode 5 pmc75 specifies operation mode of p75 pin in combination with the pfc7 register. 0: i/o port mode 1: external interrupt request and timer c3 external capture trigger (intpc30) input mode/tic3 input mode/dma request (dmarq3) input mode 4 pmc74 specifies operation mode of p74 pin in combination with the pfc7 register. 0: i/o port mode 1: toc2 output mode/dma end signal (tc2) output mode 3 pmc73 specifies operation mode of p73 pin in combination with the pfc7 register. 0: i/o port mode 1: external interrupt request and time c2 external capture trigger (intpc21) input mode/dma acknowledge signal (dmaak2) output mode 2 pmc72 specifies operation mode of p72 pin in combination with the pfc7 register. 0: i/o port mode 1: external interrupt request and timer c2 external capture trigger (intpc20) input mode/tic2 input mode/dma request (dmarq2) input mode chapter 14 port functions user?s manual u16031ej3v0ud 816 (c) port 7 function control register (pfc7) this register can be read or written in 8-bit or 1-bit units. caution when the port mode is sp ecified by the port 7 mode cont rol register (pmc7), the setting of this register becomes invalid. 7 pfc77 pfc7 6 pfc76 5 pfc75 4 pfc74 3 pfc73 2 pfc72 1 0 0 0 address fffff46eh after reset 00h bit position bit name function 7 pfc77 specifies operation mode of p77 pin in control mode. 0: toc3 output mode 1: dma end signal (tc3) output mode 6 pfc76 specifies operation mode of p76 pin in control mode. 0: external interrupt request and timer c3 external capture trigger (intpc31) input mode 1: dma acknowledge signal (dmaak3) output 5 pfc75 specifies operation mode of p75 pin in control mode. 0: external interrupt request and timer c3 external capture trigger (intpc30) input mode/tic3 input mode 1: dma request (dmarq3) input mode there is no register that selects an external interrupt request and timer c3 external capture trigger (intpc30) input mode or tic3 input mode. ? to use tic3 input mode: mask the external interrupt request and external capture trigger (intpc30) of timer c3, or use the ccc30 register as a compare register. ? to use external interrupt request and external capture trigger (intpc30) of timer c3: clear the etic3 bit of the tmcc31 register to 0. 4 pfc74 specifies operation mode of p74 pin. 0: toc2 output mode 1: dma end signal (tc2) output mode 3 pfc73 specifies operation mode of p73 pin. 0: external interrupt request and timer c2 external capture trigger (intpc21) input mode 1: dma acknowledge signal (dmaak2) output 2 pfc72 specifies operation mode of p72 pin in control mode. 0: external interrupt request and timer c2 external capture trigger (intpc20) input mode/tic2 input mode 1: dma request (dmarq2) input mode there is no register that selects an external interrupt request and timer c2 external capture trigger (intpc20) input mode or tic2 input mode. ? to use tic2 input mode: mask the external interrupt request and external capture trigger (intpc20) of timer c2, or use the ccc20 register as a compare register. ? to use external interrupt request and external capture trigger (intpc20) of timer c2: clear the etic2 bit of the tmcc21 register to 0. chapter 14 port functions user?s manual u16031ej3v0ud 817 14.3.6 port al port al (pal) is a 16-bit i/o port that can be set to the input or output mode in 1-bit units. when the higher 8 bits of port al are used as port alh (palh) and the lower 8 bits as port all (pall), port al becomes two 8-bit ports that can be set in the input or output mode in 1-bit units. 15 0 7 0 pal 14 0 6 0 13 0 5 0 12 0 4 0 11 0 3 0 10 0 2 0 9 0 1 pal1 8 0 0 pal0 address fffff001h address fffff000h after reset undefined bit position bit name function 1, 0 paln (n = 1, 0) i/o port remark for reading/writing of the i/o port, see 14.5 operation of port function . in addition to their functions as port pins, in the control mode, the port al pins operate as an address bus for when the memory is externally expanded and external interrupt request input. (1) operation in control mode port alternate function remark block type port al pal0, pal1 intpl0/a0, intpl1/a1 address bus when memory expanded/ external interrupt request input g-3 chapter 14 port functions user?s manual u16031ej3v0ud 818 (2) i/o mode/control mode setting the port al i/o mode setting is perform ed by the port al mode register (pmal), and control mode setting is performed by port al mode control register l (pmcall) and the port al function control register (pfcal). (a) port al mode register (pmal) the port al mode register (pmal) can be read or written in 16-bit units. when using the higher 8 bits of pmal as port al m ode register h (pmalh) and the lower 8 bits as port al mode register l (pmall), the pmalh register is read-only, in 8-bit or 1-bit units, and the pmall register can be read or written in 8-bit or 1-bit units. 15 1 7 1 pmal 14 1 6 1 13 1 5 1 12 1 4 1 11 1 3 1 10 1 2 1 9 1 1 pmal1 8 1 0 pmal0 address fffff021h address fffff020h after reset ffffh bit position bit name function 1, 0 pmaln (n = 1, 0) specifies input/output mode for paln pin. 0: output mode (output buffer on) 1: input mode (output buffer off) (b) port al mode control register (pmcal) the port al mode control register (pmcal) can be read or written in 16-bit units. when using the higher 8 bits of pmcal as port al mode control register h (pmcalh) and the lower 8 bits as port al mode control register l (pmcall), th e pmcalh register is read-only, in 8-bit or 1-bit units, and the pmcall register can be read or written in 8-bit or 1-bit units. 15 0 7 0 pmcal 14 0 6 0 13 0 5 0 12 0 4 0 11 0 3 0 10 0 2 0 9 0 1 pmcal1 8 0 0 pmcal0 address fffff041h address fffff040h after reset 0002h bit position bit name function 1 pmcal1 specifies operation mode of pal1 pin. 0: i/o port mode 1: intpl1 input mode/a1 output mode 0 pmcal0 specifies operation mode of pal0 pin. 0: i/o port mode 1: intpl0 input mode/a0 output mode chapter 14 port functions user?s manual u16031ej3v0ud 819 (c) port al function control register l (pfcall) this register can be read or written in 8-bit or 1-bit units. caution when the port mode is specified by th e port al mode control register (pmcal), the setting of this register becomes invalid. 7 0 pfcall 6 0 5 0 4 0 3 0 2 0 1 pfcal1 0 pfcal0 address fffff058h after reset 03h bit position bit name function 1 pfcal1 specifies operation mode of pal1 pin in control mode. 0: external interrupt request (intpl1) input mode 1: a1 output mode 0 pfcal0 specifies operation mode of pal0 pin in control mode. 0: external interrupt request (intpl0) input mode 1: a0 output mode chapter 14 port functions user?s manual u16031ej3v0ud 820 (3) selecting interrupt trigger mode the valid edges of the intpln pin can be selected by pr ogram (n = 0, 1). the level detection of the intpln pin can also be selected. external interrupt rising edge specification regist er al (intral) and external interrupt falling edge specification register al (intfal) are used to specify the valid edge and level detection. (a) external interrupt rising ed ge specification register al (int ral) and external interrupt falling edge specification register al (intfal) these registers are used to specify the trigger mode of an external interrupt request (intpln) from an external pin (n = 0, 1). the correspondence between each bit of this register and the external interrupt request controlled by that bit is as follows. ? intfal0 and intral0 bits: intpal0 ? intfal1 and intral1 bits: intpal1 the rising edge, falling edge, or both the rising and fa lling edges can be specified as the valid edge of the intpln pin, independently for each pin. both the registers can be read or written in 8-bit or 1-bit units. caution before setting the trigge r mode, set the pmcal register. if the pmcal register is set after the int ral and intfal registers have been set, an illegal interrupt may occur when the pmcal register is set. chapter 14 port functions user?s manual u16031ej3v0ud 821 7 0 intral 6 0 5 0 4 0 3 0 2 0 1 intral1 0 intral0 address fffffc30h after reset 03h 0 intfal 00000 intfal1 intfal0 fffffc10h 00h bit position bit name function specify trigger mode of intpln pin. intfaln intraln operation 0 0 falling edge 0 1 rising edge 1 0 level detection (low-level detection) notes 1, 2 1 1 both rising and falling edges 1, 0 intfaln, intraln (n = 0, 1) notes 1. the level of the intpln pin is sampled each time the main clock (f x ) is divided by four. when the low level of this pin is detected, an interrupt request is latched as the plifn bit (n = 0, 1). consequently, even when the cpu acknowledges t he interrupt and the plifn bit of the interrupt control register (plicn) is automatically cleared to 0, the plifn bit is immediately set to 1 and interrupts occur consecutively. to avoid this stat us, make the intpln pin of the external device inactive in the interrupt servicing routine, and forcibly clear the plifn bit to 0. 2. if a level-detected interrupt request (intpln) with a lower priority occurs while an interrupt is being serviced and if this level-detected interrupt requ est (intpln) that has newly occurred becomes inactive before the current interrupt has been serv iced, the interrupt request of the new interrupt (intpln) is held pending (n = 0, 1). to not ack nowledge the interrupt request of intpln, clear the plifn bit of the interrupt control register. chapter 14 port functions user?s manual u16031ej3v0ud 822 14.3.7 port ah port ah (pah) is a 10-bit i/o port that can be se t in the input or output mode in 1-bit units. when the higher 8 bits of port ah are used as port ahh (p ahh) and the lower 8 bits as port ahl (pahl), port ah becomes two 8-bit ports that can be set in the input or output mode in 1-bit units. 15 0 7 pah7 pah 14 0 6 pah6 13 0 5 pah5 12 0 4 pah4 11 0 3 pah3 10 0 2 pah2 9 pah9 1 pah1 8 pah8 0 pah0 address fffff003h address fffff002h after reset undefined bit position bit name function 9 to 0 pahn (n = 9 to 0) i/o port remark for reading/writing of the i/o port, see 14.5 operation of port function . in addition to their functions as port pins, in the control mode, the port ah pins operate as an address bus for when the memory is externally expanded. (1) operation in control mode port alternate function remark block type port ah pal9 to pal0 a25 to a16 address bus when memory expanded d-2 chapter 14 port functions user?s manual u16031ej3v0ud 823 (2) i/o mode/control mode setting the port ah i/o mode setting is performed by the por t ah mode register (pmah), and the control mode setting is performed by the port ah mode control register (pmcah). (a) port ah mode register (pmah) the port ah mode register (pmah) can be read or written in 16-bit units. if the higher 8 bits of pmah are used as port ah mo de register h (pmahh), and the lower 8 bits as port ah mode register l (pmahl), these two 8-bit port mode registers can be read or written in 8-bit or 1-bit units. 15 1 7 pmah7 pmah 14 1 6 pmah6 13 1 5 pmah5 12 1 4 pmah4 11 1 3 pmah3 10 1 2 pmah2 9 pmah9 1 pmah1 8 pmah8 0 pmah0 address fffff023h address fffff022h after reset ffffh bit position bit name function 9 to 0 pmahn (n = 9 to 0) specifies input/output mode for pahn pin. 0: output mode (output buffer on) 1: input mode (output buffer off) (b) port ah mode control register (pmcah) the port ah mode control register (pmcah) can be read or written in 16-bit units. if the higher 8 bits of pmcah are used as port ah mode control register h (pmcahh), and the lower 8 bits as port ah mode control register l (pmcahl), these two 8-bit port mode registers can be read or written in 8-bit or 1-bit units. 15 0 7 pmcah7 pmcah 14 0 6 pmcah6 13 0 5 pmcah5 12 0 4 pmcah4 11 0 3 pmcah3 10 0 2 pmcah2 9 pmcah9 1 pmcah1 8 pmcah8 0 pmcah0 address fffff043h address fffff042h after reset 03ffh bit position bit name function 9 to 0 pmcahn (n = 9 to 0) specifies operation mode of pahn pin. 0: i/o port mode 1: a25 to a16 output mode chapter 14 port functions user?s manual u16031ej3v0ud 824 14.3.8 port dh port dh (pdh) is a 16-bit i/o port that can be se t in the input or output mode in 1-bit units. when the higher 8 bits of port dh are used as port dhh (pdhh), and the lower 8 bits as port dhl (pdhl), port dh becomes two 8-bit ports that can be set in the input or output mode in 1-bit units. caution in the 32-bit mode (mode1 and mode0 pins = 00) and when the bmodcn bit of the pfcdh register is set, all the register functi ons of port dh (see 14.3.8) become invalid. 15 pdh15 7 pdh7 pdh 14 pdh14 6 pdh6 13 pdh13 5 pdh5 12 pdh12 4 pdh4 11 pdh11 3 pdh3 10 pdh10 2 pdh2 9 pdh9 1 pdh1 8 pdh8 0 pdh0 address fffff007h address fffff006h after reset undefined bit position bit name function 15 to 0 pdhn (n = 15 to 0) i/o port remark for reading/writing of the i/o port, see 14.5 operation of port function . in addition to their functions as port pins, in the control mode, the port dh pins operat e as a data bus for when the memory is externally expanded, real -time pulse unit (rpu) i/o, pwm output, and external interrupt request input. (1) operation in control mode (1/2) port alternate function remark block type pdh0 d16/intpd0 data bus when memory expanded/ external interrupt request input pdh1 d17/intpd1 data bus when memory expanded/ external interrupt request input m-1 pdh2 d18/intpd2/toc4 data bus when memory expanded/ external interrupt request input/ real-time pulse unit (rpu) output m-2 pdh3 d19/intpd3 data bus when memory expanded/ external interrupt request input pdh4 d20/intpd4 data bus when memory expanded/ external interrupt request input m-1 pdh5 d21/intpd5/toc5 data bus when memory expanded/ external interrupt request input/ real-time pulse unit (rpu) output m-2 port dh pdh6 d22/intpd6/ intp100/tcud10 data bus when memory expanded/ external interrupt request input/ timer enc10 external capture trigger input/ real-time pulse unit (rpu) input m-3 chapter 14 port functions user?s manual u16031ej3v0ud 825 (2/2) port alternate function remark block type pdh7 d23/intpd7/ intp101/tclr10 data bus when memory expanded/ external interrupt request input/ timer enc10 external capture trigger input/ real-time pulse unit (rpu) input m-3 pdh8 d24/intpd8/to10 data bus when memory expanded/ external interrupt request input/ real-time pulse unit (rpu) output m-2 pdh9 d25/intpd9/ tiud10 data bus when memory expanded/ external interrupt request input/ real-time pulse unit (rpu) input pdh10 d26/intpd10/ intp110/tcud11 data bus when memory expanded/ external interrupt request input/ timer enc11 external capture trigger input/ real-time pulse unit (rpu) input pdh11 d27/intpd11/ intp111/tclr11 data bus when memory expanded/ external interrupt request input/ timer enc11 external capture trigger input/ real-time pulse unit (rpu) input m-3 pdh12 d28/intpd12/to11 data bus when memory expanded/ external interrupt request input/ real-time pulse unit (rpu) output m-2 pdh13 d29/intpd13/ tiud11 data bus when memory expanded/ external interrupt request input/ real-time pulse unit (rpu) input m-3 pdh14 d30/intpd14/ pwm0 data bus when memory expanded/ external interrupt request input/pwm output port dh pdh15 d31/intpd15/ pwm1 data bus when memory expanded/ external interrupt request input/pwm output m-2 chapter 14 port functions user?s manual u16031ej3v0ud 826 (2) i/o mode/control mode setting the port dh i/o mode setting is performed by the por t dh mode register (pmdh), and the control mode setting is performed by the port dh mode control regi ster (pmcdh) an port dh function control register (pfcdh). (a) port dh mode register (pmdh) the port dh mode register (pmdh) can be read or written in 16-bit units. if the higher 8 bits of pmdh are used as port dh mo de register h (pmdhh), and the lower 8 bits as port dh mode register l (pmdhl), these two 8-bit port mode re gisters can be read or written in 8-bit or 1-bit units. 15 pmdh15 7 pmdh7 pmdh 14 pmdh14 6 pmdh6 13 pmdh13 5 pmdh5 12 pmdh12 4 pmdh4 11 pmdh11 3 pmdh3 10 pmdh10 2 pmdh2 9 pmdh9 1 pmdh1 8 pmdh8 0 pmdh0 address fffff027h address fffff026h after reset ffffh bit position bit name function 15 to 0 pmdhn (n = 15 to 0) specifies input/output mode for pdhn pin. 0: output mode (output buffer on) 1: input mode (output buffer off) (b) port dh mode control register (pmcdh) the port dh mode control register (pmcdh) can be read or written in 16-bit units. if the higher 8 bits of pmcdh are used as port dh mode control register h (pmcdhh), and the lower 8 bits as port dh mode control register l (pmcdhl), these two 8-bit port mode registers can be read or written in 8-bit or 1-bit units. (1/2) 15 pmcdh15 7 pmcdh7 pmcdh 14 pmcdh14 6 pmcdh6 13 pmcdh13 5 pmcdh5 12 pmcdh12 4 pmcdh4 11 pmcdh11 3 pmcdh3 10 pmcdh10 2 pmcdh2 9 pmcdh9 1 pmcdh1 8 pmcdh8 0 pmcdh0 address fffff047h address fffff046h after reset 0000h bit position bit name function 15 pmcdh15 specifies operation mode of pdh15 pi n in combination with the pfcdh register. 0: i/o port mode 1: external interrupt request (intpd15) input mode/pwm1 output mode 14 pmcdh14 specifies operation mode of pdh14 pi n in combination with the pfcdh register. 0: i/o port mode 1: external interrupt request (intpd14) input mode/pwm0 output mode 13 pmcdh13 specifies operation mode of pdh13 pi n in combination with the pfcdh register. 0: i/o port mode 1: external interrupt request (intpd13) input mode/tiud11 input mode chapter 14 port functions user?s manual u16031ej3v0ud 827 (2/2) bit position bit name function 12 pmcdh12 specifies operation mode of pdh12 pi n in combination with the pfcdh register. 0: i/o port mode 1: external interrupt request (intpd12) input mode/to11 output mode 11 pmcdh11 specifies operation mode of pdh11 pi n in combination with the pfcdh register. 0: i/o port mode 1: external interrupt request (intpd11) input mode/timer enc11 external capture trigger (intp111) input mode/tclr11 input mode 10 pmcdh10 specifies operation mode of pdh10 pi n in combination with the pfcdh register. 0: i/o port mode 1: external interrupt request (intpd10) input mode/timer enc11 external capture trigger (intp110) input mode/tcud11 input mode 9 pmcdh9 specifies operation mode of pdh9 pin in combination with the pfcdh register. 0: i/o port mode 1: external interrupt request (intpd9) input mode/tiud10 input mode 8 pmcdh8 specifies operation mode of pdh8 pin in combination with the pfcdh register. 0: i/o port mode 1: external interrupt request (intpd8) input mode/to10 output mode 7 pmcdh7 specifies operation mode of pdh7 pin in combination with the pfcdh register. 0: i/o port mode 1: external interrupt request (intpd7) input mode/timer enc10 external capture trigger (intp101) input mode/tclr10 input mode 6 pmcdh6 specifies operation mode of pdh6 pin in combination with the pfcdh register. 0: i/o port mode 1: external interrupt request (intpd6) input mode/timer enc10 external capture trigger (intp100) input mode/tcud10 input mode 5 pmcdh5 specifies operation mode of pdh5 pin in combination with the pfcdh register. 0: i/o port mode 1: external interrupt request (intpd5) input mode/toc5 output mode 4 pmcdh4 specifies operation mode of pdh4 pin in combination with the pfcdh register. 0: i/o port mode 1: external interrupt request (intpd4) input mode 3 pmcdh3 specifies operation mode of pdh3 pin in combination with the pfcdh register. 0: i/o port mode 1: external interrupt request (intpd3) input mode 2 pmcdh2 specifies operation mode of pdh2 pin in combination with the pfcdh register. 0: i/o port mode 1: external interrupt request (intpd2) input mode/toc4 output mode 1 pmcdh1 specifies operation mode of pdh1 pin in combination with the pfcdh register. 0: i/o port mode 1: external interrupt request (intpd1) input mode 0 pmcdh0 specifies operation mode of pdh0 pin in combination with the pfcdh register. 0: i/o port mode 1: external interrupt request (intpd0) input mode chapter 14 port functions user?s manual u16031ej3v0ud 828 (c) port dh function control register (pfcdh) this register can be read or written in 8-bit or 1-bit units. if the higher 8 bits of the pfcdh are used as port dh function control register h (pfcdhh), and the lower 8 bits as port dh function control register l (p fcdhl), these registers can be read or written in 8- bit or 1-bit units. caution when the port mode is specified by the port dh mode control register (pmcdh), the setting of this register becomes invalid. ho wever, bit 0 is independent of the setting of the pmcdh0 bit of the pmcdh register. (1/3) 15 pfcdh15 7 pfcdh7 pfcdh 14 pfcdh14 6 pfcdh6 13 pfcdh13 5 pfcdh5 12 pfcdh12 4 0 11 pfcdh11 3 0 10 pfcdh10 2 pfcdh2 9 pfcdh9 1 0 8 pfcdh8 0 bmodcn address fffff057h address fffff056h after reset 0000h bit position bit name function 15 pfcdh15 specifies operation mode of pdh15 pin in control mode. 0: external interrupt request (intpd15) input mode 1: pwm1 output mode 14 pfcdh14 specifies operation mode of pdh14 pin in control mode. 0: external interrupt request (intpd14) input mode 1: pwm0 output mode 13 pfcdh13 specifies operation mode of pdh13 pin in control mode. 0: external interrupt request (intpd13) input mode 1: tiud11 input mode 12 pfcdh12 specifies operation mode of pdh12 pin in control mode. 0: external interrupt request (intpd12) input mode 1: to11 output mode 11 pfcdh11 specifies operation mode of pdh11 pin in control mode. 0: external interrupt request (intpd11) input mode 1: timer enc11 external capture trigger (intp111) input mode/tclr11 input mode there is no register that selects a timer e nc11 external capture trigger (intp111) input mode or tclr11 input mode. ? to use tclr11 input mode: mask the external capture trigger (intp111) of timer enc11, or use the cc111 register as a compare register. ? to use external capture trigger (intp111) of timer enc11: set the clr111 and clr110 bits of the tmc11 register to other than 00. chapter 14 port functions user?s manual u16031ej3v0ud 829 (2/3) bit position bit name function 10 pfcdh10 specifies operation mode of pdh10 pin in control mode. 0: external interrupt request (intpd10) input mode 1: timer enc11 external capture trigger (intp110) input mode/tcud10 input mode there is no register that selects a timer e nc11 external capture trigger (intp110) input mode or tcud11 input mode. ? to use tucd11 input mode: mask the external capture trigger (intp110) of timer enc11, or use the cc110 register as a compare register. ? to use external capture trigger (intp110) of timer enc11: set the t1cmd1 bit of the tum11 register to 0. 9 pfcdh9 specifies operation mode of pdh9 pin in control mode. 0: external interrupt request (intpd9) input mode 1: tiud10 input mode 8 pfcdh8 specifies operation mode of pdh8 pin in control mode. 0: external interrupt request (intpd8) input mode 1: to10 output mode 7 pfcdh7 specifies operation mode of pdh7 pin in control mode. 0: external interrupt request (intpd7) input mode 1: timer enc10 external capture trigger (intp101) input mode/tclr10 input mode there is no register that selects a timer e nc10 external capture trigger (intp101) input mode or tclr10 input mode. ? to use tclr10 input mode: mask the external capture trigger (intp101) of timer enc10, or use the cc101 register as a compare register. ? to use external capture trigger (intp101) of timer enc10: set the clr101 and clr100 bits of the tmc10 register to other than 00. 6 pfcdh6 specifies operation mode of pdh6 pin in control mode. 0: external interrupt request (intpd6) input mode 1: timer enc10 external capture trigger (intp100) input mode/tcud10 input mode there is no register that selects a timer e nc10 external capture trigger (intp100) input mode or tcud10 input mode. ? to use tucd10 input mode: mask the external capture trigger (intp100) of timer enc10, or use the cc100 register as a compare register. ? to use external capture trigger (intp100) of timer enc10: set the t1cmd0 bit of the tum10 register to 0. 5 pfcdh5 specifies operation mode of pdh5 pin in control mode. 0: external interrupt request (intpd5) input mode 1: toc5 output mode 2 pfcdh2 specifies operation mode of pdh2 pin in control mode. 0: external interrupt request (intpd2) input mode 1: toc4 output mode chapter 14 port functions user?s manual u16031ej3v0ud 830 (3/3) bit position bit name function 0 bmodcn specifies the operation mode of the d16 to d31 pins in the 16-bit mode (16-bit data bus). however, changing the value of the bmodcn bit from 0 to 1 is not reflected in the lbs register. 0: the d16 to d31 pins are not used for starting in the 16-bit mode (data bus width: 16/8 bits). 1: the d16 to d31 pins are not used for starting in the 16-bit mode (data bus width: 32/16/8 bits). caution the bmodcn bit is valid only when the 16-bit mode is specified in accordance with the status of the mode0 and mode1 pins. this bit is invalid if the 32-bit mode is specified. the bmodcn bit can be rewritten only once. if it is rewritten twice or more, the operation is not guaranteed. when the bmodcn bit = 1, the operation is the same as when the 32-bit mode is specified in accordance with the status of the mode0 and mode1 pins. chapter 14 port functions user?s manual u16031ej3v0ud 831 (3) selecting interrupt trigger mode the valid edges of the intpdn pin can be selected by program (n = 0 to 15). the level detection of the intpdn pin can also be selected. external interrupt rising edge specification regi ster dh (intrdh) and external interrupt falling edge specification register dh (intfdh) are used to specify the valid edge and level detection. (a) external interrupt rising edge specification register dh (int rdh) and external interrupt falling edge specification register dh (intfdh) these registers are used to specify t he trigger mode of an external in terrupt request (intpdn) from an external pin (n = 0 to 15). the correspondence betwe en each bit of this register and the external interrupt request controlled by that bit is as follows. ? intfdh0 and intrdh0 bits: intpd0 ? intfdh1 and intrdh1 bits: intpd1 ? intfdh2 and intrdh2 bits: intpd2 ? intfdh3 and intrdh3 bits: intpd3 ? intfdh4 and intrdh4 bits: intpd4 ? intfdh5 and intrdh5 bits: intpd5 ? intfdh6 and intrdh6 bits: intpd6 ? intfdh7 and intrdh7 bits: intpd7 ? intfdh8 and intrdh8 bits: intpd8 ? intfdh9 and intrdh9 bits: intpd9 ? intfdh10 and intrdh10 bits: intpd10 ? intfdh11 and intrdh11 bits: intpd11 ? intfdh12 and intrdh12 bits: intpd12 ? intfdh13 and intrdh13 bits: intpd13 ? intfdh14 and intrdh14 bits: intpd14 ? intfdh15 and intrdh15 bits: intpd15 the rising edge, falling edge, or both the rising and fa lling edges can be specified as the valid edge of the intpdn pin, independently for each pin. intrdh and intfdh registers can be read or written in 16-bit units. when the higher 8 bits of the intrdh and intfdh registers are used as intrdhh and intfdhh registers, and the lower 8 bits as intrdhl and in tfdhl registers, these registers can be read or written in 8-bit or 1-bit units. caution set the pmcdh register be fore setting the trigger mode. if the pmcdh register is set after the in trdh and intfdh registers have been set, an illegal interrupt may occur when the pmcdh register is set. chapter 14 port functions user?s manual u16031ej3v0ud 832 14 intr dh14 13 intr dh13 12 intr dh12 2 intr dh2 3 intr dh3 4 intr dh4 5 intr dh5 6 intr dh6 7 intr dh7 8 intr dh8 9 intr dh9 10 intr dh10 11 intr dh11 15 intr dh15 1 intr dh1 0 intr dh0 intrdh address fffffc36h after reset ffffh intf dh14 intf dh13 intf dh12 intf dh2 intf dh3 intf dh4 intf dh5 intf dh6 intf dh7 intf dh8 intf dh9 intf dh10 intf dh11 intf dh15 intf dh1 intf dh0 intfdh fffffc16h 0000h bit position bit name function specify trigger mode of intpdn pin. intfdhn intrdhn operation 0 0 falling edge 0 1 rising edge 1 0 level detection (low-level detection) notes 1, 2 1 1 both rising and falling edges 15 to 0 intfdhn, intrdhn (n = 0 to 15) notes 1. the level of the intpdn pin is sampled each time the main clock (f x ) is divided by four. when the low level of this pin is detected, an interrupt request is latched as the pdifn bit (n = 0 to 15). consequently, even when the cpu acknowledges t he interrupt and the pdifn bit of the interrupt control register (pdicn) is automatically cleared to 0, the pdifn bit is immediately set to 1 and interrupts occur consecutively. to avoid this stat us, make the intpdn pin of the external device inactive in the interrupt servicing routine, and forcibly clear the pdifn bit to 0. 2. if a level-detected interrupt reques t (intpdn) with a lower priority occurs while an interrupt is being serviced and if this level-detected interrupt requ est (intpdn) that has newly occurred becomes inactive before the current interrupt has been serv iced, the interrupt request of the new interrupt (intpdn) is held pending (n = 0 to 15). to not acknowledge the interrupt request of intpdn, clear the pdifn bit of the inte rrupt control register. chapter 14 port functions user?s manual u16031ej3v0ud 833 14.3.9 port cs port cs (pcs) is an 8-bit i/o port that can be se t to the input or output mode in 1-bit units. 7 pcs7 pcs 6 pcs6 5 pcs5 4 pcs4 3 pcs3 2 pcs2 1 pcs1 0 pcs0 address fffff008h after reset undefined bit position bit name function 7 to 0 pcsn (n = 7 to 0) i/o port remark for reading/writing of the i/o port, see 14.5 operation of port function . in addition to their function as port pins, in the control mo de, the port pins can also operate as the chip select signal outputs when memory is externally expanded and the read/ write strobe signal output to an external i/o. (1) operation in control mode port alternate function remark block type pcs0 cs0 chip select signal output pcs1 cs1 chip select signal output d-2 pcs2 cs2/iowr chip select signal output/write strobe signal output j-2 pcs3 cs3 chip select signal output pcs4 cs4 chip select signal output d-2 pcs5 cs5/iord chip select signal output/read strobe signal output j-2 pcs6 cs6 chip select signal output port cs pcs7 cs7 chip select signal output d-2 chapter 14 port functions user?s manual u16031ej3v0ud 834 (2) i/o mode/control mode setting the port cs i/o mode setting is performed by the por t cs mode register (pmcs), and the control mode setting is performed by the port cs mode control register (pmccs) and the port cs function control register (pfccs). (a) port cs mode register (pmcs) this register can be read or written in 8-bit or 1-bit units. 7 pmcs7 pmcs 6 pmcs6 5 pmcs5 4 pmcs4 3 pmcs3 2 pmcs2 1 pmcs1 0 pmcs0 address fffff028h after reset ffh bit position bit name function 7 to 0 pmcsn (n = 7 to 0) specifies input/output mode for pcsn pin. 0: output mode (output buffer on) 1: input mode (output buffer off) (b) port cs mode control register (pmccs) this register can be read or written in 8-bit or 1-bit units. 7 pmccs7 pmccs 6 pmccs6 5 pmccs5 4 pmccs4 3 pmccs3 2 pmccs2 1 pmccs1 0 pmccs0 address fffff048h after reset ffh bit position bit name function 7 pmccs7 specifies operation mode of pcs7 pin. 0: i/o port mode 1: cs7 output mode 6 pmccs6 specifies operation mode of pcs6 pin. 0: i/o port mode 1: cs6 output mode 5 pmccs5 specifies operation mode of pcs5 pin. 0: i/o port mode 1: cs5 output mode/iord output mode 4 pmccs4 specifies operation mode of pcs4 pin. 0: i/o port mode 1: cs4 output mode 3 pmccs3 specifies operation mode of pcs3 pin. 0: i/o port mode 1: cs3 output mode 2 pmccs2 specifies operation mode of pcs2 pin. 0: i/o port mode 1: cs2 output mode/iowr output mode 1 pmccs1 specifies operation mode of pcs1 pin. 0: i/o port mode 1: cs1 output mode 0 pmccs0 specifies operation mode of pcs0 pin. 0: i/o port mode 1: cs0 output mode chapter 14 port functions user?s manual u16031ej3v0ud 835 (c) port cs function control register (pfccs) this register can be read or written in 8-bit or 1-bit units. the llwr, luwr, ulwr and uuwr signals (hereafter referred to as the xxwr signal) and lldqm, ludqm, uldqm, and uudqm signals (hereafter referred to as the xxdqm signal) are alternate-function pins (xxwr/xxdqm), and the wr signal and we sig nal are alternate-function pins (wr/we). when an access to the sram interface device occurs immediately after an access to the sdram occurs, the rise of the xxdqm (xxwr) signal or the rise (inactive timing) of the we (wr) signal overlaps the sram interface device cycle, which may cause erroneous writ e. to prevent this, set the csdcn bit to 1 to delay the timing at which the csn signal falls by one clock. caution when the port mode is specified by th e port cs mode control register (pmccs), the pfccs setting becomes invalid. 7 csdc7 pfccs 6 csdc6 5 pfccs5 4 csdc4 3 0 note 1 2 pfccs2 1 0 note 1 0 csdc0 address fffff049h after reset 00h bit position bit name function 7, 6, 4, 0 csdcn notes 2, 3, 4 when this bit is set (1), the timing at wh ich the corresponding chip select signal (csn) falls is delayed by one clock. the output timing of signals other than csn is not affected. 5 pfccs5 specifies operation mode of pcs5 pin in control mode. 0: cs5 output mode 1: iord output mode note 5 2 pfccs2 specifies operation mode of pcs2 pin in control mode. 0: cs2 output mode 1: iowr output mode note 5 notes 1. be sure to clear bits 3 and 1 to 0. 2. be sure to set the btn0 and btn1 bits of the bc t0 and bct1 registers to 00 or 01 so that the device to which erroneous write may occur is connec ted to the cs space to which the csdcn bit is set (1). 3. do not change the value of the csdcn bit for t he cs space where the program under execution is allocated. 4. be sure to insert one or more address setup waits (required number of waits + 1) in the cs space for which the csdcn bit is set (1) using the asc register. 5. to output the iord and iowr sig nals during access to the extern al i/o other than by a dma flyby transfer, the ioen bit of the bcp register must be set. remark n = 0, 4, 6, 7 chapter 14 port functions user?s manual u16031ej3v0ud 836 14.3.10 port ct port ct (pct) is a 6-bit i/o port that can be se t to input or output mode in 1-bit units. 7 pct7 pct 6 0 5 pct5 4 pct4 3 pct3 2 pct2 1 pct1 0 pct0 address fffff00ah after reset undefined bit position bit name function 7, 5 to 0 pctn (n = 7, 5 to 0) i/o port remark for reading/writing of the i/o port, see 14.5 operation of port function . in addition to the port function, this port outputs, in the control mode, c ontrol signals to externally expand the memory and byte enable signals when sdram is accessed in byte units. (1) operation in control mode port alternate function remark block type pct0 llwr/llbe/lldqm write strobe signal output/ byte enable signal output/ output disable/write mask signal pct1 luwr/lube/ludqm write strobe signal output/ byte enable signal output/ output disable/write mask signal pct2 ulwr/ulbe/uldqm write strobe signal output/ byte enable signal output/ output disable/write mask signal pct3 uuwr/uube/uudqm write strobe signal output/ byte enable signal output/ output disable/write mask signal j-3 pct4 rd read strobe signal output pct5 we/wr write enable signal output/ write strobe signal output port ct pct7 bcyst bus cycle status signal output d-2 chapter 14 port functions user?s manual u16031ej3v0ud 837 (2) i/o mode/control mode setting the port ct i/o mode setting is performed by the po rt ct mode register (pmct), and the control mode setting is performed by the port ct mode control re gister (pmcct) and port ct function control register (pfcct). (a) port ct mode register (pmct) this register can be read or written in 8-bit or 1-bit units. 7 pmct7 pmct 6 1 5 pmct5 4 pmct4 3 pmct3 2 pmct2 1 pmct1 0 pmct0 address fffff02ah after reset ffh bit position bit name function 7, 5 to 0 pmctn (n = 7, 5 to 0) specifies input/output mode for pctn pin. 0: output mode (output buffer on) 1: input mode (output buffer off) (b) port ct mode control register (pmcct) this register can be read or written in 8-bit or 1-bit units. 7 pmcct7 pmcct 6 0 5 pmcct5 4 pmcct4 3 pmcct3 2 pmcct2 1 pmcct1 0 pmcct0 address fffff04ah after reset bfh bit position bit name function 7 pmcct7 specifies operation mode of pct7 pin. 0: i/o port mode 1: bcyst output mode 5 pmcct5 specifies operation mode of pct5 pin. 0: i/o port mode 1: we/wr output mode the we output mode and wr output mode are automatically selected by accessing the memory for which each mode is targeted. 4 pmcct4 specifies operation mode of pct4 pin. 0: i/o port mode 1: rd output mode 3 pmcct3 specifies operation mode of pct3 pin. 0: i/o port mode 1: uuwr output mode/uube output mode/uudqm output mode 2 pmcct2 specifies operation mode of pct2 pin. 0: i/o port mode 1: ulwr output mode/ulbe output mode/uldqm output mode 1 pmcct1 specifies operation mode of pct1 pin. 0: i/o port mode 1: luwr output mode/lube output mode/ludqm output mode 0 pmcct0 specifies operation mode of pct0 pin. 0: i/o port mode 1: llwr output mode/llbe output mode/lldqm output mode chapter 14 port functions user?s manual u16031ej3v0ud 838 (c) port ct function c ontrol register (pfcct) this register can be read or written in 8-bit or 1-bit units. cautions 1. when the port mode is specified by the port ct mode control register (pmcct), the setting of this register becomes invalid. 2. the timing of the xxdqm signal differs between when the xxwr output mode/xxdqm output mode is selected and when the xxbe output mode/xxdqm output mode is selected. however, if ei ther mode is selected, no problems occur when connecting to sdram. for the output timing of the xxdqm signal, refer to the timing diagrams (figures 5-9 to 5-11) in 5.3.5 sdram access (xx = uu, ul, lu, ll). 7 0 pfcct 6 0 5 0 4 0 3 pfcct3 2 pfcct2 1 pfcct1 0 pfcct0 address fffff04bh after reset 00h bit position bit name function 3 pfcct3 specifies operation mode of pct3 pin in control mode. 0: uuwr output mode/uudqm output mode 1: uube output mode/uudqm output mode the uuwr output mode and uudqm output mode, and the uube output mode and uudqm output mode are automatically selected by accessing the memory for which each mode is targeted. 2 pfcct2 specifies operation mode of pct2 pin in control mode. 0: ulwr output mode/uldqm output mode 1: ulbe output mode/uldqm output mode the ulwr output mode and uldqm output mode, and the ulbe output mode and uldqm output mode are automatically selected by accessing the memory for which each mode is targeted. 1 pfcct1 specifies operation mode of pct1 pin in control mode. 0: luwr output mode/ludqm output mode 1: lube output mode/ludqm output mode the luwr output mode and ludqm output mode, and the lube output mode and ludqm output mode are automatically selected by accessing the memory for which each mode is targeted. 0 pfcct0 specifies operation mode of pct0 pin in control mode. 0: llwr output mode/lldqm output mode 1: llbe output mode/ludqm output mode the llwr output mode and lldqm output mode, and the llbe output mode and ludqm output mode are automatically selected by accessing the memory for which each mode is targeted. chapter 14 port functions user?s manual u16031ej3v0ud 839 14.3.11 port cm port cm (pcm) is a 6-bit i/o port that can be set to the input or out put mode in 1-bit units. 7 0 pcm 6 0 5 pcm5 4 pcm4 3 pcm3 2 pcm2 1 pcm1 0 pcm0 address fffff00ch after reset undefined bit position bit name function 5 to 0 pcmn (n = 5 to 0) i/o port remark for reading/writing of the i/o port, see 14.5 operation of port function . in addition to their function as port pins, in the control mode , the port cm pins operate as the wait insertion signal input, bus hold control signal output, refresh request signal output from sdram, and a/d converter external trigger input. (1) operation in control mode port alternate function remark block type pcm0 wait wait insertion signal input c-1 pcm1 ? ? d-1 pcm2 hldak bus hold acknowledge signal output d-2 pcm3 hldrq bus hold request signal input c-1 pcm4 refrq refresh request signal output d-2 port cm pcm5 selfref/adtrg self-refresh request signal input f-5 chapter 14 port functions user?s manual u16031ej3v0ud 840 (2) i/o mode/control mode setting the port cm i/o mode setting is performed by the port cm mode register (pmcm), and the c ontrol mode setting is performed by the port cm mode control regist er (pmccm) and the port cm function control register (pfccm). (a) port cm mode register (pmcm) this register can be read or written in 8-bit or 1-bit units. 7 1 pmcm 6 1 5 pmcm5 4 pmcm4 3 pmcm3 2 pmcm2 1 pmcm1 0 pmcm0 address fffff02ch after reset ffh bit position bit name function 5 to 0 pmcmn (n = 5 to 0) specifies input/output mode for pcmn pin. 0: output mode (output buffer on) 1: input mode (output buffer off) (b) port cm mode control register (pmccm) this register can be read or written in 8-bit or 1-bit units. be sure to clear bit 1 to 0. if it is set to 1, the operation is not guaranteed. 7 0 pmccm 6 0 5 pmccm5 4 pmccm4 3 pmccm3 2 pmccm2 1 0 0 pmccm0 address fffff04ch after reset 3dh bit position bit name function 5 pmccm5 specifies operation mode of pcm5 pin. 0: i/o port mode 1: selfref input mode/a/d converter external trigger (adtrg) input mode 4 pmccm4 specifies operation mode of pcm4 pin. 0: i/o port mode 1: refrq output mode 3 pmccm3 specifies operation mode of pcm3 pin. 0: i/o port mode 1: hldrq input mode 2 pmccm2 specifies operation mode of pcm2 pin. 0: i/o port mode 1: hldak output mode 0 pmccm0 specifies operation mode of pcm0 pin. 0: i/o port mode 1: wait input mode chapter 14 port functions user?s manual u16031ej3v0ud 841 (c) port cm function control register (pfccm) this register can be read or written in 8-bit or 1-bit units. caution when the port mode is specified by th e port cm mode control register (pmccm), the pfccm setting becomes invalid. 7 0 pfccm 6 0 5 pfccm5 4 0 3 0 2 0 1 0 0 0 address fffff04dh after reset 00h bit position bit name function 5 pfccm5 specifies operation mode of pcm5 pin in control mode. 0: selfref input mode 1: a/d converter external trigger (adtrg) input mode chapter 14 port functions user?s manual u16031ej3v0ud 842 14.3.12 port cd port cd (pcd) is a 4-bit i/o port that can be set to the input or output mode in 1-bit units. 7 0 pcd 6 0 5 0 4 0 3 pcd3 2 pcd2 1 pcd1 0 pcd0 address fffff00eh after reset undefined bit position bit name function 3 to 0 pcdn (n = 3 to 0) i/o port remark for reading/writing of the i/o port, see 14.5 operation of port function . in addition to their function as port pins, the port cd pi ns operate as the clock enable signal output, bus clock output, column address strobe signal output, and row a ddress strobe signal output in the control mode. (1) operation in control mode port alternate function remark block type pcd0 sdcke clock enable signal output d-2 pcd1 busclk bus clock output d-1 pcd2 sdcas column address strobe signal output port cd pcd3 sdras row address strobe signal output d-2 chapter 14 port functions user?s manual u16031ej3v0ud 843 (2) i/o mode/control mode setting the port cd i/o mode setting is performed by the por t cd mode register (pmcd), and the control mode setting is performed by the port cd mode control register (pmccd). (a) port cd mode register (pmcd) this register can be read or written in 8-bit or 1-bit units. 7 1 pmcd 6 1 5 1 4 1 3 pmcd3 2 pmcd2 1 pmcd1 0 pmcd0 address fffff02eh after reset ffh bit position bit name function 3 to 0 pmcdn (n = 3 to 0) specifies input/output mode for pcdn pin. 0: output mode (output buffer on) 1: input mode (output buffer off) (b) port cd mode control register (pmccd) this register can be read or written in 8-bit or 1-bit units. 7 0 pmccd 6 0 5 0 4 0 3 pmccd3 2 pmccd2 1 pmccd1 0 pmccd0 address fffff04eh after reset 0fh bit position bit name function 3 pmccd3 specifies operation mode of pcd3 pin. 0: i/o port mode 1: sdras output mode 2 pmccd2 specifies operation mode of pcd2 pin. 0: i/o port mode 1: sdcas output mode 1 pmccd1 specifies operation mode of pcd1 pin. 0: i/o port mode 1: busclk output mode 0 pmccd0 specifies operation mode of pcd0 pin. 0: i/o port mode 1: sdcke output mode chapter 14 port functions user?s manual u16031ej3v0ud 844 14.4 configuration of reset, a2 to a15, and d0 to d15 pins the reset, a2 to a15, and d0 to d15 pins are not alter native function pins. their configuration is as follows. (1) configuration of reset, a2 to a15, and d0 to d15 pins pin function remark block type reset schmitt buffer n-1 a2 to a15 output buffer off control n-2 d0 to d15 output buffer off control and dir control n-3 (2) block diagram of reset, a2 to a15, and d0 to d15 pins figure 14-25. block diagram of type n-1 input signal reset figure 14-26. block diagram of type n-2 output buffer off signal note an internal bus note signal that becomes active in the idle and software stop modes, and by bus hold and reset remark n = 2 to 15 chapter 14 port functions user?s manual u16031ej3v0ud 845 figure 14-27. block diagram of type n-3 output buffer off signal note input buffer off signal dn internal bus note signal that becomes active in the idle and software stop modes, and by bus hold and reset remark n = 0 to 15 chapter 14 port functions user?s manual u16031ej3v0ud 846 14.5 operation of port function the operation of a port differs depending on whether it is set in the input or output mode, as follows. 14.5.1 writing to i/o port (1) in output mode a value can be written to the output latch (pn) by writi ng it to the port n register (pn). the contents of the output latch are output from the pin. once data is written to the output latch, it is hel d until new data is written to the output latch. (2) in input mode a value can be written to the output latch (pn) by writing it to the port n regi ster (pn). however, the status of the pin does not change because the output buffer is off. once data is written to the output latch, it is hel d until new data is written to the output latch. caution a bit manipulation instruction (clr1, set 1, not1) manipulates 1 bit but accesses a port in 8-bit units. if this instruction is executed to manipulate a port with a mixture of input and output bits, the contents of the output latch of a pin set in the input mode, in addition to the bit to be manipulated, ar e overwritten to the current input pin status and become undefined. 14.5.2 reading from i/o port (1) in output mode the contents of the output latch (pn) can be read by reading the port n register (pn). the contents of the output latch do not change. (2) in input mode the status of the pin can be read by re ading the port n register (pn). t he contents of the output latch (pn) do not change. 14.5.3 output status of alternate function in control mode the status of a port pin is not dependent upon the setting of the pmcn register and can be read by setting the port n mode register (pmn) to the input mode. if the pmn register is set to the output mode, the value of the port n register (pn) can be read in the port mode, and the output status of the al ternate function can be read in the control mode. chapter 14 port functions user?s manual u16031ej3v0ud 847 14.6 noise eliminator 14.6.1 interrupt input pin the following timing controller used to secure the noise elimination time is provided for the nmi and port pins that operate in the control mode when the valid edge is input. i nput signals that change within the noise elimination time are not internally acknowledged. table 14-1. noise elimination time of interrupt input pins pin noise elimination time nmi intp10 intp11 intp21 intp22 intp23 intp24 intp25 intp50 intp51 intp52 intp65 intp66 intp67 intpl0 intpl1 intpd0 intpd1 intpd2 intpd3 intpd4 intpd5 intpd6 intpd7 intpd8 intpd9 intpd10 intpd11 intpd12 intpd13 intpd14 intpd15 analog delay (80 ns typ.) cautions 1. the above non-m askable and maskable interrupt pins are used to release the standby mode. a timing circuit that c ontrols the clock is not emplo yed because the in ternal system clock is stopped in the standby mode. 2. the noise eliminator is valid only in the control mode. chapter 14 port functions user?s manual u16031ej3v0ud 848 14.6.2 a/d converter input pin the following timing controller used to secure the noise elimination time is provided for the adtrg pin. an input signal that changes within the noise elimination time is not internally acknowledged. table 14-2. noise elimination time of a/d converter input pin pin noise elimination time pcm5/adtrg/selfref analog delay (80 ns typ.) caution the noise eliminator is valid only in the control mode. 14.6.3 timer c and timer enc1 input pins the following noise filter that operates via clock sampling is provided for the pins of timers c and enc1 that operate when the valid edge is input. input signals that change within the noise elimination time are not internally acknowledged. table 14-3. noise elimination time of timer c and timer enc1 input pins pin noise elimination time intpc00/tic0 intpc01 intpc10/tic1 intpc11 intpc20/tic2 intpc21 intpc30/tic3 intpc31 intp100/tcud10 intp101/tclr10 tiud10 intp110/tcud11 intp111/tclr11 tiud11 selected from 0, 2, 3, or 5 clocks cautions 1. the noise filter of the above pins cannot acknowledge an input signal when the cpu clock is stopped because it uses clock sampling. 2. the noise eliminator is valid only in the control mode. chapter 14 port functions user?s manual u16031ej3v0ud 849 (1) noise elimination width setting re gisters c0 to c3 (ncwc0 to ncwc3) these registers are used to set the noise elimination width of the digital noise filter of the timer c input pins. these registers can be read or written in 8-bit units. be sure to clear bits 7 to 2 to 0. if they are set to 1, the operation is not guaranteed. do not overwrite this regist er during a count operation. 7 0 0 0 0 ncwc0 ncwc1 ncwc2 ncwc3 6 0 0 0 0 5 0 0 0 0 4 0 0 0 0 3 0 0 0 0 2 0 0 0 0 1 nccc01 nccc11 nccc21 nccc31 0 nccc00 nccc10 nccc20 nccc30 address fffff610h ffff630h fffff650h fffff670h after reset 02h 02h 02h 02h bit position bit name function specify number of clocks from which noise is to be eliminated. ncccn1 ncccn0 number of clocks from which noise is to be eliminated 0 0 0 (through input) 0 1 2 1 0 3 1 1 5 1, 0 ncccn1, ncccn0 remark 1 clock = f x /4 f x : main clock remark n = 0 to 3 chapter 14 port functions user?s manual u16031ej3v0ud 850 (2) noise elimination width setti ng registers 10, 11 (ncw10, ncw11) these registers are used to set the noise elimination width of the digital noi se filter of the timer enc1 input pins. these registers can be read or written in 8-bit units. cautions 1. whether the signal is input thro ugh or inverted can be sp ecified for each of the intp1n0/tcud1n and tiud1n pins. the noi se elimination width set by the ncfn, ncc1n, and ncc0n bits is for each timer and cannot be changed for each pin. 2. the setting of the srtcn bit is valid even when the in tp1n0/tcud1n pin is used as a capture trigger (intp1n0). 7 0 ncw10 6 0 5 srtc0 4 srti0 3 0 2 ncf0 1 ncc10 0 ncc00 address fffff5c0h after reset 02h 0 ncw11 0 srtc1 srti1 0 ncf1 ncc11 ncc01 fffff5f0h 02h bit position bit name function 5 srtcn specifies the input mode of the intp1n0/tcud1n pin. 0: through input 1: inverted this bit specifies whether the signal i nput from the intp1n0/tcud1n pin is input through to tmenc1n, or inverted. 4 srtin specifies the input mode of the tiud1n pin. 0: through input 1: inverted this bit specifies whether the signal input from the tiud1n pin is input through to tmenc1n, or inverted. 2 ncfn specifies the clock freq uency for noise elimination. 0: f x /4 1: f x /32 this bit selects a clock source for the noise filter. specify the number of clocks from which noise is to be eliminated. ncc1n note 1 ncc0n note 1 number of clocks from whic h noise is to be eliminated 0 0 0 (through input) note 2 0 1 2 1 0 3 1 1 5 1, 0 ncc1n, ncc0n notes 1. do not overwrite this bit during a count operation. 2. clear the ncfn bit to 0 to input the signal through. these bits are used to select the number of cl ocks from which noise is to be eliminated. remark n = 0, 1 chapter 14 port functions user?s manual u16031ej3v0ud 851 (a) relationship between ncw1n register set value and noise elimination width table 14-4. relationship between ncw1n regi ster set value and noise elimination width ncw1n register noise elimination width (ns) ncfn bit ncc1n bit ncc0n bit f x = 150 mhz f x = 133 mhz f x = 100 mhz remark 0 0 0 0 0 0 through 0 0 1 53.3 to 80.0 60.2 to 90.2 80 to 120 (1/(f x /4)) 2 0 1 0 80.0 to 106.7 90.2 to 120.3 120 to 160 (1/(f x /4)) 3 0 1 1 133.3 to 160.0 150.4 to 180.5 200 to 240 (1/(f x /4)) 5 1 0 1 426.7 to 640.0 481.2 to 721.8 640 to 960 (1/(f x /32)) 2 1 1 0 640.0 to 853.3 721.8 to 962.9 960 to 1,280 (1/(f x /32)) 3 1 1 1 1,066.7 to 1,280.0 1,203.0 to 1,443.6 1,600 to 1,920 (1/(f x /32)) 5 remarks 1. n = 0, 1 2. f x : main clock user?s manual u16031ej3v0ud 852 chapter 15 reset functions 15.1 overview ? reset function by reset input ? forced reset function by dcu (see chapter 16 debug function (dcu) .) ? low level is input to the reset pin for 100 s min. if an oscillation stabilization time of 100 s or longer is necessary, secure the low level for as long as the necessary oscillation stabilization time. ? reset generator (rg) eliminates noise from the reset pin. 15.2 configuration reset peripheral reset rg cpu core v850e/me2 selector sscg dcu remark sscg: spread spectrum frequency synthesizer phase locked loop (see chapter 8 clock generation function ) dcu: debug control unit (see chapter 16 debug function (dcu) ) rg: reset generator during a system reset, most pins (all excluding the busclk, reset, x2, ev dd , ev ss , iv dd , iv ss , pllv dd , pllv ss , oscv dd , oscv ss , uv dd , av dd , av refp , av refm , and av ss pins) enter the high-impedance state. therefore, a pull-up (or pull-down) resistor must be con nected to each pin of the address bus, data bus, and external bus control signals. if no resistor is connected, external memory may be destroyed when these pins enter the high-impedance state. for the same reason, the output sign als of the on-chip peripheral i/o func tions and other output ports should be handled in the same manner. chapter 15 reset functions user?s manual u16031ej3v0ud 853 15.3 operation when a low-level signal is input to the reset pin, a system reset is effected and each on-chip hardware is initialized. when the reset pin level changes from low to high, the reset state is released and the cpu starts program execution using osc output clock (f x ). register contents must be initialized as required in the program. when the reset signal is cleared, the oscill ation stabilization time is not inserted. when the reset signal is to be input (reset input on power applicati on or reset input when the software stop mode is released) while the clock oscillator is stopped, therefore, a low-level width longer than the oscillation stabilization time (100 ? ? ? ? chapter 15 reset functions user?s manual u16031ej3v0ud 854 the reset operation when the reset pin is input is illustrated below. figure 15-1. reset operation with reset pin input (1/2) (a) when idle mode is released power supply voltage h osc output clock (f x ) operation at f x = f x 8 (sscg output) initialized to operation at f x = f x (osc output) analog delay (eliminated as noise) analog delay (eliminated as noise) analog delay analog delay cpu operation starts. 5 system clocks min. sscg output stabilized (lock = 0) lock = 0 ckssel = 1 100 s min. secured internal system clock reset (input) internal system reset pll lockup time (2 ms min.) caution secure the sscg initialization time (100 s) by the low-level width of the reset signal. remark lock: bit 1 of lockr register ckssel: bit 1 of cks register chapter 15 reset functions user?s manual u16031ej3v0ud 855 figure 15-1. reset operation with reset pin input (2/2) (b) when software stop mode is released power supply voltage h osc output clock (f x ) operation at f x = f x 8 (sscg output) initialized to operation at f x = f x (osc output) analog delay (eliminated as noise) analog delay (elimintaed as noise) analog delay analog delay cpu operation starts. 5 system clocks min. sscg output stabilized (lock = 0) lock = 0 ckssel = 1 oscillation stabilization time (100 s min.) secured internal system clock reset (input) internal system reset pll lockup time (2 ms min.) caution secure the oscillation stabilizati on time and sscg initialization time (100 s) by the low-level width of the reset signal. remark lock: bit 1 of lockr register ckssel: bit 1 of cks register chapter 15 reset functions user?s manual u16031ej3v0ud 856 the power-on reset operation is illustrated below. figure 15-2. power-on reset operation power supply voltage osc output clock (f x ) operation at f x = f x 8 (sscg output) initialized to operation at f x = f x (osc output) analog delay (eliminated as noise) analog delay cpu operation starts. 5 system clocks min. sscg output stabilized (lock = 0) lock = 0 ckssel = 1 oscillation stabilization time (100 s min.) secured internal system clock reset (input) internal system reset pll lockup time (2 ms min.) cautions 1. secure the oscillation stabil ization time and sscg initialization time (100 s) by the low- level width of the reset signal. 2. supply power in the order of iv dd (internal power supply) and ev dd (external power supply). remark lock: bit 1 of lockr register ckssel: bit 1 of cks register chapter 15 reset functions user?s manual u16031ej3v0ud 857 the busclk operation at power-on reset is illustrated below. figure 15-3. busclk operation at power-on reset power supply voltage osc output clock (f x ) osc output insufficient osc output stabilized pll lockup time (2 ms min.) f x = f x 8 (sscg output) f x = f x (osc output) sscg output stabilized (lock = 0) internal system clock reset (input) busclk note <1> <2> <3> <4> <5> <6> remarks 1. <1>: power on <2>: osc oscillation stabilization <3>: reset cleared (counting of pll lockup time starts) <4>: pll lock status (lock bit of lockr register = 0) <5>: busclk = f clk /2 (ckm1 and ckm0 bits of bmc register = 01) <6>: set to f x = f x 8 (ckssel bit of cks register = 1) 2. the above operation is when busclk operate s on 1/2 the cycle of the internal system clock (f clk ). chapter 15 reset functions user?s manual u16031ej3v0ud 858 15.4 initialization initialize the contents of each regist er as necessary while programming. the initial values of the cpu, inter nal data ram, internal instruction ra m, and on-chip periphe ral i/o after a reset are shown below. table 15-2. initial value of cpu, intern al data ram, internal instruction ram, and on-chip peripheral i/o after reset (1/6) internal hardware register name initial value after reset general-purpose register (r0) 00000000h general-purpose register (r1 to r31) undefined program registers program counter (pc) 00100000h status saving registers during in terrupt (eipc, eipsw) undefined status saving registers during nmi (fepc, fepsw) undefined interrupt source register (ecr) 00000000h program status word (psw) 00000020h status saving registers during call t execution (ctpc, ctpsw) undefined status saving registers during except ion/debug trap (dbpc, dbpsw) undefined cpu system registers callt base pointer (ctbp) undefined internal instruction ram, internal data ram ? chapter 15 reset functions user?s manual u16031ej3v0ud 859 table 15-2. initial value of cpu, intern al data ram, internal instruction ram, and on-chip peripheral i/o after reset (2/6) internal hardware register name initial value after reset dma source address register nh (dsanh) (n = 0 to 3) undefined dma source address register nl (dsanl) (n = 0 to 3) undefined dma destination address register nh (ddanh) (n = 0 to 3) undefined dma destination address register nl (ddanl) (n = 0 to 3) undefined dma transfer count register n (dbcn) (n = 0 to 3) undefined dma addressing control register n (dadcn) (n = 0 to 3) 0000h dma channel control register n (dchcn) (n = 0 to 3) 00h dma terminal count output control register (dtoc) 01h dma trigger factor register n (dtfrn) (n = 0 to 3) 00h dma functions dma interface control register (difc) 00h interrupt control registers (p1ic0, p1ci1, p2ic1 to p2ic5, p5ic0 to p5ic2, p6ic5 to p6ic7, pdic0 to pdic15, plic0, plic1, ovcic0 to ovcic5, ccc0ic0, ccc0ic1, ccc1ic0, ccc1ic1, ccc2ic0, ccc2ic1, ccc3ic0, ccc3ic1, ccc4ic0, ccc4ic1, ccc5ic0, ccc5ic1, cmdic0 to cmdic3, cc10ic0, cc10ic1, cc11ic0, cc11ic1, cm10ic0, cm10ic1, cm11ic0, cm11ic1, ov1ic0, ov1ic1, ud1ic0, ud1ic1, dmaic0 to dmaic3, csi3ic0, csi3ic1, covf3ic0, covf3ic1, ureic0, ureic1, uric0, uric1, utic0, utic1, uific0, uific1, utoic0, utoic1, adic, us0bic to us2bic, usp2ic, usp4ic, rsumic) 47h interrupt mask register n (imrn) (n = 0 to 5) ffffh interrupt mask register nl (imrnl) (n = 0 to 5) ffh interrupt mask register nh (imrnh) (n = 0 to 5) ffh nmi reset status register (nrs) 00h in-service priority register (ispr) 00h external interrupt falling edge specification register n (intfn) (n = 1, 2, 5, 6, al) 00h external interrupt falling edge specification register dh (intfdh) 0000h external interrupt falling edge specification register dhl (intfdhl) 00h external interrupt falling edge specification register dhh (intfdhh) 00h external interrupt rising edge specification register n (intrn) (n = 1, al) 03h external interrupt rising edge specification register 2 (intr2) 3fh external interrupt rising edge specification register 5 (intr5) 07h external interrupt rising edge specification register 6 (intr6) e0h external interrupt rising edge specification register dh (intrdh) ffffh external interrupt rising edge specification register dhl (intrdhl) ffh external interrupt rising edge specification register dhh (intrdhh) ffh valid edge select register cn (sescn) (n = 0 to 3) 00h on-chip peripheral i/o interrupt/exception control functions valid edge select register 1n (sesa1n) (n = 0, 1) 00h chapter 15 reset functions user?s manual u16031ej3v0ud 860 table 15-2. initial value of cpu, intern al data ram, internal instruction ram, and on-chip peripheral i/o after reset (3/6) internal hardware register name initial value after reset clock control register (ckc) 03h clock source select register (cks) 00h sscg control register (sscgc) see 8.3.3 usb clock control register (uckc) 00h lock register (lockr) 01h oscillation stabilization time select register (osts) 04h power-save mode register (psmr) 00h clock generation functions power-save control register (psc) 00h system control command register (prcmd) undefined timer cn (tmcn) (n = 0 to 5) 0000h capture/compare registers cn0, cn1 (cccn0, cccn1) (n = 0 to 5) 0000h timer mode control register cn0 (tmccn0) (n = 0 to 5) 00h timer mode control register cn1 (tmccn1) (n = 0 to 5) 20h valid edge select register cn (sescn) (n = 0 to 3) 00h timer/counter functions (timer c) noise elimination width setting register cn (ncwcn) (n = 0 to 3) 02h timer dn (tmdn) (n = 0 to 3) 0000h compare register dn (cmdn) (n = 0 to 3) 0000h timer/counter functions (timer d) timer mode control register dn (n = 0 to 3) 00h timer enc1n (tmenc1n) (n = 0, 1) 0000h compare register 1n (cm1n) (n = 00, 01, 10, 11) 0000h capture/compare register 1n (cc1n) (n = 00, 01, 10, 11) 0000h timer unit mode register 1n (tum1n) (n = 0, 1) 00h timer control register 1n (tmc1n) (n = 0, 1) 00h capture/compare control register 1n (ccr1n) (n = 0, 1) 00h valid edge select register 1n (sesa1n) (n = 0, 1) 00h prescaler mode register 1n (prm1n) (n = 0, 1) 07h status register 1n (status1n) (n = 0, 1) 00h timer/counter functions (timer enc1) noise elimination width setting register 1n (ncw1n) (n = 0, 1) 02h uf0 ep0nak register (uf0e0n) 00h uf0 ep0nakall register (uf0e0na) 00h uf0 epnak register (uf0en) 00h uf0 epnak mask register (uf0enm) 00h uf0 sndsie register (uf0sds) 00h uf0 clr request register (uf0clr) 00h uf0 set request register (uf0set) 00h uf0 ep status n register (uf0epsn) (n = 0 to 2) 00h uf0 int status n register (uf0isn) (n = 0 to 4) 00h uf0 int mask n register (uf0imn) (n = 0 to 4) 00h uf0 int clear n register (uf0icn) (n = 0 to 4) ffh uf0 int & dmarq register (uf0idr) 00h uf0 dma status n register (uf0dmsn) (n = 0, 1) 00h on-chip peripheral i/o serial interface functions (usbf) uf0 fifo clear n register (uf0ficn) (n = 0, 1) 00h chapter 15 reset functions user?s manual u16031ej3v0ud 861 table 15-2. initial value of cpu, intern al data ram, internal instruction ram, and on-chip peripheral i/o after reset (4/6) internal hardware register name initial value after reset uf0 data end register (uf0dend) 00h uf0 gpr register (uf0gpr) 00h uf0 mode control register (uf0modc) 00h uf0 mode status register (uf0mods) 00h uf0 active interface number register (uf0aifn) 00h uf0 active alternative setting register (uf0aas) 00h uf0 alternative setting status register (uf0ass) 00h uf0 endpoint n interface mapping register (uf0enim) (n = 1 to 4, 7, 8) 00h uf0 ep0 read register (uf0e0r) undefined uf0 ep0 length register (uf0e0l) 00h uf0 ep0 setup register (uf0e0st) 00h uf0 ep0 write register (uf0e0w) undefined uf0 bulk out n register (uf0bon) (n = 1, 2) undefined uf0 bulk out n length register (uf0bo1l) (n = 1, 2) 00h uf0 bulk in n register (uf0bin) (n = 1, 2) undefined uf0 interrupt n register (uf0intn) (n = 1, 2) undefined uf0 device status register l (uf0dstl) 00h uf0 epn status register l (uf0ensl) (n = 0 to 4, 7, 8) 00h uf0 address register (uf0adrs) 00h uf0 configuration register (uf0cnf) 00h uf0 interface n register (uf0ifn) (n = 0 to 4) 00h uf0 descriptor length register (uf0dscl) 00h uf0 device descriptor register n (uf0ddn) (n = 0 to 17) 00h uf0 configuration/interface/endpoint descriptor register n (uf0cien) (n = 0 to 255) undefined usb function 0 dma channel select register (uf0cs) 0000h serial interface functions (usbf) usb function 0 buffer control register (uf0bc) 00h uartbn control register 0 (ubnctl0) (n = 0, 1) 10h uartbn control register 2 (ubnctl2) (n = 0, 1) ffffh uartbn status register (ubnstr) (n = 0, 1) 00h uartbn transmit data register (ubntx) (n = 0, 1) ffh uartbn receive data register ap (ubnrxap) (n = 0, 1) 00ffh uartbn receive data register (ubnrx) (n = 0, 1) ffh uartbn fifo control register 0 (ubnfic0) (n = 0, 1) 00h uartbn fifo control register 1 (ubnfic1) (n = 0, 1) 00h uartbn fifo control register 2 (ubnfic2) (n = 0, 1) 0000h uartbn fifo control register 2l (ubnfic2l) (n = 0, 1) 00h uartbn fifo control register 2h (ubnfic2h) (n = 0, 1) 00h uartbn fifo status register 0 (ubnfis0) (n = 0, 1) 00h on-chip peripheral i/o serial interface functions (uartb) uartbn fifo status register 1 (ubnfis1) (n = 0, 1) 10h chapter 15 reset functions user?s manual u16031ej3v0ud 862 table 15-2. initial value of cpu, intern al data ram, internal instruction ram, and on-chip peripheral i/o after reset (5/6) internal hardware register name initial value after reset clocked serial interface mode regist er 3n (csim3n) (n = 0, 1) 00h clocked serial interface clock select r egister 3n (csic3n) (n = 0, 1) 07h receive data buffer register 3n (sirb3n) (n = 0, 1) 0000h receive data buffer register 3nl (sirb3nl) (n = 0, 1) 00h receive data buffer register 3nh (sirb3nh) (n = 0, 1) 00h transmit data csi buffer register 3n (sfdb3n) 0000h transmit data csi buffer register 3nl (sfdb3nl) 00h transmit data csi buffer register 3nh (sfdb3nh) 00h csibuf status register 3n (sfa3n) (n = 0, 1) 20h transfer data length select register 3n (csil3n) (n = 0, 1) 00h serial interface functions (csi3) transfer data number specification r egister 3n (sfn3n) (n = 0, 1) 00h a/d converter mode register n (admn) (n = 0 to 2) 00h adc trigger select register (adts) 00h a/d conversion result register n (adcrn) (10 bits) (n = 0 to 7) undefined a/d converter a/d conversion result register nh (adcrnh) (8 bits) (n = 0 to 7) undefined pwm control register n (pwmcn) (n = 0, 1) 08h pwm modulo register n (pwmn) (n = 0, 1) 0000h pwm modulo register ln (pwmln) (n = 0, 1) 00h pwm pwm modulo register hn (pwmhn) (n = 0, 1) 00h ports (p1, p2, p5 to p7, pcs, pct, pcm, pcd) undefined port (pal) undefined port (pall) undefined port (palh) undefined port (pah) undefined port (pahl) undefined port (pahh) undefined port (pdh) undefined port (pdhl) undefined port (pdhh) undefined mode register (pm1, pm2, pm5 to pm7, pmcs, pmct, pmcm, pmcd) ffh mode register (pmal) ffffh mode register (pmall) ffh mode register (pmalh) ffh mode register (pmah) ffffh mode register (pmahl) ffh mode register (pmahh) ffh mode register (pmdh) ffffh mode register (pmdhl) ffh mode register (pmdhh) ffh mode control register (pmc1, pmc5 to pmc7) 00h mode control register (pmc2) 01h on-chip peripheral i/o port functions mode control register (pmccs) ffh chapter 15 reset functions user?s manual u16031ej3v0ud 863 table 15-2. initial value of cpu, intern al data ram, internal instruction ram, and on-chip peripheral i/o after reset (6/6) internal hardware register name initial value after reset mode control register (pmcct) bfh mode control register (pmccm) 3dh mode control register (pmccd) 0fh mode control register (pmcal) 0002h mode control register (pmcall) 02h mode control register (pmcalh) 00h mode control register (pmcah) 03ffh mode control register (pmcahl) ffh mode control register (pmcahh) 03h mode control register (pmcdh) 0000h mode control register (pmcdhl) 00h mode control register (pmcdhh) 00h function control registers (pfc1, pfc2, pfc5 to pfc7, pfccs, pfcct, pfccm) 00h function control register l (pfcall) 03h function control register (pfcdh) 0000h function control register (pfcdhl) 00h function control register (pfcdhh) 00h external interrupt falling edge specification register n (intfn) (n = 1, 2, 5, 6, al) 00h external interrupt falling edge specification register dh (intfdh) 0000h external interrupt falling edge specification register dhl (intfdhl) 00h external interrupt falling edge specification register dhh (intfdhh) 00h external interrupt rising edge specification register n (intrn) (n = 1, al) 03h external interrupt rising edge specification register 2 (intr2) 3fh external interrupt rising edge specification register 5 (intr5) 07h external interrupt rising edge specification register 6 (intr6) e0h external interrupt rising edge specification register dh (intrdh) ffffh external interrupt rising edge specification register dhl (intrdhl) ffh external interrupt rising edge specification register dhh (intrdhh) ffh noise elimination width setting register cn (ncwcn) (n = 0 to 3) 02h on-chip peripheral i/o port functions noise elimination width setting register 1n (ncw1n) (n = 0, 1) 02h caution ?undefined? in the above table is undefined a fter power-on-reset, or undefined as a result of data destruction when reset is input and the data write timing has been synchronized. for other reset signals, data is held in the same stat e it was in before the reset operation. user?s manual u16031ej3v0ud 864 chapter 16 debug function (dcu) the debug control unit (dcu) consists of three function units: an execution control unit (rcu) that realizes communication with jtag and execution of debug processi ng, a trace control unit (t rcu) that implements trace functions, and a trigger event unit (teu) that implements event detection functions. on-chip debugging of the v850e/me2 can be executed by connecting an n-wire type emulator. caution the debug function is supported by the v850e/me2, but whethe r this function can be used or not depends on the debugger used. 16.1 functional outline 16.1.1 debug function (1) debug interface this interface establishes communication with the host machine by using the drst, dck, dms, ddi, and ddo signals, via an n-wire type emulator. the commun ication specifications of jtag are used for this interface. it does not support a boundary scan function. (2) on-chip debug on-chip debugging can be performed if wiring and connectors for debugging are provided on the target system. connect an n-wire type emulator to the connector for debugging. (3) forced reset function the v850e/me2 can be forcibly reset. (4) break reset function the cpu can be started in the debug mode immediat ely after resetting the cpu has been cleared. (5) forced break function execution of the user program can be forcibly stopped (however, the handl er of the illegal instruction code exception (first address: 00000060h) cannot be used). (6) debug monitor function during debugging, a memory space for debugging, different from the user memory space, is used (background monitor format). the user program c an be executed starting from any address. while execution of the user program is stopped, t he user resources (such as memory and i/o) can be read/written, and the user program can be downloaded. chapter 16 debug function (dcu) user?s manual u16031ej3v0ud 865 (7) mask function (a) nmi and all maskable interrupt request signals can be masked. (b) when the debugger is connected, the reset pin input on the target board is masked by default (the reset pin input is masked when the debugger is st arted after power application to the v850e/me2). the reset pin input can be unmasked from the de bugger. if a signal is input to the reset pin during debugging (during run execution), however, the following problems may occur. ? the break function may malfunction. if this happens, restart. ? trace data may be illegal before and after reset pi n input. recovery will o ccur after the reset signal has been released. 16.1.2 trace function (1) pc trace (branch trace) function all branches (transition of processing) that o ccur during user program execution can be traced. the trace sources can be selected from 12 types of bran ch sources that are classified by function, and pc trace can be started from execution of an instruction at any address, and the trace source can be changed. two trace start triggers are available. (2) data trace function a data access issued by the cpu to any address can be traced in a range of 1 kb to 4 bytes. read or written data can be traced, and two data trace points are available. however, a data access issued by the dmac cannot be traced. (3) real-time trace mode branch and data access can be traced during r eal-time execution of the user program. the trace packet of the trace source detected is stored in a trace buffer, and output from trace interface pins (trcclk, trcdata0 to trcdata3, and trcend) (some tr ace packets may not be traced if no more trace packets can be stored in the trace buffer). (4) full trace mode (non-real-time trace mode) all branches and data accesses of the user program can be traced. in the full trace mode, the pipeline of the cpu is te mporarily held and instruction execution is stopped to secure the time of trace data output from trace interface pins, so that all trace packets can be correctly traced. chapter 16 debug function (dcu) user?s manual u16031ej3v0ud 866 16.1.3 event function (1) instruction event detection function event detection (10 events) via size comparison by t he execution pc and range event detection (up to four pairs with each pair consisting of two event s) of the execution pc can be executed. if an instruction event source is used as a break source , two breakpoints before execut ion of the instruction at which an event is detected and eight breakpoints after instruction execution can be detected. (2) access event detection function events can be detected as follows. ? comparison of access addresses (4 addresses) ? range of access address (up to two pairs with each pair consisting of two addresses) ? match or mismatch of access data ? data of specific bit by masking data ? access size an access event source is detected after access. if an access event source is used as a break source, a break occurs after several instructions have been executed after the instruction that i ssued the access that caused event detection. (3) sequential event detection function an event can be detected when up to four stages of ev ents have successively occurred or an event that clears successive occurrence of events can be detected. sequential events can be counted by using a 12-bit pass counter. chapter 16 debug function (dcu) user?s manual u16031ej3v0ud 867 16.2 connection with n-wire type emulator a connector for the emulator and a connection ci rcuit must be provided on the target system. figure 16-1. connecting n-wire type emulator to host machine high-speed n-wire emulator target system mictor connector (plug) (amp) mictor connector (receptacle (2-767004-2)) (amp) chapter 16 debug function (dcu) user?s manual u16031ej3v0ud 868 16.2.1 emulator connector the following table shows the pin functions of the emulator connector. table 16-1. emulator connector pin function pin no. pin name i/o direction pin function 1 gnd ? ? 2 gnd ? ? 3 dck emulator v850e/me2 clock for debug serial interface (emulator v850e/me2) 4 v dd ? +3.3 v (v850e/me2 emulator) (for monitoring power to target) 5 dms emulator v850e/me2 transfer mode select for debug serial interface (emulator v850e/me2) 6 drst emulator v850e/me2 dcu reset (emulator v850e/me2) 7 ddi emulator v850e/me2 data for debug serial interface (emulator v850e/me2) 8 port0_out emulator v850e/me2 general-purpose control signal 0 (emulator v850e/me2) 9 ddo v850e/me2 emulator data for debug serial interface (v850e/me2 emulator) 10 port1_out emulator v850e/me2 general-purpose control signal 1 (emulator v850e/me2) 11 (reserved 1) ? (leave this pin open) 12 port2_out emulator v850e/me2 general-purpose control signal 2 (emulator v850e/me2) 13 (reserved 2) ? (leave this pin open) 14 port0_in v850e/me2 emulator general-purpose control signal 0 (v850e/me2 emulator) 15 (reserved 3) ? (leave this pin open) 16 port1_in v850e/me2 emulator general-purpose control signal 1 (v850e/me2 emulator) 17 trcclk v850e/me2 emulator trace clock (v850e/me2 emulator) 18 port2_in v850e/me2 emulator general-purpose control signal 2 (v850e/me2 emulator) 19 trcend v850e/me2 emulator trace data end (v850e/me2 emulator) 20 trcce v850e/me2 emulator trace packet compression enable signal (v850e/me2 emulator) 21 trcdata0 v850e/me2 emulator trace data 0 (v850e/me2 emulator) 22 trcdata8 v850e/me2 emulator trace data 8 (v850e/me2 emulator) 23 trcdata1 v850e/me2 emulator trace data 1 (v850e/me2 emulator) 24 trcdata9 v850e/me2 emulator trace data 9 (v850e/me2 emulator) 25 trcdata2 v850e/me2 emulator trace data 2 (v850e/me2 emulator) 26 trcdata10 v850e/me2 emulator trace data 10 (v850e/me2 emulator) 27 trcdata3 v850e/me2 emulator trace data 3 (v850e/me2 emulator) 28 trcdata11 v850e/me2 emulator trace data 11 (v850e/me2 emulator) 29 trcdata4 v850e/me2 emulator trace data 4 (v850e/me2 emulator) 30 trcdata12 v850e/me2 emulator trace data 12 (v850e/me2 emulator) 31 trcdata5 v850e/me2 emulator trace data 5 (v850e/me2 emulator) 32 trcdata13 v850e/me2 emulator trace data 13 (v850e/me2 emulator) 33 trcdata6 v850e/me2 emulator trace data 6 (v850e/me2 emulator) 34 trcdata14 v850e/me2 emulator trace data 14 (v850e/me2 emulator) 35 trcdata7 v850e/me2 emulator trace data 7 (v850e/me2 emulator) 36 trcdata15 v850e/me2 emulator trace data 15 (v850e/me2 emulator) 37 gnd ? ? 38 gnd ? ? remark cautions are given on the next page. chapter 16 debug function (dcu) user?s manual u16031ej3v0ud 869 cautions 1. the connection of pins not supported by the v850e/me2 depends on the emulator used. 2. the pattern on the target board must satis fy the following conditions to support high-speed interfacing. ? lay out the pattern with the odd pi ns facing the device (v850e/me2). ? keep the pattern length to within 1.97 inches (50 mm). ? shield the clock signal with gnd. v850e/me2 mictor connector (receptacle (2-767004-2)) 2 38 1 37 16.2.2 recommended circuit example the following figure shows an example of the recommended ci rcuit of the emulator conne ctor (on the target system side). figure 16-2. example of recommended emulator connection circuit v850e/me2 dck dms ddi ddo drst trcclk trcend trcdata0 trcdata1 trcdata2 trcdata3 note 2 note 1 note 1 note 1 note 1 note 2 22 ? 22 ? 50 k ? 50 k ? 50 k ? 50 k ? 50 k ? 50 k ? 50 k ? 50 k ? 50 k ? 50 k ? 50 k ? 50 k ? note 1 22 ? note 1 22 ? note 1 22 ? note 1 22 ? note 1 22 ? dck dms ddi ddo (reserved 1) (reserved 2) (reserved 3) trcclk trcend trcdata0 trcdata1 trcdata2 trcdata3 trcdata4 trcdata5 trcdata6 trcdata7 gnd gnd v dd note 3 drst port0_out port1_out port2_out port0_in port1_in port2_in trcce trcdata8 trcdata9 trcdata10 trcdata11 trcdata12 trcdata13 trcdata14 trcdata15 gnd (open) (open) (open) +3.3 v +3.3 v 4.7 k ? 50 k ? 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 1, 37 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 2, 38 ground bus mictor connector (receptacle) 2-767004-2 notes 1. keep the pattern length to within 1.97 inches (50 mm). 2. shield the dck and trcclk signals by gnd. 3. for detecting power to the target board caution the recommended circuit example shown above assumes that a 3. 3 v interface is used. user?s manual u16031ej3v0ud 870 chapter 17 electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit iv dd iv dd pin ? 0.5 to +2.0 v iv ss iv ss pin ? 0.5 to +0.5 v ev dd ev dd pin, ev dd iv dd ? 0.5 to +4.6 v ev ss ev ss pin ? 0.5 to +0.5 v oscv dd oscv dd pin ? 0.5 to +4.6 v oscv ss oscv ss pin ? 0.5 to +0.5 v pllv dd pllv dd pin ? 0.5 to +2.0 v pllv ss pllv ss pin ? 0.5 to +0.5 v uv dd uv dd pin ? 0.5 to +4.6 v av dd av dd pin, av dd < ev dd 0.5 v ? 0.5 to +4.6 v supply voltage av ss av ss pin ? 0.5 to +0.5 v input voltage v i except for x1 pin , v i < ev dd + 0.3 v ? 0.5 to +4.6 v clock input voltage v k x1 pin ? 0.5 to oscv dd + 0.5 note v per pin 4.0 ma output current, low i ol total of all pins 100 ma per pin ? 4.0 ma output current, high i oh total of all pins ? 100 ma output voltage v o ev dd = 3.3 v 0.3 v ? 0.5 to ev dd + 0.5 note v analog input voltage v wasn ani0 to ani7 pins , av dd = 3.3 v 0.3 v ? 0.3 to av dd + 0.3 note v av refp ? 0.3 to av dd + 0.3 note v a/d converter reference input voltage av refm ? 0.3 to +0.3 v 30 pf < output pin load capacitance 50 pf ? 40 to +70 c operating ambient temperature t a output pin load capacitance 30 pf ? 40 to +85 c storage temperature t stg ? 60 to +150 c note be sure not to exceed the absolute maximum ratings (max. value) of each supply voltage. cautions 1. do not directly connect the output (or i/o) pins of ic products to each other, or to iv dd , ev dd , and gnd. direct connection of the output pins between an ic product and an external circuit is possible, if the output pins can be set to the high-i mpedance state and the output timing of the external circuit is designed to avoid output conflict. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the ab solute maximum ratings are rate d values at which the product is on the verge of suffering physical damage, a nd therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. the ratings and conditions indicated for dc characteristics and ac characteristics represent the quality assurance range during normal operation. chapter 17 electrical specifications user?s manual u16031ej3v0ud 871 capacitance (t a = 25 c, iv dd = iv ss = ev dd = ev ss = oscv dd = oscv ss = pllv dd = pllv ss = uv dd = av dd = av ss = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i 15 pf i/o capacitance c io 15 pf output capacitance c o f c = 1 mhz unmeasured pins returned to 0 v 15 pf operating conditions part number internal operation clock frequency (f x ) operating ambient temperature (t a ) supply voltage (v dd ) when external pin load capacitance c l = 50 pf, ? 40 to +70 c pd7030111agm-10-ueu pd7030111af1-10-ga3 10 to100 mhz when external pin load capacitance c l = 30 pf, ? 40 to +85 c when external pin load capacitance c l = 50 pf, ? 40 to +70 c pd7030111agm-13-ueu pd7030111af1-13-ga3 10 to133 mhz when external pin load capacitance c l = 30 pf, ? 40 to +85 c iv dd = 1.5 v 0.15 v pllv dd = 1.5 v 0.15 v ev dd = 3.3 v 0.3 v oscv dd = 3.3 v 0.3 v uv dd = 3.3 v 0.3 v av dd = 3.3 v 0.3 v pd7030111agm-15-ueu pd7030111af1-15-ga3 10 to150 mhz when external pin load capacitance c l = 50 pf, ? 40 to +70 c iv dd = 1.4 to1.65 v pllv dd = 1.4 to1.65 v ev dd = 3.3 v 0.3 v oscv dd = 3.3 v 0.3 v uv dd = 3.3 v 0.3 v av dd = 3.3 v 0.3 v chapter 17 electrical specifications user?s manual u16031ej3v0ud 872 recommended oscillator (a) ceramic resonator (i) murata mfg. co., ltd. (t a = ? 40 to +85 c) x1 x2 r d c2 c1 recommended circuit constant oscillation voltage range type part number oscillation frequency f x (mhz) c1 (pf) c2 (pf) r d (k ? ) min. (v) max. (v) oscillation stabilization time (max.) t ost (ms) cstce10m0g55-r0 10.000 on-chip on-chip 0 3.0 3.6 0.07 cstce12m5g55-r0 12.500 on-chip on-chip 0 3.0 3.6 0.08 cstce16m6v53-r0 16.625 on-chip on-chip 0 3.0 3.6 0.04 cstce18m0v53-r0 18.000 on-chip on-chip 0 3.0 3.6 0.03 surface mounting cstce18m7v53-r0 18.750 on-chip on-chip 0 3.0 3.6 0.03 cautions 1. connect the oscillator as cl ose as possible to the x1 and x2 pins. 2. do not route the wir ing near broken lines. 3. sufficiently evaluate the matching between the pd703111a and the resonator. chapter 17 electrical specifications user?s manual u16031ej3v0ud 873 (ii) tdk (t a = ? 40 to +85 c) x1 x2 r d c2 c1 recommended circuit constant oscillation voltage range type part number oscillation frequency f x (mhz) c1 (pf) c2 (pf) r d (k ? ) min. (v) max. (v) oscillation stabilization time (max.) t ost (ms) lead fcr10.0mc5 10.0 on-chip on-chip 0 3.0 3.6 0.076 surface mounting ccr18.0mxc7 18.0 on-chip on-chip 0 3.0 3.6 0.9 cautions 1. connect the oscillator as cl ose as possible to the x1 and x2 pins. 2. do not route the wir ing near broken lines. 3. sufficiently evaluate the matching between the pd703111a and the resonator. chapter 17 electrical specifications user?s manual u16031ej3v0ud 874 dc characteristics (t a = ? ? ? ? ? ? ? ? ? ? ? ? ? ? chapter 17 electrical specifications user?s manual u16031ej3v0ud 875 ac characteristics (t a = ? 40 to +85 c, iv dd = pllv dd = 1.5 v 0.15 v note , ev dd = oscv dd = 3.3 v 0.3 v, iv ss = ev ss = pllv ss = oscv ss = 0 v, output pin load capacitance: c l = 30 pf) (t a = ? 40 to +70 c, iv dd = pllv dd = 1.5 v 0.15 v note , ev dd = oscv dd = 3.3 v 0.3 v, iv ss = ev ss = pllv ss = oscv ss = 0 v, output pin load capacitance: c l = 50 pf) note consider the operation conditions when operating at 133.34 to150 mhz. ac test input measurement points (a) p11/sck0/intp11, p12/rxd0/si0, p20/nmi, p21/ rxd1/intp21, p23/sck1/intp23, p24/si1/intp24, pcm1, reset 0.75ev dd 0.2ev dd 0.75ev dd 0.2ev dd measurement points input signal ev dd 0 v (b) other than (a) 2.0 v 0.8 v 2.0 v 0.8 v measurement points input signal ev dd 0 v ac test output measurement points 0.7ev dd 0.2ev dd 0.7ev dd 0.2ev dd measurement points output signal chapter 17 electrical specifications user?s manual u16031ej3v0ud 876 load conditions cor l = 50 pf c l = 30 pf dut (device under test) caution at ? 40 to +70 c: if the load capacita nce exceeds 50 pf due to the circuit configur ation, make the load capacitance of this device 50 pf or lo wer by inserting a buffer, etc. at ? 40 to +85 c: if the load capacita nce exceeds 30 pf due to the circuit configur ation, make the load capacitance of this device 30 pf or lo wer by inserting a buffer, etc. chapter 17 electrical specifications user?s manual u16031ej3v0ud 877 (1) clock timing parameter symbol conditions min. max. unit x1 input cycle <1> t cyx including resonator error 52.5 100 ns output load capacitance ? < ? ? ? chapter 17 electrical specifications user?s manual u16031ej3v0ud 878 (2) output waveform (oth er than x1, busclk) parameter symbol conditions min. max. unit other than note 6 ns output rise time <7> t or note 8 ns other than note 6 ns output fall time <8> t of note 8 ns note p10/uclk/intp10, p12/rxd0/si0, p20/nmi, p21/ rxd1/intp21, p22/txd1/intp22, p24/si1/intp24, p50/dmarq0/intp50, p51/dmaak0/intp51, p52/ tc0/intp52, p53/dmarq1/tic0/intpc00, p54/dmaak1/intpc01, p55/tc1/toc0, p65/in tpc10/tic1/intp65, p66/intpc11/intp66, p67/toc1/intp67, p72/dmarq2/intpc20/ti c2, p73/dmaak2/intpc21, p74/tc2/toc2, p75/dmarq3/intpc30/tic3, p76/ dmaak3/intpc31, p77/tc3/toc3 <8> <7> signal other than x1, busclk (3) reset timing parameter symbol conditions min. max. unit reset pin high-level width <9> t wrsh 500 ns including oscillation stabilization time at power on and stop mode release. however, when the oscillation stabilization time exceeds 100 chapter 17 electrical specifications user?s manual u16031ej3v0ud 879 (4) sram, external rom, external i/o access timing (a) access timing (sram, external rom, external i/o) (1/2) parameter symbol conditions min. max. unit address, csn output delay time (from busclk ) <11> t dka 2 11 ns address, csn output hold time (from busclk ) <12> t hka 2 11 ns rd, iord delay time (from busclk ) <13> t dkrdl 1 11 ns rd, iord delay time (from busclk ) <14> t dkrdh 2 11 ns xxwr, iowr, wr delay time (from busclk ) <15> t dkwrl 2 11 ns xxwr, iowr, wr delay time (from busclk ) <16> t dkwrh 1 11 ns bcyst delay time (from busclk ) <17> t dkbsl 2 11 ns bcyst delay time (from busclk ) <18> t dkbsh 2 11 ns wait setup time (to busclk ) <19> t swk 6 ns wait hold time (from busclk ) <20> t hkw 2 ns data input setup time (to busclk ) <21> t skid 6 ns data input hold time (from busclk ) <22> t hkid 2 ns data output delay time (from busclk ) <23> t dkod1 2 11 ns data float delay time (from busclk ) <24> t hkod 2 11 ns remarks 1. observe at least one of the data input hold times t hrdid and t hkid . 2. n = 0 to 7 xx = uu, ul, lu, ll chapter 17 electrical specifications user?s manual u16031ej3v0ud 880 (a) access timing (sram, external rom, external i/o) (2/2) busclk (output) bcyst (output) [read] [write] [read] iord, rd (output) t1 tw t2 csn (output) <11> <12> <17> <13> <15> <16> <14> <22> <21> <24> <19> <20> <19> <20> a0 to a25 (output) wait (input) d0 to d31 (i/o) d0 to d31 (i/o) <18> <16> <24> <14> <17> <13> <15> <23> note [write] uuwr, ulwr (output) luwr, llwr (output) iowr, wr (output) note when a write cycle is executed with out inserting a t0 state immediat ely after a read cycle, the data output timing is delayed by a half clock (in sy nchronization with the fa lling edge of busclk). remarks 1. timing when the number of waits set by the dwc0 and dwc1 registers is 0. 2. broken lines indicate high impedance. 3. n = 0 to 7 chapter 17 electrical specifications user?s manual u16031ej3v0ud 881 (b) read timing (sram, external rom, external i/o) (1/2) parameter symbol conditions min. max. unit data input setup time (to address) <25> t said (2 + w + w d + w as ) t ? 17 ns data input setup time (to rd) <26> t srdid (1.5 + w + w d ) t ? 17 ns rd, iord low-level width <27> t wrdl (1.5 + w +w d ) t ? 6 ns rd, iord high-level width <28> t wrdh (0.5 + w as +i) t ? 6 ns delay time from address, csn to rd, iord <29> t dard (0.5 + w as ) t ? 7.5 ns delay time from rd, iord to address <30> t drda it ? 2 ns data input hold time (from rd, iord ) <31> t hrdid 0 ns delay time from rd, iord to data output <32> t drdod (0.5 + i) t ? 6 ns wait setup time (to address) <33> t saw note 1 (1 + w as ) t ? 17 ns wait setup time (to bcyst ) <34> t sbsw note 1 (1 + w as ) t ? 17 ns wait hold time (from bcyst ) <35> t hbsw note 1 (w as + w d ) t + 2 ns wait high-level width <36> t wwh note 2 t + 2 ns data output hold time (from xxwr, iowr, wr ) <37> t hwrod (0.5 + i) t ? 5.5 ns notes 1. at the first wait sampling 2. time necessary for releasing the wait state remarks 1. t = t cyk 2. w: number of waits inserted due to wait 3. w d : number of waits inserted by dwc0 and dwc1 registers 4. observe at least one of the data input hold times t hrdid and t hkid . 5. n = 0 to 7 xx = uu, ul, lu, ll 6. i: number of idle states 7. w as : number of address setup waits inserted by asc register 8. for the number of w and w d to be inserted, refer to 4.7.3 relationship between programmable wait and external wait . chapter 17 electrical specifications user?s manual u16031ej3v0ud 882 (b) read timing (sram, external rom, external i/o) (2/2) busclk (output) csn (output) a0 to a25 (output) rd, iord (output) d0 to d31 (i/o) t1 tw t2 <31> <28> <27> <30> note <32> <25> <26> <29> <33> <34> ti tasw <35> <37> <36> wait (input) bcyst (output) uuwr, ulwr (output) luwr, llwr (output) iowr, wr (output) uube,ulbe (output) lube, llbe (output) note in the case of the csn signal remarks 1. timing when the number of waits inserted by the dw c0 or dwc1 register is 0, the number of idle states inserted by the bcc register is 1, and the number of waits inse rted by the asc register is 1. 2. broken lines indicate high impedance. 3. n = 0 to 7 chapter 17 electrical specifications user?s manual u16031ej3v0ud 883 (c) write timing (sram, external rom, external i/o) (1/2) parameter symbol conditions min. max. unit wait setup time (to address) <33> t saw note 1 (1 +w as ) t ? 17 ns wait setup time (to bcyst ) <34> t sbsw note 1 (1 +w as ) t ? 17 ns wait hold time (from bcyst ) <35> t hbsw note 1 (w as +w d ) t +2 ns wait high-level width <36> t wwh note 2 t + 2 ns delay time from address, csn to xxwr, iowr, wr <38> t dawr (0.5 +w as ) t ? 7 ns address setup time (to xxwr, iowr, wr ) <39> t sawr (1.5 + w + w d + w as ) t ? 10 ns delay time from xxwr, iowr, wr to address <40> t dwra (0.5 + i) t ? 5 ns xxwr, iowr, wr high-level width <41> t wwrh (1 + i +w as ) t ? 5 ns xxwr, iowr, wr low-level width <42> t wwrl (1 +w + w d ) t ? 5 ns data output setup time (to xxwr, iowr, wr ) <43> t sodwr (1.5 + w as + w + w d ) t ? 5 ns data output hold time (from xxwr, iowr, wr ) <37> t hwrod (0.5 + i) t ? 5.5 ns notes 1. at the first wait sampling 2. time necessary for releasing the wait state remarks 1. t = t cyk 2. w: number of waits inserted due to wait 3. w d : number of waits inserted by dwc0 and dwc1 registers 4. n = 0 to 7 xx = uu, ul, lu, ll 5. i: number of idle states 6. w as : number of address setup waits inserted by asc register 7. for the number of w and w d to be inserted, refer to 4.7.3 relationship between programmable wait and external wait . chapter 17 electrical specifications user?s manual u16031ej3v0ud 884 (c) write timing (sram, external rom, external i/o) (2/2) <41> <39> <40> note <38> <42> <43> uuwr, ulwr (output) luwr, llwr (output) iowr, wr (output) <37> busclk (output) t1 tw t2 ti tasw <33> <34> wait (input) bcyst (output) <35> <36> d0 to d31 (i/o) csn (output) a0 to a25 (output) uube, ulbe (output) lube, llbe (output) note in the case of the csn signal remarks 1. timing when the number of waits inserted by the dw c0 or dwc1 register is 0, the number of idle states inserted by the bcc register is 1, and the number of waits inse rted by the asc register is 1. 2. broken lines indicate high impedance. 3. n = 0 to 7 chapter 17 electrical specifications user?s manual u16031ej3v0ud 885 (d) dma flyby transfer timing (transfe r from sram to external i/o) (1/2) parameter symbol conditions min. max. unit wait setup time (to busclk ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? chapter 17 electrical specifications user?s manual u16031ej3v0ud 886 (d) dma flyby transfer timing (transfe r from sram to external i/o) (2/2) <28> <27> <41> <38> <39> <29> <45> <42> <19> <20> <19> <20> <33> dmaakm (output) iord (output) iowr (output) rd (output) wait (input) bcyst (output) <34> csn (output) a0 to a25 (output) <35> busclk (output) t1 tf tw tasw <30> note <46> <40> <32> ti t2 <44> <36> d0 to d31 (i/o) uube, ulbe (output) lube, llbe (output) uuwr, ulwr (output) luwr, llwr (output) wr (output) note in the case of the csn signal remarks 1. timing when the number of waits inserted by the fwc register is 1, the number of idle states inserted by the fic register is 1, and the number of waits inserted by t he asc register is 1. 2. broken lines indicate high impedance. 3. n = 0 to 7, m = 0 to 3 chapter 17 electrical specifications user?s manual u16031ej3v0ud 887 (e) dma flyby transfer timing (transfer from external i/o to sram) (1/2) parameter symbol conditions min. max. unit wait setup time (to busclk ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? chapter 17 electrical specifications user?s manual u16031ej3v0ud 888 (e) dma flyby transfer timing (transfe r from external i/o to sram) (2/2) <41> <42> <40> note <28> <49> <30> <27> <32> d0 to d31 (i/o) <38> <39> <48> <29> rd (output) dmaakm (output) iowr (output) iord (output) <19> <20> <19> <20> <33> wait (input) bcyst (output) <34> <35> busclk (output) t1 tf tw tasw t2 ti <47> <36> csn (output) a0 to a25 (output) uube, ulbe (output) lube, llbe (output) uuwr, ulwr (output) luwr, llwr (output) wr (output) note in the case of the csn signal remarks 1. timing when the number of waits inserted by the fwc register is 1, the number of idle states inserted by the fic register is 1, and the number of waits inserted by t he asc register is 1. 2. broken lines indicate high impedance. 3. n = 0 to 7, m = 0 to 3 chapter 17 electrical specifications user?s manual u16031ej3v0ud 889 (5) page rom access timing (1/2) parameter symbol conditions min. max. unit wait setup time (to busclk ) <19> t swk 6 ns wait hold time (from busclk ) <20> t hkw 2 ns data input setup time (to busclk ) <21> t skid 6 ns data input hold time (from busclk ) <22> t hkid 2 ns off-page data input setup time (to address) <25> t said (2 +w +w d +w as ) t ? 17 ns off-page data input setup time (to rd) <26> t srdid (1.5 +w +w d ) t ? 17 ns data input hold time (from rd ) <31> t hrdid 2 ns delay time from rd to data output <32> t drdod (0.5 +i) t ? 6 ns on-page data input setup time (to address) <50> t soaid (2 +w +w pr ) t ? 17 ns remarks 1. t = t cyk 2. w: number of waits inserted due to wait 3. w d : number of waits inserted by dwc0 and dwc1 registers 4. w pr : number of waits inserted by prc register 5. i: number of idle states inserted wh en a write cycle is inserted after a read cycle 6. w as : number of address setup waits inserted by asc register 7. observe at least one of the data input hold times t hrdid and t hkid . 8. for the number of w and w d to be inserted, refer to 4.7.3 relationship between programmable wait and external wait . chapter 17 electrical specifications user?s manual u16031ej3v0ud 890 (5) page rom access timing (2/2) csn (output) busclk (output) t1 tdw twt2 <25> <26> <22> <20> <19> <19> <20> d0 to d31 (i/o) rd (output) wait (input) <21> to1 tprw tw to2 <50> <21> <22> <31> <20> <19> <20> <19> tasw <32> address note (output) uuwr, ulwr (output) luwr, llwr (output) wr (output) note on-page addresses and off-page addresses are shown below. prc register ma6 ma5 ma4 ma3 on-page address off-page address 0 0 0 0 a0 to a2 a3 to a25 0 0 0 1 a0 to a3 a4 to a25 0 0 1 1 a0 to a4 a5 to a25 0 1 1 1 a0 to a5 a6 to a25 1 1 1 1 a0 to a6 a7 to a25 remarks 1. timing in the following case. number of waits inserted by dwc0 or dwc1 register (tdw): 1 number of waits inserted by prc register (tprw): 1 number of waits inserted by asc register (tasw): 1 2. broken lines indicate high impedance. 3. n = 0 to 7 chapter 17 electrical specifications user?s manual u16031ej3v0ud 891 (6) sdram access timing (a) read timing (sdram access) (1/2) parameter symbol conditions min. max. unit address delay time (from busclk ) <11> t dka 2 11 ns bcyst delay time (from busclk ) <51> t dkbc 2 11 ns csn delay time (from busclk ) <52> t dkcs 2 11 ns sdras delay time (from busclk ) <53> t dkras 2 11 ns sdcas delay time (from busclk ) <54> t dkcas 2 11 ns xxdqm delay time (from busclk ) <55> t dkdqm 2 11 ns sdcke delay time (from busclk ) <56> t dkcke 2 11 ns data input setup time (sdram read, from busclk ) <57> t sdrmk 6 ns data input hold time (sdram read, from busclk ) <58> t hkdrm 2 ns delay time from busclk to data output <59> t dsdod (0.5 +i) t ns caution if an sram (external i/o) cycle that uses the xxwr signal is ge nerated immediately after a read cycle to sdram, an sram (external i/o) writing erro r may occur. in this case, set the bcc register to insert an idle state in the sdram space or execute a countermeasure using external circuits. however, no writing error occurs in a synchroni zation design in which th e xxwr signal is sampled using busclk. remarks 1. t = t cyk 2. i: number of idle states 3. n = 1, 3, 4, 6 xx = uu, ul, lu, ll chapter 17 electrical specifications user?s manual u16031ej3v0ud 892 (a) read timing (sdram access) (2/2) sdclk (output) t0 tact tbcw tread tlate tlate sdram: csn (output) d0 to d31 (i/o) sdcke (output) a12 (output) a2 to a11 (output) <51> <52> <11> <11> <11> <11> <11> <53> <54> <55> <57> <58> <51> <52> <53> <54> <55> <11> bcyst (output) sdras (output) sdcas (output) we (output) data address bank address (output) <59> bank address, a2 to a11, address other than a12 (output) <11> bank address row address row address column address <56> <56> uudqm, uldqm (output) ludqm, lldqm (output) remarks 1. number of waits inserted by bcw1n and bc w0n bits of the scrn register (tbcw): 2 2. broken lines indicate high impedance. 3. n = 1, 3, 4, 6 chapter 17 electrical specifications user?s manual u16031ej3v0ud 893 (b) write timing (sdram access) (1/2) parameter symbol conditions min. max. unit address delay time (from busclk ) <11> t dka 2 11 ns bcyst delay time (from busclk ) <51> t dkbc 2 11 ns csn delay time (from busclk ) <52> t dkcs 2 11 ns sdras delay time (from busclk ) <53> t dkras 2 11 ns sdcas delay time (from busclk ) <54> t dkcas 2 11 ns xxdqm delay time (from busclk ) <55> t dkdqm 2 11 ns sdcke delay time (from busclk ) <56> t dkcke 2 11 ns we delay time (from busclk ) <60> t dkwe 2 11 ns data output delay time (from busclk ) <61> t dkdt 2 11 ns data float delay time (from busclk ) <62> t hzkdt 2 11 ns caution if an sram (external i/o) cycle that uses the xxwr signal is ge nerated immediately after a read cycle to sdram, an sram (external i/o) writi ng error may occur. in this case, execute a countermeasure using external circuits. however, no writing error occurs in a synchroni zation design in which th e xxwr signal is sampled using busclk. remark n = 1, 3, 4, 6 xx = uu, ul, lu, ll chapter 17 electrical specifications user?s manual u16031ej3v0ud 894 (b) write timing (sdram access) (2/2) busclk (output) bank address, a2 to a11, address other than a12 (output) t0 tact tbcw twr <11> d0 to d31 (i/o) sdcke (output) a12 (output) a2 to a11 (output) <51> <52> <11> <11> <11> <11> <11> <53> <54> <60> <55> <61> <62> <51> <52> <53> <54> <60> <55> <11> bcyst (output) sdcas (output) we (output) sdras (output) sdram: csn (output) data address bank address (output) bank address row address row address column address <56> <56> uudqm, uldqm (output) ludqm, lldqm (output) remarks 1. number of waits inserted by bcw1n and bcw0n bits of scrn register (tbcw): 2 2. broken lines indicate high impedance. 3. n = 1, 3, 4, 6 chapter 17 electrical specifications user?s manual u16031ej3v0ud 895 (c) dma flyby transfer timing (transfe r from external i/o to sdram) (1/2) parameter symbol conditions min. max. unit address delay time (from busclk ? ? ? chapter 17 electrical specifications user?s manual u16031ej3v0ud 896 (c) dma flyby transfer timing (transfe r from external i/o to sdram) (2/2) busclk (output) bank address, a2 to a11, address other than a12 (output) t0 tact tbcw tf <11> d0 to d31 (i/o) sdcke (output) iowr (output) iord (output) a12 (output) a2 to a11 (output) <11> <11> <11> dmaakx (output) <51> h <52> <11> <11> <11> <11> <11> <53> <54> <60> <55> <51> <52> <53> <54> <60> <55> <11> bcyst (output) sdcas (output) we (output) sdras (output) sdram: csn (output) bank address (output) twr t0 t1 address bank address address row address address row address column address <65> <66> <104> <102> <56> <56> <103> <14> <13> uudqm, uldqm (output) ludqm, lldqm (output) data address remarks 1. broken lines indicate high impedance. 2. n = 1, 3, 4, 6 x = 0 to 3 chapter 17 electrical specifications user?s manual u16031ej3v0ud 897 (7) dmac timing (a) level mode (1/3) parameter symbol conditions min. max. unit dmarqn setup time (to busclk ) <63> t sdrk 2-cycle/flyby transfer 8 ns 4t cpu ? 20 note 1 ns 2-cycle transfer 0 6t cpu ? 20 note 2 ns dmarqn hold time (from dmaakn ) <64> t hkdr flyby transfer 0 2t bus +w as + w fw + w ic +2t cpu ? 20 ns 2-cycle transfer 0 nt cpu +13 note 3 ns dmaakn output delay time (from busclk ) <65> t dkda flyby transfer 0 13 ns 2-cycle transfer 0 nt cpu +13 note 3 ns dmaakn output hold time (from busclk ) <66> t hkda flyby transfer 0 13 ns notes 1. second dma transfer request disable timing in single transfer. the accesses is as follows. transfer source transfer desti nation speculative read function internal data ram external memory/ internal instruction ram provided/none external memory internal data ram provided/none however, when the speculative read function is not provided, the following conditions apply. ? busclk = internal system clock (f clk ) ? external memory access wait setting = 0 2. second dma transfer request disable timing in single transfer. the access is other than that shown in the table in note 1. 3. n is as follows. ckm1 ckm0 busclk division ratio with respect to internal system clock (f clk ) n 0 0 f clk /1 1 0 1 f clk /2 2 1 0 f clk /3 3 1 1 f clk /4 4 remarks 1. n = 0 to 3 2. t bus = 1 busclk cycle 3. t cpu = 1 internal system clock cycle 4. w as = number of address setup waits inserted by asc register w fw = number of data waits inserted by fwc register w ic = number of idle states inserted by fic register chapter 17 electrical specifications user?s manual u16031ej3v0ud 898 (a) level mode (2/3) parameter symbol conditions min. max. unit note 1 2t cpu ? ? ? ? ? chapter 17 electrical specifications user?s manual u16031ej3v0ud 899 (a) level mode (3/3) busclk (output) <64> <65> <66> <68> <63> dmaakn (output) dmarqn (input) tcn (output) <69> <67> remarks 1. the minimum dmaakn inactive time is as follows. transfer mode transfer source transfer destination inactive time external memory/ external i/o on-chip peripheral i/o external memory/ external i/o on-chip peripheral i/o/ internal instruction ram 4t cpu internal data ram internal data ram 5t cpu internal data ram external memory/ external i/o on-chip peripheral i/o/ internal instruction ram 9t cpu single transfer, single-step transfer external memory/ external i/o on-chip peripheral i/o internal data ram 9t cpu block transfer ? ? chapter 17 electrical specifications user?s manual u16031ej3v0ud 900 (b) mask mode (1/3) parameter symbol conditions min. max. unit dmarqn setup time (to busclk ) <63> t sdrk 2-cycle/flyby transfer 8 ns dmarqn hold time 1 (from dmaakn ) <70> t hkdr1 2-cycle/flyby transfer to dmaakn ns 2-cycle transfer 0 3t bus ? 8 note 1 ns dmarqn hold time 2 (from busclk ) note 2 (dmaakn = ?h? sample) <71> t hkdr2 flyby transfer 0 4t bus ? 8 note 3 ns 2-cycle transfer 0 nt cpu +13 note 4 ns dmaakn output delay time (from busclk ) <65> t dkda flyby transfer 0 13 ns 2-cycle transfer 0 nt cpu +13 note 4 ns dmaakn output hold time (from busclk ) <66> t hkda flyby transfer 0 13 ns notes 1. the second transfer request disable timing in single transfer. to busclk : since the dmaakn is output asynchronous ly with busclk, in accordance with the dmaakn rising ?h? sample prescripti on, if dmaakn = ?h? is output at the timing in which it cannot be sampled at the busclk (setup time < 8 ns), +1t bus is added. 2. time to dmaakn high level from busclk after dmaakn rises 3. the second dma transfer request disable timing in single transfer. 4. n is as follows. ckm1 ckm0 busclk division rati o to internal system clock (f clk ) n 0 0 f clk /1 1 0 1 f clk /2 2 1 0 f clk /3 3 1 1 f clk /4 4 remarks 1. n = 0 to 3 2. t bus = 1 busclk cycle 3. t cpu = 1 internal system clock cycle chapter 17 electrical specifications user?s manual u16031ej3v0ud 901 (b) mask mode (2/3) parameter symbol conditions min. max. unit note 1 2t cpu ? 8 note 2 ns 2-cycle transfer note 3 6t cpu ? 8 note 2 ns dmaakn low-level width <67> t wdal flyby transfer 2t bus +w as +w fw +w ic ? 8 ns tcn output delay time (from busclk ) <68> t dktc 2-cycle/flyby transfer 2 13 ns tcn output hold time (from busclk ) <69> t hktc 2-cycle/flyby transfer 2 13 ns notes 1. normal operation (dmaakn output width = memory controller output) 2. the access is as follows. transfer source transfer desti nation speculative read function internal data ram external memory/ internal instruction ram provided/none external memory internal data ram provided/none however, when the speculative read function is not provided, the following conditions apply. ? busclk = internal system clock (f clk ) ? external memory access wait setting = 0 3. when selecting a mode in which dmaakn out put width = memory controller output +4t cpu remarks 1. n = 0 to 3 2. t bus = 1 busclk cycle 3. t cpu = 1 internal system clock cycle 4. w as = number of address setup waits inserted by asc register w fw = number of data waits inserted by fwc register w ic = number of idle states inserted by fic register chapter 17 electrical specifications user?s manual u16031ej3v0ud 902 (b) masks mode (3/3) busclk (output) <70> <65> <68> <63> dmaakn (output) dmarqn (input) tcn (output) <69> <71> <66> <67> remarks 1. the minimum dmaakn inactive time is as follows. transfer mode transfer source transfer destination inactive time external memory/ external i/o on-chip peripheral i/o external memory/ external i/o on-chip peripheral i/o/ internal instruction ram 4t cpu internal data ram internal data ram 5t cpu internal data ram external memory/ external i/o on-chip peripheral i/o/ internal instruction ram 9t cpu single transfer, single-step transfer external memory/ external i/o on-chip peripheral i/o internal data ram 9t cpu block transfer ? ? chapter 17 electrical specifications user?s manual u16031ej3v0ud 903 (c) edge mode (1/3) parameter symbol conditions min. max. unit dmarqn hold time <64> t hkdr 2-cycle/flyby transfer 2t cpu ns dmarqn high-level time 1 (from dmarqn ) <72> t wdrh1 2-cycle/flyby transfer 2t cpu ns dmarqn high-level time 2 (from dmaakn ) <73> t wdrh2 2-cycle/flyby transfer 0 ns 2-cycle transfer 0 nt cpu +13 note ns dmaakn output delay time (from busclk ) <65> t dkda flyby transfer 0 13 ns 2-cycle transfer 0 nt cpu +13 note ns dmaakn output hold time (from busclk ) <66> t hkda flyby transfer 0 13 ns note n is as follows. ckm1 ckm0 busclk ratio to internal system clock (f clk ) n 0 0 f clk /1 1 0 1 f clk /2 2 1 0 f clk /3 3 1 1 f clk /4 4 remarks 1. n = 0 to 3 2. t cpu = 1 internal system clock cycle chapter 17 electrical specifications user?s manual u16031ej3v0ud 904 (c) edge mode (2/3) parameter symbol conditions min. max. unit note 1 2t cpu ? 8 note 2 ns 2-cycle transfer note 3 6t cpu ? 8 note 2 ns dmaakn low-level width <67> t wdal flyby transfer 2t bus +w as +w fw +w ic ? 8 ns tcn output delay time (from busclk ) <68> t dktc 2-cycle/flyby transfer 2 13 ns tcn output hold time (from busclk ) <69> t hktc 2-cycle/flyby transfer 2 13 ns notes 1. time to dmaakn high level from busclk after dmaakn rises 2. the access is as follows. transfer source transfer desti nation speculative read function internal data ram external memory/ internal instruction ram provided/none external memory internal data ram provided/none however, when the speculative read function is not provided, the following conditions apply. ? busclk = internal system clock (f clk ) ? external memory access wait setting = 0 3. normal operation (dmaakn output width = memory controller output ) remarks 1. n = 0 to 3 2. t bus = 1 busclk cycle 3. t cpu = 1 internal system clock cycle 4. w as = number of address setup waits inserted by asc register w fw = number of data waits inserted by fwc register w ic = number of idle states inserted by fic register chapter 17 electrical specifications user?s manual u16031ej3v0ud 905 (c) edge mode (3/3) busclk (output) <64> <65> <66> <68> dmaakn (output) dmarqn (input) tcn (output) <69> <72> <67> <73> remarks 1. the minimum dmaakn inactive time is as follows. transfer mode transfer source transfer destination inactive time external memory/ external i/o on-chip peripheral i/o external memory/ external i/o on-chip peripheral i/o/ internal instruction ram 4t cpu internal data ram internal data ram 5t cpu internal data ram external memory/ external i/o on-chip peripheral i/o/ internal instruction ram 9t cpu single transfer, single-step transfer external memory/ external i/o on-chip peripheral i/o internal data ram 9t cpu block transfer ? ? chapter 17 electrical specifications user?s manual u16031ej3v0ud 906 (8) bus hold timing (1/2) parameter symbol conditions min. max. unit hldrq setup time (to busclk ? chapter 17 electrical specifications user?s manual u16031ej3v0ud 907 (8) bus hold timing (2/2) busclk (output) ti d0 to d31 (i/o) <74> th th th ti t0 <75> <75> <74> <81> <76> <78> <82> <77> <76> <79> <80> a0 to a25 (output) address data hldrq (input) hldak (output) csn (output) bcyst (output) iord, rd (output) iowr, we/wr (output) note (output) <74> wait (input) undefined sdras, sdcas (output) note uuwr/uube/uudqm, ulwr/ulbe/uldqm, lu wr/lube/ludqm, llwr/llbe/lldqm remarks 1. broken lines indicate high impedance. 2. n = 0 to 7 chapter 17 electrical specifications user?s manual u16031ej3v0ud 908 (9) interrupt timing (1/2) parameter symbol conditions min. max. unit nmi high-level width <83> t wnih 500 ns nmi low-level width <84> t wnil 500 ns when noise elimination has been set (number of set elimination clocks +1)/(f x /4) +10 ns intpcm0, intpcm1 pin (m = 0 to 3) high-level width <85> t witch when clock-through has been set 1/(f x /4) 2 +10 ns when noise elimination has been set (number of set elimination clocks +1)/(f x /4) +10 ns intpcm0, intpcm1 pin (m = 0 to 3) low-level width <86> t witcl when clock-through has been set 1/(f x /4) 2 +10 ns noise elimination clock = f x /4 selected (number of set elimination clocks +1)/(f x /4) +10 ns when noise elimination has been set noise elimination clock = f x /32 selected (number of set elimination clocks +1)/(fx/32) +10 ns intpa pin high-level width <87> t wit1h when clock-through has been set note noise elimination clock = f x /4 selected 1/(f x /4) 2 +10 ns noise elimination clock = f x /4 selected (number of set elimination clocks +1)/(f x /4) +10 ns when noise elimination has been set noise elimination clock = f x /32 selected (number of set elimination clocks +1)/(f x /32) +10 ns intpa pin low-level width <88> t wit1l when clock-through has been set note noise elimination clock = f x /4 selected 1/(fx/4) 2 +10 ns intpb high-level width <89> t witph both edge and level detection 500 +1/(fx/4) +10 ns intpb low-level width <90> t witpl both edge and level detection 500 +1/(fx/4) +10 ns note when clock-through has been set, do not select a noise elimination clock of f x /32. remarks 1. the noise elimination clock and clock-through are set values of the ncwc0 to ncwc3, ncw10, and ncw11 registers. 2. f x : main clock 3. a = 100, 101, 110, 111 b = 10, 11, 21 to 25, 50 to 52, 65 to 67, d0 to d15, l0, l1 chapter 17 electrical specifications user?s manual u16031ej3v0ud 909 (9) interrupt timing (2/2) <83> <84> nmi (input) <85> <86> intpcm0, intpcm1 (input) <87> <88> intpa (input) <89> <90> intpb (input) remark m = 0 to 3 a = 100, 101, 110, 111 b = 10, 11, 21 to 25, 50 to 52, 65 to 67, d0 to d15, l0, l1 (10) timer c timing parameter symbol conditions min. max. unit when noise elimination has been set (number of set elimination clocks +1) /(f x /4) +10 ns ticn high-level width <91> t wtch when clock-through has been set 1/(f x /4) chapter 17 electrical specifications user?s manual u16031ej3v0ud 910 (11) timer enc1 timing parameter symbol conditions min. max. unit noise elimination clock = f x /4 selected (number of set elimination clocks +1)/(f x /4) +10 ns when noise elimination has been set noise elimination clock = f x /32 selected (number of set elimination clocks +1)/(fx/32) +10 ns tclr1n, tcud1n, tiud1n pin high-level width <93> t wtench when clock-through has been set note noise elimination clock = f x /4 selected 1/ (f x /4) chapter 17 electrical specifications user?s manual u16031ej3v0ud 911 (12) csi30, csi31 timing (1/3) (a) master mode parameter symbol conditions min. max. unit sckn cycle <95> t cysk1 output 182 ns sckn high-level width <96> t wsk1h output 0.5t cysk1 ? 12 ns sckn low-level width <97> t wsk1l output 0.5t cysk1 ? 12 ns sin setup time (to sckn ) 12 ns sin setup time (to sckn ) <98> t ssisk 12 ns sin hold time (from sckn ) 5 ns sin hold time (from sckn ) <99> t hsksi 5 ns son output delay time (from sckn ) 7 ns son output delay time (from sckn ) <100> t dskso 7 ns son output hold time (from sckn ) 0.5t cysk1 ? 5 ns son output hold time (from sckn ) <101> t hskso 0.5t cysk1 ? 5 ns remark n = 0, 1 (b) slave mode parameter symbol conditions min. max. unit sckn cycle <95> t cysk1 input 182 ns sckn high-level width <96> t wsk1h input 0.5t cysk1 ? 20 ns sckn low-level width <97> t wsk1l input 0.5t cysk1 ? 20 ns sin setup time (to sckn ) 30 ns sin setup time (to sckn ) <98> t ssisk 30 ns sin hold time (from sckn ) 1.5t + 10 ns sin hold time (from sckn ) <99> t hsksi 1.5t + 10 ns son output delay time (from sckn ) 12 ns son output delay time (from sckn ) <100> t dskso 12 ns son output hold time (from sckn ) t wsk1h ns son output hold time (from sckn ) <101> t hskso t wsk1h ns remarks 1. n = 0, 1 2. t = f x /4 chapter 17 electrical specifications user?s manual u16031ej3v0ud 912 (12) csi30, csi31 timing (2/3) (c) timing when ckpn and dapn bits of csic3n register = 00 <95> <97> <96> <98> <99> <100> <101> sin (input) son (output) sckn (i/o) input data output data remarks 1. broken lines indicate high impedance. 2. n = 0, 1 (d) timing when ckpn and dapn bits of csic3n register = 01 <98> <99> <101> sin (input) son (output) input data output data <95> <97> <96> sckn (i/o) <100> remarks 1. broken lines indicate high impedance. 2. n = 0, 1 chapter 17 electrical specifications user?s manual u16031ej3v0ud 913 (12) csi30, csi31 timing (3/3) (e) timing when ckpn and dapn bits of csic3n register = 10 <95> <97> <96> <98> <99> <100> <101> sin (input) son (output) sckn (i/o) input data output data remarks 1. broken lines indicate high impedance. 2. n = 0, 1 (e) timing when ckpn and dapn bits of csic3n register = 11 <98> <99> <101> sin (input) son (output) input data output data <95> <97> <96> sckn (i/o) <100> remarks 1. broken lines indicate high impedance. 2. n = 0, 1 chapter 17 electrical specifications user?s manual u16031ej3v0ud 914 a/d converter characteristics (ev dd = av dd = av refp = 3.0 to 3.6 v, ev ss = av ss = av refm = 0 v) parameter symbol conditions min. typ. max. unit resolution ? 10 bit overall error note 1 ? 0.49 %fsr quantization error ? 1/2 lsb conversion time t conv 2.00 10 s sampling time t samp 3 conversion clock note 2 /16 ns zero-scale error note 1 ? 0.49 %fsr full-scale error note 1 ? 0.49 %fsr integral linearity error note 3 ? 4 lsb differential linearity error note 3 ? 4 lsb analog input voltage v wasn av refm av refp v av dd power supply current ai dd 10 ma notes 1. excluding quantization error ( 0.05%fsr). 2. the conversion clock indicates the numbe r of clocks set by the adm1 register. 3. excluding quantization error ( 0.5lsb). remark lsb: least significant bit fsr: full scale range %fsr indicates the ratio to the full-scale value. 915 user?s manual u16031ej3v0ud chapter 18 package drawings 144 176 133 45 88 132 89 s s n 176-pin plastic lqfp (fine pitch) (24x24) j t detail of lead end c d a b r k m i s p l u q g f note each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 26.0 0.2 24.0 0.2 1.25 26.0 0.2 c 24.0 0.2 l 0.5 f 1.25 n p q s 0.08 1.4 0.1 0.05 1.5 0.1 t u 0.25 0.60 0.15 s176gm-50-ueu-1 m 0.17 + 0.03 ? 0.07 h 0.22 0.05 i j k 0.08 0.5 (t.p.) 1.0 0.2 r3 + 4 ? 3 m h chapter 18 package drawings 916 user?s manual u16031ej3v0ud s wb y1 s s wa s y s e x bab m ? e d zd a a2 a1 ze index mark a s b 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v item dimensions d e w a a1 a2 e 16.00 0.10 16.00 0.10 0.80 0.08 0.10 0.20 1.20 1.20 0.20 0.35 0.06 1.48 0.10 1.13 p240f1-80-ga3 0.50 +0.05 ?0.10 (unit:mm) x y y1 zd ze b 240-pin plastic fbga (16x16) 917 user?s manual u16031ej3v0ud chapter 19 recommended soldering conditions the v850e/me2 should be soldered and mount ed under the following recommended conditions. for soldering methods and conditions other than thos e recommended below, contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (h ttp://www.necel.com/pkg/en/mount/index.html) caution the recommended solderin g conditions for the followi ng products are undetermined. ? ? ? ? 918 user?s manual u16031ej3v0ud appendix a notes a.1 restriction on conflict between sl d instruction and interrupt request a.1.1 description if a conflict occurs between the decode oper ation of an instruction in <2> imm ediately before the sld instruction following an instruction in <1> and an interr upt request before the instru ction in <1> is complete, the execution result of the instruction in <1> ma y not be stored in a register. instruction <1> ? ld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu ? sld instruction: sld.b, sld.h, sld.w, sld.bu, sld.hu ? multiplication instruction: mul, mulh, mulhi, mulu instruction <2> mov reg1, reg2 satadd reg1, reg2 and reg1, reg2 add reg1, reg2 mulh reg1, reg2 not reg1, reg2 satadd imm5, reg2 tst reg1, reg2 add imm5, reg2 shr imm5, reg2 satsubr reg1, reg2 or reg1, reg2 subr reg1, reg2 cmp reg1, reg2 sar imm5, reg2 satsub reg1, reg2 xor reg1, reg2 sub reg1, reg2 cmp imm5, reg2 shl imm5, reg2 appendix a notes 919 user?s manual u16031ej3v0ud a.2 restriction on 2-cycle dma tr ansfer to internal data ram a.2.1 description when performing any of the following 2-cycle dma transfe rs, the tc signal output may become active twice (normally it becomes active once) and the dma transfer end interrupt may occur twice (normally it occurs once) when the last data has been transferred. however, t he dma transfer itself is completed normally. this bug does not occur during flyby transfer. ? the speculative read functi on (set by the lbc0 or lbc1 registe r) is enabled for a cs space and 2-cycle dma transfer from external memory to internal data ram is executed. ? 2-cycle dma transfer from on-chip peripheral i/o to inter nal data ram is executed (regar dless of the speculative read function setting). a.2.2 countermeasures ? in the case of 2-cycle dma transfer from external memory to internal data ram disable the speculative read functi on for the cs space in the dma transfer source (side to be read). ? in the case of 2-cycle dma transfer from on-chip peripheral i/o to internal data ram do not use the tc signal. in addi tion, execute the processing of <1> and <2> below consecutively for the excessive dma transfer end interrupt in the dma transfer end interrupt servicing routine. after the processing of <2> is executed, by executing t he application processing that should be performed in the normal operation and restoring from the interrupt, occurrence of the second dma transfer end interrupt can be suppressed. <1> set the write access synchronization control register (was) to 00h. <2> clear bit 7 (dmaifn) of the inte rrupt control register (dmaicn) of the same channel as the dma transfer end interrupt currently being serviced to 0. user?s manual u16031ej3v0ud 920 appendix b register index (1/13) symbol name unit page adcr0 to adcr7 a/d conversion result registers 0 to 7 adc 727 adcr0h to adcr7h a/d conversion result registers 0h to 7h adc 727 adic interrupt control register 83 adc 317 adm0 a/d converter mode register 0 adc 722 adm1 a/d converter mode register 1 adc 723 adm2 a/d converter mode register 2 adc 725 adts adc trigger select register adc 726 asc address setup wait control register bcu 147 bcc bus cycle control register bcu 152 bcp bus cycle period control register bcu 148 bct0 bus cycle type configuration register 0 bcu 113 bct1 bus cycle type configuration register 1 bcu 113 bec endian configuration register bcu 116 bhc cache configuration register bcu 154 bmc bus mode control register bcu 143 cc100 capture/compare register 100 rpu 432 cc101 capture/compare register 101 rpu 433 cc10ic0 interrupt control register 53 intc 317 cc10ic1 interrupt control register 54 intc 317 cc110 capture/compare register 110 rpu 432 cc111 capture/compare register 111 rpu 433 cc11ic0 interrupt control register 59 intc 317 cc11ic1 interrupt control register 60 intc 317 ccc00 capture/compare register c00 rpu 391 ccc01 capture/compare register c01 rpu 391 ccc0ic0 interrupt control register 37 intc 317 ccc0ic1 interrupt control register 38 intc 317 ccc10 capture/compare register c10 rpu 391 ccc11 capture/compare register c11 rpu 391 ccc1ic0 interrupt control register 39 intc 317 ccc1ic1 interrupt control register 40 intc 317 ccc20 capture/compare register c20 rpu 391 ccc21 capture/compare register c21 rpu 391 ccc2ic0 interrupt control register 41 intc 317 ccc2ic1 interrupt control register 42 intc 317 appendix b register index user?s manual u16031ej3v0ud 921 (2/13) symbol name unit page ccc30 capture/compare register c30 rpu 391 ccc31 capture/compare register c31 rpu 391 ccc3ic0 interrupt control register 43 intc 317 ccc3ic1 interrupt control register 44 intc 317 ccc40 capture/compare register c40 rpu 391 ccc41 capture/compare register c41 rpu 391 ccc4ic0 interrupt control register 45 intc 317 ccc4ic1 interrupt control register 46 intc 317 ccc50 capture/compare register c50 rpu 391 ccc51 capture/compare register c51 rpu 391 ccc5ic0 interrupt control register 47 intc 317 ccc5ic1 interrupt control register 48 intc 317 ccr10 capture/compare control register 10 rpu 437 ccr11 capture/compare control register 11 rpu 437 ckc clock control register cg 351 cks clock source select register cg 354 cm100 compare register 100 rpu 431 cm101 compare register 101 rpu 431 cm10ic0 interrupt control register 55 intc 317 cm10ic1 interrupt control register 56 intc 317 cm110 compare register 110 rpu 431 cm111 compare register 111 rpu 431 cm11ic0 interrupt control register 61 intc 317 cm11ic1 interrupt control register 62 intc 317 cmd0 compare register d0 rpu 418 cmd1 compare register d1 rpu 418 cmd2 compare register d2 rpu 418 cmd3 compare register d3 rpu 418 cmdic0 interrupt control register 49 intc 317 cmdic1 interrupt control register 50 intc 317 cmdic2 interrupt control register 51 intc 317 cmdic3 interrupt control register 52 intc 317 covf3ic0 interrupt control register 70 intc 317 covf3ic1 interrupt control register 72 intc 317 csc0 chip area select control register 0 bcu 109 csc1 chip area select control register 1 bcu 109 csi3ic0 interrupt control register 69 intc 317 csi3ic1 interrupt control register 71 intc 317 csic30 clocked serial interface cl ock select register 30 csi30 523 appendix b register index user?s manual u16031ej3v0ud 922 (3/13) symbol name unit page csic31 clocked serial interface cl ock select register 31 csi31 523 csil30 transfer data length select register 30 csi30 531 csil31 transfer data length select register 31 csi31 531 csim30 clocked serial interfac e mode register 30 csi30 521 csim31 clocked serial interfac e mode register 31 csi31 521 dadc0 dma addressing control register 0 dmac 246 dadc1 dma addressing control register 1 dmac 246 dadc2 dma addressing control register 2 dmac 246 dadc3 dma addressing control register 3 dmac 246 dbc0 dma transfer count register 0 dmac 245 dbc1 dma transfer count register 1 dmac 245 dbc2 dma transfer count register 2 dmac 245 dbc3 dma transfer count register 3 dmac 245 dchc0 dma channel control register 0 dmac 249 dchc1 dma channel control register 1 dmac 249 dchc2 dma channel control register 2 dmac 249 dchc3 dma channel control register 3 dmac 249 dda0h dma destination address register 0h dmac 243 dda0l dma destination address register 0l dmac 244 dda1h dma destination address register 1h dmac 243 dda1l dma destination address register 1l dmac 244 dda2h dma destination address register 2h dmac 243 dda2l dma destination address register 2l dmac 244 dda3h dma destination address register 3h dmac 243 dda3l dma destination address register 3l dmac 244 difc dma interface control register dmac 259 dmaic0 interrupt control register 65 intc 317 dmaic1 interrupt control register 66 intc 317 dmaic2 interrupt control register 67 intc 317 dmaic3 interrupt control register 68 intc 317 dsa0h dma source address register 0h dmac 241 dsa0l dma source address register 0l dmac 242 dsa1h dma source address register 1h dmac 241 dsa1l dma source address register 1l dmac 242 dsa2h dma source address register 2h dmac 241 dsa2l dma source address register 2l dmac 242 dsa3h dma source address register 3h dmac 241 dsa3l dma source address register 3l dmac 242 dtfr0 dma trigger factor register 0 dmac 253 appendix b register index user?s manual u16031ej3v0ud 923 (4/13) symbol name unit page dtfr1 dma trigger factor register 1 dmac 253 dtfr2 dma trigger factor register 2 dmac 253 dtfr3 dma trigger factor register 3 dmac 253 dtoc dma terminal count output control register dmac 252 dwc0 data wait control register 0 bcu 145 dwc1 data wait control register 1 bcu 145 fic dma flyby transfer idle control register bcu 153 fwc dma flyby transfer wait control register bcu 149 icc instruction cache control register bcu 157 icch instruction cache control register h bcu 157 iccl instruction cache control register l bcu 157 icd instruction cache data co nfiguration register bcu 158 imr0 interrupt mask register 0 intc 320 imr0h interrupt mask register 0h intc 320 imr0l interrupt mask register 0l intc 320 imr1 interrupt mask register 1 intc 320 imr1h interrupt mask register 1h intc 320 imr1l interrupt mask register 1l intc 320 imr2 interrupt mask register 2 intc 320 imr2h interrupt mask register 2h intc 320 imr2l interrupt mask register 2l intc 320 imr3 interrupt mask register 3 intc 320 imr3h interrupt mask register 3h intc 320 imr3l interrupt mask register 3l intc 320 imr4 interrupt mask register 4 intc 320 imr4h interrupt mask register 4h intc 320 imr4l interrupt mask register 4l intc 320 imr5 interrupt mask register 5 intc 320 imr5h interrupt mask register 5h intc 320 imr5l interrupt mask register 5l intc 320 intf1 external interrupt falling edge specification register 1 intc 324, 797 intf2 external interrupt falling edge specification register 2 intc 309, 326, 802 intf5 external interrupt falling edge specification register 5 intc 328, 807 intf6 external interrupt falling edge specification register 6 intc 330, 812 intfal external interrupt falling edge specification register al intc 332, 820 intfdh external interrupt falling edge specification register dh intc 333, 831 intfdhh external interrupt falling edge specification register dhh intc 333, 831 intfdhl external interrupt falling edge specification register dhl intc 333, 831 appendix b register index user?s manual u16031ej3v0ud 924 (5/13) symbol name unit page intr1 external interrupt rising edge specification register 1 intc 324, 797 intr2 external interrupt rising edge specification register 2 intc 309, 326, 802 intr5 external interrupt rising edge specification register 5 intc 328, 807 intr6 external interrupt rising edge specification register 6 intc 330, 812 intral external interrupt rising edge specification register al intc 332, 820 intrdh external interrupt rising edge specification register dh intc 333, 831 intrdhh external interrupt rising edge specification register dhh intc 333, 831 intrdhl external interrupt rising edge specification register dhl intc 333, 831 iramm internal instruction ram mode register bcu 161 ispr in-service priority register intc 323 lbc0 line buffer control register 0 bcu 138 lbc1 line buffer control register 1 bcu 138 lbs local bus sizing control register bcu 115 lockr lock register cpu 360 ncw10 noise elimination width setting register 10 rpu 443, 850 ncw11 noise elimination width setting register 11 rpu 443, 850 ncwc0 noise elimination width setting register c0 rpu 400, 849 ncwc1 noise elimination width setting register c1 rpu 400, 849 ncwc2 noise elimination width setting register c2 rpu 400, 849 ncwc3 noise elimination width setting register c3 rpu 400, 849 nrs nmi reset status register intc 322 osts oscillation stabilization time select register cg 360 ov1ic0 interrupt control register 57 intc 317 ov1ic1 interrupt control register 63 intc 317 ovcic0 interrupt control register 31 intc 317 ovcic1 interrupt control register 32 intc 317 ovcic2 interrupt control register 33 intc 317 ovcic3 interrupt control register 34 intc 317 ovcic4 interrupt control register 35 intc 317 ovcic5 interrupt control register 36 intc 317 p1 port 1 port 794 p1ic0 interrupt control register 0 intc 317 p1ic1 interrupt control register 1 intc 317 p2 port 2 port 799 p2ic1 interrupt control register 2 intc 317 p2ic2 interrupt control register 3 intc 317 p2ic3 interrupt control register 4 intc 317 p2ic4 interrupt control register 5 intc 317 appendix b register index user?s manual u16031ej3v0ud 925 (6/13) symbol name unit page p2ic5 interrupt control register 6 intc 317 p5 port 5 port 804 p5ic0 interrupt control register 7 intc 317 p5ic1 interrupt control register 8 intc 317 p5ic2 interrupt control register 9 intc 317 p6 port 6 port 809 p6ic5 interrupt control register 10 intc 317 p6ic6 interrupt control register 11 intc 317 p6ic7 interrupt control register 12 intc 317 p7 port 7 port 814 pa h po r t a h port 822 pahh port ahh port 822 pa h l po r t a h l port 822 pa l po r t a l port 817 pa l h po r t a l h port 817 pall port all port 817 pcd port cd port 842 pcm port cm port 839 pcs port cs port 833 pct port ct port 836 pdh port dh port 824 pdhh port dhh port 824 pdhl port dhl port 824 pdic0 interrupt control register 13 intc 317 pdic1 interrupt control register 14 intc 317 pdic2 interrupt control register 15 intc 317 pdic3 interrupt control register 16 intc 317 pdic4 interrupt control register 17 intc 317 pdic5 interrupt control register 18 intc 317 pdic6 interrupt control register 19 intc 317 pdic7 interrupt control register 20 intc 317 pdic8 interrupt control register 21 intc 317 pdic9 interrupt control register 22 intc 317 pdic10 interrupt control register 23 intc 317 pdic11 interrupt control register 24 intc 317 pdic12 interrupt control register 25 intc 317 pdic13 interrupt control register 26 intc 317 pdic14 interrupt control register 27 intc 317 pdic15 interrupt control register 28 intc 317 appendix b register index user?s manual u16031ej3v0ud 926 (7/13) symbol name unit page pfc1 port 1 function control register port 796 pfc2 port 2 function control register port 801 pfc5 port 5 function control register port 806 pfc6 port 6 function control register port 811 pfc7 port 7 function control register port 816 pfcall port al function control register l port 819 pfccm port cm function control register port 841 pfccs port cs function control register port 835 pfcct port ct function control register port 838 pfcdh port dh function control register port 828 pfcdhh port dh function control register h port 828 pfcdhl port dh function control register l port 828 plic0 interrupt control register 29 intc 317 plic1 interrupt control register 30 intc 317 pm1 port 1 mode register port 795 pm2 port 2 mode register port 800 pm5 port 5 mode register port 805 pm6 port 6 mode register port 810 pm7 port 7 mode register port 815 pmah port ah mode register port 823 pmahh port ah mode register h port 823 pmahl port ah mode register l port 823 pmal port al mode register port 818 pmalh port al mode register h port 818 pmall port al mode register l port 818 pmc1 port 1 mode control register port 795 pmc2 port 2 mode control register port 800 pmc5 port 5 mode control register port 805 pmc6 port 6 mode control register port 810 pmc7 port 7 mode control register port 815 pmcah port ah mode control register port 823 pmcahh port ah mode control register h port 823 pmcahl port ah mode control register l port 823 pmcal port al mode control register port 818 pmcalh port al mode control register h port 818 pmcall port al mode control register l port 818 pmccd port cd mode control register port 843 pmccm port cm mode control register port 840 pmccs port cs mode control register port 834 appendix b register index user?s manual u16031ej3v0ud 927 (8/13) symbol name unit page pmcct port ct mode control register port 837 pmcd port cd mode register port 843 pmcdh port dh mode control register port 826 pmcdhh port dh mode control register h port 826 pmcdhl port dh mode control register l port 826 pmcm port cm mode register port 840 pmcs port cs mode register port 834 pmct port ct mode register port 837 pmdh port dh mode register port 826 pmdhh port dh mode register h port 826 pmdhl port dh mode register l port 826 prc page rom configuration register memc 192 prcmd command register cpu 368 prm10 prescaler mode register 10 rpu 440 prm11 prescaler mode register 11 rpu 440 psc power-save control register cpu 369 psmr power-save mode register cpu 368 pwm0 pwm modulo register 0 pwm 756 pwm1 pwm modulo register 1 pwm 756 pwmc0 pwm control register 0 pwm 754 pwmc1 pwm control register 1 pwm 754 pwmh0 pwm modulo register h0 pwm 756 pwmh1 pwm modulo register h1 pwm 756 pwml0 pwm modulo register l0 pwm 756 pwml1 pwm modulo register l1 pwm 756 rfs1 sdram refresh control register 1 memc 229 rfs3 sdram refresh control register 3 memc 229 rfs4 sdram refresh control register 4 memc 229 rfs6 sdram refresh control register 6 memc 229 rsumic interrupt control register 89 intc 317 scr1 sdram configuration register 1 memc 202 scr3 sdram configuration register 3 memc 202 scr4 sdram configuration register 4 memc 202 scr6 sdram configuration register 6 memc 202 sesa10 valid edge select register 10 intc 337, 438 sesa11 valid edge select register 11 intc 337, 438 sesc0 valid edge select register c0 intc 335, 398 sesc1 valid edge select register c1 intc 335, 398 sesc2 valid edge select register c2 intc 335, 398 appendix b register index user?s manual u16031ej3v0ud 928 (9/13) symbol name unit page sesc3 valid edge select register c3 intc 335, 398 sfa30 csibuf status register 30 csi30 528 sfa31 csibuf status register 31 csi31 528 sfdb30 transmit data csi buffer register 30 csi30 527 sfdb30h transmit data csi buffer register 30h csi30 527 sfdb30l transmit data csi buffer register 30l csi30 527 sfdb31 transmit data csi buffer register 31 csi31 527 sfdb31h transmit data csi buffer register 31h csi31 527 sfdb31l transmit data csi buffer register 31l csi31 527 sfn30 transfer data number specification register 30 csi30 532 sfn31 transfer data number specification register 31 csi31 532 sirb30 receive data buffer register 30 csi30 526 sirb30h receive data buffer register 30h csi31 526 sirb30l receive data buffer register 30l csi30 526 sirb31 receive data buffer register 31 csi31 526 sirb31h receive data buffer register 31h csi31 526 sirb31l receive data buffer register 31l csi31 526 sscgc sscg control register cg 356 status10 status register 10 rpu 442 status11 status register 11 rpu 442 tmc0 timer c0 rpu 389 tmc1 timer c1 rpu 389 tmc10 timer control register 10 rpu 435 tmc11 timer control register 11 rpu 435 tmc2 timer c2 rpu 389 tmc3 timer c3 rpu 389 tmc4 timer c4 rpu 389 tmc5 timer c5 rpu 389 tmcc00 timer mode control register c00 rpu 393 tmcc01 timer mode control register c01 rpu 395 tmcc10 timer mode control register c10 rpu 393 tmcc11 timer mode control register c11 rpu 395 tmcc20 timer mode control register c20 rpu 393 tmcc21 timer mode control register c21 rpu 395 tmcc30 timer mode control register c30 rpu 393 tmcc31 timer mode control register c31 rpu 395 tmcc40 timer mode control register c40 rpu 393 tmcc41 timer mode control register c41 rpu 395 tmcc50 timer mode control register c50 rpu 393 appendix b register index user?s manual u16031ej3v0ud 929 (10/13) symbol name unit page tmcc51 timer mode control register c51 rpu 395 tmcd0 timer mode control register d0 rpu 420 tmcd1 timer mode control register d1 rpu 420 tmcd2 timer mode control register d2 rpu 420 tmcd3 timer mode control register d3 rpu 420 tmd0 timer d0 rpu 417 tmd1 timer d1 rpu 417 tmd2 timer d2 rpu 417 tmd3 timer d3 rpu 417 tmenc10 timer enc10 rpu 429 tmenc11 timer enc11 rpu 429 tum10 timer unit mode register 10 rpu 434 tum11 timer unit mode register 11 rpu 434 ub0ctl0 uartb0 control register 0 uartb 467 ub0ctl2 uartb0 control register 2 uartb 472 ub0fic0 uartb0 fifo control register 0 uartb 476 ub0fic1 uartb0 fifo control register 1 uartb 478 ub0fic2 uartb0 fifo control register 2 uartb 479 ub0fic2h uartb0 fifo control register 2h uartb 479 ub0fic2l uartb0 fifo control register 2l uartb 479 ub0fis0 uartb0 fifo status register 0 uartb 482 ub0fis1 uartb0 fifo status register 1 uartb 483 ub0rx uartb0 receive data register uartb 474 ub0rxap uartb0 receive data register ap uartb 474 ub0str uartb0 status register uartb 470 ub0tx uartb0 transmit data register uartb 473 ub1ctl0 uartb1 control register 0 uartb 467 ub1ctl2 uartb1 control register 2 uartb 472 ub1fic0 uartb1 fifo control register 0 uartb 476 ub1fic1 uartb1 fifo control register 1 uartb 478 ub1fic2 uartb1 fifo control register 2 uartb 479 ub1fic2h uartb1 fifo control register 2h uartb 479 ub1fic2l uartb1 fifo control register 2l uartb 479 ub1fis0 uartb1 fifo status register 0 uartb 482 ub1fis1 uartb1 fifo status register 1 uartb 483 ub1rx uartb1 receive data register uartb 474 ub1rxap uartb1 receive data register ap uartb 474 ub1str uartb1 status register uartb 470 ub1tx uartb1 transmit data register uartb 473 appendix b register index user?s manual u16031ej3v0ud 930 (11/13) symbol name unit page uckc usb clock control register cg 358 ud1ic0 interrupt control register 58 intc 317 ud1ic1 interrupt control register 64 intc 317 uf0aas uf0 active alternative setting register usbf 616 uf0adrs uf0 address register usbf 657 uf0aifn uf0 active interface number register usbf 615 uf0ass uf0 alternative setting status register usbf 617 uf0bc usb function 0 buffer control register usbf 666 uf0bi1 uf0 bulk in 1 register usbf 637 uf0bi2 uf0 bulk in 2 register usbf 641 uf0bo1 uf0 bulk out 1 register usbf 630 uf0bo1l uf0 bulk out 1 length register usbf 633 uf0bo2 uf0 bulk out 2 register usbf 634 uf0bo2l uf0 bulk out 2 length register usbf 637 uf0cie0 to uf0cie255 uf0 configuration/interface/endpoint des criptor registers 0 to 255 usbf 663 uf0clr uf0 clr request register usbf 580 uf0cnf uf0 configuration register usbf 658 uf0cs usb function 0 dma channel select register usbf 665 uf0dd0 to uf0dd17 uf0 device descriptor registers 0 to 17 usbf 662 uf0dend uf0 data end register usbf 610 uf0dms0 uf0 dma status 0 register usbf 606 uf0dms1 uf0 dma status 1 register usbf 607 uf0dscl uf0 descriptor length register usbf 661 uf0dstl uf0 device status register l usbf 649 uf0e0l uf0 ep0 length register usbf 625 uf0e0n uf0 ep0nak register usbf 571 uf0e0na uf0 ep0nakall register usbf 573 uf0e0r uf0 ep0 read register usbf 624 uf0e0sl uf0 ep0 status register l usbf 650 uf0e0st uf0 ep0 setup register usbf 626 uf0e0w uf0 ep0 write register usbf 628 uf0e1im uf0 endpoint 1 interface mapping register usbf 618 uf0e1sl uf0 ep1 status register l usbf 651 uf0e2im uf0 endpoint 2 interface mapping register usbf 619 uf0e2sl uf0 ep2 status register l usbf 652 uf0e3im uf0 endpoint 3 interface mapping register usbf 620 uf0e3sl uf0 ep3 status register l usbf 653 appendix b register index user?s manual u16031ej3v0ud 931 (12/13) symbol name unit page uf0e4im uf0 endpoint 4 interface mapping register usbf 621 uf0e4sl uf0 ep4 status register l usbf 654 uf0e7im uf0 endpoint 7 interface mapping register usbf 622 uf0e7sl uf0 ep7 status register l usbf 655 uf0e8im uf0 endpoint 8 interface mapping register usbf 623 uf0e8sl uf0 ep8 status register l usbf 656 uf0en uf0 epnak register usbf 574 uf0enm uf0 epnak mask register usbf 578 uf0eps0 uf0 ep status 0 register usbf 582 uf0eps1 uf0 ep status 1 register usbf 584 uf0eps2 uf0 ep status 2 register usbf 585 uf0fic0 uf0 fifo clear 0 register usbf 608 uf0fic1 uf0 fifo clear 1 register usbf 609 uf0gpr uf0 gpr register usbf 612 uf0ic0 uf0 int clear 0 register usbf 599 uf0ic1 uf0 int clear 1 register usbf 600 uf0ic2 uf0 int clear 2 register usbf 601 uf0ic3 uf0 int clear 3 register usbf 602 uf0ic4 uf0 int clear 4 register usbf 603 uf0idr uf0 int & dmarq register usbf 604 uf0if0 uf0 interface 0 register usbf 659 uf0if1 uf0 interface 1 register usbf 660 uf0if2 uf0 interface 2 register usbf 660 uf0if3 uf0 interface 3 register usbf 660 uf0if4 uf0 interface 4 register usbf 660 uf0im0 uf0 int mask 0 register usbf 594 uf0im1 uf0 int mask 1 register usbf 595 uf0im2 uf0 int mask 2 register usbf 596 uf0im3 uf0 int mask 3 register usbf 597 uf0im4 uf0 int mask 4 register usbf 598 uf0int1 uf0 interrupt 1 register usbf 645 uf0int2 uf0 interrupt 2 register usbf 647 uf0is0 uf0 int status 0 register usbf 586 uf0is1 uf0 int status 1 register usbf 588 uf0is2 uf0 int status 2 register usbf 590 uf0is3 uf0 int status 3 register usbf 591 uf0is4 uf0 int status 4 register usbf 593 uf0modc uf0 mode control register usbf 613 uf0mods uf0 mode status register usbf 614 appendix b register index user?s manual u16031ej3v0ud 932 (13/13) symbol name unit page uf0sds uf0 sndsie register usbf 579 uf0set uf0 set request register usbf 581 uific0 interrupt control register 76 intc 317 uific1 interrupt control register 81 intc 317 ureic0 interrupt control register 73 intc 317 ureic1 interrupt control register 78 intc 317 uric0 interrupt control register 74 intc 317 uric1 interrupt control register 79 intc 317 us0bic interrupt control register 84 intc 317 us1bic interrupt control register 85 intc 317 us2bic interrupt control register 86 intc 317 usp2ic interrupt control register 87 intc 317 usp4ic interrupt control register 88 intc 317 utic0 interrupt control register 75 intc 317 utic1 interrupt control register 80 intc 317 utoic0 interrupt control register 77 intc 317 utoic1 interrupt control register 82 intc 317 vswc system wait control register bcu 103 was write access synchronization control register bcu 142 user?s manual u16031ej3v0ud 933 appendix c instruction set list c.1 conventions (1) register symbols u sed to describe operands register symbol explanation reg1 general-purpose registers: used as source registers. reg2 general-purpose registers: used mainly as destination registers. also used as source register in some instructions. reg3 general-purpose registers: used mainly to store the remainders of division results and the higher order 32 bits of multiplication results. bit#3 3-bit data for specifying the bit number immx x bit immediate data dispx x bit displacement data regid system register number vector 5-bit data that specifies the trap vector (00h to 1fh) cccc 4-bit data that shows the conditions code sp stack pointer (sp) ep element pointer (r30) listx x item register list (2) register symbols used to describe opcodes register symbol explanation r 1-bit data of a code that specifies reg1 or regid r 1-bit data of the code that specifies reg2 w 1-bit data of the code that specifies reg3 d 1-bit displacement data i 1-bit immediate data (indicates th e higher bits of immediate data) i 1-bit immediate data cccc 4-bit data that shows the condition codes cccc 4-bit data that shows the condition codes of bcond instruction bbb 3-bit data for specifying the bit number l 1-bit data that specifies a program register in the register list s 1-bit data that specifies a system register in the register list appendix c instruction set list user?s manual u16031ej3v0ud 934 (3) register symbols used in operations register symbol explanation input for gr [ ] general-purpose register sr [ ] system register zero-extend (n) expand n with zeros until word length. sign-extend (n) expand n with signs until word length. load-memory (a, b) read size b data from address a. store-memory (a, b, c) write data b into address a in size c. load-memory-bit (a, b) read bit b of address a. store-memory-bit (a, b, c) write c to bit b of address a. saturated (n) execute saturated processing of n (n is a 2?s complement). if, as a result of calculations, n 7fffffffh, let it be 7fffffffh. n 80000000h, let it be 80000000h. result reflects the results in a flag. byte byte (8 bits) halfword half word (16 bits) word word (32 bits) + addition ? subtraction ll bit concatenation multiplication division % remainder from division results and logical product or logical sum xor exclusive or not logical negation logically shift left by logical shift left logically shift right by logical shift right arithmetically shift right by arithmetic shift right (4) register symbols u sed in execution clock register symbol explanation i if executing another instruction immediately a fter executing the first instruction (issue). r if repeating execution of the same instruction immedi ately after executing the first instruction (repeat). l if using the results of instruction execution in the instruction immediately afte r the execution (latency). appendix c instruction set list user?s manual u16031ej3v0ud 935 (5) register symbols used in flag operations identifier explanation (blank) no change 0 clear to 0 x set or cleared in accordance with the results. r previously saved values are restored. (6) condition codes condition name (cond) condition code (cccc) condition formula explanation v 0 0 0 0 ov = 1 overflow nv 1 0 0 0 ov = 0 no overflow c/l 0 0 0 1 cy = 1 carry lower (less than) nc/nl 1 0 0 1 cy = 0 no carry not lower (greater than or equal) z/e 0 0 1 0 z = 1 zero equal nz/ne 1 0 1 0 z = 0 not zero not equal nh 0 0 1 1 (cy or z) = 1 not higher (less than or equal) h 1 0 1 1 (cy or z) = 0 higher (greater than) n 0 1 0 0 s = 1 negative p 1 1 0 0 s = 0 positive t 0 1 0 1 ? always (unconditional) sa 1 1 0 1 sat = 1 saturated lt 0 1 1 0 (s xor ov) = 1 less than signed ge 1 1 1 0 (s xor ov) = 0 greater than or equal signed le 0 1 1 1 ((s xor ov) or z) = 1 less than or equal signed gt 1 1 1 1 ((s xor ov) or z) = 0 greater than signed appendix c instruction set list user?s manual u16031ej3v0ud 936 c.2 instruction set (in alphabetical order) (1/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat reg1,reg2 r r rr r0 01 11 0 rrrrr gr[reg2] gr[reg2]+gr[reg1] 1 1 1 add imm5,reg2 rrrrr010010iiiii gr[reg2] gr[reg2]+sign-extend(imm5) 1 1 1 addi imm16,reg1,reg2 r r rr r1 10 00 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend(imm16) 1 1 1 and reg1,reg2 r r rr r0 01 01 0 rrrrr gr[reg2] gr[reg2]and gr[reg1] 1 1 1 0 andi imm16,reg1,reg2 r r rr r1 10 11 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]and zero-extend(imm16) 1 1 1 0 0 when conditions are satisfied 3 note 2 3 note 2 3 note 2 bcond disp9 ddddd1011dddcccc note 1 if conditions are satisfied then pc pc+sign-extend(disp9) when conditions are not satisfied 1 1 1 bsh reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000010 gr[reg3] gr[reg2] (23 : 16) ll gr[reg2] (31 : 24) ll gr[reg2] (7 : 0) ll gr[reg2] (15 : 8) 1 1 1 0 bsw reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000000 gr[reg3] gr[reg2] (7 : 0) ll gr[reg2] (15 : 8) ll gr [reg2] (23 : 16) ll gr[reg2] (31 : 24) 1 1 1 0 callt imm6 0000001000iiiiii ctpc pc+2(return pc) ctpsw psw adr ctbp+zero-extend(imm6 logically shift left by 1) pc ctbp+zero-extend(load-memory(adr,halfword)) 5 5 5 bit#3, disp16[reg1] 10bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,0) 3 note 3 3 note 3 3 note 3 clr1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100100 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,0) 3 note 3 3 note 3 3 note 3 cccc,imm5,reg2,reg3 rrrrr111111iiiii wwwww011000cccc0 if conditions are satisfied then gr[reg3] sign-extended(imm5) else gr[reg3] gr[reg2] 1 1 1 cmov cccc,reg1,reg2,reg3 r r r r r 1 1 1 1 1 1 r r r r wwwww011001cccc0 if conditions are satisfied then gr[reg3] gr[reg1] else gr[reg3] gr[reg2] 1 1 1 reg1,reg2 r r rr r0 01 11 1 rrrrr result gr[reg2]?gr[reg1] 1 1 1 cmp imm5,reg2 rrrrr010011iiiii result gr[reg2]?sign-extend(imm5) 1 1 1 ctret 0000011111100000 0000000101000100 pc ctpc psw ctpsw 4 4 4 r r r r r dbret 0000011111100000 0000000101000110 pc dbpc psw dbpsw 4 4 4 r r r r r appendix c instruction set list user?s manual u16031ej3v0ud 937 (2/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat dbtrap 1111100001000000 dbpc pc+2 (returned pc) dbpsw psw psw.np 1 psw.ep 1 psw.id 1 pc 00000060h 4 4 4 di 0000011111100000 0000000101100000 psw.id 1 1 1 1 imm5,list12 0000011001iiiiil lllllllllll00000 sp sp+zero-extend(imm5 logically shift left by 2) gr[reg in list12] load-memory(sp,word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded n+1 note 4 n+1 note 4 n+1 note 4 dispose imm5,list12,[reg1] 0 0 0 0 0 1 1 0 0 1 i i i i i l lllllllllllrrrrr note 5 sp sp+zero-extend(imm5 logically shift left by 2) gr[reg in list12] load-memory(sp,word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded pc gr[reg1] n+3 note 4 n+3 note 4 n+3 note 4 div reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01011000000 gr[reg2] gr[reg2]gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 35 35 35 reg1,reg2 r r rr r0 00 01 0 rrrrr gr[reg2] gr[reg2]gr[reg1] note 6 35 35 35 divh reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01010000000 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 35 35 35 divhu reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01010000010 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 34 34 34 divu reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01011000010 gr[reg2] gr[reg2]gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 34 34 34 ei 1000011111100000 0000000101100000 psw.id 0 1 1 1 halt 0000011111100000 0000000100100000 stop 1 1 1 hsw reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000100 gr[reg3] gr[reg2](15 : 0) ll gr[reg2] (31 : 16) 1 1 1 0 jarl disp22,reg2 r r r r r 1 1 1 1 0 d d d d d d ddddddddddddddd0 note 7 gr[reg2] pc+4 pc pc+sign-extend(disp22) 3 3 3 jmp [reg1] 00000000011rrrrr pc gr[reg1] 4 4 4 jr disp22 0000011110dddddd ddddddddddddddd0 note 7 pc pc+sign-extend(disp22) 3 3 3 ld.b disp16[reg1],reg2 r r rr r1 11 00 0 rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) gr[reg2] sign-extend(load-memory(adr,byte)) 1 1 note 11 ld.bu disp16[reg1],reg2 r r rr r1 11 10 b rrrrr dddddddddddddd1 notes 8, 10 adr gr[reg1]+sign-extend(disp16) gr[reg2] zero-extend(load-memory(adr,byte)) 1 1 note 11 appendix c instruction set list user?s manual u16031ej3v0ud 938 (3/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat ld.h disp16[reg1],reg2 rrrrr111001rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] sign-extend(load-memory(adr,halfword)) 1 1 note 11 other than regid = psw 1 1 1 ldsr reg2,regid rrrrr111111rrrrr 0000000000100000 note 12 sr[regid] gr[reg2] regid = psw 1 1 1 ld.hu disp16[reg1],reg2 r r rr r1 11 11 1 rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-exend(disp16) gr[reg2] zero-extend(load-memory(adr,halfword) 1 1 note 11 ld.w disp16[reg1],reg2 r r rr r1 11 00 1 rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-exend(disp16) gr[reg2] load-memory(adr,word) 1 1 note 11 reg1,reg2 r r rr r0 00 00 0 rrrrr gr[reg2] gr[reg1] 1 1 1 imm5,reg2 rrrrr010000iiiii gr[reg2] sign-extend(imm5) 1 1 1 mov imm32,reg1 00000110001rrrrr iiiiiiiiiiiiiiii iiiiiiiiiiiiiiii gr[reg1] imm32 2 2 2 movea imm16,reg1,reg2 r r rr r1 10 00 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend(imm16) 1 1 1 movhi imm16,reg1,reg2 r r rr r1 10 01 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+(imm16 ll 0 16 ) 1 1 1 reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01000100000 gr[reg3] ll gr[reg2] gr[reg2]xgr[reg1] 1 2 note 14 2 mul note 22 imm9,reg2,reg3 rrrrr111111iiiii wwwww01001iiii00 note 13 gr[reg3] ll gr[reg2] gr[reg2]xsign-extend(imm9) 1 2 note 14 2 reg1,reg2 r r rr r0 00 11 1 rrrrr gr[reg2] gr[reg2] note 6 xgr[reg1] note 6 1 1 2 mulh imm5,reg2 rrrrr010111iiiii gr[reg2] gr[reg2] note 6 xsign-extend(imm5) 1 1 2 mulhi imm16,reg1,reg2 r r rr r1 10 11 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] note 6 ximm16 1 1 2 reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01000100010 gr[reg3] ll gr[reg2] gr[reg2]xgr[reg1] 1 2 note 1 4 2 mulu note 22 imm9,reg2,reg3 rrrrr111111iiiii wwwww01001iiii10 note 13 gr[reg3] ll gr[reg2] gr[reg2]xzero-extend(imm9) 1 2 note 1 4 2 nop 0000000000000000 pass at least one clock cycle doing nothing. 1 1 1 not reg1,reg2 r r rr r0 00 00 1 rrrrr gr[reg2] not(gr[reg1]) 1 1 1 0 bit#3,disp16[reg1] 01bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,z flag) 3 note 3 3 note 3 3 note 3 not1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100010 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,z flag) 3 note 3 3 note 3 3 note 3 appendix c instruction set list user?s manual u16031ej3v0ud 939 (4/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat or reg1,reg2 r r rr r0 01 00 0 rrrrr gr[reg2] gr[reg2]or gr[reg1] 1 1 1 0 ori imm16,reg1,reg2 r r rr r1 10 10 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]or zero-extend(imm16) 1 1 1 0 list12,imm5 0000011110iiiiil lllllllllll00001 store-memory(sp?4,gr[reg in list12],word) sp sp?4 repeat 1 step above until all regs in list12 is stored sp sp-zero-extend(imm5) n+1 note 4 n+1 note 4 n+1 note 4 prepare list12,imm5, sp/imm note 15 0000011110iiiiil lllllllllllff011 imm16/imm32 note 16 store-memory(sp?4,gr[reg in list12],word) gr[reg in list 12] load-memory(sp,word) sp sp+4 repeat 2 step above until a ll regs in list12 is loaded pc gr[reg1] n+2 note 4 note 17 n+2 note 4 note 17 n+2 note 4 note 17 reti 0000011111100000 0000000101000000 if psw.ep=1 then pc eipc psw eipsw else if psw.np=1 then pc fepc psw fepsw else pc eipc psw eipsw 4 4 4 r r r r r reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000010100000 gr[reg2] gr[reg2]arithmetically shift right by gr[reg1] 1 1 1 0 sar imm5,reg2 rrrrr010101iiiii gr[reg2] gr[reg2]arithmetically shift right by zero-extend (imm5) 1 1 1 0 sasf cccc,reg2 rrrrr1111110cccc 0000001000000000 if conditions are satisfied then gr[reg2] (gr[reg2]logically shift left by 1) or 00000001h else gr[reg2] (gr[reg2]logically shift left by 1) or 00000000h 1 1 1 reg1,reg2 r r rr r0 00 11 0 rrrrr gr[reg2] saturated(gr[reg2]+gr[reg1]) 1 1 1 satadd imm5,reg2 rrrrr010001iiiii gr[reg2] saturated(gr[reg2]+sign-extend(imm5) 1 1 1 satsub reg1,reg2 r r rr r0 00 10 1 rrrrr gr[reg2] saturated(gr[reg2]?gr[reg1]) 1 1 1 satsubi imm16,reg1,reg2 r r rr r1 10 01 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] saturated(gr[reg1]?sign-extend(imm16) 1 1 1 satsubr reg1,reg2 r r rr r0 00 10 0 rrrrr gr[reg2] saturated(gr[reg1]?gr[reg2]) 1 1 1 setf cccc,reg2 rrrrr1111110cccc 0000000000000000 if conditions are satisfied then gr[reg2] 00000001h else gr[reg2] 00000000h 1 1 1 appendix c instruction set list user?s manual u16031ej3v0ud 940 (5/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat bit#3,disp16[reg1] 00bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not (load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,1) 3 note 3 3 note 3 3 note 3 set1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100000 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,1) 3 note 3 3 note 3 3 note 3 reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000011000000 gr[reg2] gr[reg2] logically shift left by gr[reg1] 1 1 1 0 shl imm5,reg2 rrrrr010110iiiii gr[reg2] gr[reg2] logically shift left by zero-extend(imm5) 1 1 1 0 reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000010000000 gr[reg2] gr[reg2] logically shift right by gr[reg1] 1 1 1 0 shr imm5,reg2 rrrrr010100iiiii gr[reg2] gr[reg2] logically shift right by zero-extend(imm5) 1 1 1 0 sld.b disp7[ep],reg2 r r r r r 0 1 1 0 d d d d d d d adr ep+zero-extend(disp7) gr[reg2] sign-extend(load-memory(adr,byte)) 1 1 note 9 sld.bu disp4[ep],reg2 rrrrr0000110dddd note 18 adr ep+zero-extend(disp4) gr[reg2] zero-extend(load-memory(adr,byte)) 1 1 note 9 sld.h disp8[ep],reg2 r r r r r 1 0 0 0 d d d d d d d note 19 adr ep+zero-extend(disp8) gr[reg2] sign-extend(load-memory(adr,halfword)) 1 1 note 9 sld.hu disp5[ep],reg2 rrrrr0000111dddd notes 18, 20 adr ep+zero-extend(disp5) gr[reg2] zero-extend(load-memory(adr,halfword)) 1 1 note 9 sld.w disp8[ep],reg2 rrrrr1010dddddd0 note 21 adr ep+zero-extend(disp8) gr[reg2] load-memory(adr,word) 1 1 note 9 sst.b reg2,disp7[ep] r r r r r 0 1 1 1 d d d d d d d adr ep+zero-extend(disp7) store-memory(adr,gr[reg2],byte) 1 1 1 sst.h reg2,disp8[ep] r r r r r 1 0 0 1 d d d d d d d note 19 adr ep+zero-extend(disp8) store-memory(adr,gr[reg2],halfword) 1 1 1 sst.w reg2,disp8[ep] rrrrr1010dddddd1 note 21 adr ep+zero-extend(disp8) store-memory(adr,gr[reg2],word) 1 1 1 st.b reg2,disp16[reg1] r r rr r1 11 01 0 rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) store-memory(adr,gr[reg2],byte) 1 1 1 st.h reg2,disp16[reg1] r r rr r1 11 01 1 rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend(disp16) store-memory (adr,gr[reg2], halfword) 1 1 1 st.w reg2,disp16[reg1] rrrrr111011rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) store-memory (adr,gr[reg2], word) 1 1 1 stsr regid,reg2 r r rr r1 11 11 1 rrrrr 0000000001000000 gr[reg2] sr[regid] 1 1 1 appendix c instruction set list user?s manual u16031ej3v0ud 941 (6/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat sub reg1,reg2 r r rr r0 01 10 1 rrrrr gr[reg2] gr[reg2]?gr[reg1] 1 1 1 subr reg1,reg2 r r rr r0 01 10 0 rrrrr gr[reg2] gr[reg1]?gr[reg2] 1 1 1 switch reg1 00000000010rrrrr adr (pc+2) + (gr [reg1] logically shift left by 1) pc (pc+2) + (sign-extend (load-memory (adr,halfword)) logically shift left by 1 5 5 5 sxb reg1 00000000101rrrrr gr[reg1] sign-extend (gr[reg1] (7 : 0)) 1 1 1 sxh reg1 00000000111rrrrr gr[reg1] sign-extend (gr[reg1] (15 : 0)) 1 1 1 trap vector 00000111111iiiii 0000000100000000 eipc pc+4 (return pc) eipsw psw ecr.eicc exception code (40h to 4fh, 50h to 5fh) psw.ep 1 psw.id 1 pc 00000040h (when vector is 00h to 0fh (exception code: 40h to 4fh)) 00000050h (when vector is 10h to 1fh (exception code: 50h to 5fh)) 4 4 4 tst reg1,reg2 r r rr r0 01 01 1 rrrrr result gr[reg2] and gr[reg1] 1 1 1 0 bit#3,disp16[reg1] 11bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not (load-memory-bit (adr,bit#3)) 3 note 3 3 note 3 3 note 3 tst1 reg2, [reg1] r r rr r1 11 11 1 rrrrr 0000000011100110 adr gr[reg1] z flag not (load-memory-bit (adr,reg2)) 3 note 3 3 note 3 3 note 3 xor reg1,reg2 r r rr r0 01 00 1 rrrrr gr[reg2] gr[reg2] xor gr[reg1] 1 1 1 0 xori imm16,reg1,reg2 r r rr r1 10 10 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] xor zero-extend (imm16) 1 1 1 0 zxb reg1 00000000100rrrrr gr[reg1] zero-extend (gr[reg1] (7 : 0)) 1 1 1 zxh reg1 00000000110rrrrr gr[reg1] zero-extend (gr[reg1] (15 : 0)) 1 1 1 notes 1. dddddddd: higher 8 bits of disp9. 2. 4 if there is an instruction that rewrites the contents of the psw immediately before. 3. if there is no wait state (3 + the number of read access wait states). 4. n is the total number of list12 load registers. (a ccording to the number of wait states. also, if there are no wait states, n is the total number of list12 registers. if n = 0, same operation as when n = 1) 5. rrrrr: other than 00000. 6. the lower halfword data only are valid. 7. ddddddddddddddddddddd: the higher 21 bits of disp22. 8. ddddddddddddddd: the higher 15 bits of disp16. 9. according to the number of wait stat es (1 if there are no wait states). 10. b: bit 0 of disp16. 11. according to the number of wait stat es (2 if there are no wait states). appendix c instruction set list user?s manual u16031ej3v0ud 942 notes 12. in this instruction, for convenience of mnemonic descr iption, the source register is made reg2, but the reg1 field is used in the opcode. therefore, the m eaning of register specific ation in the mnemonic description and in the opcode differs from other instructions. rrrrr = regid specification rrrrr = reg2 specification 13. iiiii: lower 5 bits of imm9. iiii: higher 4 bits of imm9. 14. in the case of reg2 = reg3 (the lower 32 bits of the results are not written in the register) or reg3 = r0 (the higher 32 bits of the results are not wri tten in the register), shortened by 1 clock. 15. sp/imm: specified by bits 19 and 20 of the sub-opcode. 16. ff = 00: load sp in ep. 01: load sign expanded 16-bit immediate data (bits 47 to 32) in ep. 10: load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep. 11: load 32-bit immediate data (bits 63 to 32) in ep. 17. if imm = imm32, n + 3 clocks. 18. rrrrr: other than 00 000. 19. ddddddd: higher 7 bits of disp8. 20. dddd: higher 4 bits of disp5. 21. dddddd: higher 6 bits of disp8. 22. do not make a combination that satisfies all the following conditions when using the ?mul reg1, reg2, reg3? instruction and ?mulu reg1, reg2, reg3? in struction. operation is not guaranteed when an instruction that satisfies the fo llowing conditions is executed. ? reg1 = reg3 ? reg1 reg2 ? reg1 r0 ? reg3 r0 943 user?s manual u16031ej3v0ud appendix d revision history d.1 major revisions in this edition (1/3) page description throughout deletion of the following product appendix d revision history 9 44 user?s manual u16031ej3v0ud (2/3) page description p. 266 modification of figure 6-9 timing of 2-cycle dma transfer (sdram appendix d revision history 945 user?s manual u16031ej3v0ud (3/3) page description p. 544 addition of caution to table 10-7 conditions under which data can be transferred in slave mode p. 578 modification of description in 11.4.1 (4) uf0 epnak mask register (uf0enm) p. 612 modification of description in 11.4.1 (32) uf0 gpr register (uf0gpr) p. 694 modification of figure 11-21 processing for bulk transfer (in) (endpoint1) p. 718 modification of figure 11-30 usb connection example p. 718 addition of description to 11.7.8 (2) detecting usb cable connection/disconnection p. 835 change of 14.3.9 (2) (c) port cs function control register (pfccs) p. 849 addition of description to 14.6.3 (1) noise elimination width setting registers c0 to c3 (ncwc0 to ncwc3) p. 850 addition of note 1 to description on ncc1n, ncc0n bits in 14.6.3 (2) noise elimination width setting registers 10, 11 (ncw10, ncw11) p. 851 modification of table 14-4 relationship between ncw1n register set value and noise elimination width p. 858 modification of table 15-2 initial value of cpu, internal instruction ram, internal data ram, and on-chip peripheral i/o after reset p. 868 modification of table 16-1 emulator connector pin function p. 883 modification of t wwrh in chapter 17 (4) (c) write timing (sram, external rom, external i/o) pp. 885, 886 modification of t saw , t sbsw , and t diwrrd , note , and timing diagram in chapter 17 (4) (d) dma flyby transfer timing (transfer from sram to external i/o) pp. 887, 888 modification of t saw , t sbsw , t wwrh , and t dwrird , note , and timing diagram in chapter 17 (4) (e) dma flyby transfer timing (transfer from external i/o to sram) p. 892 modification of chapter 17 (6) (a) read timing (sdram access) p. 894 modification of chapter 17 (6) (b) write timing (sdram access) pp. 895, 896 addition of chapter 17 (6) (c) dma flyby transfer timing (transfer from external i/o to sdram) p. 897 modification of t hkdr in chapter 17 (7) (a) level mode p. 906 modification of t dhqha1 and t dhqha2 , and addition of notes 1 , 2 , and 3 in chapter 17 (8) bus hold timing p. 916 addition of 240-pin plastic fb ga (16 x 16) package drawing to chapter 18 package drawings p. 917 addition of caution to chapter 19 recommended soldering conditions p. 918 addition of appendix a notes appendix d revision history 9 46 user?s manual u16031ej3v0ud d.2 revision history up to previous edition the following table shows the revision history up to this edi tion. the ?applied to:? column indicates the chapters of each edition in which the revision was applied. (1/5) edition major revision from previous edition applied to: ? addition of the following product. pd703111gm-15-ueu ? change of the following register name. pfcal pfcall throughout addition of execution time of 150 mhz products to minimum instruction execution time in 1.2 features chapter 1 introduction addition of note in 2.1 (2) non-port pins addition of description in 2.3 (1) (b) (vii) uclk (usb clock) modification of description in 2.3 (3) (b) (ii) dmaak0, dmaak1 (dma acknowledge) modification of description in 2.3 (5) (b) (ii) dmaak2, dmaak3 (dma acknowledge) chapter 2 pin functions addition of execution time of 150 mhz products to minimum instruction execution time in 3.1 features modification of default value in 3.2.1 (2) program counter (pc) modification of description in 3.4.7 peripheral i/o registers change of table of vswc setting values in 3.4.9 system wait control register (vswc) chapter 3 cpu function modification of description in 4.2.1 pin status during internal instruction ram, internal data ram, and peripheral i/o access modification of description when bt n1 and btn0 bits are set to 11 in 4.4.1 (1) bus cycle type configuration registers 0, 1 (bct0, bct1) modification of table of num ber of access clocks in 4.5.1 number of access clocks addition to cautions and modification of description in 4.5.6 (1) line buffer control registers 0, 1 (lbc0, lbc1) addition of remark in 4.5.6 (1) (a) speculative read function (read buffer function) modification of desc ription, addition of note, and addition to cautions in 4.5.6 (1) (b) write buffer function addition to cautions in 4.7.1 (3) bus cycle period control register (bcp) modification of cautions in 4.9.1 (1) cache configuration register (bhc) addition of (5) in 4.10.3 cautions addition of timing and modification of notes in 4.11.6 (1) sdram (when read, latency = 2, no idle state insertion) addition of timing and modification of notes in 4.11.6 (2) sdram (when read, latency = 2, two idle states inserted, 32-bit bus width) addition of timing and modification of notes in 4.11.6 (3) sdram (when written) addition of 4.14 timing at which t0 state is not inserted chapter 4 bus control function addition of timing and modification of notes in figure 5-9 sdram single read cycle 2nd addition of timing and modification of notes in figure 5-10 sdram single write cycle chapter 5 memory access control function appendix d revision history 947 user?s manual u16031ej3v0ud (2/5) edition major revision from previous edition applied to: addition of timing and modification of notes in figure 5-11 sdram access timing modification of caution in 5.3.6 (1) sdram refresh control registers 1, 3, 4, 6 (rfs1, rfs3, rfs4, rfs6) modification of description in table 5-1 example of interval factor settings chapter 5 memory access control function addition of internal instruct ion ram in block diagram in 6.2 configuration addition to cautions in 6.3.1 (1) dma source address registers 0h to 3h (dsa0h to dsa3h) addition to cautions in 6.3.2 (1) dma destination address registers 0h to 3h (dda0h to dda3h) addition to cautions in 6.3.3 dma transfer count registers 0 to 3 (dbc0 to dbc3) addition to cautions in 6.3.4 dma addressing control registers 0 to 3 (dadc0 to dadc3) addition to cautions and description in 6.3.5 dma channel control registers 0 to 3 (dchc0 to dchc3) addition to cautions and description in 6.3.6 dma terminal count output control register (dtoc) addition to cautions in 6.3.7 dma trigger factor registers 0 to 3 (dtfr0 to dtfr3) addition of 6.3.7 (1) dma request detection function addition of caution and note and modification of description in 6.3.8 dma interface control register (difc) addition of timing and modification of notes in figure 6-12 timing of 2-cycle dma transfer (sdram sram) addition of 6.5.1 (1) timing of dmarqn and dmaakn signals for 2-cycle transfer addition of 6.5.1 (2) dmaakn signal active width extension function addition of 6.5.1 (3) outline of 2-cycle transfer timing modification of timing in figure 6-19 timing of dma flyby transfer (external i/o sdram) modification of timing in figure 6-23 timing of dma flyby transfer (sdram external i/o) modification of timing in figure 6-24 timing of dma flyby transfer (external i/o sdram) modification of descri ption and addition to caution in table 6-5 relationship between transfer type and transfer object addition of description in 6.8 next address setting function addition of cautions in 6.9 dma transfer start factors modification of description in 6.13 times related to dma transfer modification of description in 6.15 (3) bus arbitration for cpu addition of 6.15 (7) read values of dsan and ddan registers chapter 6 dma functions (dma controller) 2nd modification of note in figure 7-14 pipeline operation at interrupt request acknowledgment (outline) chapter 7 interrupt/exception processing function appendix d revision history 9 48 user?s manual u16031ej3v0ud (3/5) edition major revision from previous edition applied to: modification of selection of sscg output by pllsel pin and mdl-selector table (modulation period) in 8.1 features addition to cautions and modification of description in 8.3.1 clock control register (ckc) modification of sample coding <2> for data setting sequence of clock source select register (cks) in 8.3.2 clock source select register (cks) modification of description in 8.3.3 sscg control register (sscgc) addition of caution in 8.3.4 usb clock control register (uckc) modification of oscillati on stabilization time in 8.3.6 oscillation stabilization time select register (osts) addition to notes in table 8-1 operation status of each clock modification of description in table 8-2 frequency list addition of 8.5 operating clock provisions modification of oscillati on stabilization time in table 8-11 counting time examples chapter 8 clock generation function addition to caution in 9.1.5 (2) timer mode control registers c01 to c51 (tmcc01 to tmcc51) modification of figure 9-7 tmc1 compare operation example (set/reset output mode) addition of noise elimination width when f x = 150 mhz in table 9-6 relationship between ncw1n register set value and noise elimination width addition of 9.3.7 (6) overflow interrupt signal (intov1n) and underflow interrupt signal (intud1n) chapter 9 timer/ counter function (real-time pulse unit) modification of transfer rate in 10.2.1 features modification of description in 10.2.2 (10) uartbn receive data register ap (ubnrxap), uartbn receive data register (ubnrx) (n = 0, 1) addition of description in 10.2.2 (12) uartbn transmit data register n (ubntx) (n = 0, 1) modification of caution in 10.2.3 (3) uartbn control register 2 (ubnctl2) (n = 0, 1) addition of description in 10.2.3 (4) uartbn transmit data register (ubntx) (n = 0, 1) modification of description in 10.2.3 (5) uartbn receive data register ap (ubnrxap), uartbn receive data register (ubnrx) (n = 0, 1) addition and modification of description in 10.2.3 (6) uartbn fifo control register 0 (ubnfic0) (n = 0, 1) modification of description in 10.2.3 (7) uartbn fifo control register 1 (ubnfic1) (n = 0, 1) addition of description in 10.2.4 (5) (b) fifo mode addition of description in 10.2.5 (2) pending mode/pointer mode addition of note in 10.2.5 (2) (a) (i) during transmission (writing to transmit fifon) addition of note in 10.2.5 (2) (a) (ii) during recept ion (reading from receive fifon) chapter 10 serial interface function addition of description in 10.2.6 (4) (c) (ii) reception timeout interrupt (ubtiton) (in fifo mode only) 2nd addition of value when f x = 150 mhz in table 10-4 baud rate generator setting data chapter 10 serial interface function appendix d revision history 949 user?s manual u16031ej3v0ud (4/5) edition major revision from previous edition applied to: addition of 10.2.8 control flow modification of description in figure 10-22 block diagram of clocked serial interfaces 30 and 31 modification of description of caution 2 in 10.3.3 (1) clocked serial interface mode registers 30, 31 (csim30, csim31) modification of description in 10.3.3 (2) clocked serial interface clock select registers 30, 31 (csic30, csic31) addition of description in 10.3.3 (3) receive data buffer registers 30, 31 (sirb30, sirb31) addition of description in 10.3.3 (4) transmit data csi buffer registers 30, 31 (sfdb30, sfdb31) modification of description in 10.3.3 (5) csibuf status registers 30, 31 (sfa30, sfa31) modification of example in caution 2 in 10.3.4 (2) baud rate modification of description in figure 10-25 transfer data length: 8 bits (ccln3 to ccln0 bits = 1000 in csil3n register), transfer direction: msb first (dirn bit = 0 in csim3n register) modification of description in figure 10-26 transfer data length: 8 bits (ccln3 to ccln0 bits = 1000 in csil3n register), transfer direction: lsb first (dirn bit = 1 in csim3n register) deletion of description of 10.3.5 (7) slave mode modification of figure 10-30 slave mode (ckpn and dapn bits = 00 in csic3n register, ccln3 to ccln0 bits = 1000 in csil3n register (transfer data length: 8 bits)) modification of description in figure 10-32 continuous mode modification of description in 10.3.5 (11) transmission mode addition of description in 10.3.5 (12) reception mode deletion of description in 10.3.5 (16) (a) sckn pin modification of description in table 10-8 default output level of sckn pin modification of descripti on of (1) to (12) in 10.3.6 usage chapter 10 serial interface function addition of caution in 11.1 overview addition of items in table 11-2 correspondence between requests and decoded values addition of description in 11.4.1 (3) uf0 epnak register (uf0en) deletion of description in 11.4.1 (9) uf0 ep status 1 register (uf0eps1) modification of description in 11.4.1 (11) uf0 int status 0 register (uf0is0) modification of description in 11.4.1 (34) uf0 mode status register (uf0mods) modification of description in 11.4.3 (2) uf0 ep0 status register l (uf0e0sl) modification of description in 11.4.3 (9) uf0 address register (uf0adrs) modification of description in 11.4.3 (10) uf0 configuration register (uf0cnf) modification of description in 11.4.3 (11) uf0 interface 0 register (uf0if0) 2nd modification of description in 11.4.3 (12) uf0 interface 1 to 4 registers (uf0if1 to uf0if4) chapter 11 usb function controller (usbf) appendix d revision history 9 50 user?s manual u16031ej3v0ud (5/5) edition major revision from previous edition applied to: modification of caution 2 in 11.4.3 (14) uf0 device descriptor registers 0 to 17 (uf0dd0 to uf0dd17) modification of caution 2 in 11.4.3 (15) uf0 configuration/interface/endpoint descriptor registers 0 to 255 (uf0cie0 to uf0cie255) modification of caution in 11.4.4 (1) usb function 0 dma channel select register (uf0cs) deletion of caution in table 11-8 fw-supported standard requests modification of description in figure 11-15 automatically processed requests for control transfer modification of description in figure 11-20 cpudec request for control transfer modification of description in figure 11-30 usb connection example chapter 11 usb function controller (usbf) addition of value when f x = 150 mhz in table 12-1 setting of a/d conversion operation time addition of 12.9 how to read a/d converter characteristics table chapter 12 a/d converter modification of repeat frequency in 13.1 features modification of description in figure 13-1 block diagram of pwm unit modification of description in 13.3 (1) pwm control registers 0 and 1 (pwmc0 and pwmc1) modification of description in 13.4.2 (1) setting for starting pwm operation modification of description in table 13-1 repeat cycle of pwmn chapter 13 pwm unit modification of caution in 14.3.8 port dh modification of caution and description on bit 0 in 14.3.8 (2) (c) port dh function control register (pfcdh) addition to caution in 14.3.10 (2) (c) port ct function control register (pfcct) addition of noise elimination width when f x = 150 mhz in table 14-4 relationship between ncw1n register set value and noise elimination width chapter 14 port functions modification of value of program counter (pc) after reset in table 15-2 initial value of cpu, internal data ram, internal instruction ram, and on-chip peripheral i/o after reset chapter 15 reset functions modification of description in 16.1.1 (7) mask function chapter 16 debug function (dcu) addition of chapter 17 electrical specifications (target values) chapter 17 electrical specifications addition of chapter 18 package drawing chapter 18 package drawing addition of chapter 19 recommended soldering conditions chapter 19 recommended soldering conditions addition to note in b.2 instruction set (in alphabetical order) appendix b instruction set list 2nd addition of appendix c revision history appendix c revision history |
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