rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD7545 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1997 preliminary technical data cmos 12-bit buffered multiplying dac functional block diagram 19 16 17 20 1 2 3 18 AD7545 r r fb out 1 agnd v dd dgnd db11?b0 (pins 4?5) 12 12 12-bit multiplying dac input data latches v ref wr cs features 12-bit resolution low gain tc: 2 ppm/ 8 c typ fast ttl compatible data latches single +5 v to +15 v supply small 20-lead 0.3" dip and 20-terminal surface mount packages latch free (schottky protection diode not required) low cost ideal for battery operated equipment pin configurations dip lccc plcc general description the AD7545 is a monolithic 12-bit cmos multiplying dac with onboard data latches. it is loaded by a single 12-bit wide word and directly interfaces to most 12- and 16-bit bus systems. data is loaded into the input latches under the control of the cs and wr inputs; tying these control inputs low makes the input latches transparent, allowing direct unbuffered operation of the dac. the AD7545 is particularly suitable for single supply operation and applications with wide temperature variations. the AD7545 can be used with any supply voltage from +5 v to +15 v. with cmos logic levels at the inputs the device dissi- pates less than 0.5 mw for v dd = +5 v. 20 19 18 db6 db5 db4 db3 db2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 dgnd top view (not to scale) pin 1 identifier agnd db11 (msb) db10 r fb db9 v ref db8 db7 v dd wr out 1 cs db0 (lsb) db1 AD7545 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) AD7545 out 1 wr v dd v ref r fb agnd dgnd db11 (msb) db1 db0 (msb) cs db10 db9 db8 db7 db6 db5 db4 db3 db2 20 19 1 2 3 18 14 15 16 17 4 5 6 7 8 9 10 11 12 13 top view (not to scale) AD7545 db11 (msb) db10 db9 db8 db7 v dd wr cs db0 (lsb) db1 db6 db5 db4 db3 db2 dgnd agnd out 1 v ref r fb
C2C rev. a AD7545Cspecifications preliminary technical data v dd = +5 v v dd = +15 v limits limits parameter version t a = + 25 8 ct min, t max 1 t a = + 25 8 ct min, t max 1 units test conditions/comments static performance resolution all 12 12 12 12 bits j, a, s 2 2 2 2 lsb max k, b, t 1 1 1 1 lsb max l, c, u 1/2 1/2 1/2 1/2 lsb max gl, gc, gu 1/2 1/2 1/2 1/2 lsb max differential nonlinearity j, a, s 4 4 4 4 lsb max 10-bit monotonic t min to t max k, b, t 1 1 1 1 lsb max 12-bit monotonic t min to t max l, c, u 1 1 1 1 lsb max 12-bit monotonic t min to t max gl, gc, gu 1 1 1 1 lsb max 12-bit monotonic t min to t max gain error (using internal rfb) 2 j, a, s 20 20 25 25 lsb max dac register loaded with k, b, t 10 10 15 15 lsb max 1111 1111 1111 l, c, u 5 6 10 10 lsb max gain error is adjustable using gl, gc, gu 1 2 6 7 lsb max the circuits of figures 4, 5, and 6 gain temperature coefficient 3 d gain/ d temperature all 5 5 10 10 ppm/ c max typical value is 2 ppm/ c for v dd = +5 v dc supply rejection 3 d gain/ d v dd all 0.015 0.03 0.01 0.02 % per % max d v dd = 5% output leakage current at out1 j, k, l, gl 10 50 10 50 na max db0Cdb11 = 0 v; wr , cs = 0 v a, b, c, gc 10 50 10 50 na max s, t, u, gu 10 200 10 200 na max dynamic performance current settling time 3 all 2 2 2 2 m s max to 1/2 lsb. out1 load = 100 w . dac output measured from falling edge of wr , cs = 0. propagation delay 3 (from digital input change to 90% of final analog output) all 300 C 250 C ns max out1 load = 100 w , c ext = 13 pf 4 digital-to-analog glitch inpulse all 400 C 250 C nv sec typ v ref = agnd ac feedthrough 5 at out1 all 5 5 5 5 mv p-p typ v ref = 10 v, 10 khz sinewave reference input input resistance all 7 7 7 7 k w min input resistance tc = C300 ppm/ c typ (pin 19 to gnd) 25 25 25 25 k w max typical input resistance = 11 k w analog output output capacitance 3 c out1 all 70 70 70 70 pf max db0Cdb11 = 0 v, wr , cs = 0 v c out1 200 200 200 200 pf max db0Cdb11 = v dd , wr , cs = 0 v digital inputs input high voltage v ih all 2.4 2.4 13.5 13.5 v min input low voltage v il all 0.8 0.8 1.5 1.5 v max input current 6 i in all 1 10 1 10 m a max v in = 0 or v dd input capacitance 3 db0Cdb11 all 5 5 5 5 pf max v in = 0 wr , cs all 20 20 20 20 pf max v in = 0 switching characteristics 7 chip select to write setup time all 280 380 180 200 ns min see timing diagram t cs 200 270 120 150 ns typ chip select to write hold time t ch all 0 0 0 0 ns min write pulse width t wr all 250 400 160 240 ns min t cs 3 t wr , t ch 3 0 175 280 100 170 ns typ data setup time all 140 210 90 120 ns min t ds 100 150 60 80 ns typ data hold time t dh all 10 10 10 10 ns min power supply i dd all 2 2 2 2 ma max all digital inputs v il or v ih 100 500 100 500 m a max all digital inputs 0 v to v dd 10 10 10 10 m a typ all digital inputs 0 v to v dd notes 1 temperature range as follows: j, k, l, gl versions, 0 c to +70 c; a, b, c, gc versions, C25 c to +85 c; s, t, u gu versions, C55 c to +125 c. 2 this includes the effect of 5 ppm max gain tc. 3 guaranteed but not tested. 4 db0Cdb11 = 0 v to v dd or v dd to 0 v. 5 feedthrough can be further reduced by connecting the metal lid on the ceramic package (suffix d) to dgnd. 6 logic inputs are mos gates. typical input current (+25 c) is less than 1 na. 7 sample tested at +25 c to ensure compliance. specifications subject to change without notice. (v ref = +10 v, v out1 = o v, agnd = dgnd unless otherwise noted)
AD7545 C3C rev. a preliminary technical data absolute maximum ratings* (t a = + 25 c unless otherwise noted) v dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3, +17 v digital input voltage to dgnd . . . . . . . C0.3 v, v dd +0.3 v v rfb , v ref to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . 25 v v pin1 to dgnd . . . . . . . . . . . . . . . . . . . . C0.3 v, v dd +0.3 v agnd to dgnd . . . . . . . . . . . . . . . . . C0.3 v, v dd + 0.3 v power dissipation (any package) to +75 c . . . . . . . 450 mw derates above +75 c . . . . . . . . . . . . . . . . . . . . . . 6 mw/ c operating temperature terminology relative accuracy the amount by which the d/a converter transfer function differs from the ideal transfer function after the zero and full- scale points have been adjusted. this is an endpoint linearity measurement. differential nonlinearity the difference between the measured change and the ideal change between any two adjacent codes. if a device has a differ- ential nonlinearity of less than 1 lsb it will be monotonic, i.e., the output will always increase for an increase in digital code applied to the d/a converter. propagation delay this is a measure of the internal delay of the circuit and is mea- sured from the time a digital input changes to the point at which the analog output at out1 reaches 90% of its final value. digital-to-analog glitch impulse this is a measure of the amount of charge injected from the digital inputs to the analog outputs when the inputs change state. it is usually specified as the area of the glitch in nv secs and is measured with v ref = agnd and an adlh0032cg as the output op amp, c1 (phase compensation) = 33 pf. commercial (j, k, l, gl) grades . . . . . . . . 0 c to +70 c industrial (a, b, c, gc) grades . . . . . . . . C25 c to +85 c extended (s, t, u, gu) grades . . . . . . . C55 c to +125 c storage temperature . . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 secs) . . . . . . . . . . . +300 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD7545 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide 1 maximum gain error temperature relative t a = +25 8 c package model 2 range accuracy v dd = +5 v options 3 AD7545jn 0 c to +70 c 2 lsb 20 lsb n-20 AD7545aq C25 c to +85 c 2 lsb 20 lsb q-20 AD7545sq C55 c to +125 c 2 lsb 20 lsb q-20 AD7545kn 0 c to +70 c 1 lsb 10 lsb n-20 AD7545bq C25 c to +85 c 1 lsb 10 lsb q-20 AD7545tq C55 c to +125 c 1 lsb 10 lsb q-20 AD7545ln 0 c to +70 c 1/2 lsb 5 lsb n-20 AD7545cq C25 c to +85 c 1/2 lsb 5 lsb q-20 AD7545uq C55 c to +125 c 1/2 lsb 5 lsb q-20 AD7545gln 0 c to +70 c 1/2 lsb 1 lsb n-20 AD7545gcq C25 c to +85 c 1/2 lsb 1 lsb q-20 AD7545guq C55 c to +125 c 1/2 lsb 1 lsb q-20 AD7545jp 0 c to +70 c 2 lsb 20 lsb p-20a AD7545se C55 c to +125 c 2 lsb 20 lsb e-20a AD7545kp 0 c to +70 c 1 lsb 10 lsb p-20a AD7545te C55 c to +125 c 1 lsb 10 lsb e-20a AD7545lp 0 c to +70 c 1/2 lsb 5 lsb p-20a AD7545ue C55 c to +125 c 1/2 lsb 5 lsb e-20a AD7545glp 0 c to +70 c 1/2 lsb 1 lsb p-20a AD7545gue C55 c to +125 c 1/2 lsb 1 lsb e-20a notes 1 analog devices reserves the right to ship either ceramic (d-20) in lieu of cerdip packages (q-20). 2 to order mil-std-883, class b process parts, add /883b to part number. contact local sales office for military data sheet. for u.s. standard military drawing (smd) see desc drawing 5962-87702. 3 e = leadless ceramic chip carrier; n = plastic dip; p = plastic leaded chip carrier; q = cerdip. write cycle timing diagram chip select write data in (db0?b11) v dd 0 v dd 0 v dd 0 data valid v ih v il t ds t dh t wr t cs t ch mode selection cs and wr low, dac responds to data bus (db0?b11) inputs. write mode: hold mode: either cs or wr high, data bus (db0?b11) is locked out; dac holds last data present when wr or cs assumed high state. notes: v dd = +5v; t r = t f = 20ns v dd = +15v; t r = t f = 40ns all input signal rise and fall times measured from 10% to 90% of v dd . timing measurement reference level is v ih + v il /2.
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