features to other serial devices v bb regulator kgn gnd v cc gnd microprocessor port port port port gnd 0.1 f d in vfd driver gnd gren stb clk an31 an30 an29 an6 an5 an4 an3 an2 an1 grid2 grid1 grid3 multiplexed vf display 5v 12.5v metal mask rom six 20ma anode drivers twenty-five, 2ma anode drivers three, 50ma grid drivers power on reset display dimming possible package options cs1085 vacuum fluorescent display tube driver cs1085 description absolute maximum ratings supply voltage (v bb ) .....................................................................-0.6v to 18.0v input voltages (d in , clk, stb, gren) .......................................-0.6v to 6.0v maximum power dissipation (@t a = 105c)............................................1.0w junction temperature range ......................................................-40c to 150c storage temperature range ........................................................-55c to 150c esd susceptibility (human body model) ...................................................2kv esd susceptibility (machine model) ..........................................................200v lead temperature soldering wave solder(through hole styles only)...........10 sec. max, 260c peak reflow (smd styles only)...........60 sec. max above 183c, 230c peak 140 40 lead pdip 1 144 44 lead plcc cherry semiconductor corporation 2000 south county trail, east greenwich, ri 02818 tel: (401)885-3600 fax: (401)885-5786 email: info@cherry-semi.com web site: www.cherry-semi.com a company ? rev. 7/23/99 the vfd driver is a microprocessor interface ic that drives a multi- plexed vf (vacuum fluorescent) display tube. it consists of a 34-bit shift register, a 34-bit transparent data latch, a metal mask rom, six 20ma anode output drivers, twen- ty-five 2ma anode output drivers, and three 50ma grid drivers with output enables. the metal mask programmable rom (at factory request) allows the 31 anode out- puts and 3 grid outputs to be assigned to any of the 34 serial data bits. application diagram 48 lead lqfp 48 1
cs1085 2 electrical characteristics: 8.0v v bb 16.5v, gnd = 0v, -40c t a 105c, the sign (+ or -) refers to the direction of the current (positive current goes into the lead); unless otherwise stated parameter test conditions min typ max unit v bb input v bb input voltage 8.0 16.5 v i bb0 current no outputs active, v bb = 12.5v 29 38 ma no outputs active, v bb = 16.5v 30 40 ma i bb2 current per active no load on grid and anode outputs, 0.20 0.45 ma 2ma output v bb = 16.5v i bb20 current per active no load on grid and anode outputs, 2.0 4.0 ma 20ma output v bb = 16.5v i bb50 current per active no load on grid and anode outputs, 6.0 9.0 ma 50ma output v bb = 16.5v din, clk, stb inputs v ill , input low voltage 1.575 v v ih , input high voltage 3.325 v i il , input current v in = v ih 020a gren input v il , input low voltage 1.575 v v ih , input high voltage 3.325 v i ih , input pull-down v in = 3.325v 30 90 170 a current grid1, grid2, grid3 outputs i ol 1.0 ma i oh -50.0 ma v ol i out = 1ma 0.5 v v oh i out = -50ma v bb - 0.5 v bb v an24-an29 outputs i ol 400 a i oh -20.0 ma v ol i out = 400a 0.5 v v oh i out = -20ma v bb - 0.5 v bb v an1-an23, an30-an31 outputs i ol 100 a i oh -2.0 ma v ol i out = 100a 0.5 v v og i out = -2ma v bb - 0.5 v bb v
cs1085 3 electrical characteristics: 8.0v v bb 16.5v, gnd = 0v, -40c t a 105c, the sign (+ or -) refers to the direction of the current (positive current goes into the lead); unless otherwise stated parameter test conditions min typ max unit package lead description package lead # lead symbol function ac characteristics: input and output timing f c , clk frequency dc 600 khz t cl , clk low time 300 ns t ch , clk high time 300 ns t cr , clk rise time 100 ns t cf , clk fall time 100 ns t cs , clk low to stb high time 0 ns t sc , stb low to clk high time 0 ns t st , stb high time 500 ns t an , stb high to anode 5.0 s output propagation delay t gl , grid enable time 5.0 s t g0 , grid disable time 10.0 s t gr , grid rise time 0.250 5.0 s t gf , grid fall time 0.250 5.0 s t ar , anode rise time 0.150 5.0 s t tf , anode fall time 0.150 5.0 s note: grid and anode rise/fall times are measured from 10% and 90% points. output currents are at the maximum rated currents for the respective stages. 40l dip 44l plcc 48l lqfp (31 anode configuration) 1 14 8 grid1 50ma grid output. 2 15 9 grid2 50ma grid output. 3 16 10 grid3 50ma grid output. 4 17 11 an1 2ma anode output. 5 18 13 an2 2ma anode output. 6 19 14 an3 2ma anode output. 7 20 15 an4 2ma anode output. 8 21 16 an5 2ma anode output. 9 22 17 an6 2ma anode output. 10 24 19 an7 2ma anode output. 11 25 20 an8 2ma anode output. 12 26 21 an9 2ma anode output. 13 27 22 an10 2ma anode output. 14 28 23 an11 2ma anode output. 15 29 25 an12 2ma anode output. 16 30 26 an13 2ma anode output. 17 31 27 an14 2ma anode output. 18 32 28 an15 2ma anode output.
cs1085 4 operation description package lead # lead symbol function package lead description: continued 40l dip 44l plcc 48l lqfp (31 anode configuration) 19 33 29 an16 2ma anode output. 20 35 31 gnd ground connection. 21 36 32 an17 2ma anode output. 22 37 33 an18 2ma anode output. 23 38 34 an19 2ma anode output. 24 39 35 an20 2ma anode output. 25 40 37 an21 2ma anode output. 26 41 38 an22 2ma anode output. 27 42 39 an23 2ma anode output. 28 43 40 an24 20ma anode output. 29 44 41 an25 20ma anode output. 30 2 43 an26 20ma anode output. 31 3 44 an27 20ma anode output. 32 4 45 an28 20ma anode output. 33 5 46 an29 20ma anode output. 34 6 47 an30 2ma anode output. 35 7 1 d in shift register data input. 36 8 2 clk shift register clock input. 37 9 3 stb transfer contents of shift registers to out- put stages. 38 10 4 gren grid outputs enable. 39 11 5 an31 2ma anode output. 40 13 7 v bb supply voltage input. 1, 12, 23, 34 6, 12, 18, 24 nc no connection. 30, 36, 42, 48 upon the initial application of power, the power on reset function will cause all of the anode and grid driver outputs to be off and all shift register outputs to be set low. data is fed into the shift register through the d in pin at the rising edge of the clk input. thirty four bits of data are capable of being stored by the shift register. once the desired pat- tern is stored in the shift register, it can be transferred to the latch by setting the stb input high. the output of each latch drives its corresponding output stage. a logic high input to the shift register/latch will cause the correspond- ing output to turn on. a logic low input to the shift register/latch will cause the corresponding output to turn off. please note that if the stb is held high, the outputs of the latch reflect the outputs of the corresponding shift reg- ister bits and will change if data is shifted in. the three grid outputs are gated by the gren input. when gren is low, the grid outputs are forced low regardless of the state of the corresponding latch output. when gren is high, the grid outputs correspond to the state of their respective latch outputs. the anode outputs, an1 to an31 are always enabled.
cs1085 5 block diagram typical operation * selected grid goes high only if input bit pattern from shift register to grid is high. application information bit # 1234567891011121314151617 pin name g1 g2 g3 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 table 1: bit pattern, g = grid, a = anode. bit # 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 pin name a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 an31 an30 an29 an28 an27 an26 an25 an3 an2 an1 grid3 grid2 grid1 v bb gnd gren stb d in clk v reg v reg v reg v reg por v reg metal mask rom d q r d q r d q r d q r d q r d q r d q r d q r d q r d q r d q r d q r d q r clk clk clk clk clk clk clk clk clk clk clk clk clk d q le d q le d q le d q le d q le d q le d q le d q le d q le d q le d q le d q le d q le v reg output drive capability grid outputs: 50ma an24 - an29: 20ma an1 - an23, an30, an31: 2ma clk in d in stb anodes gren grids * 1 2 3 4 6 7 8 9 32 33 34 1 2 3 5 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 32 bit 33 bit 34 bit 1 bit 2 bit 3
ab ab lead count metric english max min max min max min max min 44l plcc 17.65 17.40 16.66 16.51 .695 .685 .656 .650 cs1085 6 rev. 7/23/99 ? 1999 cherry semiconductor corporation package specification package dimensions in mm (inches) d lead count metric english max min max min 40l pdip 52.3 53.2 1.980 2.095 thermal data 40l 44l 48l pdip plcc lqfp r jc typ 20 16 ? c/w r ja typ 45 55 ? c/w package thermal data ordering information part number description cs1085xn40 40 lead pdip cs1085xfn44 44 lead plcc cs1085xfnr44 44 lead plcc (tape & reel) cs1085xfl48 48 lead lqfp CS1085XFLR48 48 lead lqfp (tape & reel) plastic dip (n); 600 mil wide d ref: jedec ms-011 15.87 (.625) 15.24 (.600) 14.73 (.580) 12.32 (.485) 1.77 (.070) 1.14 (.045) 2.54 (1.00) bsc 3.94 (.155) 3.18 (.125) .558 (.022) .356 (.014) 0.39 (.015) min plcc (fn) ref jedec mo-047 4.06 (.160) 3.69 (.145) .66 (.026) .81 (.032) 1.27 (.050) bsc b a b a .53 (.021) .33 (.013) .51 (.020) min 48 lead lqfp (fl) 7 7mm body 9.00 (.354) bsc 7.00 (.276) bsc 0.50 (.020) bsc 9.00 bsc (.354) 7.00 bsc (.276) 0.75 (.030) 0.45 (.018) see detail a 1.60 (.063) max 1.00 (.039) ref 1.45 (.057) 1.35 (.053) 0.20 (.008) 0.09 (.004) 0.15 (.006) 0.05 (.002) ref jedec ms-026 detail a 0.27 (.011) 0.17 (.007) cherry semiconductor corporation reserves the right to make changes to the specifications without notice. please contact cherry semiconductor corporation for the latest available information.
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