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8733-01 www.icst.com/products/hipercocks.html july 17, 2001 1 ics8733-01 f orward e rror c orrection c lock g enerator advanced information b lock d iagram p in a ssignment 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32-lead lqfp y package top view div_sel0 div_sel1 mr pll_sel ref_clk nref_clk fec_nsel fec_msel test_sel test_en fout1 nfout1 fout0 nfout0 test 0 1 0 1 15 14 14 0 1 pll 0 1 15 1 2 4 0 0 0 1 1 0 1 1 ref_clk nref_clk vdda vdda div_sel0 div_sel1 nc mr nc fec_nsel fec_msel vee vee test_sel test_en gnd vee nfout0 fout0 vddo nfout1 fout1 vdd test nc nc pll_sel vdd vdd nc nc nc ics8733-01 ? n ? ? m ? g eneral d escription f eatures hiperclocks? ,&6 the ics8733-01 is a dual output clock genera- tor and a member of the hiperclocks ? family of high performance clock solutions from ics. the ics8733-01 is designed to be used for ap- plications utilizing forward error correction (fec) designs. the ics8733-01 generates a 14/15 or a 15/ 14 output clock based upon the input reference clock in order to incorporate the fec capability required by the application. clock generator is performed by a fully integrated and low-jitter phase-locked loop. the ics8733-01 accepts any differential signal as its input with an input reference fre- quency range of 36.27mhz to 750mhz. there are two lvpecl outputs which can generate output frequencies of 38.88mhz to 700mhz. ? clock synthesis of 14/15 or 15/14 of the input reference clock to be utilized in forward error correction (fec) applications ? fully integrated pll ? accepts any differential input signal (pecl, hstl, lvds, sstl, etc.) ? dual differential 3.3v lvpecl outputs ? 38.88mhz to 700mhz output frequency ? pll bypass and test modes that support in-circuit testing and on-chip functional block characterization ? lvttl / lvcmos control inputs ? 3.3v supply voltage ? 32 lead low profile qfb (lqfp), 7mm x 7mm x 1.4mm package body, 0.8mm package lead pitch ? 0 c to 70 c ambient operating temperature the advance information presented herein represents a product currently in design or being considered for design. the noted cha racteristics are design targets. integrated circuit systems, incorporated (ics) reserves the right to change any circuitry or specifications wit hout notice. 8733-01 www.icst.com/products/hipercocks.html july 17, 2001 2 ics8733-01 f orward e rror c orrection c lock g enerator advanced information f unctional d escription the ics8733-01 features a fully integrated pll and therefore requires no external component for setting the loop bandwidth. the ics8733-01 will generate an output having a frequency as follows: the m and n bits are controlled by the fec_nsel and fec_msel control pins as shown in table 3a and table 3b. as a result, fout0 can be configured to have an output frequency equal to 14/15, 15/14, 14/14, or 15/15 of the reference input frequency. the second output clock (fout1) is configured to produce a frequency equal to fout0, fout/2, fout0/4, or fout0x4, dependent upon the div_sel0 and div_sel1 bits as shown in table 3c. the reference input frequency range is dependent upon not only the m and n bits, but also upon the fout1 output configuration which is determined by the div_sel0 and div_sel1 bits. table 3b shows the possible fout0 and fout1 output configurations as well as the reference input frequency range for each of these configurations. the ics8733-01 also supports in-circuit testing and on-chip functional block characterization via two test inputs and one test output. with the ics8733-01 in pll bypass mode (pll_sel = 0), the reference input bypasses the pll and in-circuit testing of the n, m, and output dividers can take place. table 3d shows the output configurations for the different combinations of the div_sel1 and div_sel0 pins. ffout0 = fref_clk x m n 8733-01 www.icst.com/products/hipercocks.html july 17, 2001 3 ics8733-01 f orward e rror c orrection c lock g enerator advanced information t able 1. p in d escriptions t able 2. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n i c t u p n i e c n a t i c a p a c , k l c _ f e r k l c _ f e r n d b tf p , r m , l e s _ l l p , n e _ t s e t , l e s _ t s e t , 0 l e s _ v i d , 1 l e s _ v i d , l e s n _ c e f l e s m _ c e f d b tf p p u l l u p r t u p n i r o t s i s e r p u l l u p 1 5k ? n w o d l l u p r t u p n i n w o d l l u p r o t s i s e r 1 5k ? r e b m u ne m a ne p y tn o i t p i r c s e d , 8 1 , 1 , 6 2 , 5 2 2 3 , 1 3 , 0 3 c nd e s u n u. n i p d e s u n u 2l e s n _ c e ft u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . e u l a v e d i v i d n e h t s t c e l e s 3l e s m _ c e ft u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . e u l a v e d i v i d m e h t s t c e l e s 6 1 , 8 , 5 , 4e e vr e w o p. d n u o r g o t t c e n n o c . n i p d n u o r g 6l e s _ t s e tt u p n in w o d l l u p . s e d o m t s e t t n e r e f f i d o w t f o e n o o t n i p t u p t u o t s e t e h t s e r u g i f n o c . s l e v e l e c a f r e t n i l t t v l / s o m c v l 7n e _ t s e tt u p n in w o d l l u p . s l e v e l e c a f r e t n i l t t v l / s o m c v l . n i p t u p t u o t s e t e h t s e l b a n e 9t s e tt u p t u o . d 3 e l b a t n i n w o h s s a n i p l e s _ t s e t g n i s u d e m m a r g o r p . n i p t s e t t u p t u o 9 2 , 8 2 , 0 1d d vr e w o p. t u p t u o t s e t d n a e r o c r o f n i p y l p p u s r e w o p 2 1 , 1 1 , 1 t u o f 1 t u o f n t u p t u o . s l e v e l e c a f r e t n i l c e p v l v 3 . 3 . r o t a r e n e g e h t r o f t u p t u o l a i t n e r e f f i d 3 1o d d vr e w o p. v 3 . 3 o t t c e n n o c . s n i p y l p p u s r e w o p t u p t u o 5 1 , 4 1 , 0 t u o f 0 t u o f n t u p t u o . s l e v e l e c a f r e t n i l c e p v l v 3 . 3 . r o t a r e n e g e h t r o f t u p u o l a i t n e r e f f i d 7 1r mt u p n in w o d l l u p . w o l 1 t u o f d n a 0 t u o f s e c r o f . r e d i v i d t u p t u o d n a , n , m e h t s t e s e r . s l e v e l e c a f r e t n i l t t v l / s o m c v l 0 2 , 9 1 , 1 l e s _ v i d 0 l e s _ v i d t u p n in w o d l l u p . 1 t u o f r o f e u l a v e d i v i d t u p t u o e h t s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l 2 2 , 1 2a d d vr e w o p. v 3 . 3 o t t c e n n o c . n i p y l p p u s r e w o p l l p 3 2, k l c _ f e r nt u p n ip u l l u p. s l e v e l l a i t n e r e f f i d y n a s t p e c c a . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 4 2k l c _ f e rt u p n in w o d l l u p . s l e v e l l a i t n e r e f f i d y n a s t p e c c a . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 7 2l e s _ l l pt u p n ip u l l u p . e d o m s s a p y b r o l l p n i s i r o t a r e n e g r e h t e h w s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l 8733-01 www.icst.com/products/hipercocks.html july 17, 2001 4 ics8733-01 f orward e rror c orrection c lock g enerator advanced information t able 3c. o utput c onfiguration and i nput f requency r ange t able t able 3a. fec_nsel t ruth t able t able 3d. o utput c onfiguration t able for t est m ode o peration (pll_sel = 0 and test_en = 1) 1 l e s _ v i d0 l e s _ v i d0 t u o f1 t u o f ) z h m ( e g n a r y c n e u q e r f t u p n i e c n e r e f e r : l e s n _ c e f 0 0 = l e s m _ c e f : l e s n _ c e f 1 0 = l e s m _ c e f : l e s n _ c e f 0 1 = l e s m _ c e f : l e s n _ c e f 1 1 = l e s m _ c e f 00 n / m x f e r fn / m 4 x f e r f7 6 . 1 8 - 7 2 . 6 30 5 . 7 8 - 7 2 . 6 30 5 . 7 8 - 8 8 . 8 35 7 . 3 9 - 8 8 . 8 3 01 n / m x f e r fn / m x f e r f7 6 . 6 2 3 - 3 . 3 90 5 3 - 0 0 10 5 3 - 0 0 15 7 3 - 1 . 7 0 1 10 n / m x f e r fn 2 / m x f e r f3 3 . 3 5 6 - 7 . 6 8 10 0 7 - 0 0 20 0 7 - 0 0 20 5 7 - 3 . 4 1 2 11 n / m x f e r fn 4 / m x f e r f3 3 . 3 5 6 - 7 . 6 8 10 0 7 - 0 0 20 0 7 - 0 0 20 5 7 - 3 . 4 1 2 1 l e s _ v i d0 l e s _ v i d0 t u o f1 t u o f t s e t 0 = l e s _ t s e t1 = l e s _ t s e t 00 n 4 / f e r fn / f e r fn / f e r f 2n m 2 / f e r f 01 n / f e r fn / f e r fn / f e r f 2n m / f e r f 2 10 n / f e r fn 2 / f e r fn / f e r fn m / f e r f 11 n / f e r fn 4 / f e r fn / f e r fn m / f e r f l e s n _ c e fn 04 1 15 1 t able 3b. fec-msel t ruth t able l e s m _ c e fm 05 1 14 1 8733-01 www.icst.com/products/hipercocks.html july 17, 2001 5 ics8733-01 f orward e rror c orrection c lock g enerator advanced information t able 4a. p ower s upply dc c haracteristics , vdd=vdda=vddo=3.3v5%, t a =0 c to 70 c a bsolute m aximum r atings supply voltage 4.6v inputs -0.5v to vdd+0.5 v outputs -0.5v to vdd+0.5v ambient operating temperature 0 c to 70 c storage temperature -65 c to 150 c stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any conditions beyond those listed in the dc character- istics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u d d ve g a t l o v y l p p u s r e w o p t u p n i 5 3 1 . 33 . 35 6 4 . 3v a d d ve g a t l o v y l p p u s r e w o p g o l a n a 5 3 1 . 33 . 35 6 4 . 3v o d d ve g a t l o v y l p p u s r e w o p t u p t u o 5 3 1 . 33 . 35 6 4 . 3v e e it n e r r u c y l p p u s r e w o p a m t able 4b. d ifferential dc c haracteristics , vdd=vdda=vddo=3.3v5%, t a =0 c to 70 c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u h i it n e r r u c h g i h t u p n i k l c _ f e rv 5 6 4 . 3 = n i v0 5 1a k l c _ f e r nv 5 6 4 . 3 = n i v5a l i it n e r r u c w o l t u p n i k l c _ f e rv 0 = n i v5 -a k l c _ f e r nv 0 = n i v0 5 1 -a . e l b a t s c i t s i r e t c a r a h c c a n i r m c v d n a p p v e e s , s l e v e l t u p n i k l c _ f e r n , k l c _ f e r r o f : e t o n 8733-01 www.icst.com/products/hipercocks.html july 17, 2001 6 ics8733-01 f orward e rror c orrection c lock g enerator advanced information t able 4c. lvcmos/lvttl dc c haracteristics , vdd=vdda=vddo=3.3v5%, t a =0 c to 70 c t able 5. i nput f requency c haracteristics , vdd=vdda=vddo=3.3v5%, t a =0 c to 70 c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n i f m u m i x a m y c n e u q e r f t u p n i k l c _ f e r7 2 . 6 30 5 7z h m r te m i t e s i r t u p n ik l c _ f e rs t n i o p % 0 8 o t % 0 2 t a d e r u s a e md b ts n f te m i t l l a f t u p n ik l c _ f e rs t n i o p % 0 8 o t % 0 2 t a d e r u s a e md b ts n c d t t u p n i e l c y c y t u d e c n e r e f e r k l c _ f e rd b td b t% t able 4d. lvpecl dc c haracteristics , vdd=vdda=vddo=3.3v5%, t a =0 c to 70 c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u h i ve g a t l o v h g i h t u p n i , 1 l e s _ v i d , 0 l e s _ v i d , r m , l e s _ l l p , l e s m _ c e f , l e s n _ c e f n e _ t s e t , l e s _ t s e t v 5 6 4 . 3 = i d d v2 5 6 7 . 3v l i ve g a t l o v w o l t u p n i , 1 l e s _ v i d , 0 l e s _ v i d , r m , l e s _ l l p , l e s m _ c e f , l e s n _ c e f n e _ t s e t , l e s _ t s e t v 5 6 4 . 3 = i d d v3 . 0 -8 . 0v h i it n e r r u c h g i h t u p n i , 1 l e s _ v i d , 0 l e s _ v i d , l e s m _ c e f , l e s n _ c e f r m , n e _ t s e t , l e s _ t s e t = x d d v v 5 6 4 . 3 = n i v 0 5 1a l e s _ l l p = x d d v v 5 6 4 . 3 = n i v 5a l i it n e r r u c w o l t u p n i , 1 l e s _ v i d , 0 l e s _ v i d , l e s m _ c e f , l e s n _ c e f r m , n e _ t s e t , l e s _ t s e t , v 5 6 4 . 3 = x d d v v 0 = n i v 5 -a l e s _ l l p , v 5 6 4 . 3 = x d d v v 0 = n i v 0 5 1 -a h o ve g a t l o v h g i h t u p t u ot s e t , v 5 3 1 . 3 = x d d v a m 6 3 - = h o i 6 . 2v l o ve g a t l o v w o l t u p t u ot s e t , v 5 3 1 . 3 = x d d v a m 6 3 = l o i 5 . 0v l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u h o v ; e g a t l o v h g i h t u p t u o 2 , 1 e t o n , 0 t u o f n , 0 t u o f 1 t u o f n , 1 t u o f v 3 . 3 = x d d v1 . 2v l o v ; e g a t l o v w o l t u p t u o 2 , 1 e t o n , 0 t u o f n , 0 t u o f 1 t u o f n , 1 t u o f v 3 . 3 = x d d v6 . 1v g n i w s v k a e p - o t - k a e p g n i w s e g a t l o v t u p t u o , 0 t u o f n , 0 t u o f 1 t u o f n , 1 t u o f 0 5 h t i w d e t a n i m r e t s t u p t u o 1 t u o f n , 1 t u o f , 0 t u o f n , 0 t u o f : 1 e t o n ? . v 2 - o d d v o t . o d d v h t i w 1 : 1 y r a v l l i w s l e v e l t u p t u o . v 3 . 3 - o d d v r o f d e i f i c e p s e r a s l e v e l e s e h t : 2 e t o n 8733-01 www.icst.com/products/hipercocks.html july 17, 2001 7 ics8733-01 f orward e rror c orrection c lock g enerator advanced information t able 6. ac c haracteristics , vdd=vdda=vddo=3.3v5%, t a =0 c to 70 c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u t u o fy c n e u q e r f t u p t u o5 3 1 . 3 x d d v v 5 6 4 . 35 2 . 1 30 0 7z h m p p v k a e p - o t - k a e p e g a t l o v t u p n i , k l c _ f e r k l c _ f e r n 5 1 . 03 . 1v r m c v e d o m n o m m o c e g a t l o v t u p n i , k l c _ f e r k l c _ f e r n s l e v e l l c e p v l8 . 14 . 2v , s d v l , l t s h , m c d s l e v e l l t s s 1 3 . 03 . 1v ) o ( k s tw e k s t u p t u o 0 1s p ) c c ( t i j tr e t t i j e l c y c - o t - e l c y c k a e p 0 5s p c d te l c y c y t u d t u p t u o 7 43 5% r te m i t e s i r t u p t u o , 0 t u o f n , 0 t u o f 1 t u o f n , 1 t u o f % 0 8 o t % 0 20 0 30 0 8s p f te m i t l l a f t u p t u o , 0 t u o f n , 0 t u o f 1 t u o f n , 1 t u o f % 0 8 o t % 0 20 0 30 0 8s p k c o l te m i t k c o l l l p d b ts n 8733-01 www.icst.com/products/hipercocks.html july 17, 2001 8 ics8733-01 f orward e rror c orrection c lock g enerator advanced information p ackage o utline - y s uffix e e1 d1 d ccc c seating plane d2 -c- e2 e a n a1 a2 b c l 916 1 2 3 817 24 32 25 t able 7. p ackage d imensions n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s a b b m u m i n i ml a n i m o nm u m i x a m n 2 3 a 0 6 . 1 1 a 5 0 . 05 1 . 0 2 a 5 3 . 10 4 . 15 4 . 1 b 0 3 . 07 3 . 05 4 . 0 c 9 0 . 00 2 . 0 d c i s a b 0 0 . 9 1 d c i s a b 0 0 . 7 2 d 0 6 . 5 e c i s a b 0 0 . 9 1 e c i s a b 0 0 . 7 2 e 0 6 . 5 e c i s a b 0 8 . 0 l 5 4 . 00 6 . 05 7 . 0 0 7 c c c 0 1 . 0 reference document: jedec publication 95, ms-026 8733-01 www.icst.com/products/hipercocks.html july 17, 2001 9 ics8733-01 f orward e rror c orrection c lock g enerator advanced information while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without noti ce. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. t able 8. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pt n u o ce r u t a r e p m e t 1 0 - y 3 3 7 8 s c i1 0 - 3 3 7 8 s c ip f q l d a e l 2 3y a r t r e p 0 5 2c 0 7 o t c 0 1 0 - t y 3 3 7 8 s c i1 0 - 3 3 7 8 s c il e e r d n a e p a t n o p f q l d a e l 2 30 0 0 2c 0 7 o t c 0 |
Price & Availability of ICS8733Y-01
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