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MSM7630 ? semiconductor 1/89 general description the MSM7630 is a speech processor lsi device with internal d/a converter. it is optimized for speech output applications such as text-to-speech conversion. features ? parallel and serial interfaces ? single 3.3v power supply ? 5v interface available ? internal 16-bit x 16-bit to 32-bit multiplier (2-clock data throughput) ? 26 vax mips performance at 40 mhz operation (when using ordinary rom/sram) ? package: 100-pin plastic qfp (qfp100-p-1420-0.65-bk)(product name: MSM7630gs-bk) ? semiconductor MSM7630 universal speech processor preliminary e2f0005-18-31 this version: mar. 1998 previous version: jan. 1998
MSM7630 ? semiconductor 2/89 block diagram cpu dramc pio sio tmr tmr tmr tst pll mpy dac reg clk mclka tstm exint dao1 sg rst stby sclk txd rxd dsr dtr cts rts a23-0 d31-16 wr0,1 rd rom sram ras cas0,1 pd7-0 pstb pack pcs pioa pobf pibf we local bus
MSM7630 ? semiconductor 3/89 pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 gnd gnd rst rd stby wr1 wr0 as rom v dd sram d31 d30 d29 d28 d27 gnd d26 d25 d24 d23 d22 d21 v dd d20 d19 d18 d17 d16 pd7 pd6 gnd pd5 pd4 pd3 pd2 pd1 pd0 pioa v dd pcs pack pibf pstb pobf dsr rts gnd cts dtr a18 gnd a17 a16 a15 a14 a13 a12 v dd a11 a10 a9 a8 a7 a6 a5 gnd a4 a3 a2 a1 a0 cas1 cas0 v dd we sclk rxd ras txd dao1 test0 sg v dd v dd gnd gnd xo clk clka uport tstm2 tstm1 v dd extint a23 a22 a21 a20 a19 100-pin plastic qfp
MSM7630 ? semiconductor 4/89 pin descriptions description type i/o o o o o o o o o i 16-bit data bus. 8-bit devices are accessed through d31-24. 24-bit address bus. dram addresses are output from a13-0. rom select signal. rom indicates that rom space is assigned to the specified address. it is used as a chip select signal. sram select signal. sram indicates that sram space is assigned to the specified address. it is used as a chip select signal. read signal. rd is active during both 8-bit and 16-bit reads. write signals. wr0 corresponds to writes from d31-24, and wr1 corresponds to writes from d23-16. row address strobe. ras is active during both 8-bit and 16-bit reads. write enable. we is active during writes to dram space as the dram write signal. address strobe. serial data output. serial data input. symbol d31-16 a23-0 rom sram rd wr0,1 we as txd rxd o ras column address strobe. cas0 corresponds to accesses from d31-24, and cas1 corresponds to accesses from d23-16. o cas0,1 o i control signal indicating sio can transmit and receive. input signal indicating that modem is in operable state. dtr dsr o i sio transmit request signal. input signal indicating that modem can transmit. rts cts o i/o synchronous transfer clock output. parallel port data input/output. sclk pd7-0 i parallel port read signal. set high for centronics interface. pack i parallel port write signal. strobe signal for centronics interface. pstb i parallel port chip select signal. pcs i parallel port address signal. selects data or status during an access. pioa 3-state output port buffer full. indicates that data has been set in the output buffer. pobf 3-state input port buffer full. indicates that there is data in the input buffer. busy output signal for centronics interface. pibf o general flag output signal. uport i connects with sg. test0 o d/a converter output. dao1 i signal ground. connects with test0. sg i clock input signal. clk o clock signal. inverse of clk. xo o internal clock signal. clka i reset input. rst i standby signal. stby suspends operation and places the MSM7630 in a standby state. stby i external interrupt signal. extint i test mode select input signal. tstm2,1
MSM7630 ? semiconductor 5/89 absolute maximum ratings recommended operating conditions electrical characteristics dc characteristics parameter symbol condition power supply voltage v dd rating C0.3 to +4.5 unit v ta=25c (excluding test0) input voltage v in C0.3 to +5.5 v ta=25c storage temperature t stg C55 to +125 c parameter symbol conditon power supply voltage v dd range 3.0 to 3.6 unit v operating temperature t op C40 to +85 c parameter symbol condition "h" input voltage v ih unit v excluding clk 2.2 min. typ. max. (v dd =3.0 to 3.6v, ta=C40 to +85c) "l" input voltage v il excluding clk 0.8 v "h" input voltage v ih v clk 0.8 v dd "l" input voltage v il clk 0.2 v dd v "h" output voltage v oh v i oh =C4ma 2.4 "l" output voltage v ol i ol =4ma 0.4 v input leakage current i li 0 v in v dd 10 m a C10 output leakage current i lo 0 v out v dd 10 m a C10 dynamic supply current i do v dd =3.6, f ope =20mhz 120 ma d/a output relative accuracy v dae no load 10 mv 20 d/a output impedance r da 28 k w 12 static supply current i ds 1.5 ma
MSM7630 ? semiconductor 6/89 ac characteristics parameter symbol condition source oscillation frequency f osc 40 unit mhz 20 min. typ. max. source oscillation cycle t osc 25 ns 50 operating cycle t cyc 25 ns 50 clka delay time t clk 14 ns xo delay time t xo 7ns required rst time t w_rst t cyc 1024 a delay time t a 28 ns d setup time t s_d ns 14 d hold time t h_d ns 2 d delay time t d 32 ns time for d to go into hi-z t dz 24 ns rd delay time t rd 24 ns a to rd time t w_ard t cyc 1 as delay time t as 23 ns as pulse width t w_as read access t cyc 2 write access t cyc 3 a to as time t w_aas t cyc 1 rom delay time t rom 18+0.5t cyc ns sram delay time t sram 18+0.5t cyc ns ras delay time t ras 20 ns ras pulse width t w_ras t cyc 3 a to ras time t w_aras t cyc 1 cas delay time t cas 2n t access falling edge 20 ns 20+0.5t cyc ns cas pulse width t w_cas normal refresh t cyc 4 t cyc 1.5 a to cas time t w_acas ns 15 ras to cas time t w_rascas t cyc 1.5 we to cas time t w_wecas t cyc 1.5 we delay time t we 20 ns we pulse width t w_we t cyc 3 a to we time t w_awe t cyc 1 cas to ras time t w_casras t cyc 1 refresh rts delay time t rts 20 ns required rxd time t w_rxd s 1/bps rxd setup time t s_rxd s 0.5/bps rxd hold time t h_rxd s 0.5/bps cts setup time t s_cts ns 0 cts hold time t h_cts ns 0 rd pulse width t w_rd t cyc 2 normal (v dd =3.0 to 3.6v, ta=C40 to +85c)
MSM7630 ? semiconductor 7/89 parameter symbol condition unit min. typ. max. txd delay time t txd 19 ns txd pulse width t w_txd s 1/bps dtr delay time t dtr 20 ns sclk delay time t sclk 19 ns sclk pulse width t w_sclk s 1/bps pcs to pd delay time t pcs 19 ns pioa to pd delay time t pioa 19 ns pack to pd delay time t pack 18 ns time for pd to go into hi-z from pack t packz 16 ns pcs setup time for pstb t s_pcs ns 0 pcs hold time for clka (during writes) t h_pcs_w ns 0 pcs hold time for pack (during reads) t h_pcs_r ns 0 required pcs time t w_pcs t cyc 3 pioa setup time for pstb t s_pioa ns 0 pioa hold time for clka (during writes) t h_pioa_w ns 0 pioa hold time for pack (during reads) t h_pioa_r ns 0 required pioa time t w_pioa t cyc 3 pack setup time for clka t s_pack ns 0 pack hold time for clka t h_pack ns 0 required pack time t w_pack t cyc 3 pstb setup time for clka t s_pstb ns 0 pstb hold time for clka t h_pstb ns 0 required pstb time t w_pstb t cyc 3 pd setup time for pstb t s_pd ns 0 pd hold time for pstb t h_pd ns 0 uport delay time t uport 21 ns (v dd =3.0 to 3.6v, ta=C40 to +85c)
MSM7630 ? semiconductor 8/89 timing diagram clock and reset clk xo clka rst t osc t xo t clka t cyc t w_rst
MSM7630 ? semiconductor 9/89 rom read 3 t t t t t /4 t t t t t access clk clka a d rom rd t w_rom t w_rd t rd t rom t rd t rom t h_d t a t s_d t a t clka 5 t t t t t /6 t t t t t /8 t t t t t /10 t t t t t /12 t t t t t access clk clka a d rom rd t w_rom t w_rd t rd t rom t rd t rom t h_d t a t s_d t a t clka
MSM7630 ? semiconductor 10/89 sram read clk clka a d sram rd t w_sram t w_rd t rd t sram t rd t sram t h_d t a t s_d t a t clka 3 t t t t t /4 t t t t t access clk clka a d sram rd t w_sram t w_rd t rd t sram t rd t sram t h_d t a t s_d t a t clka 5 t t t t t /6 t t t t t /8 t t t t t /10 t t t t t /12 t t t t t access
MSM7630 ? semiconductor 11/89 sram write clk clka a d sram wr t w_sram t w_wr t wr t sram t wr t sram t d t a t d t a t clka 3 t t t t t access 4 t t t t t /5 t t t t t /6 t t t t t /8 t t t t t /10 t t t t t /12 t t t t t access clk clka a d sram wr t w_sram t w_wr t wr t sram t wr t sram t d t a t d t a t clka
MSM7630 ? semiconductor 12/89 dram read clk t h_d t s_d clka a d ras cas we t osc t a t cas t w_cas t w_acas t cas t w_rascas t ras t w_aras t w_ras row address column address 2n t t t t t access clk clka a d ras cas we t osc t cas t w_cas t cas t w_rascas t w_aras t w_ras row address column address t a column address t h_d t s_d t h_d t s_d t cas t ras t ras t w_acas 2n t t t t t access
MSM7630 ? semiconductor 13/89 3n t t t t t access clk clka a d ras cas we t osc t cas t w_cas t w_acas t cas t w_rascas t w_aras t w_ras column address t h_d t s_d row address t a t ras t ras clk clka a d ras cas we t osc t cas t w_cas t w_acas t cas t w_rascas t w_aras t w_ras column address row address t ras t h_d t s_d t h_d t s_d t a column address t ras t cas t w_cas t cas 3n t t t t t access
MSM7630 ? semiconductor 14/89 dram write clk clka a d ras cas we t osc t w_ras row address column address t a t d t d t ras t w_aras t cas t we t w_cas t w_acas t w_we t we t w_awe t w_rascas t w_wecas t cas 2n t t t t t access t osc row address clk clka a d ras cas we t a t d t d t d t ras t w_aras t w_ras t cas t we t w_cas t w_acas t cas t w_cas t w_acas t w_rascas t we t w_awe t w_we t cas t w_wecas column address column address 2n t t t t t access
MSM7630 ? semiconductor 15/89 ras cas we t osc row address column address t d t a t d t cas t we t ras t w_ras t ras t w_aras t w_awe t we t w_rascas t w_we t w_wecas t w_cas t cas t w_acas a d clk clka 3n t t t t t access 3n t t t t t access clk clka a d ras cas we t osc row address t a t ras t d t d t d t w_aras t ras t w_wecas t w_rascas t w_awe t we t w_acas t cas t w_cas t w_ras t cas t w_we column address column address t we
MSM7630 ? semiconductor 16/89 dram refresh clk clka a d ras cas we t osc t cas t ras t w_ras t ras t w_casrash t w_casras t cas t w_cas ignore ignore 2n t t t t t cas-before-ras refresh clk clka a d ras cas we t osc t ras t w_ras t w_cas ignore ignore t ras t w_casrash t cas t cas t w_casras 3n t t t t t cas-before-ras refresh
MSM7630 ? semiconductor 17/89 clk clka a d ras cas we t osc t cas t ras t w_ras t ras t w_casrash t w_casras t cas t w_cas ignore ignore cas-before-ras self-refresh
MSM7630 ? semiconductor 18/89 general device access clk clka a d as rd t h_d t s_d t a t clka t a t h_aas t as t rd t s_aas t as t rd t w_as t w_rd bus read bus write clk clka a d as wr t clka t a t d t as t wr t wr t as t w_as t w_wr t a t d
MSM7630 ? semiconductor 19/89 parallel interface clk clka t osc pcs pioa pack pstb pd pibf pobf t clka t w_pcs t w_pack t w_pcs t w_pack t w_pcs t w_pstb t w_pa t w_pa t pack t pcs t pioa t prdz t s_pwr t h_pwr t pcs t pcs t pack t pack t prdz t prdz
MSM7630 ? semiconductor 20/89 serial interface clk clka rxd rts t osc t clka t rts t h_rxd t s_rxd t w_rxd t w_rxd bit7 stop_bit (=1) t h_rxd t s_rxd bit6 bit1 bit0 start_bit (=0) t h_rxd t s_rxd t h_rxd t s_rxd t w_rxd t w_rxd t rts bit6 bit1 bit0 stop_bit (=1) bit7 start_bit (=0) t txd t txd t txd t txd t txd t txd t w_txd t w_txd t w_txd t w_txd t h_cts t s_cts t osc t clka clk clka txd cts
MSM7630 ? semiconductor 21/89 synchronous transfer output general port output clk clka uport t sclk t sclk t clka general port output clk t clka t sclk t sclk t sclk t w_sclk t w_sclk clka sclk
MSM7630 ? semiconductor 22/89 standby operation maintain the pin level on the stby signal until the cpu has completed its suspend process and clock signal clka has stopped. after the stby signal is released, the cpu will not resume until oscillation has stabilized (1024 t cyc ). * the rst signal is not necessary for self-refresh dram. clk xo t rststby_h operating suspend process suspend resume process operating clka rts * stby cpu operation ras cas t stbyclka t rststby_s t w_rst
MSM7630 ? semiconductor 23/89 interrupt process clk xo clka extint the external interrupt signal extint requests an interrupt to the cpu. the pin level on extint must be maintained until the cpu accepts the interrupt. also, be sure to clear the interrupt source within the interrupt routine.
MSM7630 ? semiconductor 24/89 functional description cpu core 1. features the scp (speech control processor) uses a cpu core with an oki-original 32-bit risc architecture. 2. register configuration the cpu core registers are configured as 32 words for general registers, 7 words for privileged registers, and 1 word for a special register. %r0 (link) %r1 (pre-pc) %r2 (pre-npc) %r3 (long-immed.) %r4 %r5 %r30 %r31 general registers %psr %vba %prpsr %irr privileged registers %bpa %pc %npc %nop special register 2.1 general registers the general registers are a set of 32 registers with 32-bit width. of these registers %r0 to %r3 can be used as general registers, but they do have special functions pre-assigned by the system. registers %r4 to %r31 can be used freely. contents are undefined after reset. gr bit 31 0
MSM7630 ? semiconductor 25/89 %r0: link register (stores subroutine return address). also stores %pc+4 during bl instruction execution. %r1: stores value of %pc when an exception, interrupt, or trap is accepted. %r2: stores value of %npc when an exception, interrupt, or trap is accepted. %r3: stores the immediate value of setli (set long immediate) instructions. 2.2 privileged registers reads are allowed at any processor level (processor level: 0 = user mode, 1 or above = supervisor mode), but write accesses are allowed only when the processor level is supervisor mode. the privileged registers are configured as 7 words, and are used primarily for processor control. if the processor attempts a write access to a privileged register while in user mode, then the instruction will not be executed and a privileged instruction exception will be issued. 2.2.1 psr (processor status register) this register sets and displays the state of the processor. 31 28 27 26 25 24 0000 23 22 21 20 0 m f u 32 m f u 16 0 19 18 17 16 0000 15 14 13 12 vcnz 11 10 9 8 0 i c p i c l n o p 7 6 5 4 00 e b p e m 3 0 pl bit ver ? bit[31:28] ver: version (read-only) indicates the cpu core version. currently fixed to "3". ? bit[22] mfu32 (read-only) indicates whether the 32-bit multiplier unit is present ("1") or not ("0"). this is "0" for the MSM7630. ? bit[21] mfu16 (read-only) indicates whether the 16-bit multiplier unit is present ("1") or not ("0"). this is "1" for the MSM7630. ? bit[15] v: overflow (read-only) indicates that execution of an addition or subtraction instruction resulted in an arithmetic overflow. ? bit[14] c: carry (read-only) indicates that execution of an addition or subtraction instruction resulted in an arithmetic carry or borrow. ? bit[13] n: negative (read-only) indicates that execution of an addition or subtraction instruction resulted in a negative value (bit[31] is "1").
MSM7630 ? semiconductor 26/89 ? bit[12] z: zero (read-only) indicates that execution of an addition or subtraction instruction resulted in a zero value (bit[31:0] are all "0"). ? bit[10] icp: instruction cache purge (read/write) invalidates all instruction cache entries. writing "1" to this bit purges the contents of the instruction cache. after this process (after one cycle) this bit is automatically cleared to "0" by hardware. the instruction cache is purged during reset. ? bit[9] icl: instruction cache lock (read/write) freezes all instruction cache entries. after "1" is written to this bit, instruction cache contents are frozen and then instruction execution continues. this bit will be "1" after reset. ? bit[8] nop: non-operation (read-only) when set to "1", forces the next instruction to a nop regardless of the instruction. there is no way to directly set this bit to "1". this bit will be "0" after reset. ? bit [5] ebp: breakpoint trap enable (read/write) enables breaks. if this bit is set to "1", then a trap will occur when the value of the instruction execution address (%pc) equals the value of the breakpoint address (%bpa). the instruction that generated the break will not be executed. this bit will be "0" after reset. ? bit[4] em: master enable (read/write) disables all exceptions, interrupts, and traps. this bit automatically becomes "0" at the point when the processor accepts an exception, interrupt, or trap. while this bit is "0", further exceptions, interrupts or traps will not be accepted, with instruction execution continuing in the normal instruction sequence. an instruction must be used to return this bit to "1". it will be "0" after reset. ? bit[3:0] pl: processor level (read/write) sets and provides the processors instruction execution level. processor levels are 0-15. an external interrupt will be accepted if its level has a higher priority than the processor level at that time. external interrupt levels are 1-16, so when pl is 0 all external interrupts will be accepted, and when pl is 1 external interrupts of level 2 and above will be accepted. when an external interrupt is accepted, the processor level will become the same as the external interrupt level. for example, if pl is 5 and a level 7 external interrupt is accepted, then pl will transition to 7 at that point. when pl is restored to its previous state, its saved value in %prpsr will be restored to %psr. alternatively pl can be set to its previous value explicitly by an instruction in the interrupt process routine. however, %psr is a privileged register, so writes are only permitted in supervisor mode. pl will be set to 15 after reset.
MSM7630 ? semiconductor 27/89 2.2.2 vba: vector base address (read/write) this read/write register sets the leading address of the dispatch table (vector table) to exception, interrupt, and trap process routines. 31 12 11 00 0 bit 000000 0000 vba the dispatch table is 256 entries of 4k bytes size, with 16 bytes (4 instructions) save for each entrys dispatch routine. entry points are generated by an or operation with this register, so they are set at 4k-byte boundaries. as a result, only the upper 20 bits of an argument will be written to the vba register (the lower 12 bits will be ignored). entry_point = vba[31:12] (vector_number << 4) this register is undefined after reset. 2.2.3 prpsr: pre-processor status register (read/write) this read/write register saves the value of %psr at the time an exception, interrupt, or trap is accepted. in order to accept overlapping exceptions, interrupts, and traps, the value of %prpsr must be pushed on a stack and then em of %psr must be set to "1". 31 28 27 26 25 24 0000 23 22 21 20 0 m f u 32 m f u 16 0 19 18 17 16 0000 15 14 13 12 p v p c p n p z 11 10 9 8 0 p i c p p i c l p n o p 7 6 5 4 00 p e b p p e m 3 0 ppl bit ver the upper 16 bits of %prpsr are always identical to %psr. refer to the descriptions of the same bit positions in %psr for an explanation of %prpsr bits. 2.2.4 irr: interrupt request register (read-only) this register indicates whether there is an interrupt request at each of the 16 levels of external interrupts. it is read-only, and shows interrupt requests regardless of pl (processor level). the irr value will continue until an interrupt source is released. 31 12 11 i r q 8 i r q 7 0 bit i r q 6 i r q 5 i r q 4 i r q 3 i r q 2 i r q 1 i r q 12 i r q 11 i r q 10 i r q 9 n m i i r q 15 i r q 14 i r q 13 0000 0000 0000 0000 1 2 3 4 5 6 7 8 9 10 13 14 15 16
MSM7630 ? semiconductor 28/89 the MSM7630 uses only 6 interrupts of the 16 interrupt levels. 31 12 11 0 i r q 7 0 bit 0 i r q 5 0 i r q 3 00 0 i r q 11 0 i r q 9 0000 0000 0000 0000 0000 1 2 3 4 5 6 7 8 9 10 13 14 15 16 2.2.5 bpa: breakpoint address (read/write) this read/write register sets and shows the instruction address (byte address) where a breakpoint trap occurred. the lowest 2 bits will always be "0". when ebp of %psr is "1", a trap will be generated immediately before execution of the instruction at the breakpoint set by this register. this register will be undefined after reset. 31 0 bit 00 bpa 1 2 2.2.6 pc: program counter (read-only) this read-only register provides the instruction address (byte address) in the execution phase. its lowest 2 bits will always be "0". 31 0 bit 00 pc 1 2 2.2.7 npc: next program counter (read-only) this read-only register provides the instruction address (byte address) in the instruction decode phase. its lowest 2 bits will always be "0". 31 0 bit 00 npc 1 2
MSM7630 ? semiconductor 29/89 2.3 special registers these are not privileged registers, but they are special registers used for specific functions. 2.3.1 nop: non-operation (read/write) when this register is specified as a destination register, execution results will not be stored anywhere. when specified as a source register, it will read as an undefined value. 31 0 bit nop 3. data formats there are two data format types: one for internal processor core calculations and one for memory accesses. 3.1 internal data format the cpu core handles all data as 32 bits (word format). therefore, when the format of data stored in memory is byte (8 bits) or half-word (16 bits) it must be used internally as 32-bit data through a signed load instruction or unsigned load instruction. similarly when internal core processing results are stored to memory, a store instruction corresponding to the data format in memory must be executed. also, bit addresses specified for bit test instructions and bit manipulation instructions are shown in the diagram below. 31 0 bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
MSM7630 ? semiconductor 30/89 3.2 memory data format the following memory data formats are supported: byte (8 bits), half-word (16 bits), and word (32 bits). memory addresses are always byte addresses regardless of data format. however, half-word accesses must be on 16-bit boundaries (least significant bit is "0"), and word accesses must be on 32- bit boundaries (least significant 2 bits are "00"). if a load or store instruction execution attempts a memory access that violates these boundaries, then a data address invalid exception will occur. memory addressing is big-endian. the diagrams below show memory data formats for byte data access, half-word data access, and word data access. 31 24 byte 23 16 15 8 7 0 bit byte byte byte n n+1 n+2 n+3 address byte data access 31 half word 16 15 0 bit n address half-word data access n+1 half word 31 0 bit n address word data access word
MSM7630 ? semiconductor 31/89 3.3 memory addressing modes memory addresses are byte addresses, so memory addressing is performed with three types of load instructions and two types of store instructions. swap instructions have the same memory addressing as store instructions. 3.3.1 load instruction addressing 1. base + index the effective address (ea) is obtained by adding the values of any two general registers %r0-31 specified. ea = [reg_s1 + reg_s2] 2. base + displacement the effective address (ea) is obtained by adding the value of any general register %r0-31 specified and a displacement given by the instructions immediate value field. ea = [reg_s1] + offs 3.3.2 store instruction addressing 1. base + displacement the effective address (ea) is obtained by adding the value of any general register %r0-31 specified and a displacement given by the instructions immediate value field. ea = [reg_s1] + offs
MSM7630 ? semiconductor 32/89 4. instruction set all instructions are fixed 32-bit length. category instruction jlr {,x} s2,d* function conditional branch to subroutine conditional branch to subroutine jlrt {,x/t} s1,s2,d* jlrf {,x/t} s1,s2,d* conditional branch to subroutine return from subroutine rt s2 bit test btst1 s1,s2/immu,d bit test bit test btst0 s1,s2/immu,d comparison [=] comparison cmpeq s1,s2/imms,d comparison [signed: ] cmple s1,s2/imms,d comparison [signed: <] cmplt s1,s2/imms,d comparison [unsigned: ] cmpls s1,s2/imms,d comparison [unsigned: <] cmpc s1,s2/imms,d comparison [ 1 ] cmpne s1,s2/imms,d comparison [signed: >] cmpgt s1,s2/imms,d comparison [signed: 3 ] cmpge s1,s2/imms,d comparison [unsigned: >] cmphi s1,s2/imms,d comparison [unsigned: 3 ] cmpnc s1,s2/imms,d transfer to trap toutine trap trap vct add arithmetic/logical operation add s1,s2/imms9,d subtract sub s1,s2/imms9,d add with carry adc s1,s2/imms9,d subtract with carry sbc s1,s2/imms9,d logical and and s1,s2/imms9,d or s1,s2/imms9,d logical or msb extend extend ext s1,s2/immu,d msb extend shift sl s1,s2/imms,d logical shift rot s1,s2/imms,d logical rotate slr s1,s2/imms,d logical shift sar s1,s2/imms,d arithmetic shift bit manipulation brst s1,s2/immu,d set bit to "0" bset s1,s2/immu,d set bit to "1" bnot s1,s2/immu,d invert bit brst %psr,4/5,%psr set bit to "0" unconditional branch b{,x}? unconditional branch unconditional branch to subroutine bl{,x}? conditional branch bt{,x/t} s1,? conditional branch conditional branch bf{,x/t} s1,? xor s1,s2/imms9,d exclusive or sbr s1,s2/imms12,d subtract extu s1,s2/immu,d brst %psr,4/5,%psr set bit to "1"
MSM7630 ? semiconductor 33/89 multiply instructions need two clocks for execution time. the MSM7630 can only use the mul0 and mulu0 instructions of the multiplication instructions. category instruction setli const25 function store immediate value left-shifted 7 bits to %r3 swap swap swap s2,[s1+offs] byte load lb [s1+offs],d' half-word load lhw [s1+offs],d' word load lw [s1+offs],d' signed multiply multiplication mul0 s1,s2/imms,d' signed multiply mul16 s1,s2/imms,d' signed multiply mul32 s1,s2/imms,d' unsigned multiply mulu0 s1,s2/imms,d' unsigned multiply mulu16 s1,s2/imms,d' mulu32 s1,s2/imms,d' unsigned multiply register-register move mov s,d move move upper bits movh s1,d' store immediate value seti imm17s,d store immediate value store immediate value to upper 16 bits setih const16,d' store sb s2/imms,[s1+offs] byte store half-word store shw s2/imms,[s1+offs] word store sw s2/imms,[s1+offs] load
MSM7630 ? semiconductor 34/89 5. exceptions, traps, and interrupts the cpu core of scp provides error exceptions, traps, external interrupts, and software traps (by trap instructions). each type has a corresponding interrupt priority level and instruction dispatch address. the system reset vector is at absolute address 0. all others are ored with vba as the base address. synchronous detection is acceptance of a request within an instruction cycle. asynchronous detection is acceptance of a request between instruction cycles or at any point in time after. source vector number branch address priority synchronous/asynchronous (sense) system reset 0x00000000 0 1 cpu reset (init) 0 2 instruction access exception 1 3 instruction address invalid exception 2 4 reserved instruction exception 3 5 privileged instruction exception 4 8 data address invalid exception 5 9 data access exception 6 6 reserved 7 reserved 9 to 32 25 external interrupt 1 33 asynchronous (level) vba+0x000 asynchronous (edge) synchronous synchronous synchronous synchronous asynchronous (edge) asynchronous (edge) synchronous asynchronous (level) synchronous vba+0x010 vba+0x020 vba+0x030 vba+0x040 vba+0x050 vba+0x060 vba+0x070 vba+0x080 vba+0x090 to vba+0x200 vba+0x210 breakpoint trap 8 24 external interrupt 2 34 vba+0x220 23 external interrupt 3 35 vba+0x230 22 external interrupt 4 36 vba+0x240 21 external interrupt 5 37 vba+0x250 20 external interrupt 6 38 vba+0x260 19 external interrupt 7 39 vba+0x270 18 external interrupt 8 40 vba+0x280 17 external interrupt 9 41 vba+0x290 16 external interrupt 10 42 vba+0x2a0 15 external interrupt 11 43 vba+0x2b0 14 external interrupt 12 44 vba+0x2c0 13 external interrupt 13 45 vba+0x2d0 12 external interrupt 14 46 vba+0x2e0 11 external interrupt 15 47 vba+0x2f0 10 external interrupt 16 (nmi) 48 vba+0x300 7 trap instruction 0 to 255 vba+0x000 to vba+0xff0 asynchronous (level) asynchronous (level) asynchronous (level) asynchronous (level) asynchronous (level) asynchronous (level) asynchronous (level) asynchronous (level) asynchronous (level) asynchronous (level) asynchronous (level) asynchronous (level) asynchronous (level) asynchronous (level) asynchronous (edge)
MSM7630 ? semiconductor 35/89 5.1 rst: system reset a system reset resets all states under all circumstances. type: asynchronous hardware reset after rst pin level detection. vector address: absolute address 0 (0x00000000). conditions: non-maskable (unconditional) pl after interrupt transition: 15 5.2 iae: instruction access exception an instruction access exception is generated when an instruction is fetched from an undefined memory space. if the instruction is converted to a nop by delayed instruction control (x-bit manipulation), then no exception will be generated. type: instruction-synchronous exception caused by memory access error during instruction fetch. vector number/address: vector number = 1 / vba+0x010 conditions: non-maskable (unconditional). invalidated by delayed instruction control (x-bit). saved address: address of the instruction that caused the exception. pl after interrupt transition: 15 5.3 iaie: instruction address invalid exception an instruction address invalid exception is generated when a register indirect branch instruction attempts an instruction fetch at an address that is not on a word boundary. if the instruction is converted to a nop by delayed instruction control (x-bit manipulation), then no exception will be generated. type: instruction-synchronous exception caused by an illegal jlr or rt instruction. vector number/address: vector number = 2 / vba+0x020 conditions: non-maskable (unconditional). invalidated by delayed instruction control (x-bit). saved address: address of the instruction that caused the exception. pl after interrupt transition: 15
MSM7630 ? semiconductor 36/89 5.4 pie: privileged instruction exception a privileged instruction exception is generated when an action that can only be performed in supervisor mode attempted in user mode: (a) in user mode a privileged register is specified as a destination, or (b) in user mode a number 64 or below is specified for a trap instruction vector. if the instruction is converted to a nop by delayed instruction control (x-bit manipulation), then no exception will be generated. type: instruction-synchronous exception caused by an illegal privileged instruction. vector number/address: vector number = 4 / vba+0x040 conditions: non-maskable (unconditional). invalidated by delayed instruction control (x-bit). saved address: address of the instruction that caused the exception. pl after interrupt transition: 15 5.5 daie: data address invalid exception a data address invalid exception is generated when a memory access instruction attempts to access a memory address not on a word boundary. type: asynchronous exception caused by an illegal memory access instruction. vector number/address: vector number = 5 / vba+0x050 conditions: em == 1. however, exception must be maintained until accepted. saved address: address being executed when the exception was accepted. pl after interrupt transition: 15 5.6 dae: data access exception a data access exception is generated when data is accessed in an undefined memory space. type: asynchronous exception caused by a memory access instruction error. vector number/address: vector number = 6 / vba+0x060 conditions: em == 1. however, exception must be maintained until accepted. saved address: address being executed when the exception was accepted. pl after interrupt transition: 15
MSM7630 ? semiconductor 37/89 5.7 bpt: breakpoint trap a breakpoint trap is generated when the instruction execution address matches the address pointed to by the %bpa register. however, the ebp bit in the %psr register must be enabled. the instruction at the address that causes the trap will not be executed. the trap will be generated even if the instruction is converted to a nop by delayed instruction control (x-bit manipulation). type: instruction-synchronous trap caused by hardware. vector number/address: vector number = 8 / vba+0x080 conditions: em == 1 && ebp == 1. not invalidated by delayed instruction control (x-bit). saved address: address pointed to by the %bpa register. pl after interrupt transition: 15 5.8 eint: external interrupt 1-15 external interrupts are generated by inputs. however, an external interrupt will be accepted only when its level has higher priority than the current processor level. when an external interrupt is accepted, the processor level becomes the same as its level. type: asynchronous interrupt when level on int1-int15 pins is detected. vector number/address: vector number = 33-47 / vba + 0x210-0x2f0 conditions: em == 1 && pl < external_interrupt_number saved address: address being executed when the interrupt was accepted. pl after interrupt transition: external interrupt number the MSM7630 assigns interrupt levels as follows. it does not use other interrupts (including nmi). interrupt source priority interrupt number user block/tmr2 1 int11 external pin (extint) 2 int9 serial i/o 3 int7 parallel i/o 4 int5 tmr1 5 int3
MSM7630 ? semiconductor 38/89 5.9 return from interrupt in order to return from an interrupt process caused by an exception, external interrupt, or software trap, the pipeline at the time of the interrupt must be regenerated before execution. there are two types of returns: (1) re-execution of an instruction that was in its execution phase at the time an exception, external interrupt, or asynchronous trap caused an interrupt, and (2) re- execution of the instruction after the instruction that was in its execution phase at the time a software trap caused an interrupt. however, if breakpoints are supported by software traps then case (1) applies. the return sequence from an interface process is described below. also, an rt instruction must not be executed while the em bit of %psr is 1 (the state permitting overlapping interrupts). if an interrupt occurred during the rt instruction in such a case, then the contents of %psr would be corrupted. 1. resume from interrupted instruction brst %psr, 4, %psr ; em-bit reset jlr %r1, %nop ; delay slot, branch %r1 (old %pc), ; return address not saved rt %r2 ; return to %r2 (old %npc), %prpsr move to %psr 2. return from instruction after interrupt add %r2, 4, %r1 ; %r2+4 (old %npc+4) ? %r1 brst %psr, 4, %psr ; em-bit reset jlr %r2, %nop ; delay slot, branch %r2 (old %npc), return address not saved rt %r1 ; return to %r1 (old %npc+4), %prpsr move to %psr in this case the pnop bit of %prpsr must be cleared in advance of rt instruction execution. if the pnop bit of %prpsr is set and then the rt instruction is executed, then the instruction at the return point would not be executed.
MSM7630 ? semiconductor 39/89 bus interface unit 1. features the scps bus interface unit (biu) manages address space and outputs control signals that enable optimal memory access. this allows rom, sram, dram and other general devices to be accessed. 2. address space the address space that can be directly accessed by load/store instructions is 4 gigabytes. the biu manages this address space by dividing it into several. rom sram dram reserved general devices reserved internal rom internal ram registers 0x00000000 0x0fffffff 0x10000000 0x1fffffff 0x20000000 0x2fffffff 0x30000000 0x3fffffff 0x40000000 0x7fffffff 0x80000000 0xbfffffff 0xc0000000 0xcfffffff 0xd0000000 0xdfffffff 0xe0000000 0xffffffff external internal 4gb 512mb 256mb 256mb 1gb 256mb 256mb 256mb
MSM7630 ? semiconductor 40/89 2.1 rom space rom space is assigned to 0x00000000-0x0fffffff. when this space is accessed the rom signal goes "l". 2.2 sram space sram space is assigned to 0x10000000-0x1fffffff. when this space is accessed the sram signal goes "l". 2.3 dram space dram space is assigned to 0x20000000-0x2fffffff. when this space is accessed the dram controller outputs a signal required for dram access. 2.4 general device space general device space is assigned to 0x40000000-0x7fffffff. when this space is accessed the as signal goes "l". this space is used to access general devices external to the MSM7630. 2.5 internal rom space internal rom space is assigned to 0xc0000000-0xcfffffff. it is used to access internal rom. this space is not used by the MSM7630. accesses to this space will cause instruction access exceptions or data access exceptions. 2.6 internal ram space internal ram space is assigned to 0xd0000000-0xdfffffff. it is used to access internal ram. this space is not used by the MSM7630. access to this will cause instruction access exceptions or data access exceptions. 2.7 register space register space is assigned to 0xe0000000-0xffffffff. within this space, 0xf8000000-0xffffffff is assigned for standard i/o and system registers.
MSM7630 ? semiconductor 41/89 tmr sio pio 0xff000040 0xff00005f 0xff000080 test circuit 0xff0000ff system registers bsr bea ecr scr dramc 0xff000000 0xff000004 0xff000008 0xff00000c 0xff000010 0xff000014 0xff000018 0xff00001c 0xff000020 0xff00003f 0xf8000000 0xf8ffffff 0xf9000000 0xf9ffffff 0xfa000000 0xfaffffff 0xfb000000 0xfbffffff 0xfc000000 0xfcffffff 0xfd000000 0xfdffffff 0xfe000000 0xfeffffff 0xff000000 0xffffffff
MSM7630 ? semiconductor 42/89 3. registers this is a register group used for bus control. 3.1 bea: bus error address this register provides the address at the time a bus error occurred. 31 0 bit bea 3.2 bsr: bus status register this register provides bus status information. 31 19 18 17 16 xsp 15 14 12 0st 11 8 peb 7 6 4 0 bes 30 0 bit 1 2 c s p 0r h ? bit[18:17] xsp: sleep (read/write) when the stby signal is "l", these bits either stop the clock without cpu intervention (xsp=00) or stop the clock after waiting for the cpu suspend process (xsp=11). ? bit[16] csp: cpu sleep (read/write) this bit indicates whether the cpu core is operating or suspended. writing "1" will stop the cpu cores clock. ? bit[14:12] st: status (read-only) these bits save the status signals when an access by the cpu core causes a bus error. ? bit[11:8] peb: parity error byte (read-only) these bits provide the byte position when a parity error occurs. ? bit[6:4] bes: bus error status (read-only) these bits provide the source of a bus error. bes = 000 no error bes = 001 biu register privilege violation bes = 010 parity error bes = 100 invalid space access these bits will be "000" after reset.
MSM7630 ? semiconductor 43/89 ? bit[1] h: hold (read/write) this bit sets whether or not bus rights will be passed upon a cpu core bus rights request. this bit will be "0" after reset. 3.3 ecr: extra configuration register this register sets bus operation. 31 11 87 6 4 p m bm 30 bit 1 2 a 10 9 0 a x o x a v o v d v ? bit[10] ox: internal rom (read-only) this bit indicates whether or not internal rom will be accessed in 2 clocks. MSM7630 does not use this bit. ? bit[9] ax: internal ram (read-only) this bit indicates whether or not internal ram will be accessed in 2 clocks. MSM7630 does not use this bit. ? bit[7] pm: parity mode (read/write) this bit sets parity. pm = 0 even parity pm = 1 odd parity this bit will be "0" after reset. MSM7630 does not use parity checking, so it ignores this field. ? bit[3] a: all internal rom (read/write) this bit sets whether or not internal rom will be accessed instead of external rom. MSM7630 has no internal rom, so this bit is always "0". ? bit[2] ov: internal rom valid (read-only) this bit shows whether internal rom is enabled or disabled. this bit is "0" for MSM7630. ? bit[1] av: internal ram valid (read-only) this bit shows whether internal ram is enabled or disabled. this bit is "0" for MSM7630.
MSM7630 ? semiconductor 44/89 3.4 scr: space configuration register this register sets rom space, sram space, and general device space. 31 18 17 16 as 15 14 12 10 8 os 76 4 d s 30 bit 1 2 wt sz 20 21 23 24 25 26 13 9 5 x s d p c orw o d o c 0 aww arw a c a d ? bit[25] ac: sram parity check (read/write) this bit sets parity checking of sram space. it will be "0" after reset. ac = 0 ignore parity checks. ac = 1 generate a bus error if a parity error is detected. ? bit[24] ad: sram dummy cycle (read/write) this bit sets whether or not sram space may be accessed continuously after rom space or dram space has been read. ad = 0 continuous access allowed. ad = 1 open an interval of at least one clock. this bit will be "1" after reset. ? bit[23:21] arw: sram read wait (read/write) these bits set the wait count when sram space is accessed by a read. arw = 000 2 t access (1 wait) arw = 001 3 t access (2 waits) arw = 010 4 t access (3 waits) arw = 011 5 t access (4 waits) arw = 100 6 t access (5 waits) arw = 101 8 t access (7 waits) arw = 110 10 t access (9 waits) arw = 111 12 t access (11 waits) these bits will be "111" after reset.
MSM7630 ? semiconductor 45/89 ? bit[20:18] aww: sram write wait (read/write) these bits set the wait count when sram space is accessed by a write. aww = 000 2 t access (1 wait) aww = 001 3 t access (2 waits) aww = 010 4 t access (3 waits) aww = 011 5 t access (4 waits) aww = 100 6 t access (5 waits) aww = 101 8 t access (7 waits) aww = 110 10 t access (9 waits) aww = 111 12 t access (11 waits) these bits will be "111" after reset. ? bit[17:16] as: sram device size (read/write) these bits set the device size of sram space. as = 00 no sram (space is invalid) as = 01 8-bit wide device as = 10 16-bit wide device as = 11 32-bit wide device these bits will be "00" after reset. when this field is "00", attempting to access sram space will cause an instruction access exception or data access exception. ? bit[14] oc: rom parity check (read/write) this bit sets parity checking for rom space. it will be "0" after reset. oc = 0 ignore parity errors. oc = 1 generate a bus error if a parity error is detected. this bit will be "0" for the MSM7630. ? bit[13] od: rom dummy cycle (read/write) this bit sets whether or not a rom space access will immediately follow an sram space or dram space read. od = 0 consecutive access enabled. od = 1 force an interval of at least one clock. this bit will be "1" after reset.
MSM7630 ? semiconductor 46/89 ? bit[12:10] orw: rom read wait (read/write) these bits set the wait count when rom space is accessed by a read. orw = 000 2 t access (1 wait) orw = 001 3 t access (2 waits) orw = 010 4 t access (3 waits) orw = 011 5 t access (4 waits) orw = 100 6 t access (5 waits) orw = 101 8 t access (7 waits) orw = 110 10 t access (9 waits) orw = 111 12 t access (11 waits) these bits will be "111" after reset. ? bit[9:8] os: rom device size (read/write) these bits set the device size of rom space. os = 00 no rom (space is invalid) os = 01 8-bit wide device os = 10 16-bit wide device os = 11 32-bit wide device when this field is "00", attempting to access rom space will cause an instruction access exception or data access exception. ? bit[7] ds: other data setup (read/write) this bit sets whether or not the data setup time to the write strobe signal wr is guaranteed during writes to general device space. ds = 0 not guaranteed. ds = 1 guaranteed. this bit will be "1" after reset. ? bit[6] pc: other parity check (read/ write) this bit sets parity checking for general device space. it will be "0" after reset. pc = 0 ignore parity errors. pc = 1 generate a bus error if a parity error is detected. this bit will be "0" for the MSM7630.
MSM7630 ? semiconductor 47/89 ? bit[5] sd: other dummy cycle (read/write) this bit sets whether or not a general device space access will immediately follow an sram space or dram space read. sd = 0 consecutive access enabled. sd = 1 force an interval of at least one clock. this bit will be "1" after reset. ? bit[4] x: external bus clock unit (read/write) this bit sets the operating clock unit for general device space. x = 0 use 1 clock as the unit. x = 1 use 2 clocks as the unit. this bit will be "0" after reset. ? bit[3:2] wt: other wait (read/write) these bits set the wait count when general device space is accessed. wt = 00 4 t access wt = 01 5 t access wt = 10 6 t access wt = 11 7 t access these bits will be "11" after reset. ? bit[1:0] sz: other device size (read/write) these bits set the device size of general device space. sz = 00 no general device (space is invalid) sz = 01 8-bit wide device sz = 10 16-bit wide device sz = 11 32-bit wide device these bits will be "11" after reset. when this field is "00", attempting to access general device space will cause an instruction access exception or data access exception.
MSM7630 ? semiconductor 48/89 3.5 dram: dram configuration register this register sets dram space. 31 28 27 26 25 24 tp 23 22 21 20 18 17 16 ra cs 15 13 12 11 10 9 sz r f m e m 0 rfc bit 0 29 0 0 dt d p md ca after this register has been written, dram must not be accessed until the dram is operating properly. refer to the data sheet of the dram used to obtain the required conditions for proper dram operation. ? bit[28:27] dt: device type (read/write) these bits set the dram device type. dt = 00 high-speed page mode dt = 01 hyper-page mode (edo dram) these bits will be "00" after reset. ? bit[26] pr: parity check (read/write) this bit sets parity checking for dram space. it will be "0" after reset. pr = 0 ignore parity errors. pr = 1 generate a bus error if a parity error is detected. this bit will be "0" for the MSM7630. ? bit[25:24] tp: type (read/write) this bit sets the drams ras signal and byte position control signal. tp = 00 1 ras mode, byte position cas control tp = 01 2 ras mode, byte position cas control tp = 10 1 ras mode, byte position we control tp = 11 2 ras mode, byte position we control these bits will be "00" after reset. ? bit[23] dp: data priority (read/write) this bit sets the priority of processing when data access is requested by a load/store instruction during a one-line instruction cache read from dram due to an instruction cache miss. dp = 0 give priority to the instruction cache read from dram. dp = 1 give priority to the data access. this bit will be "0" after reset.
MSM7630 ? semiconductor 49/89 ? bit[22:21] md: mode (read/write) these bits set the number of clocks for a dram access. md = 01 2n clock access md = 10 3n clock access these bits will be "10" after reset. ? bit[20:18] ra: row address (read/write) these bits set the most significant bit position of the row address. ra = 000 a17 ra = 001 a18 ra = 010 a19 ra = 011 a20 ra = 100 a21 ra = 101 a22 ra = 110 a23 these bits will be "000" after reset. ? bit[17:16] rs: row shift (read/write) these bits set how many bits to shift the row address to output it as a dram address. rs = 00 8-bit shift rs = 01 9-bit shift rs = 10 10-bit shift rs = 11 11-bit shift these bits will be "00" after reset. ? bit[15:13] ca: column address (read/write) these bits set the most significant bit position of the column address. ca = 000 a08 ca = 001 a09 ca = 010 a10 ca = 011 a11 ca = 100 a12 these bits will be "000" after reset.
MSM7630 ? semiconductor 50/89 ? bit[12:11] sz: device size (read/write) these bits set the device size of dram space. sz = 00 no dram (space is invalid) sz = 01 8-bit wide device sz = 10 16-bit wide device sz = 11 32-bit wide device these bits will be "00" after reset. when this field is "00", attempting to access dram space will cause an instruction access exception or data access exception. ? bit[10] rfm: refresh mode (read/write) this bit sets the refresh operation mode. rfm = 0 cas-before-ras refresh rfm = 1 cas-before-ras self-refresh this bit will be "0" after reset. ? bit[9:0] rfc: refresh counter (read/write) these bits set the initial value of the refresh counter. it should be set as an integer value obtained by: [(refresh period) ? (clock period) ? 16]C1 these bits will be "0000000000" after reset.
MSM7630 ? semiconductor 51/89 4. rom access the MSM7630 interface with rom is shown below. the rom signal will become "0" when the address signal and specified rom space match. refer to the timing diagram for basic timing of rom accesses. 5. sram access the MSM7630 interface with sram is shown below. the sram signal will become "0" when the address signal and specified sram space match. refer to the timing diagram for basic timing of sram accesses. MSM7630 axx rom rd axx cs oe rom dxx data external bus MSM7630 axx we rd axx we oe sram dxx sram cs data external bus
MSM7630 ? semiconductor 52/89 6. dram access there are two MSM7630 interfaces with dram: one when byte position is specified by cas , and one when byte position is specified by we . this is set by the dram registers tp field. an interface example when byte position is specified by cas is shown below. an interface example when byte position is specified by we is shown below. refer to the timing chart for basic timing of dram accesses. MSM7630 axx cas [0 : 1] we axx cas we dram dxx ras ras data external bus MSM7630 axx we cas [0 : 1] axx cas we dram dxx ras ras data external bus
MSM7630 ? semiconductor 53/89 the table below shows how address signals are connected for different dram configurations. configuration row column address lines ca rs ra 17-09 08-00 a[08:00] 000 01 000 18-10 09-01 a[09:01] 001 01 001 18-09 08-01 a[09:01] 000 00 001 19-11 10-02 a[10:02] 010 01 010 19-10 09-02 a[11:02] 001 00 010 18-09 08-00 a[09:00] 000 01 001 19-10 09-01 a[10:01] 001 01 010 20-11 10-02 a[11:02] 010 01 011 19-10 09-00 a[09:00] 001 10 010 20-11 10-01 a[10:01] 010 10 011 20-10 09-01 a[11:01] 001 01 011 20-09 08-01 a[12:01] 000 00 011 21-12 11-02 a[11:02] 011 10 100 21-11 10-02 a[12:02] 010 01 100 21-10 09-02 a[13:02] 001 00 100 20-10 09-00 a[10:00] 001 10 011 20-09 08-00 a[11:00] 000 01 011 21-11 10-01 a[11:01] 010 10 100 21-10 09-01 a[12:01] 001 01 100 22-12 11-02 a[12:02] 011 10 101 22-11 10-02 a[13:02] 010 01 101 21-11 10-00 a[10:00] 010 11 100 21-10 09-00 a[11:00] 001 10 100 22-12 11-01 a[11:01] 011 11 101 22-11 10-01 a[12:01] 010 10 101 23-13 12-02 a[12:02] 100 11 110 23-12 11-02 a[13:02] 011 10 110 256k 8 256k 16 256k 32 512k 8 512k 16 512k 32 1m 8 1m 16 1m 32 2m 8 2m 16 2m 32 4m 8 4m 16 4m 32
MSM7630 ? semiconductor 54/89 serial interface 1. features the serial interface (sio) performs both clock synchronized and start-stop transfers. 2. sio functions 2.1 port configuration ? independent transmit and receive circuits ? double buffer configuration for receive buffer because the transmit and receive circuits are independent, start-stop transfers are all full-duplex communication. 2.2 transfer methods ? start-stop transfer data length: 7 bits or 8 bits selectable transfer sequence: lsb first stop bits: 1 bit or 2 bits selectable parity bit: no parity, even parity, or odd parity selectable flag bit: enables inter-processor communication using the serial port. however, cannot be used together with parity bit. ? clock synchronized transfer data length: 8 bits fixed transfer sequence: lsb first
MSM7630 ? semiconductor 55/89 the chart below shows the data format with start-stop transfers. 1 0 bit0 bit1 bit2 bit3 bit4 bit5 bit6 1 1 0 bit0 bit1 bit2 bit3 bit4 bit5 bit6 1 1 1 0 bit0 bit1 bit2 bit3 bit4 bit5 bit6 flag 1 1 0 bit0 bit1 bit2 bit3 bit4 bit5 bit6 parity 1 1 0 bit0 bit1 bit2 bit3 bit4 bit5 bit6 flag 1 1 1 0 bit0 bit1 bit2 bit3 bit4 bit5 bit6 parity 1 1 1 0 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 1 1 0 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 1 1 1 0 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 1 flag 1 0 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 1 parity 1 0 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 1 flag 1 0 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 1 parity 7n1 7n2 7f1 7p1 7f2 7p2 8n1(*) 8n2 8f1 8p1 8f2 8p2 1 1 stop bits flag/parity 1 : 1 stop bit, 2 : 2 stop bits n : non, f : flag, p : parity data size 7 : 7 bits, 8 : 8 bits ( * ) after reset the format will be 8 bits , no p arit y, 1 sto p bit.
MSM7630 ? semiconductor 56/89 2.3 baud rate ? internal baud rate generator ? clock synchronized transfers b = f/(8 n (256Cp)) where b : baud rate (bps) f : processor (scp) clock frequency (hz) n : baud rate parameter one of 1, 2, 4, 8, 16, 32, and 64. selected by sbrs sbrp field. (refer to the register description.) p : baud rate adjustment value (0 p 255) set by sbrs sbrv field. (refer to the register description.) at a processor (scp) clock of 20 mhz, the maximum transfer rate is 2.5 mbps. at 40 mhz, the maximum transfer rate is 5 mbps. ? start-stop transfers b = f/(16 n (256Csbr)) where b : baud rate (bps) f : processor (scp) clock frequency (hz) n : baud rate parameter one of 1, 2, 4, 8, 16, 32, and 64. selected by sbrs sbrp field. (refer to the register description.) sbr : baud rate adjustment value (0 sbr 255) set by sbrs sbrv field. (refer to the register description.) 2.4 error detection ? parity errors (start-stop transfers) a parity error will be detected when a parity bit generated from received data does not match the received parity bit. ? framing errors (start-stop transfers) a framing error will be detected when a received stop bit is "0". when 2 stop bits have been selected, only the first bit received will be checked. ? overrun errors (start-stop and clock synchronized transfers) an overrun error will be detected when the next receive frame's stop bit is detected before the receive buffer has been read.
MSM7630 ? semiconductor 57/89 2.5 interrupts the sio is the source of the following interrupts. ? interrupts - receive error interrupt a receive error interrupt will be generated whenever a parity error, framing error, or overrun error is detected. - receive buffer full interrupt a receive buffer full interrupt will be generated whenever the valid receive data has been transferred to the receive buffer. - transmit buffer empty interrupt a transmit buffer empty interrupt will be generated whenever the transmit buffer becomes empty. - transmit end interrupt a transmit end interrupt will be generated whenever an sio data transfer ends. - modem status interrupt a modem status interrupt will be generated whenever a change in a modem control input signal (cts, dsr) is detected. ? interrupt enable/disable each interrupt source can be independently enabled or disabled. also, all interrupts can be disabled at once. ? interrupt requests whenever any of the five interrupts above is enabled and its conditions are fulfilled, the cpu will get an sio interrupt request.
MSM7630 ? semiconductor 58/89 3. sio registers these registers control sio. 3.1 sib: sio input buffer this register holds data that has been input externally. it is undefined after reset. 7 bit sib 0 3.2 sob: sio output buffer this register holds data to be output externally. it is undefined after reset. 7 bit sob 0 3.3 ssts: sio status register this register provides sio status. 15 11 s p t e s m s i 0 bit s o s t s i s t s e r i s r x i s t x i s t e i s o v e s f r e 0 0000 1 2 3 4 5 6 7 8 9 10 0 ? bit[10] sove 0 : no overrun error 1 : overrun error generated this bit can only be written with "0". it will be "0" after reset. ? bit[9] sfre 0 : no framing error 1 : framing error generated this bit can only be written with "0". it will be "0" after reset.
MSM7630 ? semiconductor 59/89 ? bit[8] spte 0 : no parity error 1 : parity error generated this bit can only be written with "0". it will be "0" after reset. ? bit[6] smsi 0 : no modem status interrupt 1 : modem status interrupt requested this bit is read-only. it will be "0" after reset. ? bit[5] sost 0 : transmit buffer full 1 : transmit buffer empty this bit can only be written with "0". it will be "1" after reset. ? bit[4] sist 0 : receive buffer empty 1 : receive buffer full this bit can only be written with "0". it will be "0" after reset. ? bit[3] seri 0 : no receive error interrupt 1 : receive error interrupt requested this bit is read-only. it will be "0" after reset. ? bit[2] srxi 0 : no receive buffer full interrupt 1 : receive buffer full interrupt requested this bit is read-only. it will be "0" after reset. ? bit[1] stxi 0 : no transmit buffer empty interrupt 1 : transmit buffer empty interrupt requested this bit is read-only. it will be "0" after reset.
MSM7630 ? semiconductor 60/89 ? bit[0] stei 0 : no transmit end interrupt 1 : transmit end interrupt requested this bit can only be written with "0". it will be "0" after reset. 3.4 scmd: sio command register 15 11 s t e i e s m o d 0 bit s f b m s f b s f l s p t y s s t p s r x i e s t x i e 0 1 2 3 4 5 6 7 8 9 10 0 12 13 14 s r e n s t e n s e r i e s i e n ? bit[15] sren 0 : data receive disabled 1 : data receive enabled this bit will be "0" after reset. ? bit[14] sten 0 : data transmit disabled 1 : data transmit enabled this bit will be "0" after reset. ? bit[12] sien 0 : interrupts disabled 1 : interrupts enabled this bit will be "0" after reset. ? bit[11] serie 0 : receive error interrupts disabled 1 : receive error interrupts enabled this bit will be "0" after reset. ? bit[10] srxie 0 : receive buffer full interrupts disabled 1 : receive buffer full interrupts enabled this bit will be "0" after reset.
MSM7630 ? semiconductor 61/89 ? bit[9] stxie 0 : transmit buffer empty interrupts disabled 1 : transmit buffer empty interrupts enabled this bit will be "0" after reset. ? bit[8] steie 0 : transmit end interrupts disabled 1 : transmit end interrupts enabled this bit will be "0" after reset. ? bit[6] smod 0 : start-stop transfer mode 1 : clock synchronized transfer mode this bit will be "0" after reset. ? bit[5] sfbm 0 : clear flag bit mode 1 : set flag bit mode this bit will be "0" after reset. ? bit[4] sfb 0 : flag bit value set to "0" 1 : flag bit value set to "1" this bit will be "0" after reset. ? bit[3] sfl 0 : transfer data length is 8 bits 1 : transfer data length is 7 bits this bit will be "0" after reset. ? bit[2:1] spty 00 : no parity 10 : even parity 11 : odd parity these bits will be "00" after reset.
MSM7630 ? semiconductor 62/89 ? bit[0] sstp 0 : 1 stop bit 1 : 2 stop bits this bit will be "0" after reset. 3.5 sbr: baud rate adjustment register this register sets values that adjust the baud rate. 15 11 0 bit 0 7 8 10 0 000 sbrp sbrv ? bit[10:8] sbrp 000 : baud rate parameter n = 1 001 : baud rate parameter n = 2 010 : baud rate parameter n = 4 011 : baud rate parameter n = 8 100 : baud rate parameter n = 16 101 : baud rate parameter n = 32 110 : baud rate parameter n = 64 these bits will be undefined after reset. ? bit[7:0] sbrv these bits are the baud rate adjustment value. they will be undefined after reset. 3.6 msts: modem status register this register provides the states of modem signals. 15 11 0 bit c t s 0 1 2 3 4 9 10 0 12 d c t s 0 00 d d s r 0 0 000 d s r 00 ? bit[11] dcts 0 : cts signal has not changed 1 : cts signal has changed this bit is read-only. it will be "0" after reset.
MSM7630 ? semiconductor 63/89 ? bit[10] ddsr 0 : dsr signal has not changed 1 : dsr signal has changed this bit is read-only. it will be "0" after reset. ? bit[3] cts 0 : cts input signal value = "0" 1 : cts input signal value = "1" this bit is read-only. it will be the cts pin input value after reset. ? bit[2] dsr 0 : dsr input signal value = "0" 1 : dsr input signal value = "1" this bit is read-only. it will be the dsr pin input value after reset. 3.7 mcmd: modem command register this register enables/disables modem status interrupts and auto-enable mode, and controls rts and dtr output signals. 15 0 bit c t s 0 1 2 9 10 0 d c t s 0 00 d d s r 000 d s r 87 00 00 ? bit[9] smsie 0 : disables modem status interrupts 1 : enables modem status interrupts this bit will be "0" after reset. ? bit[8] saen 0 : disables auto-enable mode 1 : enables auto-enable mode this bit will be "0" after reset. ? bit[1] rts 0 : output rts signal "0" 1 : output rts signal "1" this bit will be "0" after reset.
MSM7630 ? semiconductor 64/89 ? bit[0] dtr 0 : output dtr signal "0" 1 : output dtr signal "1" this bit will be "0" after reset. 3.8 scnt: sio control register this register controls sio. 15 0 bit 0 0 0 0 0 000 c s t p 00 00 00 0 ? bit[0] cstp 0 : enable sio clock supply 1 : disable sio clock supply this bit will be "0" after reset.
MSM7630 ? semiconductor 65/89 5. sio operation there are two methods of sio operation: start-stop transfers where communication is performed synchronized to characters, and clock synchronized transfers where communication is performed synchronized to the clock. 5.1 clock synchronized transfers clock synchronized transfer mode is selected by setting the scmd (command register) smod bit to "1". in this mode 8-bit data will be input/output synchronized to the clock output from the sclk pin. with clock synchronized transfers, transfer data is only 8 bits, so parity bits and flag bits cannot be added. the scmd (command register) sfbm bit, sfl bit, and spty bits will be set to "0", "0", and "00" respectively. 5.1.1 clock synchronized transfer baud rate b = f 8 n (256Cp) where b : baud rate f : scp clock frequency n : baud rate parameter (set by sbr registers sbrp bit) p : baud rate adjustment value (set by sbr registers sbrv bit) set sbr (baud rate adjustment register) to achieve the required baud rate. 4. sio register addresses sio register addresses for the MSM7630 are shown below. 0xfa000000 sio input buffer 0xfa000004 sio output buffer 0xfa000008 baud rate adjustment register 0xfa00000c sio status register 0xfa000010 sio command register 0xfa000014 modem status register 0xfa000018 modem command register 0xfa00001c sio control register
MSM7630 ? semiconductor 66/89 5.1.2 clock synchronized transmit operation 1) verify that the ssts (status register) sost bit is "1", and then write the data to be transferred to the transmit buffer sob. 2) write "0" to sost to indicate that sob has valid data. 3) if using sio interrupts, set the scmd (command register) sien bit to "1". if using the transmit buffer empty interrupt, write "1" to the scmd stxie bit. if using the transmit end interrupt, write "1" to the scmd steie bit. 4) if the mcmd (modem command register) saen bit is "0", then setting the scmd (command register) sten bit to "1" will start the transfer. if the mcmd saen bit is "1", then the transfer will start when the scmd sten bit is "1" and the cts input is "1". 5) sob (transmit buffer) data will be transferred lsb first from the txd output. also, a synchronous clock will be transmitted from the sclk pin. data on the txd output will change synchronous to the falling edge of sclk. the receiving device should sample txd data on the rising edge of sclk. 6) when the next data can be written to the transmit buffer, the ssts (status register) sost bit will change from "0" to "1". if the scmd (command register) stxie and sien bits are "1" at this time, then the ssts stxi bit will become "1" and an interrupt request to the cpu will be generated. 7) for continuous transfers, after the ssts (status register) sost bit becomes "1" write new data to sob (transmit buffer) and write "0" to the sost bit. 8) if there is no more data to be transmitted, then write "0" to the scmd (command register) stxie bit. this will disable interrupt requests from sio. 9) when transfer of the eighth bit of data ends, the ssts (status register) sost bit will become "1" (transmit buffer sob is empty), sclk will stop, and the transmit operation will end. if the scmds steie and sien bits are "1" at this time, then the sstss stei bit will become "1" and an interrupt request to the cpu will be generated. this interrupt can be released by writing "0" to the sstss stei bit or the scmds steie bit.
MSM7630 ? semiconductor 67/89 5.1.3 clock synchronized receive operation 1) the receive operation will begin if the mcmds saen bit is "0" (auto-enable mode disabled) and the scmds sren bit is "1" (data receive enabled). 2) when the receive operation begins, a synchronous clock will be output from sclk. 3) if using sio interrupts, set scmds sien bit to "1". if using the receive buffer full interrupt, set scmds srxie bit to "1". 4) the transmitting device should input the data to be transferred on rxd on the falling edge of sclk, lsb first. the sio will sample rxd data on sclks rising edge, shifting it into the receive shift register. 5) when the eighth bit of data has been received, the receive shift registers data is transferred to sib. however, it will not be transferred to sib if an overrun error occurs. 6) after data has transferred from the receive shift register to the receive buffer sib, sist will change from "0" to "1", indicating that there is valid data in the receive buffer sib. if scmds srxi bit and sien bit are both "1" at this time, an interrupt request to the cpu will be generated. 7) to continue receiving data, read the sib data after sis becomes "1", and then write "0" to sist. 8) to end the receive operation, write "0" to scmds sren bit. at the time "0" is written to sren, data currently being received will be transferred to sib and the receive operation will end. 9) when sstss sist bit is "1" and the sio enters the state in which data is ready to be transferred from the receive shift register to the receive buffer, the sio will assume that an overrun error (receipt of further data before the value of the receive buffer sib is read) has occurred. sstss sove bit will then be set to "1". in this case the receive shift register value will not be transferred to the receive buffer sib. if scmds serie bit and sien bit are "1", then ssts's seri bit will be set to "1" and an interrupt request to the cpu will be generated. to release the interrupt, write "0" to sstss sove bit or to scmds serie or sien bit. 5.2 start-stop transfers start-stop transfer mode is selected by setting the scmd (command register) smod bit to "0". in this mode data is output lsb first from txd, and input lsb first from rxd. 5.2.1 start-stop transfer baud rate b = f 16 n (256Cp) where b : baud rate f : scp clock frequency n : baud rate parameter (set by sbr registers sbrp bit) p : baud rate adjustment value (set by sbr registers sbrv bit) set sbr (baud rate adjustment register) to achieve the required baud rate.
MSM7630 ? semiconductor 68/89 5.2.2 start-stop transmit operation 1) verify that the ssts (status register) sost bit is "1", and then write the data to be transferred to the transmit buffer sob. next write "0" to sost to indicate that sob has valid data. 2) if the mcmd (modem command register) saen bit is "0", then setting the scmd (command register) sten bit to "1" will start the transfer. if the mcmd saen bit is "1", then the transfer will start when the scmd sten bit is "1" and the cts input is "1". 3) for start-stop transmit operation, a start bit "0" will be output from txd. then the data written in sob will be output lsb first. if scmds sfl bit is "0", then 8 bits of data will be output. if the sfl bit is "1", then 7 bits will be output. 4) when scmd (command register) sfbm bit is "0", a parity bit will be output after the sob data. the parity will be even if the spty field is "10", and odd if the spty field is "11". if scmds sfbm bit is "1" and spty is "00", then the value set in scmds sfb bit will be output after the sob data. if scmds sfbm bit is "0" and the spty field is "0", then neither a parity bit nor flag bit will be output after sob data. 5) finally, one stop bit will be output if the scmd (command register) sstp bit is "0", or two stop bits will be output if the sstp bit is "1". this will end the transfer of one frame of data. 6) when the next data can be written to the transmit buffer, the ssts (status register) sost bit will change from "0" to "1". if the scmd (command register) stxie and sien bits are "1" at this time, then the ssts stxi bit will become "1" and an interrupt request to the cpu will be generated. 7) for continuous transfers, after the ssts (status register) sost bit becomes "1" write new data to sob (transmit buffer) and write "0" to the sost bit. this will disable interrupt requests from sio. 8) if there is no more data to be transmitted, then write "0" to the scmd (command register) stxie bit. the will disable interrupt requests from sio. 9) when transfer of the stop bit ends, the transmit operation will end if the sost bit is "1". if the scmd's steie and sien bits are "1" at this time, then the ssts's stei bit will become "1" and an interrupt request to the cpu will be generated. this interrupt can be released by writing "0" to the ssts's stei bit or the scmd's steie or sint bit.
MSM7630 ? semiconductor 69/89 5.2.3 start-stop receive operation 1) the receive operation can begin if the mcmds saen bit is "0" and the scmds sren bit is "1". 2) if using sio interrupts, set scmds sien bit to "1". if using the receive buffer full interrupt, set scmds srxie bit to "1". if using the receive error interrupt, set scmds serie bit to "1". 3) the sio receive operation will start when a falling edge is detected on rxd. the first bit of data is received as the start bit. if the received value is "1", then it will not be recognized as a start bit, the receive operation will be suspended, and the device will wait for another rxd falling edge to be detected. if the received value is "0", then data will continue to be received. 4) when the start bit is received, receive of data will start. if scmds sfl bit is "0", then 8 bits of data will be input serially into the receive shift register. if the sfl bit is "1", then 7 bits of data will be input. 5) when scmd (command register) sfbm bit is "0", a parity bit will be received after the data. the parity will be even if the spty field is "10", and odd if the spty field is "11". if scmds sfbm bit is "1" and spty is "00", one flag bit will be received. if scmds sfbm bit is "0" and the spty field is "00", then neither a parity bit nor flag bit will be received. 6) finally one stop bit will be received. even if scmds sstp bit is "1", only the first stop bit will be received. 7) when all bits have been received, the data input in the receive shift register will be transferred to the receive buffer sib. however, if either of the following two conditions applies, then data will not be transferred to sib, and sib will retain its previous value. 1. scmds sfbm bit is "1", its spty field is "00", and the received flag bit does not match scmds sfb bit. 2. an overrun error occurred. 8) when data has been transferred from the receive shift register to the receive buffer sib, sstss sist will change from "0" to "1". if scmds srxie and sien bits are both "1", then sstss srxi bit will become "1" and an interrupt request to the cpu will be generated. to release the interrupt, write "0" to sstss sist bit or to scmds srxie or sien bit. 9) when sstss sist bit is "1" and the sio enters the state in which data is ready to be transferred from the receive shift register to the receive buffer, the sio will assume that an overrun error (receipt of further data before the value of the receive buffer is read) has occurred. sstss sove bit will then be set to "1". 10) if the received stop bit is "0", then it will be considered indication of a framing error. sstss sfre bit will then be set to "1". 11) when scmds spty field is "10" or "11", a mismatch between parity generated from the receive data and the parity bit will be considered a parity error. sstss spte bit will then be set to "1". 12) if one or more of the sove, sfre, and spte bits are "1" and the scmd' s serie and sien bits are "1", then ssts's seri bit will be set to "1" and an interrupt request to the cpu will be generated. 13) to release the interrupt for any error, write "0" to all of sstss sove, sfre, and spte bits, or write "0" to scmds serie or sien bits.
MSM7630 ? semiconductor 70/89 parallel interface 1. features the parallel interface (pio) inputs and outputs 8-bit wide parallel data. it has three data transfer methods: software control mode where input/output is specified with 1-bit ports, handshake control mode through strobe/acknowledge signals and flags indicating buffer status, and bus control mode through read/write signals. 2. pio functions 2.1 pio data size ? 8 bits 2.2 pio control modes ? software control mode in software control mode, the pio controls input and output of bits in accordance with the value written in the direction register. if a direction register bit is "0", then the corresponding pin level will be an input. if "1", then the value in the corresponding output buffer will be output to the pin. ? handshake control mode in handshake control mode, the pio inputs external data through a handshake using a strobe signal ( pstb ) and input buffer full signal (pibf). it outputs data externally through a handshake using an output buffer full signal (pobf) and acknowledge signal ( pack ). ? bus control mode in bus control mode, the pio controls data input/output with a chip select signal ( pcs ), flag/buffer select signal (pioa), read signal ( pack ), and write signal ( pstb ). 2.3 pio interrupts interrupts to the cpu core are available when handshake control mode or bus control mode is selected. ? input buffer full interrupts when pcmds pien bit is "1", writing "0" to the piie bit will disable input buffer full interrupts, and writing "1" will enable them. when the pien bit is "0", input buffer full interrupts will be disabled regardless of the value of the piie bit. if input buffer full interrupts are enabled, then one will be generated whenever the input buffer is written from an external device. to release input buffer full interrupts, write "0" to the status register pstss pist bit, to the command register pcmds piie bit, or to pcmds pien bit.
MSM7630 ? semiconductor 71/89 ? output buffer empty interrupts when pcmds poen bit is "1", writing "0" to the poie bit will disable output buffer empty interrupts, and writing "1" will enable them. when the poen bit is "0", output buffer empty interrupts will be disabled regardless of the value of the poie bit. if output buffer empty interrupts are enabled, then one will be generated whenever the output buffer is read by an external device. to release output buffer empty interrupts, write "0" to the status register pstss post bit, to the command register pcmds poie bit, or to pcmds poen bit. 3. pio registers these registers control the pio. 3.1 pib: pio input buffer this buffer saves data input from an external device. it will be undefined after reset. 3.2 pob: pio output buffer this buffer saves data to be output to an external device. it will be undefined after reset. 3.3 pdir: pio direction register this register specifies under software control whether each parallel port bit is input or output. it will be "00000000" after reset. 7 bit pib 0 7 bit pob 0 7 bit pdir 0
MSM7630 ? semiconductor 72/89 3.4 psts: pio status register this register provides the pio status. ? bit[5] pinti 0 : no input buffer full interrupt 1 : input buffer full interrupt occurred this bit will be "0" after reset. ? bit[4] pinto 0 : no output buffer empty interrupts 1 : output buffer empty interrupt occurred this bit will be "0" after reset. ? bit[3] pack 0 : no acknowledge 1 : acknowledge this bit will be undefined after reset. ? bit[2] post 0 : output buffer full 1 : output buffer empty this bit can only be written with "0". it will be "1" after reset. ? bit[1] pstb 0 : no strobe 1 : strobe this bit will be undefined after reset. ? bit[0] pist 0 : input buffer empty 1 : input buffer full this bit can only be written with "0". it will be "0" after reset. 0 p i n t i p i n t o p a c k p o s t p s t b p i s t 1 2 3 4 5 6 7 bit 00
MSM7630 ? semiconductor 73/89 3.5 pcmd: pio command register this register specifies the parallel port mode and specifies whether interrupts are enabled or disabled. it will be "00000000" after reset. ? bit[7:6] pmod 00 : bus control mode 01 : handshake control mode 1x : software control mode ? bit[5] poen 0 : output operation disabled 1 : output operation enabled ? bit[4] pien 0 : input operation disabled 1 : input operation enabled ? bit[1] poie 0 : output buffer empty interrupts disabled 1 : output buffer empty interrupts enabled ? bit[0] piie 0 : input buffer full interrupts disabled 1 : input buffer full interrupts enabled 4. pio register addresses for the MSM7630, pio register addresses are listed below. 0xfb000000 pio input buffer 0xfb000004 pio output buffer 0xfb000008 pio direction register 0xfb00000c pio status register 0xfb000010 pio command register 0 00 p o i e p i i e 1 2 3 4 5 6 7 bit p m o d p i e n p o e n
MSM7630 ? semiconductor 74/89 5. pio operation 5.1 software control mode in software control mode data input/output and control signals are all controlled by software. 5.1.1 data input from external device 1) write "1x" to the pcmd (command register) pmod bits ("x" indicates that either "0" or "1" is acceptable). 2) read the input buffer pib to read the parallel ports pin levels at that time. 5.1.2 data output to external device 1) write "1x" to the pcmd (command register) pmod bits ("x" indicates that either "0" or "1" is acceptable). 2) write a value to the output buffer pob. 3) write "1" to the bits in pdir (direction register) that correspond to parallel port pins that will be outputs. this starts to drive the parallel port for data to be output. 4) if "0" is written to any bits in pdir, then the corresponding parallel port pins will stop being driven. 5.2 handshake control mode in handshake control mode data input is controlled by handshake using a strobe ( pstb ), input buffer full (pibf), acknowledge ( pack ), and output buffer full (pobf) for input/output. 5.2.1 data input from external device (a) scp operation 1) write "01" to the pcmd (command register) pmod bits. also write "1" to pcmds pien bit to enable input operation. 2) when data is written to the input buffer pib from the external device, the psts (status register) pist bit will become "1" to indicate that there is valid data in pib. when pstss pist bit becomes "1", the input buffer full output (pibf) will become "1". 3) if pstss pist bit is "1" and input buffer full interrupts have been enabled (pcmds piie bit is "1"), then a pio interrupt to the cpu core will be generated. 4) the cpu core verifies that pstss pist bit is "1" in the pio interrupt vector process routine and reads the input buffer pib. it then writes "0" to pstss pist bit to release the interrupt. 5) when pstss pist bit becomes "0", the input buffer full output (pibf) also becomes "0". 6) repeat the operation from step 2).
MSM7630 ? semiconductor 75/89 (b) external operation 1) verify that the input buffer full output (pibf) is "0". 2) drive the parallel input/output bus (pd[7:0]) with input data. 3) set the strobe input ( pstb ) to "1". this writes the data to the input buffer pib. 4) when the input buffer full output (pibf) becomes "1", stop driving the parallel input/output bus and set the strobe input ( pstb ) to "0". 5) repeat the operation from step 1). 5.2.2 data output to external device (a) scp operation 1) write "01" to the pcmd (command register) pmod bits. also write "1" to pcmds poen bit to enable output operation. 2) verify that the psts (status register) post bit is "1", indicating that the output buffer pob is empty. 3) write data to the output buffer pob. 4) write "0" to pstss post bit. when post becomes "0", the output buffer full output (pobf) will become "1". 5) if pstss post bit is "1" and output buffer full interrupts have been enabled (pcmds poie bit is "1"), then a pio interrupt to the cpu core will be generated. this interrupt will be released by writing "0" to pstss post bit or writing "0" to pcmds poie bit. 6) write data to the output buffer pob and repeat the operation from step 4).
MSM7630 ? semiconductor 76/89 (b) external operation 1) verify that the output buffer full output (pobf) is "1". 2) set the acknowledge input ( pack ) to "1". when the acknowledge input is set to "1", the pio will output the value of the output buffer (pob) to the parallel input/output bus (pd[7:0]). 3) verify that the output buffer full output (pobf) is "0". 4) read the value on the input/output bus. 5) set the acknowledge input ( pack ) to "0". when the acknowledge input becomes "0", the pio will stop driving the input/output bus. 6) repeat the operation from step 1). 5.3 bus control mode in bus control mode data input/output is controlled externally by the chip select input ( pcs ), flag/ buffer select input (pioa), read input ( pack ), and write input ( pstb ). (a) scp operation 1) write "00" to the pcmd (command register) pmod bits. also write "1" to pcmds pien bit to enable input operation. 2) when an external device writes data to the input buffer pib, the psts (status register) pist bit will become "1", indicating that there is valid data in the input buffer pib. 3) if pcmds piie bit is "1", then a pio interrupt to the cpu core will be generated. 4) the cpu core verifies that pstss pist bit is "1" in the pio interrupt vector process routine and reads the input buffer pib. it then writes "0" to pstss pist bit to release the interrupt. 5) repeat the operation from step 2). (b) external operation 1) read the input buffer full output (pibf). chip select input pcs 0 flag/buffer select input pioa 0 read input pack 0 write input pstb 1 2) verify that the input buffer full output (pibf) is "0".
MSM7630 ? semiconductor 77/89 3) write data to the input buffer (pib). chip select input pcs 0 flag/buffer select input pioa 1 read input pack 1 write input pstb 0 input/output bus pd[7:0] write data 4) repeat the operation from step 1). 5.3.2 data output to external device (a) scp operation 1) write "00" to the pcmd (command register) pmod bits. also write "1" to pcmds poen bit to enable output operation. 2) verify that the psts (status register) post bit is "1", indicating that the output buffer pob is empty. 3) write data to the output buffer pob. 4) write "0" to pstss post bit. when post is "0", the output buffer full output (pobf) will become "1". 5) when post becomes "1" and pcmds poie bit is "1", then a pio interrupt to the cpu core will be generated. this interrupt will be released by writing "0" to pstss post bit or by writing "0" to pcmds poie bit. 6) repeat the operation from step 3). (b) external operation 1) read the output buffer full output (pobf). chip select input pcs 0 flag/buffer select input pioa 0 read input pack 0 write input pstb 1 2) verify that the output buffer full output (pobf) is "1". 3) read the output buffer (pob). chip select input pcs 0 flag/buffer select input pioa 1 read input pack 0 write input pstb 1 input/output bus pd[7:0] read data 4) when the output buffer is read, psts's post bit will become "1". 5) repeat the operation from step 1).
MSM7630 ? semiconductor 78/89 timer unit 1. features the timer unit (tmr) is a 16-bit programmable timer. it has two modes: an interval timer mode which requests interrupts to the cpu core, and a clock division mode which generates a 50% duty, frequency divided clock. 2. tmr functions 2.1 counter ? 16-bit up counter 2.2 counter clock period ? f (scp operating frequency 1) ? 4 f (scp operating frequency 4) ? 16 f (scp operating frequency 16) ? 64 f (scp operating frequency 64) 2.3 interval timer interrupts when the counter overflows (counter value changes from 0xffff to 0x0000), it will request an interrupt to the cpu core. 2.4 divided clock generation when the counter overflows (counter value changes from 0xffff to 0x0000), it will invert the value currently being output. 3. tmr registers 3.1 tir: timer initial value register this register saves the counters initial value. when this register is written, the same value will be written to the timer value register (tcr). this register will be undefined after reset. 3.2 tcr: timer value register this register provides the counters current value. it will be undefined after reset. tir 0 15 bit tcr 0 15 bit
MSM7630 ? semiconductor 79/89 3.3 tsts: timer status register this register provides tmr status. ? bit[1] tdat 0 : no timer interrupt request occurred (interval timer mode) divided clock output is "0" (divided clock mode) 1 : timer interrupt request occurred (interval timer mode) divided clock output is "1" (divided clock mode) ? bit[0] tca 0 : timer counter operation is suspended 1 : timer counter is operating 3.4 tcmr: command register this register sets tmr operation. ? bit[7] tcg 0 : disable timer counter operation 1 : enable timer counter operation this bit will be "0" after reset. ? bit[5] tmod 0 : interval timer mode 1 : divided clock mode this bit will be "0" after reset. 0 t c s 1 2 3 4 5 6 7 bit 0 t c g t m o d t c a i 00 0 t d a t t c a 1 7 bit 000000
MSM7630 ? semiconductor 80/89 ? bit[4] tcai 0 : disable auto-initialization of timer value register 1 : enable auto-initialization of timer value register this bit will be "0" after reset. ? bit[1:0] tcs 00 : count clock f 01 : count clock 4 f 10 : count clock 16 f 11 : count clock 64 f these bits will be 00 after reset. 4. tmr register addresses the MSM7630 has two timers. the register addresses for each are listed below. 5. tmr operation 5.1 interval timer mode in interval timer mode counting begins from the value set in the timer initial value register, and a timer interrupt is generated to the cpu when the counter overflows. 1) set the tcmr (command register) tcg bit to "0", disabling counting. 2) set tcmrs tcs bits to select the counters increment clock. 3) set tcmrs tmod bit to "0", setting interval timer mode as the operating mode. 4) to generate periodic interrupts set tcmrs tcai bit to "1", which will set the counter to be loaded with the value of the timer initial value register each time the counter overflows. for a one-shot interrupt set the tcai bit to "0". 5) set the timers initial value in the timer initial value register tir. writing to this register will simultaneously write the same value to the timer value register tcr. 6) write "1" to tcmrs tcg bit to start counting. an interrupt will be generated when the counter overflows. 7) to release the interrupt set the tsts (status register) tdat bit to "0" in software. tmr1 tmr2 0xf8000000 0xf8000010 0xf8000004 0xf8000014 0xf8000008 0xf8000018 0xf800000c 0xf800001c timer initial value register timer initial value register timer value register timer value register timer status register timer status register timer command register timer command register
MSM7630 ? semiconductor 81/89 5.2 divided clock mode in divided clock mode counting begins from the value set in the timer initial value register, and the divided clock output value inverts when the counter overflows. 1) set the tcmr (command register) tcg bit to "0", disabling counting. 2) set tcmrs tcs bits to select the counters increment clock. 3) set tcmrs tmod bit to "1", setting divided clock mode as the operating mode. 4) to generate a periodic divided clock set tcmrs tcai bit to "1", which will set the counter to be loaded with the value of the timer initial value register each time the counter overflows. for a one-shot divided clock set the tcai bit to "0". 5) set the timers initial value in the timer initial value register tir. writing to this register will simultaneously write the same value to the timer value register tcr. 6) write "1" to tcmrs tcg bit to start counting and generating a divided clock.
MSM7630 ? semiconductor 82/89 speech data registers 1. features this is a register group and control circuit used for speech output. 2. speech data registers functions 2.1 speech output registers these are 12-bit registers that store speech output data. there are two registers and one output register configured to operate at the speech sampling frequency. use of two registers reduces the frequency of interrupt generation during waveform output, which lightens the cpu load. the output stage is provided in the register, which corrects the inaccuracies in the sampling frequencies that are caused by interrupts. the two registers are in parallel, continuously written with d/a conversion data. the output register reads the data from the two registers alternately in every sampling cycle. the output level registers' clock is generated by tmr2. this clock is multiplied by 1/2 to output interrupt signals. the interrupt signals are used to write the waveform output data to the speech output registers. note the following when the msm7576 mode (described later) is not used when using the speech output registers : C the tmr2 must be set to the divided clock mode. C to write data to dac1 and dac2, write to da2 first, then da1. C do not clear the status register of the tmr2. if it is cleared by an interrupt routine, the sampling frequency for the speech output will change. data clk data d wr interrupt to cpu tmr2 output 12-bit reg 12-bit reg 1 1/2 12-bit reg dac
MSM7630 ? semiconductor 83/89 tmr2 output darego dareg1 interrupt to cpu dareg2 0x0001 0x0000 0x0003 0x0002 0xxxxx 0x0000 0x0001 0x0002 2.2 msm7576 mode this mode forces operation to be the same as msm7576 operation. interrupt signals from tmr2 are output directly as interrupts to the cpu. data clk tmr2 output interrupt to cpu 12-bit reg dac 3. speech data registers details 3.1 dac1: speech output register 1 this register stores speech output data. it will be "000000000000" after reset. 3.2 dac2: speech output register 2 this register stores speech output data. it will be "000000000000" after reset. dac1 0 15 bit 0000 12 11 dac2 0 15 bit 0000 12 11
MSM7630 ? semiconductor 84/89 3.3 daco: d/a conversion register this register stores data to be input to the d/a converter. it will be "000000000000" after reset. daco 0 15 bit 0000 12 11 3.4 ustat: status register this register indicates whether or not the speech output registers/circuits have generated an interrupt to the cpu. writing "0" to this register releases the interrupt from the speech output registers/circuits. in msm7576 mode ustat will become "0" when the tmr2 interrupt is released. 3.5 uport: general register this is a general register. it will be "0" after reset. 3.6 mode7576: msm7576 mode select register this register sets msm7576 mode. it will be "0" after reset. 0 u p o r t 1 7 bit 0000000 0 m o d e 1 7 bit 0000000 0 u s t a t 1 7 bit 0000000
MSM7630 ? semiconductor 85/89 4. speech output registers address configuration the addresses used by the speech output registers/circuits are assigned at 0x80000000. accesses to this space will be 3 t access. 0x80000000 speech output register 1 0x80000004 speech output register 2 0x80000008 d/a conversion register 0x8000000c status register 0x80000010 general register 0x80000020 msm7576 mode select register speech output 1. output waveform from dao1 the speech output pin directly outputs the output of the da converter. the output waveform from dao1 will be a staircase synchronized to the sampling frequency. maximum output amplitude will be (4095/4096 v dd ). 2. output filter because the output from dao1 is a staircase described above, add a low-pass filter. the diagram below shows a reference circuit for a butterworth low-pass filter. 2 3 + C rr 1000p 300p r 1200p 15 14 + C 13 16 4 0.1 r r 2200p 220p 11 12 + C 9 10 1k 20k 47k 6 5 + C 7 8 1 1k mc14573p butterworth low-pass filter r = 47k, f=4.8khz (95 model: for 12khz sampling) r = 36k, f=6.4khz (96 model: for 16khz sampling) r = 27k , f=9.6khz ( 97 model: for 22khz sam p lin g)
MSM7630 ? semiconductor 86/89 oscillation circuit there are two methods to generate the MSM7630 system clock: adding an external crystal oscillator or supplying an external clock. 1. crystal oscillator the diagram below shows a connection example for a crystal oscillator. MSM7630 clk xo 1m w gnd 22pf 22pf crystal 2. external clock the diagram below shows an example using an external clock. MSM7630 clk xo external clock open the external clock is input on the clk pin. leave the xo pin open.
MSM7630 ? semiconductor 87/89 system configuration example parallel interface application example + C + C + C + C 3 2 8 1 rr 1k 1000p r 1200p 100p 13 7 4 6 5 12 11 rr 2200p 1k 10 a+5v mc14573 8 2.0k(vr) 220p 14 15 16 13 rca jack stby rst +3.3v a+3.3v 20mhz v cc 1m 22p 22p 10 24 40 56 72 87 96 97 3 5 90 92 93 91 96 100 99 98 1 2 17 32 48 64 79 94 95 v dd v dd v dd v dd v dd v dd v dd av dd rst stby uport clk xo clka extint dao1 test0 sg agnd gnd gnd gnd gnd gnd gnd gnd gnd d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 wr1 wr0 rd sram rom we ras cas1 cas0 as tstm1 MSM7630 tstm2 v cc d26 d25 d24 d31 d30 d29 d28 d27 d26 d25 d24 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 we oe ce msm29c401 a18 a17 a16 a15 a14 a13 a12 a11 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a10 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a8 a7 a6 a5 a4 a3 a2 a1 a0 ras ocas lcas we oe msm514260zs a9 a8 a7 a6 a5 a4 a3 a2 a1 pull-up/down 10k (when the bus capacitance is 100pf)* text-to-speech conversion system configuration example (parallel interface application) 4mb flash rom (x8) 4mb dram (x16) 16mb rom (x16) msm27c1602 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 byte oe ce a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 v cc d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a20 pd<7 : 0> iow ior pcs pa0 v cc 54 51 53 46 50 49 47 30 31 33 34 35 36 37 38 45 43 44 42 41 39 sclk txd rxd dsr dtr cts rts pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pobf pibf pstb pack pcs pioa a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 85 84 83 82 81 80 78 77 76 75 74 73 71 70 69 68 67 66 65 63 62 61 60 59 12 13 14 15 16 18 19 20 21 22 23 25 26 27 28 29 d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 6 7 4 11 9 55 52 58 57 8 88 89 butterworth low-pass filter r = 47k, f=4.8khz (95 model: for 12khz sampling) r = 36k, f=6.4khz (96 model: for 16khz sampling) r = 27k, f=9.6khz (97 model: for 22khz sampling) a a a a a a a a a a a a d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 0.1 * determine the value of each resistor so that the bus will stabilize within 18 m s.
MSM7630 ? semiconductor 88/89 serial interface application example 7 + C + C + C + C 3 2 8 1 rr 1k 1000p r 1200p 300p 13 7 4 6 5 12 11 rr 2200p 1k 10 a+5v mc14573 8 2.0k(vr) 220p 14 15 16 13 rca jack stby rst +3.3v a+3.3v 20mhz 1m 22p 22p 10 24 40 56 72 87 96 97 3 5 90 92 93 91 86 100 99 98 1 2 17 32 48 64 79 94 95 v dd v dd v dd v dd v dd v dd v dd av dd rst stby uport clk xo clka extint dao1 test0 sg agnd gnd gnd gnd gnd gnd gnd gnd gnd d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 wr1 wr0 rd sram rom we ras cas1 cas0 as tstm1 MSM7630 tstm2 d26 d25 d24 d31 d30 d29 d28 d27 d26 d25 d24 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 we oe ce msm29c401 a18 a17 a16 a15 a14 a13 a12 a11 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a10 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a8 a7 a6 a5 a4 a3 a2 a1 a0 ras ocas lcas we oe msm514260zs a9 a8 a7 a6 a5 a4 a3 a2 a1 text-to-speech conversion system configuration example (serial interface application) 4mb flash rom (x8) 4mb dram (x16) 16mb rom (x16) msm27c1602 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 byte oe ce a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 v cc d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a20 54 51 53 46 50 49 47 30 31 33 34 35 36 37 38 45 43 44 42 41 39 sclk txd rxd dsr dtr cts rts pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pobf pibf pstb pack pcs pioa a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 85 84 83 82 81 80 78 77 76 75 74 73 71 70 69 68 67 66 65 63 62 61 60 59 12 13 14 15 16 18 19 20 21 22 23 25 26 27 28 29 d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 6 4 11 9 55 52 58 57 8 88 89 butterworth low-pass filter r = 47k, f=4.8khz (95 model: for 12khz sampling) r = 36k, f=6.4khz (96 model: for 16khz sampling) r = 27k, f=9.6khz (97 model: for 22khz sampling) a a a a a a a a a a a a v cc v cc v cc 2400bps 4800bps 9600bps 19200bps v cc max232 t1in t1out r1out r1in c1+ c1C c2+ c2C r2out t2in 1 1 1 2 3 4 5 6 7 8 din8p v cc 1 1 v cc v+ vC gnd r2in t2out 0.1 v cc d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 pull-up/down 10k (when the bus capacitance is 100pf)* * determine the value of each resistor so that the bus will stabilize within 18 m s.
MSM7630 ? semiconductor 89/89 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp100-p-1420-0.65-bk package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.29 typ. mirror finish

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