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intel ? 855gm/855gme chipset graphics and memory controller hub (gmch) datasheet april 2005 document number: 252615-005 r
r 2 datasheet information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel?s terms and conditions of sale for such products , intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpo se, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustai ning applications. intel may make changes to spec ifications and product de scriptions at any time, without notice. designers must not rely on the absence or c haracteristics of any features or instruc tions marked "reserv ed" or "undefined." int el reserves these for future definition and shall have no re sponsibility whatsoever for c onflicts or incompat ibilities arising from future changes to them. the intel? 855gm/855gme chipset gmch may c ontain design defects or errors known as errata which ma y cause the product to deviat e from published specificat ions. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest s pecifications and before placing your product o rder. i 2 c is a two-wire communications bus/protocol developed by philips. sm bus is a subset of the i 2 c bus/protocol and was developed by intel. implementations of the i 2 c bus/protocol may require licenses fr om various entities, including philips electronics n.v. and north american philips corporation. intel, pentium, celeron, intel speedstep, and intel centrino and the intel logo are tr ademarks or registered trademarks of inte l corporation or its subsidiaries in the united st ates and other countries. *other names and brands may be claim ed as the property of others. copyright ? 2002 ? 2005, intel corporation
r datasheet 3 contents 1 introduc tion ................................................................................................................... .... 19 1.1 terminol ogy.......................................................................................................... 19 1.2 reference do cuments.......................................................................................... 21 2 intel ? 855gm/855gme chipse t gmch over view ............................................................ 23 2.1 system arch itectu re ............................................................................................. 23 2.1.1 intel ? 855gm chipse t gmch ............................................................... 23 2.1.2 intel ? 855gme chip set gm ch............................................................. 23 2.2 processor host interfac e...................................................................................... 24 2.3 gmch system memory interf ace ........................................................................ 24 2.4 graphics f eatures ................................................................................................ 25 2.5 display f eatures .................................................................................................. 26 2.5.1 gmch analog disp lay po rt .................................................................. 26 2.5.2 gmch integrated lvds po rt................................................................ 26 2.5.3 gmch integrated dvo ports ............................................................... 26 2.6 intel ? 855gme gmch agp interfac e .................................................................. 26 2.7 hub interf ace ........................................................................................................ 27 2.8 address decode policie s ..................................................................................... 27 2.9 gmch clocking.................................................................................................... 27 2.10 system inte rrupts ................................................................................................. 28 3 signal descri ptions ........................................................................................................... 2 9 3.1 host interfac e signal s .......................................................................................... 30 3.2 ddr sdram inte rface......................................................................................... 32 3.3 agp interfac e signal s .......................................................................................... 34 3.3.1 agp addressi ng signal s ...................................................................... 34 3.3.2 agp flow cont rol signal s .................................................................... 35 3.3.3 agp status signals .............................................................................. 35 3.3.4 agp str obes ......................................................................................... 36 3.3.5 agp/pci signals- semantic s ................................................................ 36 3.4 hub interfac e signal s ........................................................................................... 39 3.5 clocks................................................................................................................... 39 3.6 internal graphics di splay si gnals ........................................................................ 41 3.6.1 dedicated lvds lcd flat panel inte rface........................................... 41 3.6.2 digital video output b (dvob) port ..................................................... 42 3.6.3 intel ? 855gme gmch dvo/i 2 c to agp pi n mappi ng ......................... 42 3.6.4 digital video output c (dvoc) port ..................................................... 44 3.6.5 analog crt di splay ............................................................................. 45 3.6.6 general purpose inpu t/output si gnals................................................. 46 3.7 voltage references , pll po wer .......................................................................... 48 4 register de scription.......................................................................................................... 5 1
r 4 datasheet 4.1 conceptual overview of the platfo rm configurati on struct ure ............................ 51 4.2 nomenclature for ac cess attr ibutes ..................................................................... 52 4.3 standard pci bus confi guration me chanism ....................................................... 53 4.4 routing configurat ion acce sses .......................................................................... 53 4.4.1 pci bus #0 configur ation mec hanism .................................................. 53 4.4.2 primary pci and downstream configuration mechani sm .................... 54 4.4.3 agp/pci_b bus confi guration me chanism .......................................... 54 4.5 register de finiti ons .............................................................................................. 55 4.6 i/o mapped regi sters .......................................................................................... 56 4.6.1 config_address ? configurat ion address register ...................... 56 4.6.2 config_data ? configurat ion data r egister ................................... 57 4.7 vga i/o mapped r egister s.................................................................................. 58 4.8 intel ? 855gm/gme gmch host-hub interface bridge device registers (device #0, f unction #0) ...................................................................................... 59 4.8.1 vid ? vendor identific ation regi ster .................................................... 60 4.8.2 did ? device identif ication r egister ..................................................... 60 4.8.3 pcicmd ? pci co mmand regi ster ..................................................... 61 4.8.4 pci status regist er .............................................................................. 62 4.8.5 rid ? register i dentificat ion ................................................................. 63 4.8.6 subc ? sub class code regi ster ....................................................... 63 4.8.7 bcc ? base class code regi ster........................................................ 63 4.8.8 hdr ? header type regist er............................................................... 64 4.8.9 svid ? subsystem vendor i dentification regist er ............................... 64 4.8.10 sid ? subsystem identif ication r egister .............................................. 64 4.8.11 capptr ? capabilities po inter regi ster.............................................. 65 4.8.12 capid ? capability identificati on register (d evice #0)........................ 65 4.8.13 gmc ? gmch miscellaneous contro l register (d evice #0)................ 66 4.8.14 ggc ? gmch graphics control register (d evice 0) .......................... 67 4.8.15 dafc ? device and function cont rol register (device 0) .................. 68 4.8.16 fdhc ? fixed dram hole contro l register (d evice #0) .................... 68 4.8.17 pam(6:0) ? programmable attribut e map register (device #0) .......... 69 4.8.18 smram ? system management ram c ontrol register (device #0) .. 72 4.8.19 esmramc ? extended system management ram control (device #0)............................................................................................ 73 4.8.20 errsts ? error status register (d evice #0) ...................................... 74 4.8.21 errcmd ? error command r egister (dev ice #0) .............................. 75 4.8.22 smicmd ? smi error command register (d evice #0) ........................ 76 4.8.23 scicmd ? sci error command register (d evice 0)........................... 77 4.8.24 shic ? secondary host interface control register (device #0).......... 78 4.8.25 acapid ? agp capability identifie r register (d evice #0) ................... 79 4.8.26 agpstat ? agp status r egister (dev ice #0) .................................... 80 4.8.27 agpcmd ? agp command r egister (dev ice #0) ............................... 81 4.8.28 agpctrl ? agp control r egister (dev ice #0) .................................. 82 4.8.29 aft ? agp functional test register (d evice #0)................................ 82 4.8.30 apsize ? aperture si ze (devic e #0) .................................................... 83 4.8.31 attbase ? aperture translation tabl e base register (device #0) ... 84 4.8.32 amtt ? agp interface multi-transac tion timer register (device #0) 84 4.8.33 lptt ? low priority transaction timer register (device #0) .............. 85 4.8.34 hem ? host error control, stat us and observati on (devic e #0) ......... 85 4.9 intel ? 855gm/gme gmch main memory contro l, memory i/o control registers (device #0, f unction #1) ...................................................................................... 86 4.9.1 vid ? vendor identific ation regi ster .................................................... 87
r datasheet 5 4.9.2 did ? device identif ication r egister ..................................................... 87 4.9.3 pcicmd ? pci co mmand regi ster ..................................................... 88 4.9.4 pcists ? pci stat us regi ster ............................................................. 89 4.9.5 rid ? revision identif ication r egister .................................................. 90 4.9.6 subc ? sub-class code regi ster ....................................................... 90 4.9.7 bcc ? base class code regi ster........................................................ 90 4.9.8 hdr ? header type regist er............................................................... 91 4.9.9 svid ? subsystem vendor i dentification regist er ............................... 91 4.9.10 sid ? subsystem identif ication r egister .............................................. 91 4.9.11 capptr ? capabilities po inter regi ster.............................................. 92 4.9.12 drb ? dram row (0:3) boundary register (d evice #0) .................... 92 4.9.13 dra ? dram row attribute register (d evice #0) ............................... 93 4.9.14 drt ? dram timing regi ster (dev ice #0) .......................................... 94 4.9.15 pwrmg ? dram controller power management control register (device #0)............................................................................................ 98 4.9.16 drc ? dram controller mode r egister (dev ice #0) ........................... 99 4.9.17 dtc ? dram throttling contro l register (d evice #0) ....................... 101 4.10 intel ? 855gm/gme gmch configuration pr ocess registers (device #0, function #3)........................................................................................................ 105 4.10.1 vid ? vendor identific ation regi ster .................................................. 106 4.10.2 did ? device identif ication r egister ................................................... 106 4.10.3 pcicmd ? pci co mmand regi ster ................................................... 106 4.10.4 pcists ? pci stat us regi ster ........................................................... 107 4.10.5 rid ? revision identif ication r egister ................................................ 108 4.10.6 subc ? sub-class code regi ster ..................................................... 108 4.10.7 bcc ? base class code regi ster ...................................................... 108 4.10.8 hdr ? header type regist er............................................................. 109 4.10.9 svid ? subsystem vendor i dentification regist er ............................. 109 4.10.10 id ? subsystem identif ication r egister ............................................... 109 4.10.11 capptr ? capabilities po inter regi ster ............................................ 110 4.10.12 hpllcc ? hpll clock control register (d evice #0)........................ 110 4.11 intel ? 852gm gmch integrated graphics devi ce registers (device #2, function #0)........................................................................................................ 113 4.11.1 vid ? vendor identification register (d evice #2) ............................... 114 4.11.2 did ? device identificati on register (d evice #2) ............................... 114 4.11.3 pcicmd ? pci command r egister (dev ice #2) ................................ 114 4.11.4 pcists ? pci status r egister (dev ice #2) ........................................ 115 4.11.5 rid ? revision identificati on register (d evice #2) ............................ 116 4.11.6 cc ? class code regist er (devic e #2) .............................................. 116 4.11.7 cls ? cache line size r egister (dev ice #2) .................................... 116 4.11.8 mlt ? master latency timer register (d evice #2)............................ 117 4.11.9 hdr ? header type regist er (devic e #2) ......................................... 117 4.11.10 gmadr ? graphics memory range a ddress register (device #2).. 117 4.11.11 mmadr ? memory mapped range address register (device #2) ... 118 4.11.12 iobar ? i/o base address register (d evice #2) .............................. 118 4.11.13 svid ? subsystem vendor identific ation register (device #2).......... 119 4.11.14 sid ? subsystem identificati on register (d evice #2)......................... 119 4.11.15 romadr ? video bios rom base a ddress registers (device #2) 119 4.11.16 intrline ? interrupt line register (d evice #2) ................................ 120 4.11.17 intrpin ? interrupt pin register (d evice #2).................................... 120 4.11.18 mingnt ? minimum grant register (d evice #2) ............................... 120 4.11.19 maxlat ? maximum latency r egister (d evice #2) ......................... 120 4.11.20 pmcap ? power management capabilities register (device #2)..... 121
r 6 datasheet 4.11.21 pmcs ? power management control/st atus register (device #2) ... 121 5 intel ? 855gm/gme gmch system address map .......................................................... 123 5.1 system memory address ranges ...................................................................... 123 5.2 dos compatib ility ar ea ..................................................................................... 125 5.3 extended system me mory ar ea......................................................................... 127 5.4 main system memory address range (0010_0000h to top of main memory). 128 5.4.1 15-mb ? 16-mb window ..................................................................... 128 5.4.2 pre-allocated sy stem me mory ............................................................ 128 5.4.2.1 extended smram address range (hseg and tseg) ... 129 5.4.2.2 hseg ................................................................................ 129 5.4.2.3 tseg ................................................................................. 129 5.4.2.4 dynamic video memory technology (dvmt) ................... 129 5.4.2.5 pci memory address range (top of main system memory to 4 gb ) ............................................................................. 129 5.4.2.6 apic configuration space (fec0_0000h -fecf_ffffh, fee0_0000h- feef _ffffh) ............................................ 130 5.4.2.7 high bios area ( ffe0_0000h -ffff_ ffffh)................. 130 5.4.3 system management mode (s mm) memory range .......................... 130 5.4.3.1 smm space rest ricti ons ................................................... 131 5.4.3.2 smm space de finiti on ....................................................... 131 5.4.4 system memory shadowin g ............................................................... 132 5.4.5 i/o address space .............................................................................. 132 5.4.5.1 agp/pci i/o addr ess mappi ng ......................................... 132 5.4.6 gmch decode rules and cross- bridge addre ss mappi ng............... 133 5.4.7 hub interface de code rule s............................................................... 133 5.4.7.1 hub interface accesses to gmch that cross device boundarie s ........................................................................ 133 5.4.7.2 agp interface de code rule s ............................................ 134 6 functional de scripti on .................................................................................................... 137 6.1 host interfac e overvi ew ..................................................................................... 137 6.2 dynamic bus in versio n....................................................................................... 137 6.2.1 system bus interr upt deliv ery ............................................................ 137 6.2.2 upstream interr upt mess ages ............................................................ 138 6.3 system memory interfac e .................................................................................. 138 6.3.1 ddr sdram interfac e overvi ew ....................................................... 138 6.3.2 system memory organizati on and configur ation............................... 139 6.3.2.1 configuration mechani sm for so -dimms ......................... 139 6.3.2.2 system memory regi ster progr amming ........................... 139 6.3.3 ddr sdram performanc e descrip tion ............................................. 140 6.3.3.1 data integr ity (ecc) .......................................................... 140 6.4 integrated graphi cs overvi ew............................................................................ 140 6.4.1 3d/2d instructi on proce ssing ............................................................. 141 6.4.2 3d engi ne ........................................................................................... 141 6.4.2.1 bi-cubic filtering (intel ? 855gme gmch) ........................ 142 6.4.2.2 video mixer rendering (intel ? 855gme gmch) .............. 142 6.4.2.3 setup e ngine ..................................................................... 142 6.4.2.4 viewport transform and pe rspective divide ..................... 142 6.4.2.5 3d primitives and data formats support .......................... 143 6.4.2.6 pixel accurate fast scissoring and clipping operation.... 143 6.4.2.7 backface cu lling................................................................ 143
r datasheet 7 6.4.2.8 scan conver ter.................................................................. 143 6.4.2.9 texture e ngine .................................................................. 143 6.4.2.10 perspective correct texture s upport ................................ 144 6.4.2.11 texture deco mpressi on .................................................... 144 6.4.2.12 texture chro makey ........................................................... 144 6.4.2.13 anti-alia sing....................................................................... 144 6.4.2.14 texture map f ilterin g ........................................................ 145 6.4.2.15 multiple texture composit ion............................................ 145 6.4.2.16 cubic environm ent mappi ng ............................................. 146 6.4.2.17 bump m apping .................................................................. 146 6.4.3 raster e ngine ..................................................................................... 146 6.4.3.1 texture map blending ....................................................... 146 6.4.3.2 combining intrinsic and specular color components ...... 146 6.4.3.3 color shadi ng modes ........................................................ 147 6.4.3.4 color dit hering ................................................................... 147 6.4.3.5 vertex and per pi xel foggi ng............................................ 147 6.4.3.6 alpha blendi ng .................................................................. 147 6.4.3.7 color buffer formats: (destinati on alpha) ........................ 148 6.4.3.8 depth bu ffer ...................................................................... 148 6.4.3.9 stencil bu ffer ..................................................................... 148 6.4.3.10 projective textur es............................................................ 149 6.4.4 2d engi ne ........................................................................................... 149 6.4.4.1 256-bit pattern fill and blt e ngine .................................. 149 6.4.4.2 alpha stretc h blt ............................................................. 150 6.4.5 planes and e ngines ............................................................................ 150 6.4.5.1 dual pipe independent disp lay functi onality.................... 150 6.4.6 hardware curs or pl ane ...................................................................... 150 6.4.6.1 cursor color format s........................................................ 151 6.4.6.2 popup plane (second cursor ) .......................................... 151 6.4.6.3 popup color fo rmats ........................................................ 151 6.4.7 overlay plane ..................................................................................... 151 6.4.7.1 multiple overlays (display c) ............................................ 151 6.4.7.2 source/destination co lor/chroma keying .......................... 151 6.4.7.3 gamma corre ction ............................................................ 152 6.4.7.4 yuv to rgb c onversi on ................................................... 152 6.4.7.5 color cont rol ..................................................................... 152 6.4.7.6 dynamic bob and weav e.................................................. 152 6.4.8 video functi onality .............................................................................. 152 6.4.8.1 mpeg-2 de coding ............................................................ 152 6.4.8.2 hardware motion compensat ion....................................... 153 6.4.8.3 sub-picture support .......................................................... 153 6.5 display inte rface................................................................................................. 153 6.5.1 analog display port characteri stics ................................................... 153 6.5.1.1 integrated ramdac.......................................................... 154 6.5.1.2 ddc (display da ta channel ) ............................................ 154 6.5.2 digital display interfac e ...................................................................... 154 6.5.2.1 dedicated lvds interfac e................................................. 154 6.5.2.2 lvds interfac e signal s ..................................................... 155 6.5.2.3 lvds pair states............................................................... 155 6.5.2.4 single channel versus dual channel mode ..................... 155 6.5.2.5 lvds channel skew ......................................................... 155 6.5.2.6 ssc suppor t...................................................................... 155 6.5.2.7 panel power sequencin g .................................................. 156
r 8 datasheet 6.5.2.7.1 panel power s equence stat es.......................... 156 6.5.2.8 back light invert er cont rol................................................ 157 6.5.2.9 digital video ou tput po rt................................................... 157 6.5.2.10 intel 855gme gmch agp in terface ov erview................. 158 6.5.2.11 agp target o perati ons..................................................... 158 6.5.3 agp transaction orderin g ................................................................. 159 6.5.4 agp signal levels .............................................................................. 159 6.5.5 4x agp pr otocol ................................................................................. 159 6.5.5.1 fast wr ites ........................................................................ 160 6.5.5.2 agp frame# transac tions on agp ................................ 160 6.5.6 concurrent and simu ltaneous disp lay ............................................... 163 7 power and therma l managem ent................................................................................... 165 7.1 general description of supported cpu states .................................................. 165 7.2 7.2. general descripti on of acpi states............................................................ 166 7.3 enhanced intel speedstep ? technology overvi ew ........................................... 167 7.4 internal ther mal sens or..................................................................................... 167 7.4.1 overvi ew ............................................................................................. 167 7.4.2 hysteresis o peratio n .......................................................................... 167 7.5 external thermal sensor input ........................................................................... 167 7.5.1 usage.................................................................................................. 168 8 electrical char acterist ics................................................................................................. 169 8.1 absolute maxi mum rati ngs................................................................................ 169 8.2 thermal charac teristic s ..................................................................................... 170 8.3 power characte ristics ........................................................................................ 171 8.4 signal gr oups..................................................................................................... 172 8.5 dc characteri stics ............................................................................................. 176 8.5.1 general dc charac teristic s ................................................................ 176 8.5.2 dac dc characte ristic s ..................................................................... 183 8.5.3 dac reference and output specific ations ........................................ 184 9 video filter capacitors and ferrite bead arranged in a pi configuration (one pi filter testab ility) ................................................................................................................... .... 185 9.1 xor test m ode entr y ........................................................................................ 186 9.2 xor chain differ ential pa irs.............................................................................. 187 9.3 xor chain excl usion li st .................................................................................. 187 9.4 xor chain connectivi ty/order ing ..................................................................... 188 9.4.1 vcc/vss volt age groups .................................................................. 200 10 intel ? 855gm/gme gmch strap pi ns............................................................................ 201 10.1 strapping confi guratio n...................................................................................... 201 11 ballout and package informat ion .................................................................................... 203 11.1 package mechanical informat ion ....................................................................... 211
r datasheet 9 figures figure 1. intel ? 855gm gmch chipset syst em block diagram ...................................... 16 figure 2. intel ? 855gme gmch chipset sy stem block diagram .................................... 18 figure 3. configurati on address r egister ......................................................................... 56 figure 4. configurati on data r egister .............................................................................. 57 figure 5. pam registers ................................................................................................... 70 figure 6. simplified view of system addr ess map ......................................................... 124 figure 7. detailed view of system addr ess map ........................................................... 125 figure 8. intel ? 855gm gmch graphics block di agram ............................................... 141 figure 9. panel po wer sequenc ing ................................................................................ 156 figure 10. xor? tree chai n ........................................................................................... 185 figure 11. xor chain test mode entry event s diagr am .............................................. 186 figure 12. allz test m ode entry event s diagr am ........................................................ 186 figure 13. intel ? 855gm/855gme gmch ballout diagram (top view)......................... 203 figure 14. intel ? 855gm/855gme gmch micro-fcbga package dimensions (top view )................................................................................................................ 211 figure 15. intel ? 855gm/855gme gmch micro-fcbga package dimensions (side vi ew) ............................................................................................................... 212 figure 16. intel ? 855gm/855gme gmch micro-fcbga package dimensions (bottom vi ew) .......................................................................................................... 213 tables table 1. ddr sdram me mory capac ity ......................................................................... 25 table 2. intel ? 855gm/855gme gmch in terface cl ocks ................................................ 28 table 3. host interfac e signal descr iptions ...................................................................... 30 table 4. ddr sdram inte rface descr iptions .................................................................. 32 table 5. agp addressi ng signal descr iptions ................................................................. 34 table 6. agp flow control si gnals .................................................................................. 35 table 7. agp status signal descr iptions ......................................................................... 35 table 8. agp str obe descrip tions .................................................................................... 36 table 9. agp/pci signals-se mantics desc ripti ons.......................................................... 36 table 10. hub inte rface si gnals........................................................................................ 39 table 11. clo ck signal s .................................................................................................... 39 table 12. dedicated lvds lcd flat panel interface si gnal descrip tions....................... 41 table 13. digital video output b (d vob) port signal descrip tions ................................. 42 table 14. intel ? 855gme gmch agp/dv o pin mu xing.................................................. 43 table 15. digital video output c (d voc) port signal descript ions................................. 44 table 16. dvob and dvoc port common signal descripti ons ...................................... 44 table 17. analog crt disp lay signal de scripti ons ......................................................... 45 table 18. gpio si gnal descrip tions ................................................................................. 46 table 19. voltage refer ences, pll power ....................................................................... 48 table 20. device nu mber assi gnment ............................................................................. 51 table 21. nomenclature fo r access a ttribut es ................................................................. 52 table 22. vga i/o m apped register list ......................................................................... 58 table 23. index ? da ta regist ers ..................................................................................... 58 table 24. gmch configuration s pace - device #0, functi on#0 ...................................... 59 table 25. attribut e bit assi gnment .................................................................................... 69
r 10 datasheet table 26. pam registers and associ ated system memo ry segm ents............................ 71 table 27. host-hub i/f bridge/system memory controller configuration space (device #0, func tion#1) .......................................................................................................... 86 table 28. configuration process confi guration space (devic e#0, functi on #3) ........... 105 table 29. intel ? 855gm gmch configurations and some resoluti on examples.......... 111 table 30. for intel ? 855gme gmch configurations and some resolution examples. 112 table 31. integrated graphics device confi guration space (device #2, function#0)... 113 table 32. system memory s egments and their attribut es ............................................ 126 table 33. pre-allocat ed system memory ........................................................................ 128 table 34. smm space tr ansaction h andling ................................................................. 131 table 35. relation of dbi bits to da ta bits ..................................................................... 137 table 36. data bytes on so-dimm us ed for programming dra m regist ers............... 139 table 37. dual display usage model (intel ? 852gm gm ch) ........................................ 150 table 38. panel power sequenc ing timing pa ramete rs................................................ 157 table 39. agp commands supported by the gmch when acting as an agp target . 158 table 40. fast writ e initializ ation.................................................................................... 160 table 41. pci commands supported by the gmch when acting as a frame# target ....................................................................................................................... 16 1 table 42. enhanced intel speedstep ? technology overvi ew ....................................... 167 table 43. absolute maximum ra tings ............................................................................ 169 table 44. intel ? 855gm/855gme gmch package thermal resi stance ....................... 170 table 45. power c haracterist ics ..................................................................................... 171 table 46. tabl e signal s .................................................................................................. 173 table 47. dc char acterist ics .......................................................................................... 176 table 48. dac dc characteristi cs: functional operating range (vccdac = 1.5 v 5%)........................................................................................... 183 table 49. dac reference and output specif icati ons .................................................... 184 table 50. differential signal s in the xo r chai ns ........................................................... 187 table 51. xor chain excl usion list of pi ns................................................................... 187 table 52. xo r mappi ng ................................................................................................. 188 table 53. voltage levels and ba ll out for vo ltage gr oups ............................................ 200 table 54. strapping signal s and configur ation .............................................................. 201 table 55. ball out tabl e ................................................................................................... 204
r datasheet 11 revision history revision number description date 001 initial release july 2003 002 updates include: ? edited 855gm features under host bus support ? changed naming convention for host bus from processor system bus (psb) to front side bus (fsb) ? added 855gme features and system diagram to features section ? section 1: added disclaimer for intel ? centrino? mobile technology ? updated reference documents list ? section 2: added system architecture details for 855gm/855gme ? section 3: updated section with agp interface signal details, which is supported by 855gme ? updated sections 3.3.1-3.3.5 and section 3.6 ? section 4: added registers related to host interface and agp port ? section 5: updated sections for agp memory addresses ? section 6: incorporated 855gme feat ures as bi-cubic filtering, video mixer rendering ? added sections 6.5.2.10 ? 6.5.6 with agp interface overview ? section 7: updated power and thermal management with features as system memory refresh ? section 8: added xor test mode entry subsection ? added note to voltage table to indicate 855gme nominal voltage levels. ? edited package dimensions (bottom view) figure, row z (original) renamed row y september 2003 003 updates include: ? added intel ? celeron ? m processor support january 2004 004 updates include: ? added intel ? pentium ? m processor on 90 nm process with 2-mb l2 cache support updated table 55. ballout table to include agp signals may 2004
r 12 datasheet revision number description date 005 updates include: ? added new chapter 8 electrical characteristics ? absolute maximum ratings ? thermal characteristics ? power characteristics ? signal groups ? dc characteristics ? testability moved to chapter 9 ? intel 855gm/gme gmch strap pins is now chapter 10 ballout and package information is now chapter 11 april 2005
r datasheet 13 intel ? 855gm chipset gmch features ? processor/host bus support ? intel? pentium? m processor and intel? celeron? m processor ? 2x address, 4x data ? supports 400 mhz front side bus (fsb) ? supports host bus dynamic bus inversion (dbi) ? supports 64-bit host data bus and 32-bit addressing ? 8-deep in-order queue ? agtl+ bus driver technology with integrated agtl+ termination resistors and low voltage operation (vtt = 1.05 v) ? supports enhanced intel speedstep ? technology (intel pentium m processor ? support for dpwr# signal to intel pentium m processor and intel celeron m processor for fsb power management ? memory system ? directly supports one ddr sdram channel, 64-bits wide (72-bits with ecc) ? supports 200/266 mhz ddr sdram devices with max of two, double-sided so- dimms (four rows populated) with unbuffered pc1600/pc2100 ddr sdram. ? supports 128-mbit, 256-mbit, and 512-mbit technologies providing maximum capacity of 1 gb with x16 devices and up to 2-gb with high density 512-mbit technology ? all supported devices have four banks ? supports up to 16 simultaneous open pages ? supports page sizes of 2-kb, 4-kb, 8-kb, and 16-kb. page size is individually selected for every row ? uma support only ? system interrupts ? supports intel 8259 and front side bus interrupt delivery mechanism ? supports interrupts signaled as upstream memory writes from pci and hub interface ? msi sent to the cpu through the system bus ? ioxapic in ich4-m provides redirection for upstream interrupts to the system bus ? video stream decoder ? improved hardware motion compensation for mpeg2 ? all format decoder (18 atsc formats) supported ? dynamic bob and weave support for video streams ? software dvd at 60 fields/second and 30 frames/second full screen ? support for standard definition dvd (i.e. ntsc pixel resolution of 720x480, etc.) quality encoding at low cpu utilization ? video overlay ? single high quality scalable overlay and second sprite to support second overlay ? multiple overlay functionality provided via arithmetic stretch blt(block transfer) ? 5-tap horizontal, 3-tap vertical filtered scaling ? multiple overlay formats ? direct yuv from overlay to tv-out ? independent gamma correction ? independent brightness / contrast/ saturation ? independent tint/hue support ? destination colorkeying ? source chromakeying ? multiple hardware color cursor support (32-bit with alpha and legacy 2-bpp mode) ? accompanying i2c and ddc channels provided through multiplexed interface ? display ? analog display support ? 350 mhz integrated 24-bit ramdac that can drive a standard progressive scan analog monitor with pixel resolution up to 1600x1200 at 85 hz and up to 2048x1536 at 75 hz ? dual independent pipe support ? concurrent: different images and native display timings on each display device ? simultaneous: same images and native display timings on each display device
r 14 datasheet ? dvo (dvob and dvoc) support ? digital video out ports dvob and dvoc with 165 mhz dot clock on each 12-bit interface; two 12-bit channels can be combined to form one dual channel 24-bit interface with an effective dot clock of 330 mhz ? the combined dvo b/c ports as well as individual dvo b/c ports can drive a variety of dvo devices (tv-out encoders, tmds and lvds transmitters, etc.) with pixel resolution up to 1600x1200 at 85 hz and up to 2048x1536 at 72 hz. ? compliant with dvi specification 1.0 ? dedicated lfp (local flat panel) lvds interface ? single- or dual-channel lvds panel support up to uxga panel resolution with frequency range from 25 mhz to 112 mhz (single channel/dual channel) ? supports data format of 18 bpp ? ssc support of 0.5%, 1.0%, and 2.5% center and down spread with external ssc clock ? lcd panel power sequencing compliant with spwg timing specification ? compliant with ansi/tia/eia ?644- 1995 spec ? integrated pwm interface for lcd backlight inverter control ? bi-linear panel fitting ? tri-view support through lfp interface, dvo b/c port, and crt ? internal graphics features ? up to 64 mb of dynamic video memory allocation ? display image rotation ? graphics core frequency ? display core frequency at 133 mhz or 200 mhz ? render core frequency at 100 mhz, 133 mhz, 200 mhz ? 2d graphics engine ? optimized 128-bit blt engine ? ten programmable and predefined monochrome patterns ? alpha stretch blt (via 3d pipeline) ? anti-aliased lines ? hardware-based blt clipping and scissoring ? 32-bit alpha blended cursor ? programmable 64 x 64 3-color transparent cursor ? color space conversion ? three operand raster blts ? 8-bit, 16-bit, and 32-bit color ? rop support ? dib translation and linear/tile addressing ? 3d graphics engine ? 3d setup and render engine ? zone rendering ? high quality performance texture engine ? viewpoint transform and perspective divide ? triangle lists, strips and fans support ? indexed vertex and flexible vertex formats ? pixel accurate fast scissoring and clipping operation ? backface culling support ? microsoft directx* and sgi opengl* pixelization rules ? anti-aliased lines support ? sprite points support ? provides the highest sustained fill rate performance in 32-bit color and 24-bit w mode ? high quality performance texture engine ? 266-megatexel/s peak performance ? per pixel perspective corrected texture mapping ? single pass texture compositing (multi- textures) ? enhanced texture blending functions
r datasheet 15 ? twelve level of detail mip map sizes from 1x1 to 2k x 2k ? numerous texture formats including 32- bit rgba ? alpha and luminance maps ? texture chromakeying ? bilinear, trilinear, and anisotropic mip map filtering ? cubic environment reflection mapping ? dot product bump-mapping ? embossed bump-mapping ? dxtn texture decompression ? fx1 texture compression ? 3d graphics rasterization enhancements ? one pixel per clock ? flat and gouraud shading ? color alpha blending for transparency ? vertex and programmable pixel fog and atmospheric effects ? color specular lighting ? z bias support ? dithering ? line and full-scene anti-aliasing ? 16 and 24-bit z buffering ? 16 and 24-bit w buffering ? 8-bit stencil buffering ? double and triple render buffer support ? 16 and 32-bit color ? destination alpha ? vertex cache ? optimal 3d resolution supported ? fast clear support ? rop support ? hub interface to ich4-m ? 266 -mb/s point-t o-point hub interface to ich4-m ? 66 mhz base clock ? power management ? smram space remapping to a0000h (128- kb)
r 16 datasheet figure 1. intel ? 855gm gmch chipset system block diagram intel? pentium? m processor or intel? celeron? m processor lpc i/f ac'97 2.2/2.3 pci bus hub interface 1.5 intel? 82801dbm 421 bga (ich4-m) intel? 855gm gmch 732 micro- fcbga fwh dvi device dvob & dvoc 1.5 v 400 mhz fsb 200/266 mhz ddr kbc sio audio codec modem codec ata100 ide (2) usb2.0/1.1 (6) ck-408 cardbus lan moon 2 pci docking intel? pro/ wireless network connection mini-pci imvp-iv vr lvds crt
r datasheet 17 intel ? 855gme chipset gmch features note: the intel 855gme chipset gmch has identical features to the intel 855gm chipset gmch except for the additional features listed below. ? processor/host bus support ? pin and spec compatible with the intel ? pentium ? m processor, intel ? pentium ? m processor on 90 nm process with 2-mb l2 cache and intel ? celeron ? m processor ? memory system ? support for 333 mhz ddr sdram devices with max of two double-sided so- dimms (4 rows populated) with unbuffered pc2700 ddr sdram. ? display ? dedicated lfp (local flat panel) interface ? supports data format up to 24-bpp ? internal graphics features ? core vcc = 1.2 v or 1.35 v (1.35 v needed to support graphics core frequency of 250 mhz and 333 mhz ddr sdram devices) ? graphics core frequency ? display core frequency at 133 mhz,200 mhz, 250 mhz ? render core frequency at 100 mhz, 133 mhz, 166 mhz, 200 mhz, 250 mhz ? intel? dual-frequency graphics technology ? 3d graphics engine ? enhanced hardware binning instruction set supported ? bi-cubic filtering supported ? linear gamma blending for video mixer rendering (vmr) ? video mixer rendering (vmr) supported ? graphics power management ? dynamic frequency switching ? memory self-refresh during c3 ? intel? display power saving technology ? power management ? optimized clock gating for 3d and display engines ? on-die thermal sensor ? accelerated graphics port (agp) interface ? supports a single agp device ? supports agp 2.0 including 1x,2x, and 4x agp data transfers and 2x/4x fast write protocol ? supports only 1.5 v agp electricals ? 32 deep agp request queue ? pci semantic (frame# initiated) accesses to ddr sdram are snooped ? agp semantic (pipe# and sba) accesses to ddr sdram are not snooped ? hierarchical pci conf iguration mechanism ? delayed transaction support ? agp busy/stop protocol
r 18 datasheet figure 2. intel ? 855gme gmch chipset system block diagram intel? pentium ? m processor or intel? celeron? m processor lpc i/f ac'97 2.2/2.3 pci bus hub interface 1.5 intel? 82801dbm 421 bga (ich4-m) intel? 855gme gmch 732 micro- fcbga fwh dvi/agp device dvob/c or agp 1.5 v 400 mhz fsb 200/266/333 mhz ddr sdram kbc sio audio codec modem codec ata100 ide (2) usb2.0/1.1 (6) ck-408 cardbus lan moon 2 pci docking intel? pro/ wireless network connection mini-pci imvp-iv vr lvds crt
introduction r datasheet 19 1 introduction this datasheet provides intel?s specifications for the intel ? 855gm/855gme chipset based system. the intel 855gm/855gme chipset graphics and memory controller hub (gmch) is also an intel ? centrino? mobile technology component. intel centrino mobile technology with integrated wireless lan capabilities was designed specifica lly for wireless note book pcs ? delivering outstanding mobile performance and enabling extended battery life, and thinner, lighter designs. note: wireless connectivity and some features may require you to purchase additional software, services or external hardware. availability of public wireless lan access points limited. system performance measured by mobilemark* 2002. system performance, battery life, wireless performance and functionality will vary depending on your specific hardware and software configurations. see http://www.intel.com/products/centrino/moreinfo for more information. 1.1 terminology term description agtl+ advanced gunning transceiver logic + (agtl+) bus ddc display data channel (standard created by vesa) dpms display power management signaling (standard created by vesa) i2c inter-ic (a two wire serial bus created by philips) crt cathode ray tube lcd liquid crystal display bli backlight inverter core the internal base logic in the intel 855gm/gme gmch cpu central processing unit dbi dynamic bus inversion dbl display brightness link dvo digital video out dvi* digital visual interface is the interfac e specified by the ddwg (digital display working group) dvi spec. rev. 1.0 utilizing only the silicon image developed tmds protocol dvmt dynamic video memory technology edid extended display identification data full reset a full intel 855gm/gme gmch reset is defined in this document when rstin# is asserted gmch graphics and memory controller hub hub interface (hi) the proprietary interconnect between the intel 855gm/gme gmch and the ich4-m component. in this document, the h ub interface cycles originating from
introduction r 20 datasheet term description or destined for the ich4-m are generally re ferred to as ?hub interface cycles.? hub cycles originating from or desti ned for the primary pci interface on are sometimes referred to as ?hub interface/pci cycles? host this term is used synonymously with processor igd integrated graphics device intel 855gm/gme gmch refers to the gmch component. throughout this datasheet, the intel 855gm/gme gmch will be referred to as the gmch. intel 82801dbm ich4-m the component contains the pr imary pci interface, lpc interface, usb 2.0, ata-100, ac?97, and other i/o functions. it communicates with the intel 855gm/gme gmch over a proprietary interconnect called the hub interface. throughout this datasheet, the intel 82801dbm ich4-m component will be referred to as the ich4-m intel pentium m processor refers to the intel pentium m processor and intel pentium m processor on 90nm process with 2-mb l2 cache. intel pentium m processor will reference both processors unless specified ipi inter processor interrupt lfp local flat panel lvds low voltage differential signals us ed for interfacing to lcd flat panels msi message signaled interrupts. msi allo w a device to request interrupt service via a standard memory write transaction instead of through a hardware signal fsb front side bus. connection between intel 855gm/gme gmch and the cpu. also known as the host interface pwm pulse width modulation ssc spread spectrum clocking system bus processor-to-intel 855gm/gme gmch interface. the enhanced mode of the scalable bus is the p6 bus plus enhancements, consisting of source synchronous transfers for address and data, and system bus interrupt delivery. the intel pentium m processor, intel pentium m on 90nm process with 2-mb l2 cache and intel celeron m processor implement a subset of enhanced mode. uma unified memory architecture with graphics memory for the igd inside system memory vdl video data link
introduction r datasheet 21 1.2 reference documents document location intel ? pentium ? m processor datasheet (252612) http://www. intel.com/design/mobile/datashts/252612.h tm intel ? pentium ? m processor on 90 nm process with 2- mb l2 cache datasheet (302189) http://developer.intel.com/ design/mobile/datashts/302 189.htm intel ? celeron ? m processor datasheet (300302) http://www. intel.com/design/mobile/datashts/300302.h tm intel? 852gm/855gm/855gme chipset mobile thermal design guide note 1 pci local bus specification 2.2 http://www.pcisig.com intel ? 82801dbm i/o controller hub 4 mobile (ich4- m) datasheet (252337) http://developer.intel.com/ design/mobile/datashts/252 337.htm intel ? 855gm/855gme chipset platform design guide (252616) http://www. intel.com/design/mobile/desguide/252616. htm advanced configuration and power management(acpi) specification 1.0b & 2.0 http://www.acpi.info/ advanced power management (apm) specification 1.2 http://www. microsoft.com/hwdev/busbios/ amp_12.htm ia-32 intel ? architecture software developer manual volume 3: system programming guide (253668) http://developer.intel.com /design/pentium4/manuals/i ndex_new.htm notes: 1. contact your intel representative for the current document.
introduction r 22 datasheet
intel? 855gm/855gme chipset gmch overview r datasheet 23 2 intel ? 855gm/855gme chipset gmch overview 2.1 system architecture the intel 855gm/855gme gmch components provi de the processor interface, ddr sdram interface, display interface, a nd hub interface. the intel 855gme also has an option for agp external graphics port, in addition to integrated graphics support for added board flexibility options. 2.1.1 intel ? 855gm chipset gmch the intel 855gm gmch is in a 732-pin micro-fcbga package and contains the following functionality listed below: ? agtl+ host bus supporting 32-bit host addressing with enhanced intel speedstep ? technology support ? supports a single channel of ddr sdram memory ? system memory supports ddr200/266 mhz (sstl_2) ddr sdram ? integrated graphics capabilities: display core frequency at 133 mhz or 200 mhz ? render core frequency at 100 mhz ,133 mhz, and 200 mhz ? provides supports four display ports: one progressive scan analog monitor, dual channel lvds interface and two dvo port. 2.1.2 intel ? 855gme chipset gmch the intel 855gme gmch is in a 732-pin micro-fcbga package and contains all features listed above and the additional functionality list below: ? display core frequency at 133 mhz, 200 mhz, or 250 mhz ? render core frequency at 100 mhz ,133 mhz, 166 mhz, 200 mhz, or 250 mhz ? system memory supports 200/266/333- mhz (sstl_2) ddr sdram. ? enhanced power management graphics features
intel? 855gm/855gme chipset gmch overview r 24 datasheet 2.2 processor host interface the intel 855gm/855gme gmch is optimized for the intel pentium m processor and intel celeron m processor key features of the front side bus (fsb) are: ? support for a 400 mhz system bus frequency. ? source synchronous double pumped address (2x) ? source synchronous quad pumped data (4x) ? front side bus interrupt delivery ? low voltage swing vtt (1.05v) ? dynamic power down (dpwr#) support ? integrates agtl+ termination resistors on all of the agtl+ signals ? supports 32-bit host bus addressing allowing the cpu to access the entire 4 gb of the gmch memory address space. ? an 8-deep, in-order queue ? support dpwr# signal ? supports one outstanding de fer cycle at a time to any particular i/o interface 2.3 gmch system memory interface the gmch system memory controller directly supports the following: ? one channel of pc1600/2100 so-dimm ddr sdram memory (intel 855gm gmch) ? one channel of pc1600/2100/2700 so-dimm ddr sdram memory (intel 855gme gmch) ? ddr sdram devices with densities of 128-mb, 256-mb, and 512-mb technology ? up to 1 gb (512-mb technology) with two so-dimms ? up to 2 gb (512-mb technology) using high density devices with two so-dimms
intel? 855gm/855gme chipset gmch overview r datasheet 25 table 1. ddr sdram memory capacity technology width system memory capacity system memory capacity with stacked memory 128 mb 16 256 mb - 256 mb 16 512 mb - 512 mb 16 1 gb - 128 mb 8 256 mb 512 mb 256 mb 8 512 mb 1 gb 512 mb 8 1 gb 2 gb the gmch system memory interface supports a th ermal throttling scheme to selectively throttle reads and/or writes. throttling can be triggered either by the on-die thermal sensor, or by preset write bandwidth limits. read throttle can also be triggered by an external input pin. the memory controller logic supports aggressive dynamic ro w power down features to help reduce power and supports address and control line tri-stating when ddr sdram is in an active power down or in self refresh state. the gmch system memory architecture is optimized to maintain open pages (up to 16-kb page size) across multiple rows. as a result, up to 16 pages across four rows is supported. to complement this, the gmch will tend to keep pages open within rows, or will only close a single bank on a page miss. the gmch supports only four bank memory technologies. 2.4 graphics features the gmch igd provides a highly integrated gr aphics accelerator deliv ering high performance 2d, 3d, and video capabilities. with its interf aces to uma using a dvmt configuration, an analog display, a lvds port, and two digital display ports (e.g. flat panel), the gmch can provide a complete graphics solution. the gmch also provides 2d hard ware acceleration for block transf ers of data (blts). the blt engine provides the ability to copy a source block of data to a destination and perform raster operations (e.g., rop1, rop2, and rop3) on the data using a pattern, and/or another destination. performing these common tasks in hardware redu ces cpu load, and thus improves performance. high bandwidth access to data is provided thr ough the system memory interface. the gmch uses tiling architecture to increase system me mory efficiency and t hus maximize effective rendering bandwidth. the intel 855gm/855gme gmch improves 3d performance and quality with 3d zone rendering technology. the intel 855gme gmch also supports video mixer rendering, and bi-cubic filtering.
intel? 855gm/855gme chipset gmch overview r 26 datasheet 2.5 display features the intel 855gm/855gme gmch has four display ports, one analog and three digital. with these interfaces, the gmch can provide support for a progressive scan analog monitor, a dedicated dual channel lvds lcd panel, and two dvo devices. each port can transmit data according to one or more protocols. the data that is sent out the display port is selected from one of the two possible sources, pipe a or pipe b. 2.5.1 gmch analog display port intel 855gm/855gme gmch has an integrated 350 mhz, 24-bit ramdac that can directly drive a progressive scan analog monitor pixel resolution up to 1600x1200 at 85-hz refresh and up to 2048x1536 at 75-hz refresh. the analog display port can be driven by pipe a or pipe b. 2.5.2 gmch integrated lvds port the intel 855gm/855gme gmch have an integrat ed dual channel lfp transmitter interface to support lvds lcd panel resolutions up to uxga th e display pipe provides panel up-scaling to fit a smaller source image onto a specific nativ e panel size, as well as provides panning and centering support. the lvds port is only supported on pipe b. the lvds port can only be driven by pipe b, either independently or simultaneously with the analog display port. spread spectrum clocking is supported: center and down spread support of 0.5%, 1%, and 2.5% utilizing an external ssc clock. 2.5.3 gmch integrated dvo ports the dvo b/c interface is compliant with the dvi specification 1.0. when combined with a dvi compliant external device (e.g. tmds flat panel transmitter, tv-out encoder, etc.), the gmch provides a high-speed interface to a digital or analog display (e.g. fl at panel, tv monitor, etc.). the dvo ports are connected to an external di splay device. examples of this are tv-out encoders, external dacs, lvds transmitters, and tmds transmitters. each display port has control signals that may be used to control, configure and/or determine the capabilities of an external device. the gmch provides two dvo ports that are each capable of driving a 165 mhz pixel clock at the dvo b or dvo c interface. when dvo b and dvo c are combined into a single dvo port, then an effective pixel rate of 330 mhz can be achieved. the dvo b/c ports can be driven by pipe a or pipe b. if driven on pipe b, then the lvds port must be disabled. 2.6 intel ? 855gme gmch agp interface the intel 855gme has support for a single agp co mponent is supported by the agp interface. the agp buffers operate only in 1.5 v mode. they are not 3.3 v tolerant. the agp interface supports 1x/2x/4x agp signa ling and 2x/4x fast writes. agp semantic cycles to ddr sdram are not snooped on the host bus. pci semantic cycles to ddr sdram are snooped on the host bus. the gmch/mch support pipe# or sba[7:0] agp address mechanisms, but not both simultaneously. either the pipe# or the sba[7:0] mechanism must be
intel? 855gm/855gme chipset gmch overview r datasheet 27 selected during system initialization. both upstream and downstream addressing is limited to 32- bits for agp and agp/pci transactions. the gmch/mch contains a 32-deep agp request queue. high priority accesses are supported. a ll accesses from the agp/pci interface that fall within the graphics aperture address range pass through an address translation mechanism with a fully associative 20 entry tlb. accesses between agp and hub interface are limited to memory writes originating from the hub interface destined for agp. the agp interface is clocked from a dedicated 66 mhz clock (glckin). the agp -to-host/core interface is asynchronous. the agp interface should be powered-off or tri- stated without voltage on the interface during acpi s3 or apm suspend to ram state. refer to the agp busy and stop signal s specification for more information. 2.7 hub interface a proprietary interconnect connects the gmch to the ich4-m. all communication between the gmch and the ich4-m occurs over the hub in terface 1.5. the hub interface runs at 66 mhz (266-mb/s). 2.8 address decode policies host initiated i/o cycles are positively dec oded to the gmch configuration space and subtractively decoded to hub interface. host initiated system memory cycles are positively decoded to ddr sdram and are again subtrac tively decoded to hub interface if under 4 gb. system memory accesses from hub interface to ddr sdram will be snooped on the fsb. 2.9 gmch clocking the gmch has the following clock input/output pins: ? 400 mhz, spread spectrum, low voltage differential bclk, bclk# for front side bus (fsb) ? 66 mhz, 3.3 v gclkin for hub interface buffers ? six pairs of differential output clocks (sck[5:0], sck[5:0]#), 200/266 mhz, 2.5 v for system memory interface ? 48 mhz, non-spread spectrum, 3.3 v drefclk for the display frequency synthesis ? 48 mhz or 66 mhz, spread spectrum, 3. 3 v drefssclk for the display frequency synthesis ? up to 85 mhz, 1.5 v dvobcclkint for tv-out mode ? dpms clock for s1-m clock synthesizer chips are responsible for generating the system host clocks, gmch display clocks, hub interface clocks, pci clocks, sio clocks, and fwh cloc ks. the host target speed is 400 mhz. the gmch does not require any relationship between the bclk host clock and the 66 mhz clock generated for hub interface; they are asynchronous to each other. the hub interface runs at a constant 66 mhz base fre quency. table 2 indicat es the frequency ratios between the various interfaces that the gmch supports.
intel? 855gm/855gme chipset gmch overview r 28 datasheet table 2. intel ? 855gm/855gme gmch interface clocks interface clock speed cpu system bus frequency ratio samples per clock data rate (mega- samples/s) data width (bytes) peak bandwidth (mb/s) cpu bus 100 mhz reference 4 400 8 3200 100 mhz 1:1 synchronous 2 200 8 1600 133 mhz 1:1 synchronous 2 266 8 2128 ddr sdram 166 mhz 1:1 synchronous 2 333 8 2664 lvds flat panel 35 mhz-112 mhz (single channel) asynchronous 1 112 2.25 252 dvo b or dvo c up to 165 mhz asynchronous 2 330 1.5 495 dvo b+dvo c up to 330 mhz asynchronous 2 660 3 1980 dac interface 350 mhz asynchronous 1 350 3 1050 2.10 system interrupts the gmch supports both the legacy intel 8259 programmable interrupt delivery mechanism and the intel pentium m processor and intel celeron m processor fsb interrupt delivery mechanism. the serial apic interrupt mechanism is not supported. the intel 8259 interrupt delivery mechanism support consists of flushing in bound hub interface write buffers when an interrupt acknowledge cycle is forwarded from the system bus to the hub interface. pci msi interrupts are generated as memory writes. the gmch decodes upstream memory writes to the range 0fee0_0000h - 0feef_ffffh from the hub interface as message based interrupts. the gmch forwards the memory writes along with the associated write data to the system bus as an interrupt message transaction. since this address does not decode as part of main system memory, the write cycle and the write data do not get forwarded to system memory via the write buffer. the gmch provides the re sponse and htrdy# for all interrupt message cycles including the ones originating from the gmch. the gmch also supports interrupt redirection for upstream interrupt memory writes. for message based interrupts, syst em write buffer coherency is maintained by relying on strict ordering of memory writes. the gmch ensures that all memory writes received from a given interface prior to an interrupt message memory wr ite are delivered to the system bus for snooping in the same order that they occur on the given interface.
signal descriptions r datasheet 29 3 signal descriptions this section describes the gmch signals. th ese signals are arranged in functional groups according to their associated in terface. the following notations ar e used to describe the signal type: i input pin o output pin i/o bi-directional input/output pin the signal description also includes the type of buffer used for the particular signal: agtl+ open drain agtl+ interface signal. refer to the agtl+ i/o specification for complete details. the gmch integrates agtl+ termination resistors, and supports vttlf of 1.05 v 5%. agtl+ signals are ?inverted bus? style where a low voltage represents a logical 1. dvo dvo buffers (1.5 v tolerant) hub compatible to hub interface 1.5 sstl_2 stub series termination logic compatible signals (2.5 v tolerant) lvttl low voltage ttl compatible signals (3.3 v tolerant) cmos cmos buffers (3.3 v tolerant) lvds low voltage differential signal interface analog analog signal interface ref voltage reference signal system address and data bus signals are logically inverted signals. in other words, the actual values are inverted of what appears on the system bus. this must be taken into account and the addresses and data bus signals must be inverted inside the gmch. all processor control signals follow normal convention: a 0 indicates an active level (low voltage), and a 1 indicates an active level (high voltage).
signal descriptions r 30 datasheet 3.1 host interface signals table 3. host interface signal descriptions signal name type description ads# i/o agtl+ address strobe: the system bus owner asserts ads# to indicate the first of two cycles of a request phase. the gmch can assert this signal for snoop cycles and interrupt messages. bnr# i/o agtl+ block next request: used to block the current request bus owner from issuing a new request. this signal is used to dynamica lly control the cpu bus pipeline depth. bpri# o agtl+ bus priority request: the gmch is the only priority agent on the system bus. it asserts this signal to obtain the ownership of the address bus. this signal has priority over symmetric bus requests and will caus e the current symmetric owner to stop issuing new transactions unless the hlock# signal was asserted. breq0# i/o agtl+ bus request 0#: the gmch pulls the processor bus breq0 # signal low during cpurst#. the signal is sampled by the processo r on the active-to-inactive transition of cpurst#. the minimum setup time for th is signal is 4 bclks. the minimum hold time is 2 clocks and the maximum hold time is 20 bclks. breq0# should be tristated after the hold time requirement has been satisfied. during regular operation, the gmch will us e breq0# as an early indication for fsb address and ctl input buffer and sense amp activation. cpurst# o agtl+ cpu reset: the cpurst# pin is an output from the gmch. the gmch asserts cpurst# while reset# (pcirst# from ich4-m) is asserted and for approximately 1 ms after reset# is deasserted. the cpurst # allows the processor to begin execution in a known state. note that the ich4-m must provide cpu strap set-up and hold-times around cpurst#. this requires strict sy nchronization between gmch, cpurst# deassertion and ich4-m driving the straps. dbsy# i/o agtl+ data bus busy: used by the data bus owner to hold the data bus for transfers requiring more than one cycle. defer# o agtl+ defer: gmch will generate a deferred response as defined by the rules of the gmch?s dynamic defer policy. the gmch will also us e the defer# signal to indicate a cpu retry response. dinv[3:0]# i/o agtl+ dynamic bus inversion: driven along with the hd[63:0]# signals. indicates if the associated signals are inverted or not. dinv[3 :0]# are asserted such that the number of data bits driven electrically low (low voltage) within the corresponding 16-bit group never exceeds 8. dinv# data bits dinv[3]# hd[63:48]# dinv[2]# hd[47:32]# dinv[1]# hd[31:16]# dinv[0]# hd[16:0]# dpslp# i cmos deep sleep #: this signal comes from the ich4-m device, providing an indication of c3 and c4 state control to the cpu. deasse rtion of this signal is used as an early indication for c3 and c4 wake up (to active hpll). note that this is a low-voltage cmos buffer operating on the fsb vtt power plane.
signal descriptions r datasheet 31 signal name type description drdy# i/o agtl+ data ready: asserted for each cycle that data is transferred. ha[31:3]# i/o agtl+ host address bus: ha[31:3]# connects to the cp u address bus. during processor cycles the ha[31:3]# are inputs. the gm ch drives ha[31:3]# during snoop cycles on behalf of hub interface. ha[31:3]# are transferred at 2x rate. note that the address is inverted on the cpu bus. hadstb[1:0]# i/o agtl+ host address strobe: ha[31:3]# connects to the cpu address bus. during cpu cycles, the source synchronous strobes are used to transfer ha[31:3]# and hreq[4:0]# at the 2x transfer rate. strobe address bits hadstb[0]# ha[16:3]#, hreq[4:0]# hadstb[1]# ha[31:17]# hd[63:0]# i/o agtl+ host data: these signals are connected to the cpu data bus. hd[63:0]# are transferred at 4x rate. note that the data signals are inverted on the cpu bus. hdstbp[3:0]# hdstbn[3:0]# i/o agtl+ differential host data strobes: the differential source synchronous strobes are used to transfer hd[63:0]# and dinv[3:0]# at the 4x transfer rate. strobe data bits hdstbp[3]#, hdstbn[3]# hd[63:48]#, dinv[3]# hdstbp[2]#, hdstbn[2]# hd[47:32]#, dinv[2]# hdstbp[1]#, hdstbn[1]# hd[31:16]#, dinv[1]# hdstbp[0]#, hdstbn[0]# hd[15:0]#, dinv[0]# hit# i/o agtl+ hit: indicates that a caching agent holds an unmodified version of the requested line. also, driven in conjunction with hitm# by the target to extend the snoop window. hitm# i/o agtl+ hit modified: indicates that a caching agent holds a modified version of the requested line and that this agent assumes responsibility for providing the line. also, driven in conjunction with hit# to extend the snoop window. hlock# i/o agtl+ host lock: all cpu bus cycles sampled with the assertion of hlock# and ads#, until the negation of hlock# must be atomic, i.e. no hub interface snoopable access to system memory is allowed when hlock# is asserted by the cpu. hreq[4:0]# i/o agtl+ host request command: defines the attributes of the request. hreq[4:0]# are transferred at 2x rate. asserted by the requesting agent during both halves of the request phase. in the first half the signals define the transaction type to a level of detail that is sufficient to begin a snoop request. in the second half the signals carry additional information to define the complete transaction type. the transactions supported by the gmch host bridge are defined in the host interface section of this document. htrdy# o agtl+ host target ready: indicates that the target of the processor transaction is able to enter the data transfer phase.
signal descriptions r 32 datasheet signal name type description rs[2:0]# o agtl+ response status: indicates the type of response according to the following the table: rs[2:0]# response type 000 idle state 001 retry response 010 deferred response 011 reserved (not driven by gmch) 100 hard failure (not driven by gmch) 101 no data response 110 implicit write back 111 normal data response 3.2 ddr sdram interface table 4. ddr sdram interface descriptions signal name type description scs[3:0]# o sstl_2 chip select: these pins select the particular ddr sdram components during the active state. note: there is one scs# per ddr-sdram ph ysical so-dimm device row. these signals can be toggled on every rising sy stem memory clock edge (scmdclk). sma[12:0] o sstl_2 multiplexed memory address: these signals are used to provide the multiplexed row and column address to the ddr sdram. sba[1:0] o sstl_2 bank select (memory bank address): these signals define which banks are selected within each ddr sdram row. the sma and sba signals combine to address every possible location within a ddr sdram device. sras# o sstl_2 ddr row address strobe: sras# may be heavily loaded and requires tw0 ddr sdram clock cycles for setup time to the ddr sdrams. used with scas# and swe# (along with scs#) to define the system memory commands. scas# o sstl_2 ddr column address strobe: scas# may be heavily loaded and requires two clock cycles for setup time to the ddr sdrams . used with sras# and swe# (along with scs#) to define the system memory commands. swe# o sstl_2 write enable: used with scas# and sras# (along with scs#) to define the ddr sdram commands. swe# is asserted duri ng writes to ddr sdram. swe# may be heavily loaded and requires two clock cycles for setup time to the ddr sdrams. sdq[71:0] i/o sstl_2 data lines: these signals are used to interface to the ddr sdram data bus. note: ecc error detection is supported: by the sdq[71:64] signals.
signal descriptions r datasheet 33 signal name type description sdqs[8:0] i/o sstl_2 data strobes: data strobes are used for capturi ng data. during writes, sdqs is centered on data. during reads, sdqs is edge aligned with data. the following list matches the data strobe with the data bytes. there is an associated data strobe (dqs) fo r each data signal (dq) and check bit (cb) group. sdqs[7] -> sdq[63:56] sdqs[6] -> sdq[55:48] sdqs[5] -> sdq[47:40] sdqs[4] -> sdq[39:32] sdqs[3] -> sdq[31:24] sdqs[2] -> sdq[23:16] sdqs[1] -> sdq[15:8] sdqs[0] -> sdq[7:0] note: ecc error detection is suppor ted by the sdqs[8] signal. scke[3:0] o sstl_2 clock enable: these pins are used to signal a self-refresh or power down command to the ddr sdram array when entering system suspend. scke is also used to dynamically power down inactive ddr sdram rows. there is one scke per ddr sdram row. these signals can be toggled on every rising sck edge. smab[5,4,2,1] o sstl_2 memory address copies: these signals are identical to sma[5,4,2,1] and are used to reduce loading for selective cpc(clock-per-c ommand). these copies are not inverted. sdm[8:0] o sstl_2 data mask: when activated during writes, the corresponding data groups in the ddr sdram are masked. there is one sdm fo r every eight data lines. sdm can be sampled on both edges of the data strobes. note: ecc error detection is supported by the sdm[8] signal. rcvenout# o sstl_2 clock output: reserved, nc. rcvenin# o sstl_2 clock input: reserved, nc.
signal descriptions r 34 datasheet 3.3 agp interface signals note: agp interface is only supported on the intel 85 5gme gmch. unless otherwise specified, the voltage level for all signals in this interface is 1.5 volts. 3.3.1 agp addressing signals table 5. agp addressing signal descriptions signal name type description gpipe# i agp pipelined read: this signal is asserted by the agp master to indicate a full width address is to be enqueued on by the target using the ad bus. one address is placed in the agp request queue on each rising clock edge while pipe# is asserted. when pipe # is deasserted no new requests are queued across the ad bus. during sba operation: this signal is not used if sba (side band addressing) is selected. during frame# operation: this signal is not used during agp frame# operation. pipe# is a sustained tri-state signal from ma sters (graphics controller), and is an input to the gmch. gsba[7:0] i agp side-band address: these signals are used by the ag p master (graphics controller) to pass address and command to the gmch. the sba bus and ad bus operate independently. that is, transac tions can proceed on the sba bus and the ad bus simultaneously. during pipe# operation: these signals are not used during pipe# operation. during frame# operation: these signals are not used during agp frame# operation. note: when sideband addressing is disabled, these signals are isolated (no external/internal pu ll-ups are required). section 5 contains two mechanisms to queue reque sts by the agp master. note that the master can only use one mechanism. the master may not switch methods without a full reset of the system. when pipe# is used to queue addresses the master is not allowed to queue addresses using the sba bus. for example, during configuration time, if the master indicates that it can use either mechanism, the configuration software will indicate which mechanism the master will use. once this choice has been made, the master will continue to use the mechanism selected until the master is reset (and reprogrammed) to use the othe r mode. this change of modes is not a dynamic mechanism, but rather a static decision when th e device is first being configured after reset.
signal descriptions r datasheet 35 3.3.2 agp flow control signals table 6. agp flow control signals signal name type description grbf# i agp read buffer full: read buffer full indicates if the master is ready to accept previously requested low priority read data. when rbf# is asserted the gmch is not allowed to initiate the return low priority read data. that is, the gmch can finish returning the data for the request currently being serviced. rbf# is only sampled at the beginning of a cycle. if the agp master is always ready to accept return read data then it is not required to implement this signal. during frame# operation: this signal is not used during agp frame# operation. gwbf# i agp write-buffer full: indicates if the master is ready to accept fast write data from the gmch. when wbf# is asserted the gmch is not allowed to drive fast write data to the agp master. wbf# is only sampled at the beginning of a cycle. if the agp master is always ready to accept fast write data then it is not required to implement this signal. during frame# operation: this signal is not used during agp frame# operation. 3.3.3 agp status signals table 7. agp status signal descriptions signal name type description st[2:0 meaning 000 previously requested low priority read data is being returned to the master 001 previously requested high priority read data is being returned to the master 010 the master is to provide low priority write data for a previously queued write command 011 the master is to provide high priority write data for a previously queued write command. 100 reserved 101 reserved 110 reserved gst[2:0] o agp status: provides information from the arbiter to an agp master on what it may do. st[2:0] only have meaning to the master when its gnt# is asserted. when gnt# is deasserted these signals have no meaning and must be ignored. 110 the master has been given permission to start a bus transaction. the master may queue agp requests by asserting pipe# or start a pci transaction by asserting frame# .
signal descriptions r 36 datasheet 3.3.4 agp strobes table 8. agp strobe descriptions signal name type description gadstb[0] i/o agp address/data bus strobe-0: provides timing for 2x and 4x data on ad[15:0] and c/be[1:0]# signals. the agent that is provid ing the data will drive this signal. gadstb#[0] i/o agp address/data bus strobe-0 complement: with ad stb0, forms a differential strobe pair that provides timi ng information for the ad[15:0] and c/be[1:0]# signals. the agent that is providing the data will drive this signal. gadstb[1] i/o agp address/data bus strobe-1: provides timing for 2x and 4x data on ad[31:16] and c/be[3:2]# signals. the agent that is provid ing the data will drive this signal. gadstb#[1] i/o agp address/data bus strobe-1 complement: with ad stb1, forms a differential strobe pair that provides timing in formation for the ad[15:0] and c/be[1:0]# signals in 4x mode. the agent that is providing the data will drive this signal. gsbstb i agp sideband strobe: provides timing for 2x and 4x data on the sba[7:0] bus. it is driven by the agp master after the system has been configured for 2x or 4x sideband address mode. gsbstb# i agp sideband strobe complement: the differential complement to the sb_stb signal. it is used to provide timing 4x mode. 3.3.5 agp/pci signals-semantics for transactions on the agp interface carried usi ng agp frame# protocol these signals operate similarly to their semantics in the pci 2.1 specification, as defined below. table 9. agp/pci signals-semantics descriptions signal name type description gframe# i/o agp g_frame: frame. during pipe# and sba operation: not used by agp sba and pipe# operations. during fast write operation: used to frame transactions as an output during fast writes. during frame# operation: g_frame# is an output when the gmch acts as an initiator on the agp interface. g_frame# is asserted by the gmch to indicate the beginning and duration of an access. g_frame# is an input when the gmch acts as a frame#-based agp target. as a fram e#-based agp target, the gmch latches the c/be[3:0]# and the ad[31:0] signals on the first clock edge on which gmch samples frame# active.
signal descriptions r datasheet 37 signal name type description girdy# i/o agp g_irdy#: initiator ready. during pipe# and sba operation: not used while enqueueing requests via agp sba and pipe#, but used during the data phase of pipe# and sba transactions. during frame# operation: g_irdy# is an output when gmch acts as a frame#- based agp initiator and an input when t he gmch acts as a frame#-based agp target. the assertion of g_irdy# indicates the current frame#-based agp bus initiator's ability to complete the current data phase of the transaction. during fast write operation: in fast write mode, g_irdy# indicates that the agp- compliant master is ready to provide all write data for the current transaction. once g_irdy# is asserted for a write operation, the master is not allowed to insert wait states. the master is never allowed to insert a wait state during the initial data transfer (32 bytes) of a write transaction. however, it may insert wait states after each 32-byte block is transferred. gtrdy# i/o agp g_trdy#: target ready. during pipe# and sba operation: not used while enqueueing requests via agp sba and pipe#, but used during the data phase of pipe# and sba transactions. during frame# operation: g_trdy# is an input when the gmch acts as an agp initiator and is an output when the gmch acts as a frame#-based agp target. the assertion of g_trdy# indicates the target?s ability to complete the current data phase of the transaction. during fast write operation: in fast write mode, g_trdy# indicates the agp- compliant target is ready to receive write data for the entire transaction (when the transfer size is less than or equal to 32 bytes) or is ready to transfer the initial or subsequent block (32 bytes) of data when the transfer size is greater than 32 bytes. the target is allowed to insert wait states after each block (32 bytes) is transferred on write transactions. gstop# i/o agp g_stop#: stop. during pipe# and sba operation: this signal is not used during pipe# or sba operation. during frame# operation: g_stop# is an input when the gmch acts as a frame#-based agp initiator and is an out put when the gmch acts as a frame#- based agp target. g_stop# is used fo r disconnect, retry, and abort sequences on the agp interface. gdevsel# i/o agp g_ devsel#: device select. during pipe# and sba operation: this signal is not used during pipe# or sba operation. during frame# operation: g_devsel#, when asserted, indicates that a frame#- based agp target device has decoded its address as the target of the current access. the gmch asserts g_devsel# based on the ddr sdram address range being accessed by a pci initiator. as an input, g_devsel# indicates whether the agp master has recognized a pci cycle to it. greq# i agp g_req#: request. during sba operation: this signal is not used during sba operation. during pipe# and frame# operation: g_req#, when asserted, indicates that the agp master is requesting use of the agp in terface to run a frame#- or pipe#-based operation.
signal descriptions r 38 datasheet signal name type description ggnt# o agp g_gnt#: grant. during sba, pipe# and frame# operation: g_gnt#, along with the information on the st[2:0] signals (status bus), indicates how the agp interface will be used next. refer to the agp interface specification, revision 2.0 for further explanation of the st[2:0] values and their meanings. gad[31:0] i/o agp g_ad[31:0]: address/data bus. during pipe# and frame# operation: the g_ad[31:0] signals are used to transfer both address and data information on the agp interface. during sba operation: the g_ad[31:0] signals are used to transfer data on the agp interface. gcbe#[3:0] i/o agp command/byte enable. during frame# operation: during the address phase of a transaction, the g_cbe[3:0]# signals define the bus command. during the data phase, the g_cbe[3:0]# signals are used as byte enables. the byte enables determine which byte lanes carry meaningful data. t he commands issued on the g_cbe# signals during frame#-based agp transactions ar e the same g_cbe# command described in the pci 2.2 specification. during pipe# operation: when an address is enqueued using pipe#, the c/be# signals carry command information. t he command encoding used during pipe#-based agp is different than the command encoding used during frame#-based agp cycles (or standard pci cycles on a pci bus). during sba operation: these signals are not used during sba operation. gpar i/o agp parity. during frame# operation: g_par is driven by the gmch when it acts as a frame#-based agp initiator during address and data phases for a write cycle, and during the address phase for a read cycle. g_ par is driven by the gmch when it acts as a frame#-based agp target during each data phase of a frame#-based agp memory read cycle. even parity is generated across g_ad[31:0] and g_cbe[3:0]#. during sba and pipe# operation: this signal is not used during sba and pipe# operation. pcirst# from the ich4-m is assumed to be conn ected to rstin# and is used to reset agp interface logic within the gmch . the agp agent will also typi cally use pcirst# provided by the ich4-m as an input to reset its internal logic.
signal descriptions r datasheet 39 3.4 hub interface signals table 10. hub interface signals signal name type description hl[10:0] i/o hub packet data: data signals used for hi read and write operations. hlstb i/o hub packet strobe: one of two differential strobe si gnals used to transmit or receive packet data over hi. hlstb# i/o hub packet strobe complement : one of two differential strobe signals used to transmit or receive packet data over hi. 3.5 clocks table 11. clock signals signal name type description host processor clocking bclk bclk# i cmos differential host clock in: these pins receive a buffered host clock from the external clock synthesizer. this clock is used by all of the gmch logic that are in the host clock domain (host, hub and system memory). the clock is also the reference clock for the graphics core pll. this is a low voltage differential input. system memory clocking sck[5:0] o sstl_2 differential ddr sdram clock: sck and sck# pairs are differential clock outputs. the crossing of the positive edge of sck and the negative edge of sck# is used to sample the address and control signals on the ddr sdram. there are 3 pairs to each so-dimm. note: ecc error detection is supported by the sck[2] and sck[5] signals. sck[5:0]# o sstl_2 complementary differential ddr sdram clock: these are the complimentary differential ddr sdram clock signals. note: ecc error detection is supported by the sck[2]# and sck[5]# signals. dvo/hub input clocking gclkin i cmos input clock: 66 mhz, 3.3 v input clock from external buffer dvo/hub interface. dvo clocking dvobclk dvobclk# o dvo differential dvo clock output: these pins provide a di fferential pair reference clock that can run up to 165 mhz. dvobclk corresponds to the primary clock out. dvobclk# corresponds to the primary complementary clock out. dvobclk and dvobclk# should be left as nc (?not connected?) if the dvo b port is not implemented.
signal descriptions r 40 datasheet signal name type description dvocclk dvocclk# o dvo differential dvo clock output : these pins provide a di fferential pair reference clock that can run up to 165 mhz. dvocclk corresponds to the primary clock out. dvocclk# corresponds to the primary complementary clock out. dvocclk and dvocclk# should be left as nc (?not connected?) if the dvo c port is not implemented. dvobcclkint i dvo dvobc pixel clock input/interrupt: this signal may be selected as the reference input to either dot clock pll (dpll) or may be configured as an interrupt input. a tv-out device can provide the clock re ference. the maximum input frequency for this signal is 85 mhz. dvobc pixel clock input: when selected as the dot clock pll (dpll) reference input, this clock reference input supports ssc clocking for dvo lvds devices. dvobc interrupt: when configured as an inte rrupt input, this interrupt can support either dvob or dvoc. dvobcclkint needs to be pulled down if the signal is not used. dpms i dvo display power management signaling: this signal is used only in mobile systems to act as the drefclk in certain pow er management states(i.e. display power down mode); dpms clock is used to re fresh video during s1-m. clock chip is powered down in s1-m. dpms should come fr om a clock source that runs during s1-m and needs to be 1.5 v. so, an example would be to use a 1.5 v version of susclk from ich4-m. dac clocking drefclk i lvttl display clock input: this pin is used to provide a 48 mhz input clock to the display pll that is used for 2d/video and dac. lvds lcd flat panel clocking drefssclk i lvttl display ssc clock input: this pin provides a 48 mhz or 66 mhz input clock (ssc or non-ssc) to the display pll b.
signal descriptions r datasheet 41 3.6 internal graphics display signals the igd has support for a dedicated lvds lcd fl at panel interface, dvob/c interfaces, and an analog crt port. 3.6.1 dedicated lvds lcd flat panel interface table 12. dedicated lvds lcd flat panel interface signal descriptions name type voltage description iclkap o lvds 1.25 v 225 mv channel a differential clock pair output (true): 245?800 mhz iclkam o lvds 1.25 v 225 mv channel a differential clock pair output (compliment): 245? 800 mhz. iyap[3:0] o lvds 1.25 v 225 mv channel a differential data pair 3:0 output (true): 245?800 mhz. iyam[3:0] o lvds 1.25 v 225 mv channel a differential data pair 3:0 output (compliment): 245? 800 mhz. iclkbp o lvds 1.25 v 225 mv channel b differential clock pair output (true): 245?800 mhz. iclkbm o lvds 1.25 v 225 mv channel b differential clock pair output (compliment): 245? 800 mhz. iybp[3:0] o lvds 1.25 v 225 mv channel b differential data pair 3:0 output (true): 245?800 mhz. iybm[3:0] o lvds 1.25 v 225 mv channel b differential data pair 3:0 output (compliment): 245? 800 mhz.
signal descriptions r 42 datasheet 3.6.2 digital video output b (dvob) port table 13. digital video output b (dvob) port signal descriptions name type description dvobd[11:0] o dvo dvob data: this data bus is used to driv e 12-bit rgb data on each edge of the differential clock signals, dvobclk and dvobcl k#. this provides 24-bits of data per clock period. in dual channel mode, this pr ovides the lower 12-bits of pixel data. dvobd[11:0] should be left as left as nc (?not connected?) if not used. dvobhsync o dvo horizontal sync : hsync signal for the dvob interface. dvobhsync should be left as left as nc (?not connected?) if not used. dvobvsync o dvo vertical sync : vsync signal for the dvob interface. dvobvsync should be left as left as nc (?not connected?) if the signal is not used when using internal graphics device. dvobblank# o dvo flicker blank or border period indication: dvobblank# is a programmable output pin driven by the gmch. when programmed as a blank peri od indication, this pin indica tes active pixels excluding the border. when programmed as a border period i ndication, this pin indicates active pixel including the border pixels. dvobblank# should be left as left as nc (?not connected?) if not used. dvobfldstl i dvo tv field and flat panel stall signal . this input can be programmed to be either a tv field input from the tv encoder or stall input from the flat panel. dvob tv field signal: when used as a field input, it synchronizes the overlay field with the tv encoder field when the overlay is displaying an interleaved source. dvob flat panel stall signal: when used as the stall input, it indicates that the pixel pipeline should stall one horizontal line. t he signal changes during horizontal blanking. the panel fitting logic, when expanding the image vertically, uses this. dvobfldstl needs to be pulled down if not used. 3.6.3 intel ? 855gme gmch dvo/i 2 c to agp pin mapping the gmch will mux a dvodetect signal with th e gpar signal on the agp bus. this signal will act as a strap and indicate whether the inte rface is in agp or dvo mode. the gmch has an internal 8.2-k pull-up on this signal that will naturally pull it high. if an agp graphics device is present, the signal will be pulle d low at the agp graphics de vice and the agp/dvo mux select bit in the shic register will be set to agp mode. boards that do not use an agp graphics device should have a pull-down resistor on dvodetect if they have dig ital display devices connected to the agp/dvo interface. sba[7:0] will act as straps for an addid. when an agp graphics device is present, dvodetect=1 (agp mode),
signal descriptions r datasheet 43 table 14. intel ? 855gme gmch agp/dvo pin muxing dvo mode agp mode dvo mode agp mode dvo mode agp mode dvobd[0] gad[3] dvocd[0] gad[19] mi2cclk girdy# dvobd[1] gad[2] dvocd[1] gad[20] mi2cdata gdevsel# dvobd[2] gad[5] dvocd[2] gad[21] mdviclk gtrdy# dvobd[3] gad[4] dvocd[3] gad[22] mdvidata gframe# dvobd[4] gad[7] dvocd[4] gad[23] mddccdata gad[15] dvobd[5] gad[6] dvocd[5] gcbe#[3] mddcclk gstop# dvobd[6] gad[8] dvocd[6] gad[25] dvobcint# gad[30] dvobd[7] gcbe#[0] dvocd[7] gad[24] dvobcclkint gad[13] dvobd[8] gad[10] dvocd[8] gad[27] addid[7] gsba[7] dvobd[9] gad[9] dvocd[9] gad[26] addid[6] gsba[6] dvobd[10] gad[12] dvocd[10] gad[29] addid[5] gsba[5] dvobd[11] gad[11] dvocd[11] gad[28] addid[4] gsba[4] dvobclk gadstb[0] dvocclk gadstb[1] addid[3] gsba[3] dvobclk# gadstb#[0] dvocclk# gadstb#[1] addid[2] gsba[2] dvobhsync gad[0] dvochsync gad[17] addid[1] gsba[1] dvobvsync gad[1] dvocvsync gad[16] addid[0] gsba[0] dvobblank# gcbe#[1] dvocblank# gad[18] dvodetect gpar dvobfldstl gad[14] dvocflds tl gad[31] dpms gpipe#
signal descriptions r 44 datasheet 3.6.4 digital video output c (dvoc) port table 15. digital video output c (dvoc) port signal descriptions name type description dvocd[11:0] o dvo dvoc data : this data bus is used to driv e 12-bit rgb data on each edge of the differential clock signals, dvocclk and dvoccl k#. this provides 24-bits of data per clock period. in dual channel mode, this pr ovides the upper 12-bits of pixel data. dvocd[11:0] should be left as left as nc (?not connected?) if not used. dvochsync o dvo horizontal sync : hsync signal for the dvoc interface. dvochsync should be left as left as nc (?not connected?) if not used. dvocvsync o dvo vertical sync : vsync signal for the dvoc interface. dvocvsync should be left as left as nc (?not connected?) if the signal is not used when using internal graphics device. dvocblank# o dvo flicker blank or border period indication : dvocblank# is a programmable output pin driven by the gmch. when programmed as a blank peri od indication, this pin indica tes active pixels excluding the border. when programmed as a border period i ndication, this pin indicates active pixel including the border pixels. dvocblank# should be left as left as nc (?not connected?) if not used. dvocfldstl i dvo tv field and flat panel stall signal . this input can be programmed to be either a tv field input from the tv encoder or stall input from the flat panel. dvoc tv field signal: when used as a field input, it synchronizes the overlay field with the tv encoder field when the overlay is displaying an interleaved source. dvoc flat panel stall signal: when used as t he stall input, it indicates that the pixel pipeline should stall one horizontal line. t he signal changes during horizontal blanking. the panel fitting logic, when expanding the image vertically, uses this. dvocfldstl needs to be pulled down if not used. table 16. dvob and dvoc port common signal descriptions name type description dvobcintr# i dvo dvobc interrupt : this pin is used to signal an interr upt, typically used to indicate a hot plug or unplug of a digital display. addid[7:0] i dvo addid[7:0] : these pins are used to communicate to the video bios when an external device is interfaced to the dvo port. note : bit[7] needs to be strapped low when an on- board dvo device is present. the other pins should be left as nc. dvodetect i dvo dvodetect : this strapping signal indicates to the gmch whether a dvo device is present or not. when a dvo device is connected, then dvodetect = 0.
signal descriptions r datasheet 45 3.6.5 analog crt display table 17. analog crt display signal descriptions pin name type description vsync o cmos crt vertical synchronization : this signal is used as t he vertical sync signal. hsync o cmos crt horizontal synchronization : this signal is used as t he horizontal sync signal. red o analog red (analog video output) : this signal is a crt analog video output from the internal color palette dac. the dac is designed for a 37.5 ? equivalent load on each pin (e.g., 75 ? resistor on the board, in parallel with the 75 ? crt load). red# o analog red# (analog output): tied to ground. green o analog green (analog video output) : this signal is a crt analog video output from the internal color palette dac. the dac is designed for a 37.5 ? equivalent load on each pin (e.g., 75 ? resistor on the board, in parallel with the 75 ? crt load). green# o analog green# (analog output): tied to ground. blue o analog blue (analog video output) : this signal is a crt analog video output from the internal color palette dac. the dac is designed for a 37.5 ? equivalent load on each pin (e.g., 75 ? resistor on the board, in parallel with the 75 ? crt load). blue# o analog blue# (analog output): tied to ground.
signal descriptions r 46 datasheet 3.6.6 general purpose input/output signals table 18. gpio signal descriptions gpio i/f total type comments rstin# i cmos reset: primary reset, connected to pcirst# of ich4-m. pwrok i cmos power ok : indicates that power to gmch is stable. agpbusy# o cmos agpbusy: output of the gmch igd to the ich4-m, which indicates that certain graphics activity is taking place. it will indicate to the ac pi software not to enter the c3 state. it will also cause a c3/c4 exit if c3/c4 was being entered, or was already entered when agpbusy# went active. not active when the igd is in any acpi state other than d0. extts_0 i cmos external thermal sensor input: this signal is an active low i nput to the gmch and is used to monitor the thermal condition around the system memory and is used for triggering a read throttle. the gmch can be optionally programm ed to send a serr, sci, or smi message to the ich4-m upon the triggering of this signal. lclkctla o cmos ssc chip clock control: can be used to control an external clock chip with ssc control. lclkctlb o cmos ssc chip data control: can be used to control an external clock chip for ssc control. panelvdden o cmos lvds lcd flat panel power control: this signal is used enable pow er to the panel interface. panelbklten o cmos lvds lcd flat panel backlight enable: this signal is used to enable the backlight inverter (bli). panelbkltctl o cmos lvds lcd flat panel backlight brightness control: this signal is used as the pulse width modulated (pwm) control signal to control the backlight inverter. ddcaclk i/o cmos crt ddc clock: this signal is used as the ddc cl ock signal between the crt monitor and the gmch. ddcadata i/o cmos crt ddc data: this signal is used as the ddc data signal between the crt monitor and the gmch. ddcpclk i/o cmos panel ddc clock: this signal is used as the ddc clock signal between the lfp and the gmch. ddcpdata i/o cmos panel ddc data: this signal is used as the ddc dat a signal between the lfp and the gmch. mi2cclk i/o dvo dvo i2c clock: this signal is used as the i2c_clk for a digital display (i.e. tv-out encoder, tmds transmitter). this signal is tri-stated during a hard reset. mi2cdata i/o dvo dvo i2c data: this signal is used as the i2c_data fo r a digital display (i.e. tv-out encoder, tmds transmitter). this signal is tri-stated during a hard reset.
signal descriptions r datasheet 47 gpio i/f total type comments mdviclk i/o dvo dvi ddc clock: this signal is used as the ddc clock for a digital display connector (i.e. primary digital monitor). this signal is tri-stated during a hard reset. mdvidata i/o dvo dvi ddc data: the signal is used as the ddc data for a digital display connector (i.e. primary digital monitor). this signal is tri-stated during a hard reset. mddcdata i/o dvo dvi ddc clock: the signal is used as the ddc data fo r a digital display connector (i.e. secondary digital monitor). this signal is tri-stated during a hard reset. mddcclk i/o dvo dvi ddc data: the signal is used as the ddc clock for a digital display connector (i.e. secondary digital monitor). this signal is tri-stated during a hard reset.
signal descriptions r 48 datasheet 3.7 voltage references, pll power table 19. voltage references, pll power signal name type description host processor hxrcomp analog host rcomp: used to calibrate the host agtl+ i/o buffers. hyrcomp analog host rcomp: used to calibrate the host agtl+ i/o buffers. hxswing analog host voltage swing (rco mp reference voltage): these signals provide a reference voltage used by the fsb rcomp circuit. hyswing analog host voltage swing (rcomp reference voltage) : these signals provide a reference voltage used by the fsb rcomp circuit. hdvref[2:0] ref analog host data (input buffer) vref : reference voltage input for the data signals of the host agtl+ interface. input buffer differential amplifier to determine a high versus low input voltage. havref ref analog host address (input buffer) vref : reference voltage input for the address signals of the host agtl+ interface. this signal is connected to the input buffer differential amplifier to determine a high versus low input voltage. hccvref ref analog host common clock (command input buffer) vref : reference voltage input for the common clock signals of the host agtl+ in terface. this signal is connected to the input buffer differential amplifier to determine a high versus low input voltage. vttlf power fsb power supply: vttlf is the low frequency connection from the board. this signal is the primary connection of power for gmch. vtthf power fsb power supply: vtthf is the high frequency supply. it is for direct connection from an internal package plane to a capacit or placed immediately adjacent to the gmch. note: not to be connected to power rail. system memory smrcomp analog system memory rcomp : this signal is used to calibrate the memory i/o buffers. smvref_0 ref analog memory reference voltage (input buffer vref) :reference voltage input for memory interface. input buffer differential amplifier to determine a high versus low input voltage. smvswingh ref analog rcomp reference voltage: this is connected to the rcomp buffer differential amplifier and is used to calibrate the i/o buffers. smvswingl ref analog rcomp reference voltage : this is connected to the rcomp buffer differential amplifier and is used to calibrate the i/o buffers. vccsm power power supply for memory i/o. vccqsm power power supply for system memory clock buffers. vccasm power power supply for system memory logic r unning at the core voltage (isolated supply, not connected to the core). hub interface hlrcomp analog hub interface rcomp : this signal is connected to a re ference resistor in order to calibrate the buffers.
signal descriptions r datasheet 49 signal name type description pswing analog rcomp reference voltage : this is connected to the rcomp buffer differential amplifier and is used to calibrate the buffers. hlvref ref analog input buffer vref : input buffer differential amplifier to determine a high versus low input voltage. vcchl power power supply for hub interface buffers dvo dvorcomp analog analog compensation for dvo : this signal is used to calibrate the dvo i/o buffers. gvref ref analog input buffer vref : input buffer differential amplifier to determine a high versus low input voltage. vccdvo power power supply for dvo. gpio vccgpio power power supply for gpio buffers dac refset ref analog resistor set: set point resistor for the internal color palette dac. vccadac power power supply for the dac vssadac power ground supply for the dac lvds libg analog lvds reference current: signal connected to reference resistor. vccdlvds power digital power supply. vcctxlvds power data/clk tx power supply. vccalvds power analog power supply. vssalvds power ground supply for lvds. clocks vccahpll power power supply for the host pll. vccagpll power power supply for the hub/dvo pll. vccadplla power power supply for the display pll a. vccadpllb power power supply for the display pll b. core vcc power power supply for the core. vss power ground supply for the chip.
signal descriptions r 50 datasheet
register description r datasheet 51 4 register description 4.1 conceptual overview of the platform configuration structure the intel 855gm gmch and ich4-m are physica lly connected by hub interface. from a configuration standpoi nt, the hub interface is logically pc i bus #0. as a result, all devices internal to the gmch and ich4-m appear to be on pci bus #0. the system?s primary pci expansion bus is physically attached to the ich4 -m and from a configuration perspective, appears to be a hierarchical pci bus behind a pci-to-pci bridge and th erefore has a programmable pci bus number. note that the primary pci bus is referred to as pci_a in this document and is not pci bus #0 from a configuration standpoint. for the intel 855gme gmch, the agp appears to system software to be real pc i bus behind pci-to-pci bridges resi dent as devices on pci bus #0. the gmch contains two pci devices within a single physical component. the configuration registers for the two devices are mapped as devices residing on pci bus #0. device #0: host-hub interface bridge/ddr sdram contro ller. logically this appears as a pci device residing on pci bus #0. physically, device #0 contains the standard pci registers, ddr sdram registers, the graphics aperture controller registers, hi control registers and other gmch specific registers. device #0 is divided into the following functions: function #0: host bridge legacy registers including graphics aperture control registers, hi configuration registers and interrupt control registers function #1: ddr sdram interface registers function #3: intel configuration process registers device #2: integrated graphics controller. logically this appears as a pci device residing on pci bus #0. physically device #2 contains the conf iguration registers for 2d, 3d, and display functions. table 20 shows the device # assignment for the various internal gmch devices. table 20. device number assignment gmch function bus #0, device# host-hub interface, ddr sdram i/f, legacy control device #0 host-to-agp bridge (virtual pci-to-pci) device #1 (intel 855gme gmch only) integrated graphics controller (igd) device #2
register description r 52 datasheet 4.2 nomenclature for access attributes table 21 provides the nomenclat ure for the access attributes. table 21. nomenclature for access attributes ro read only . if a register is read only, writes to this register have no effect. r/w read/write . a register with this attribute can be read and written. r/w/l read/write/lock . a register with this attribute can be read, written, and locked. r/wc read/write clear . a register bit with this attribute can be read and written. however, a write of a 1 clears (sets to 0) the corresponding bit and a write of a 0 has no effect. r/wo read/write once . a register bit with this attri bute can be written to only once after power up. after the first write, this bit becomes read only. l lock . a register bit with this attribute bec omes read only after a lock bit is set. reserved bits some of the gmch registers descri bed in this section contain reserved bits. these bits are labeled "reserved?. software must deal correctly with fields that are reserved. on reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being of any particular value. on writes, software must ensure that the values of reserved bi t positions are preserved. that is, the values of reserved bit positions must firs t be read, merged with the new values for other bit positions and then written back. note the software does not need to perform read, merge, and write operations for the configuration address register. reserved registers in addition to reserved bits with in a register, the gmch contains address locations in the configuration space of the host-h ub interface bridge entity that are marked either "reserved" or ?intel reserv ed?. the gmch responds to accesses to ?reserved? address locations by completi ng the host cycle. when a ?reserved? register location is read, in certain case s, a zero value can be returned (?reserved? registers can be 8-bit, 16-bit, or 32-bit in size) or a non-zero value can be returned. in certain cases, writes to ?reserved? registers may have no effect on the gmch or may cause system failure. registers that are marked as ?intel reserved? must not be modified by system software. default value upon a reset upon reset, the gmch sets all of its in ternal configuration registers to predetermined default states. some register values at reset are determined by external strapping options. the default st ate represents the minimum functionality feature set required to successfully br ing up the system. hence, it does not represent the optimal system configurati on. it is the responsibility of the system initialization software (usually bios) to properly determine the ddr sdram configurations, operating parameters and optional system features that are applicable, and to program the gmch registers accordingly. s sw semaphore. a physical pci bus #0 does not exist. the hub in terface and the internal devices in the gmch and ich4-m logically constitute pci bus #0 to configuration software
register description r datasheet 53 4.3 standard pci bus configuration mechanism the pci bus defines a slot base d ?configuration space? that allows each device to contain up to eight functions with each functio n containing up to 256, 8-bit conf iguration registers. the pci specification defines two bus cycles to access the pci confi guration space: conf iguration read and configuration write. memo ry and i/o spaces are supporte d directly by the cpu. configuration space is supported by a mapping mechanism implem ented within the gmch. the pci 2.2 specification defines two mechanisms to access configuration space: mechanism #1 and mechanism #2. the gmch supports only mechanism #1. the configuration access mechanism makes us e of the config_address register (at i/o address 0cf8h though 0cfbh) and config_data register (a t i/o address 0cfch though 0cffh). to reference a configura tion register a dword i/o write cycle is used to place a value into config_address that specifies the pci bus, the device on that bus, the function within the device, and a specific conf iguration register of the device function being accessed. config_address[31] must be a 1 to enable a configuration cycle. config_data then becomes a window into the four bytes of conf iguration space specified by the contents of config_address. any read or write to config_data will result in the gmch translating the config_address into the appropriate configuration cycle. the gmch is responsible for translating and routing the cpu?s i/o accesses to the config_address and config_data registers to internal gmch configuration registers and to the hub interface, or agp_pci_b. 4.4 routing configuration accesses the gmch supports one bus interface: the h ub interface. pci confi guration cycles are selectively routed to this in terface. the gmch is responsible for routing pci configuration cycles to the proper interface. pci configurati on cycles to the ich4-m internal devices, and primary pci (including downstream devices) are r outed to the ich4-m via the hub interface. agp/pci_b configuration cycles are routed to agp. the agp/pci_b interface is treated as a separate pci bus from the configuration point of view. routing of configuration agp/pci_b is controlled via the standard pci-to-pci bridge m echanism using information contained within the primary bus number, the secondary bus number, a nd the subordinate bus number registers of the corresponding pci-to-pci bridge device. 4.4.1 pci bus #0 configuration mechanism the gmch decodes the bus number (bits 23: 16) and the device number fields of the config_address register. if the bus number field of config_address is 0, then the configuration cycle is targeting a pci bus #0 device. the host-hub interface bridge en tity within the gmch is hard wired as device #0 on pci bus #0. configuration cycles to any of the gmch?s inte rnal devices are confined to the gmch and not sent over hub interface. accesses to disabled gm ch internal devices will be forwarded over the hub interface as type 0 configuration cycles.
register description r 54 datasheet 4.4.2 primary pci and downstream configuration mechanism if the bus number in the config_address is non-zero, and is less than the value in the host- agp/pci_b device?s secondary bus number register or greater than the value in the host- agp/pci_b device?s subordinate bus number register, the gmch will generate a type 1 hub interface configuration cycle. a[1:0] of the hub interface re quest packet for the type 1 configuration cycle will be ?01?. this hub inte rface configuration cycle will be sent over hub interface. if the cycle is forwarded to the ich4-m via hub interface, the ich4-m compares the non-zero bus number with the secondary bus number and subordinate bus number registers of its pci-to- pci bridges to determine if the configuration cycle is meant for primary pci, one of the ich4- m?s hub interfaces, or a downstream pci bus. 4.4.3 agp/pci_b bus configuration mechanism from the chip-set configuration perspective, agp/p ci_b is seen as pci bus interfaces residing on a secondary bus side of the ?virtual? pci-to-pci bridges referred to as the gmch host- pci_b/agp bridge. on the primary bus side, the ?v irtual? pci-to-pci bridge is attached to pci bus #0. therefore the primary bus number register is hardwired to ?0?. th e ?virtual? pci-to-pci bridge entity converts type #1 pc i bus configuration cycles on pc i bus #0 into type 0 or type 1 configuration cycles on the agp/pci_b interf ace. type 1 configuratio n cycles on pci bus #0 that have a bus number that matches the second ary bus number of the gmch ?s ?virtual? host- to-pci_b/agp bridge will be translated into type 0 configuration cycles on the pci_b/agp interface. the gmch will decode the device number field [15:11 ] and assert the appropriate gad signal as an idsel in acco rdance with the pci-to-pci br idge type 0 configuration mechanism. if the bus number is non-zero, greater than the value programmed into the secondary bus number register, and less than or equal to the value programmed into the subordinate bus number register, the configuration cycle is targeting a pci bus downstream of the targeted interface. the gmch will generate a type 1 pci configuration cycle on pci_b/agp. to prepare for mapping of the configuration cycles on agp/pci_b, the initialization software will go through the following sequence: 1. scan all devices residing on the pci bus #0 using type 0 conf iguration accesses. 2. for every device residing at bus #0 which implements pci-to-pci bridge functionality, it will configure the secondary bus of the bridge with the appropriate number and scan further down the hierarchy. this process will include the configuration of the ?virtual? pci-to-pci bridges within the gmch used to map the agp devi ce?s address spaces in a software specific manner. note: although initial agp platform implementations will not support hierarchical buses residing below agp, this specification still must define this capability in order to support pci-66 compatibility. note also th at future implementations of the agp devices may support hierarchical pci or agp-like buses coming out of the root agp device.
register description r datasheet 55 4.5 register definitions the gmch contains four sets of software accessible register s accessed via the host cpu i/o address space, and they are as follows: ? control registers: i/o mapped into the cpu i/o sp ace, which control access to pci configuration space via configuration mechanism #1 in the pci 2.2 specification. ? internal configuration registers: residing within the gmch, they are partitioned into two logical device register sets (?l ogical? since they reside within the single physical device). the first register set is dedicated to host-hi bridge functionality (i.e. ddr sdram configuration, other chip-set operating parameters and optional features). the second register block is for the integrated graphics functions . ? internal memory mapped configuration registers: reside in the gmch device #0. ? internal memory mapped configuratio n registers and legacy vga registers: reside in the gmch device #2 that controls th e integrated graphics controller . the gmch internal registers (i/ o mapped and configura tion registers) are acce ssible by the host cpu. the registers can be accessed as byte, word (16-bit), or dword (32-b it) quantities, with the exception of config_address, which can onl y be accessed as a dword. all multi-byte numeric fields use ?little endian byte ordering? (i.e., lower addresses contain the least significant parts of the field). reserved bits some of the gmch registers described in this section contain reserved bits. these bits are labeled ?reserved?. software must deal correctly with fields that ar e reserved. on reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. on writes, software must ensure that the values of reserved bit positions are preserved. that is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. note: the software does not need to perform read, me rge, and write operations for the configuration address register. default value upon reset upon a full reset, the gmch sets all of its internal configuration registers to a predetermined default state. some register values at reset are determined by external strapping options. the default state represents the minimum functionality feature set required to successfully bring up the system. hence, it does not represent the optimal sy stem configuration. it is the responsibility of the system initialization software (usually bios) to properly determine the ddr sdram configurations, operating paramete rs, and optional system features that are applicable and to program the gmch registers accordingly.
register description r 56 datasheet 4.6 i/o mapped registers the gmch contains two register s that reside in the cpu i/o address space: the configuration address (config_address) register and the configuration data (config_data) register. the configuration a ddress register enables/disabl es the configuration space and determines what portion of c onfiguration space is visible th rough the configuration data window. 4.6.1 config_address ? configuration address register i/o address: 0cf8h accessed as a dword default value: 00000000h access: read/write size: 32 bits config_address is a 32-bit register that can be accessed only as a dword. a byte or word reference will ?pass through? the configuration a ddress register and the hub interface, onto the pci bus as an i/o cycle. the config_address register contains the bus number, device number, function number, and register number for which a subsequent configuration access is intended. figure 3. configuration address register r 1 0 2 7 8 11 15 16 23 24 30 31 10 r 0 0 0 0 0 reserved register number function number device number bus number reserved enable bit default
register description r datasheet 57 bit description 31 configuration enable (cfge): when this bit is se t to 1, accesses to pci configuration space are enabled. if this bit is reset to 0, accesses to pci configuration space are disabled. 30:24 reserved 23:16 bus number: when the bus number is programmed to 00h, the target of the configuration cycle is a hub interface agent (gmch, ich4-m, etc.). the configuration cycle is forwarded to hub inte rface if the bus number is programmed to 00h and the gmch is not the target (the device number is >= 2). 15:11 device number: this field selects one agent on the pci bus selected by the bus number. when the bus number field is 00 the gmch decodes the device number field. the gmch is always device number 0 for the host-hub interface bridge entity. therefore, when the bus number =0 and the device number=0-1 the internal gmch devices are selected. for bus numbers resulting in hub interface c onfiguration cycles, the gmch propagates the device number field as a[15:11]. 10:8 function number: this field is mapped to a[10:8] during hub interface configuration cycles. this allows the configuration registers of a particular function in a multi-function device to be accessed. the gmch ignores configuration cycles to its inte rnal devices if the function number is not equal to 0. 7:2 register number: this field selects one register within a particular bus, device, and function as specified by the other fields in the configurati on address register. this field is mapped to a[7:2] during hub interface configuration cycles. 1:0 reserved 4.6.2 config_data ? configuration data register i/o address: 0cfch default value: 00000000h access: read/write size: 32 bits config_data is a 32-bit read/write window into configuration space. the portion of configuration space that is refe renced by config_data is dete rmined by the contents of config_address. figure 4. configuration data register 31 0 0 bit default configuration data window
register description r 58 datasheet bit descriptions 31:0 configuration data window (cdw). if bit 31 of config_address is 1, then any i/o access to the config_data register will be mapped to c onfiguration space using the contents of config_address. 4.7 vga i/o mapped registers if device #2 is enabled, and function #0 within device #2 is enabled for vga, and io_en is set within function #0 then gmch claims a set of i/o registers for legacy vga function. table 22 lists direct cpu access registers and table 23 lists registers that are inde x ? data registers that are used to access internal vga registers. table 22. vga i/o mapped register list name function read @ write @ st00 vga input status register 0 3c2h ? st01 vga input status register 1 3bah/3dah ? fcr vga feature control register 3cah 3bah/3dah msr vga miscellaneous status/output register 3cch 3c2h table 23. index ? data registers name function index io data io srx sequencer registers 3c4 3c5 grx graphics controller registers 3ce 3cf arx attribute control registers 3c0 3c0: write 3c1: read dacmask pixel data mask register -- 3c6h dacstate dac state register -- 3c7 read only dacrx palette read index register 3c7 write only -- dacwx palette write index r egister 3c8 write only dacdata palette data register 3c9 crx crt registers 3b4/3d4 (mda/cga) 3b5/3d5 (mda/cga)
register description r datasheet 59 4.8 intel ? 855gm/gme gmch host-hub interface bridge device registers (device #0, function #0) table 24 summarizes the configura tion space for device #0, function#0. table 24. gmch configurati on space - device #0, function#0 register name register symbol register start register end default value access vendor identification vid 00 01 8086h ro device identification did 02 03 3580h ro pci command pcicmd 04 05 0006h ro,r/w pci status pcists 06 07 0090h ro,r/wc revision identification rid 08 08 02h ro sub-class code subc 0a 0a 00h ro base class code bcc 0b 0b 06h ro header type hdr 0e 0e 80h ro subsystem vendor identification svid 2c 2d 0000h r/wo subsystem identification sid 2e 2f 0000h r/wo capabilities pointer capptr 34 34 40h ro capability identification capid 40 44 84_a105_0009h ro gmch misc. control gmc 50 51 0000h r/w gmch graphics control ggc 52 53 0030h r/w device and function control dafc 54 55 0000h r/w fixed dram hole control fdhc 58 58 00h r/w programmable attribute map pam (6:0) 59 5f 00h each r/w system management ram control smram 60 60 02h r/w/l extended system management ram control esmramc 61 61 38h r/w/l error status errsts 62 63 0000h r/wc error command errcmd 64 65 0000h r/w smi command smicmd 66 66 00h r/w sci command scicmd 67 67 00h r/w secondary host interface control register shic 74 77 00006010h ro, r/w agp capability identifier acapid a0 a3 00200002h ro agp status register ag pstat a4 a7 1f000217h ro
register description r 60 datasheet register name register symbol register start register end default value access agp command agpcmd a8 ab 0000 0000h ro, r/w agp control agpctrl b0 b1 0000h ro, r/w agp functional test aft b2 b3 e9f0h r/w, r/wc aperture translation table base attbase b8 bb 00000000h ro, r/w agp interface multi transaction timer amtt bc bc 00h r/w low priority transaction timer lptt bd bd 00h r/w host error control/status/obs hem f0 f3 00000000h ro, r/w 4.8.1 vid ? vendor identification register address offset: 00-01h default value: 8086h access: read only size: 16 bits the vid register contains the vendor identification number. this 16-bit register, combined with the device identification register, uniquely identifies any pci device. writes to this register have no effect. bit description 15:0 vendor identification (vid): this register field contains the pci standard identification for intel. 4.8.2 did ? device identification register address offset: 02-03h default value: 3580h access: read only size: 16 bits this 16-bit register combined with the vendor identification register uniquely identifies any pci device. writes to this register have no effect. bit description 15:0 device identification number (did): this is a 16-bit value assigned to the gmch host-hub interface bridge, device #0.
register description r datasheet 61 4.8.3 pcicmd ? pci command register address offset: 04-05h default value: 0006h access: read only, read/write size: 16 bits since gmch device #0 does not physically reside on pci_a many of the bits are not implemented. bit descriptions 15:10 reserved 9 fast back-to-back enable (fb2b): this bit controls whether or not the master can do fast back-to- back write. since device #0 is strictly a target, this bit is not implemented and is hardwired to 0. writes to this bit position have no affect. 8 serr enable (serre): this bit is a global enable bit fo r device #0 serr messaging. the gmch does not have an serr# signal, but communica tes the serr# condition by sending an serr message to the ich4-m. 1 = enable. gmch is enabled to generate serr messages over hub interface for specific device #0 error conditions that are individually enabled in the e rrcmd register. the error status is reported in the errsts and pcists registers. 0 = serr message is not generated by the gmch for device #0. note : this bit only controls serr me ssaging for the device #0. device #1 has its own serre bit to control error reporting for error c onditions occurring on device #1. the two control bits are used in a logical or manner to enable the se rr hub interface message mechanism. 7 address/data stepping enable (adstep): address/data stepping is not implemented in the gmch, and this bit is hardwired to 0. writes to this bit position have no effect. 6 parity error enable (perre): perr# is not implemented by gmch and this bit is hardwired to 0. writes to this bit position have no effect. 5 vga palette snoop enable (vgasnoop): the gmch does not implement this bit and it is hardwired to a 0. writes to this bit position have no effect. 4 memory write and invalidate enable (mwie): the gmch will never issue memory write and invalidate commands. this bit is therefore hardwired to 0. writes to this bit position will have no effect. 3 special cycle enable (sce): the gmch does not implement this bit and it is hardwired to a 0. writes to this bit position have no effect. 2 bus master enable (bme): the gmch is always enabled as a master on hi. this bit is hardwired to a 1. writes to this bit position have no effect. 1 memory access enable (mae): the gmch always allows access to main system memory. this bit is not implemented and is hardwired to 1. writ es to this bit position have no effect. 0 i/o access enable (ioae): this bit is not implemented in the gm ch and is hardwired to a 0. writes to this bit position have no effect.
register description r 62 datasheet 4.8.4 pci status register address offset: 06-07h default value: 0090h access: read only, read/writeclear size: 16 bits pcists is a 16-bit status register that reports the occurrence of error ev ents on device #0?s pci interface. bit 14 is read/write clear. all other bits are read on ly. since gmch device #0 does not physically reside on pci_a many of the bits are not implemented. bit description 15 detected parity error (dpe): the gmch does not implement this bit and it is hardwired to a 0. writes to this bit position have no effect. 14 signaled system error (sse): r/wc. this bit is set to 1 when gmch device #0 generates an serr message over hi for any enabled device #0 error c ondition. device #0 error conditions are enabled in the pcicmd and errcmd registers. device #0 error fl ags are read/reset from the pcists or errsts registers. software sets sse to 0 by writing a 1 to this bit. 13 received master abort status (rmas): r/wc. this bit is set when the gmch generates a hi request that receives a master abort completion packet or ma ster abort special cycle. software clears this bit by writing a 1 to it. 12 received target abort status (rtas): r/wc. this bit is set when the gmch generates a hi request that receives a target abort completion packet or tar get abort special cycle. software clears this bit by writing a 1 to it. if bit 6 in the errcmd is set to a one and an serr# special cycle is generated on the hi bus. 11 signaled target abort status (stas): the gmch will not generate a target abort hi completion packet or special cycle. this bit is not implemented in the gmch and is hardwired to a 0. writes to this bit position have no effect. 10:9 devsel timing (devt): these bits are hardwired to ?00?. writes to these bit positions have no affect. device #0 does not physically connect to pci_a. these bits are set to ?00? (fast decode) so that the gmch does not limit optimum devsel timing for pci_a. 8 master data parity error detected (dpd): perr signaling and messaging are not implemented by the gmch therefore this bit is hardwired to 0. writes to this bit position have no effect. 7 fast back-to-back (fb2b): this bit is hardwired to 1. writes to these bit positions have no effect. device #0 does not physically connect to pci_a. this bit is set to 1 (indicating fast back-to-back capability) so that the gmch does not limit the optimum setting for pci_a. 6:5 reserved 4 capability list (clist): this bit is hardwired to 1 to indicate to the configuration software that this device/function implements a list of new capabilities. a list of new capabilities is accessed via register capptr at configuration address offset 34h. 3:0 reserved
register description r datasheet 63 4.8.5 rid ? register identification address offset: 08h default value: 02h access: read only size: 8 bits this register contains the revision number of the gmch device #0. these bits are read only and writes to this register have no effect. bit description 7:0 revision identification number (rid): this is an 8-bit value that i ndicates the revision identification number for the gmch device #0. 4.8.6 subc ? sub class code register address offset: 0ah default value: 00h access: read only size: 8 bits this register contains the sub-class code for the gmch device #0. this code is 00h indicating a host bridge device. bit description 7:0 sub-class code (subc): this is an 8-bit value that indicates the category of bridge into which the gmch falls. the code is 00h indicating a host bridge. 4.8.7 bcc ? base class code register address offset: 0bh default value: 06h access: read only size: 8 bits this register contains the base class code of the gmch device #0. this code is 06h indicating a bridge device. bit description 7:0 base class code (basec): this is an 8-bit value that indicates the base class code for the gmch. this code has the value 06h, indicating a bridge device.
register description r 64 datasheet 4.8.8 hdr ? header type register address offset: 0eh default value: 80h access: read only size: 8 bits this register identifies th e header layout of the configuration space. no physical register exists at this location. bit description 7:0 pci header (hdr): this field always returns 80 to indicate that device #0 is a multifunction device. if functions other than 0 are disabled, this field returns a 00 to indicate that the gmch is a single function device with standard header layout. writes to this location have no effect. 4.8.9 svid ? subsystem vendor identification register address offset: 2c-2dh default value: 0000h access: read/write once size: 16 bits this value is used to identify the vendor of the subsystem. bit description 15:0 subsystem vendor id (subvid): this field should be programmed during boot-up to indicate the vendor of the system board. after it has been written once, it becomes read only. 4.8.10 sid ? subsystem identification register address offset: 2e-2fh default value: 0000h access: read/write once size: 16 bits this value is used to identify a particular subsystem. bit description 15:0 subsystem id (subid): this field should be programmed during bios initialization. after it has been written once, it becomes read only.
register description r datasheet 65 4.8.11 capptr ? capabilities pointer register bit description 7:0 pointer to the offset of the first capability id register block: in this case the first capability is the product-specific capability, which is located at offset 40h. 4.8.12 capid ? capability identification register (device #0) address offset: 40h ? 44h default: chipset dependent access: read only size 40 bits the capability identification register uniquely identifies chipset capabilities as defined in the table below. the bits in this register are intended to define a capability ceiling for each feature, not a capability select. the capability selection fo r each feature is implemented elsewhere. the mechanism to select th e capability for each feature must co mprehend these capability registers and not allow a selected setting ab ove the ceiling specified in these registers. the bios must read this register to identify the part and comprehend the capabilities specified within when configuring the effected portions of the gmch. the default setting, in most cases, allows the maximum capability. exceptions are noted in the individual bits. this register is read only. writes to this register have no effect. bit description 39:37 capability id [2:0]: 000 = intel 855gme gmch 001-011 = reserved 100 = intel 855gm gmch 101-111 = reserved 36:28 reserved 27:24 capreg version: this field has the value 0001b to identify t he first revision of the capreg definition. 23:16 cap_length: this field has the value 05h indicating the structure length. 15:0 reserved
register description r 66 datasheet 4.8.13 gmc ? gmch miscellaneous control register (device #0) address offset: 50?51h default value: 0000h access: read/write size: 16 bits bit description 15:10 reserved 9 reserved 8 rrbar access enable?r/w: 1 = enables the rrbar space. 0 = disable 7:1 reserved 0 mda present (mdap)?r/w: this bit should not be set when the vga enable bit is not set. if the vga enable bit is set, then accesses to io address range x3bch?x3bfh are forwarded to h ub interface. if the vga enable bit is not set then accesses to io address range x3bch?x3bfh are tr eated just like any other io accesses. mda resources are defined as the following: memory: 0b0000h ? 0b7fffh i/o: 3b4h, 3b5h, 3b8h, 3b9h, 3bah, 3bfh, (including isa address aliases, a[15:10] are not used in decode) any i/o reference that includes the i/o locations lis ted above, or their aliases, will be forwarded to hub interface even if the reference incl udes i/o locations not listed above. the following table shows the behavior for all combinations of mda and vga: vga mda behavior 0 0 all references to mda and vga go to hub interface (default) 0 1 reserved 1 0 all references to vga go to pci. mda-only references ( i/o address 3bf and aliases) will go to hub interface. 1 1 vga references go to pci; mda references go to hub interface
register description r datasheet 67 4.8.14 ggc ? gmch graphics control register (device 0) address offset: 52?53h default value: 0030h access: read/write size: 16 bits bit description 15:7 reserved 6:4 graphics mode select (gms): this field is used to select the amount of main system memory that is pre-allocated to support the inter nal graphics device in vga (non-li near) and native (linear) modes. the bios ensures that system memory is pre- allocated only when internal graphics is enabled. 000 = no system memory pre-allocated. device #2 (i gd) does not claim vga cycles (memory and i/o), and the sub-class code field within device #2 function #0 class code register is 80. 001 = dvmt (uma) mode, 1 mb of system memory pre-allocated for frame buffer. 010 = dvmt (uma) mode, 4 mb of system memory pre-allocated for frame buffer. 011 = dvmt (uma) mode, 8 mb of system memory pre-allocated for frame buffer. 100 = dvmt (uma) mode, 16 mb of system memory pre-allocated for frame buffer. 101 = dvmt (uma) mode, 32 mb of system memory pre-allocated for frame buffer. all other combinations reserved. 3:2 reserved 1 igd vga disable (ivd): 1 = disable. device #2 (igd) does not claim vga memory and i/o mem cycles, and the sub-class code field within device #2 function #0 class code register is 80. 0 = enable. device #2 (igd) claims vga memory and i/o cycles, the sub-class code within device #2 class code register is 00. 0 reserved
register description r 68 datasheet 4.8.15 dafc ? device and function control register (device 0) address offset: 54?55h default value: 0000h access: read/write size: 16 bits this 16-bit register controls the visibility of devices and functions within the gmch to configuration software. bit description 15:8 reserved 7 device #2 disable: 1 = disabled. 0 = enabled. 6:3 reserved 2 device #0 function #3 disable: 1 = disable function #3 registers within de vice #0 and all associated ddr sdram and i/o ranges. 0 = enable function #3 within device #0. 1 reserved 0 device #0 function #1 disable: 1 = disable function #1 within device #0. 0 = enable function #1 within device #0. 4.8.16 fdhc ? fixed dram hole control register (device #0) address offset: 58h default value: 00h access: read/write size: 8 bits this 8-bit register controls a single fixed ddr sdram hole: 15?16 mb. bit description 7 hole enable (hen): this field enables a memory hole in ddr sdram space. host cycles matching an enabled hole are passed onto ich4-m through hub interf ace. the gmch will ignore hub interface cycles matching an enabled hole. note : a selected hole is not re-mapped. 0 = none 1 = 15 mb?16 mb (1mbs) 6:0 reserved
register description r datasheet 69 4.8.17 pam(6:0) ? programmable attribute map register (device #0) address offset: 59?5fh default value: 00h each attribute: read/write size: 4 bits/register, 14 registers the gmch allows programmable ddr sdram attributes on 13 legacy system memory segments of various sizes in the 640 kb ?1 mb address range. seven programmable attribute map (pam) registers are used to support these f eatures. cacheability of these areas is controlled via the mtrr registers in the p6 processor. two bits are used to specify system memory attributes for each system memory segment. th ese bits apply to both host and hub interface initiator accesses to the pam ar eas. these attributes are: ? re - read enable . when re = 1, the cpu read accesses to the corresponding system memory segment are claimed by the gmch and directed to main system memory. conversely, when re = 0, the host read accesses are directed to pci0. ? we - write enable . when we = 1, the host write accesses to the corresponding system memory segment are claimed by the gmch and directed to main system memory. conversely, when we = 0, the host write accesses are directed to pci0. the re and we attributes permit a system memory segment to be read only, write only, read/write, or disabled. for example, if a syst em memory segment has re = 1 and we = 0, the segment is read only. each pam register controls two regions, typically 16 kb in size. each of these regions has a 4-bit field. the 4 bits that control each region have the same encoding and are defined in the following table. table 25. attribute bit assignment bits [7, 3] reserved bits [6, 2] reserved bits [5, 1] we bits [4, 0] re description x x 0 0 disabled . ddr sdram is disabled and all accesses are directed to hub interface. the gmch does not respond as a hub interface target for any read or write access to this area. x x 0 1 read only . reads are forwarded to ddr sdram and writes are forwarded to hub interface for termination. this write protects the corresponding ddr sdram segment. the gmch will respond as a hub interface target for read accesses but not for any write accesses. x x 1 0 write only . writes are forwarded to ddr sdram and reads are forwarded to the hub interface for termination. the gmch will respond as a hub interface target for write accesses but not for any read accesses.
register description r 70 datasheet bits [7, 3] reserved bits [6, 2] reserved bits [5, 1] we bits [4, 0] re description x x 1 1 read/write . this is the normal operating mode of main system memory. both read and write cycles from the host are claimed by the gmch and forwarded to ddr sdram. the gmch will respond as a hub interface target for both read and write accesses. as an example, consider a bios that is implemented on the expansion bus. during the initialization process, the bios can be shadowed in main system memory to increase the system performance. when bios is shadowed in main system memory, it should be copied to the same address location. to shadow the bios, the attributes for that address range should be set to write only. the bios is shadowed by first doing a read of that address. this r ead is forwarded to the expansion bus. the host then does a write of the same address, which is directed to main system memory. after the bios is shadowed, the attributes for that system memory area are set to read only so that all writes are forwarded to the expansion bus. figure 5 and table 26 show the pam registers and the associated attribute bits. figure 5. pam registers pam re we re r r we r r 76543210 pam6 pam5 pam4 pam3 pam2 pam1 pam0 read enable (r/w) 1=enable 0=disable write enable (r/w) 1=enable 0=disable reserved reserved read enable (r/w) 1=enable 0=disable write enable (r/w) 1=enable 0=disable reserved reserved 5fh 5eh 5dh 5ch 5bh 5ah 59h offset
register description r datasheet 71 table 26. pam registers and associated system memory segments pam reg attribute bits system memory segment offset pam0[3:0] reserved comments 59h pam0[7:4] r r we re 0f0000h?0fffffh bios area 59h pam1[3:0] r r we re 0c0000h?0c3fffh isa add-on bios 5ah pam1[7:4] r r we re 0c4000h?0c7fffh isa add-on bios 5ah pam2[3:0] r r we re 0c8000h?0cbfffh isa add-on bios 5bh pam2[7:4] r r we re 0cc000h?0cffffh isa add-on bios 5bh pam3[3:0] r r we re 0d0000h?0d3fffh isa add-on bios 5ch pam3[7:4] r r we re 0d4000h?0d7fffh isa add-on bios 5ch pam4[3:0] r r we re 0d8000h?0dbfffh isa add-on bios 5dh pam4[7:4] r r we re 0dc000h?0dffffh isa add-on bios 5dh pam5[3:0] r r we re 0e0000h?0e3fffh bios extension 5eh pam5[7:4] r r we re 0e4000h?0e7fffh bios extension 5eh pam6[3:0] r r we re 0e8000h?0ebfffh bios extension 5fh pam6[7:4] r r we re 0ec000h?0effffh bios extension 5fh for details on overall system address mapping sche me see the address decoding section of this document. dos application area (00000h?9fffh) the dos area is 640 kb in size and it is further divided into two parts. the 512-kb area at 0 to 7ffffh is always mapped to the main system memory controlled by the gmch, while the 128- kb address range from 080000 to 09ffffh can be ma pped to pci0 or to main ddr sdram. by default this range is mapped to main system memory and can be declared as a main system memory hole (accesses forwarded to pci0) vi a gmch?s fdhc conf iguration register. video buffer area (a0000h?bffffh) attribute bits do not control this 128-kb area. the host-initiated cycles in this region are always forwarded to either pci0 or pci2 unl ess this range is accessed in smm mode. routing of accesses is controlled by the legacy vga control mechanism of the ?virtual? pci-pci bridge device embedded within the gmch. this area can be programmed as smm area via the smram register. when used as an smm space, this range can not be accessed from the hub interface. expansion area (c0000h?dffffh) this 128-kb area is divided into eight 16-kb segments that can be assigned with different attributes via pam control register as defined in figure 5 and table 26.
register description r 72 datasheet extended system bios area (e0000h?effffh) this 64-kb area is divided into four 16-kb segments that can be assigned with different attributes via pam control register as defined in figure 5 and table 26. system bios area (f0000h?fffffh) this area is a single 64-kb segment that can be assigned with different attributes via pam control register as defined in figure 5 and table 26. 4.8.18 smram ? system management ram control register (device #0) address offset: 60h default value: 02h access: read/write/ lock, read only size: 8 bits the smram register controls how accesses to compatible and extended smram spaces are treated. the open, close, and lock bits function only when g_smrame bit is set to a 1. also, the open bit must be reset before the lock bit is set. bit description 7 reserved 6 smm space open (d_open): when d_open=1 and d_lck=0, the smm space ddr sdram is made visible even when smm decode is not active. this is intended to help bios initialize smm space. software should ensure that d_open=1 and d_cls=1 are not set at the same time. when d_lck is set to a 1, d_open is reset to 0 and becomes read only. 5 smm space closed (d_cls): when d_cls = 1 smm space, ddr sdram is not accessible to data references, even if smm decode is active. c ode references may still access smm space ddr sdram. this will allow smm software to refer ence ?through? smm space to update the display even when smm is mapped over the vga range. softwar e should ensure that d_open=1 and d_cls=1 are not set at the same time. d_cls applies to all smm spaces (cseg, hseg, and tseg). 4 smm space locked (d_lck): when d_lck is set to 1, then d_open is reset to 0 and d_lck, d_open, g_smrame, c_base_seg, gms, drb, dra, h_smram_en, tseg_sz and tseg_en become read only. d_lck can be set to 1 via a nor mal configuration space write but can only be cleared by a full reset. the combination of d_lc k and d_open provide convenience with security. the bios can use the d_open function to initia lize smm space and then use d_lck to ?lock down? smm space in the future so that no application softw are (or bios itself) can violate the integrity of smm space, even if the program has knowledge of the d_open function. 3 global smram enable (g_smrame): if set to a 1, then compatible smram functions is enabled, providing 128 kb of ddr sdram accessible at the a0000h address while in smm (ads# with smm decode). to enable extended smram function this bit mu st be set to 1, refer to the section on smm for more details. once d_lck is set, this bit becomes read only. 2:0 compatible smm space base segment (c_base_seg)?ro: this field indicates the location of smm space. ?smm dram? is not remapped. it is simply ?made visible? if the conditions are right to access smm space, otherwise the access is forw arded to hub interface. c_base_seg is hardwired to 010 to indicate that the gmch s upports the smm space at a0000h?bffffh.
register description r datasheet 73 4.8.19 esmramc ? extended system management ram control (device #0) address offset: 61h default value: 38h access: read/write/lock size: 8 bits the extended smram register controls the configuration of extended smram space. the extended smram (e_smram) me mory provides a write-back cacheable smram memory space that is above 1 mb. bit description 7 h_smram_en (h_smrame): controls the smm memory space location (i.e., above 1 mb or below 1 mb). when g_smrame is 1 and h_smrame this bi t is set to 1, the high smram memory space is enabled. smram accesses from 0feda0000h to 0fedbffffh are remapped to ddr sdram address 000a0000h to 000bffffh. once d_lck is set, this bit becomes read only. 6 e_smram_err (e_smerr): this bit is set when cpu accesses the defined ddr sdram ranges in extended smram (high system memory and t-segm ent) while not in smm space. it is software?s responsibility to clear this bit. the software must write a 1 to this bit to clear it. 5 smram_cache (sm_cache): gmch forces this bit to 1. 4 smram_l1_en (sm_l1): gmch forces this bit to 1. 3 smram_l2_en (sm_l2): gmch forces this bit to 1. 2:1 reserved 0 tseg_en (t_en): enabling of smram memory (tseg, 1 mb ytes of additional smram memory) for extended smram space only. when g_smrame =1 and tseg_en = 1, the tseg is enabled to appear in the appropriate physical address space. once d_lck is set, this bit becomes read only.
register description r 74 datasheet 4.8.20 errsts ? error status register (device #0) address offset: 62?63h default value: 0000h access: read/write clear size: 16 bits this register is used to report various erro r conditions via hub interface special cycles. an serr, smi, or sci error hub interface special cycle may be generated on a zero to one transition of any of these fl ags when enabled in the pcic md/errcmd, smicmd, or scicmd registers respectively. bit description 15:14 reserved 13 fsb strobe glitch detected (fsbagl): when this bit is set to 1 the gmch has detected a glitch on one of the fsb strobes. writing a 1 to it clears this bit. 12 gmch software generated event for smi: 1 = this indicates the source of the smi was a device #2 software event. 0 = software must write a 1 to clear this bit. 11 gmch thermal sensor event for smi/sci/serr: 1 = indicates that a gmch thermal sensor trip has occurred and an smi, sci or serr has been generated. note that the status bit is set only if a message is sent based on thermal event enables in error command, smi command and sci command registers. note that a trip point can generate one of smi, sci or serr interrupts (two or mo re per event is illegal). multiple trip points can generate the same interrupt. if software chooses this mode, then subsequent trips may be lost. 0 = software must write a 1 to clear this status bit. if this bit is set, then an interrupt message will not be sent on a new thermal sensor event. 10 reserved 9 lock to non-ddr sdram memory flag (lckf)?r/wc: 1 = indicates that a cpu initiated lock cycl e targeting non-ddr sdram memory space occurred. 0 = software must write a 1 to clear this status bit 8 received refresh timeout?r/wc: 1 = this bit is set when 1024 memory core refresh are queued up. 0 = software must write a 1 to clear this status bit. 7 dram throttle flag (dtf)?r/wc: 1 = indicates that the ddr sdram throttling condition occurred. 0 = software must write a 1 to clear this status bit. 6 reserved 5 received unimplemented special cycle hub in terface completion packet flag (unsc)?r/wc: 1 = indicates that the gmch initiated a hub interface request that was terminated with an unimplemented special cycle completion packet. 0 = software must write a 1 to clear this status bit. 4:0 reserved
register description r datasheet 75 4.8.21 errcmd ? error command register (device #0) address offset: 64?65h default value: 0000h access: read/write size: 16 bits this register enables various e rrors to generate a serr hub in terface special cycle. since the gmch does not have a serr# signal, serr messages are passed from the gmch to the ich4- m over hub interface. the actual generation of the serr message is globally enabled for device #0 via the pci command register. note: an error can generate one and only one hub inte rface error special cycle. it is software?s responsibility to make sure that when an serr e rror message is enabled for an error condition, smi and sci error messages are disabl ed for that same error condition. bit description 15:14 reserved 13 serr on fsb strobe glitch: when this bit is asserted, the gmch will generate a hi serr message when a glitch is detected on one of the fsb strobes. 12 reserved 11 serr on gmch thermal sensor event: 1 = the gmch generates a serr hub interface specia l cycle on a thermal sensor trip that requires an serr. the serr must not be enabled at the same time as the smi/sci for a thermal sensor trip event. 0 = software must write a 1 to clear this status bit. 10 reserved 9 serr on lock to non-ddr sdram memory: 1 = the gmch generates an serr hub interface special cycle when a cpu initiated lock transaction targeting non-ddr sdra m memory space occurs. 0 = reporting of this condition is disabled. 8 serr on ddr sdram refresh timeout: 1 = the gmch generates an serr hub interface s pecial cycle when a ddr sdram refresh timeout occurs. 0 = reporting of this condition is disabled. 7 serr on ddr sdram throttle condition: 1 = the gmch generates an serr hub interface special cycle when a ddr sdram read or write throttle condition occurs. 0 = reporting of this condition is disabled. 6 serr on receiving target abort on hub interface: 1 = the gmch generates an serr hub interfac e special cycle when a gmch originated hub interface cycle is terminated with a target abort. 0 = reporting of this condition is disabled.
register description r 76 datasheet bit description 5 serr on receiving unimplemented special cycle hub interface completion packet: 1 = the gmch generates an serr hub interface spec ial cycle when a gmch initiated hub interface request is terminated with a unimplem ented special cycle completion packet. 0 = reporting of this condition is disabled. 4:2 reserved 1 serr on multiple-bit ecc error: 1 = for systems that support ecc, this field must be set to 1. 0 = reserved 0 serr on single-bit ecc error: 1 = for systems that support ecc, this field must be set to 1. 0 = reserved 4.8.22 smicmd ? smi error command register (device #0) address offset: 66h default value: 00h access: read/write size: 8 bits this register enables various e rrors to generate an smi hub in terface special cycle. when an error flag is set in the errsts register, it can generate a serr, smi, or sci hub interface special cycle when enabled in the errcmd, smicmd, or scic md registers respectively. note: an error can generate one and only one hub inte rface error special cycle. it is software?s responsibility to make sure that when an smi e rror message is enabled for an error condition, serr, and sci error messages are disabl ed for that same error condition. bit description 7:4 reserved 3 smi on gmch thermal sensor trip: 1 = an smi hub interface special cycle is generat ed by gmch when the thermal sensor trip requires an smi. a thermal sensor trip point c annot generate more than one special cycle. 2 reserved 1 smi on multiple-bit ecc error: 1 = for systems that support ecc, this field must be set to 1. 0 = reserved 0 smi on single-bit ecc error: 1 = for systems that support ecc, this field must be set to 1. 0 = reserved
register description r datasheet 77 4.8.23 scicmd ? sci error command register (device 0) address offset: 67h default value: 00h access: read/write size: 8 bits this register enables various erro rs to generate a sci hub interf ace special cycle. when an error flag is set in the errsts register, it can gene rate a serr, smi, or sci hub interface special cycle when enabled in the errcmd, smic md, or scicmd registers respectively. note: an error can generate one and only one hub inte rface error special cycle. it is software?s responsibility to make sure that when an sci e rror message is enabled for an error condition, serr and smi error messages are disabl ed for that same error condition. bit description 7:4 reserved 3 sci on gmch thermal sensor trip: 1 = an sci hub interface special cycle is generat ed by gmch when the thermal sensor trip requires an sci. a thermal sensor trip point c annot generate more than one special cycle. 2 reserved 1 sci on multiple-bit ecc error: 1 = for systems that support ecc, this field must be set to 1. 0 = for systems that do not support ecc, this field must be 0. 0 sci on single-bit ecc error: 1 = for systems that support ecc, this field must be set to 1. 0 = for systems that do not support ecc, this field must be 0.
register description r 78 datasheet 4.8.24 shic ? secondary host interface control register (device #0) address offset: 74-77h default value: 00006010h access: read only, read/write size: 32 bits bit description 31 reserved 30 breq0# control of fsb address and control bus power management: 0 = disable fsb address and control bus power management. 1 = enable fsb address and control bus power management. 29:28 reserved 27 on die termination (odt) gating disable: 0 = enable. 1 = disable. 26:7 reserved 6 fsb data bus power management control: 0 = fsb data bus power management disabled (default). 1 = fsb data bus power management enabled 5 reserved 4:3 dpwr# control. 00 = dpwr# pin is always asserted. 10 = dpwr# pin is asserted at least 2 clocks before read data is returned to the processor on the fsb (2 clocks before drdy# asserted). this is default setting. 01 = dpwr# is always de-asserted. 11 = reserved 2 c2 state gmch fsb interface power management control: 0 = power management disabled in c2 state 1 = power management enabled in c2 state
register description r datasheet 79 bit description 1 agp/dvo mux strap (read only) specifies the use of agp bus muxed with dvo. this bit is defined at reset by a strap on the g_par/dvo_detect signal. by default the agp bus pu lls this signal high. the presence of an dvo device pulls this signal low. the presence of a dv o device disables device #1 and associated memory and io spaces are disabled. in additi on, sets the next_pointer = 00h in the capability register, converts apbase to read only, and disables aperture global access. also prevents vga memory and io decodes to the agp interface. if agp capability is limited (disabled), then the ag p pins are dedicated to internal graphics dvo functionality. if agp capability is available, then based on this str ap, the agp interface is used for agp functionality or dvo functionality based on this strap. 1= agp. 0 = dvo 0 reserved 4.8.25 acapid ? agp capability identifier register (device #0) address offset: a0-a3h default value: 00200002h access: read only size: 32 bits this register provides standard identifier for agp capability. bit description 31:24 reserved 23:20 major agp revision number. these bits provide a major revisi on number of agp specification to which this version of gmch conforms . these bits are set to the value 0010b to indicate agp rev. 2.x. 19:16 minor agp revision number . these bits provide a minor revisi on number of agp specification to which this version of gmch conforms. this is set to 0000b (i.e., implying rev x.0) together with major revision number this field i dentifies gmch as an agp rev 2.0 compliant device. 15:8 next capability pointer . agp capability is the last capabilit y described via the capability pointer mechanism and therefore these bits are set to 00h to indicate the end of the capability linked list. 7:0 agp capability id. this field identifies the linked list item as containing agp registers. this field has the value 02h as assigned by the pci sig.
register description r 80 datasheet 4.8.26 agpstat ? agp status register (device #0) address offset: a4?a7h default value: 1f000217h access: read only size: 32 bits this register reports agp device capability/status. bit description 31:24 request (rq). indicates a maximum of 32 outstanding agp command requests can be handled by the gmch . default =1fh to allow a maximum of 32 outstanding agp command requests. 23:10 reserved 9 side band addressing (sba). indicates that the gmch supports side band addressing. 8:6 reserved 5 address support above 4 gb (4 gb). indicates that the gmch does not support addresses greater than 4 gigabytes. 4 fast writes. 1 = the gmch supports fast writes from the cpu to the agp master. (default) 3 reserved 2:0 rate . after reset the gmch reports its data transfer rate capability. bit 0 identifies if agp device supports 1x data transfer mode, bit 1 identifies if agp device supports 2x data transfer mode, bit 2 identifies if agp device supports 4x data transfer mode. 1x , 2x , and 4x data transfer modes are supported by the gmch and therefore this bit field has a default value = 111. note : the selected data transfer mode applies to both ad bus and sba bus.
register description r datasheet 81 4.8.27 agpcmd ? agp command register (device #0) address offset: a8?abh default value: 00000000h access: read/write size: 32 bits this register provides control of the agp operational parameters. bit description 31:10 reserved 9 side band addressing enable (sba_en). when this bit is set to 1, the side band addressing mechanism is enabled. 8 agp enable. 0 = disable. when this bit is reset to 0, the gmch will ignore all agp operations, including the sync cycle. any agp operations received while this bit is set to 1 will be serviced even if this bit is reset to 0. if this bit transitions from a 1 to a 0 on a clock edge in the middle of an sba command being delivered in 1x mode, the command will be issued. 1 = enable. the gmch will respond to agp operat ions delivered via pipe#, or to operations delivered via sba if the agp side band enable bit is also set to 1. 7:6 reserved 5 address support above 4 gb enable (4 gb_en). the gmch as an agp target does not support addressing greater than 4 gigabytes. 4 fast write enable. 1 = enable. gmch agp master supports fast writes. 0 = disable (default). fast writes are disabled. 3 reserved 2:0 data rate. the settings of these bits determi ne the agp data transfer rate. one ( and only one ) bit in this field must be set to indicate the desired data trans fer rate. bit 0: 1x, bit 1: 2x, bit 2: 4x. the same bit must be set on both master and target. configuration software will update this field by setti ng only one bit that corresponds to the capability of agp master (after that capability has been verified by accessing the same functional register within the agp masters configuration space.) note : the selected data transfer mode applies to both ad bus and sba bus.
register description r 82 datasheet 4.8.28 agpctrl ? agp control register (device #0) address offset: b0?b1h default value: 0000h access: read/write size: 16 bits this register provides for additi onal control of the agp interface. bit 7 is visible to the operating system and must be retained in this position. bit description 15:8 reserved 7 gtlb enable (and gtlb flush control). note: this bit can be changed dynamically (i.e ., while an access to gtlb occurs). this bit must not be changed through memory m apped configuration register access space. 6:0 reserved 4.8.29 aft ? agp functional test register (device #0) address offset: b2?b3h default value: e9f0h access: read/write, read/writeclear size: 16 bits this register provides for additi onal control of the agp interface. bit description 15:11 retry timer time-out count (rttoc): these bits control the retry time-out period (for initial data phase) for the purpose of enhancing the system testab ility. these bits correspond to value loaded into retry timer. default value is 11101b (29d) for retry clock count of 32d (value +3). 10 pci write streaming disable (pcibwsd): when this bit is set to ?1?, pci_b writes to ddr sdram are disconnected at a 32 byte cache line boundary (write streaming is disabled). w hen this bit is set to ?0? (default), write streaming is enabled. 9 pci read buffer disable. 1 = when set to ?1? the pci read buffering mechanism is disabled. in this mode all data prefetched and buffered for a pci to ddr sdram read will be di scarded when that read transaction terminates. this bit defaults to ?0?. 8:4 agp/pci1 discard timer time-out count. these bits control the length of agp/pci1 delayed transaction discard time-out for the purpose of enhanc ing the system testability. default value is 11111b (31d) for a discard count of 1024d ((value+1)*32). 3 pci_b write combining disable (pcibwcd ): when this bit is set to ?1 ?, write combining is disabled for host bus writes targeting the pci_b bus (depends on configuration). when this bit is ?0? (default), write combining is enabled.
register description r datasheet 83 bit description 2 agp/pci1 discard timer disable. 0 = enable (default). enables the discard time r for the delayed transactions on the pci1/agp interface (initiated by the agp agent using pci protocol). the counter starts once the delayed transaction request is ready to complete as fa r as gmch is concerned (i .e., read data is pending on the top of agp outbound queue). if the agp agent (using pci protocol) does not repeat the transaction before the counter expires after 2^10 clocks (66 mhz) the gmch will delete the delayed transaction from its queue and set the discard timer status bit. 1 = disable. the discard timer is disabled. 1 agp/pci discard timer status (agpdts): r/wc when set to 1 this bit indicates that a delayed transaction on pci_b has been discarded due to dt time r expiration. when set this bit can be cleared by writing it with 1. 0 reserved 4.8.30 apsize ? aperture size (device #0) address offset: b4h default value: 00h access: read/write size: 8 bits this register determines the effective size of th e graphics aperture used for a particular gmch configuration. this register can be updated by the gmch -specific bios configuration sequence before the pci standard bus enumeration sequence. if the register is not updated then a default value will select an aperture of maximum size (i.e., 256 mb). the size of the table that will correspond to a 256 mb aperture is not practical for most applications and therefore these bits must be programmed to a smaller practical value that will force adequate address range to be requested via apbase register fro m the pci configuration software. bit description 7:6 reserved 5:0 graphics aperture size (apsize). each bit in apsize[5:4] operates on similarly ordered bits in apbase[27:26] of the aperture base configuration regist er. when a particular bit of this field is 0 it forces the similarly ordered bit in apbase[27:26] to behave as 0. when a particular bi t of this field is set to 1 it allows corresponding bit of the apbase[27:26] to be read/write accessible. only the following combinations are allowed when the aperture is enabled: bits[5:4] aperture size 11 64 mb 10 128 mb 00 256 mb default for apsize[5:4]=00b forces default apbase[27:26] =00b (i.e. all bits respond as hardwired to 0). this provides maximum aperture size of 256 mb . as another example, programming apsize[5:4]=11b enables apbase[27:26] as read/write programmabl e providing a minimum size of 64 mb. 3:0: reserved set to zero for software compatibility.
register description r 84 datasheet 4.8.31 attbase ? aperture translation table base register (device #0) address offset: b8?bbh default value: 00000000h access: read/write size: 32 bits this register provides the starting address of the graphics aperture translation table base located in the main ddr sdram. this value is used by the gmch?s graphics aperture address translation logic (including the gtlb logic) to obtain the appropriate address translation entry required during the translation of the apertu re address into a corresponding physical ddr sdram address. the attbase register may be dynamically changed. the address provided via attbase is 4 kb aligned. bit description 31:12 this field contains a pointer to the base of the translation table used to map memory space addresses in the aperture range to addresses in main memory. 11:0 reserved 4.8.32 amtt ? agp interface multi-transaction timer register (device #0) address offset: bch default value: 00h access: read/write size: 8 bits amtt is an 8-bit register that controls the amount of time that the gmch ?s arbiter allows agp/pci master to perform multiple back-to-back transactions. the gmch ?s amtt mechanism is used to optimize the performance of the agp master (using pci semantics) that performs multiple back-to-back transactions to fragmented memory ranges (and as a consequence it can not use long burst transfers). the amtt mechanism applies to the cpu-agp/pci transactions as well and it guarantees to the cpu a fair share of the agp/pci interface bandwidth. the number of clocks programmed in the amtt re presents the guaranteed time slice (measured in 66- mhz clocks) allotted to the current agent (either agp/pci master or host bridge) after which the agp arbiter will grant the bus to another agent. the default value of amtt is 00h and disables this function. the amtt value can be programmed with 8 clock granularity. for example, if the amtt is programmed to 18h, then the selected value corresponds to the time period of 24 agp (66 mhz) clocks. bit description 7:3 multi-transaction timer count value . the number programmed in these bits represents the guaranteed time slice (measured in eight 66 mhz clock granularity) allotted to the current agent (either agp/pci master or host bridge) after which t he agp arbiter will grant the bus to another agent. 2:0 reserved .
register description r datasheet 85 4.8.33 lptt ? low priority transaction timer register (device #0) address offset: bdh default value: 00h access: read/write size: 8 bits lptt is an 8-bit register similar in a function to amtt. this register is used to control the minimum tenure on the agp for low priority data transaction (both reads and writes) issued using pipe# or sb mechanisms. the number of clocks programmed in the lptt repr esents the guaranteed time slice (measured in 66 mhz clocks) allotted to the current low priority agp transaction data transfer state. this does not necessarily apply to a single transaction but it can span over multiple low-priority transactions of the same type. after this time expires the agp arbiter may grant the bus to another agent if there is a pending request. the lptt does not apply in the case of high-priority request where ownership is transferred directly to high-prior ity requesting queue. the default value of lptt is 00h and disables this function. the lptt value can be programmed with 8 clock granularity. for example, if the lptt is programmed to 10h, then the selected value corresponds to the time period of 16 agp (66 mhz) clocks. bit description 7:3 low priority transaction timer count value . the number of clocks programmed in these bits represents the guaranteed time slice (measured in ei ght 66 mhz clock granularity) allotted to the current low priority agp transaction data transfer state. 2:0 reserved. 4.8.34 hem ? host error control, status and observation (device #0) address offset: f0?f3h default value: 0000000000h access: read/write, ro size: 32 bits bit description 31 detected hadstb1# glitch (astb1gl): this bit is set when the gmch has detected a glitch on address strobe hadstb1#. software must write a 1 to clear this status bit. 30 detected hadstb0# glitch (astb0gl): this bit is set when the gmch has detected a glitch on address strobe hadstb0#. software must write a 1 to clear this status bit. 29 detected hdstb3# glitch (dstb3gl): this bit is set when the gmch has detected a glitch on data strobe pair hdstb3#. software must write a 1 to clear this status bit. 28 detected hdstb2# glitch (dstb2gl): this bit is set when the gmch has detected a glitch on data strobe pair hdstb2#. software must write a 1 to clear this status bit. 27 detected hdstb1# glitch (dstb1gl): this bit is set when the gmch has detected a glitch on data strobe pair hdstb1#. software must write a 1 to clear this status bit.
register description r 86 datasheet 4.9 intel ? 855gm/gme gmch main memory control, memory i/o control registers (device #0, function #1) the following table shows the gmch configur ation space for device #0, function #1. see section 4.2f or access nomenclature. table 27. host-hub i/f bridge/system memory controller configuration space (device #0, function#1) register name register symbol register start register end default value access vendor identification vid 00 01 8086h ro device identification did 02 03 3584h ro pci command pcicmd 04 05 0006h ro,r/w pci status pcists 06 07 0080h ro,r/wc revision identification rid 08 08 02h ro sub-class code subc 0a 0a 80h ro base class code bcc 0b 0b 08h ro header type hdr 0e 0e 80h ro subsystem vendor identification svid 2c 2d 0000h r/wo subsystem identification sid 2e 2f 0000h r/wo capabilities pointer capptr 34 34 00h ro dram row 0-3 boundary drb 40 43 00000000h rw dram row 0-3 attribute dra 50 51 7777h rw dram timing drt 60 63 18004425h rw dram controller power management control pwrmg 68 6b 00000000h r/w dram controller mode drc 70 73 00000081h r/w dram throttle control dtc a0 a3 00000000h r/w/l
register description r datasheet 87 4.9.1 vid ? vendor identification register address offset: 00-01h default value: 8086h access: read only size: 16 bits the vid register contains the vendor identification number. this 16-bit register combined with the device identification register uniquely identifies any pci device. writes to this register have no effect. bit description 15:0 vendor identification (vid): this register field contains the pci standard identification for intel. 4.9.2 did ? device identification register address offset: 02-03h default value: 3584h access: read only size: 16 bits this 16-bit register combined with the vendor identification register uniquely identifies any pci device. writes to this register have no effect. bit description 15:0 device identification number (did): this is a 16-bit value assigned to the gmch host? hi bridge function #1 (3584h).
register description r 88 datasheet 4.9.3 pcicmd ? pci command register address offset: 04-05h default value: 0006h access: read only, read/write size: 16 bits since intel chipset device #0 does not physically reside on pci_a, many of the bits are not implemented. bit description 15:10 reserved 9 fast back-to-back enable (fb2b): this bit controls whether or not the master can do fast back-to- back write. since device #0 is strictly a target, this bit is not implemented and is hardwired to 0. writes to this bit position have no affect. 8 serr enable (serre): serr# is not implemented by function #1 of device #0 of the gmch and this bit is hardwired to 0. writes to this bit position have no effect. 7 address/data stepping enable (adstep): address/data stepping is not implemented in the gmch, and this bit is hardwired to 0. writes to this bit position have no effect. 6 parity error enable (perre): perr# is not implemented by gmch and this bit is hardwired to 0. writes to this bit position have no effect. 5 vga palette snoop enable (vgasnoop): the gmch does not implement this bit and it is hardwired to a 0. writes to this bit position have no effect. 4 memory write and invalidate enable (mwie): the gmch will never issue memory write and invalidate commands. this bit is therefore hardwired to 0. writes to this bit position will have no effect. 3 special cycle enable (sce): the gmch does not implement this bit and it is hardwired to a 0. writes to this bit position have no effect. 2 bus master enable (bme): the gmch is always enabled as a master on hi. this bit is hardwired to a 1. writes to this bit position have no effect. 1 memory access enable (mae): the gmch always allows access to main system memory. this bit is not implemented and is hardwired to 1. writ es to this bit position have no effect. 0 i/o access enable (ioae): this bit is not implemented in the gm ch and is hardwired to a 0. writes to this bit position have no effect.
register description r datasheet 89 4.9.4 pcists ? pci status register address offset: 06-07h default value: 0080h access: read only, read/writeclear size: 16 bits pcists is a 16-bit status register that reports the occurrence of error ev ents on device #0?s pci interface. bit 14 is read/write clear. all other bits are read on ly. since gmch device #0 does not physically reside on pci_a, many of the bits are not implemented. bit description 15 detected parity error (dpe): the gmch does not implement this bit and it is hardwired to a 0. writes to this bit position have no effect. 14 signaled system error (sse): the gmch does not implement this bit and it is hardwired to a 0. writes to this bit position have no effect. 13 received master abort status (rmas): the gmch does not implement this bit and it is hardwired to a 0. writes to this bit position have no effect. 12 received target abort status (rtas): the gmch does not implement this bit and it is hardwired to a 0. writes to this bit position have no effect. 11 signaled target abort status (stas): the gmch does not implement this bit and it is hardwired to a 0. writes to this bit position have no effect. 10:9 devsel timing (devt): these bits are hardwired to ?00?. writes to these bit positions have no affect. device #0 does not physically connect to pci_a. these bits are set to ?00? (fast decode) so that the gmch does not limit optimum devsel timing for pci_a. 8 master data parity error detected (dpd): the gmch does not implement this bit and it is hardwired to a 0. writes to this bit position have no effect. 7 fast back-to-back (fb2b): this bit is hardwired to 1. writes to these bit positions have no effect. device #0 does not physically connect to pci_a. this bit is set to 1 (indicating fast back-to-back capability) so that the gmch does not limit the optimum setting for pci_a. 6:5 reserved 4 capability list (clist): this bit is hardwired to 0 to indicate to the configuration software that this device/function does not implement new capabilities. default value = 0 3:0 reserved
register description r 90 datasheet 4.9.5 rid ? revision identification register address offset: 08h default value: 02h access: read only size: 8 bits this register contains the revision number of the intel 855gm/gme gmch device #0. these bits are read only and writes to this register have no effect. bit description 7:0 revision identification number (rid): this is an 8-bit value that i ndicates the revision identification number for the gmch device #0. 4.9.6 subc ? sub-class code register address offset: 0ah default value: 80h access: read only size: 8 bits this register contains the sub-class code for the intel 855gm/gme gmch device #0. this code is 80h indicating other peripheral device. bit descriptions 7:0 sub-class code (subc): this is an 8-bit value that indicate s the category of peripheral device into which the gmch function #1 falls. the code is 80h indicating other peripheral device. 4.9.7 bcc ? base class code register address offset: 0bh default value: 08h access: read only size: 8 bits this register contains the base class code of the intel 855gm/gme gmch device #0 function #1. this code is 08h indicating other peripheral device. bit description 7:0 base class code (basec): this is an 8-bit value that indicates the base class code for the gmch. this code has the value 08h, indi cating other peripheral device.
register description r datasheet 91 4.9.8 hdr ? header type register address offset: 0eh default value: 80h access: read only size: 8 bits this register identifies th e header layout of the configuration space. no physical register exists at this location. bit description 7:0 pci header (hdr): this field always returns 80 to indicate that device #0 is a multifunction device. reads and writes to this location have no effect. 4.9.9 svid ? subsystem vendor identification register address offset: 2c-2dh default value: 0000h access: read/write once size: 16 bits this value is used to identify the vendor of the subsystem. bit description 15:0 subsystem vendor id (subvid): this field should be programmed during boot-up to indicate the vendor of the system board. after it has been written once, it becomes read only. 4.9.10 sid ? subsystem identification register address offset: 2e-2fh default value: 0000h access: read/write once size: 16 bits this value is used to identify a particular subsystem. bit description 15:0 subsystem id (subid): this field should be programmed during bios initialization. after it has been written once, it becomes read only.
register description r 92 datasheet 4.9.11 capptr ? capabilities pointer register address offset: 34h default value: 00h access: read only size: 8 bits the capptr provides the offset that is the pointer to the location of the first device capability in the capability list. bit description 7:0 pointer to the offset of the first capability id register block: in this case there are no capabilities, therefore these bits are hardwired to 00h to indicate the end of the capability linked list. 4.9.12 drb ? dram row (0:3) boundary register (device #0) address offset: 40-43h default value: 00h each access: read/write size: 8 bits each the ddr sdram row boundary register defines the upper boundary address of each ddr sdram row with a granularity of 32-mb. each row has its own single-byte drb register. for example, a value of 1 in drb0 indicates that 32-mb of ddr sdram has been populated in the first row. since the gmch supports a total of fo ur rows of system memory, drb0-3 are used. the registers from 44h-4fh are reserved for drbs 4-15. row0: 40h row1: 41h row2: 42h row3: 43h 44h to 4fh is reserved. drb0 = total system memory in row0 (in 32 -mb increments) drb1 = total system memory in row0 + row1 (in 32 -mb increments) drb2 = total system memory in row0 + row1 + row2 (in 32 -mb increments) drb3 = total system memory in row0 + ro w1 + row2 + row3 (in 32- mb increments) each row is represented by a byte. each byte has the following format. bit description 7:0 ddr sdram row boundary address: this 8-bit value defines the upper and lower addresses for each ddr sdram row. this 8-bit value is compared agai nst a set of address lines to determine the upper address limit of a particular row. also the mini mum system memory supported is 64-mb in 64-mb granularity; hence bit 0 of this register must be programmed to a zero.
register description r datasheet 93 4.9.13 dra ? dram row attribute register (device #0) address offset: 50-51h default value: 77h each access: read/write size: 8 bits the ddr sdram row attribute register defines the page sizes to be used when accessing different pairs of rows. each nibble of information in the dra registers describes the page size of a pair of rows: row0, 1: 50h row2, 3: 51h 52h-5fh: reserved. 7 6 4 3 2 0 r row attribute for row1 r row attribute for row0 7 6 4 3 2 0 r row attribute for row3 r row attribute for row2 bit description 7 reserved 6:4 row attribute for odd-numbered row: this field defines the page size of the corresponding row. 000: reserved 001: 4 kb 010: 8 kb 011: 16 kb 111: not populated others: reserved 3 reserved 2:0 row attribute for even-numbered row: this field defines the page size of the corresponding row. 000: reserved 001: 4 kb 010: 8 kb 011: 16 kb 111: not populated others: reserved
register description r 94 datasheet 4.9.14 drt ? dram timing register (device #0) address offset: 60-63h default value: 18004425h access: read/write size: 32 bits this register controls the timing of the ddr sdram controller. bit description 31 ddr internal write to read command delay (twtr): the twtr is a std. ddr sdram timing parameter with a value of 1 ck for cl=2 and 2.5. the twtr is used to time rd command after a wr command (to same row): 0: twtr is set to 1 clock (ck), used for ddr sdram cl=2 or 2.5 1: reserved 30 ddr write recovery time (twr): write recovery time is a std. ddr timing parameter wi th the value of 15 ns. it should be set to 2 ck when ddr200 is used. the twr is used to time pr e command launch after a wr command, when ddr sdram components are populated. 0: twr is set to 2 clocks (ck) 1: twr is set to 3 clocks (ck) 29:28 back to back write-read commands spacing (ddr different rows/bank ): this field determines the wr- rd command spacing, in terms of common clocks for ddr sdram based on the following formula: dqss + 0.5xbl + ta (wr-rd) ? cl dqss: is time from write command to data and is always 1 ck bl: is burst length and can be set to 4. ta (wr-rd): is required dq turn-around, can be set to 1 or 2 ck cl: is cas latency, can be set to 2 or 2.5 examples of usage: for bl=4, with single dq turn-around and cl=2, this field must be set to 2 ck (1+2+1-2) encoding ck between wr and rd commands 00: 4 01: 3 10: 2 11: reserved
register description r datasheet 95 bit description 27:26 back to back read-write commands spacing (ddr, same or different rows/bank): this field determines the rd-wr command spacing, in terms of common clocks based on the following formula: cl + 0.5xbl + ta (rd-wr) ? dqss dqss: is time from write command to data and is always 1 ck bl: is burst length which is set to 4 ta (rd-wr): is required dq turn-around, can be set to 1, 2 or 3 ck cl: is cas latency, can be set to 2 or 2.5 examples of usage: for bl=4, with single dq turn-around and cl=2, this field must be set to 4 ck (2+2+1-1) encoding ck between rd and wr commands 00: 7 01: 6 10: 5 11: 4 note: since reads in ddr sdram cannot be terminated by writes, the space between commands is not a function of cycle length but of burst length. 25 back to back read-read commands spacing (ddr, different rows): this field determines the rd-rd command spacing, in terms of common clocks based on the following formula: 0.5xbl + ta(rd-rd) bl: is burst length and can be set to 4. ta (rd-rd): is required dq turn -around, can be set to 1 or 2 ck examples of usage: for bl=4, with single dq turn-around, this field must be set to 3 ck (2+1) encoding ck between rd and rd commands 0: 4 1: 3 note: since a read to a different row does not termi nate a read, the space between commands is not a function of cycle length but of burst length. 24:15 reserved
register description r 96 datasheet bit description 14:12 refresh cycle time (trfc): refresh cycle time is measured for a given row from ref command (to perform a refresh) until following act to same row (to perform a read or write). it is tracked separately from trc for ddr sdram. current ddr sdram spec requires trfc of 75 ns ( ddr266) and 80 ns (ddr200). therefore, this field will be set to 8 clocks for ddr200, 10 clocks for ddr266. encoding trfc 000: 14 clocks 001: 13 clocks 010: 12 clocks 011: 11 clocks 100: 10 clocks 101: 9 clocks 110: 8 clocks 111: 7 clocks 11 activate to precharge delay (tras), max: this bit controls the maximum number of clocks that a ddr sdram bank can remain open. after this time period, the system memory controller will guar antee to pre-charge the bank. note that this time period may or may not be set to overlap with time period that requires a refresh to happen. the ddr sdram controller includes a separate tras- max counter for every supported bank. with a maximum of four rows and four banks per row, there are 16 counters. 0: 120 micro-seconds 1: reserved. 10:9 activate to precharge delay (tras), min: this bit controls the number of ddr sdram clocks for tras min 00: 8 clocks 01: 7 clocks 10: 6 clocks 11: 5 clocks 8:7 reserved 6:5 cas# latency (tcl): encoding ddr sdram cl 00: 2.5 01: 2 10: reserved 11: reserved 4 reserved
register description r datasheet 97 bit description 3:2 ddr sdram ras# to cas# delay (trcd): this bit controls the number of clocks inserted between a row activate command and a read or write command to that row. encoding trcd 00: 4 ddr sdram clocks (ddr 333 sdram) 01: 3 ddr sdram clocks 10: 2 ddr sdram clocks 11: reserved 1:0 ddr sdram ras# precharge (trp): this bit controls the number of clocks that are inserted between a row precharge command and an activate command to the same row. encoding trp 00: 4 ddr sdram clocks (ddr 333 sdram) 01: 3 ddr sdram clocks 10: 2 ddr sdram clocks 11: reserved
register description r 98 datasheet 4.9.15 pwrmg ? dram controller power management control register (device #0) address offset: 68h-6bh default value: 00000000h access: read/write size: 32 bits bit description 31:24 reserved 23:20 row state control: this field determines the number of clocks the system memory controller will remain in the idle state before it begins pre-charging all pages or powering down rows. - pden: power down enable - pcen: page close enable - tc: timer control pden(23): pcen(22): tc(21:20) function 0 0 xx all disabled 0 1 xx reserved 1 0 xx reserved 1 1 00 immediate precharge and powerdown 1 1 01 reserved 1 1 10 precharge and power down after 16 ddr sdram clocks 1 1 11 precharge and power down after 64 ddr sdram clocks 19:16 reserved 15 self refresh gmch memory interface data bus power management optimization enable: 0 = enable 1 = disable 14 cs# signal drive control: 0 = enable cs# drive control, based on rules described in drc bit 12. 1 = disable cs# drive control, based on rules described in drc bit 12. 13 self refresh gmch memory interface data bus power management: 0 = in self refresh mode gmch power management is enabled. 1 = in self refresh mode the gmch power management is disabled. 12 dynamic memory interface power management: 0 = dynamic memory interface power management enabled. 1 = dynamic memory interface power management disabled.
register description r datasheet 99 bit description 11 rcven dll shutdown disable: 0 = normal operation. rcven dll is turned off when the corresponding so-dimm is unpopulated. 1 = rcven dll is turned on irrespective of so-dimm population. 10 ecc so-dimm clock tri-state disable: 0 = when ddr sdram ecc is not enabled, the ecc clocks (i.e., sck2/sck2#, sck5/sck5#,) are tri- stated. 1 = when ddr sdram ecc is enabled, the ecc clocks (i.e., sck2/sck2#, sck5/sck5#,) are treated just like the other clocks. 9:1 reserved 0 power state s1/s3 refresh control: 0 = normal operation, pending refreshes are not co mpleted before entering self refresh for s1/s3. 1 = all pending refreshes plus one extra is perfo rmed before entering self refresh for s1/s3. 4.9.16 drc ? dram controller mode register (device #0) address offset: 70-73h default value: 00000081h access: ro, read/write size: 32 bits bit description 31:30 revision number (rev): reflects the revision number of the format used for ddr sdram register definition (read only). 29 initialization complete (ic): this bit is used for communication of software state between the memory controller and the bios. bios sets this bit to 1 a fter initialization of the ddr sdram memory array is complete. setting this bit to a 1 enables ddr sdra m refreshes. on power up and s3 exit, the bios initializes the ddr sdram array and sets this bit to a 1. this bit works in combination with the rms bits in controlling refresh state: ic refresh state 0 off 1 on 28:24 reserved 23:22 number of channels (chan): reflects that gmch supports only one system memory channel. 00 one channel is populated appropriately others: reserved 21:20 ddim ddr sdram data integrity mode: 00: no-ecc. no read-merge-write on partial writes. e cc data sense-amps are disabled and the data output is tristate (default). 01: ecc xx: reserved
register description r 100 datasheet bit description 19:16 reserved 15 ras lock-out enable: set to a 1 if all populated rows support ras lock-out. defaults to 0. if this bit is set to a 1 the ddr sdram controller assumes that the ddr sdram guarantees tras min before an auto precharge (ap) completes (note: an ap is sent with a read or a write command). also, the ddr sdram controller does not issue an activate command to the auto pre-charged bank for trp. if this bit is set to a 0 the ddr sdram contro ller does not schedule an ap if tras min is not met. 14:13 reserved 12 address tri-state enable (adrtrien): when set to a 1, the sdram controller will tri-state the ma, cmd, and cs# (only when all ckes are deasserted). note that when cke to a row is deasserted, fast chip select assertion is not permitted by the hardware. ckes deassert based on idle timer and/or max row count control. 0:- address tri-state disabled 1:- address tri-state enabled 11:10 reserved 9:7 refresh mode select (rms) : this field determines whether refres h is enabled and, if so, at what rate refreshes will be executed. 000: refresh disabled 001: refresh enabled. refresh interval 15.6 sec 010: refresh enabled. refresh interval 7.8 sec 011: reserved. 111: refresh enabled. refresh interval 64 clocks (fast refresh mode) other: reserved any change in the programming of this field resets t he refresh counter to zero. this function is for testing purposes, it allows test program to align re fresh events with the test and thus improve failure repeatability. 6:4 mode select (sms). these bits select the special operati onal mode of the ddr sdram interface. the special modes are intended for initialization at power up. 000: post reset state ? when the gmch exits reset ( power-up or otherwise), the mode select field is cleared to 000. software is not expected to write this va lue, however if this value is written, there are no side effects (no self refresh or any other special ddr sdram cycle). during any reset sequence, while power is applied and reset is active, the gmch deasserts all cke signals. after internal reset is deasserted, cke signal s remain deasserted until this field is written to a value different than 000. on this event, all cke signals are asserted. during suspend (s3, s4), gmch internal signal triggers ddr sdram controller to flush pending commands and enter all rows into self-refresh mode. as part of resume sequence, gmch will be reset , which will clear this bit field to 000 and main tain cke signals deasserted. after internal reset is deasserted, cke signals remain deasserted until this field is written to a value different than 000. on this event, all cke signals are asserted. during entry to other low power states (c3, s1-m), gmch internal signal triggers ddr sdram controller to flush pending commands and enter all ro ws in s1 and relevant rows in c3 (based on rpdnc3) into self-refresh mode. during exit to normal mode, the gmch signal triggers ddr sdram controller to exit self-refresh and resume normal operation without s/w involvement. 001: nop command enable ? all cpu cycles to ddr sdram result in a nop command on the ddr sdram interface. 010: all banks pre-charge enable ? all cpu cycles to ddr sdram result in an all banks precharge command on the ddr sdram interface.
register description r datasheet 101 bit description 011: mode register set enable ? all cpu cycles to ddr sdram result in a mode register set command on the ddr sdram interface. host addre ss lines are mapped to ddr sdram address lines in order to specify the command sent. host address ha[13:3] are mapped to memory address sma[11,9:0]. sma3 must be driven to 1 for interleave wrap type. for double data rate ma[6:4] needs to be driven based on the value programmed in the cas# latency field. cas latency ma[6:4 ] 1.5 clocks 001 2.0 clocks 010 2.5 clocks 110 sma[7] should always be driven to a 0. sma[8] should be driven to a 1 for dll reset and 1 for normal operation. sma[12:9] must be driven to 00000. bios must calculate and drive the correct host address for each row of memory such that the correct command is driven on the sma[12:0] lines. note that smab[5,4,2,1]# are inverted from sma[5,4,2,1]; bios must account for this. 100: extended mode register set enable ? all cpu cycles to ddr sdram result in an ?extended mode register set? command on the ddr sdram in terface. host address lines are mapped to ddr sdram address lines in order to specify the command sent. host address lines are mapped to ddr sdram address lines in order to specify the co mmand sent. host address ha[13:3] are mapped to memory address sma[11,9:0]. sma[0] = 0 for dll enabl e and 1 for dll disable. all the other sma lines are driven to 0?s. note that smab[5,4,2,1]# are inve rted from sma[5,4,2,1]; bios must account for this. 101: reserved 110: cbr refresh enable ? in this mode all cpu cycl es to ddr sdram result in a cbr cycle on the ddr sdram interface 111: normal operation 3:0 reserved 4.9.17 dtc ? dram throttling control register (device #0) offset address: a0?a3h default value: 00000000h access: read/write/lock size: 32 bits throttling is independent for system memory banks, gmch writes, and thermal sensor trips. read and write bandwidth is measured indepe ndently for each bank. if the number of octal - words (16 bytes) read/written during the window defined below (global ddr sdram sampling window: gdsw) exceeds the ddr sdra m bandwidth threshold, then the ddr sdram throttling mechanism will be invoked to limit ddr sdram reads/writes to a lower bandwidth checked over smaller time windows. the throttling will be active for the remainder of the current gdsw and for the next gdsw after which it will return to non-throttling mode. the throttling mechanism accounts for the actual bandw idth consumed during the sampling window, by reducing the allowed bandwidth within the smaller throttling window based on the bandwidth
register description r 102 datasheet consumed during the sampling period. although bandwidth from/to independent rows and gmch write bandwidth is measured independently, once tripped all transactions except high priority graphics reads are subject to throttling. bit description 31:28 ddr sdram throttle mode (tmode): four bits control which mechanisms for thrott ling are enabled in an ?or? fashion. counter-based throttling is lower priority than thermal trip s throttling when both are enabled and tripped. counter- based trips point throttling values and thermal-based trip point throttling values are specified in this register. if the counter and thermal mechanisms for either rank or gmch are both enabled, throttle settings for the one that trips first is used until the end of the second gdsw. [rank counter, gmch write counter, rank thermal sensor, gmch thermal sensor] 0000 = throttling turned off. this is the default setting. all counters are off. 0001 = only gmch thermal sensor based thrott ling is enabled. if gmch thermal sensor is tripped, write throttling begins based on the setting in wttc. 0010 = only rank thermal sensor based thro ttling is enabled. when the external so-dimm thermal sensor is tripped, ddr sdram thro ttling begins based on the setting in rttc. 0011 = both rank and gmch thermal sensor based throttling is enabled. when the external so- dimm thermal sensor is tripped ddr sdram thrott ling begins based on the setting in rttc. if the gmch thermal sensor is tripped, write th rottling begins based on the setting in wttc. 0100 = only the gmch write counter mechanism is enabled. when the length of write transfers programmed (gdsw * wctc) is reached, dram throttling begins based on the setting in wctc . . 0101 = gmch thermal sensor and gmch writ e ddr sdram counter mechanisms are both enabled. if the gmch write ddr sdram counter me chanism threshold is reached, ddr sdram throttling begins based on the setting in wctc. if the gmch thermal sensor is tripped, ddr sdram throttling begins based on the setting in w ttc. if both threshold mechanisms are tripped, the ddr sdram throttling begins based on the settings in wttc. 0110 = rank thermal sensor and gmch writ e ddr sdram counter mechanisms are both enabled. if the gmch write ddr sdram counter me chanism threshold is reached, ddr sdram throttling begins based on setting in wctc. if the exte rnal so-dimm thermal s ensor is tripped, rank ddr sdram throttling begins based on the setting in rttc. 0111 = similar to 0101 for writes and when the rank thermal sensor is tripped, ddr sdram throttling begins based on the setting in rttc. 1000 = only rank counter mechanism is enabled. when the length of read transfers programmed (gdsw * rctc) is reached, dram thrott ling begins based on the setting in rctc 1001 = rank counter mechanism is enabled and gm ch thermal sensor based throttling are both enabled. if gmch thermal sensor is tripped, write throttling begins based on the setting in wttc. if the rank counter mechanism is tripped, dram throttling begins based on the setting in rctc. 1010 = rank thermal sensor and rank ddr sdra m counter mechanisms are both enabled. if the rank ddr sdram counter mechanism threshold is reached, ddr sdram throttling begins based on the setting in rctc. if the external so-dimm t hermal sensor is tripped, dram throttling begins based on the setting in rttc. 1011 = similar to 1010 and if the gmch thermal sens or is tripped, write throttling begins based on the setting in wttc. 1111 = rank and gmch thermal sensor based throttling and rank and gmch write counter based throttling are enabled. if both the writ e counter and gmch thermal sensor based mechanisms are tripped, ddr sdram throttling begi ns based on the setting allowed in wttc. if both the rank counter and rank thermal s ensor based mechanisms are tripped, ddr sdram throttling begins based on the setting allowed in rttc.
register description r datasheet 103 bit description 27:24 read counter based power throttle control (rctc): these bits select the counter based power throttle bandwidth limits for read operations to system memory. r/w, ro if throttle lock. 0h = 85% 1h = 70% 2h = 65% 3h = 60% 4h = 55% 5h = 50% 6h = 45% 7h = 40% 8h = 35% 9h = 30% ah = 20% b-fh = reserved 23:20 write counter based power throttle control (wctc): these bits select the counter based power throttle bandwidth limits for write operations to system memory. r/w, ro if throttle lock 0h = 85% 1h = 70% 2h = 65% 3h = 60% 4h = 55% 5h = 50% 6h = 45% 7h = 40% 8h = 35% 9h = 30% ah = 20% b-fh = reserved
register description r 104 datasheet bit description 19:16 read thermal based power throttle control (rttc): these bits select the thermal sensor based power throttle bandwidth limits for read operations to system memory. r/w, ro if throttle lock. 0h = 85% 1h = 70% 2h = 65% 3h = 60% 4h = 55% 5h = 50% 6h = 45% 7h = 40% 8h = 35% 9h = 30% ah = 20% b-fh = reserved 15:12 write thermal based power throttle control (wttc): these bits select the thermal based power throttle bandwidth limits for write operations to system memory. r/w, ro if throttle lock 0h = 85% 1h = 70% 2h = 65% 3h = 60% 4h = 55% 5h = 50% 6h = 45% 7h = 40% 8h = 35% 9h = 30% ah = 20% b-fh = reserved 11 counter based throttle lock (ctlock): this bit secures rctc and wctc. this bit defaults to 0. once a 1 is written to this bit, rctc and wctc (including ctlock) become read-only. 10 thermal throttle lock (ttlock): this bit secures the ddr sdram throttling control register. this bit defaults to 0. once a 1 is written to this bit, a ll of the configuration regist er bits in dtc (including ttlock) except ctlock, rctc and wctc become read-only. 9 thermal power throttle control fields enable: 0 = rttc and wttc are not used. rctc and wtct are used for both counter and thermal based throttling. 1 = rttc and wttc are used for thermal based throttling.
register description r datasheet 105 bit description 8 high priority stream throttling enable: normally high priority streams are not throttl ed when either the counter based mechanism or thermal sensor mechanism demands throttling. 0 = normal operation. 1 = block high priority streams during throttling. 7:0 global ddr sdram sampling window (gdsw): this 8-bit value is multiplied by 4 to define the length of time in milliseconds (0?1020) over which t he number of octal words (16 bytes) read/written is counted and throttling is imposed. note that progr amming this field to 00h disables system memory throttling. recommended values are between 0.25 and 0.75 seconds. 4.10 intel ? 855gm/gme gmch configuration process registers (device #0, function #3) see section 4.2 for access nomenclature. tabl e 28 summarizes all device#0, function #3 registers. table 28. configuration process conf iguration space (device#0, function #3) register name register symbol register start register end default value access vendor identification vid 00 01 8086h ro device identification did 02 03 3585h ro pci command pcicmd 04 05 0006h ro,r/w pci status pcists 06 07 0080h ro,r/wc revision identification rid 08 08 02h ro sub-class code subc 0a 0a 80h ro base class code bcc 0b 0b 08h ro header type hdr 0e 0e 80h ro subsystem vendor identification svid 2c 2d 0000h r/wo subsystem identification sid 2e 2f 0000h r/wo capabilities pointer capptr 34 34 00h ro hpll clock control hpllcc c0 c1 00h ro
register description r 106 datasheet 4.10.1 vid ? vendor identification register the vid register contains the vendor identification number. this 16-bit register combined with the device identification register uniquely identifies any pci device. writes to this register have no effect. bit description 15:0 vendor identification (vid): this register field contains t he pci standard identification for 8086h. 4.10.2 did ? device identification register address offset: 02-03h default value: 3585h access: read only size: 16 bits this 16-bit register combined with the vendor identification register uniquely identifies any pci device. writes to this register have no effect. bit description 15:0 device identification number (did): this is a 16-bit value assigned to the intel 855gm/gme gmch host-hi bridge function #3 (3585h). 4.10.3 pcicmd ? pci command register address offset: 04-05h default value: 0006h access: read only, read/write size: 16 bits since intel 855gm/gme gmch device #0 does not physically reside on pci_a many of the bits are not implemented. bit description 15:10 reserved 9 fast back-to-back enable (fb2b): this bit controls whether or not the master can do fast back-to- back write. since device #0 is strictly a target, this bit is not implemented and is hardwired to 0. writes to this bit position have no effect. 8 serr enable (serre): serr# is not implemented by function #1 of device #0 of the gmch and this bit is hardwired to 0. writes to this bit position have no effect. 7 address/data stepping enable (adstep): address/data stepping is not implemented in the gmch, and this bit is hardwired to 0. writes to this bit position have no effect. 6 parity error enable (perre): perr# is not implemented by gmch and this bit is hardwired to 0. writes to this bit position have no effect. 5 vga palette snoop enable (vgasnoop): the gmch does not implement this bit and it is hardwired to a 0. writes to this bit position have no effect.
register description r datasheet 107 bit description 4 memory write and invalidate enable (mwie): the gmch will never issue memory write and invalidate commands. this bit is therefore hardwired to 0. writes to this bit position will have no effect. 3 special cycle enable (sce): the gmch does not implement this bit and it is hardwired to a 0. writes to this bit position have no effect. 2 bus master enable (bme): the gmch is always enabled as a master on hi. this bit is hardwired to a 1. writes to this bit position have no effect. 1 memory access enable (mae): the gmch always allows access to main memory. this bit is not implemented and is hardwired to 1. writes to this bit position have no effect. 0 i/o access enable (ioae): this bit is not implemented in the gm ch and is hardwired to a 0. writes to this bit position have no effect. 4.10.4 pcists ? pci status register address offset: 06-07h default value: 0080h access: read only, read/writeclear size: 16 bits pcists is a 16-bit status register that reports the occurrence of error ev ents on device #0?s pci interface. bit 14 is read/write clear. all other bits are read only. since gmch device #0 does not physically reside on pci_a many of the bits are not implemented. bit description 15 detected parity error (dpe): the gmch does not implement this bit and it is hardwired to a 0. writes to this bit position have no effect. 14 signaled system error (sse): the gmch does not implement this bit and it is hardwired to a 0. writes to this bit position have no effect. 13 received master abort status (rmas): the gmch does not implement this bit and it is hardwired to a 0. writes to this bit position have no effect. 12 received target abort status (rtas): the gmch does not implement this bit and it is hardwired to a 0. writes to this bit position have no effect. 11 signaled target abort status (stas): the gmch does not implement this bit and it is hardwired to a 0. writes to this bit position have no effect. 10:9 devsel timing (devt): these bits are hardwired to "00". writes to these bit positions have no affect. device #0 does not physically connect to pci_a. these bits are set to "00" (fast decode) so that the gmch does not limit optimum devsel timing for pci_a. 8 master data parity error detected (dpd): the gmch does not implement this bit and it is hardwired to a 0. writes to this bit position have no effect. 7 fast back-to-back (fb2b): this bit is hardwired to 1. writes to these bit positions have no effect. device #0 does not physically connect to pci_a. this bit is set to 1 (indicating fast back-to-back capability) so that the gmch does not limit the optimum setting for pci_a. 6:5 reserved 4 capability list (clist): this bit is hardwired to 0 to indicate to the configuration software that this device/function does not implement new capabilities. 3:0 reserved
register description r 108 datasheet 4.10.5 rid ? revision identification register address offset: 08h default value: 02h access: read only size: 8 bits this register contains the revision number of the intel 855gm/gme gmch. these bits are read only and writes to this register have no effect. bit description 7:0 revision identification number (rid): this is an 8-bit value that i ndicates the revision identification number for the gmch. 4.10.6 subc ? sub-class code register address offset: 0ah default value: 80h access: read only size: 8 bits this register contains the sub-class code for the intel 855gm/gme gmch device #0. this code is 80h indicating a peripheral device. bit description 7:0 sub-class code (subc): this is an 8-bit value that indicate s the category of bridge into which gmch falls. the code is 80h indicati ng other peripheral device. 4.10.7 bcc ? base class code register address offset: 0bh default value: 08h access: read only size: 8 bits this register contains the base class code of the intel 855gm/gme gmch device #0 function #3. this code is 08h indicating a peripheral device. bit description 7:0 base class code (basec): this is an 8-bit value that indica tes the base class code for the gmch. this code has the value 08h, indi cating other peripheral device.
register description r datasheet 109 4.10.8 hdr ? header type register address offset: 0eh default value: 80h access: read only size: 8 bits this register identifies th e header layout of the configuration space. no physical register exists at this location. bit description 7:0 pci header (hdr): this field always returns 80 to indicate that device #0 is a multifunction device. if functions other than #0 are disabled this field returns a 00 to indi cate that the gmch is a single function device with standard header layout. the default is 80 reads and writes to this location have no effect. 4.10.9 svid ? subsystem vendor identification register address offset: 2c-2dh default value: 0000h access: read/write once size: 16 bits this value is used to identify the vendor of the subsystem. bit description 15:0 subsystem vendor id (subvid): this field should be programmed during boot-up to indicate the vendor of the system board. after it has been written once, it becomes read only. 4.10.10 id ? subsystem identification register address offset: 2e-2fh default value: 0000h access: read/write once size: 16 bits this value is used to identify a particular subsystem. bit description 15:0 subsystem id (subid): this field should be programmed during bios initialization. after it has been written once, it becomes read only.
register description r 110 datasheet 4.10.11 capptr ? capabilities pointer register address offset: 34h default value: 00h access: read only size: 8 bits the capptr provides the offset that is the pointer to the location of the first device capability in the capability list. bit description 7:0 pointer to the offset of the first capability id register block: in this case there are no capabilities therefore these bits are hardwired to 00h to indicate the end of the capability-linked list. 4.10.12 hpllcc ? hpll clock control register (device #0) address offset: c0?c1h default value: 00h access: read only size: 16 bits bit description 15:11 reserved 10 hpll vco change sequence initiate bit : software must write a 0 to clear this bit and then write a 1 to initiate sequence again. 9 hphase reset bit: 1 = assert 0 = deassert (default) 8 reserved 7:2 reserved 1:0 hpll clock control: software is allowed to update this register. see table 29 below.
register description r datasheet 111 table 29. intel ? 855gm gmch configurations and some resolution examples straps read through hpllcc[2:0]: d0:f3:regist er offset c0- c1h, bits[2:0] fsb rate system memory frequency gfx core clock(low) gfx core clock (high) lvds port dvo port crt port 1400x1050@75 hz dclk = 155 mhz 1400x1050@ 85 hz dclk = 177 mhz 133 mhz 1400x1050 @ 60 hz dclk = 108 mhz 1600x1200@60 hz dclk = 162 mhz 1600x1200@85-hz dclk = 229 mhz 1600x1200@85 hz dclk = 229- mhz 1600x1200@85-hz dclk = 229 mhz 000 400 mhz 266 mhz 200 mhz 1600x1200 @ 60 hz dclk = 162 mhz 2048x1536@72 hz dclk = 324 mhz 2048x1536@75 hz dclk = 340 mhz 1400x1050@85 hz dclk = 177 mhz 1400x1050@ 85 hz dclk = 177 mhz 100 mhz 1024x768 @ 60 hz dclk = 65 mhz 1920x1080@60 hz dclk = 172 mhz 1920x1080@ 60 hz dclk = 172 mhz 1600x1200@85 hz dclk = 229 mhz 1600x1200@85 hz dclk = 229 mhz 001 400 mhz 200 mhz 200 mhz 1600x1200 @ 60 hz dclk = 162 mhz 2048x1536@72 hz dclk = 324 mhz 2048x1536@75 hz dclk = 340 mhz 1400x1050@85 hz dclk = 177 mhz 1400x1050@ 85 hz dclk = 177 mhz 100 mhz 1024x768 @ 60 hz dclk = 65 mhz 1920x1080@60 hz dclk = 172 mhz 1920x1080@ 60 hz dclk = 172 mhz 1400x1050@75-hz dclk = 155 mhz 1400x1050@85 hz dclk = 177 mhz 010 400 mhz 200 mhz 133 mhz 1400x1050 @ 60 hz dclk = 108 mhz 1600x1200@60 hz dclk = 162 mhz 1600x1200@85 hz dclk = 229 mhz
register description r 112 datasheet table 30. for intel ? 855gme gmch configurations and some resolution examples straps read through hpllcc[2:0]: d0:f3:register offset c0-c1h, bits[2:0] fsb rate system memory frequency gfx core clock(low) gfx core clock (high) lvds port dvo port vga port 133 mhz n/a n/a n/a 1600x1200@ 85 hz dclk = 229 mhz 1600x1200@85 hz dclk = 229 mhz 000 400 mhz 266 mhz 200 mhz 1600x1200@6 0 hz dclk = 162 mhz 2048x1536@ 72 hz dclk = 324 mhz 2048x1536 @ 75 hz dclk = 340 mhz 100 mhz n/a n/a n/a 1600x1200@85h z dclk = 229 mhz 1600x1200 @ 85 hz dclk = 229 mhz 001 400 mhz 200 mhz 200 mhz 1600x1200 @60 hz dclk = 162 mhz 2048x1536 @ 72 hz dclk = 324 mhz 2048x1536 @75hz dclk = 340 mhz 100 mhz n/a n/a n/a 1400x1050 @ 75 hz dclk = 155 mhz 1400x1050@ 85 hz dclk = 177 mhz 010 400 mhz 200 mhz 133 mhz 1400x1050@6 0hz dclk = 108 mhz 1600x1200 @ 60 hz dclk = 162 mhz 1600x1200 @ 85 hz dclk = 229 mhz 166 mhz n/a n/a n/a 111 400 mhz 333 mhz 250 mhz 1600x1200@6 0hz dclk = 162 mhz 1600x1200 @ 85 hz dclk = 229 mhz 2048x1536@ 72 hz dclk = 324 mhz 1600x1200 @ 85 hz dclk = 229 mhz 2048x1536@ 75 hz dclk = 340 mhz note: the maximum calculated display pipe dot clocks were used to select supporting resolutions/refresh rates from the vesa table. memory bandwidth, simultaneous functions, and vga mode support were not accounted for in determin ing the resolutions supported. in all cases, only single pipe was used to determine the resolution supported ? lvds is only supported on a single wide pipe b, and dvo and vga resolution.
register description r datasheet 113 4.11 intel ? 852gm gmch integrated graphics device registers (device #2, function #0) this section contains the pci configuration regist ers listed in order of ascending offset address. device #2 incorporates function #0. s ee section 4.2 for access nomenclature. note: c0f0 = copy of function #0 and u1f1 = unique in function #1. table 31. integrated graphics device c onfiguration space (device #2, function#0) register name register symbol address offset register end default value access regs in function#1 vendor identification vid 00h 01h 8086h ro c0f0 device identification did 02h 03h 3582h ro c0f0 pci command pcicmd 04h 05h 0000h ro,r/w u1f1 pci status pcists 06h 07h 0090h ro u1f1 revision identification rid 08h 08h 02h ro c0f0 class code cc 09h 0bh 030000h ro u1f1 cache line size cls 0ch 0ch 00h ro c0f0 master latency timer mlt 0dh 0dh 00h ro c0f0 header type hdr 0eh 0eh 00h ro c0f0 graphics memory range address gmadr 10h 13h 00000008h ro,r/w u1f1 memory mapped range address mmadr 14h 17h 00000000h ro,r/w u1f1 io range iobar 18h 1bh 00000001h ro,r/w ? subsystem vendor id svid 2ch 2dh 0000h r/wo c0f0 subsystem id sid 2eh 2fh 0000h r/ wo c0f0 video bios rom base address romadr 30h 33h 00000000h ro c0f0 interrupt line intrline 3ch 3ch 00h ro in f #1,r/w ? interrupt pin intrpin 3dh 3dh 01h ro, reserved in f#1 ? minimum grant mingnt 3eh 3eh 00h ro c0f0 maximum latency maxlat 3fh 3fh 00h ro c0f0 power management capabilities pmcap d2h d3h 0221h ro c0f0 power management control pmcs d4h d5h 0000h ro,r/w u1f1
register description r 114 datasheet 4.11.1 vid ? vendor identification register (device #2) address offset: 00 ? 01h default value: 8086h access attributes: read only size: 16 bits the vid register contains the vendor identification number. this 16-bit register combined with the device identification register uniquely identifies any pci device. writes to this register have no effect. bit description 15:0 vendor identification number: this is a 16-bit value assigned to intel. 4.11.2 did ? device identification register (device #2) address offset: 02 ? 03h default value: 3582h access attributes: read only size: 16 bits this 16-bit register combined with the vendor identification register uniquely identifies any pci device. writes to this register have no effect. bit description 15:0 device identification number: this is a 16-bit value assigned to the gmch igd (3582h). 4.11.3 pcicmd ? pci command register (device #2) address offset: 04 ? 05h default: 0000h access: read only, read/write size: 16 bits this 16-bit register provides basic control over the igd?s ability to respond to pci cycles. the pcicmd register in the igd di sables the igd pci compliant master accesses to main system memory. bit description 15:10 reserved 9 fast back-to-back (fb2b) ? ro 8 serr# enable (serre) ? ro 7 address/data stepping ? ro 6 parity error enable (perre) ? ro 5 video palette snooping (vps) ? ro 4 memory write and invalidate enable (mwie) ? ro 3 special cycle enable (sce) ? ro
register description r datasheet 115 bit description 2 bus master enable (bme) ? r/w: this bit determines if the igd is to function as a pci compliant master. 0= disable igd bus mastering (default). 1 = enable igd bus mastering. 1 memory access enable (mae) ? r/w: this bit controls the igd?s re sponse to system memory space accesses. 0= disable (default). 1 = enable. 0 i/o access enable (ioae) ? r/w: this bit controls the igd?s response to i/o space accesses. 0 = disable (default). 1 = enable. 4.11.4 pcists ? pci status register (device #2) address offset: 06 ? 07h default value: 0090h access: read only size: 16 bits pcists is a 16-bit status register that reports the occurrence of a pci compliant master abort and pci compliant target abort. pcis ts also indicates the devsel# tim ing that has been set by the igd. bit description 15 detected parity error (dpe): since the igd does not detect parity, this bit is always set to 0. 14 signaled system error (sse) ? ro 13 received master abort status (rmas) ? ro 12 received target abort status (rtas) ? ro 11 signaled target abort status (stas) ? ro 10:9 devsel# timing (devt) ? ro 8 data parity detected (dpd) ? ro 7 fast back-to-back (fb2b) ? ro 6 user defined format (udf) ? ro 5 66 mhz pci capable (66c) ? ro 4 cap list: this bit is set to 1 to indicate that the regi ster at 34h provides an offset into the function?s pci configuration space containing a pointer to the location of the first item in the list. 3:0 reserved
register description r 116 datasheet 4.11.5 rid ? revision identification register (device #2) address offset: 08h default value: 02h access: read only size: 8 bits this register contains the revision number of th e igd. these bits are read only and writes to this register have no effect. bit description 7:0 revision identification number: this is an 8-bit value that indica tes the revision identification number for the gmch. 4.11.6 cc ? class code register (device #2) address offset: 09 ? 0bh default value: 030000h access: read only size: 24 bits this register contains the devi ce programming interface information related to the sub-class code and base class code definition for the igd. this register also contains the base class code and the function sub-class in relation to the base class code. bit description 23:16 base class code (basec): 03=display controller 15:8 sub-class code (scc): function 0: 00h=vga compatible or 80h=non vga function 1: 80h=non vga 7:0 programming interface (pi): 00h=hardwired as a display controller. 4.11.7 cls ? cache line size register (device #2) address offset: 0ch default value: 00h access: read only size: 8 bits the igd does not support this register as a pci slave. bit description 7:0 cache line size (cls) ? ro
register description r datasheet 117 4.11.8 mlt ? master latency timer register (device #2) address offset: 0dh default value: 00h access: read only size: 8 bits the igd does not support the programmability of the master latency timer because it does not perform bursts. bit description 7:0 master latency timer count value ? ro 4.11.9 hdr ? header type register (device #2) address offset: 0eh default value: 00h access: read only size: 8 bits this register contains the header type of the igd. bit description 7 multi function status (mfunc): indicates if the device is a multi-function device. 6:0 header code (h): this is a 7-bit value that indicates t he header code for the igd. this code has the value 00h, indicating a type 0 configuration space format. 4.11.10 gmadr ? graphics memory range address register (device #2) address offset: 10 ? 13h default value: 00000008h access: read/write, read only size: 32 bits igd graphics system memory base addr ess is specified in this register. bit description 31:27 memory base address ? r/w: set by the os, these bits correspond to address signals [31:26]. 26 128-mb address mask ? ro: 0 indicates 128-mb address 25:4 address mask ? ro: indicates (at least) a 32-mb address range. 3 prefetchable memory ? ro: enable prefetching. 2:1 memory type ? ro: indicate 32-bit address. 0 memory/io space ? ro: indicate system memory space.
register description r 118 datasheet 4.11.11 mmadr ? memory mapped range address register (device #2) address offset: 14 ? 17h default value: 00000000h access: read/write, read only size: 32 bits this register requests allocation for the igd registers and instruction ports. the allocation is for 512-kb and the base address is defined by bits [31:19]. bit description 31:19 memory base address ? r/w: set by the os, these bits correspond to address signals [31:19]. 18:4 address mask ? ro: indicate 512-kb address range. 3 prefetchable memory ? ro: prevents prefetching. 2:1 memory type ? ro: indicates 32-bit address. 0 memory / io space ? ro: indicates system memory space. 4.11.12 iobar ? i/o base address register (device #2) address offset: 18-1bh default: 00000001h access: read/write size: 16-bits this register provides the base offset of the i/o registers within device #2. bits 15:3 are programmable allowing the i/o base to be located anywhere in 16-bit i/o address space. bits 2:1 are fixed and return zero, bit 0 is hardwired to a one indicating that 8-bytes of i/o space are decoded. access to the 8bs of io space is allowed in pm state d0 when io enable (pcicmd bit 0) set. access is disallowed in pm states d1-d3 or if io enable is clear or if device #2 is turned off or if internal graphics is disabled. note that access to this io bar is independent of vga functionality within device #2. al so note that this mechanism is available only through function #0 of device#2 and is not duplicated in function #1. if accesses to this i/o bar are allowed, then the gmch claims all 8-bit, 16-bit, or 32-bit i/o cycles from the cpu that falls within the 8b claimed. bit description 31:16 reserved 15:3 io base address ? r/w: set by the os, these bits correspond to address signals [15:3]. 2:1 memory type ? ro: indicates 32-bit address. 0 memory / io space ? ro
register description r datasheet 119 4.11.13 svid ? subsystem vendor identification register (device #2) address offset: 2c ? 2dh default value: 0000h access: read/write once size: 16 bits bit description 15:0 subsystem vendor id: this value is used to identify the vendor of the subsystem. this register should be programmed by bios during boot-up. once written, this register becomes read only. this register can only be cleared by a reset. 4.11.14 sid ? subsystem identification register (device #2) address offset: 2e ? 2fh default value: 0000h access: read/write once size: 16 bits bit description 15:0 subsystem identification: this value is used to identify a parti cular subsystem. this field should be programmed by bios during boot-up. once written, th is register becomes read only. this register can only be cleared by a reset. 4.11.15 romadr ? video bios rom base address registers (device #2) address offset: 30 ? 33h default value: 00000000h access: read only size: 32 bits the igd does not use a separate bios rom, therefore this register is hardwired to 0?s. bit description 31:18 rom base address ? ro 17:11 address mask ? ro: indicates 256-kb address range. 10:1 reserved 0 rom bios enable ? ro: indicates rom not accessible.
register description r 120 datasheet 4.11.16 intrline ? interrupt line register (device #2) address offset: 3ch default value: 00h access: read/write size: 8 bits bit description 7:0 interrupt connection: used to communicate interrupt line routi ng information. post software writes the routing information into this register as it in itializes and configures the system. the value in this register indicates which input of the system interrupt controller that the device? s interrupt pin is connected to. 4.11.17 intrpin ? interrupt pin register (device #2) address offset: 3dh default value: 01h access: read only size: 8 bits bit description 7:0 interrupt pin: as a single function device, the igd specifies inta# as its interrupt pin. 01h=inta#. for function #1, this register is set to 00h. 4.11.18 mingnt ? minimum grant register (device #2) address offset: 3eh default value: 00h access: read only size: 8 bits bit description 7:0 minimum grant value: the igd does not burst as a pci compliant master. 4.11.19 maxlat ? maximum latency register (device #2) address offset: 3fh default value: 00h access: read only size: 8 bits bit description 7:0 maximum latency value: bits[7:0]=00h. the igd has no specific requirements for how often it needs to access the pci bus.
register description r datasheet 121 4.11.20 pmcap ? power management capabilities register (device #2) address offset: d2h ? d3h default value: 0221h access: read only size: 16 bits bit description 15:11 pme support: this field indicates the power states in which the igd may assert pme#. hardwired to 0 to indicate that the igd does not assert the pme# signal. 10:6 reserved 5 device specific initialization (dsi): hardwired to 1 to indicate that special initialization of the igd is required before generic class dev ice driver is to use it. 4 auxiliary power source: hardwired to 0. 3 pme clock: hardwired to 0 to indicate igd does not support pme# generation. 2:0 version: hardwired to 001b to indicate there are 4 by tes of power management registers implemented. 4.11.21 pmcs ? power management control/status register (device #2) address offset: d4h ? d5h default value: 0000h access: read/write, read only size: 16 bits bit description 15 pme_status ? ro: this bit is 0 to indicate that igd does not support pme# generation from d3 (cold). 14:9 reserved 8 pme_en ? ro: this bit is 0 to indicate that pme# assertion from d3 (cold) is disabled. 7:2 reserved 1:0 powerstate ? r/w: this field indicates the current power state of the igd and can be used to set the igd into a new power state. if software attempts to write an unsupported state to this field, write operation must complete normally on the bus, but the data is discarded and no state change occurs. on a transition from d3 to d0 the graphics cont roller is optionally reset to initial values. bits[1:0] power state 00 d0 default 01 d1 10 d2 not supported 11 d3
register description r 122 datasheet
intel? 855gm/gme gmch system address map r datasheet 123 5 intel ? 855gm/gme gmch system address map a system based on the gmch supports 4 gb of addressable system memory space and 64 kb+3b of addressable i/o space. the i/o and system memory spaces are divided by system configuration software into regions. the system memory ranges are useful either as system memory or as specialized system memory, while the i/o regions are used solely to control the operation of devices in the system. when the gmch receives a write request whose a ddress targets an invalid space, the data is ignored. for reads, the gmch responds by re turning all zeros on the requesting interface. 5.1 system memory address ranges the gmch provides a maximum system memory of 2-gb. the gmch does not remap apic memory space and does not limit ddr sdram space in hardware. it is the bios or system designer?s responsibility to limit system memory population so that adequate pci high bios and apic memory space can be allocated. figure 6 and figure 7 depict the system memory address map in a simplified form and provide details on mapping specific system memory regions as defined and supported by the gmch.
intel? 855gm/gme gmch system address map r 124 datasheet figure 6. simplified view of system address map independently programmable non-overlapping memory windows main memory address range pci memory address range 4 gb top of the main memory 0 graphic ( local) memory gmch system memory space
intel? 855gm/gme gmch system address map r datasheet 125 figure 7. detailed view of system address map extended sbios lower bios area ( 64 kb) 16 kb x 4 sbios upper bios area (64 kb) expansion card bios and buffer area (128 kb) 16 kbx8 standard pci/isa video memory (smm memory) 128 kb dos area pci memory range optional isa hole dos compatibility memory 4 gb max tom 1 gb 16 mb 15 mb 1 mb 640 kb 0 b dos compatibility memory 0fffffh 0f0000h 0effffh 0e0000h 0dffffh 0c0000h 0bffffh 0a0000h 09ffffh 000000h 1 mb 960 kb 896 kb 640 kb 768 kb 5.2 dos compatibility area this compatibility region is divided into the following address regions: ? 0 ? 640-kb dos area ? 640 ? 768-kb video buffer area ? 768 ? 896 kb in 16-kb sections (total of eight sections) - expansion area ? 896 ? 960 kb in 16-kb sections (total of four sections) - extended system bios area ? 960 kb ? 1-mb system bios area there are 16 system memory segments in the compatibility area. thirteen of the system memory ranges can be enabled or disabled independently for both read and write cycles.
intel? 855gm/gme gmch system address map r 126 datasheet table 32. system memory segments and their attributes system memory segments attributes comments 000000h - 09ffffh fixed - always mapped to main ddr sdram 0 to 640 kb ? dos region 0a0000h - 0bffffh mapped to hub interface or igd - configurable as smm space video buffer (physical ddr sdram configurable as smm space) 0c0000h - 0c3fffh we(write enable) re (read enable) add-on bios 0c4000h - 0c7fffh we re add-on bios 0c8000h - 0cbfffh we re add-on bios 0cc000h - 0cffffh we re add-on bios 0d0000h - 0d3fffh we re add-on bios 0d4000h - 0d7fffh we re add-on bios 0d8000h - 0dbfffh we re add-on bios 0dc000h - 0dffffh we re add-on bios 0e0000h - 0e3fffh we re bios extension 0e4000h - 0e7fffh we re bios extension 0e8000h - 0ebfffh we re bios extension 0ec000h - 0effffh we re bios extension 0f0000h - 0fffffh we re bios area dos area (000000h-09ffffh) the dos area is 640-kb in size and is always mapped to the main system memory controlled by the gmch. legacy vga ranges (0a0000h-0bffffh) the legacy 128-kb vga memory range a0000h-b ffffh (vga frame buffer) can be mapped to igd (device #2) and to the hub interface de pending on the programming of the vga steering bits. priority for vga mapping is constant in that the gmch always decodes internally mapped devices first. internal to the gmch, decode precedence is always given to igd. the gmch always positively decodes internally mapped devices, namely the igd. subsequent decoding of regions mapped to the hub interface depends on the legacy vga configurations bits (vga enable and mdap). this region is also the default for smm space. compatible smram address range (0a0000h-0bffffh) when compatible smm space is en abled, smm-mode cpu accesses to this range are routed to physical ddr sdram at this address. non- smm-mode cpu accesses to this range are considered to be to the video buffer area as de scribed above. hub interface originated cycles to enabled smm space are not allowed and are cons idered to be to the video buffer area.
intel? 855gm/gme gmch system address map r datasheet 127 monochrome display adapter (mda) range (0b0000h - 0b7fffh) legacy support requires the ability to have a s econd graphics controller (monochrome) in the system. accesses in the standard vga range are forwarded to igd and the hub interface (depending on configuration bits). since the monochrome adapter may be mapped to anyone of these devices, the gmch must decode cycles in the mda range and forward them either to igd or to hub interface. this cap ability is controlled by a vga st eering bits and the legacy configuration bit (mdap bit). in addition to the system memory range b0000h to b7fffh, the gmch decodes io cycles at 3b4h, 3b5h, 3b8h, 3b 9h, 3bah, and 3bfh and forwards them to the either the igd or the hub interface. expansion area (0c0000h-0dffffh) this 128-kb isa expansion region is divided into eight, 16-kb segments. each segment can be assigned one of four read/write states: read-only, write-only, read /write, or disabled. typically, these blocks are mapped through gmch and are subtractively decoded to isa space. system memory that is disabled is not remapped. extended system bios area (0e0000h-0effffh) this 64-kb area is divided into four, 16-kb segm ents. each segment can be assigned independent read and write attributes so it can be mapped e ither to main ddr sdram or to hub interface. typically, this area is used for ram or rom. sy stem memory segments that are disabled are not remapped elsewhere. system bios area (0f0000h-0fffffh) this area is a single 64-kb segment. this segment can be assigned read and write attributes. it is by default (after reset) read/write disabled and cycles are forwarded to hub interface. by manipulating the read/write attributes, the gmch can ?shadow? bios into the main ddr sdram. when disabled, this segment is not remapped. 5.3 extended system memory area this system memory area covers 100000h (1 mb ) to ffffffffh (4 gb-1) address range and it is divided into the following regions: ? main system memory from 1 mb to the top of system memory. ? pci memory space from the top of system me mory to 4 gb with two specific ranges. ? apic configuration space from fec0_0000h (4 gb?20 mb) to fecf_ffffh (4 gb?19 mb -1) and fee0 _ 0000h (4 gb?18 mb) to feef _ ffffh (4 gb?17 mb-1). ? high bios area from 4 gb to 4 gb - 2 mb
intel? 855gm/gme gmch system address map r 128 datasheet 5.4 main system memory address range (0010_0000h to top of main memory) the address range from 1 mb to the top of main system memory is mapped to main ddr sdram address range controlled by the gm ch. the gmch will fo rward all accesses to addresses within this range to the ddr sdram unless a hole in this range is created using the fixed hole as controlled by the fdhc register. accesses within this hole are forwarded to hub interface. the gmch provides a maximum ddr sdram address decode space of 4-gb. the gmch does not remap apic memory space. the gmch does not limit ddr sdram address space in hardware. 5.4.1 15-mb ? 16-mb window a hole can be created at 15 mb-16 mb as controlled by the fixed hole enable (fdhc register) in device 0 space. accesses within th is hole are forwarded to th e hub interface. the range of physical ddr sdram disabled by opening the hole is not remapped to the top of the memory ? that physical ddr sdram space is not accessible. this 15 mb-1 6 mb hole is an optionally enabled isa hole. video accelerators originally used this hole. va lidation and customer sv teams also use it for some of their test cards. that is why it is being supported. there is no inherent bios request for the 15-16 hole. 5.4.2 pre-allocated system memory voids of physical addresses that are not accessible as general syst em memory and reside within system memory address range (< tom) are created for smm-mode and legacy vga graphics compatibility. it is the responsibility of bios to properly initialize these regions . the number of uma options has been extended. allocation is at a fixed address in terms of rigid positioning of uma system memory ? tom-tseg-uma(size), but it is mapp ed at any available address by a pci allocation algorithm. gmadr and mmadr are requested through bars. the following table details the location and attributes of the regions. table 33. pre-allocated system memory system memory segments attributes comments 00000000h - 03e7ffffh r/w available system memory 62.5 -mb 03e80000h - 03f7ffffh r/w pre-a llocated graphics vga memory 1-mb (or 4/8/16/32- mb) when igd is enabled 03f80000h - 03ffffffh smm mode only - cpu reads tseg address range 03f80000h - 03ffffffh smm mode only - cpu reads tseg pre-allocated system memory
intel? 855gm/gme gmch system address map r datasheet 129 5.4.2.1 extended smram address range (hseg and tseg) the hseg and tseg smm transaction address sp aces reside in this extended system memory area. 5.4.2.2 hseg smm mode cpu accesses to enabled hseg are remapped to 000a0000h-000bffffh. non- smm mode cpu accesses to enabled hseg are cons idered invalid are te rminated immediately on the fsb. the exceptions to this rule are non-smm mode write back cycles that are remapped to smm space to maintain cache coherency. hub interface orig inated cycles to enabled smm space are not allowed. physical ddr sdram be hind the hseg transaction address is not remapped and is not accessible. 5.4.2.3 tseg tseg is 1-mb in size and is at the top of ph ysical system memory. smm mode cpu accesses to enabled tseg access the physical ddr sdram at the same address. non-smm mode cpu accesses to enabled tseg are cons idered invalid and are terminat ed immediately on the fsb. the exceptions to this rule are non-smm-mode write back cycles that are di rected to the physical smm space to maintain cache cohere ncy. hub interface originated cycles that enable smm space are not allowed. the size of the smram space is determined by the usmm value in the smram register. when the extended smram space is enabled, non-smm cpu accesses and all other accesses in this range are forwarded to the hub interface. when smm is enabled the amount of system memory available to the system is equal to the amount of physical ddr sdram minus the value in the tseg register. 5.4.2.4 dynamic video memory technology (dvmt) the igd supports dvmt in a non-graphics system memory configuration. dvmt is a mechanism that manages system memory and the internal graphics device for optimal graphics performance. dvmt-enabled software drivers, working with the memory arbiter and the operating system, utilize the system memory to support 2d graphics and 3d applications. dvmt dynamically responds to application requirements by allocating the proper amount of display and texturing memory. 5.4.2.5 pci memory address range (top of main system memory to 4 gb) the address range from the top of main ddr sdram to 4-gb (top of physical system memory space supported by the gmch) is normally mapped via the hub interface to pci. as an internal graphics configuration, there are two exceptions to this rule. 1. the first exception is addresses decoded to th e graphics memory range. one per function in device #2. 2. the second exception is addresses decoded to the system memory mapped range of the internal graphics device. one per function in device #2. both exception cases are forwarded to the internal graphics device. 3. as an agp configuration, there are two exceptions to this rule:
intel? 855gm/gme gmch system address map r 130 datasheet ? addresses decoded to the agp memory window defined by the mbase,mlimit,pmbase, and pmlimit registers are mapped to agp. ? addresses decoded to the graphics aperture range defined by the apbase and apsize registers are mapped to the main ddr sdram. there are two sub-ranges within the pci memory address range de fined as apic configuration space and high bios address range. as an intern al graphics device, the graphics memory range and the memory mapped range of the internal graphics device must not overlap with these two ranges. these ranges are described in detail in the following paragraphs. 5.4.2.6 apic configuration space (fec0_0000h -fecf_ffffh, fee0_0000h- feef_ffffh) this range is reserved for apic configura tion space that includes the default i/o apic configuration space. the default local apic configuration space is fee0_0000h to feef_0fffh. cpu accesses to the local apic configuration sp ace do not result in external bus activity since the local apic configuration space is internal to the cpu. however, an mtrr must be programmed to make the local apic range uncach eable (uc). the local apic base address in each cpu should be relocated to the fec0_0000h (4 gb-20 mb) to fecf_ffffh range so that one mtrr can be programmed to 64-kb for the lo cal and i/o apics. th e i/o apic(s) usually resides in the ich4-m portion of the chip-set or as a stand-alone component(s). i/o apic units will be located beginning at th e default address fec0_0000h. the first i/o apic will be located at fec0_0000h. each i/o apic unit is located at fec0_x000h where x is i/o apic unit number 0 through f(hex). this address range will be normally mapped to hub interface. the address range between the apic configur ation space and the high bios (fed0_0000h to ffdf_ffffh) is always mapped to the hub interface. 5.4.2.7 high bios area (ffe0_0000h -ffff_ffffh) the top 2-mb of the extended memory region is reserved for system bios (high bios), extended bios for pci devices, and the a20 alias of the system bios. cpu begins execution from the high bios after reset. this region is ma pped to hub interface so that the upper subset of this region aliases to 16 mb to 256-kb range. th e actual address space required for the bios is less than 2-mb but the minimum cpu mtrr range for this region is 2-mb so that full 2-mb must be considered. 5.4.3 system management mode (smm) memory range the gmch supports the use of main system memory as system management ram (smm ram) enabling the use of system management mode. the gmch supports three smm options: compatible smram (c_smram), high segment (hseg), and top of memory segment (tseg). system management ram space provides a sy stem memory area that is available for the smi handler?s and code and data storage. this system memory resource is normally hidden from the system os so that the processor has imme diate access to this system memory space upon entry to smm. the gmch provides three smram options: ? below 1-mb option that supports compatible smi handlers.
intel? 855gm/gme gmch system address map r datasheet 131 ? above 1-mb option that allows new smi ha ndlers to execute with write-back cacheable smram. ? above 1-mb solutions require changes to compatible smram handlers code to properly execute above 1 mb. note: hub interface is not allowe d to access the smm space. 5.4.3.1 smm space restrictions if any of the following conditions are violated the results of smm accesses are unpredictable and may cause the system to hang: ? the compatible smm space must not be set-up as cacheable. ? high or tseg smm transaction address space must not overlap addr ess space assigned to ddr sdram or to any pci devi ces (including hub interface and graphics devices). this is a bios responsibility. ? both d_open and d_close must not be set to 1 at the same time. when tseg smm space is enabled, the tseg space must not be reported to the os as available. this is a bios responsibility. 5.4.3.2 smm space definition smm space is defined by its addressed s mm space and its ddr sdram smm space. the addressed smm space is defined as the range of bus addresses used by the cpu to access smm space. ddr sdram smm space is defined as th e range of physical ddr sdram locations containing the smm code. smm space can be accessed at one of three transaction address ranges: compatible, high, and tseg. the compatible and tseg smm space is not remapped and therefore the addressed and ddr sdram smm sp ace is the same address range. since the high smm space is remapped the addressed and ddr sdram smm space is a different address range. note that the high ddr sdram space is the same as the compatible transaction address space table 34 describes three unique address ranges: 1. compatible transaction address (adr c) 2. high transaction address (adr h) 3. tseg transaction address (adr t) these abbreviations are used later in table 34. table 34. smm space transaction handling smm space enabled transaction address space (adr) dram space (dram) compatible (c) a0000h to bffffh a0000h to bffffh high (h) 0feda0000h to 0fedbffffh a0000h to bffffh tseg (t) (tom-tseg_sz) to tom (tom-tseg_sz) to tom
intel? 855gm/gme gmch system address map r 132 datasheet 5.4.4 system memory shadowing any block of system memory that can be designated as read-only or write-only can be ?shadowed? into gmch ddr sdram. typically this is done to allow rom code to execute more rapidly out of main ddr sdram. rom is used as a read-only during the copy process while ddr sdram at the same time is designated write-only. after copying, the ddr sdram is designated read-only so that rom is shadowed. cpu bus transactions are routed accordingly. 5.4.5 i/o address space the gmch does not support the existence of any other i/o devices beside itself on the cpu bus. the gmch generates hub interface or pci bus cy cles for all cpu i/o accesses that it does not claim. within the host bridge the gmch contai ns two internal registers in the cpu i/o space, configuration address register (config_addre ss) and the configuration data register (config_data). these locations are used to implement configuration space access mechanism and as described in the configuration register section. the cpu allows 64 kb +3 b to be addressed within the i/o space. th e gmch propagates the cpu i/o address without any translation on to the destination bus and therefore provides addressability for 64 k+3 b locations. note that the upper three locations can be accessed only during i/o address wrap-around when cpu bus a16# address signal is asserted. a16# is asserted on the cpu bus whenever an i/o access is made to 4 bytes from address 0fffdh, 0fffeh, or 0ffffh. a16# is also asserted when an i/o acce ss is made to 2 bytes from address 0ffffh. a set of i/o accesses (other than ones used for configuration space access) is consumed by the internal graphics device if it is enabled. the mechanisms for intern al graphics io decode and the associated control is explained later. the i/o accesses (other than ones used for conf iguration space access) are forwarded normally to the hub interface. the gmch will not post i/o write cycles to ide. 5.4.5.1 agp/pci i/o address mapping the gmch can be programmed to direct non-me mory (i/o) accesses to the agp bus interface when cpu initiated i/o cycle addresses are within the agp i/o address range. this range is controlled via the i/o base address (iobase) a nd i/o limit address (iolimit) registers in gmch device #1 configuration space. address decoding for this range is based on the following concept. the top 4 bits of the respective i/o base and i/o limit registers correspond to address bits a[15:12] of an i/o address. for the purpose of address decoding, the gmch assumes that lower 12 address bits a[11:0] of the i/o base are zero and that address bits a[11:0] of the i/o limit address are fffh . this forces the i/o address range alignment to 4-kb boundary and produces a size granularity of 4 kb. the gmch positively decodes i/o accesses to agp i/o address space as defined by the following equation: i/o_base_address * cpu i/o cycle address * i/o_limit_address the effective size of the range is programmed by the plug-and-play configuration software and it depends on the size of i/o space claimed by the agp device.
intel? 855gm/gme gmch system address map r datasheet 133 the gmch also forwards accesses to the legacy vga i/o ranges acco rding to the settings in the device #1 configuration registers bctrl ( vga enable) and pcicmd1 (ioae1), unless a second adapter (monochrome) is present on the hub interface/pci (or isa). the presence of a second graphics adapter is determined by the mdap configuration bit. when mdap is set, the gmch will decode legacy monochrome io ranges and forward them to the hub interface. the io ranges decoded for the monochrome adapter are 3b4h, 3b5h, 3b8h, 3b9h, 3bah and 3bfh. note: the gmch device #1 i/o address range registers defined abov e are used for all i/o space allocation for any devices requiring such a window on agp. these devices would include the agp device, pci-66mhz/3.3v agents, and multifunctional agp devices where one or more functions are implemented as pci devices. the pcicmd1 register can disable the routing of i/o cycles to the agp. 5.4.6 gmch decode rules and cross-bridge address mapping the address map described above applies globally to accesses a rriving on any of the three interfaces i.e. host bus, igd, and hub interface. 5.4.7 hub interface decode rules the gmch accepts accesses from hub interf ace to the following address ranges: ? all memory read and write accesses to ma in ddr sdram including pam region (except smm space) ? all memory read/write accesses to the graphi cs aperture (dram) defined by apbase and apsize. ? all hub interface memory write accesses to agp memory range de fined by mbase, mlimit, pmbase, and pmlimit. ? memory writes to vga range. all memory reads from the hub in terface a that are targeted > 4- gb system memory range will be terminated with master abort completion, and all memory writes (>4-gb) from the hub interface will be ignored. hub interface system memory accesses that fall el sewhere within the syst em memory range are considered invalid and will be remapped to syst em memory address 0h, snooped on the host bus, and dispatched to ddr sdram. reads will return all 1?s with master abort completion. writes will have be?s deasserted and will terminate with master abort if completion is required. i/o cycles will not be accepted. they are terminat ed with master abor t completion packets. 5.4.7.1 hub interface accesses to gmch that cross device boundaries hub interface accesses are limited to 256 b (bytes) but have no restrictions on crossing address boundaries. a single hub interface request may ther efore span device boundaries (ddr sdram) or cross from valid addresses to invalid addre sses (or visa versa). the gmch does not support transactions that cross device boundaries. for reads and for writes requiring completion, the gmch will provide separate comp letion status for each naturally aligned 32-b or 64-b block. if the starting address of a transaction hits a valid address, the portion of a request that hits that
intel? 855gm/gme gmch system address map r 134 datasheet target device (ddr sdram) will complete norma lly. the remaining portion of the access that crosses a device boundary (targets a different device than that of the starting address) or hits an invalid address will be remapped to system me mory address 0h, snooped on the host bus, and dispatched to ddr sdram. reads will return all 1?s with master abort completion. writes will have be?s (byte enable) deasserted and will terminate with master abort if completion is required. if the starting address of a transaction hits an invalid address the entire transaction will be remapped to system memory address 0h, snooped on the host bus, and dispatched to ddr sdram. reads will return all 1?s with master abort completion. writes will have be?s deasserted and will terminate with master abort if completion is required. 5.4.7.2 agp interface decode rules cycles initiated using pci protocol the gmch does not support any agp/pci access ta rgeting hub interface. the gmch will claim agp/pci initiated memory read and write transactions decoded to the main ddr sdram range or the graphics aperture range. all other memory read and write requests will be master-aborted by the agp/pci initiator as a consequence of gmch not responding to a transaction. under certain conditions, the gmch restrict access to the dos compatibility ranges governed by the pam registers by disti nguishing access type and destination bus. the gmch accept agp/pci write transactions to the compatibility ranges if the pam designates ddr sdram as write-able. if accesses to a range are not write en abled by the pam, the gmch does not respond and the cycle will result in a master-abort. the gmch accept agp/pci read transactions to the compatibility ranges if the pam designates ddr sdram as readable. if accesses to a range are not read enabled by the pam, the gmch does not respond and the cycle will result in a master- abort. if agent on agp/pci issues an i/o or pci special cycle transaction, the gmch will not respond and cycle will result in a master-abort. the gm ch will accept pci configur ation cycles to the internal gmch devices as part of the pci configuration/co-pilot mode mechanism. cycles initiated using agp protocol all cycles must reference main memory i.e. main ddr sdram address range (excluding pam) or graphics aperture range (also physically mapped within ddr sdram but using different address range). agp accesses to the pam regi on from 640k -to- 1m are not allowed. agp accesses to smm space are not allo wed. agp initiated cycles that target ddr sdram are not snooped on the host bus, even if they fall outside of the agp aperture range. if a cycle is outside of a valid main memory range then it will terminate as follows: ? reads: remap to memory address 0h, return data from address 0h, and set the iaaf error flag. ? writes:remapped to memory address 0h with be ?s de-asserted (effectively dropped ?on the floor?) and set the iaaf error flag. agp accesses to gmch that cross device boundaries for frame# accesses, when an agp or pci master gets disconnected it will resume at the new address which allows the cycle to be routed to or claimed by the new target. therefore accesses
intel? 855gm/gme gmch system address map r datasheet 135 should be disconnected by the target on potential device bounda ries. the gmch will disconnect agp/pci transactions on 4-kb boundaries. agppipe# and sba accesses are limited to 256 by tes and must hit ddr sdram. agp accesses are dispatched to ddr sdram on naturally aligned 32 byte block boundaries. the portion of the request that hits a valid address will complete no rmally. the portion of a read access that hits an invalid address will be remapped to address 0h, return data from address 0h, and set the iaaf error flag. the portion of a write access that hits an invalid address will be remapped to memory address 0h with be?s deasserted (effectively droppe d ?on the floor?) and set the iaaf error flag.
intel? 855gm/gme gmch system address map r 136 datasheet
functional description r datasheet 137 6 functional description 6.1 host interface overview the gmch front side bus uses source synchronous transfer for the address and data signals. the address signals are double pumped and two addre sses can be generated every bus clock. at 100 mhz bus frequency, the two address signals run at 200 mhz for a maximum address queue rate of 50-m addresses/sec. the data is quad pumped and an entire 64-b cache line can be transferred in two bus clocks. at 100 mhz bus fre quency, the data signals run at 400 mhz for a maximum bandwidth of 3.2- gb/s. the gmch supports a 8-deep ioq (in-order-queue) using the intel pentium m processor or intel celeron m processor. 6.2 dynamic bus inversion the gmch supports dynamic bus inversion (dbi) when driving a nd receiving data from the host bus. dbi limits the number of data signals that are driven to a low voltage on each quad pumped data phase. this decreases the power consumption of the gmch. dinv[3:0]# indicates if the corresponding 16 bits of data are inverted on the bus for each quad pumped data phase: table 35. relation of dbi bits to data bits dinv[3:0] data bits dinv[0]# hd[15:0]# dinv[1]# hd[31:16]# dinv[2]# hd[47:32]# dinv[3]# hd[63:48]# whenever the cpu or the gmch dr ives data, each 16-bit segment is analyzed. if more than eight of the 16 signals would normally be driven low on the bus the corresponding dinv# signal will be asserted and the data will be inverted prior to being driven on the bus. whenever the cpu or the gmch receives data it monitors dinv[3:0]# to determine if the corresponding data segment should be inverted. 6.2.1 system bus interrupt delivery the intel pentium m processor and intel celeron m processor support system bus interrupt delivery. it does not support the apic serial bus interrupt delivery mechanism. interrupt related messages are encoded on the system bus as interrupt message transactions. system bus interrupts may originate from the processo r on the system bus, or from a downstream device on the hub interface.
functional description r 138 datasheet in a gmch platform, the ich4-m contains ioxapics and its interrupts are generated as upstream hub interface memory writes. furthermor e, pci 2.2 defines ms i?s (message signaled interrupts) that are also in the form of memory writes. a pci 2.2 device may generate an interrupt as an msi cycle on its pci bus instead of asserting a hardware signal to the ioxapic. the msi may be directed to the ioxapic, which in turn generates an interrupt as an upstream hub interface memory write. altern atively the msi may be directed directly to the system bus. the target of an msi is dependent on the address of the interrupt memory write. the gmch forwards inbound hub interface memory writes to address 0feex_xxxxh, to the system bus as interrupt message transactions. 6.2.2 upstream interrupt messages the gmch accepts message based interrupts from its hub interface and forwards them to the system bus as interrupt message transactions. the interrupt messages presented to the gmch are in the form of memory writes to address 0f eex_xxxxh. at the hub interface, the memory write interrupt message is treated like any other memory write; it is either posted into the inbound data buffer (if space is available) or retried (if data buffer space is not imme diately available). once posted, the memory write from the hub interf ace, to address 0feex_xxxxh, is decoded as a cycle that needs to be propagat ed by the gmch to the front side bus as an interrupt message transaction. 6.3 system memory interface 6.3.1 ddr sdram interface overview the gmch supports ddr sdram at 200/266 mhz and includes the following support: ? up to 1 gb of pc1600/pc2100 ddr sdram ? up to 2 gb (high density) of pc1600/pc2100 ddr sdram ? pc1600/2100 unbuffered 200-pin ddr sdram so-dimms ? configurable optional ecc ? maximum of two so-dimms, single-sided and/or double-sided the 2-bank select lines sba[1:0] and the 13 address lines sma[12:0] allow the gmch to support 64-bit wide so-dimms using 128-mb, 256-mb, and 512-mb ddr sdram technology. while address lines sma[9:0] determine the starting address for a burst, burst length can only be 4. four chip selects scs[3:0]# lines allow a maximum of two rows of single-sided ddr sdram so-dimms and four rows of double-sided ddr sdram so-dimms. the gmch main system memory controller targets cas latencies of 2 and 2.5 for ddr sdram. the gmch provides refresh functionality with a programmable rate (normal ddr sdram rate is 1 refresh/15.6 s). for write ope rations of less than a full cache line, gmch will perform a cache-line read and into the write buffer and perform byte-wise write-merging in the write buffer.
functional description r datasheet 139 6.3.2 system memory organization and configuration 6.3.2.1 configuration mechanism for so-dimms detection of the type of ddr sdram installed on the so-dimm is supported via serial presence detect mechanism as defined in the jedec 200-pin so- dimm specification. before any cycles to the system memory in terface can be supported, the gmch ddr sdram registers must be initialized. the gmch must be configured for operation with the installed system memory types. detection of system memory type and size is done via the system management bus (smb) interface on the ich4-m. th is two-wire bus is used to extract the ddr sdram type and size information from the se rial presence detect port on the ddr sdram so-dimms. ddr sdram so-dimms contain a 5-pin serial presence detect interface, including scl (serial clock), sda (serial data) and sa[2:0]. devices on the smbus have a 7-bit address. for the ddr sdram so-dimms, the upper four bits are fixed at 1010b. the lower three bits are strapped on the sa[2:0] pins. scl and sda are connected directly to the system management bus on the ich4-m. thus data is read from the serial presence detect port on the so-dimms via a series of i/o cycles to the s outh bridge. the bios needs to determine the size and type of system memory used for each of the rows of system memory in order to properly configure the gmch system memory interface. for smbus configuration and access of the se rial presence detect ports, refer to the intel? 82801dbm i/o controller hub 4 mobile (ich4-m) datasheet (252337) for more details. 6.3.2.2 system memory register programming this section provides an overview of how the required information for programming the ddr sdram registers is obtained from the serial presence detect ports on the so-dimms. the serial presence detect ports are used to dete rmine refresh rate, ma and md buffer strength, row type (on a row by row basis), ddr sdram timings, row sizes and row page sizes. table 36 lists a subset of the data available through the on board serial presence detect rom on each so-dimm. table 36. data bytes on so-dimm used for programming dram registers byte function 2 system memory type (ddr sdram) 3 number of row addresses, not counting bank addresses 4 number of column addresses 5 number of so-dimm banks 11 ecc, no ecc 12 refresh rate/type 17 number banks on each device table 36 is only a subset of the defined spd bytes on the so-dimms. these bytes collectively provide enough data for programming the gmch ddr sdram registers.
functional description r 140 datasheet 6.3.3 ddr sdram performance description the overall system memory performance is controlled by the ddr sdram timing register, pipelining depth used in gmch, system memory speed grade and the type of ddr sdram used in the system. besides this, the exact performan ce in a system is also dependent on the total system memory supported, external buffering and system memory array layout. the most important contribution to overall performance by the system memory controller is to minimize the latency required to initiate and complete request s to system memory, and to support the highest possible bandwidth (full streaming, quick turn-arounds). one measure of performance is the total flight time to complete a cache lin e request. a true discussion of performance really involves the entire chipset, not just the system memory controller. 6.3.3.1 data integrity (ecc) the gmch supports single-bit error correcting code (or error checking and correcting) and multiple-bit ec (error checking) on the main memory interface. the gmch generate an 8-bit code word for each 64-bit qword of memory a nd performs two qword writes at a time so two 8- bit codes are sent with each write . since the code word covers a full qword, writes of less than a qword require a read-merge-write operation. cons ider a dword write to memory. in this case, when in ecc mode, gmch will read the qword where the addressed dword will be written, merge in the new dword, generate a code cove ring the new qword and finally write the entire qword and code back to memory. any correctable (single-bit) errors detected during the initial qword read are corrected before merging the new dword. gmch also supports another data integrity mode, ec (error checking) mode. in this mode, the gmch generates and stores a code for each qword of memory. it th en checks the code for reads fro m memory but does not correct any errors that are found. 6.4 integrated graphics overview the intel 855gm/855gme gmch provides a highly in tegrated graphics accelerator and pci set while allowing a flexible integrated system graphics solution. note: intel 855gme gmch can support an agp discrete graphics controller.
functional description r datasheet 141 figure 8. intel ? 855gm gmch graphics block diagram instr./ data setup/transform 3d engine scan conversion texture engine raster engine 2d engine video engine (mpeg2 decode) overlay sprite cursor primary display secondary display display c 2 n d overlay alpha blend/ gamma/ crc cursor cntl mux port dac lvds dvob dvoc memory control ddr/sdram pipe a pipe b high bandwidth access to data is provided through the system memory port. the gmch uses a tiling architecture to minimize page miss latencies and thus maximize effective rendering bandwidth. 6.4.1 3d/2d instruction processing the gmch contains an extensive set of instructions that control various functions including 3d rendering, blt operations, display, mpeg decode acceleration, and overlay. the 3d instructions set 3d pipeline states and control the processing functions. the 2d instructions provide an efficient method for invoking blt operations. 6.4.2 3d engine the 3d engine of the gmch has been designed with a deeply pipelined architecture, where performance is maximized by allowing each stage of the pipeline to simultaneously operate on different primitives or portions of the same primitive. the gmch supports the following: ? perspective-corrected texture mapping ? multitexturing ? embossed and dot-product bump mapping ? cubic environment maps
functional description r 142 datasheet ? bilinear, trilinear, and anisotropic mip map filtering ? gouraud shading and flat shading ? alpha-blending ? per-vertex and per- pixel fog ? z/w buffering these features are independently controlled via a set of 3d instructions. the 3d pipeline subsystem performs the 3d rendering acceleration. the main blocks of the pipeline are the setup engine, scan converter, texture pipeline, and raster pipeline. a typical programming sequence would be to send instructions to set the state of the pipeline followed by rendering instructions containing 3d primitive vertex data. 6.4.2.1 bi-cubic filtering (intel ? 855gme gmch) bi-cubic filtering is an alternat e method to bi-linear filtering. the filter (blend factor) is determined by the relative distance between the pixel center and the nearest 4 texel (2x2). this method provides a significant level of filtering an d looks very crisp on a display. this method also creates a smooth motion of textur e as it traverses acr oss the display. 6.4.2.2 video mixer rendering (intel ? 855gme gmch) vmr refers to the ability to blend any data format/source with other displayable content. it allows 3d, video/dvd, 2d bitmap and closed caption to be mixed together. vmr works mainly as a front-end processor, thereby reducing dependence on video ports and overlays 6.4.2.3 setup engine the gmch 3d setup engine takes the input data associated with each vertex of a 3d primitive and computes the various paramete rs required for scan conversion. in formatting this data, the gmch maintains sub-pixel accuracy. the per-vertex da ta is converted into gradients that can be used to interpolate the data at any pixel within a polygon (colors, alpha, z or w depth, fog, and texture coordinates). the pixels covered by a polygon are identified and per-pixel texture addresses are calculated. 6.4.2.4 viewport transform and perspective divide a 3d-geometry pipeline typically involves tran sformation of vertices from model space to clipping space followed by clip test and cli pping. lighting can be performed during the transformation or at any other point in the pipeline. after clipping, the next stage involves perspective divide followed by transformation to the viewport or scr een space. the gmch can support viewport transform and perspective divide portion of the 3d geometry pipeline in hardware.
functional description r datasheet 143 6.4.2.5 3d primitives and data formats support the 3d primitives rendered by the gmch are points, lines, discrete triangles, line strips, triangle strips, triangle fans, a nd polygons. in addition to this, the gmch supports directx?s* flexible vertex format* (fvf), which enables the application to specify a variable length parameter list, obviating the need for sending unused informati on to the hardware. strips, fans, and indexed vertices as well as fvf improves delivered ve rtex rate to the setup engine significantly. 6.4.2.6 pixel accurate fast sc issoring and clipping operation the gmch supports clipping to a scissoring rectangle within the drawing window. the gmch clipping and scissoring in hardware reduce the n eed for software to process polygons, and thus improves performance. during the setup stage, the gmch clips polygons to the drawing window. the scissor rectangle accelerates th e clipping process by allowing th e driver to clip to a bigger region than the hardware renders to. the scissor rectangle is pixel accura te, and independent of line and point width. the gmch supports a single scissor box rectangle. 6.4.2.7 backface culling as part of the setup, the gmch can discard polygons from further processing, if they are either facing away from or towards the user?s viewpoi nt. this operation, referred to as back face culling is accomplished based on the clockwise or co unter-clockwise orientation of the vertices on a primitive. this can be enabled or disabled by the driver. 6.4.2.8 scan converter the scan converter takes the vertex and edge inform ation identifies all pixels that are affected by features being rendered. it works on a per-pol ygon basis, and one polygon may be entering the pipeline while calculations finish on another. 6.4.2.9 texture engine the gmch allows an image pattern or video to be placed on the surface of a 3d polygon. the texture engine performs texture color or chromakey matching texture filtering (anisotropic, trilinear, and bilinear) and yuv to rgb conversion. as texture sizes increase beyond the bounds of graphics memory, executing textures from graphics memory becomes impractical. every rendering pass would requi re copying each and every texture in a scene from system memory to graphics memory, then using the texture, and finally overwriting the local memory copy of the texture by copying the next texture into graphics memory. the gmch, using intel?s direct memory execution model, simplifies this process by rendering each scene using the texture located in system memory. the gmch includes a cache controller to avoid frequent memory fetches of recently used texture data.
functional description r 144 datasheet 6.4.2.10 perspective correct texture support a textured polygon is ge nerated by mapping a 2d texture patte rn onto each pixel of the polygon. a texture map is like wallpaper pasted onto the polygon. since polygons are rendered in perspective, it is important that texture be ma pped in perspective as well. without perspective correction, texture is distorted when an object recedes into the distance. perspective correction involves a compute-intensive ?pe r-pixel-divide? operation on each pixe l. perspective correction is necessary for realistic 3d graphics. 6.4.2.11 texture decompression as the textures? average size gets larger with higher color depth and multiple textures become the norm, it becomes increasingly important to provide support for compressed textures. microsoft directx* supports texture compression/decompression to reduce the bandwidth required to deliver textures. the gmch supports several compressed texture formats (directx: dxt1, dxt2, dxt3, dxt4, dxt5) and opengl fxt1 formats. 6.4.2.12 texture chromakey chromakey is a method for removing a specific color or range of colors from a texture map before it is applied to an object. for nearest texture filter modes, removing a color simply makes those portions of the object transparent (the prev ious contents of the back buffer show through). for linear texture filtering modes, the texture filter is modified if only the non-nearest neighbor texels match the key (range). chromakeying can be performed for both paletted and non-paletted textures, and removes texels that fall within a specified color range. the chromakey mode refers to testing the argb or yuv components to see if they fall between high and low state variable values. if the color of a texel contribution is in this range and chromakey is en abled, then this contribution is removed from the resulting pixel color. 6.4.2.13 anti-aliasing aliasing is one of the artifacts that degrade image quality. in its simplest manifestation, aliasing causes the jagged staircase effects on sloped lines and polygon edges. another artifact is the moir patterns, which occur as a result of the fact that there is very small number of pixels available on screen to contain the data of a high-resolution texture map. full scene anti-aliasing uses super-sampling, which means that the image is rendered internally at a higher resolution than it is displayed on screen. the gmch renders internally at 1600x1200, reads the image as a texture, and finally down-samples (via a bilinear filter) to the screen resolution of 640x480 and 800x600. full scene anti- aliasing removes jaggies at the edges.
functional description r datasheet 145 6.4.2.14 texture map filtering many texture-mapping modes are supported. perspective correct mapping is always performed. as the map is fitted across the polygon, the map can be tiled, mirrored in either the u or v directions, or mapped up to the end of the text ure and no longer placed on the object (this is known as clamp mode). the way a texture is combined with other object attributes is also definable. the gmch supports up to 12 levels-of-detail (lods) ranging in size from 2048x2048 to 1x1 texels. (a texel is defined as a texture map element.) included in the texture processor is a texture cache, which provides efficient mip-mapping. the gmch supports seven types of texture filtering: ? nearest (also known as point filteri ng): texel with coordinates n earest to the desired pixel is used. (this is used if only one lod is present.) ? linear (also known as bilinear filtering): a weighted average of a 2x2 area of texels surrounding the desired pixel is used. (this is used if only one lod is present.) ? nearest mip nearest (also known as point filtering) : this is used if many lods are present. the nearest lod is chosen and the texel with coordinates nearest to the desired pixel are used. ? linear mip nearest (bilinear mip mapping): this is used if many lods are present. the nearest lod is chosen and a weighted average of a 2x2 area of texels surrounding the desired pixel is used (four texels). this is also referred to as bilinear mip mapping. ? nearest mip linear (point mip mapping): this is used if many lods are present. two appropriate lods are selected and within each lod the texel with coor dinates nearest to the desired pixel are selected. the final texture value is generated by linear interpolation between the two texels select ed from each of the mip maps. ? linear mip linear (trilinear mip mapping): this is used if many lods are present. two appropriate lods are selected and a weighted average of a 2x2 area of texels surrounding the desired pixel in each mip map is generated (four texels per mip map). the final texture value is generated by linear interpolation betw een the two texels generated for each of the mip maps. trilinear mip mapping is used minimize the visibility of lod transitions across the polygon. ? anisotropic mip nearest (anisotropic filtering): this filter can be used when textured object pixels map back to significantly non-square regions of the texture (e.g., when the texture is scaled in one screen direction th an the other screen direction). ? both directx and opengl (rev.1.1) allow support for all these filtering modes. 6.4.2.15 multiple texture composition the gmch also performs multiple texture composition. this allows the combination of two or greater mip maps to produce a new one with new lods and texture attributes in a single or iterated pass. the setup engine supports up to four texture map coordinates in as single pass. the gmch allows up to two bilinear mip maps or a single trilinear mip map to be composited in a single pass. greater than two bilinear mip maps or more than one trilinear mip map would require multiple passes. the actual blending or composition of the mi p maps is done in the raster engine. the texture engine provides the requi red texels including blending information.
functional description r 146 datasheet flexible vertex format support allows multi-text uring because it makes it possible to pass more than one texture in th e vertex structure. 6.4.2.16 cubic environment mapping environment maps allow applications to render scenes with complex lighting and reflections while significantly decreasing cpu load. there are several methods to generate environment maps such as spherical, circular and cubic. the gmch supports cubic reflection mapping over spherical and circular since it is the best choice to provide real-time environment mapping for complex lighting and reflections. cubic mapping supports a texture map for each of the 6 cube faces. these can be generated by pointing a camera with a 90-degree field-of-view in the appropriate direction. per-vertex vectors (normal, reflection or refraction) are interpolated across the polygon and the intersection of these vectors with the cube texture faces are calculated. texel values ar e then read from the intersection point on the appropriate f ace and filtered accordingly. 6.4.2.17 bump mapping the gmch only supports embossed and dot product bump mapping, not environment bump mapping. 6.4.3 raster engine the raster engine is where the color data such as fogging, specular rgb, texture map blending, etc. is processed. the final color of the pixel is calculated and the rgb value combined with the corresponding components resulting from the texture engine. these textured pixels are modified by the specular and fog parameters. these specular highlighted, fogged, textured pixels are color blended with the existing values in the frame buffer. in parallel, stencil, alpha, and depth buffer tests are conducted which will determine whether the frame and depth buffers will be updated with the new pixel values. 6.4.3.1 texture map blending multiple textures can be blended together in an iterative process and applied to a primitive. the gmch allows up to four distinct or shared texture coordinates and texture maps to be specified onto the same polygon. also, the gmch supports a texture coordinate set to access multiple texture maps. state variables in multiple textures are bound to texture coordinates, texture map or texture blending. 6.4.3.2 combining intrinsic and specular color components the gmch allows an independen tly specified and interpolated specular rgb attribute to be added to the post-texture blended pixel color. this feature provides a full rgb specular highlight to be applied to a textured surface, permitting a high quality reflective colo red lighting effect not available in devices which apply texture after the lighting components have been combined. if the specular-add state variable is disa bled, only the resultant colors from the map blending are used. if this state variable is enabled, the specular rgb color is added to the rgb values from the output of the map blending.
functional description r datasheet 147 6.4.3.3 color shading modes the raster engine supports the flat and gouraud shading modes. these shading modes are programmed by the appropriate state variables issued through the command stream. ? flat shading is performed by smoothly interpolating the vertex intrinsic color components (red, green, blue), specular (r, g, b), fog, a nd alpha to the pixel, where each vertex color has the same value. the setup engine substitutes one of the vertex?s attribute values for the other two vertices attribute values thereby cr eating the correct flat shading terms. this condition is set up by the appropriate state variables issued prior to rendering the primitive. ? gouraud shading is performed by smoothly interpolating the vertex intrinsic color components (red, green, blue). specular (rgb), fog, and alpha to the pixel, where each vertex color has a different value. 6.4.3.4 color dithering color dithering in the gmch helps to hide color quantization errors for 16-bit color buffers. color dithering takes advantage of the human eye? s propensity to average the colors in a small area. input color, alpha, and fog components are c onverted from 8-bit components to 5-bit or 6-bit component by dithering. dithering is performed on blended textured pixels. in 32-bit mode, dithering is not performed. 6.4.3.5 vertex and per pixel fogging fogging is used to create atmospheric effects such as low visibility conditions in flight simulator- type games. it adds another level of realism to computer-generated scenes. fog can be used for depth cueing or hiding distant objects. with fog, distant objects can be rendered with fewer details (less polygons), thereby improving the rendering speed or frame rate. fog is simulated by attenuating the color of an object with the fog co lor as a function of distance, and the greater the distance, the higher the density (lower visibility for distant objects). there are two ways to implement the fogging technique: per-vertex (linear) fogging and per-pixel (non-linear) fogging. the per-vertex method interpolates the fog value at the vertices of a polygon to determine the fog factor at each pixel within the polygon. this method provides r ealistic fogging as long as the polygons are small. with large polygons (such as a ground plane depicting an airport runway), the per-vertex technique results in unnatural fogging. the gmch supports both types of fog operations, vertex and per pixel. if fog is disabled, the incoming color intensities are passed unchanged to the destination blend unit. if fog is enabled, the incoming pixel color is blended with the fog color based on a fog coefficient on a per pixel basis. 6.4.3.6 alpha blending alpha blending in the gmch adds the material property of transparency or opacity to an object. alpha blending combines a source pixel color and alpha component with a destination pixel color and alpha component. for example, this is so th at a glass surface on top (source) of a red surface (destination) would allow much of the red base color to show through. blending allows the source and destination color values to be multiplied by programmable factors and then combined via a programmable blend func tion. the combined and independent selection of factors and blend functions for color and alpha is supported.
functional description r 148 datasheet 6.4.3.7 color buffer formats: (destination alpha) the raster engine supports 8-bit, 16-bit, and 32-b it color buffer formats. the 8-bit format is used to support planar yuv4:2:0 format, which is used only in motion compensation and arithmetic stretch format. the bit format of color and z is allowed to mix. the gmch can support an 8-bit destination alpha in 32-bit mode. destination alpha is supported in 16-bit mode in 1:5:5:5 or 4:4:4:4 format. the gmch does not support general 3d rendering to 8-bit surfaces. 8-bit destinati ons are supported for operations on planar yuv surfaces (e.g., stretch blts) where each 8-bit co lor component is written in a se parate pass. the gmch also supports a mode where both u and v planar surfaces can be operated on simultaneously. the frame buffer of the gmch contains at least two hardware buffers - the front buffer (display buffer) and the back buffer (rendering buffer). while the back buffer may act ually coincide with (or be part of) the visible display surface, a se parate (screen or window-sized) back buffer is typically used to permit double-buffered drawing. that is, the image being drawn is not visible until the scene is complete and the back buffer made visible or copied to the front buffer via a 2d blt operation. rendering to one buffer and di splaying from the other buffer removes image tearing artifacts. additionally, more than two back buffers (e.g., triple-buffering) can be supported. 6.4.3.8 depth buffer the raster engine is able to read and write from this buffer and use the data in per fragment operations that determine resultant color and dept h value of the pixel for the fragment are to be updated or not. typical applications for en tertainment or visual simulations with exterior scenes require far/near ratios of 1000 to 10000. at 1000, 98% of the range is spent on the first 2% of the depth. this can cause hidden surface artifacts in di stant objects, especially when using 16-bit depth buffers. a 24- bit z-buffer provides 16 million z-values as oppose d to only 64 k with a 16-bit z-buffer. with lower z-resolution, two distant overlapping objects may be assigned the same z-value. as a result, the rendering hardware may have a probl em resolving the order of the objects, and the object in the back may appear through the object in the front. by contrast, when w (or eye-relative z) is used , the buffer bits can be more evenly allocated between the near and far clip planes in world sp ace. the key benefit is that the ratio of far and near is no longer an issue, and allows applica tions to support a maximum range of miles, yet still get reasonably accurate depth buffering within inch es of the eye point. th e selection of depth buffer size is relatively independent of the color buffer. a 16-bit z/w or 24-bit z/w buffer can be selected with a 16-bit color buffer. z buffer is not supported in 8-bit mode. 6.4.3.9 stencil buffer the raster engine provides 8-bit stencil buffer storage in 32-bit mode and the ability to perform stencil testing. stencil testing controls 3d drawing on a per pixel basis and conditionally eliminates a pixel on the outcome of a comparison between a stencil refere nce value and the value in the stencil buffer at the location of the source pi xel being processed. they are typically used in multipass algorithms to achieve special effects, such as decals, outlining, shadows, and constructive solid geometry rendering. one of three possible stencil operations is performed when stencil testing is enabled. the stencil operation specifies how the stencil buffer is modifi ed when a fragment passes or fails the stencil
functional description r datasheet 149 test. the selection of the stencil operation to be performed is based upon the result of the stencil test and the depth test. a stencil write mask is also included that controls the writing of particular bits into the stencil buffer. it selects between the destination value and the updated value on a per- bit basis. the mask is 8-bit wide. 6.4.3.10 projective textures the gmch supports two simultaneous projective text ures at full rate processing. these textures require three floating-point texture coordinates to be included in the fvf format. projective textures enable special effects such as projecting spot light textures obliquely onto walls, etc. 6.4.4 2d engine the gmch provides an extensiv e set of 2d instructions a nd 2d hw acceleration for block transfers of data (blts). the blt engine provides the ability to copy a source block of data to a destination and perform operations (e.g., rop1, rop2, and rop3) on the data using a pattern, and/or another destination. the st retch blt engine is used to move source data to a destination that need not be the same size, with source transparency. performing these common tasks in hardware reduces cpu load, and thus improves performance. 6.4.4.1 256-bit pattern fill and blt engine use of this blt engine accelerates the graphical user interface (gui) of microsoft* windows*. the gmch blt engine provides ha rdware acceleration of block tran sfers of pixel data for many common windows operations. the term blt refers to a block transfer of pixel data between system memory locations. the blt engi ne can be used for the following: ? move rectangular blocks of data between system memory locations ? data alignment ? perform logical opera tions (raster ops) the rectangular block of data does not change as it is transferred between system memory locations. data to be transferred can consist of re gions of system memory, patterns, or solid color fills. a pattern will always be 8x8 pixels wide a nd may be 8-bits, 16-bits, or 32-bits per pixel. the gmch blt engine has the ability to expand m onochrome data into a color depth of 8 bits, 16 bits, or 32 bits. blts can be either opaque or transparent. opaque tr ansfers, move the data specified to the destination. tr ansparent transfers co mpare destination color to source color and write according to the mode of transparency selected. data is horizontally and vertically aligned at the destination. if the destination for the blt overlaps with the source system memory location, the gmch can specify which area in system memory to begin the blt transfer. hardware is included for all 256 raster operations (source, pattern, and destination) defined by microsoft*, including transparent blt. the gmch has instructions to invoke blt operations, permitting software to set up instruction buffers and use batch processing as described in the instruction processing section. the gmch can perform hardware clipping during blts.
functional description r 150 datasheet 6.4.4.2 alpha stretch blt the stretch blt function can stretch source data in the x and y directions to a destination larger or smaller than the source. stretch blt functionality expands a region of system memory into a larger or smaller region using replication and interpolation. the stretch blt function also provides format conversion and data alignment. 6.4.5 planes and engines the gmch display can be functionally delineated into planes and engines (pipes and ports). a plane consists of rectangular sh aped image that has ch aracteristics such as source, size, position, method, and format. these planes get attached to source surfaces, which are rectangular system memory surfaces with a similar set of characteristics. they are also associated with a particular destination pipe. a pipe consists of a set of planes that will be combined with a timing generator. a port is the destination for the result of the pipe. the gmch supports one analog output port, one lvds lcd flat panel port, and two dvo ports. in conclu sion, planes are associated with pipes and pipes are associated with ports. 6.4.5.1 dual pipe independent display functionality the display consists of two display pipes, a and b. pipes have a set of planes that are assigned to them as sources. the analog display port may only use pipe a or pipe b, the dvo b or c ports may use either pipe a or pipe b, and the inte rnal lvds interface may only use pipe b. this limits the resolutions available on a digital display when an analog crt is active. table 37. dual display usage model (intel ? 852gm gmch) display pipe a display pipe b crt internal lvds dvo b or c or both crt crt dvo b or c or both dvo b or c or both internal lvds crt/dvo b or c or both (no tv support) internal lvds 6.4.6 hardware cursor plane the gmch supports two hardware cursors. the cursor plane is one of the simplest display planes. with a few exceptions, has a fixed size of 64 x 64 and a fixed z-order (top). in legacy modes, cursor can cause the display data below it to be inverted. in the alpha blend mode, true color cursor data can be alpha blended into the display stream. it can be assigned to either display pipe a or display pipe b and dynamically flipped from one to the other when both are running.
functional description r datasheet 151 6.4.6.1 cursor color formats color data can be in an indexed format or a true color format. indexed data uses the entries in the four-entry cursor palette to convert the two-bit i ndex to a true color format before being passed to the blenders. the index can optionally specify that a cursor pixel be tr ansparent or cause an inversion of the pixel value below it or one of two colors from the cursor palette. blending of yuv or rgb data is only supported with planes that have data of the same format. 6.4.6.2 popup plane (second cursor) the popup plane is used for control functions in mobile applications. only the hardware cursor has a higher z-order precedence over the hardware icon. in standard modes (non-vga) either cursor a or cursor b can be used as a popup icon. for vga modes, 32-bpp data format is not supported. 6.4.6.3 popup color formats source color data for the popup is in an indexed format. indexed data uses the entries in the four- entry cursor palette to convert the two-bit index to a true color format before being passed to the blenders. blending of color data is only supported with data of the same format. 6.4.7 overlay plane the overlay engine provides a method of merging either video capture data (from an external video capture device) or data delivered by the cpu, with the graphics data on the screen. 6.4.7.1 multiple overlays (display c) a single overlay plane and scalar is implemented. this overl ay plane can be connected to the primary display, secondary display or in bypass mode. in the default mode, it appears on the primary display. the overlay may be displayed in a multi-monitor scenario for single-pipe simultaneous displays only. picture-in-picture feature is supported via software through the arithmetic stretch blt. 6.4.7.2 source/destination color/chromakeying overlay source/destination chromakeying enables blending of the overlay with the underlying graphics background. destination color-/chromake ying can be used to handle occluded portions of the overlay window on a pixel-by-pixel basis that is actually an underlay. destination color keying supports a specific color (8-bit or 15-bit) mode as well as 32-bit alpha blending. source color/chromakeying is used to handle transparency based on the overlay window on a pixel-by-pixel basis. this is used when ?blue sc reening? an image to ove rlay the image on a new background later.
functional description r 152 datasheet 6.4.7.3 gamma correction to compensate for overlay color intensity loss, the overlay engine supports independent gamma correction. this allows the overlay data to be converted to linear data or corrected for the display device when not blending. 6.4.7.4 yuv to rgb conversion the format conversion can be bypassed in the case of rgb source data. 6.4.7.5 color control color control provides a method of changing the color characteristics of the pixel data. it is applied to the data while in yuv format and uses input parameters such as brightness, saturation, hue (tint) and contrast. this feature is supplied for the overlay only and works in yuv formats only. 6.4.7.6 dynamic bob and weave interlaced data that originates fro m a video camera creates two fields that are temporally offset by 1/60 of a second. there are several schemes to de-interlace the video stream: line replication, vertical filtering, field merging, and vertical te mporal filtering. field merging takes lines from the previous field and inserts them into the current field to construct the frame ? this is known as weaving. this is the best solution for images with little motion; however, showing a frame that consists of the two fields will have serration or feathering of moving edges when there is motion in the scene. vertical filtering or ?bob? interpolates ad jacent lines rather re plicating the nearest neighbor. this is the best solution for images with motion however, it w ill have reduced spatial resolution in areas that have no motion and introduce jaggies. in absence of any other de- interlacing, these form the baseline and are supported by the gmch. 6.4.8 video functionality the gmch supports mpeg-2 decoding hardware, sub-picture support and dtv. 6.4.8.1 mpeg-2 decoding the gmch mpeg2 decoding supports hardware motion compensation (hwmc). the gmch can accelerate video decoding for the following video c oding standards: ? mpeg-2 support ? mpeg-1: full feature support ? h.263 support ? mpeg-4: only supports some features in the simple profile the gmch hwmc interface is optimized for microsoft?s* va or api. hardware video acceleration api (hva) is a generic direct draw and directshow interface supported in windows xp, windows 2000 and windows 98 mille nnium to provide video decoding acceleration. direct va is the ope n standard implementation of hva, which is natively supported by the gmch hardware.
functional description r datasheet 153 6.4.8.2 hardware motion compensation the hwmc process consists of reconstructing a new picture by predicting (either forward, backward, or bi-directional) the resulting pixel co lors from one or more reference pictures. the gmch receives the video stream and implements motion compensation and subsequent steps in hardware. performing motion compensation in ha rdware reduces the processor demand of software-based mpeg-2 decoding, and thus improves system performance. 6.4.8.3 sub-picture support sub-picture is used for two purposes: subtitles for movie captions, which are superimposed on a main picture, and for menus to provide some visual operation environments for the user. dvd allows movie subtitles to be recorded as s ub-pictures. on a dvd disc, it is called subtitle because it has been prepared for storing captions. since the disc can have a maximum of 32 tracks for subtitles, they can be used for various applications, for example, as subtitles in different languages. there are two kinds of menus, the system menus and other in-title menus. first, the system menus are displayed and operated at startup of or during the playback of the disc or from the stop state. second, in-title menus can be programmed as a combination of su b-picture and highlight commands to be displayed during playback of the disc. the gmch supports sub-picture for dvd by mixing the two video streams via alpha blending. unlike color keying, alpha blending provides a softer effect and each pixel that is displayed is a composite between the two video stream pixe ls. the gmch can utilize four methods when dealing with sub-pictures. this flexibility means that the gmch can work with all sub-picture formats. 6.5 display interface the gmch has four dedicated display ports: an analog crt port, the internal lvds interface, and two digital display ports, dvob and c. dvob and c can support tv-out encoders, external dacs, lvds transmitters, and tmds transmitters. each display port has control signals that may be used to control, configure and/or determine the capabilities of an external device. the data that is sent out the display ports are selected from one of the two possible sources, display pipe a or display pipe b, except for the lvds port which can only be driven on pipe b. the gmch?s digital display port is capable of driving a 165 mhz pixel clock on a single dvo port, or 330 mhz pixel clock by combining dvob and dvoc. 6.5.1 analog display port characteristics the analog display port provides an rgb signal output along with an hsync and vsync signal. there is an associated ddc signal pair th at is implemented using gpio pins dedicated to the analog port. the intended target device is for a crt based monitor with a vga connector.
functional description r 154 datasheet 6.5.1.1 integrated ramdac the display function contains a 350 mhz, integrated, 24-bit, ram-based digital-to-analog converter (ramdac) that transforms up to 2048x1536 digital pixels at a maximum refresh rate of 75 hz. three, 8-bit dacs provide the r, g, and b signals to the monitor. 6.5.1.2 ddc (display data channel) ddc is defined by vesa. it allows communication between the host system and display. both configuration and control information can be ex changed allowing plug-and-play systems to be realized. support for ddc 1 and 2 is implemented. 6.5.2 digital display interface 6.5.2.1 dedicated lvds interface the gmch has a dedicated ansi/tia/eia ?644-1995 specification compliant dual channel lfp lvds interface that can support tft panel re solutions up to uxga with a maximum pixel format of 18 bpp (with ssc supported frequency range from 35 mhz to 112 mhz (single channel/dual channel). the display pipe selected by the lvds display port is programmed with the panel timing parameters that are determined by installed panel specifications or read from an onboard edid rom. the programmed timing values are then ?locked? into the registers to prevent unwanted corruption of the values. from that point on, the display modes are changed by selecting a different source size for that pipe, programming the vga registers, or selecting a source size and enabling the vga. the timing signals will remain stable and active through mode changes. these mode changes include vga to vga, vga to hires, hires to vga, and hires to hires. the transmitter can operate in a variety of modes and supports several data formats. the serializer supports 6-bit or 8-bit color and single or dual channel operating modes. the display stream from the display pipe is sent to the lvds transmitter port at the dot clock frequency, which is determined by the panel timing requirements. the output of lvds is running at a fixed multiple of the dot clock frequency, which is determined by the mode of operation; single or dual channel. depending on configuration and mode, a single channe l can take 18-bits of rgb pixel data plus 3 bits of timing control (hsync/vsync/de) and output them on three differential data pair outputs; or 24 bits of rgb plus 3 bits of timing control output on four differential data pair outputs. a dual channel interface conve rts 36 bits or 48 bits of color information plus the 3 bits of timing control and outputs it on six or eight sets of differential data outputs. this display port is normally used in conjunction w ith the pipe functions of panel scaling and a 6- bit to 8-bit dither. this display port is also used in conjunction with the panel power sequencing and additional associated functions. when enabled, the lvds constant current drivers consume significant power. individual pairs or sets of pairs can be selected to be powered do wn when not used. when disabled, individual or sets of pairs will enter a low power state. when the port is disabled all pairs enters a low power mode. the panel power sequencing can be set to override the selected power state of the drivers during power sequencing.
functional description r datasheet 155 6.5.2.2 lvds interface signals lvds for flat panel is compatible with the ansi/tia/eia-644 specification. this is an electrical standard only defining dr iver output characteristics and receive r input characteristics. there are two lvds transmitter channels (channel a and cha nnel b) in the lvds in terface. each channel consists of four data pairs and a clock pair. th e interface consists of a total of ten differential signal pairs of which eight are data and two ar e clocks. the phase locked transmit clock is transmitted in parallel with the data being sent out over the data pairs and over the lvds clock pair. each channel supports transmit clock frequency ranges from 35 mhz to 112 mhz, which provides a throughput of up to 784 mbps on each data output and up to 112 mhz on the input. when using both channels, they each operate at the same frequency each carrying a portion of the data. the maximum pixel rate is increased to 224 mhz but may be limited to less than that due to restrictions elsewhere in the circuit. the lvds port enable bit enab les or disables the entire lvds interface. when the port is disabled, it will be in a low power state. once the port is enabled, individual driver pairs will be disabled based on the operating mode. disabled dr ivers can be powered down for reduced power consumption or optionally fixed to forced 0?s output. 6.5.2.3 lvds pair states the lvds pairs can be put into one of the following five states: powered down tri-state, powered down zero volts, common mode, send zeros, or activ e. when in the active state, several data formats are supported. when in powered down state, the circuit enters a low power state and drives out 0 v or tri-states on both the output pins for the entire channel. the common mode tri- state is both pins of the pair set to the common mode voltage. when in the send zeros state, the circuit is powered up but sends only zero for the pixel color data regardless what the actual data is with the clock lines and timing signals sending the normal clock and timing data. 6.5.2.4 single channel versus dual channel mode both single channel and dual channel modes are available to allow interfacing to either single or dual channel panel interfaces. this lvds port can operate in single channel or dual channel mode. dual channel mode uses twice the number of lvds pairs and transfers the pixel data at twice the rate of the single channel. in general, one channel will be used for even pixels and the other for odd pixel data. the first pixel of the line is determined by the display enable going active and that pixel will be sent out channel a. all horizontal timings for active, sync, and blank will be limited to be on two pixel boundaries in the two channel modes. 6.5.2.5 lvds channel skew when in dual channel mode, the two channels must meet the panel requirements with respect to the inter channel skew. 6.5.2.6 ssc support the gmch is designed to tolerate 0.5%, 1.0%, and 2.5% down/center spread at a modulation rate from 30-50 khz triangle. an external ssc clock synthesizer can be used to provide the 48/66 mhz reference clock into the gmch pipe b pll.
functional description r 156 datasheet 6.5.2.7 panel power sequencing this section provides details for the power sequence timing relationship of the panel power, the backlight enable and the lvds data timing delivery. in order to meet the panel power timing specification requirements, tw o signals, panelvdden and panelbklten are provided to control the timing sequencing function of th e panel and the backlight power supplies. 6.5.2.7.1 panel power sequence states a defined power sequence is recommended when en abling the panel or disabling the panel. the set of timing parameters can vary from panel to panel vendor, provided that they stay within a predefined range of values. the panel vdd power, the backlight on/off state and the lvds clock and data lines are all managed by an internal power sequencer. a requested power-up sequence is only allowed to begin after the power cycle delay time requirement t4 is met. figure 9. panel power sequencing power on sequence from off state and power off sequence after full on panel vdd enable panel backlight enable clock/data lines t1+t2 t5 t3 valid t4 panel on off off tx t4
functional description r datasheet 157 table 38. panel power sequencing timing parameters panel power sequence timing parameters name spec name from to t1+t2 vdd on to lvds active panel vdd must be on for a minimum time before the lvds data stream is enabled. .1 vdd lvds active t5 backlight lvds data must be enabled for a minimum time before the backlight is turned on. lvds active backlight on tx backlight state backlight must be disabled for a minimum time before the lvds data stream is stopped. backlight off lvds off t3 lvds state data must be off for a minimum time before the panel vdd is turned off. lvds off start power off t4 power cycle delay when panel vdd is turned from on to off, a minimum wait must be satisfied before the panel vdd is enabled again. power off power on sequence start 6.5.2.8 back light inverter control the gmch offers integrated pwm for tft panel backlight inverter control. other methods of control are specified below: ? smbus-based backlight brightness control ? gmbus-based backlight brightness control ? pwm ? based backlight brightness control ? dbl(display brightness link) ?to- vdl (video data link) power sequencing. 6.5.2.9 digital video output port the gmch has the capability to support additional digital display devices (e.g. tmds transmitter, lvds transmitter or tv-out enc oder) through its digital video output port. dvob and c can each deliver a 165 mhz dot clock on each of their 12-bit in terfaces, or 330 mhz dot clock on a combined 24-bit interface. the digital display port consists of a dig ital data bus, vsync, hsync, and blank# signals. the data bus can operate only in a 12-bit mode . embedded sync information or hsync and vsync signals can optionally provide the basic timing information to the external device and the blank# signal indicates which clock cycles contain valid data. the blank# signal can be optionally selected to include the border area of the timing. the vsync and hsync signals can be disabled when embedded sync information is to be used or to support dpms. optionally a stall signal can cause the next line of data to not be sent until the stall signal is removed.
functional description r 158 datasheet optionally the field pin can indicate to the overlay which field is currently being displayed at the display device. 6.5.2.10 intel 855gme gmch agp interface overview the gmch support 1.5 v agp 1x/2x/4x devices. the agp signal buffers are 1.5 v drive/receive (buffers are not 3.3 v tolerant ). the gmch support 2x/4x source synchronous clocking transfers for read and write data, and sideband addressing. the gmch also support 2x and 4x clocking for fast writes initiated from the gmch (on behalf of the processor). agp pipe# or sba[7:0] transactions to dram do not get snooped and are, therefore, not coherent with the processor caches. agp fram e# transactions to dram are snooped. agp pipe# and sba[7:0] accesses to and from the hub interface are not supported. agp frame# access from an agp master to the hub interface is also not supported. only the agp frame memory writes from the hub interface are supported. 6.5.2.11 agp target operations as an initiator, the gmch does not initiate cycles using agp enhanced protocols. the gmch supports agp cycles targeting interface to main memory only. the gmch supports interleaved agp pipe#] and agp frame#, or agp sb a[7:0] and agp frame# transactions. table 39. agp commands supported by the gmch when acting as an agp target gmch host bridge agp command c/be[3:0]# encoding cycle destination response as pcix target read 0000 main memory low priority read 0000 the hub interface complete locally with random data; does not go to the hub interface hi-priority read 0001 main memory high priority read 0000 the hub interface complete locally with random data; does not go to the hub interface reserved 0010 n/a no response reserved 0011 n/a no response write 0100 main memory low priority write 0100 the hub interface cycle goes to dram with be?s inactive; does not go to the hub interface hi-priority write 0101 main memory high priority write 0101 the hub interface cycle goes to dram with be?s inactive; does not go to the hub interface reserved 0110 n/a no response reserved 0111 n/a no response long read 1000 main memory low priority read the hub interface complete locally with random data; does not go to the hub interface
functional description r datasheet 159 gmch host bridge agp command c/be[3:0]# encoding cycle destination response as pcix target hi-priority long read 1001 main memory high priority read the hub interface complete locally with random data; does not go to the hub interface flush 1010 gmch complete with qw of random data reserved 1011 n/a no response fence 1100 gmch no response - flag inserted in gmch request queue reserved 1101 n/a no response reserved 1110 n/a no response reserved 1111 n/a no response note: n/a refers to a function that is not applicable. as a target of an agp cycle, the gmch supports all the transactions targeted at main memory (summarized in the table above). the gmch supports both normal and high-priority, read and write requests. the gmch does not support agp cycles to the hub interface. pipe# and sba cycles are assumed not to requi re coherency management and all agp initiator accesses to main memory using agp pipe# or sb a protocol are treated as non- snoopable cycles. these accesses are directed to the agp aperture in main memory that is progr ammed as either uncacheable (uc) memory or write combining (wc) in the processor?s mtrrs. 6.5.3 agp transaction ordering the gmch observes transaction ordering rules as defined by the agp interface specification rev 2.0. 6.5.4 agp signal levels the 4x data transfers use 1.5 v signaling levels as described in the agp interface specification rev 2.0. the gmch supports 1x/2x data transfers using 1.5 v signaling levels. 6.5.5 4x agp protocol in addition to the 1x and 2x agp protocol, the gmch supports 4x agp read and write data transfers and 4x sideband address generation. the 4x operation is compliant with agp 2.0 specification. the gmch indicates that it supports 4x data transfers through rate[2] (bit 2) of the agp status register. when data_rate[2] of the agp command register is set to 1 during system initialization, the gmch performs agp read/write data transactions using 4x protocol. this bit is not dynamic. once this bit is set during initialization, the data transfer rate will not change.
functional description r 160 datasheet the 4x data rate transfer provides 1.06 gb/s transfer rates. the control signal protocol for the 4x data transfer protocol is identical to 1x/2x protocol. in 4x mode 16 bytes of data are transferred on every 66 mhz clock edge. the minimum throttleable block size remains four, 66 mhz clocks, which means 64 bytes of data are transferred per block. three additional signal pins are required to implement the 4x data transfer protocol. thes e signal pins are complementary data transfer strobes for the ad bus (2) and the sba bus (1). 6.5.5.1 fast writes the gmch supports 2x and 4x fast writes from the gmch to the graphics controller on agp. fast write operation is compliant with the agp 2.0 specification. the gmch will not generate fast back to back (fb2b) cycles in 1x mode, but will generate fb2b cycles in 2x and 4x fast write modes. to use the fast write protocol, the fast write enable configuration bit, agpcmd[fwen] (bit 4 of the agp command register), must be set to 1. memory writes originating from the host or from the hub interface use the fast write protocol when it is both capability enabled and enabled. the data rate used to perform the fast writes is dependent on the bits set in the agp command register bits 2:0 (data_rate). if bit 2 of the agpcmd[data_rate] field is 1, the data transfers occur using 4x strobing. if bit 1 of agpcmd[data_rate] field is 1, the data transfers occur using 2x strobing. if bit 0 of agpcmd[data_rate] field is 1, fast writes are disabled and data transfers occur using standard pci protocol. note that only one of the three data_rate bits may be set by initialization software. this is summarized in the following table. table 40. fast write initialization fwen data_rate [2] data_rate [1] data_rate [0] gmch =>agp master write protocol 0 x x x 1x 1 0 0 1 1x 1 0 1 0 2x strobing 1 1 0 0 4x strobing 6.5.5.2 agp frame# transactions on agp the gmch accepts and generates agp frame# transactions on the agp bus. the gmch guarantees that agp frame# accesse s to dram are kept coherent with the processor caches by generating snoops to the host bus. lock#, serr#, and perr# signals are not supported. gmch initiator and target operations table 41 summarizes gmch target operation for agp frame# initiators. the cycles can be either destined to main memory or the hub interface.
functional description r datasheet 161 table 41. pci commands supported by the gmch when acting as a frame# target gmch pci command c/be[3:0]# encoding cycle destination response as a frame# target interrupt acknowledge 0000 n/a no response special cycle 0001 n/a no response i/o read 0010 n/a no response i/o write 0011 n/a no response reserved 0100 n/a no response reserved 0101 n/a no response memory read 0110 main memory read 0110 the hub interface no response memory write 0111 main memory posts data 0111 the hub interface no response reserved 1000 n/a no response reserved 1001 n/a no response configuration read 1010 n/a no response configuration write 1011 n/a no response memory read multiple 1100 main memory read 1100 the hub interface no response dual address cycle 1101 n/a no response memory read line 1110 main memory read 1110 the hub interface no response memory write and invalidate 1111 main memory posts data 1111 the hub interface no response note: n/a refers to a function that is not applicable. as a target of an agp frame# cycle, the gmch only supports the following transactions: ? memory read, memory read line, and memory read multiple. these commands are supported identically by the gmch. the gmch does not support reads of the hub interface bus from agp. ? memory write and memory write and inva lidate. these commands are aliased and processed identically. the gmch does not support writes to the hub interface bus from agp. ? other commands. other commands such as i/o r/w and configuration r/w are not supported by the gmch as a target and result in master abort. ? exclusive access. the gmch does not sup port pci locked cycles as a target.
functional description r 162 datasheet ? fast back-to-back transactions. gmch as a targ et supports fast back-to-back cycles from an agp frame# initiator. as an initiator of agp frame# cycle, the gmch only supports the following transactions: ? memory read and memory read line. gmch supports reads from host to agp. gmch does not support reads from the hub interface to agp. ? memory read multiple. this command is not supported by the gmch as an agp frame# initiator. ? memory write. gmch initiates agp frame# cycles on behalf of the host or the hub interface. gmch does not issue memory write and invalidate as an initiator. gmch does not support write merging or write collapsing. gmch allows non-snoopable write transactions from the hub interface to the agp bus. ? i/o read and write. i/o read and write from th e host are sent to the agp bus. i/o base and limit address range for agp bus are programmed in agp frame# configuration registers. all other accesses that do not correspond to this programmed address range are forwarded to the hub interface. ? exclusive access. gmch does not issue a locked cycle on the agp bus on behalf of either the host or the hub interface. the hub interface and host locked transactions to agp are initiated as unlocked transactions by the gmch on the agp bus. ? configuration read and write. host configura tion cycles to agp are forwarded as type 1 configuration cycles. ? fast back-to-back transactions. gmch as an initiator does not perform fast back-to-back cycles. gmch retry/disconnect conditions the gmch generates retry/disc onnect according to the agp sp ecification rules when being accessed as a target from the agp frame# device. delayed transaction when an agp frame#-to-dram read cycle is retried by the gmch, it is processed internally as a delayed transaction. the gmch supports the delayed transaction mechanism on the agp target interface for the transactions issued using agp frame# protocol. this mechanism is compatible with the pci 2.1 specification. the process of latching all information required to complete the transaction, terminating with retry, and completing the request without holding the master in wait-states is called a delayed transaction. the gmch latches the address and command when establishing a delayed transaction. the gmch generates a delayed transaction on the agp only for agp frame# to dram read accesses. the gmch does not allow more than one delayed transaction access from agp at any time.
functional description r datasheet 163 6.5.6 concurrent and simultaneous display the gmch has two independent pipes, each with its own timing generato r and dot clock, and thus is able to support two displays concurrently. windows 98* and windows 2000* have enabled support for multi-monitor display. there are two types of multi-monitor solutions: concurrent and simultaneous. concurrent disp lays different data on two screens whereas simultaneous displays the same information on both displays. the gmch also supports a combination of concurrent and simultaneous displays.
functional description r 164 datasheet
power and thermal management r datasheet 165 7 power and thermal management the intel 855gm/855gme gmch chipset platform is intended to be compliant with the following specifications and technologies: ? apm rev 1.2 ? pci power management rev 1.0 ? pc?99, rev 1.0, pc?99a, and pc?01, rev 1.0 ? acpi 1.0b and 2.0 support ? acpi s0, s1-m, s3, s4, s5 , c0, c1, c2, c3 states ? internal graphics adapter d0, d1, d3 (hot/cold) ? on die thermal sensor, enabling core and system memory write thermal throttling for prevention of catastrophic thermal conditions ? external thermal sensor input pin ? enabling so-dimm thermal throttling ? the gmch also reduces i/o power dynamically, by disabling sense amps on input buffers, as well as tristating output buffers when possible ? dynamic clock power down reduces power in all modes of operation ? system memory self-refresh in c3 state (intel 855gme gmch) ? enhanced intel speedstep technology (using intel pentium m processor) ? flat panel power sequencing ? intel 855gm/gme gmch reduces i/o power dynamically by disabling sense amps on the input buffers, as well as tri-stating the output buffers when possible 7.1 general description of supported cpu states c0 (full on): this is the only state that runs software. all clocks are running, stpclk is deasserted, and the processor core is active. th e processor can service snoops and maintain cache coherency in this state. c1 (auto halt): the first level of power reduction occurs when the processo r executes an auto- halt instruction. this stops the execution of the instruction stream and reduces the processor?s power consumption. the processor can service snoops and maintain cache coherency in this state. c2 (stop grant): to enter this low power state, stpclk is asserted. the processor can still service snoops and maintain cach e coherency in this state. c3 (sleep or deep sleep): in these states the processor clock is stopped. the gmch assumes that no hub interface cycles (excep t special cycles) will occur while the gmch is in this state. the processor cannot snoop its caches to maintain coherency while in the c3 state. the gmch
power and thermal management r 166 datasheet will transition from the c0 state to the c3 state when software reads the level 3 register. this is an acpi defined register but bios or apm (via bios) can use this facility when entering a low power state. the host clock pll within the gmch can be programmed to be shut off for increased power savings and the gmch uses the dpslp signal input for this purpose. c4 (deeper sleep): the c4 state appears to th e gmch as identical to th e c3 state, but in this state the processor core voltage is lowered. there are no internal ev ents in gmch for the c4 state that differ from the c3 state. (c4 state not supported by intel celeron m processor) 7.2 7.2. general description of acpi states ? internal graphics adapter: ? d0 full on, display active ? d1 low power state, low latency recovery. no display, system memory retained ? d3 hot ? all state lost other than pci config. system memory lost (optionally) ? d3 cold ? power off cpu: ? c0 full on ? c1 auto halt ? c2 stop clock. clk to cpu still running. clock stopped to cpu core. ? c3 deep sleep. clock to cpu stopped. ? c4 deeper sleep. same as c3 with reduced voltage on the cpu. system states: ? g0/s0 full on ? g1/s1-m power on suspend (pos). system context preserved ? g1/s2 not supported. ? g1/s3 suspend to ram (str). power and context lost to chipset. ? g1/s4 suspend to disk (std). all power lost (except wakeup on ich4-m) ? g2/s5 soft off. total reboot.
power and thermal management r datasheet 167 7.3 enhanced intel speedstep ? technology overview with enhanced intel speedstep technology the pr ocessor core voltage changes and allows true cpu core frequency changes versus only clock throttling. table 42. enhanced intel speedstep ? technology overview cpu intel ? pentium ? m processor benefit over non-power managed cpu additional lower voltages and frequencies transition prompt os based on cpu load demand, thermal control, or user event based cpu availability cpu unavailability can be restricted to ~250 s (cpu dependent) by s/w 7.4 internal thermal sensor this section describes the new on-die thermal sensor capability. 7.4.1 overview the thermal sensor functions are provided below: catastrophic trip point: this trip point is programmed th rough the bios during initialization. this trip point is set at the temperature at which the gmch should be shut down immediately with minimal software support. th e settings for this are lockable. high temperature trip point: this trip point is nominally 14oc below the catastrophic trip point. the bios can be programmed to provide an interrupt when it is crossed in either direction. upon the trip event, hardware throttling may be enabled when the te mperature is exceeded. 7.4.2 hysteresis operation hysteresis provides a small amount of positive feedback to the thermal sensor circuit to prevent a trip point from flipping back and forth rapidly when the temperature is right at the trip point. 7.5 external thermal sensor input an external thermal sensor with a serial interface may be placed next to ddr sdram so- dimm (or any other appropriate platform locati on), or a remote thermal diode may be placed next to the so-dimm (or any other appropriate pl atform location) and conn ected to the external thermal sensor. intel advises that the external th ermal sensor contains some form of hysteresis, since none is provided by the gmch hardware. the external sensor can be connected to the ich4-m via the sm bus interface to allow programming and setup by bios so ftware over the serial interface. the external sensor?s output
power and thermal management r 168 datasheet should include an active-low open-drain signa l indicating an over-temp condition, which remains asserted for as long as the over-temp condition exists, and deasserts when temperature has returned to within normal operating range. this external sensor output will be connected to the gmch input (extts_0) and will trigger a pres et interrupt and/or read-throttle on a level- sensitive basis. additional external thermal sensor?s outputs, for multiple sensors, can be wire-or'ed together allow signaling from multiple sens ors located physically separate ly. software can, if necessary, distinguish which so-dimm(s) is the source of the over-temp through the serial interface. however, since the so-dimm(s) will be located on the same system memory bus data lines, any gmch-based read throttle will apply equally. note: the use of external sensors that include an internal pull-up resistor on the open-drain thermal trip output is discouraged. however, it may be possible depending on the size of the pull-up and the voltage of the sensor. please refer to the intel ? pentium ? m processor, intel ? celeron ? m processor, and intel ? 855gm/855gme gmch platform design guide . 7.5.1 usage external sensor(s) used for dyna mic temperature feedback control: ? sensor on so-dimms, which can be used to dynamically control read throttling.
electrical characteristics r datasheet 169 8 electrical characteristics 8.1 absolute maximum ratings table 43 lists the intel 855gm/855gme gmch maximum environmental stress ratings. functional operation at the absolute maximum and minimum is neither implied nor guaranteed. functional operating parameters are lis ted in the ac and dc tables. warning: stressing the device beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. operating bey ond the ?operating conditi ons? is not recommended and extended exposure be yond ?operating conditions? may affect reliability. table 43. absolute maximum ratings symbol parameter min max unit notes intel 855gm/855gme gmch common t die die temperature under bias 0 105 c 1 t storage storage temperature -55 150 c 2 vcc 1.2 v core supply voltage with respect to vss -0.3 1.65 v vttlf 1.05 v agtl+ buffer dc input voltage with respect to vss -0.3 1.55 v vcchl 1.2 v hub interface supply voltage with respect to vss -0.3 1.65 v vccadac 1.5 v dac supply voltage with respect to vss -0.3 1.65 v vccdvo 1.5 v supply voltage with respect to vss -0.3 1.65 v vccdlvds 1.5 v lvds digital power supply -0.3 1.65 v vcctxlvds 2.5 v lvds data/clock transmitter supply voltage with respect to vss -0.3 3.25 v vccalvds 1.5 v lvds analog s upply voltage with respect to vss -0.3 1.65 v vccsm 2.5 v ddr system memory data buffers supply voltage with respect to vss -0.3 3.25 v vccqsm 2.5 v ddr system memory clock buffers supply voltage with respect to vss -0.3 3.25 v vccasm (ddr 200/266 sdram) 1.2 v ddr system memory logic supply voltage (not connected to core) with respect to vss -0.3 1.65 v vccgpio 3.3 v gpio supply voltage with respect to vss -0.3 3.6 v
electrical characteristics r 170 datasheet symbol parameter min max unit notes vccahpll, vccagpll, vccadplla, vccadpllb power supply for the host pll, power supply for the hub pll, power supply for the display pll a, power supply for the display pll b, respectively -0.3 1.65 v intel 855gme gmch only vcc 1.35 v core supply voltage with respect to vss -0.3 1.65 v vcchi 1.35 v hub interface supply voltage with respect to vss -0.3 1.65 v vccasm (ddr333 sdram) 1.35 v ddr sdram system memory logic supply voltage (not connected to core) with respect to vss -0.3 1.65 v vccahpll, vccagpll, vccadplla, vccadpllb power supply for the host pll, power supply for the hub pll, power supply for the display pll a, power supply for the display pll b, respectively -0.3 1.65 v notes: 1. functionality is not guaranteed for parts that ex ceed tdie temperature above 105 c. full performance may be affected if the on-die thermal sensor is enabled. please refer to the intel? 852gm/855gm/855gme chipset mobile thermal design guide for supplementary details. 2. possible damage to the gmch may occur if the gmch temperature exceeds 150 c. intel does not guarantee functionality for parts that have ex ceeded temperatures above 150 c due to spec violation. 8.2 thermal characteristics the intel 855gm/855gme gmch is designed for operation at die temperatures between 0 c and 105 c. the thermal resistance of the package is given in table 44. table 44. intel ? 855gm/855gme gmch package thermal resistance parameter airflow velocity in meters/second 0 m/s 1 m/s jt ( c/watt)** 0.5 1.8 ja ( c/watt)** 20.0 17.3 note: ** estimate
electrical characteristics r datasheet 171 8.3 power characteristics table 45. power characteristics symbol parameter min typ max unit notes intel 855gm gmch only tdptyp thermal design power < 3.2 w intel 855gme gmch only tdptyp (max performance) thermal design power (internal graphics) < 4.3 w tdptyp (max performance) thermal design power (agp discrete graphics) < 3.2 w i vccmax 1.35 v core supply current 2.24 a i vcchi 1.35 v hub interface supply current 0.09 a i vccasm 1.35 v ddr sdram system memory dll supply current (ddr333 sdram) 0.09 a intel 855gm/855gme gmch common i gtl 1.05 v intel? pentium? m processor agtl+ supply current and 1.05 v dothan processor agtl+ supply current 0.69 a i vccmax 1.2 v core supply current 1.29 a i vccdlvds 1.5 v lvds (digital) supply current 0.04 a i vccalvds 1.5 v lvds (analog) supply current 0.07 a i vcctxlvds 2.5 v lvds (i/o) supply current 0.05 a i vccdac 1.5 v dac supply current 0.07 a i vcc1_5_dvo 1.5 v dvo/agp supply current 0.09 a i vcchi 1.2 v hub interface supply current 0.09 a i vccgpio 3.3 v gpio supply current 0.02 a 2.5 v ddr sdram system memory data buffer supply current (ddr266 sdram) 1.60 a i vccsm 2.5 v ddr sdram system memory data buffer supply current (ddr333 sdram for intel 855gme gmch only) 1.80 a i vccasm 1.2 v ddr sdram system memory dll supply current (ddr266 sdram) 0.24 a
electrical characteristics r 172 datasheet symbol parameter min typ max unit notes 2.5 v ddr sdram system memory clock buffers supply current (ddr266 sdram) 0.14 a i vccqsm 2.5 v ddr sdram system memory clock buffers supply current (ddr333 sdram) 0.18 a i sus_vccsm 2.5 v ddr sdram system memory interface standby supply current 1 ma i smvref_0 1.25 v ddr sdram system memory interface reference voltage supply current 0.05 ma i sus_smvref_0 1.25 v ddr sdram system memory interface reference voltage standby supply current 0.05 ma i ttrc/rcomp 1.25 v ddr sdram system memory interface resister compensation voltage supply current 40 ma i sus_ttrc 1.25 v ddr sdram system memory interface resister compensation voltage standby supply current 0 ma note: this spec is the thermal design power and is the estimated maximum possible expected power generated in a component by a realistic application. it is based on extrapolations in both hardware and software technology over the life of the com ponent. it does not represent the expected power generated by a power virus. studies by intel indicate that no application will cause thermally significant power dissipation exceeding this spec ification, although it is possible to concoct higher power synthetic workloads that write but never read. under realis tic read/write conditions, th is higher power workload can only be transient and is acc ounted in the icc (max) spec. 8.4 signal groups the signal description includes the type of buffer used for the particular signal: signal type description agtl+ open drain agtl+ interface signal. re fer to the agtl+ i/o specification for complete details. the intel 855gm/855gme gmch integrate most agtl+ termination resistors dvo/agp dvo buffers, these are 1.5 v tolerant. hub compatible to hub interface 1.5 sstl_2 stub series termination logic compatible signals (2.5 v tolerant) lvttl low voltage ttl compatible signals (3.3 v tolerant) cmos cmos buffers (3.3 v tolerant) lvds low voltage differential signal interface analog analog signal interface ref voltage reference signal
electrical characteristics r datasheet 173 table 46. table signals signal group signal type signals notes host interface signal groups (a) agtl+ input/outputs ads#, bnr#, breq0#,dbsy#, drdy#, dinv[3:0]#, ha[31:3]#, hadstb[1:0]#, hd[63:0]#,hdstbp[3:0]#, hdstbn[3:0]#, hit#, hitm#, hreq[4:0]#, hlock# (b) agtl+ common clock outputs bpri#, cpurst#, defer#, htrdy#, rs[2:0]#, dpwr# (d) analog/ref host miscellaneous signals havref, hccvref, hdvref[2:0], hxswing, hyswing, hxrcomp, hyrcomp (c) agtl+ asynchronous input dpslp#, hlock# dvo signal groups (e) dvo inputs dvobcclkint, dvocfldstl, dvobcintr#, dvobfldstl, addid[7:0], dvodetect (f) dvo outputs dvocd[11:0], dvochsync, dvocvsync, dvocblank#, dvobd[11:0], dvobhsync, dvobvsync, dvobblank# (e),(f) dvo ddc/i2c input/output mi2cclk, mi2cdata, mdviclk, mdvidata, mddcdata, mddcclk (g) analog/ref dvo miscellaneous signals gvref, dvorcomp agp signal groups (m1) agp i/o ad_stb0, ad_stb0#, ad_stb1, ad_stb1#, g_frame#, g_irdy#, g_trdy#, g_stop#, g_devsel#, g_ad[31:0], g_cbe[3:0]#, g_par (m2) agp input pipe#, sba[7:0], rbf#, wbf#, sbstb, sbstb#, g_req# (m3) agp output gst[2:0], g_gnt# lvds signal groups (h) lvds lvds outputs iyap[3:0], iyam[3:0], iybp[3:0], iybm[3:0] (i) analog lvds miscellaneous libg dac signal groups (j) cmos/analog dac outputs red, red#, green, green#, blue, blue# (k) analog/ref dac miscellaneous refset
electrical characteristics r 174 datasheet signal group signal type signals notes hub interface signal groups (l) cmos hi inputs/outputs hl[10:0], hlstb, hlstb# (m) analog/ref hi miscellaneous hlrcomp, pswing, hlvref ddr sdram interface signal groups (n) sstl_2 ddr input/outputs sdq[63:0], sdqs[7:0] (o) sstl_2 ddr outputs scs[3:0]#, sma[12:0], sba[1:0], sras#, scas#, swe#, scke[3:0], smab[5,4,2,1], sdm[7:0] (p) analog/ref ddr miscellaneous smvref_0, smvswingh, smvswingl, smrcomp clocks, reset, and miscellaneous signal groups (q) cmos inputs rstin#(3.3v), pwrok, extts_0 (r) cmos outputs agpbusy#,panelvdden, panelbklten, panelbkltctl, lclkctla, lclkctlb, hsync, vsync (q),(r) cmos ddc/i 2 c input/outputs ddcadata, ddcpdata, ddcaclk, ddcpclk (t) cmos clock inputs gclkin (u) cmos clock outputs sck[5:0], sck[5:0]# (w) 1.5 v clock inputs dpms (x) dvo clock outputs dvocclk, dvocclk#, dvobclk, dvobclk# (z) cmos low voltage differential inputs bclk, bclk# (a1) lvttl inputs drefclk, drefssclk (b1) lvds clock outputs iclkap, iclkam, iclkbp, iclkbm i/o buffer supply voltages/grounds (intel 855gme gmch only) (n1) 1.35 v core vcc (p1) 1.35 v hub interface vcchl (s1) 1.35 v pll vccagpll, vccahpll, v ccadplla, vccadpllb
electrical characteristics r datasheet 175 signal group signal type signals notes (q1) 1.35v ddr sdram dll supply vccasm i/o buffer supply voltages/grounds (intel 855gm/855gme gmch common) (m1) agtl+ power supply vttlf (d1) 1.2 v core vcc (e1) 1.2 v hub interface vcchl (f1) 1.2 v pll vccagpll, vccahpll, v ccadplla, vccadpllb (g1) 2.5 v ddr sdram supply vccsm, vccqsm (g1) 1.2v ddr sdram dll supply vccasm (h1) 1.5 v dvo supply vccdvo (i1) 1.5 v dac supply vccadac (j1) 3.3 v gpio supply vccgpio (k1) 1.5 v lvds digital supply vccdlvds (k1) 2.5 v lvds data/clk transmitter supply vcctxlvds (k1) 1.5 v lvds analog supply vccalvds
electrical characteristics r 176 datasheet 8.5 dc characteristics 8.5.1 general dc characteristics table 47. dc characteristics symbol signal group parameter min nom max unit notes supply voltages (intel 855gme gmch only) vcc (n1) core voltage 1.28 1.35 1.42 v vcchl (p1) hi i/o supply voltage 1.28 1.35 1.42 v vccasm (q1) ddr sdram i/o supply voltage 1.28 1.35 1.42 v vccagpll vccahpll vccadplla vccadpllb (s1) pll supply voltage 1.28 1.35 1.42 v supply voltages (intel 855gm/855gme gmch common) vttlf (m1) agtl+ power supply 1.0 1.05 1.1 v vccsm vccqsm (g1) ddr sdram i/o supply voltage 2.375 2.5 2.625 v vccasm (g1) ddr sdram i/o supply voltage 1.14 1.2 1.26 v vcchl (e1) hi i/o supply voltage 1.14 1.2 1.26 v vccagpll vccahpll vccadplla vccadpllb (f1) pll supply voltage 1.14 1.2 1.26 v vcc (d1) core voltage 1.14 1.2 1.26 v vccdvo (h1) dvo i/o voltage 1.425 1.5 1.575 v vccdlvds (k1) digital lvds supply voltage 1.425 1.5 1.575 v vcctxlvds (k1) data/clock transmitter lvds supply voltage 2.375 2.5 2.625 v
electrical characteristics r datasheet 177 symbol signal group parameter min nom max unit notes vccalvds (k1) analog lvds supply voltage 1.425 1.5 1.575 v vccadac (i1) dac supply voltage 1.425 1.5 1.575 v vccgpio (j1) cmos supply voltage 3.135 3.3 3.465 v reference voltages havref (d) host address and reference voltage (0.66 x vttlf) ? 2% 0.66 x vttlf (0.66 x vttlf)+ 2% v hdvref[2:0] (d) host data reference voltage (0.66 x vttlf) ? 2% 0.66 x vttlf (0.66 x vttlf)+ 2% v hccvref (d) host common clock voltage (0.66 x vttlf) ? 2% 0.66 x vttlf (0.66 x vttlf)+ 2% v hxswing hyswing (d) host compensation reference voltage (0.33 x vttlf)? 2% 0.33 x vttlf (0.33 x vttlf) + 2% v hlvref (m) hub interface reference voltage 0.343 0.350 0.357 v smvref_0 (p) ddr reference voltage 0.49 x vccsm 0.5 x vccsm 0.51 x vccsm v gvref (g) dvo reference voltage 0.73 0.75 0.77 v pswing (m) rcomp buffer differential amp reference voltage 0.8 ? 2% 0.8 0.8 + 2% v smvswingh (p) system memory rcomp buffer differential amp reference voltage (vccsm* 0.8)-2% vccsm * 0.8 (vccsm* 0.8) + 2% v
electrical characteristics r 178 datasheet symbol signal group parameter min nom max unit notes smvswingl (p) system memory rcomp buffer differential amp reference voltage (vccsm * 0.2) - 2 % vccsm * 0.2 (vccsm * 0.2) + 2% v host interface v il_h (a), (c) host agtl+ input low voltage -0.10 0 (0.66 x vttlf) ? 0.1 v v ih_h (a),(c) host agtl+ input high voltage (0.66 x vttlf) + 0.1 vtt vttlf+ 0.1 v v ol_h (a),(b) host agtl+ output low voltage (0.33 x vttlf) + 0.1 v v oh_h (a),(b) host agtl+ output high voltage vttlf- 0.1 vttlf v i ol_h (a),(b) host agtl+ output low current vttlfma x/0.75rtt min ma rttmin =45 ? ? i leak_h (a),(c) host agtl+ input leakage current 2 a vol< vpad< vttl f, 2 c pad (a),(c) host agtl+ input capacitance 1 1.1 1.3 pf c pckg (a),(c) host agtl+ input capacitance (common clock) 1 2 2.5 pf 1 ddr interface v il(dc) (n) ddr sdram input low voltage smvref ? 0.15 v v ih(dc) (n) ddr sdram input high voltage smvref + 0.15 v v il(ac) (n) ddr sdram input low voltage smvref ? 0.31 v
electrical characteristics r datasheet 179 symbol signal group parameter min nom max unit notes v ih(ac) (n) ddr sdram input high voltage smvref + 0.31 v v ol (o), (u) ddr sdram output low voltage 0.6 v v oh (o), (u) ddr sdram output high voltage 1.9 v i ol (o), (u) ddr sdram output low current 30 ma i oh (o), (u) ddr sdram output high current -30 ma i leak (n) input leakage current 10 a c pad (n) ddr sdram input/output pin capacitance 4 5 6 pf c pckg (n) ddr sdram input/output pin capacitance 1 2 3 pf 1 1.5v agp interface v il_a (m1), (m2) agp input low voltage gvref ? 0.15 v v ih_a (m1), (m2) agp input high voltage gvref+ 0.15 v v ol_a (m1), (m3) agp output low voltage 0.225 v v oh_a (m1), (m3) agp output high voltage 1.275 v i ol_a (m1), (m3) agp output low current 6.9 ma @0.15 vddq i oh_a (m1), (m3) agp output high current -6.9 ma @.85 vddq i leak_a (m1), (m2) agp input leakage current 10 a 0 electrical characteristics r 180 datasheet symbol signal group parameter min nom max unit notes 1.5 v dvo interface: functional operating range (vcc=1.5 v 5%) v il_dvo (e), (w) dvo input low voltage gvref ? 0.15 v v ih_dvo (e), (w) dvo input high voltage gvref+ 0.15 v v ol_dvo (f), (x) dvo output low voltage 0.225 v v oh_dvo (f), (x) dvo output high voltage 1.275 v i ol_dvo (f), (x) dvo output low current 6.9 ma @0.15 vddq i oh_dvo (f), (x) dvo output high current -6.9 ma @.85 vddq i leak_dvo (e), (w) dvo input leakage current 10 a 0 electrical characteristics r datasheet 181 symbol signal group parameter min nom max unit notes c pad (l) hub interface input capacitance 2 3 4 pf c pckg (l) hub interface input capacitance 1 2 3 pf lvds interface: functional operating range (vcc=2.5 v 5%) v od (h), (b1) differential output voltage 250 345 450 mv ? v od (h), (b1) change in v od between complimentary output states 50 mv v os (h), (b1) offset voltage 1.125 1.25 1.375 v ? v os (h), (b1) change in v os between complimentary output states 50 mv i os (h), (b1) output short circuit current -3.5 -10 ma i oz (h), (b1) output tri- state current 1 10 a miscellaneous signals v il (q) input low voltage (cmos inputs) 0.80 v v ih (q) input high voltage (cmos inputs) 2.0 v v ol (r) output low voltage (cmos outputs) 0.1 x vcc v iol= 1 ma v oh (r) output high voltage (cmos outputs) 0.9 x vcc v ioh = 1 ma, 7 i ol (r) output low current (cmos outputs) 1 ma @vo l_hi max i oh (r) output high current (cmos outputs) -1 ma @vo h_hi min
electrical characteristics r 182 datasheet symbol signal group parameter min nom max unit notes i leak (q) input leakage current (cmos inputs) 10 a 0 electrical characteristics r datasheet 183 symbol signal group parameter min nom max unit notes v ih (t), (a1) input high voltage (cmos/lvtt l clk inputs) 2.0 v c pad (t) input capacitance (cmos clk inputs) 1 1.25 1.5 pf c pckg (t) input capacitance (cmos clk inputs) 1 2 3 pf 1 notes: 1. c pckg is the trace capacitance in the gmch/mch package. 8.5.2 dac dc characteristics table 48. dac dc characteristics: functi onal operating range (vccdac = 1.5 v 5%) parameter min typical max units notes dac resolution 8 bits (1) max luminance (full-scale) 0.665 0.700 0.770 v (1, 2, 4) white video level voltage min luminance 0.000 v (1, 3, 4) black video level voltage lsb current 73.2 a (4, 5) integral linearity (inl) 0 +2.0 lsb (1, 6) differential linearity (dnl) -1.0 +1.0 lsb (1, 6) video channel-channel voltage amplitude mismatch 6 % (7) monotonicity guaranteed notes: 1. measured at each r, g, b termination accordi ng to the vesa test procedure ? evaluation of analog display graphics subsystems proposal (ver sion 1, draft 4, december 1, 2000). 2. max steady-state amplitude 3. min steady-state amplitude 4. defined for a double 75- termination. 5. set by external reference resistor value. 6. inl and dnl measured and calculated according to vesa video signal standards. 7. max full-scale voltage difference among r,g,b output s (percentage of steady-state full-scale voltage) note: refer to the intel ? pentium ? m processor and intel ? 855gm/855gme chipset platform design guide for interconnect length specifications.
electrical characteristics r 184 datasheet 8.5.3 dac reference and output specifications table 49. dac reference and output specifications parameter min typical max units notes reference resistor 124 127 130 ? 1% tolerance, 1/16 w r,g,b termination resistor 75 ? (1) 1% tolerance, 1/16 w video filter ferrite bead 75 ? @ 100- mhz, (each r,g,b output) video filter capacitors 3.3 pf two capacitors per r,g,b output notes: 1. vesa video signal standard 2. complement dac channel output termination resistor s are only required for differential video routing to the vga connector.
video filter capacitors and ferrite bead arranged in a pi configuration (one pi filter testability) r datasheet 185 9 video filter capacitors and ferrite bead arranged in a pi configuration (one pi filter testability) in the intel 855gm/gme gmch, testability for automated test equipment (ate) board level testing has been implemented as an xor chain. an xor-tree is a chain of xor gates, each with one input pin connected to it. the xor chain test mode is used by product engineers during manufacturing and oems during board level connectivity tests. the main purpose of this test mode is to detect connectivity shorts between adjacent pins and to check proper bonding between i/o pads and i/o pins. figure 10. xor?tree chain input xor out xor.vsd input input input input vcc1_2 the algorithm used for in?circuit test is as follows: 1. drive all input pins to an initial logic level 1. observe the output corres ponding to scan chain being tested. 2. toggle pins one at a time starting from the first pin in the chain, continuing to the last pin, from its initial logic level to the opposite logi c level. observe the out put changes with each pin toggle
video filter capacitors and ferrite bead arranged in a pi configuration (one pi filter testability) r 186 datasheet 9.1 xor test mode entry figure 11. xor chain test mode entry events diagram powerok lclkctla hsync don't care don't care rstin# (p c i re se t) don't care vsync note: hsync and lclkctla = xor chain test mode activati on; no clock is required for xor chain test mode. a minimum of 50 ns pwrok assertion prio r to rstin# assertion is recommended. a minimum of 10 ns vsync/hsync/lclkctla assertion pr ior to pwrok assertion is recommended. figure 12. allz test mode entry events diagram powerok lclkctla don't care hsync vsync don't care don't care rstin# (p c i re set) note: vsync and lclkctla = all z test mode activation; no clock is required for allz test mode activation. a minimum of 50 ns pwrok asserti on prior to rstin# assertion is recommended. a minimum of 10 ns vsync/hsync/lclkctla asserti on prior to pwrok assertion is recommended.
video filter capacitors and ferrite bead arranged in a pi configuration (one pi filter testability) r datasheet 187 9.2 xor chain differential pairs table 50 provides differential signals in the xor chains that must be treated as pairs. pin1 and pin2 as shown below need to drive to the opposite value always. table 50. differential signals in the xor chains pin1 pin2 xor chain dvocclk# dvocclk dvo xor 2 hlstb# hlstb hub xor 9.3 xor chain exclusion list see table 51 for a list of pins that are not included in the xor chains (excluding all vcc/vss/vtt). note: connectivity column is used to identify what need to be driven on that particular pin during xor chain test mode. table 51. xor chain exclusion list of pins item# in/out ball pin/vhdl i/o type voltage connectivity 1 in y3 gclkin pll clk 3.3 0 2 - w1 hlvref analog 1/3 vcchl 0.4 3 - t2 hlrcomp analog n/a n/a 4 - u2 pswing analog n/a n/a 5 - f1 gvref analog 1/2 vccdvo 0.75 6 - d1 dvorcomp analog n/a n/a 7 in j11 pwrok cmos 3.3 n/a 8 in b7 drefclk pll clk 3.3 0 9 - e8 refset analog n/a n/a 10 - c9 blue analog n/a n/a 11 - d9 blue# analog n/a n/a 12 - c8 green analog n/a n/a 13 - d8 green# analog n/a n/a 14 a7 red analog n/a n/a 15 - a8 red# analog n/a n/a 16 - d12 lvrefh analog 1.1 1.1 17 - a10 libg analog n/a n/a
video filter capacitors and ferrite bead arranged in a pi configuration (one pi filter testability) r 188 datasheet item# in/out ball pin/vhdl i/o type voltage connectivity 18 - b12 lvbg analog n/a n/a 19 - f12 lvrefl analog 1.1 1.1 20 in b17 drefssclk pll clk 3.3 0 21 - j17 hdvref[2] analog 2/3 vttlf 1.0 22 - b20 hxrcomp analog n/a n/a 23 - b18 hxswing analog n/a n/a 24 - j21 hdvref[1] analog 2/3 vttlf 1.0 25 in ad29 bclk# diff 0.7 0 26 in ae29 bclk diff 0.7 0.7 27 - k21 hdvref[0] analog 2/3 vttlf 1.0 28 - y28 hccvref analog 2/3 vttlf 1.0 29 - y22 havref analog 2/3 vttlf 1.0 30 - h28 hyrcomp analog n/a n/a 31 - k28 hyswing analog n/a n/a 32 in d28 rstin# cmos 3.3 n/a 33 - aj24 smvref_0 analog 1/2 vccsm 1.25 34 - ab1 smrcomp analog n/a n/a 9.4 xor chain connectivity/ordering the following tables contain the ordering for all of the intel 855gm/gme gmch xor chains and pin to ball mapping information: table 52. xor mapping xor chain dvo 1 dvo in/out ball pin/vhdl i/o type voltage xor out out ab5 sma[12] sstl_2 2.5 1 inout t6 rsvd dvo 1.5 2 inout t5 rsvd dvo 1.5 3 inout t7 mddcdata dvo 1.5 4 inout r3 rsvd dvo 1.5 5 inout r4 rsvd dvo 1.5 6 inout r6 rsvd dvo 1.5 7 inout r5 rsvd dvo 1.5 8 inout p2 rsvd dvo 1.5 9 inout p4 rsvd dvo 1.5
video filter capacitors and ferrite bead arranged in a pi configuration (one pi filter testability) r datasheet 189 10 inout p3 rsvd dvo 1.5 11 inout p6 rsvd n/a n/a 12 inout p5 rsvd n/a n/a 13 inout n2 rsvd n/a n/a 14 inout n3 rsvd n/a n/a 15 inout m1 rsvd n/a n/a 16 inout n5 rsvd n/a n/a 17 inout m2 rsvd n/a n/a 18 inout m5 rsvd n/a n/a 19 inout m3 dvobcclkint dvo 1.5 20 inout l2 rsvd n/a n/a 21 inout p7 mddcclk dvo 1.5 22 inout n6 mi2cdata dvo 1.5 23 inout m6 mdvidata dvo 1.5 24 inout n7 mdviclk dvo 1.5 25 inout l7 dvodetect dvo 1.5 26 inout k7 mi2cclk dvo 1.5 27 out b2 rsvd n/a n/a 28 in b3 rsvd n/a n/a xor chain dvo 2 dvo in/out ball pin/vhdl i/o type voltage xor out out ad5 sma[11] sstl_2 2.5 1 inout l3 dvocblank# dvo 1.5 2 inout k1 dvocd[1] dvo 1.5 3 inout l4 rsvd dvo n/a 4 inout l5 dvocvsync dvo 1.5 5 inout k2 dvocd[3] dvo 1.5 6 inout k5 dvocd[0] dvo 1.5 7 inout k3 dvocd[2] dvo 1.5 8 inout j2 dvocclk# dvo 1.5 9 inout j3 dvocclk dvo 1.5 10 inout h2 dvocd[6] dvo 1.5 11 inout j5 dvocd[5] dvo 1.5 12 inout h1 dvocd[7] dvo 1.5 13 inout j6 dvocd[4] dvo 1.5 14 inout k6 dvochsync dvo 1.5 15 inout h4 dvocd[9] dvo 1.5
video filter capacitors and ferrite bead arranged in a pi configuration (one pi filter testability) r 190 datasheet 16 inout h3 dvocd[8] dvo 1.5 17 inout h5 dvocfldstl dvo 1.5 18 inout h6 dvocd[10] dvo 1.5 19 inout g2 dvobcint# dvo 1.5 20 inout g3 dvocd[11] dvo 1.5 21 in d2 rsvd n/a n/a 22 in d3 rsvd n/a n/a 23 in f4 addid[5] dvo 1.5 24 in f5 addid[1] dvo 1.5 25 in f6 addid[7] dvo 1.5 26 in e2 addid[3] dvo 1.5 27 in e5 addid[0] dvo 1.5 28 in f3 rsvd n/a n/a 29 in f2 rsvd n/a n/a 30 out c2 rsvd n/a n/a 31 in e3 addid[2] dvo 1.5 32 out c3 gst[1] dvo 1.5 33 out c4 gst[0] dvo 1.5 34 in g5 addid[4] dvo 1.5 35 in g6 addid[6] dvo 1.5 36 in d5 dpms dvo 1.5 xor chain fsb 1 in/out ball pin i/o type voltage xor out out ac19 sma[10] sstl_2 2.5 1 inout d16 hd[62]# agtl+ 1.5 2 inout c16 hd[60]# agtl+ 1.5 3 inout g16 hd[58]# agtl+ 1.5 4 inout c17 hd[55]# agtl+ 1.5 5 inout e17 hd[61]# agtl+ 1.5 6 inout e16 hd[59]# agtl+ 1.5 7 inout f17 hd[56]# agtl+ 1.5 8 inout b19 hd[57]# agtl+ 1.5 9 inout e18 hdstbp[3]# agtl+ 1.5 10 inout d18 hdstbn[3]# agtl+ 1.5 11 inout c18 hd[63]# agtl+ 1.5 12 inout g17 hd[51]# agtl+ 1.5 13 inout c19 hd[54]# agtl+ 1.5
video filter capacitors and ferrite bead arranged in a pi configuration (one pi filter testability) r datasheet 191 14 inout d20 hd[52]# agtl+ 1.5 15 inout e20 hd[50]# agtl+ 1.5 16 inout e19 hd[49]# agtl+ 1.5 17 inout g19 dinv[3]# agtl+ 1.5 18 inout f19 hd[53]# agtl+ 1.5 19 inout g18 hd[48]# agtl+ 1.5 20 inout b21 hd[32]# agtl+ 1.5 21 inout c20 hd[46]# agtl+ 1.5 22 inout c23 hd[35]# agtl+ 1.5 23 inout b23 hd[43]# agtl+ 1.5 24 inout b22 hd[42]# agtl+ 1.5 25 inout b25 dinv[2]# agtl+ 1.5 26 inout d22 hd[36]# agtl+ 1.5 27 inout c24 hd[34]# agtl+ 1.5 28 inout c21 hd[47]# agtl+ 1.5 29 inout e21 hdstbp[2]# agtl+ 1.5 30 inout e22 hdstbn[2]# agtl+ 1.5 31 inout d24 hd[39]# agtl+ 1.5 32 inout c25 hd[37]# agtl+ 1.5 33 inout f21 hd[45]# agtl+ 1.5 34 inout e24 hd[38]# agtl+ 1.5 35 inout e23 hd[41]# agtl+ 1.5 36 inout g21 hd[33]# agtl+ 1.5 37 inout f23 hd[44]# agtl+ 1.5 38 inout g20 hd[40]# agtl+ 1.5 39 out m27 rs[2]# agtl+ 1.5 40 out p28 bpri# agtl+ 1.5 41 out aa22 dpwr# agtl+ 1.5 42 inout aa26 hadstb[1]# agtl+ 1.5 xor chain fsb 2 in/out ball pin i/o type voltage xor out out ac5 sma[9] sstl_2 2.5 1 inout e25 dinv[1]# agtl+ 1.5 2 inout b26 hd[26]# agtl+ 1.5 3 inout c26 hd[28]# agtl+ 1.5 4 inout b27 hd[18]# agtl+ 1.5 5 inout b28 hd[31]# agtl+ 1.5
video filter capacitors and ferrite bead arranged in a pi configuration (one pi filter testability) r 192 datasheet 6 inout g23 hd[30]# agtl+ 1.5 7 inout e26 hd[9]# agtl+ 1.5 8 inout d26 hdstbp[1]# agtl+ 1.5 9 inout c27 hdstbn[1]# agtl+ 1.5 10 inout g22 hd[27]# agtl+ 1.5 11 inout g24 hd[24]# agtl+ 1.5 12 inout c28 hd[25]# agtl+ 1.5 13 inout e27 hd[20]# agtl+ 1.5 14 inout f2 hd[17]# agtl+ 1.5 15 inout d27 hd[23]# agtl+ 1.5 16 inout g25 hd[21]# agtl+ 1.5 17 inout f25 hd[16]# agtl+ 1.5 18 inout h23 hd[19]# agtl+ 1.5 19 inout f28 hd[22]# agtl+ 1.5 20 inout k23 hd[11]# agtl+ 1.5 21 inout j23 hd[14]# agtl+ 1.5 22 inout h25 hd[10]# agtl+ 1.5 23 inout g27 hd[12]# agtl+ 1.5 24 inout k22 hd[0]# agtl+ 1.5 25 inout h26 hd[15]# agtl+ 1.5 26 inout g28 hd[5]# agtl+ 1.5 27 inout h27 hd[1]# agtl+ 1.5 28 inout j24 hd[9]# agtl+ 1.5 29 inout l23 hd[7]# agtl+ 1.5 30 inout k25 hd[2]# agtl+ 1.5 31 inout k27 hdstbp[0]# agtl+ 1.5 32 inout j28 hdstbn[0]# agtl+ 1.5 33 inout j25 dinv[0]# agtl+ 1.5 34 inout k26 hd[13]# agtl+ 1.5 35 inout l24 hd[3]# agtl+ 1.5 36 inout l25 hd[8]# agtl+ 1.5 37 inout l27 hd[6]# agtl+ 1.5 38 inout j27 hd[4]# agtl+ 1.5 39 out m28 defer# agtl+ 1.5 40 out n23 rs[0]# agtl+ 1.5 41 out p26 rs[1]# agtl+ 1.5 42 inout t26 hadstb[0]# agtl+ 1.5
video filter capacitors and ferrite bead arranged in a pi configuration (one pi filter testability) r datasheet 193 xor chain fsb 3 in/out ball pin i/o type voltage xor out out ac6 sma[8] sstl_2 2.5 1 out f15 cpurst# agtl+ 1.5 2 in y23 dpslp# cmos 1.5 3 inout n27 hit# agtl+ 1.5 4 inout n28 hitm# agtl+ 1.5 5 inout n25 bnr# agtl+ 1.5 6 inout n24 drdy# agtl+ 1.5 7 in p27 hlock# agtl+ 1.5 8 inout m23 breq0# agtl+ 1.5 9 out m25 htrdy# agtl+ 1.5 10 inout m26 dbsy# agtl+ 1.5 11 inout l28 ads# agtl+ 1.5 12 inout r28 hreq[0]# agtl+ 1.5 13 inout p25 hreq[1]# agtl+ 1.5 14 inout t28 ha[5]# agtl+ 1.5 15 inout r27 ha[6]# agtl+ 1.5 16 inout r23 hreq[2]# agtl+ 1.5 17 inout r24 ha[9]# agtl+ 1.5 18 inout t27 ha[13]# agtl+ 1.5 19 inout u28 ha[10]# agtl+ 1.5 20 inout p23 ha[3]# agtl+ 1.5 21 inout t25 ha[4]# agtl+ 1.5 22 inout r25 hreq[3]# agtl+ 1.5 23 inout v27 ha[14]# agtl+ 1.5 24 inout u27 ha[12]# agtl+ 1.5 25 inout v28 ha[11]# agtl+ 1.5 26 inout t23 hreq[4]# agtl+ 1.5 27 inout u24 ha[8]# agtl+ 1.5 28 inout u23 ha[7]# agtl+ 1.5 29 inout v26 ha[16]# agtl+ 1.5 30 inout u25 ha[15]# agtl+ 1.5 31 inout v25 ha[18]# agtl+ 1.5 32 inout y26 ha[30]# agtl+ 1.5 33 inout w28 ha[28]# agtl+ 1.5 34 inout w25 ha[20]# agtl+ 1.5
video filter capacitors and ferrite bead arranged in a pi configuration (one pi filter testability) r 194 datasheet 35 inout v23 ha[19]# agtl+ 1.5 36 inout w27 ha[25]# agtl+ 1.5 37 inout y25 ha[21] agtl+ 1.5 38 inout w24 ha[23]# agtl+ 1.5 39 inout y27 ha[26]# agtl+ 1.5 40 inout y24 ha[17]# agtl+ 1.5 41 inout aa27 ha[22]# agtl+ 1.5 42 inout w23 ha[24]# agtl+ 1.5 43 inout ab28 ha[31]# agtl+ 1.5 44 inout ab27 ha[29]# agtl+ 1.5 45 inout aa28 ha[27] agtl+ 1.5 xor chain gpio in/out ball pin i/o type voltage xor out out ad7 sma[7] sstl_2 2.5 1 out g8 panelbkltctl cmos 3.3 2 out f8 panelbklten cmos 3.3 3 out c6 lclkctlb cmos 3.3 4 in d6 extts_0 cmos 3.3 5 out f7 agpbusy# cmos 3.3 6 in d7 rsvd n/a n/a 7 inout c5 ddcpdata cmos 3.3 8 inout b4 ddcpclk cmos 3.3 9 out h10 hsync cmos 3.3 10 out a5 panelvdden cmos 3.3 11 inout b6 ddcaclk cmos 3.3 12 out j9 vsync cmos 3.3 13 inout g9 ddcadata cmos 3.3 14 out h9 lclkctla cmos 3.3 xor chain hub in/out ball pin i/o type voltage xor out out ad8 sma[6] sstl_2 2.5 1 inout w2 hl[4] hl1.5 1.2 2 inout w6 hl[5] hl1.5 1.2 3 inout w7 hl[7] hl1.5 1.2 4 inout v6 hl[6] hl1.5 1.2 5 inout w3 hlstb hl1.5 1.2 6 inout v2 hlstb# hl1.5 1.2
video filter capacitors and ferrite bead arranged in a pi configuration (one pi filter testability) r datasheet 195 7 in v5 hl[9] hl1.5 1.2 8 inout v4 hl[10] hl1.5 1.2 9 inout v3 hl[3] hl1.5 1.2 10 inout u4 hl[1] hl1.5 1.2 11 inout u3 hl[2] hl1.5 1.2 12 inout u7 hl[0] hl1.5 1.2 13 out t3 hl[8] hl1.5 1.2 xor chain lvds in/out ball pin i/o type voltage xor out out ad17 sma[3] sstl_2 2.5 1 inout f10 iclkbp lvds 1.5 2 inout e10 iclkbm lvds 1.5 3 inout g10 iybp[3] lvds 1.5 4 inout g11 iybm[3] lvds 1.5 5 inout g12 iybp[0] lvds 1.5 6 inout h12 iybm[0] lvds 1.5 7 inout e11 iybp[1] lvds 1.5 8 inout e12 iybm[1] lvds 1.5 9 inout c11 iybp[2] lvds 1.5 10 inout c12 iybm[2] lvds 1.5 11 inout e13 iclkap lvds 1.5 12 inout d14 iclkam lvds 1.5 13 inout b13 iyap[3] lvds 1.5 14 inout c13 iyam[3] lvds 1.5 15 inout f14 iyap[0] lvds 1.5 16 inout g14 iyam[0] lvds 1.5 17 inout c14 iyap[2] lvds 1.5 18 inout c15 iyam[2] lvds 1.5 19 inout e14 iyap[1] lvds 1.5 20 inout e15 iyam[1] lvds 1.5 xor chain sm1 ddr sdram in/out ball pin i/o type voltage xor out out ad23 scs[0]# sstl_2 2.5 1 inout ae27 sdq[62] sstl_2 2.5 2 inout ad27 sdq[63] sstl_2 2.5 3 inout af26 sdq[61] sstl_2 2.5
video filter capacitors and ferrite bead arranged in a pi configuration (one pi filter testability) r 196 datasheet 4 inout ag26 sdq[60] sstl_2 2.5 5 out ac25 scs[3]# sstl_2 2.5 6 out ad24 sdm[6] sstl_2 2.5 7 inout ah24 sdqs[6] sstl_2 2.5 8 out ad25 swe# sstl_2 2.5 9 out ac18 sma[0] sstl_2 2.5 10 inout ah17 sdqs[4] sstl_2 2.5 11 out ad19 sdm[4] sstl_2 2.5 12 clk ac26 sck[1] sstl_2 2.5 13 clk ab23 sck[4] sstl_2 2.5 14 clk aa3 sck[5] sstl_2 2.5 15 clk ac2 sck[3] sstl_2 2.5 16 clk ab2 sck[0] sstl_2 2.5 17 clk ac3 sck[2] sstl_2 2.5 18 out ah15 sdm[8] sstl_2 2.5 19 inout af17 rsvd n/a n/a 20 inout af16 rsvd n/a n/a 21 inout ag16 rsvd n/a n/a 22 inout ae15 rsvd n/a n/a 23 inout ah14 rsvd n/a n/a 24 inout ae17 rsvd n/a n/a 25 inout ad15 sdqs[8] sstl_2 2.5 26 inout ae14 rsvd n/a n/a 27 inut ag14 rsvd n/a n/a 28 inout ah8 sdqs[2] sstl_2 2.5 29 out ae9 sdm[2] sstl_2 2.5 30 out ac7 scke[0] sstl_2 2.5 31 inout ag2 sdqs[0] sstl_2 2.5 32 out ae5 sdm[0] sstl_2 2.5 xor chain sm2 ddr sdram in/out ball pin i/o type voltage xor out out ad26 scs[1]# sstl_2 2.5 1 inout af28 sdq[59] sstl_2 2.5 2 inout ag28 sdq[58] sstl_2 2.5 3 inout ah27 sdqs[7] sstl_2 2.5 4 out ah28 sdm[7] sstl_2 2.5
video filter capacitors and ferrite bead arranged in a pi configuration (one pi filter testability) r datasheet 197 5 inout ae26 sdq[57] sstl_2 2.5 6 inout ah26 sdq[56] sstl_2 2.5 7 inout ah25 sdq[51] sstl_2 2.5 8 inout ag25 sdq[55] sstl_2 2.5 9 inout af25 sdq[54] sstl_2 2.5 10 inout ae24 sdq[50] sstl_2 2.5 11 inout ah23 sdq[49] sstl_2 2.5 12 inout af23 sdq[53] sstl_2 2.5 13 inout ae23 sdq[48] sstl_2 2.5 14 inout ag23 sdq[52] sstl_2 2.5 15 inout ae21 sdqs[5] sstl_2 2.5 16 out ad21 sdm[5] sstl_2 2.5 17 out ad20 sba[1] sstl_2 2.5 18 out ad22 sba[0] sstl_2 2.5 19 out ac21 sras# sstl_2 2.5 20 out ac15 rcvenout# sstl_2 2.5 21 inout ac16 rcvenin# sstl_2 2.5 22 clk ab24 sck[4]# sstl_2 2.5 23 clk ab25 sck[1]# sstl_2 2.5 24 clk ab4 sck[5]# sstl_2 2.5 25 clk aa2 sck[0]# sstl_2 2.5 26 clk ad2 sck[3]# sstl_2 2.5 27 clk ad4 sck[2]# sstl_2 2.5 28 out ad10 smab[5] sstl_2 2.5 29 out ad14 sma[1] sstl_2 2.5 30 out ad16 smab[1] sstl_2 2.5 31 out ad13 sma[2] sstl_2 2.5 32 out af11 smab[4] sstl_2 2.5 33 out ac12 smab[2] sstl_2 2.5 34 out ac13 sma[5] sstl_2 2.5 35 inout ae12 sdqs[3] sstl_2 2.5 36 out ah12 sdm[3] sstl_2 2.5 37 out ad11 sma[4] sstl_2 2.5 38 out ac10 scke[3] sstl_2 2.5 39 out ae6 sdm[1] sstl_2 2.5 40 inout ah5 sdqs[1] sstl_2 2.5 41 out ac9 scke[2] sstl_2 2.5
video filter capacitors and ferrite bead arranged in a pi configuration (one pi filter testability) r 198 datasheet 42 out ab7 scke[1] sstl_2 2.5 xor chain sm 3 ddr sdram in/out ball pin i/o type voltage xor out out ac22 scs[2]# sstl_2 2.5 1 out ac24 scas# sstl_2 2.5 2 inout ag22 sdq[47] sstl_2 2.5 3 inout ah22 sdq[43] sstl_2 2.5 4 inout af22 sdq[42] sstl_2 2.5 5 inout ag20 sdq[41] sstl_2 2.5 6 inout af20 sdq[44] sstl_2 2.5 7 inout ah21 sdq[46] sstl_2 2.5 8 inout ah19 sdq[45] sstl_2 2.5 9 inout ah20 sdq[40] sstl_2 2.5 10 inout ah16 sdq[32] sstl_2 2.5 11 inout ad18 sdq[36] sstl_2 2.5 12 inout ag19 sdq[39] sstl_2 2.5 13 inout ah18 sdq[38] sstl_2 2.5 14 inout af19 sdq[34] sstl_2 2.5 15 inout ae18 sdq[37] sstl_2 2.5 16 inout ag17 sdq[33] sstl_2 2.5 17 inout ae20 sdq[35] sstl_2 2.5 18 inout ag13 sdq[26] sstl_2 2.5 19 inout af14 sdq[27] sstl_2 2.5 20 inout af13 sdq[30] sstl_2 2.5 21 inout ah13 sdq[31] sstl_2 2.5 22 inout ad12 sdq[29] sstl_2 2.5 23 inout ah10 sdq[24] sstl_2 2.5 24 inout ah11 sdq[25] sstl_2 2.5 25 inout ag11 sdq[28] sstl_2 2.5 26 inout af10 sdq[22] sstl_2 2.5 27 inout ae11 sdq[23] sstl_2 2.5 28 inout ag10 sdq[19] sstl_2 2.5 29 inout af8 sdq[16] sstl_2 2.5 30 inout ah9 sdq[18] sstl_2 2.5 31 inout ad9 sdq[21] sstl_2 2.5 32 inout ah7 sdq[20] sstl_2 2.5 33 inout ag8 sdq[17] sstl_2 2.5
video filter capacitors and ferrite bead arranged in a pi configuration (one pi filter testability) r datasheet 199 34 inout af7 sdq[14] sstl_2 2.5 35 inout ag7 sdq[10] sstl_2 2.5 36 inout ae8 sdq[11] sstl_2 2.5 37 inout ah6 sdq[15] sstl_2 2.5 38 inout af5 sdq[12] sstl_2 2.5 39 inout ad6 sdq[8] sstl_2 2.5 40 inout ah4 sdq[13] sstl_2 2.5 41 inout ag5 sdq[9] sstl_2 2.5 42 inout ah2 sdq[3] sstl_2 2.5 43 inout af4 sdq[2] sstl_2 2.5 44 inout ag4 sdq[6] sstl_2 2.5 45 inout ah3 sdq[7] sstl_2 2.5 46 inout af2 sdq[0] sstl_2 2.5 47 inout ad3 sdq[4] sstl_2 2.5 48 inout ae3 sdq[1] sstl_2 2.5 49 inout ae2 sdq[5] sstl_2 2.5
video filter capacitors and ferrite bead arranged in a pi configuration (one pi filter testability) r 200 datasheet 9.4.1 vcc/vss voltage groups table 53. voltage levels and ball out for voltage groups name voltage level ballout vcc 1.2 (855gm) 1.35 (855gme) h14,j15,n14,n16,p13,p15,p17,r14,r16,t13,t15, t17,u14,u16,w21,aa15,aa17,aa19 vccadac 1.5 a9,b9 vccdvo 1.5 e1,e4,e6,h7,j1,j4,j8,k9,l8,m4,m8,m9,n1,n8,p9,r8 vccasm 1.2 (855gm) 1.35 (855gme) ad1,af1 vccdlvds 1.5 b14,b15,g13,j13 vccgpio 3.3 a3,a4 vcchl 1.2 (855gm) 1.35 (855gme) u6,u8,v1,v7,v9,w5,w8,y1 vccqsm 2.5 aj6,aj8 vccsm 2.5 y4,y7,y9,aa6,aa8, aa11,aa13,ab3,ab6,ab8,ab10, ab12,ab14,ab16,ab18,ab20,ab22,ac1,ac29,af3, af6,af9,af12,af15,af18, af21,af24,af27,af29, ag1,ag29,aj5,aj9,aj13,aj17,aj21,aj25 vcctxlvds 2.5 a12,b10,d10,f9 vtthf 1.5 a22,a24,h29,m29,v29 vttlf 1.5 a18,a20,a26,f29,g15,h16,h18,h20,h22,j19,k29,l21, m22,n21,p22,r21,t22,u21,v22,y29,ab29 vss gnd a13,a17,a19,a21,a23,a25,a27,b5,b24,c1,c7,c10,c22,c29, d4,d11,d13,d15,d17,d19,d21,d23,d25,d28,e7,e9,e28,e29, f11,f13,f16,f18,f20,f22,f24,f27,g1,g4,g7,g26,g29,h8,h11, h13,h15,h17,h19,h21,h24,j7,j10,j12,j 14,j16,j18,j20,j22,j26, j29,k4,k8,k24,l1,l6,l9,l22,l26,l29,m7,m21,m24,n4,n9,n13, n15,n17,n22,n26,n29,p8,p14,p16,p21,p24,r2,r7,r9,r13,r15, r17,r22,r26,t4,t8,t9,t14,t16,t21,t24,u1,u5,u9,u13,u15, u17,u22,u26,u29,v8,v21,v24,w4,w 9,w22,w26,w29,y5,y6, y8,y21,aa1,aa4,aa7,aa10,aa12,aa14,aa16,aa18,aa20, aa21,aa23,aa24,aa25,aa29,ab9,ab11,ab13,ab15,ab17, ab19,ab21,ab26,ac4,ac8,ac11,ac14,ac17,ac20,ac23, ac27,ac28,ae1,ae4,ae7,ae10,ae13,ae16,ae19,ae22,ae25, ae28,ag3,ag6,ag9,ag12,ag15, ag18,ag21,ag24,ag27,aj1, aj3,aj7,aj10,aj11,aj12, aj18,aj20,aj23,aj26,aj27
intel? 855gm/gme gmch strap pins r datasheet 201 10 intel ? 855gm/gme gmch strap pins 10.1 strapping configuration table 54. strapping signals and configuration pin name strap description configuration i/f type buffer type hsync xor chain test low = normal ops (default) high = xor test on gpio out vsync all z test low = normal ops (default) high = allz test on gpio out lclkctlb vtt voltage select high = 1.05 v ? intel pentium m processor / intel celeron m processor gpio out dvodetect dvo select (if dvodetect=0 during reset, addid[7:0] is latched to the addid register) (1) low = dvo (default) high = reserved dvo bi gst[2] clock config: bit_2 (1) gst[1] clock config: bit_1 (1) gst[0] clock config: bit_0 (1) please refer to device #0 function #3 (hpllcc register) for proper gst[2:0] settings dvo out: 0) before cpurst#, there is internal pull-down 1) just out of cpurst#: these pins are hi-z 2) c3: these pins are hi-z 3) s1-m: these pins are hi-z 4) internal gfx d1/d3: these pins are hi-z 5) s3: these pins are power down 6) s4/s5: these pins are power down notes: 1. external pull-ups/downs will be required on the board to enable the non-default state of the straps. note: all strap signals are sampled with respect to the leading edge of the intel 855gm/gme gmch pwrok in signal.
intel? 855gm/gme gmch strap pins r 202 datasheet
ballout and package information r datasheet 203 11 ballout and package information figure 13. intel ? 855gm/855gme gmch ballout diagram (top view) 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 aj nc nc vss vss vccsm smvref _0 vss smvswi ngl vccsm vss smvswi ngh vss vccsm vccsm vss vss vss vccsm vccqs m vss vccqs m vccsm nc vss nc vss aj ah nc sdm[7] sdqs[7] sdq[56] sdq[51] sdqs[6] sdq[49] sdq[43] sdq[46] sdq[40] sdq[45] sdq[38] sdqs[4] sdq[32] sdm[8] sdq[68] sdq[31] sdm[3] sdq[25] sdq[24] sdq[18] sdqs[2] sdq[20] sdq[15] sdqs[1] sdq[13] sdq[7] sdq[3] nc ah ag vccsm sdq[58] vss sdq[60] sdq[55] vss sdq[52] sdq[47] vss sdq[41] sdq[39] vss sdq[33] sdq[67] vss sdq[64] sdq[26] vss sdq[28] sdq[19] vss sdq[17] s dq[10] vss sdq[9] sdq[6] vss sdqs[0] vccsm ag af vccsm sdq[59] vccsm sdq[61] sdq[54] vccsm sdq[53] sdq[42] vccsm sdq[44] sdq[34] vccsm sdq[71] sdq[70] vccsm sdq[27] sdq[30] vccsm smab[4] sdq[22 ] vccsm sdq[16] sdq[14] vccsm sdq[12] sdq[2] vccsm sdq[0] vccas m af ae bclk vss sdq[62] sdq[57] vss sdq[50] sdq[48] vss sdqs[5] sdq[35] vss sdq[37] sdq[66] vss sdq[69] sdq[65] vss sdqs[3] sdq[23] vss sdm[2] sdq[11] vss sdm[1] sdm[0] vss sdq[1] sdq[5] vss ae ad bclk# rstin# sdq[63] scs[1]# sw e# sdm[6] scs[0]# sba[0] sdm[5] sba[1] sdm[4] sdq[36] sma[3] smab[1] sdqs[8] sma[1] sma[2] sdq[29] sma[4] smab[5] sdq[21] sma[6] sma[7] sdq[8] sma[11] sck[2]# sdq[4] sck[3]# vccas m ad ac vccsm vss vss sck[1] scs[3]# scas# vss scs[2]# sras# vss sma[10] sma[0] vss rcveni n# rcven out# vss sma[5] smab[2] vss scke[3] scke[2] vss scke[0] sma[8] sma[9] vss sck[2] sck[3] vccsm ac ab vttlf ha[31]# ha[29]# vss sck[1]# sck[4]# sck[4] vccsm vss vccsm vss vccsm vss vccsm vss vccsm vss vccsm vss vccsm vss vccsm scke[1] vccsm sma[12] sck [5]# vccsm sck[0] smrco mp ab aa vss ha[27]# ha[22]# hadstb [1]# vss vss vss dpwr# vss vss vcc vss vcc vss vcc vss vccsm vss vccsm vss nc vccsm vss vccsm rsvd vss sck[5] sck[0]# vss aa yvttlf hccvr e f ha[26]# ha[30]# ha[21]# ha[17]# dpslp# havref vss vccsm vss vccsm vss vss vccsm gclkin vccag p ll vcchl y w vss ha[28]# ha[25]# vss ha[20]# ha[23]# ha[24]# vss vcc vss vcchl hl[7] hl[5] vcchl vss hlstb hl[4] hlvref w v vtthf ha[11]# ha[14]# ha[16]# ha[18]# vss ha[19]# vttlf vss vcchl vss vcchl hl[6] hl[9] hl[10] hl[3] hlstb# vcchl v u vss ha[10]# ha[12]# vss ha[15]# ha[8]# ha[7]# vss vttlf vss vcc vss vcc vss vss vcchl hl[0] vcchl vss hl[1] hl[2] pswing vss u t ha[5]# ha[13]# hadstb [0]# ha[4]# vss hreq[4] # vttlf vss vcc vss vcc vss vcc vss vss mddcd ata dvobh s ync dvobvs ync vss hl[8] hlrco mp t r hreq[0] # ha[6]# vss hreq[3] # ha[9]# hreq[2] # vss vttlf vss vcc vss vcc vss vss vccdv o vss dvobd[ 2] dvobd[ 1] dvobd[ 3] dvobd[ 0] vss r p bpri# hlock# rs[1]# hreq[1] # vss ha[3]# vttlf vss vcc vss vcc vss vcc vccdv o vss mddcc lk dvobd[ 4] dvobd[ 5] dvobcl k# dvobcl k dvobd[ 7] p n vss hitm# hit# vss bnr# drdy# rs[0]# vss vttlf vss vcc vss vcc vss vss vccdv o mdvicl k mi2cda ta dvobd[ 6] vss dvobd[ 9] dvobd[ 8] vccdv o n m vtthf defer# rs[2]# dbsy# htrdy# vss breq0# vttlf vss vccdv o vccdv o vss mdvida ta dvobd[ 11] vccdv o dvobc clkint dvobfl dstl dvobd[ 10] m l vss ads# hd[6]# vss hd[8]# hd[3]# hd[7]# vss vttlf vss vccdv o dvodet ect vss dvocv s ync rsvd dvocbl ank# dvobbl ank# vss l kvttlf hyswin g hdstbp [0]# hd[13]# hd[2]# vss hd[11]# hd[0]# hdvref [0] vccdv o vss mi2ccl k dvoch sync dvocd[ 0] vss dvocd[ 2] dvocd[ 3] dvocd[ 1] k j vss hdstbn [0]# hd[4]# vss dinv[0]# hd[9]# hd[14]# vss hdvref [1] vss vttlf vss hdvref [2] vss vcc vss vccdlv ds vss pwrok vss vsync vccdv o vss dvocd[ 4] dvocd[ 5] vccdv o dvocc l k dvocc l k# vccdv o j h vtthf hyrco mp hd[1]# hd[15]# hd[10]# vss hd[19]# vttlf vss vttlf vss vttlf vss vttlf vss vcc vss iybm[0] vss hsync lclkct la vss vccdv o dvocd[ 10] dvocfl dstl dvocd[ 9] dvocd[ 8] dvocd[ 6] dvocd[ 7] h g vss hd[5]# hd[12]# vss hd[21]# hd[24]# hd[30]# hd[27]# hd[33] # hd[40]# dinv[3]# hd[48]# hd[51]# hd[58]# vttlf iyam[0] vccdlv ds iybp[0] iybm[3] iybp[3] ddcad a ta panelb kltctl vss addid[6] addid[4] vss dvocd[ 11] dvobci ntr# vss g f vttlf hd[22]# vss hd[17]# hd[16]# vss hd[44]# vss hd[45]# vss hd[53]# vss hd[56]# vss cpurst # iyap[0] vss rsvd vss iclkbp vcctxl vds panelb klten agpbus y# addid[7] addid[1] addid[5] rsvd rsvd gvref f e vss vss hd[20]# hd[29]# dinv[1]# hd[38]# hd[41]# hdstbn [2]# hdstbp [2]# hd[50]# hd[49]# hdstbp [3]# hd[61]# hd[59]# iyam[1] iyap[1] iclkap iybm[1] iybp[1] iclkbm vss refset vss vccdv o addid[0] vccdv o addid[2] addid[3] vccdv o e d vccahp ll vss hd[23]# hdstbp [1]# vss hd[39]# vss hd[36]# vss hd[52]# vss hdstbn [3]# vss hd[62]# vss iclkam vss rsvd vss vcctxl vds blue# green# rsvd extts_ 0 dpms vss rsvd rsvd dvorc omp d c vss hd[25]# hdstbn [1]# hd[28]# hd[37]# hd[34]# hd[35]# vss hd[47]# hd[46]# hd[54]# hd[63]# hd[55] # hd[60]# iyam[2] iyap[2] iyam[3] iybm[2] iybp[2] vss blue green vss lclkct lb ddcpd a ta gst[0] gst[1] gst[2] vss c b nc hd[31]# hd[18]# hd[26]# dinv[2]# vss hd[43]# hd[42]# hd[32]# hxrco mp hd[57]# hxswin g drefss clk vccadp llb vccdlv ds vccdlv ds iyap[3] rsvd vssalv ds vcctxl vds vccad a c vssada c drefcl k ddcacl k vss ddcpcl k rsvd rsvd nc b a nc nc vss vttlf vss vtthf vss vtthf vss vttlf vss vttlf vss vss vcctxl vds vccalv ds libg vccad a c red# red vccadp lla panelv dden vccgpi o vccgpi o nc a 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
ballout and package information r datasheet 204 table 55. ballout table row column signal name e 5 gsba0/addid[0] f 5 gsba1/addid[1] e 3 gsba2/addid[2] e 2 gsba3/addid[3] g 5 gsba4/addid[4] f 4 gsba5/addid[5] g 6 gsba6/addid[6] f 6 gsba7/addid[7] l 28 ads# f 7 agpbusy# ae 29 bclk ad 29 bclk# c 9 blue d 9 blue# n 25 bnr# p 28 bpri# m 23 breq0# f 15 cpurst# m 26 dbsy# b 6 ddcaclk g 9 ddcadata b 4 ddcpclk c 5 ddcpdata m 28 defer# j 25 dinv[0]# e 25 dinv[1]# b 25 dinv[2]# g 19 dinv[3]# d 5 gpipe#/dpms y 23 dpslp# aa 22 dpwr# n 24 drdy# b 7 drefclk b 17 drefssclk row column signal name l 2 gcbe#/dvobblank# m 3 gad13/dvobcclkint g 2 gad30/dvobcintr# p 3 gadstb0/dvobclk p 4 gadstb#0/dvobclk# r 3 gad3/dvobd[0] r 5 gad2/dvobd[1] m 1 gad12/dvobd[10] m 5 gad11/dvobd[11] r 6 gad5/dvobd[2] r 4 gad4/dvobd[3] p 6 gad7/dvobd[4] p 5 gad6/dvobd[5] n 5 gad8/dvobd[6] p 2 gcbe#0/dvobd[7] n 2 gad10/dvobd[8] n 3 gad9/dvobd[9] m 2 gad14/dvobfldstl t 6 gad0/dvobhsync t 5 gad1/dvobvsync l 3 gad18/dvocblank# j 3 gadstb1/dvocclk j 2 gadstb#1/dvocclk# k 5 gad19/dvocd[0] k 1 gad20/dvocd[1] h 6 gad29/dvocd[10] g 3 gad28/dvocd[11] k 3 gad21/dvocd[2] k 2 gad22/dvocd[3] j 6 gad23/dvocd[4] j 5 gcbe#3/dvocd[5] h 2 gad25/dvocd[6] h 1 gad24/dvocd[7] h 3 gad27/dvocd[8] row column signal name h 4 gad26/dvocd[9] h 5 gad31/dvocfldstl k 6 gad17/dvochsync l 5 gad16/dvocvsync l 7 gpar/dvodetect d 1 dvorcomp d 6 extts_0 y 3 gclkin c 8 green d 8 green# f 1 gvref u 28 ha[10]# v 28 ha[11]# u 27 ha[12]# t 27 ha[13]# v 27 ha[14]# u 25 ha[15]# v 26 ha[16]# y 24 ha[17]# v 25 ha[18]# v 23 ha[19]# w 25 ha[20]# y 25 ha[21]# aa 27 ha[22]# w 24 ha[23]# w 23 ha[24]# w 27 ha[25]# y 27 ha[26]# aa 28 ha[27]# w 28 ha[28]# ab 27 ha[29]# p 23 ha[3]# y 26 ha[30]# ab 28 ha[31]#
ballout and package information r datasheet 205 row column signal name t 25 ha[4]# t 28 ha[5]# r 27 ha[6]# u 23 ha[7]# u 24 ha[8]# r 24 ha[9]# t 26 hadstb[0]# aa 26 hadstb[1]# y 22 havref y 28 hccvref k 22 hd[0]# h 27 hd[1]# h 25 hd[10]# k 23 hd[11]# g 27 hd[12]# k 26 hd[13]# j 23 hd[14]# h 26 hd[15]# f 25 hd[16]# f 26 hd[17]# b 27 hd[18]# h 23 hd[19]# k 25 hd[2]# e 27 hd[20]# g 25 hd[21]# f 28 hd[22]# d 27 hd[23]# g 24 hd[24]# c 28 hd[25]# b 26 hd[26]# g 22 hd[27]# c 26 hd[28]# e 26 hd[29]# l 24 hd[3]# g 23 hd[30]# b 28 hd[31]# row column signal name b 21 hd[32]# g 21 hd[33]# c 24 hd[34]# c 23 hd[35]# d 22 hd[36]# c 25 hd[37]# e 24 hd[38]# d 24 hd[39]# j 27 hd[4]# g 20 hd[40]# e 23 hd[41]# b 22 hd[42]# b 23 hd[43]# f 23 hd[44]# f 21 hd[45]# c 20 hd[46]# c 21 hd[47]# g 18 hd[48]# e 19 hd[49]# g 28 hd[5]# e 20 hd[50]# g 17 hd[51]# d 20 hd[52]# f 19 hd[53]# c 19 hd[54]# c 17 hd[55]# f 17 hd[56]# b 19 hd[57]# g 16 hd[58]# e 16 hd[59]# l 27 hd[6]# c 16 hd[60]# e 17 hd[61]# d 16 hd[62]# c 18 hd[63]# l 23 hd[7]# row column signal name l 25 hd[8]# j 24 hd[9]# j 28 hdstbn[0]# c 27 hdstbn[1]# e 22 hdstbn[2]# d 18 hdstbn[3]# k 27 hdstbp[0]# d 26 hdstbp[1]# e 21 hdstbp[2]# e 18 hdstbp[3]# k 21 hdvref[0] j 21 hdvref[1] j 17 hdvref[2] n 27 hit# n 28 hitm# u 7 hl[0] u 4 hl[1] v 4 hl[10] u 3 hl[2] v 3 hl[3] w 2 hl[4] w 6 hl[5] v 6 hl[6] w 7 hl[7] t 3 hl[8] v 5 hl[9] p 27 hlock# t 2 hlrcomp w 3 hlstb v 2 hlstb# w 1 hlvref r 28 hreq[0]# p 25 hreq[1]# r 23 hreq[2]# r 25 hreq[3]# t 23 hreq[4]#
ballout and package information r 206 datasheet row column signal name h 10 hsync m 25 htrdy# b 20 hxrcomp b 18 hxswing h 28 hyrcomp k 28 hyswing d 14 iclkam e 13 iclkap e 10 iclkbm f 10 iclkbp g 14 iyam[0] e 15 iyam[1] c 15 iyam[2] c 13 iyam[3] f 14 iyap[0] e 14 iyap[1] c 14 iyap[2] b 13 iyap[3] h 12 iybm[0] e 12 iybm[1] c 12 iybm[2] g 11 iybm[3] g 12 iybp[0] e 11 iybp[1] c 11 iybp[2] g 10 iybp[3] h 9 lclkctla c 6 lclkctlb a 10 libg p 7 gstop#/mddcclk t 7 gad15/mddcdata n 7 gtrdy#/mdviclk m 6 gframe#/mdvidata k 7 girdy#/mi2cclk n 6 gdevsel#/mi2cdata aj 29 nc row column signal name ah 29 nc b 29 nc a 29 nc aj 28 nc a 28 nc aa 9 nc aj 4 nc aj 2 nc a 2 nc ah 1 nc b 1 nc g 8 panelbkltctl f 8 panelbklten a 5 panelvdden u 2 pswing j 11 pwrok ac 16 rcvenin# ac 15 rcvenout# a 7 red a 8 red# e 8 refset n 23 rs[0]# p 26 rs[1]# m 27 rs[2]# ad 28 rstin# f 12 rsvd d 12 rsvd b 12 rsvd aa 5 rsvd l 4 rsvd c 4 gst[0] f 3 rsvd d 3 rsvd c 3 gst[1] b 3 rsvd f 2 rsvd row column signal name d 2 rsvd c 2 gst[2] b 2 rsvd d 7 rsvd ad 22 sba[0] ad 20 sba[1] ac 24 scas# ab 2 sck[0] aa 2 sck[0]# ac 26 sck[1] ab 25 sck[1]# ac 3 sck[2] ad 4 sck[2]# ac 2 sck[3] ad 2 sck[3]# ab 23 sck[4] ab 24 sck[4]# aa 3 sck[5] ab 4 sck[5]# ac 7 scke[0] ab 7 scke[1] ac 9 scke[2] ac 10 scke[3] ad 23 scs[0]# ad 26 scs[1]# ac 22 scs[2]# ac 25 scs[3]# ae 5 sdm[0] ae 6 sdm[1] ae 9 sdm[2] ah 12 sdm[3] ad 19 sdm[4] ad 21 sdm[5] ad 24 sdm[6] ah 28 sdm[7] ah 15 sdm[8]
ballout and package information r datasheet 207 row column signal name af 2 sdq[0] ae 3 sdq[1] ag 7 sdq[10] ae 8 sdq[11] af 5 sdq[12] ah 4 sdq[13] af 7 sdq[14] ah 6 sdq[15] af 8 sdq[16] ag 8 sdq[17] ah 9 sdq[18] ag 10 sdq[19] af 4 sdq[2] ah 7 sdq[20] ad 9 sdq[21] af 10 sdq[22] ae 11 sdq[23] ah 10 sdq[24] ah 11 sdq[25] ag 13 sdq[26] af 14 sdq[27] ag 11 sdq[28] ad 12 sdq[29] ah 2 sdq[3] af 13 sdq[30] ah 13 sdq[31] ah 16 sdq[32] ag 17 sdq[33] af 19 sdq[34] ae 20 sdq[35] ad 18 sdq[36] ae 18 sdq[37] ah 18 sdq[38] ag 19 sdq[39] ad 3 sdq[4] ah 20 sdq[40] row column signal name ag 20 sdq[41] af 22 sdq[42] ah 22 sdq[43] af 20 sdq[44] ah 19 sdq[45] ah 21 sdq[46] ag 22 sdq[47] ae 23 sdq[48] ah 23 sdq[49] ae 2 sdq[5] ae 24 sdq[50] ah 25 sdq[51] ag 23 sdq[52] af 23 sdq[53] af 25 sdq[54] ag 25 sdq[55] ah 26 sdq[56] ae 26 sdq[57] ag 28 sdq[58] af 28 sdq[59] ag 4 sdq[6] ag 26 sdq[60] af 26 sdq[61] ae 27 sdq[62] ad 27 sdq[63] ag 14 sdq[64] ae 14 sdq[65] ae 17 sdq[66] ag 16 sdq[67] ah 14 sdq[68] ae 15 sdq[69] ah 3 sdq[7] af 16 sdq[70] af 17 sdq[71] ad 6 sdq[8] ag 5 sdq[9] row column signal name ag 2 sdqs[0] ah 5 sdqs[1] ah 8 sdqs[2] ae 12 sdqs[3] ah 17 sdqs[4] ae 21 sdqs[5] ah 24 sdqs[6] ah 27 sdqs[7] ad 15 sdqs[8] ac 18 sma[0] ad 14 sma[1] ac 19 sma[10] ad 5 sma[11] ab 5 sma[12] ad 13 sma[2] ad 17 sma[3] ad 11 sma[4] ac 13 sma[5] ad 8 sma[6] ad 7 sma[7] ac 6 sma[8] ac 5 sma[9] ad 16 smab[1] ac 12 smab[2] af 11 smab[4] ad 10 smab[5] ab 1 smrcomp aj 24 smvref_0 aj 19 smvswingh aj 22 smvswingl ac 21 sras# ad 25 swe# w 21 vcc aa 19 vcc aa 17 vcc t 17 vcc
ballout and package information r 208 datasheet row column signal name p 17 vcc u 16 vcc r 16 vcc n 16 vcc aa 15 vcc t 15 vcc p 15 vcc j 15 vcc u 14 vcc r 14 vcc n 14 vcc h 14 vcc t 13 vcc p 13 vcc b 9 vccadac a 9 vccadac a 6 vccadplla b 16 vccadpllb y 2 vccagpll d 29 vccahpll a 11 vccalvds af 1 vccasm ad 1 vccasm b 15 vccdlvds b 14 vccdlvds j 13 vccdlvds g 13 vccdlvds p 9 vccdvo m 9 vccdvo k 9 vccdvo r 8 vccdvo n 8 vccdvo m 8 vccdvo l 8 vccdvo j 8 vccdvo h 7 vccdvo row column signal name e 6 vccdvo m 4 vccdvo j 4 vccdvo e 4 vccdvo n 1 vccdvo j 1 vccdvo e 1 vccdvo a 4 vccgpio a 3 vccgpio v 9 vcchl w 8 vcchl u 8 vcchl v 7 vcchl u 6 vcchl w 5 vcchl y 1 vcchl v 1 vcchl aj 8 vccqsm aj 6 vccqsm ag 29 vccsm af 29 vccsm ac 29 vccsm af 27 vccsm aj 25 vccsm af 24 vccsm ab 22 vccsm aj 21 vccsm af 21 vccsm ab 20 vccsm af 18 vccsm ab 18 vccsm aj 17 vccsm ab 16 vccsm af 15 vccsm ab 14 vccsm aj 13 vccsm row column signal name aa 13 vccsm af 12 vccsm ab 12 vccsm aa 11 vccsm ab 10 vccsm aj 9 vccsm af 9 vccsm y 9 vccsm ab 8 vccsm aa 8 vccsm y 7 vccsm af 6 vccsm ab 6 vccsm aa 6 vccsm aj 5 vccsm y 4 vccsm af 3 vccsm ab 3 vccsm ag 1 vccsm ac 1 vccsm a 12 vcctxlvds d 10 vcctxlvds b 10 vcctxlvds f 9 vcctxlvds aa 29 vss w 29 vss u 29 vss n 29 vss l 29 vss j 29 vss g 29 vss e 29 vss c 29 vss ae 28 vss ac 28 vss e 28 vss
ballout and package information r datasheet 209 row column signal name d 28 vss aj 27 vss ag 27 vss ac 27 vss f 27 vss a 27 vss aj 26 vss ab 26 vss w 26 vss u 26 vss r 26 vss n 26 vss l 26 vss j 26 vss g 26 vss ae 25 vss aa 25 vss d 25 vss a 25 vss ag 24 vss aa 24 vss v 24 vss t 24 vss p 24 vss m 24 vss k 24 vss h 24 vss f 24 vss b 24 vss aj 23 vss ac 23 vss aa 23 vss d 23 vss a 23 vss ae 22 vss w 22 vss row column signal name u 22 vss r 22 vss n 22 vss l 22 vss j 22 vss f 22 vss c 22 vss ag 21 vss ab 21 vss aa 21 vss y 21 vss v 21 vss t 21 vss p 21 vss m 21 vss h 21 vss d 21 vss a 21 vss aj 20 vss ac 20 vss aa 20 vss j 20 vss f 20 vss ae 19 vss ab 19 vss h 19 vss d 19 vss a 19 vss aj 18 vss ag 18 vss aa 18 vss j 18 vss f 18 vss ac 17 vss ab 17 vss u 17 vss row column signal name r 17 vss n 17 vss h 17 vss d 17 vss a 17 vss ae 16 vss aa 16 vss t 16 vss p 16 vss j 16 vss f 16 vss ag 15 vss ab 15 vss u 15 vss r 15 vss n 15 vss h 15 vss d 15 vss ac 14 vss aa 14 vss t 14 vss p 14 vss j 14 vss ae 13 vss ab 13 vss u 13 vss r 13 vss n 13 vss h 13 vss f 13 vss d 13 vss a 13 vss aj 12 vss ag 12 vss aa 12 vss j 12 vss
ballout and package information r 210 datasheet row column signal name aj 11 vss ac 11 vss ab 11 vss h 11 vss f 11 vss d 11 vss aj 10 vss ae 10 vss aa 10 vss j 10 vss c 10 vss ag 9 vss ab 9 vss w 9 vss u 9 vss t 9 vss r 9 vss n 9 vss l 9 vss e 9 vss ac 8 vss y 8 vss v 8 vss t 8 vss p 8 vss k 8 vss h 8 vss aj 7 vss ae 7 vss aa 7 vss r 7 vss row column signal name m 7 vss j 7 vss g 7 vss e 7 vss c 7 vss ag 6 vss y 6 vss l 6 vss y 5 vss u 5 vss b 5 vss ae 4 vss ac 4 vss aa 4 vss w 4 vss t 4 vss n 4 vss k 4 vss g 4 vss d 4 vss aj 3 vss ag 3 vss r 2 vss aj 1 vss ae 1 vss aa 1 vss u 1 vss l 1 vss g 1 vss c 1 vss b 8 vssadac row column signal name b 11 vssalvds j 9 vsync v 29 vtthf m 29 vtthf h 29 vtthf a 24 vtthf a 22 vtthf ab 29 vttlf y 29 vttlf k 29 vttlf f 29 vttlf a 26 vttlf v 22 vttlf t 22 vttlf p 22 vttlf m 22 vttlf h 22 vttlf u 21 vttlf r 21 vttlf n 21 vttlf l 21 vttlf h 20 vttlf a 20 vttlf j 19 vttlf h 18 vttlf a 18 vttlf h 16 vttlf g 15 vttlf
ballout and package information r datasheet 211 11.1 package mechanical information figure 14 through figure 16 provide detail on the package information and dimensions of the intel 855gm/855gme gmch. the intel 855gm/855gme gmch comes in a micro-fcbga package, which is similar to the mobile processors. the package consists of a silicon die mounted face down on an organic substrate populated with so lder balls on the botto m side. capacitors may be placed in the area surrounding the die. becau se the die-side capacitors are electrically conductive, and only slightly shorter than the die height, care should be taken to avoid contacting the capacitors with electrically conductive materials. doing so may short the capacitors and possibly damage the device or render it inactive. the use of an insulating material between the capacitors and any thermal solution should be considered to prevent capacitor shorting. an ex clusion, or keepout area, surrounds the die and capacitors, and identifies the contact area for the package. care should be taken to avoid contact with the package in side this area. figure 14. intel ? 855gm/855gme gmch micro-fcbga package dimensions (top view)
ballout and package information r 212 datasheet figure 15. intel ? 855gm/855gme gmch micro-fcbga p ackage dimensions (side view)
ballout and package information r datasheet 213 figure 16. intel ? 855gm/855gme gmch micro-fcbga p ackage dimensions (bottom view)

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