View TMP88FW45FG_6906981.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

8 bit microcontroller tlcs-870/x series TMP88FW45FG
the information contained herein is subject to change without notice. 021023_d toshiba is continually working to improve the qua lity and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utiliz ing toshiba products, to comply with the standards of safety in making a safe design for the entire sy stem, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most r ecent toshiba products specifications. also, please keep in mind the precauti ons and conditions set forth in the ? handling guide for semiconductor devices, ? or ? toshiba semiconductor reliability handbook ? etc. 021023_a the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, of fice equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ( ? unintended usage ? ). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation in struments, traffic signal instruments, combustion control instruments, medical instrument s, all types of safety devices, etc. unintended usage of toshiba products listed in this document shall be made at the customer's own risk. 021023_b the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohib ited under any applicable laws and regulations. 060106_q the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba for any infring ements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patents or other rights of toshiba or the third parties. 070122_c the products described in this document are subject to foreign exchange and foreign trade control laws. 060925_e for a discussion of how the reliability of microcontro llers can be predicted, please refer to section 1.3 of the chapter entitled quality and reliabil ity assurance/handling precautions. 030619_s ? 2008 toshiba corporation all rights reserved
revision history date revision 2006/4/26 1 first release 2006/6/2 2 contents revised 2006/8/2 3 periodical updating. no change in contents. 2007/5/10 4 contents revised 2007/6/28 5 contents revised 2007/7/10 6 contents revised 2008/3/4 7 contents revised 2008/9/30 8 contents revised
caution in setting the ua rt noise rejection time when uart is used, settings of rxdnc are limited depend ing on the transfer clock specified by brg. the com- bination "o" is available but please do not select the combination "?". the transfer clock generated by timer/counter in terrupt is calculated by the following equation : transfer clock [hz] = time r/counter source clock [hz] ttreg set value brg setting transfer clock [hz] rxdnc setting 00 (no noise rejection) 01 (reject pulses shorter than 31/fc[s] as noise) 10 (reject pulses shorter than 63/fc[s] as noise) 11 (reject pulses shorter than 127/fc[s] as noise) 000 fc/13 o o o ? 110 (when the transfer clock gen- erated by timer/counter inter- rupt is the same as the right side column) fc/8 o ? ? ? fc/16 o o ? ? fc/32ooo ? the setting except the aboveoooo

i table of contents TMP88FW45FG 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 pin names and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. functional description 2.1 functions of the cpu core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.1 memory address map ............................................................................................................................... 9 2.1.2 program memory (rom) ........................................................................................................................ 10 2.1.3 data memory (ram) ............................................................................................................................... 10 2.1.4 system clock control circuit .................................................................................................................. 11 2.1.4.1 clock generator 2.1.4.2 timing generator 2.1.4.3 standby control circuit 2.1.4.4 controlling operation modes 2.1.5 reset circuit ............................................................................................................................... ............ 23 2.1.5.1 external reset input 2.1.5.2 adress trap reset 2.1.5.3 watchdog timer reset 2.1.5.4 system clock reset 3. interrupt control circuit 3.1 interrupt latches (il39 to il2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2 interrupt enable register (eir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2.1 interrupt master enable flag (imf) .......................................................................................................... 27 3.2.2 individual interrupt enable flags (ef39 to ef3) ...................................................................................... 27 3.3 interrupt sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.3.1 interrupt acceptance processing is packaged as follows. ....................................................................... 30 3.3.2 saving/restoring general-purpose registers ............................................................................................ 31 3.3.2.1 using automatic register bank switcing 3.3.2.2 using register bank switching 3.3.2.3 using push and pop instructions 3.3.2.4 using data transfer instructions 3.3.3 interrupt return ............................................................................................................................... ......... 33 3.4 software interrupt (intsw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.4.1 address error detection .......................................................................................................................... 34 3.4.2 debugging ............................................................................................................................... ............... 34 3.5 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4. special function register 4.1 sfr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.2 ebr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
ii 4.3 dbr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5. input/output ports 5.1 port p0 (p03 to p00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.2 port p1 (p17 to p10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.3 port p2 (p22 to p20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.4 port p3 (p37 to p30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.5 port p4 (p47 to p40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.6 port p5 (p57 to p50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.7 port p6 (p67 to p60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.8 port p7 (p77 to p70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.9 port p8 (p87 to p80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.10 port p9 (p97 to p90) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6. time base timer (tbt) and divider output (dvo) 6.1 time base timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.2 divider output (dvo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7. watchdog timer (wdt) 7.1 watchdog timer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.2 watchdog timer control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.2.1 malfunction detection methods using the watchdog timer ................................................................... 62 7.2.2 watchdog timer enable ......................................................................................................................... 63 7.2.3 watchdog timer disable ........................................................................................................................ 64 7.2.4 watchdog timer interrupt (intwdt) ...................................................................................................... 64 7.2.5 watchdog timer reset ........................................................................................................................... 65 8. 16-bit timercounter 1 (tc1) 8.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 8.2 timercounter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 8.3.1 timer mode ............................................................................................................................... .............. 70 8.3.2 external trigger timer mode .................................................................................................................. 72 8.3.3 event counter mode ............................................................................................................................... 74 8.3.4 window mode ............................................................................................................................... .......... 75 8.3.5 pulse width measurement mode ............................................................................................................ 76 8.3.6 programmable pulse generate (ppg) output mode ............................................................................. 79 9. 16-bit timer (ctc) 9.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 9.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 9.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 9.3.1 timer mode with software start ............................................................................................................... 87 9.3.2 timer mode with external trigger start .................................................................................................... 88
iii 9.3.3 event counter mode ............................................................................................................................... . 89 9.3.4 programmable pulse generate (ppg) output mode .............................................................................. 90 10. 8-bit timercounter 3 (tc3) 10.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 10.2 timercounter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 10.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.3.1 timer mode ............................................................................................................................... ............ 99 figure 10-3 ................................................................................................................ .................................... 101 10.3.3 capture mode ............................................................................................................................... ...... 102 11. 8-bit timercounter 4 (tc4) 11.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 11.2 timercounter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 11.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 11.3.1 timer mode ............................................................................................................................... .......... 105 11.3.2 event counter mode ........................................................................................................................... 105 11.3.3 programmable divider output (pdo) mode ....................................................................................... 105 11.3.4 pulse width modulation (pwm) output mode .................................................................................... 106 12. 8-bit timercounter 5,6(tc5, 6) 12.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 12.2 timercounter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 12.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 12.3.1 8-bit timer mode (tc5 and 6) ............................................................................................................ 114 12.3.2 8-bit event counter mode (tc5, 6) .................................................................................................... 115 12.3.3 8-bit programmable divider output (pdo) mode (tc5, 6) ................................................................. 115 12.3.4 8-bit pulse width modulation (pwm) output mode (tc5, 6) .............................................................. 117 12.3.5 16-bit timer mode (tc5 and 6) .......................................................................................................... 119 12.3.6 16-bit event counter mode (tc5 and 6) ............................................................................................ 120 12.3.7 16-bit pulse width modulation (pwm) output mode (tc5 and 6) ...................................................... 120 12.3.8 16-bit programmable pulse generate (ppg) output mode (tc5 and 6) ........................................... 123 13. motor control circuit (pmd: programmable motor driver) 13.1 outline of motor control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.2 configuration of the motor control circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 13.3 position detection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 13.3.1 configuration of the position detection unit ......................................................................................... 130 13.3.2 position detection circ uit register functions ..................................................................................... 131 13.3.3 outline processing in the position detection unit .............................................................................. 134 13.4 timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 13.4.1 configuration of the timer unit ........................................................................................................... 136 13.4.1.1 timer circuit register functions 13.4.1.2 outline processing in the timer unit 13.5 three-phase pwm output unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 13.5.1 configuration of the three-phase pwm output unit ............................................................................. 140 13.5.1.1 pulse width modulation circuit (pwm waveform generating unit) 13.5.1.2 commutation control circuit 13.5.2 register functions of the waveform synthesis circuit ....................................................................... 144 13.5.3 port output as set with uoc/voc/ woc bits and upwm/vpwm/wpwm bits ................................... 146
iv 13.5.4 protective circuit ............................................................................................................................... .. 148 13.5.5 functions of protective circuit registers ............................................................................................ 150 13.6 electrical angle timer and waveform arithmetic circuit . . . . . . . . . . . . . . . . . . 152 13.6.1 electrical angle timer and wa veform arithmetic circuit .................................................................... 153 13.6.1.1 functions of the electrical angle timer and waveform arithmetic circuit registers 13.6.1.2 list of pmd related control registers 14. asynchronous serial interface (uart1) 14.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 14.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 14.3 transfer data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 14.4 transfer rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 14.5 data sampling method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 14.6 stop bit length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 14.7 parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 14.8 transmit/receive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 14.8.1 data transmit operation .................................................................................................................... 170 14.8.2 data receive operation ..................................................................................................................... 170 14.9 status flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 14.9.1 parity error ............................................................................................................................... ........... 171 14.9.2 framing error ............................................................................................................................... ....... 171 14.9.3 overrun error ............................................................................................................................... ....... 171 14.9.4 receive data buffer full ..................................................................................................................... 172 14.9.5 transmit data buffer empty ............................................................................................................... 172 14.9.6 transmit end flag .............................................................................................................................. 173 15. asynchronous serial interface (uart2) 15.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 15.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 15.3 transfer data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 15.4 transfer rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 15.5 data sampling method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 15.6 stop bit length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 15.7 parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 15.8 transmit/receive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 15.8.1 data transmit operation .................................................................................................................... 180 15.8.2 data receive operation ..................................................................................................................... 180 15.9 status flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 15.9.1 parity error ............................................................................................................................... ........... 181 15.9.2 framing error ............................................................................................................................... ....... 181 15.9.3 overrun error ............................................................................................................................... ....... 181 15.9.4 receive data buffer full ..................................................................................................................... 182 15.9.5 transmit data buffer empty ............................................................................................................... 182 15.9.6 transmit end flag .............................................................................................................................. 183 16. synchronous serial interface (sio) 16.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 16.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 16.3 serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 16.3.1 clock source ............................................................................................................................... ........ 187
v 16.3.1.1 internal clock 16.3.1.2 external clock 16.3.2 shift edge ............................................................................................................................... ............. 189 16.3.2.1 leading edge 16.3.2.2 trailing edge 16.4 number of bits to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 16.5 number of words to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 16.6 transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 16.6.1 4-bit and 8-bit transfer modes ............................................................................................................. 190 16.6.2 4-bit and 8-bit receive modes ............................................................................................................. 192 16.6.3 8-bit transfer / receive mode ............................................................................................................... 193 17. 10-bit ad converter (adc) 17.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 17.2 register configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 17.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 17.3.1 software start mode ........................................................................................................................... 199 17.3.2 repeat mode ............................................................................................................................... ....... 199 17.3.3 register setting ............................................................................................................................... . 200 example : .................................................................................................................. .................................... 201 17.4 stop mode during ad conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 17.5 analog input voltage and ad conversion result . . . . . . . . . . . . . . . . . . . . . . . 202 17.6 precautions about ad converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 17.6.1 analog input pin voltage range ........................................................................................................... 203 17.6.2 analog input shared pins .................................................................................................................... 203 17.6.3 noise countermeasure ....................................................................................................................... 203 18. 8-bit high-speed pwm (hpwm0 and hpwm1) 18.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 18.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 18.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 18.3.1 operation modes ............................................................................................................................... . 206 18.3.1.1 8-bit mode 18.3.1.2 7-bit mode 18.3.1.3 6-bit mode 18.3.2 setting output data .............................................................................................................................. 209 19. flash memory 19.1 flash memory control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 19.1.1 flash memory command sequence execution control (flscr) ..................................... 212 19.2 command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 19.2.1 byte program ............................................................................................................................... ....... 213 19.2.2 sector erase (4-kbyte erase) ............................................................................................................. 214 19.2.3 chip erase (all erase) ........................................................................................................................ 214 19.2.4 product id entry ............................................................................................................................... .. 214 19.2.5 product id exit ............................................................................................................................... ..... 215 19.2.6 read protect ............................................................................................................................... ........ 215 19.3 toggle bit (d6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 19.4 access to the flash memory area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 19.4.1 flash memory control in the serial prom mode ............................................................................... 216 19.4.1.1 how to write to the flash memory by executing the contro l program in the ram area (in the ram loader mode within the serial prom mode) 19.4.2 flash memory control in the mcu mode ............................................................................................ 218
vi 19.4.2.1 how to write to the flash memory by executing a user write control program in the ram area (in the mcu mode) 20. serial prom mode 20.1 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 20.2 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 20.3 serial prom mode setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 20.3.1 serial prom mode control pins ........................................................................................................ 222 20.3.2 pin function ............................................................................................................................... ......... 222 20.3.3 example connection for on-board writing ......................................................................................... 223 20.3.4 activating the serial prom mode ...................................................................................................... 224 20.4 interface specifications for uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 20.5 operation command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 20.6 operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 20.6.1 flash memory erasing mode (operating command: f0h) ................................................................. 229 20.6.2 flash memory writing mode (operation command: 30h) .................................................................. 231 20.6.3 ram loader mode (operation command: 60h) ................................................................................ 234 20.6.4 flash memory sum output mode (operation command: 90h) ......................................................... 236 20.6.5 product id code output mode (operation command: c0h) .............................................................. 237 20.6.6 flash memory status output mode (operation command: c3h) ...................................................... 239 20.6.7 flash memory read protection setting mode (operation command: fah) ...................................... 240 20.7 error code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 20.8 checksum (sum) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 20.8.1 calculation method ............................................................................................................................. 2 42 20.8.2 calculation data ............................................................................................................................... ... 242 20.9 intel hex format (binary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 20.10 passwords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 20.10.1 password string ............................................................................................................................... . 244 20.10.2 handling of password error .............................................................................................................. 244 20.10.3 password management during program development .................................................................... 244 20.11 product id code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 20.12 flash memory status code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 20.13 specifying the erasure area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 note 2: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 note 2: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 20.14 port input control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 20.15 flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 20.16 uart timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 21. input/output circuitry 21.1 control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 21.2 input/output ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 22. electrical characteristics 22.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 22.2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 22.2.1 mcu mode (flash programming or erasing) ..................................................................................... 256 22.2.2 mcu mode (except flash pr ogramming or erasing) ......................................................................... 256 22.2.3 serial prom mode ............................................................................................................................. 2 57 22.3 dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
vii 22.4 ad characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 22.5 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 22.6 flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 22.7 recommended oscillating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 22.8 handling precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 23. package dimensions this is a technical docu ment that describes the operat ing functions and electrical specifications of the 8-bit microc ontroller series tlcs-870/x (lsi).
viii
page 1 TMP88FW45FG cmos 8-bit microcontroller ? the information contained herein is subject to change without notice. 021023_d ? toshiba is continually working to improve the quality and reli ability of its products. neverthel ess, semiconductor devices in general can malfunction or fail due to their inherent el ectrical sensitivity and vul nerability to physical stre ss. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of sa fety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, pleas e ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling gui de for semiconductor devices,? or ?toshiba se miconductor reliability handbook? etc. 021023_a ? the toshiba products listed in this document are intended for usage in general electronics applic ations (computer, personal eq uip- ment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neithe r intended nor warranted for usage in equipment that requires extr aordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bod ily injury (?unintended usage?). unintended us age include atomic energy control instru ments, airplane or spaceship instruments, transporta tion instruments, traffic signal instrume nts, combustion control instruments, medi cal instru- ments, all types of safety dev ices, etc. unintended usage of toshiba products li sted in this document shall be made at the cust omer's own risk. 021023_b ? the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and /or sale are prohibited under any appl icable laws and regulations. 060106_q ? the information contained herein is present ed only as a guide for the applications of our products. no responsibility is assum ed by toshiba for any infringements of patents or other rights of the th ird parties which may result from its use. no license is gran ted by impli- cation or otherwise under any patents or other rights of toshiba or the third parties. 070122_c ? the products described in this document are subject to foreign exchange and foreign trade control laws. 060925_e ? for a discussion of how the reliability of microcontrollers c an be predicted, please refer to section 1.3 of the chapter entit led quality and reliability assurance/h andling precautions. 030619_s this product uses the super flash ? technology under the licence of silicon storage technology, inc. super flash ? is registered trademark of silicon storage technology, inc. TMP88FW45FG 1.1 features 1. 8-bit single chip microcomputer tlcs-870/x series - instruction execution time : 0.20 s (at 20 mhz) - 181 types & 842 basic instructions 2. 36 interrupt sources (external : 5 internal : 31) 3. input / output ports (71 pins) large current output: 24pins (typ. 20ma), led direct drive 4. prescaler - time base timer divider output function (dvo) 5. watchdog timer select of "internal reset request" or "interrupt request". 6. 16-bit timer counter: 1 ch - timer, external trigger, wi ndow, pulse width measurement, event counter, programmable pulse generate (ppg) modes 7. 16-bit timer/counter(ctc): 1ch - ctc:timer,event counter or ppg (programmable pulse) output 8. 8-bit timer counter : 1 ch - timer, event counter, capture modes 9. 8-bit timer counter : 1 ch product no. rom (flash) ram package TMP88FW45FG 122880 bytes 4224 bytes qfp80-p-1420-0.80b
page 2 1.1 features TMP88FW45FG - timer, event counter, pulse width modulation (pwm) output, programmable divider output (pdo) modes 10. 8-bit timer counter : 2 ch - timer, event counter, programmable divider output (pdo), pulse width modulation (pwm) output, programmable pulse generation (ppg) modes 11. programmable motor driver (pmd) : 2 ch - sine wave drive circuit (built-in sine wave data-table ram) rotor position detect function motor contro timer and capture function overload protective function auto commutation and auto position detection start function 12. 8-bit uart : 2 ch 13. 8-bit sio: 1 ch 14. 10-bit successive approximation type ad converter - analog input: 16 ch 15. 8-bit high-speed pwm ( hpwm0 and hpwm1 ) 16. clock oscillation circuit : 1 set 17. low power consumption operation (2 modes) - stop mode: oscillation stops. (battery/capacitor back-up.) - idle mode: cpu stops. only peripherals operate using high frequency clock. release by interruputs (cpu restarts). 18. operation voltage: 4.5 v to 5.5 v at 20 mhz
page 3 TMP88FW45FG 1.2 pin assignment figure 1-1 pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 vss xout test vdd (tc3) p21 ( pwm4/pdo4 /tc4/int4) p22 reset ( stop / int5 ) p20 (z1) p30 (x1) p32 (v1) p34 (w1) p33 (u1) p35 ( emg1 ) p36 ( cl1 ) p37 (pdw1) p40 (pdv1) p41 (pdu1) p42 ( sck ) p43 ( ppg2 ) p46 (so/txd1) p45 p47(ctc) p61(ain1) p62(ain2) p64(ain4) p63(ain3) p76 (ain14) p75 (ain13) p74 (ain12) p73 (ain11) p72 (ain10) p71 (ain9) p70 (ain8) p67 (ain7/dbout1) p66 (ain6) p65 (ain5) p60(ain0) p85 p84 p83 p82 p81 (txd3) p80 (rxd3) avss avdd varef p77 (ain15/dbout2) p00 (rxd2/tc6) p03 ( hpwm1 ) p02 ( hpwm0 ) p01 (txd2/ pdo6/pwm6/ppg6 ) p97 p96 p95 p94 p93 p92 p91 p90 p87 p86 (boot/si/rxd1) p44 (y1) p31 xin ( int0 ) p10 (int1) p11 (tc1/int2) p12 (tc5/ dvo ) p13 (pdu2) p15 (pdv2) p16 (pdw2) p17 ( cl2 ) p50 ( emg2 ) p51 (u2) p52 (v2) p53 (w2) p54 (x2) p55 (y2) p56 (z2) p57 ( pwm5/pdo5 / ppg1 ) p14
page 4 1.3 block diagram TMP88FW45FG 1.3 block diagram figure 1-2 block diagram
page 5 TMP88FW45FG 1.4 pin names and functions the TMP88FW45FG has mcu mode, parallel prom mode, and serial prom mode. table 1-1 shows the pin functions in mcu mode. the serial prom mode is explained later in a separate chapter. table 1-1 pin names and functions(1/4) pin name pin number input/output functions p03 hpwm1 64 io o port03 high-spped pwm1 output p02 hpwm0 63 io o port02 high-spped pwm0 output p01 txd2 pdo6/pwm6/ppg6 62 io o o port01 uart data output 2 pdo6/pwm6/ppg6 output p00 rxd2 tc6 61 io i i port00 uart data input 2 tc6 input p17 pdw2 72 io i port17 pmd control input w2 p16 pdv2 71 io i port16 pmd control input v2 p15 pdu2 70 io i port15 pmd control input u2 p14 ppg1 pwm5/pdo5 69 io o o port14 ppg1 output pwm5/pdo5 output p13 dvo tc5 68 io o i port13 divider output tc5 input p12 int2 tc1 67 io i i port12 external interrupt 2 input tc1 input p11 int1 66 io i port11 external interrupt 1 input p10 int0 65 io i port10 external interrupt 0 input p22 int4 tc4 pwm4/pdo4 7 io i i o port22 external interrupt 4 input tc4 input pwm4/pdo4 output p21 tc3 6 io i port21 tc3 pin input p20 int5 stop 9 io i i port20 external interrupt 5 input stop mode release signal input p37 cl1 17 io i port37 pmd over load protection input1 p36 emg1 16 io i port36 pmd emergency stop input1 p35 u1 15 io o port35 pmd control output u1
page 6 1.4 pin names and functions TMP88FW45FG p34 v1 14 io o port34 pmd control output v1 p33 w1 13 io o port33 pmd control output w1 p32 x1 12 io o port32 pmd control output x1 p31 y1 11 io o port31 pmd control output y1 p30 z1 10 io o port30 pmd control output z1 p47 ctc 25 i i port47 ctc input p46 ppg2 24 io o port46 ppg2o? p45 txd1 so 23 io o o port45 uart data output 1 serial data output p44 rxd1 si boot 22 io i i i port44 uart data input 1 serial data input serial prom mode control input p43 sck 21 io io port43 serial clock i/o p42 pdu1 20 io i port42 pmd control input u1 p41 pdv1 19 io i port41 pmd control input v1 p40 pdw1 18 io i port40 pmd control input w1 p57 z2 80 io o port57 pmd control output z2 p56 y2 79 io o port56 pmd control output y2 p55 x2 78 io o port55 pmd control output x2 p54 w2 77 io o port54 pmd control output w2 p53 v2 76 io o port53 pmd control output v2 p52 u2 75 io o port52 pmd control output u2 p51 emg2 74 io i port51 pmd emergency stop input2 p50 cl2 73 io i port50 pmd over load protection input2 p67 ain7 dbout1 33 io i o port67 analog input7 pmd debug output1 table 1-1 pin names and functions(2/4) pin name pin number input/output functions
page 7 TMP88FW45FG p66 ain6 32 io i port66 analog input6 p65 ain5 31 io i port65 analog input5 p64 ain4 30 io i port64 analog input4 p63 ain3 29 io i port63 analog input3 p62 ain2 28 io i port62 analog input2 p61 ain1 27 io i port61 analog input1 p60 ain0 26 io i port60 analog input0 p77 ain15 dbout2 41 io i o port77 analog input15 pmd debug output2 p76 ain14 40 io i port76 analog input14 p75 ain13 39 io i port75 analog input13 p74 ain12 38 io i port74 analog input12 p73 ain11 37 io i port73 analog input11 p72 ain10 36 io i port72 analog input10 p71 ain9 35 io i port71 analog input9 p70 ain8 34 io i port70 analog input8 p87 52 io port87 p86 51 io port86 p85 50 io port85 p84 49 io port84 p83 48 io port83 p82 47 io port82 p81 txd3 46 io i port81 uart data output 3 p80 rxd3 45 io i port80 uart data input 3 p97 60 io port97 p96 59 io port96 p95 58 io port95 table 1-1 pin names and functions(3/4) pin name pin number input/output functions
page 8 1.4 pin names and functions TMP88FW45FG p94 57 io port94 p93 56 io port93 p92 55 io port92 p91 54 io port91 p90 53 io port90 xin 2 i resonator connecting pins for high-frequency clock xout 3 o resonator connecting pins for high-frequency clock reset 8 i reset signal test 4 i test pin for out-going test and the serial prom mode control pin. usually fix to low level. fix to high level when the serial prom mode starts. varef 42 i analog base voltage input pin for a/d conversion avdd 43 i analog power supply avss 44 i analog power supply vdd 5 i +5v vss 1 i 0(gnd) table 1-1 pin names and functions(4/4) pin name pin number input/output functions
page 9 TMP88FW45FG 2. functional description 2.1 functions of the cpu core the cpu core consists mainly of the cpu, system clock control circuit, and interrupt control circuit. this chapter describes the cpu core, program memory, data memory, and reset circuit of the TMP88FW45FG. 2.1.1 memory address map the memory of the TMP88FW45FG consists of four blocks: rom, ram, sfr (special function regis- ters), and dbr/ebr (data buffer registers), which ar e mapped into one 1-mbyte address space. the general- purpose registers consist of 16 banks, which are ma pped into the ram addre ss space. figure 2-1 shows a memory address map of the TMP88FW45FG. figure 2-1 memory address map vector table for vector call instructions interrupt vector table interrupt vector table program memory rom ( bytes) ram ( bytes) ram (128 bytes) sfr rom: read-only memory program memory vector table sfr: special function registers input/output port peripheral hardware control register peripheral hardware status register system control register interrupt control register program status word dbr: data buffer registers input/output port peripheral hardware control registe r peripheral hardware status register ram: random access memory data memory stack general-purpose register bank random-access memory special function register general-purpose register bank (8 registers 16 banks) data buffer register (peripheral hardware control register / status register) 64 bytes 64 bytes 64 bytes 128 bytes bytes bytes 128 bytes 00000h 000c0h 000bfh 04000h 0003fh 00040h 01fffh fffffh fff7fh fff80h fff40h fff00h fff3fh bytes 4k 4096 120k 122624 dbr/ebr 01f70h 21effh ebr: extra data buffer registers input/output port peripheral hardware control register peripheral hardware status register 010bfh 144
page 10 2. functional description 2.1 functions of the cpu core TMP88FW45FG 2.1.2 program memory (rom) the TMP88FW45FG contains 120kbytes program memory (flash) located at addresses 04000h to 21effh and addresses fff00h to fffffh. 2.1.3 data memory (ram) the TMP88FW45FG contains 4kbytes +128bytes ram. the first 128bytes location (00040h to 000bfh) of the internal ram is shared wi th a general-purpose register bank. the content of the data memory is indeterminate at power-on, so be sure to initialize it in the initialize rou- tine . note:because general-purpose registers exist in the ra m, never clear the current bank address of ram. in the above example, the ram is cleared except bank 0. example :clearing the internal ra m of the TMP88FW45FG (clear all ram addresses to 0, except bank 0) ld hl, 0048h ; set the start address ld a, 00h ; set the initialization data (00h) ld bc, 1077h ; set byte counts (-1) sramclr: ld (hl+), a dec bc jrs f, sramclr
page 11 TMP88FW45FG 2.1.4 system clock control circuit the system clock control circuit consists of a clock generator, timing generator, and standby control cir- cuit. figure 2-2 system clock control circuit 2.1.4.1 clock generator the clock generator generates the fundamental clock which serves as the reference for the system clocks supplied to the cpu core and peripheral hardware units. the high-frequency clock (frequency fc) can be obtai ned easily by connecting a resonator to the xin and xout pins. or a clock generated by an external os cillator can also be used. in this case, enter the external clock from the xin pin and leave the xout pin open. the TMP88FW45FG does not support the cr network that produces a time constant. figure 2-3 example fo r connecting a resonator adjusting the oscillation frequency note: although no hardware functions are provided that a llow the fundamental clock to be monitored directly from the outside, the oscillation frequency can be adjus ted by forwarding the pulse of a fixed frequency (e.g., clock output) to a port and monitoring it in a program while interrupts and the watchdog timer are disabled. for systems that require adjusting the os cillation frequency, an adjustment program must be created beforehand. 2.1.4.2 timing generator the timing generator generates various system cloc ks from the fundamental clock that are supplied to the cpu core and peripheral hardware units. the timing generator has the following functions: 1. generate a divider output ( dvo ) pulse 2. generate the source clock for the time base timer 3. generate the source clock for the watchdog timer 4. generate the internal source clock for the timer counter 5. generate a warm-up clock when exiting stop mode (1) configuration of the timing generator the timing generator a 3-stage prescaler, 21-st age dividers, and a machine cycle counter. xin high-frequency clock xout (a) using a crystal or ceramic resonator xin xout (b) using an external oscillator (open)
page 12 2. functional description 2.1 functions of the cpu core TMP88FW45FG when reset and when entering/exiting stop mode , the prescaler and divi ders are cleared to 0. figure 2-4 configuration of the timing generator dv1ck fc prescaler divider divider selector timer counter machine cycle counter 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 s a y b 6 5 4 3 2 1 1 2 0 standby control circuit watchdog timer time base timer divider output etc.
page 13 TMP88FW45FG note 1: fc: the high-frequency clock [hz], *: don?t care note 2: the cgcr register bits 4 and 3 show an indeterminate value when read. note 3: be sure to write ?0? to cgcr register bits 7, 6, 2, 1 and 0. note 1: *: don?t care note 2: be sure to write ?0? to tbtcr register bit 4. (2) machine cycle instruction execution and the intern al hardware operations are sync hronized to the system clocks. the minimum unit of instruction execution is referred to as the ?machine cycle?. the tlcs-870/x series has 15 types of instructions, from 1-cycl e instructions which are executed in one machine cycle up to 15-cycle instru ctions that require a maxi mum of 15 machine cycles. a machine cycle consists of four states (s0 to s3), with each st ate comprised of one main system clock cycle. figure 2-5 machine cycles divider control register cgcr (0030h) 76543210 0 0 dv1ck 0 0 0 (initial value: 000* *000) dv1ck selects input clock to the first divider stage 0: fc/4 1: fc/8 r/w timing generator control register tbtcr (0036h) 76543210 dvoen dvock 0 tbten tbtck (initial value: 0000 0000) main system clock states s0 s1 s2 s3 s0 s1 s2 s3 1/fc (0.20 s at 20 mhz) machine cycle
page 14 2. functional description 2.1 functions of the cpu core TMP88FW45FG 2.1.4.3 standby control circuit the standby control circuit starts/stops the high-fre quency clock oscillator ci rcuit and selects the main system clock. the system contro l registers (syscr1, syscr2) are us ed to control operation modes of this circuit. figure 2-6 shows an operation mode tran sition diagram, followed by description of the sys- tem control registers. (1) single clock mode only the high-frequency clock osci llator circuit is used. because the main system clock is gener- ated from the high-frequency clock, the machin e cycle time in single clock mode is 4/fc [s]. 1. normal mode in this mode, the cpu core and peripheral hardware units are opera ted with the high-fre- quency clock. the TMP88FW45FG enters this normal mode after reset. 2. idle mode in this mode, the cpu and watchdog timer ar e turned off while the peripheral hardware units are operated with the hi gh-frequency clock. idle mode is entered into by using system control register 2. the device is placed out of this mode and back into normal mode by an interrupt from the peripheral hardware or an external interrupt. wh en imf (interrupt mas- ter enable flag) = 1 (interrupt enabled), the de vice returns to normal op eration after the inter- rupt has been serviced. when imf = 0 (interr upt disabled), the devi ce restarts execution beginning with the instruction next to one that placed it in idle mode. 3. stop mode the entire system operat ion including the oscillator circuit is halted, retaining the internal state immediately before being stopped, with a minimal amount of power consumed. stop mode is entered into by using system control register 1, and is exited by stop pin input (level or edge selectable). after an elap se of the warm-up time, the device restarts exe- cution beginning with the inst ruction next to one that placed it in stop mode. figure 2-6 operation mode transition diagram table 2-1 single clock mode operation mode oscillator circuit cpu core peripheral circuit machine cycle time high frequency low frequency single clock reset oscillate - reset reset 4/fc [s] normal operate operate idle stop stop stop stop - reset stop mode normal mode idle mode interrupt instruction input for releasing mode instruction reset deasserted
page 15 TMP88FW45FG note 1: when entering from normal mode into stop mode, always be sure to set syscr1 to 0. note 2: when the device is released from stop mode by reset pin input, it always returns to normal mode regardless of how syscr1 is set. note 3: fc: high-frequency clock [hz], *: don?t care note 4: the values of the syscr1 register bits 1 and 0 are indeterminate when read. note 5: when placed the device in stop mode, make sure to set "1" to syscr1. note 6: releasing the device from the stop mode caus es the stop bit to be automatically cleared to ?0?. note 7: select an appropriate value for the warm-up time according to the characteristic of the resonator used. note 1: when exiting stop mode, syscr2 ar e automatically rewritten according to syscr1.. note 2: when syscr2is cleared to 0, the device is reset. note 3: wdt: watchdog timer, *: don?t care note 4: be sure to write "0" to syscr2 register bit6. note 5: the values of the syscr2 register bits 3 to 0 are indeterminate when read. note 6: change the operation mode after disabling external interrupts. if interrupts are enabled after changing operation mode, clear interrupt latches as appropriate in advance. system control register 1 syscr1 (0038h) 76543210 stop relm retm outen wut (initial value: 0000 00**) stop place the device in stop mode 0: keep the cpu core and peripheral hardware operating 1: stop the cpu core and peripheral hardware (placed in stop mode) r/w relm select method by which the device is released from stop mode 0: released by a rising edge on stop pin input 1: released by a high level on stop pin input retm select operation mode after exiting stop mode 0: returns to normal mode 1: reserved outen select port output state during stop mode 0: high-impedance state 1: hold output wut unit of warm-up time when exiting stop mode when returning to normal mode dv1ck = 0 dv1ck = 1 00 3 2 16 /fc 3 2 17 /fc 01 2 16 /fc 2 17 /fc 10 2 14 /fc 2 15 /fc 11 reserved reserved system control register 2 syscr2 (0039h) 76543210 xen 0 sysck idle (initial value: 1000 ****) xen control high-frequency oscilla- tor 0: stop oscillation 1: continue or start oscillating r/w sysck select (write)/monitor (read) system clock 0: high-frequency clock (normal/idle) 1: reserved r/w idle place the device in idle mode 0: keep the cpu and wdt operating 1: stop the cpu and wdt (idle mode entered) r/w retm operation mode after releasing stop mode xen sysck 0 normal mode 1 0 1 no operation 0 1
page 16 2. functional description 2.1 functions of the cpu core TMP88FW45FG 2.1.4.4 controlling operation modes (1) stop mode stop mode is controlled by system control register 1 (syscr1) and the stop pin input. the stop pin is shared with p20 port and int5 (external interrupt input 5). stop mode is entered into by setting stop (syscr1 register b it 7) to 1. during stop mode, the device retains the following state. 1. stop oscillation, thereby stopping operation of all internal circuits. 2. the data memory, register, program status word, and port output latch hold the state in which they were immediately before entering stop mode. 3. clear the prescaler and divide r for the timing generator to 0. 4. the program counter holds the instruction ad dress two instructions ahead the one that placed the device in stop mode (e.g., ?set (syscr1).7?). the device is released from stop mode by the ac tive level or edge on stop pin input as selected by syscr1. note: before entering stop mode, be sure to disable interrupts. this is because if the signal on an external interrupt pin changes state during stop (from entering stop mode till completion of warm-up) the interrupt latch is set to 1, so th at the device may accept the interrupt immediately after exiting stop mode. also, when reenabling interrupts after exiting stop mode, be sure to clear the unnecessary interrupt latches beforehand. a. released by level (when relm = 1) the device is released from stop mode by a high level on stop pin input. any instruction to place the device in stop mode is ignored when executed while stop pin input level is high, and the device imme diately goes to a release sequence (warm-up) without entering stop mode. th erefore, before stop mode can be entered while relm = 1, the stop pin input must be verified to be low in a program. there are following methods to do this verification. 1. testing the port status 2. int5 interrupt (interrupt generated at a falling edge on int5 pin input) example 1 :entering stop mode from normal mode by testing p20 port ld (syscr1), 01010000b ; select to be released from stop mode by level sstoph : test (p2dr) . 0 ; wait until stop pin input goes low jrs f, sstoph di ; imf 0 set (syscr1) . 7 ; place the device in stop mode example 2 :entering stop mode from normal mode by int5 interrupt pint5 : test (p2dr) . 0 ; do not enter stop mode if p20 port input level is high, to eliminate noise jrs f, sint5 ; do not enter stop mode if p20 port input level is high, to eliminate noise ld (syscr1), 01010000b ; select to be released from stop mode by level di ; imf 0 set (syscr1) . 7 ; place the device in stop mode sint5 : reti
page 17 TMP88FW45FG figure 2-7 released fr om stop mode by level note 1: once warm-up starts, the device does not return to stop mode even when the stop pin input is pulled low again. note 2: if relm is changed to 1 (level mode) after being set to 0 (edge mode), stop mode remains unchanged unless a rising edge on stop pin input is detected. a. released by edge (when relm = 0) the device is released from stop mode by a rising edge on stop pin input. this method is used in applications where a relatively short time of program processi ng is repeated at cer- tain fixed intervals. apply a fixed-period sign al (e.g., clock from the low-power oscillating source) to the stop pin. when relm = 0 (edge mode), the device is placed in stop mode even when the stop pin input level is high. figure 2-8 released fr om stop mode by edge example :entering stop mode from normal mode di ; imf 0 ld (syscr1) , 10010000b ; set to be released by edge when entering stop mode stop pin xout pin normal operation released from stop mode in hardware normal operation v ih stop mode warm-up detect low on stop pin input in a program before entering stop mode always released by a high level on stop pin input stop pin xout pin normal operation v ih stop mode warm-up stop mode placed into stop mode in a program released from stop mode in hardware by a rising edge on stop pin input. normal operation
page 18 2. functional description 2.1 functions of the cpu core TMP88FW45FG the device is released from stop mode following the sequence described below. 1. only the high-frequency oscillator is oscillating. 2. a warm-up time is inserted in order to allow for the clock oscillation to stabilize. during warm-up, the internal circuits remain idle. the warm-up time can be selected from three choices according to the oscillator characteristics by using syscr1. 3. after an elapse of the warm-up time, the de vice restarts normal operation beginning with the instruction next to one that placed it in stop mode. at this time, the prescaler and divider for the timing generator st art from the zero-cleared state. note: because the warm-up time is obtained from the f undamental clock by dividi ng it, if the oscillation frequency fluctuates while exiting stop mode, t he warm-up time becomes to have some error. therefore, the warm-up time must be handled as an approximate value. the device can also be released from stop mode by pulling the reset pin input low, in which case the device is immediately reset as is normally reset by reset . after reset, the device starts oper- ating from normal mode. note: when exiting stop mode while the device is re tained at low voltage, the following caution is required. before exiting stop mode, the power supply volt age must be raised to the operating voltage. at this time, the reset pin level also is high and rises along with the power supply voltage. if the device has a time-constant circuit added external to the chip, the voltage on reset pin input does not rise as fast as the power supply voltage. therefore, if the voltage level on reset pin input is below the reset pin?s noninverted, high-level input voltage (hysteresis input), the device may be reset. table 2-2 warm-up time (example: fc = 20 mhz) wut warm-up time [ms] when returning to normal mode dv1ck = 0 dv1ck = 1 00 9.831 19.662 01 3.277 6.554 10 0.819 1.638 11 reserved reserved
page 19 TMP88FW45FG figure 2-9 entering and exit ing stop mode (when dv1ck = 0) oscillation instruction execution divider (a) entering stop mode (example: entered into by the set (syscr1). 7 instruction placed at address a) main system clock main system clock program counter stop stop a + 2 a + 3 n n + 1 n + 2 n + 3 n + 4 0 set (syscr1). 7 oscillator circuit oscillator circuit warm-up (b) exiting stop mode oscillation instruction execution divider program counter stop stop count up 0 0 1 2 3 a + 3 instruction at address a + 4 instruction at address a + 3 instruction at address a + 2 stop pin input a + 4 a + 5 a + 6
page 20 2. functional description 2.1 functions of the cpu core TMP88FW45FG (2) idle mode idle mode is controlled by system control re gister 2 (syscr2) and a maskable interrupt. dur- ing idle mode, the device retains the following state. 1. the cpu and watchdog timer stop operating. the peripheral hardware continues operating. 2. the data memory, register, program status word, and port output latch hold the state in which they were immediately before entering idle mode. 3. the program counter holds the instruction ad dress two instructions ahead the one that placed the device in idle mode. figure 2-10 idle mode example :placing the device in idle mode set (syscr2) . 4 place the device in idle mode (by instruction) stop the cpu and wdt interrupt handling execute the instruction next to one that placed device idle mode reset ye s no no no interrupt request ? imf = 1 reset input ? ye s yes (released by interrupt) (released normally)
page 21 TMP88FW45FG the device can be released from id le mode normally or by an interr upt as selected with the inter- rupt master enable flag (imf). a. released normally (when imf = 0) the device can be released from idle mode by the interrupt source enabled by the inter- rupt individual enable flag (e f), and restarts execution beginning with the instruction next to one that placed it in idle mode. the interrupt latc h (il) for the interrupt source used to exit idle mode normally needs to be clear ed to 0 using a load instruction. b. released by interrupt (when imf = 1) the device can be released from idle mode by the interrupt source enabled by the inter- rupt individual enable flag (e f), and enters interrupt handling. after interrupt handling, the device returns to the instruction next to one that placed it in idle mode. the device can also be released from idle mode by pulling the reset pin input low, in which case the device is immediately reset as is normally reset by reset . after reset, the device starts oper- ating from normal mode. note: if a watchdog timer interrupt occurs immedi ately before entering idle mode, the device pro- cesses the watchdog timer interrupt without entering idle mode.
page 22 2. functional description 2.1 functions of the cpu core TMP88FW45FG figure 2-11 entering and exiting idle mode (b) exiting idle mode (a) entering idle mode (example: entered into by the set instruction placed at address a) idle a + 2 a + 3 set (syscr2). 4 operating 1. released normally idle idle a + 3 a + 4 instruction at address a + 2 operating 2. released by interrupt idle idle a + 3 interrupt accepted operating main system clock interrupt request program counter instruction execution main system clock interrupt request program counter instruction execution watchdog timer main system clock interrupt request program counter instruction execution watchdog timer watchdog timer
page 23 TMP88FW45FG 2.1.5 reset circuit the TMP88FW45FG has four ways to generate a reset: external reset input, addr ess trap reset, watchdog timer reset and system clock reset. table 2-3 shows how the internal hardware is initialized by reset operation. at power-on time, the internal cause reset circuits (watch dog timer reset, address trap reset, and system clock reset) are not initialized. 2.1.5.1 external reset input the reset pin is a hysteresis input with a pull-up resistor included. by holding the reset pin low for at least three machine cycles (12/fc [s]) or more while the power supply voltage is within the rated operat- ing voltage range and the oscillator is oscillating stably, the device is reset and its internal state is initial- ized. when the reset pin input is released back high, the device is freed from reset and starts executing the program beginning with the vector addre ss stored at addresses ffffch to ffffeh. figure 2-12 reset circuit 2.1.5.2 adress trap reset if the cpu should start looping for reasons of noise, etc. and attempts to fetch instructions from the internal ram,sfr or dbr/ebr area, the device generats an internal reset. table 2-3 internal hardware in itialization by reset operation internal hardware initial value i nternal hardware initial value program counter (pc) (ffffeh to ffffch) prescaler and divider for the timing generator 0 stack pointer (sp) not initialized general-purpose registers (w, a, b, c, d, e, h, l) not initialized register bank selector (rbs) 0 watchdog timer enable jump status flag (jf) 1 zero flag (zf) not initialized output latch of input/output port see description of each input/output port. carry flag (cf) not initialized half carry flag (hf) not initialized sign flag (sf) not initialized overflow flag (vf) not initialized interrupt master enable flag (imf) 0 interrupt individual enable flag (ef) 0 control register see description of each control register. interrupt latch (il) 0 interrupt nesting flag (inf) 0 ram not initialized reset input vdd reset
page 24 2. functional description 2.1 functions of the cpu core TMP88FW45FG the addess trap permission/prohibition is set by the address trap reset contro l register (atas,atkey). the address trap is permited initially and the inte rnal reset is generated by fetching from internal ram,sfr or dbr/ebr area. if the address trap is prohibited, instru ctions in the internal ram area can be executed. note: read-modify-write instructions, such as a bit manipulat ion, cannot access atas or atkey register because these register are write only. note 1: in development tools, address trap cannot be pr ohibited in the internal ram,sfr or dbr/ebr area with the address trap control registers. when us ing development tools, even if the address trap per- mission/prohibition setting is changed in the user?s program, this change is ineffective. to execute instructions from the ram area, development tools must be set accordingly. note 2: while the swi instruction at an address imm ediately before the address trap area is executing, the program counter is incremented to point to the next address in the address trap area; an address trap is therefore taken immediately. development tool setting ? to prohibit the address trap: 1. modify the iram (mapping attribute) area to (00040h to 000bfh) in the memory map win- dow. 2. set 000c0h to "address trap prohibition ar ea" as a new eram (mapping attribute) area. 3. load the user program 4. execute the address trap prohibition code in the user?s program 2.1.5.3 watchdog timer reset refer to the section ?watchdog timer.? 2.1.5.4 system clock reset when syscr2 is cleared to 0 or wh en syscr2 is cleared to 0 while syscr2 = 0, the system clock is turned off, causing the cpu to become locked up. to prevent this problem, upon detecting syscr2 = 0, syscr2 = syscr2 = 0 or syscr2 = 1, the device automatically generates an internal reset signal to let the system clock continue oscillating. address trap control register atas (1f94h) 76543210 - - - - - - - atas (initial value: **** ***0) atas select the address trap permission / prohibition 0: permit address trap 1: prohibit address trap (it may be available after setting control code for atkey register) write only address trap control code register atkey (1f95h) 76543210 (initial value: **** ****) atkey write control code to prohibit address trap d2h: address trap prohibition code others: ineffective write only
page 25 TMP88FW45FG 3. interrupt control circuit the TMP88FW45FG has a total of 36 interrupt sources excludi ng reset. interrupts can be nested with priorities. two of the internal interrupt sources are pseudo nonmaskable while the rest are maskable. interrupt sources are provided with interrupt latches (il) , which hold interrupt requests, and independent vectors. the interrupt latch is set to ?1? by th e generation of its interrupt request wh ich requests the cpu to accept its inter- rupts. interrupts are enabled or disabled by software using the interrupt master enable fl ag (imf) and in terrupt enable flag (ef). if more than one interrupts are generated simultaneously, interrup ts are accepted in order which is domi- nated by hardware. however, there are no prioritized interrupt factors among non-maskable interrupts. interrupt factors enable condition interrupt latch vector address priority internal/external (reset) nonmaskable ? ffffc high 0 internal intswi (software interrupt) pseudo nonmaskable ? ffff8 1 internal intwdt (watchdog timer interrupt) pseudo nonmaskable il2 ffff4 2 - reserved (external interrupt 0) imf? ef3 = 1, int0en = 1 il3 ffff0 3 reserved imf? ef4 = 1 il4 fffec 4 external int1 (external interrupt 1) imf? ef5 = 1 il5 fffe8 5 internal inttbt (tbt interrupt) imf? ef6 = 1 il6 fffe4 6 reserved imf? ef7 = 1 il7 fffe0 7 internal intemg1 (ch1 error detect interrupt) imf? ef8 = 1 il8 fffdc 8 internal intemg2 (ch2 error detect interrupt) imf? ef9 = 1 il9 fffd8 9 internal intclm1 (ch1 overload protection interrupt) imf? ef10 = 1 il10 fffd4 10 internal intclm2 (ch2 overload protection interrupt) imf? ef11 = 1 il11 fffd0 11 internal inttmr31 (ch1 timer 3 interrupt) imf? ef12 = 1 il12 fffcc 12 internal inttmr32 (ch2 timer 3 interrupt) imf? ef13 = 1 il13 fffc8 13 reserved imf? ef14 = 1 il14 fffc4 14 external int5 (external interrupt 5) imf? ef15 = 1 il15 fffc0 15 internal intpdc1 (ch1 posision detect interrupt) imf? ef16 = 1 il16 fffbc 16 internal intpdc2 (ch2 posision detect interrupt) imf? ef17 = 1 il17 fffb8 17 internal intpwm1 (ch1 waveform generater interrupt) imf? ef18 = 1 il18 fffb4 18 internal intpwm2 (ch2 waveform generater interrupt) imf? ef19 = 1 il19 fffb0 19 internal intedt1 (ch1 erectric angle timer interrupt) imf? ef20 = 1 il20 fffac 20 internal intedt2 (ch2 erectric angle timer interrupt) imf? ef21 = 1 il21 fffa8 21 internal inttmr11 (ch1 timer1 interrupt) imf? ef22 = 1 il22 fffa4 22 internal inttmr12 (ch2 timer1 interrupt) imf? ef23 = 1 il23 fffa0 23 internal inttmr21 (ch1 timer2 interrupt) imf? ef24 = 1 il24 fff9c 24 internal inttmr22 (ch2 timer2 interrupt) imf? ef25 = 1 il25 fff98 25 internal inttc1 (tc1 interrupt) imf? ef26 = 1 il26 fff94 26 internal intctc1 (ctc interrupt) imf? ef27 = 1 il27 fff90 27 internal inttc6 (tc6 8bit/16bit interrupt) imf? ef28 = 1 il28 fff8c 28 external int2 (external interrupt 2) imf? ef29 = 1 il29 fff88 29
page 26 3. interrupt control circuit 3.1 interrupt latches (il39 to il2) TMP88FW45FG note 1: to use the watchdog timer interrupt (intwdt), clear wdtcr1 to "0" (it is set for the "reset request" after reset is released). it is described in the section "watchdog timer" for details. 3.1 interrupt latches (il39 to il2) an interrupt latch is provided for eac h interrupt source, except for a software interrupt and an executed the unde- fined instruction interrupt. when interrupt request is genera ted, the latch is set to ?1?, and the cpu is requested to accept the interrupt if its interrupt is enabled. the interrupt latch is cleared to "0" immediately after accepting inter- rupt. all interrupt latches are initialized to ?0? during reset. the interrupt latches are located on address 003ch, 0 03dh, 002eh, 002fh and 002bh in sfr area. each latch can be cleared to "0" individually by instruction. however, il2 and il3 should not be cleared to "0" by software. for clearing the interrupt latch, load instruction should be used and then il2 should be set to "1". if the read-modify- write instructions such as bit manipulation or operation instructions are used, interrupt request would be cleared inadequately if interrupt is requeste d while such instructions are executed. since interrupt latches can be read, the status for interrupt requests can be monitored by software. but interrupt latches are not set to ?1? by an instruction. note: in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf new ly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0 " automatically, clearing imf need not execute normally on interrupt service routine. however, if using multiple inte rrupt on interrupt service routine, manipulating ef or il should be executed before setting imf="1". internal intrxd2 (ch2 uart receive interrupt) imf? ef30 = 1 il30 fff84 30 external int4 (external interrupt 4) imf? ef31 = 1 il31 fff80 31 internal intrxd (ch1 uart receive interrupt) imf? ef32 = 1 il32 fff3c 32 internal inttxd (ch1 uart transmit interrupt) imf? ef33 = 1 il33 fff38 33 internal intsio (sio interrupt) imf? ef34 = 1 il34 fff34 34 internal inttc3 (tc3 interrupt) imf? ef35= 1 il35 fff30 35 internal inttc4 (tc4 interrupt) imf? ef36 = 1 il36 fff2c 36 internal inttc5 (tc5 interrupt) imf? ef37 = 1 il37 fff28 37 internal intadc (a/d converter interrupt) imf? ef38 = 1 il38 fff24 38 internal inttxd2 (ch2 uart transmit interrupt) imf? ef39 = 1 il39 fff20 low 39 example 1 :clears interrupt latches di ; imf 0 ld (ill), 111010000011 1111b ; il2 to il7 0 ld (ilh), 1110100000 111111b ; il8 to i l15 0 ld (ile), 1110100000111111b ; il16 to il23 0 ld (ild), 1110100000 111111b ; il24 to il31 0 ld (ilc), 1110100000 111111b ; il32 to il39 0 ei ; imf 1 example 2 :reads interrupt latches ld wa, (ill) ; w (ilh), a (ill) ld bc, (ile) ; b (ild), c (ile) ld d, (ilc) ; d (ilc) example 3 :tests interrupt latches test (ill). 7 ; if il7 = 1 then jump jr f, sset interrupt factors enable condition interrupt latch vector address priority
page 27 TMP88FW45FG 3.2 interrupt enab le register (eir) the interrupt enable register (eir) enables and disabl es the acceptance of interrupts, except for the pseudo non- maskable interrupts (software interrupt, undefined instru ction interrupt, address trap interrupt and watchdog inter- rupt). pseudo non-maskable interrupt is accep ted regardless of the contents of the eir. the eir consists of an interrupt mast er enable flag (imf) and the individua l interrupt enable flags (ef). these registers are located on address 003a h, 003bh, 002ch, 002dh and 002ah in sf r area, and they can be read and written by an instructions (including read-modify-write in structions such as bit manipulation or operation instruc- tions). 3.2.1 interrupt ma ster enable flag (imf) the interrupt enable register (imf ) enables and disables the acceptance of the whole maskable interrupt. while imf = ?0?, all maskable interrupts are not accepted regardless of the status on each individual interrupt enable flag (ef). by setting imf to ?1?, the inte rrupt becomes acceptable if th e individuals are enabled. when an interrupt is accepted, imf is cleared to ?0? after the latest st atus on imf is stacked. thus the maskable interrupts which follow are disabled temporarily . imf flag is set to "1" by the maskable interrupt return instruction [reti] after execu ting the interrupt service program r outine, and mcu can accept the inter- rupt again. the latest interrupt request is generated alr eady, it is available immedi ately after the [reti] instruc- tion is executed. on the pseudo non-maskable interrupt, the non-maskable return instruction [retn] is adopted. in this case, imf flag is set to "1" only when it performs the pseu do non-maskable interrupt service routine on the interrupt acceptable status (imf=1). however, imf is set to "0" in the pseudo non-maskable interrupt service routine, it maintains its status (imf="0"). the imf is located on bit0 in eirl (address: 003ah in sfr), and can be read and written by an instruction. the imf is normally set and cl eared by [ei] and [di] instruction respectively. during reset, the imf is initial- ized to ?0?. 3.2.2 individual interrupt enable flags (ef39 to ef3) each of these flags enables and disables the acceptan ce of its maskable interrupt . setting the corresponding bit of an individual interrupt enable flag to ?1? enables acceptan ce of its interrupt, and setting the bit to ?0? dis- ables acceptance. during reset, all the i ndividual interrupt enable flags (ef39 to ef3) ar e initialized to ?0? and all maskable interrupts are not accepted until they are set to ?1?. note:in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf become s "0" automatically, clearing imf need not execute nor- mally on interrupt service routine. however, if using mult iple interrupt on interrupt service routine, manipulat- ing ef or il should be executed before setting imf="1". example :enables interrupts individually and sets imf di ; imf 0 set (eirl), .5 ; ef5 1 clr (eirl), .6 ; ef6 0 clr (eirh), .4 ; ef12 0 clr (eird), .0 ; ef24 0 : ei ; imf 1
page 28 3. interrupt control circuit 3.2 interrupt enable register (eir) TMP88FW45FG note 1: il2 cannot alone be cleard. note 2: unable to detect the under-flow of counter. note 3: the nesting counter is set "0" initially, it performs c ount-up by the interrupt acceptance and count-down by executing t he interrupt return instruction. note 4: in main program, before manipulating the interrupt enable fl ag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clear ing imf need not execute normally on inter- rupt service routine. however, if using multiple interrupt on interrupt service routine, mani pulating ef or il should be exe- cuted before setting imf="1". note 5: do not clear il with read-modify-w rite instructions such as bit operations. interrupt latches (initial value: 0*000000 *00*0000) ilh,ill (003dh, 003ch) 1514131211109876543210 il15 - il13 il12 il11 il10 il9 il8 - il6 il5 - il3 il2 inf ilh (003dh) ill (003ch) (initial value: 00000000 00000000) ild,ile (002fh, 002eh) 1514131211109876543210 il31 il30 il29 il28 il27 il26 il25 il24 il23 il22 il21 il20 il19 il18 il17 il16 ild (002fh) ile (002eh) (initial value: 00000000) ilc (002bh) 76543210 il39 il38 il37 il36 il35 il34 il33 il32 ile (002bh) il39 to il2 interrupt latches read write r/w 0: no interrupt request 1: interrupt request 0: clears the interrupt request (note1) 1: (unable to set interrupt latch) inf interrupt nesting flag 00: out of interrupt service 01: on interrupt service of level 1 10: on interrupt service of more than level 2 11: on interrupt service of more than level 3 00: reserved 01: clear the nesting counter 10: count-down 1 step for the nesting counter (note2) 11: reserved interrupt enable registers (initial value: 0*000000 *00*0**0) eirh,eirl (003bh, 003ah) 1514131211109876543210 ef15 - ef13 ef12 ef11 ef10 ef9 ef8 - ef6 ef5 - ef3 imf eirh (003bh) eirl (003ah) (initial value: 00000000 00000000) eird,eire (002dh, 002ch) 1514131211109876543210 ef31 ef30 ef29 ef28 ef27 ef26 ef25 ef24 ef23 ef22 ef21 ef20 ef19 ef18 ef17 ef16 eird (002dh) eire (002ch) (initial value: 00000000) eire (002ah) 76543210 ef39 ef38 ef37 ef36 ef35 ef34 ef33 ef32 eire (002ah)
page 29 TMP88FW45FG note 1: do not set imf and the interrupt enable flag (ef39 to ef3) to ?1? at the same time. note 2: in main program, before manipulating the interrupt enable fl ag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clear ing imf need not execute normally on inter- rupt service routine. however, if using multiple interrupt on interrupt service routine, mani pulating ef or il should be exe- cuted before setting imf="1". ef39 to ef3 individual-interrupt enable flag (specified for each bit) 0: 1: disables the acceptance of each maskable interrupt. enables the acceptance of each maskable interrupt. r/w imf interrupt master enable flag 0: 1: disables the acceptance of all maskable interrupts enables the acceptance of all maskable interrupts
page 30 3. interrupt control circuit 3.3 interrupt sequence TMP88FW45FG 3.3 interrupt sequence an interrupt request, which raised inte rrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to ?0? by resetting or an instruction. interrupt accep tance sequence requires 12 machine cycles (2.4 s @20 mhz) after the completion of the current instruction. the interrupt serv ice task terminates upon execution of an interrupt return instruction [reti] (for maskable interrupts) or [retn] (for non-maskable interrupts). figure 3-1 shows the timing chart of interrupt acceptance processing. 3.3.1 interrupt acceptance proc essing is packaged as follows. a. the interrupt master enab le flag (imf) is cleared to ?0? in or der to disable the acceptance of any fol- lowing interrupt. b. the interrupt latch (il) for the interrupt source accepted is cleared to ?0?. c. the contents of the program coun ter (pc) and the program status word, including the interrupt master enable flag (imf), are saved (pushed) on the st ack in sequence of pswh, pswl, pce, pch, pcl. meanwhile, the stack pointer (sp) is decremented by 5. d. the entry address (interrupt vect or) of the corresponding interrupt service program, loaded on the vec- tor table, is transferred to the program counter. e. read the rbs control code from the vector table, add its msb(4bit) to the register bank selecter (rbs). f. count up the interrupt nesting counter. g. the instruction stored at the entry address of the inte rrupt service program is executed. note:when the contents of psw are saved on the stack, the contents of imf are also saved. note 1: a: return address, b: entry address, c: address which reti instruction is stored note 2: on condition that interrupt is enabled, it takes 62/fc [s] at maximum (if the interrupt latch is set at the first machin e cycle on 15 cycle instruction) to start interrupt accept ance processing since its interrupt latch is set. figure 3-1 timing chart of interrupt acceptance/return in terrupt instruction example: correspondence be tween vector table address for inttbt an d the entry address of the interrupt service program interrupt request interrupt latch (il) imf execute instruction pc sp 1-machine cycle interrupt service task n-3 n-4 n-4 a n-3 n n-5 a-1 a b b+1 b+2 a+1 a+2 b+3 c+2 c+1 execute instruction execute instruction execute reti instruction interrupt acceptance a+1 a n n-2 n-1 n-2 n-1
page 31 TMP88FW45FG figure 3-2 vector table address,entry address a maskable interrupt is not accepted until the imf is set to ?1? even if th e maskable interrupt higher than the level of current servicing interrupt is requested. in order to utilize nested interrupt service, the imf is set to ?1? in the interrupt service program. in this case, acceptable interrupt sour ces are selectively enabled by the individual interrupt enable flags. but don?t use the read-modify-write instruction for eirl(0003ah) on the pseudo non-maskable interrupt service task. to avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting imf to ?1?. as for non-maskable interr upt, keep interrupt service shorten compared with length between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply nested. 3.3.2 saving/restoring general-purpose registers during interrupt acceptance processing , the program counter (pc) and the program status word (psw, includes imf) are automati cally saved on the stack, but the accumulato r and others are not. these registers are saved by software if necessary. when multiple interrupt se rvices are nested, it is also necessary to avoid using the same data memory area for saving registers. the fo llowing four methods are used to save/restore the gen- eral-purpose registers. 3.3.2.1 using automatic register bank switcing by switching to non-use register bank, it can re store the general-purpose register at hige speed. usually the bank register "0" is assigned for main task and the bank register "1 to 15" are for the each interrupt service task. to make up its data memory efficiency, the common bank is assigned for non-mul- tiple intrrupt factor. it can return back to main-flow by executing the interrupt return instructions ([reti]/[retn]) from the current interrupt register bank automatically. thus, no need to restore the rbs by a program. 3.3.2.2 using register bank switching by switching to non-use register bank, it can restor e the general-purpose register at hige speed. usually the bank register "0" is assigned for main task and th e bank register "1 to 15" ar e for the each interrupt ser- vice task. example :register bank switching pintxx: (interrupt processing) ; begin of interrupt routine reti ; end of interrupt : vintxx: dp pintxx ; pintxx vector address setting db 1 ; rbs <- rbs + 1 rbs setting on pintxx 45h 23h 01h 06h fffe4h fffe5h fffe6h fffe7h vector rbs control code vector table address 12345h 12346h 12347h 12348h entry address interrupt service program
page 32 3. interrupt control circuit 3.3 interrupt sequence TMP88FW45FG 3.3.2.3 using push and pop instructions if only a specific register is saved or interrupts of the same source are nested , general-purpose registers can be saved/restored using the push/pop instructions. figure 3-3 save/store register using push and pop instructions 3.3.2.4 using data transfer instructions to save only a specific register wi thout nested interrupts, data tran sfer instructions are available. example :register bank switching pintxx: ld rbs, n ; rbs <- n begin of interrupt routine (interrupt processing) reti ; end of interrupt , restore rbs and interrupt return : vintxx: dp pintxx ; pintxx vector address setting db 0 ; rbs <- rbs + 0 rbs setting on pintxx example :save/store register us ing push and pop instructions pintxx: push wa ; save wa register (interrupt processing) pop wa ; restore wa register reti ; return example :save/store register us ing data transfer instructions pintxx: ld (gsava), a ; save a register (interrupt processing) ld a, (gsava) ; restore a register reti ; return pc l pc h psw l psw h at acceptance of an interrupt pc l pc h psw l psw h a w pc l pc h psw l psw h b-5 b-4 b-3 b-2 b-1 b address (example) sp sp sp sp at execution of push instruction at execution of pop instruction at execution of reti instruction
page 33 TMP88FW45FG figure 3-4 saving/restoring general-purpose r egisters under interrupt processing 3.3.3 interrupt return interrupt return instructions [reti]/[retn] perform as follows. interrupt requests are sampled during the final cycle of the instruction being executed. thus, the next inter- rupt can be accepted immediat ely after the interrupt retu rn instruction is executed. note: when the interrupt processing time is longer than t he interrupt request generation time, the interrupt service task is performed but not the main task. [reti] maskable interrupt return [retn] non-maskable interrupt return 1. the contents of the program counter and the program status word are restored from the stack. 2. the stack pointer is incremented 5 times. 3. the interrupt master enable flag is set to "1". 4. the interrupt nesting counter is decremented, and the interrupt nesting flag is changed. 1. the contents of the program counter and the program status word are restored from the stack. 2. the stack pointer is incremented 5 times. 3. the interrupt master enable flag is set to "1" only when a non-maskable interrupt is accepted in interrupt enable status. however, the interrupt master enable flag remains at "0" when so clear by an interrupt service program. 4. the interrupt nesting counter is decremented, and the interrupt nesting flag is changed. main task interrupt acceptance interrupt return interrupt service task saving registers restoring registers main task bank m interrupt acceptance interrupt return interrupt service task switch to bank n automatically restore to bank m automatically by [reti]/[retn] bank m bank n switch to bank n by ld, rbs and n instruction (a) saving/restoring by register bank changeover (b) saving/restoring general-purpose registers using push/pop data transfer instruction bank m
page 34 3. interrupt control circuit 3.4 software interrupt (intsw) TMP88FW45FG 3.4 software interrupt (intsw) executing the swi instruction generates a software interr upt and immediately starts interrupt processing (intsw is highest prioritized interrupt). however, if processing of a non-maskable inerrupt is already underway, executing the swi instruction will not generate a software interrupt but will result in the same operation as the nop instruc- tion. use the swi instruction only for detection of the address error or for debugging. 3.4.1 address error detection ffh is read if for some cause such as noise the cpu attempts to fetch an instruction from a non-existent memory address during single chip mode. code ffh is th e swi instruction, so a software interrupt is gener- ated and an address error is detect ed. the address error detection range can be further expanded by writing ffh to unused areas of the program memory. address trap reset is generated in case that an instruction is fetched from ram, dbr or sfr areas. 3.4.2 debugging debugging efficiency can be increased by placing the swi instruction at the software break point setting address.
page 35 TMP88FW45FG 3.5 external interrupts the TMP88FW45FG has 5 external interrupt inputs. these inputs are equipped with digital noise reject circuits (pulse inputs of less than a certa in time are elimin ated as noise). edge selection is also possible with int1,int2 and int4. the int0 /p10 pin can be configured as either an exter- nal interrupt input pin or an input/output port, and is configured as an input port during reset. edge selection, and noise reject control and int0 /p10 pin function selection are performed by the external inter- rupt control register (eintcr). note 1: in normal or idle mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "signal establishment time" from the input si gnal's edge to set the interrupt latch. (1) int1 pin 49/fc [s] ( at eintcr< int1nc> = "1") , 193/fc [s] ( at eintcr = "0") (2) int2 , 4 pins 25/fc [s] note 2: when eintcr = "0", il3 is not set even if a falling edge is detected on the int0 pin input. note 3: when a pin with more than one function is used as an out put and a change occurs in data or input/output status, an inter - rupt request signal is generated in a pseudo manner. in this ca se, it is necessary to perform appropriate processing such as disabling the interrupt enable flag. source pin sub-pin enable conditions release edge (level) digital noise reject int0 int0 p10 imf + ef3 + int0en=1 falling edge pulses of less than 2/fc [s] are eliminated as noise. pulses of 6/fc [s ] or more are considered to be signals. (at cgcr=0). int1 int1 p11 imf + ef5 = 1 falling edge or rising edge pulses of less than 15/fc or 63/fc [s] are elimi- nated as noise. pulses of 48/fc or 192/fc [s] or more are considered to be signals. (at cgcr=0). int2 int2 p12/tc1 imf + ef29 = 1 pulses of less than 7/fc [s] are eliminated as noise. pulses of 24/fc [s] or more are considered to be signals.(at cgcr=0). int4 int4 p22/tc4 imf + ef31 = 1 int5 int5 p20/ stop imf + ef15 = 1 falling edge pulses of less than 2/fc [s] are eliminated as noise. pulses of 6/fc [s ] or more are considered to be signals.
page 36 3. interrupt control circuit 3.5 external interrupts TMP88FW45FG note 1: fc: high-frequency clock [hz], *: don?t care note 2: when the external interrupt control register (eintcr) is overwritten, the noise canceller may not operate normally. it i s recommended that external interrupts are disabl ed using the interrupt enable register (eir). note 3: the maximum time from modifying eintcr until a noise reject time is changed is 2 6 /fc. note 4: in case reset pin is released while the state of int4 pin keeps "h" level, the external interrupt 4 request is not generated even if the int4 edge select(eintcr) is spec ified as "h" level. the rising edge is needed after reset pin is released. external interrupt control register eintcr76543210 (0037h) int1nc int0en int4es - int2es int1es (initial value: 0000 *00*) int1nc noise reject time select 0: pulses of less than 63/fc [s] are eliminated as noise 1: pulses of less than 15/fc [s] are eliminated as noise r/w int0en p10/ int0 pin configuration 0: p10 input/output port 1: int0 pin (port p10 should be set to an input mode) r/w int4 es int4 edge select 00: rising edge 01: falling edge 10: rising edge and falling edge 11: h level r/w int2 es int2 edge select 0: rising edge 1: falling edge r/w int1 es int1 edge select
page 37 TMP88FW45FG 4. special function register the TMP88FW45FG adopts the memory mapped i/o syst em, and all peripheral control and transfers are per- formed through the special function register (sfr) or the data buffer register (dbr,ebr). the sfr is mapped on address 0000h to 003fh, dbr is mappped on address 1f 80h to 1fffh and ebr is ma ppped on address 1f70h to 1f7fh. this chapter shows the arrang ement of the special function register (sfr ) and data buffer register (dbr,ebr) for TMP88FW45FG. 4.1 sfr address read write 0000h p0dr 0001h p1dr 0002h p2dr 0003h p3dr 0004h p4dr 0005h p5dr 0006h p6dr 0007h p7dr 0008h p8dr 0009h p9dr 000ah p0cr 000bh p1cr 000ch hpwmcr 000dh hpwmdr0 000eh hpwmdr1 000fh tc1cr 0010h tc1dral 0011h tc1drah 0012h tc1drbl 0013h tc1drbh 0014h ctc1cr1 0015h ctc1cr2 0016h - ctc1drl 0017h - ctc1drh 0018h reserved 0019h reserved 001ah tc4cr 001bh tc4dr 001ch tc3dra 001dh tc3drb - 001eh tc3cr 001fh reserved 0020h tc5cr 0021h tc6cr 0022h ttreg5 0023h ttreg6 0024h pwreg5
page 38 4. special function register 4.1 sfr TMP88FW45FG note 1: do not access reserved areas by the program. note 2: ? ; cannot be accessed. note 3: write-only registers and interrupt latches cannot use the read-modify-write instructions (bit manipulation instructions such as set, clr, etc. and logical operation instructions such as and, or, etc.). 0025h pwreg6 0026h adccra 0027h adccrb 0028h adcdrl - 0029h adcdrh - 002ah eirc 002bh ilc 002ch eire 002dh eird 002eh ile 002fh ild 0030h cgcr 0031h reserved 0032h reserved 0033h reserved 0034h - wdtcr1 0035h - wdtcr2 0036h tbtcr 0037h eintcr 0038h syscr1 0039h syscr2 003ah eirl 003bh eirh 003ch ill 003dh ilh 003eh pswl 003fh pswh address read write
page 39 TMP88FW45FG 4.2 ebr note 1: do not access reserved areas by the program. note 2: ? ; cannot be accessed. note 3: write-only registers and interrupt latches cannot use the read-modify-write instructions (bit manipulation instructions such as set, clr, etc. and logical operation instructions such as and, or, etc.). address read write 1f70h uartsr2 uartcr21 1f71h ? uartcr22 1f72h rdbuf2 tdbuf2 1f73h reserved 1f74h reserved 1f75h reserved 1f76h reserved 1f77h reserved 1f78h reserved 1f79h reserved 1f7ah reserved 1f7bh reserved 1f7ch reserved 1f7dh reserved 1f7eh reserved 1f7fh reserved
page 40 4. special function register 4.3 dbr TMP88FW45FG 4.3 dbr address pmd ch read write 1f80h p0ode 1f81h ? 1f82h ? 1f83h p3ode 1f84h p4ode 1f85h p5ode 1f86h p8ode 1f87h p9ode 1f88h ? 1f89h p3cr 1f8ah p4cr 1f8bh p5cr 1f8ch p6cr 1f8dh p7cr 1f8eh p8cr 1f8fh p9cr 1f90h uartsel 1f91h uartsr uartcr1 1f92h ? uartcr2 1f93h rdbuf tdbuf 1f94h ? atas 1f95h ? atkey 1f96h ? siocr1 1f97h siosr siocr2 1f98h siobr0 1f99h siobr1 1f9ah siobr2 1f9bh siobr3 1f9ch siobr4 1f9dh siobr5 1f9eh siobr6 1f9fh siobr7 1fa0h for pmd ch.1 pdcra 1fa1h for pmd ch.1 pdcrb 1fa2h for pmd ch.1 pdcrc ? 1fa3h for pmd ch.1 sdreg 1fa4h for pmd ch.1 mtcra 1fa5h for pmd ch.1 mtcrb 1fa6h for pmd ch.1 mcapl ? 1fa7h for pmd ch.1 mcaph ? 1fa8h for pmd ch.1 cmp1l 1fa9h for pmd ch.1 cmp1h 1faah for pmd ch.1 cmp2l 1fabh for pmd ch.1 cmp2h 1fach for pmd ch.1 cmp3l 1fadh for pmd ch.1 cmp3h 1faeh for pmd ch.1 mdcra 1fafh for pmd ch.1 mdcrb
page 41 TMP88FW45FG 1fb0h for pmd ch.1 emgcra 1fb1h for pmd ch.1 emgcrb 1fb2h for pmd ch.1 mdoutl 1fb3h for pmd ch.1 mdouth 1fb4h for pmd ch.1 mdcntl ? 1fb5h for pmd ch.1 mdcnth ? 1fb6h for pmd ch.1 mdprdl 1fb7h for pmd ch.1 mdprdh 1fb8h for pmd ch.1 cmpul 1fb9h for pmd ch.1 cmpuh 1fbah for pmd ch.1 cmpvl 1fbbh for pmd ch.1 cmpvh 1fbch for pmd ch.1 cmpwl 1fbdh for pmd ch.1 cmpwh 1fbeh for pmd ch.1 dtr 1fbfh for pmd ch.1 ? emgrel 1fc0h for pmd ch.1 edcra 1fc1h for pmd ch.1 edcrb 1fc2h for pmd ch.1 edsetl 1fc3h for pmd ch.1 edseth 1fc4h for pmd ch.1 eldegl 1fc5h for pmd ch.1 eldegh 1fc6h for pmd ch.1 ampl 1fc7h for pmd ch.1 amph 1fc8h for pmd ch.1 edcapl ? 1fc9h for pmd ch.1 edcaph ? 1fcah for pmd ch.1 ? wfmdr 1fcbh ? 1fcch reserved 1fcdh reserved 1fceh reserved 1fcfh reserved 1fd0h for pmd ch.2 pdcra 1fd1h for pmd ch.2 pdcrb 1fd2h for pmd ch.2 pdcrc ? 1fd3h for pmd ch.2 sdreg 1fd4h for pmd ch.2 mtcra 1fd5h for pmd ch.2 mtcrb 1fd6h for pmd ch.2 mcapl ? 1fd7h for pmd ch.2 mcaph ? 1fd8h for pmd ch.2 cmp1l 1fd9h for pmd ch.2 cmp1h 1fdah for pmd ch.2 cmp2l 1fdbh for pmd ch.2 cmp2h 1fdch for pmd ch.2 cmp3l 1fddh for pmd ch.2 cmp3h 1fdeh for pmd ch.2 mdcra 1fdfh for pmd ch.2 mdcrb 1fe0h for pmd ch.2 emgcra 1fe1h for pmd ch.2 emgcrb 1fe2h for pmd ch.2 mdoutl address pmd ch read write
page 42 4. special function register 4.3 dbr TMP88FW45FG note 1: do not access reserved areas by the program. note 2: ? ; cannot be accessed. note 3: write-only registers and interrupt latches cannot use the read-modify-write instructions (bit manipulation instructions such as set, clr, etc. and logical operation instructions such as and, or, etc.). 1fe3h for pmd ch.2 mdouth 1fe4h for pmd ch.2 mdcntl ? 1fe5h for pmd ch.2 mdcnth ? 1fe6h for pmd ch.2 mdprdl 1fe7h for pmd ch.2 mdprdh 1fe8h for pmd ch.2 cmpul 1fe9h for pmd ch.2 cmpuh 1feah for pmd ch.2 cmpvl 1febh for pmd ch.2 cmpvh 1fech for pmd ch.2 cmpwl 1fedh for pmd ch.2 cmpwh 1feeh for pmd ch.2 dtr 1fefh for pmd ch.2 ? emgrel 1ff0h for pmd ch.2 edcra 1ff1h for pmd ch.2 edcrb 1ff2h for pmd ch.2 edsetl 1ff3h for pmd ch.2 edseth 1ff4h for pmd ch.2 eldegl 1ff5h for pmd ch.2 eldegh 1ff6h for pmd ch.2 ampl 1ff7h for pmd ch.2 amph 1ff8h for pmd ch.2 edcapl ? 1ff9h for pmd ch.2 edcaph ? 1ffah for pmd ch.2 ? wfmdr 1ffbh ? 1ffch reserved 1ffdh reserved 1ffeh spcr 1fffh flscr address pmd ch read write
page 43 TMP88FW45FG 5. input/output ports the TMP88FW45FG contains 10 input/output ports comprised of 71 pins. all output ports contain a latch, and the output data ther efore are retained by the latch. but none of the input ports have a latch, so it is desirable that the input data be retain ed externally until it is read out, or read several times before being processed. figure 5-1 shows input/output timing. the timing at which external data is read in from input/out put ports is s1 state in the read cycle of instruction exe- cution. because this timing cannot be recognized from the out side, transient input data such as chattering needs to be dealt with in a program. the timing at which data is forwarded to input/output ports is s2 state in the write cycle of instruction execution. note: the read/write cycle positi ons vary depending on instructions. figure 5-1 example of input/output timing when an operation is performed for read from any input/output port except programmable input/output ports, whether the input value of the pin or the content of the output latch is read depends on the instruction executed, as shown below. primary function secondary functions port p0 4-bit i/o port timer/counter input, serial interface input/output, and high-speed pwm out- put port p1 8-bit i/o port external interrupt input, timer/counter input/output, divider output, and motor control circuit input port p2 3-bit i/o port external interrupt input, timer/counter input/output, and stop mode release signal input port p3 8-bit i/o port motor control input/output port p4 8-bit i/o port timer/counter output, serial interface input/output, motor control circuit input and serial prom mode control input port p5 8-bit i/o port motor control circuit input/output port p6 8-bit i/o port analog input and motor control circuit output port p7 8-bit i/o port analog input and motor control circuit output port p8 8-bit i/o port serial interface input/output port p9 8-bit i/o port !" #" $" %" !" #" $" %" !" #" $" % & ' !" #" $" %" !" #" $" %" !" #" $" % ( & (
page 44 5. input/output ports TMP88FW45FG 1. instructions which read the content of the output latch - xch r, (src) - set/clr/cpl (src).b - set/clr/cpl (pp).g - ld (src).b, cf - ld (pp).b, cf - xch cf, (src). b - add/addc/sub/subb/and/or/xor (src), n - add/addc/sub/subb/and/or/xor (src), (hl) instructions, the (src) side thereof - mxor (src), m 2. instructions which read the input value of the pin any instructions other than those listed above and add/addc/sub/subb/and/or/xor (src),(hl) instructions, the (hl) side thereof
page 45 TMP88FW45FG 5.1 port p0 (p03 to p00) port p0 is a 4-bit input/output port shared with serial in terface input/output. this port is switched between input and output modes using the p0 port input/output control regi ster (p0cr). when reset, the p0cr register is initialized to 0, with the p0 port set for input mode. also, the output latch (p0dr) is initialized to 0 when reset. the p0 port contains bitwise programmable open-drain cont rol. the p0 port open-drain control register (p0ode) is used to select open-drain or tri-state mode for the port. when reset, the p0ode register is initialized to 0, with tri- state mode selected for the port. figure 5-2 port p0 note 1: even when open-drain mode is selected, the protecti ve diode remains connected. therefore, do not apply voltages exceeding v dd . note 2: read-modify-write (rmw) operation executes at open-drain mode is selected, read out the output latch states. when any other instruction is executed, external pin states is read out. note 3: *: don?t care p0 port input/output registers p0dr (00000h) 76543210 p03 hpwm1 p02 hpwm0 p01 tc6o txd2 p00 tc6i rxd2 read/write (initial value: **** 0000) tc6o: pdo6 , pwm6 , ppg6 p0cr (0000ah) 76543210 (initial value: **** 0000) p0cr p0 port input/output control (specify bitwise) 0: input mode 1: output mode r/w p0ode (01f80h) 76543210 (initial value: **** 0000) p0ode p0 port open-drain control (specify bitwise) 0: tri-state 1: open-drain r/w

page 46 5. input/output ports TMP88FW45FG 5.2 port p1 (p17 to p10) port p1 is an 8-bit input/output port shared with external interrupt input, timer/counter input/output, and divider output. this port is switched between input and output modes using the p1 port input/output control register (p1cr). when reset, the p1cr register is initialized to 0, with the p1 port set for input mode. also, the output latch (p1dr) is initialized to 0 when reset. figure 5-3 port p1 p1 port input/output registers p1dr (00001h) 76543210 p17 pdw2 p16 pdv2 p15 pdu2 p14 ppg1 tc5o p13 dvo tc5i p12 int2 tc1 p11 int1 p10 int0 read/write (initial value: 0000 0000) tc5o: pdo5 , pwm5 p1cr (0000bh) 76543210 (initial value: 0000 0000) p1cr p1 port input/output control (specify bitwise) 0: input mode 1: output mode r/w

page 47 TMP88FW45FG 5.3 port p2 (p22 to p20) port p2 is a 3-bit input/output port shared with external interrupt input and stop mode release signal. when using this port as these functional pins or an input port, set the ou tput latch to 1. when reset, the output latch is initialized to 1. we recommend using the p20 pin as external interrupt inpu t, stop mode release signal input, or input port. when using this port as an output port, note that the interrupt la tch is set by a falling edge of output pulse. and note that outputs on this port during st op mode go to a high-imp edance state even if syscr1 is set "1" , because p20 port is also used as stop port. when a read instruction is executed on p2 port, in determinate values are read in from bits 7 to 3. when any read-modify-wr ite instruction is executed on p2 port, the c ontent of the output la tch is read out. when any other instruction is executed, th e external pin st ate is read out. figure 5-4 port p2 note 1: when a read instruction is executed on p2 port, indeterminate values are read in from bits 7 to 3. note 2: port p20 is used as stop pin. therefore, when stop mode is started, syscr1 does not affect to p20, and p20 becomes high-z mode. note 3: *: don?t care p2 port input/output registers p2dr (00002h) 76543210 p22 tc4 int4 pwm4 pdo4 p21 tc3 p20 int 5 stop read/write (initial value: **** *111)

page 48 5. input/output ports TMP88FW45FG 5.4 port p3 (p37 to p30) port p3 is an 8-bit input/output port. this port is switched between input and output modes using the p3 port input/ output control register (p3cr). when rese t, the p3cr register is initialized to 0, with the p3 port set for input mode. also, the output latch (p3dr) is initialized to 0 when reset. the p3 port contains bitwise programmable open-drain control. the p3 port open-drain control register (p3ode) is used to select open-drain or tri-state mode fo r the port. when reset, the p3ode register is initialized to 0, with tri-state mode selected for the port. figure 5-5 port p3 note 1: even when open-drain mode is selected, the protecti ve diode remains connected. therefore, do not apply voltages exceeding v dd . note 2: read-modify-write (rmw) operation executes at open-drain mode is selected, read out the output latch states. when any other instruction is executed, external pin states is read out. note 3: for pmd circuit output, set the p3dr output latch to 1. note 4: when using p3 port as an input/ output port, disable the emg1 circuit. p3 port input/output registers p3dr (00003h) 76543210 p37 cl1 p36 emg1 p35 u1 p34 v1 p33 w1 p32 x1 p31 y1 p30 z1 read/write (initial value: 0000 0000) p3cr (01f89h) 76543210 (initial value: 0000 0000) p3cr p3 port input/output control (specify bitwise) 0: input mode 1: output mode r/w p3ode (01f83h) 76543210 (initial value: 0000 0000) p3ode p3 port open-drain control (specify bitwise) 0: tri-state 1: open-drain r/w

page 49 TMP88FW45FG 5.5 port p4 (p47 to p40) port p4 is an 8-bit input/output port shared with serial interface input/output and serial prom mode control input. this port is switched between input and output modes usi ng the p4 port input/output control register (p4cr). when reset, the p4cr register is initialized to 0, with the p4 po rt set for input mode. also, the output latch (p4dr) is ini- tialized to 0 when reset. the p4 port contains bitwise programmable open-drain cont rol. the p4 port open-drain control register (p4ode) is used to select open-drain or tri-state mode for the port. when reset, the p4ode register is initialized to 0, with tri- state mode selected for the port. figure 5-6 port p4 note 1: even when open-drain mode is selected, the protecti ve diode remains connected. therefore, do not apply voltages exceeding v dd . note 2: read-modify-write (rmw) operation executes at open-drain mode is selected, read out the output latch states. when any other instruction is executed, external pin states is read out. note 3: when using the 16-bit timer (ctc) as an ordinary timer, set p47 (ctc) for output mode. p4 port input/output registers p4dr (00004h) 76543210 p47 ctc p46 ppg2 p45 so txd1 p44 si rxd1 boot p43 sck p42 pdu1 p41 pdv1 p40 pdw1 (initial value: 0000 0000) p4cr (01f8ah) 76543210 (initial value: 0000 0000) p4cr p4 port input/output control (specify bitwise) 0: input mode 1: output mode r/w p4ode (01f84h) 76543210 (initial value: 0000 0000) p4ode p4 port open-drain control (specify bitwise) 0: tri-state 1: open-drain r/w

page 50 5. input/output ports TMP88FW45FG 5.6 port p5 (p57 to p50) port p5 is an 8-bit input/output port. this port is switc hed between input and output modes using the p5 port input/ output control register (p5cr). when reset, the p5cr register is initialized to 0, with the p5 port set for input mode. also, the output latch (p5dr) is initialized to 0 when reset. the p5 port contains bitwise programmable open-drain cont rol. the p5 port open-drain control register (p5ode) is used to select open-drain or tri-state mode for the port. when reset, the p5ode register is initialized to 0, with tri- state mode selected for the port. figure 5-7 port p5 note 1: even when open-drain mode is selected, the protecti ve diode remains connected. therefore, do not apply voltages exceeding v dd . note 2: read-modify-write (rmw) operation executes at open-drain mode is selected, read out the output latch states. when any other instruction is executed, external pin states is read out. note 3: for pmd circuit output, set the p5dr output latch to 1. note 4: when using p5 port as an input/ output port, disable the emg2 circuit. p5 port input/output registers p5dr (00005h) 76543210 p57 z2 p56 y2 p55 x2 p54 w2 p53 v2 p52 u2 p51 emg2 p50 cl2 read/write (initial value: 0000 0000) p5cr (01f8bh) 76543210 (initial value: 0000 0000) p5cr p5 port input/output control (specify bitwise) 0: input mode 1: output mode r/w p5ode (01f85h) 76543210 (initial value: 0000 0000) p5ode p5 port open-drain control (specify bitwise) 0: tri-state 1: open-drain r/w

page 51 TMP88FW45FG 5.7 port p6 (p67 to p60) port p6 is an 8-bit input/output port shared with ad co nverter analog input. this port is switched between input and output modes using the p6 port input/output control register (p6cr), p6 port output latch (p6dr), and adc- cra. when reset, the p6cr register and the p6dr output latch are initialized to 0 while adc- cra is set to 1, so that p67 to p60 have their inpu ts fixed low (= 0). when using the p6 port as an input port, set the corresponding bits for input mode (p6cr = 0, p6dr = 1). the reason why the output latch = 1 is because it is necessary to prevent curren t from flowing into the shared data in put circuit. when us ing the port as an output port, set the p6cr register's corresponding bits to 1. when using the port for analog input, set the corre- sponding bits for analog input (p6cr = 0, p6dr = 0). then set adccra = 0, and ad conversion will start. the ports used for analog input must have their output latches set to 0 beforehand. the actual input channels for ad conversion are selected using adccra. although the bits of p6 port not used for analog input can be used as input/output ports, do not execute output instructions on these ports during ad conversion. this is necessary to ma intain the accuracy of ad conversion. also, do not apply rapidly changing signals to ports adjacent to analog input during ad conversion. if an input instruction is executed while the p6dr output latc h is cleared to 0, data ?0? is read in from said bits. figure 5-8 port p6

! " # $ %& &'%# ( ) ( ) % !
page 52 5. input/output ports TMP88FW45FG note 1: the pins used for analog input cannot be set for output m ode (p6cr = 1) because they become shorted with external sig- nals. note 2: when a read instruction is executed on bits of this por t which are set for analog input mode, data "0" is read in. note 3: for dbout1 output, set the p6dr (p67) output latch to 1. note 4: when using this port in input mode (including analog input), do not use bit manipulating or ot her read-modify-write inst ruc- tions. when a read instruction is executed on the bits of this port that are set for input, the contents of the pins are read i n, so that if a read-modify-write instruction is executed, t heir output latches may be rewritten, making the pins unable to accept input. (a read-modify-write instruct ion first reads data from all of the eight bits and after modifying them (bit manip- ulation), writes data for all of the eight bits to the output latches.) p6 port input/output registers p6dr (00006h) 76543210 p67 ain7 dbout1 p66 ain6 p65 ain5 p64 ain4 p63 ain3 p62 ain2 p61 ain1 p60 ain0 read/write (initial value: 0000 0000) p6cr (01f8ch) 76543210 (initial value: 0000 0000) p6cr p6 port input/output control (specify bitwise) ainds = 1 (when not using ad) ainds = 0 (when using ad) r/w p6dr = ?0? p6dr = ?1? p6dr = ?0? p6dr = ?1? 0 inputs fixed to 0 input mode analog input mode (note2) input mode 1 output mode
page 53 TMP88FW45FG 5.8 port p7 (p77 to p70) port p7 is an 8-bit input/output port shared with ad co nverter analog input. this port is switched between input and output modes using the p7 port input/output control register (p7cr), p7 port output latch (p7dr), and adc- cra. when reset, the p7cr register and the p7dr output latch are initialized to 0 while adc- cra is set to 1, so that p77 to p70 have their inpu ts fixed low (= 0). when using the p7 port as an input port, set the corresponding bits for input mode (p7cr = 0, p7dr = 1). the reason why the output latch = 1 is because it is necessary to prevent curren t from flowing into the shared data in put circuit. when us ing the port as an output port, set the p7cr register's corresponding bits to 1. when using the port for analog input, set the corre- sponding bits for analog input (p7cr = 0, p7dr = 0). then set adccra = 0, and ad conversion will start. the ports used for analog input must have their output latches set to 0 beforehand. the actual input channels for ad conversion are selected using adccra. although the bits of p7 port not used for analog input can be used as input/output ports, do not execute output instructions on these ports during ad conversion. this is necessary to ma intain the accuracy of ad conversion. also, do not apply rapidly changing signals to por ts adjacent to analog input during ad conversion. if an input instruction is executed while the p7dr output latch is cleared to 0, data ?0? is read in from said bits. figure 5-9 port p7

! " # $% %&$" ' ( ' ( $
page 54 5. input/output ports TMP88FW45FG note 1: the pins used for analog input cannot be set for output m ode (p7cr = 1) because they become shorted with external sig- nals. note 2: when a read instruction is executed on bits of this por t which are set for analog input mode, data "0" is read in. note 3: for dbout2 output, set the p7dr (p77) output latch to 1. note 4: when using this port in input mode (including analog input), do not use bit manipulating or ot her read-modify-write inst ruc- tions. when a read instruction is executed on the bits of this port that are set for input, the contents of the pins are read i n, so that if a read-modify-write instruction is executed, t heir output latches may be rewritten, making the pins unable to accept input. (a read-modify-write instruct ion first reads data from all of the eight bits and after modifying them (bit manip- ulation), writes data for all of the 8 bits to the output latches.) p7 port input/output registers p7dr (00007h) 76543210 p77 ain15 dbout2 p76 ain14 p75 ain13 p74 ain12 p73 ain11 p72 ain10 p71 ain9 p70 ain8 read/write (initial value: 0000 0000) p7cr (01f8dh) 76543210 (initial value: 0000 0000) p7cr p7 port input/output control (specify bitwise) ainds = 1 (when not using ad) ainds = 0 (when using ad) r/w p7dr = ?0? p7dr = ?1? p7dr = ?0? p7dr = ?1? 0 inputs fixed to 0 input mode analog input mode (note2) input mode 1 output mode
page 55 TMP88FW45FG 5.9 port p8 (p87 to p80) port p8 is an 8-bit input/output port. this port is switc hed between input and output modes using the p8 port input/ output control register (p8cr). when reset, the p8cr register is initialized to 0, with the p8 port set for input mode. also, the output latch (p8dr) is initialized to 0 when reset. the p8 port contains bitwise programmable open-drain cont rol. the p8 port open-drain control register (p8ode) is used to select open-drain or tri-state mode for the port. when reset, the p8ode register is initialized to 0, with tri- state mode selected for the port. figure 5-10 port p8 note 1: even when open-drain mode is selected, the protecti ve diode remains connected. therefore, do not apply voltages exceeding v dd . note 2: read-modify-write (rmw) operation executes at open-drain mode is selected, read out the output latch states. when any other instruction is executed, external pin states is read out. p8 port input/output registers p8dr (00008h) 76543210 p87 p86 p85 p84 p83 p82 p81 txd3 p80 rxd3 read/write (initial value: 0000 0000) p8cr (01f8eh) 76543210 (initial value: 0000 0000) p8cr p8 port input/output control (specify bitwise) 0: input mode 1: output mode r/w p8ode (01f86h) 76543210 (initial value: 0000 0000) p8ode p8 port open-drain control (specify bitwise) 0: tri-state 1: open-drain r/w output latch p8crj data output data input control output control input d q output latch p8cri data output data input p8i note: i = 7 ~ 2 d q control input value external input cr 1 0 1 0 0 0 0 1 p80, 81 note: j = 1 ~0
page 56 5. input/output ports TMP88FW45FG 5.10 port p9 (p97 to p90) port p9 is an 8-bit input/output port. this port is switc hed between input and output modes using the p9 port input/ output control register (p9cr). when reset, the p9cr register is initialized to 0, with the p9 port set for input mode. also, the output latch (p9dr) is initialized to 0 when reset. the p9 port contains bitwise programmable open-drain cont rol. the p9 port open-drain control register (p9ode) is used to select open-drain or tri-state mode for the port. when reset, the p9ode register is initialized to 0, with tri- state mode selected for the port. figure 5-11 port p9 note 1: even when open-drain mode is selected, the protecti ve diode remains connected. therefore, do not apply voltages exceeding v dd . note 2: read-modify-write (rmw) operation executes at open-drain mode is selected, read out the output latch states. when any other instruction is executed, external pin states is read out. p9 port input/output registers p9dr (00009h) 76543210 p97 p96 p95 p94 p93 p92 p91 p90 read/write (initial value: 0000 0000) p9cr (01f8fh) 76543210 (initial value: 0000 0000) p9cr p9 port input/output control (specify bitwise) 0: input mode 1: output mode r/w p9ode (01f87h) 76543210 (initial value: 0000 0000) p9ode p9 port open-drain control (specify bitwise) 0: tri-state 1: open-drain r/w

page 57 TMP88FW45FG 6. time base timer (tbt) and divider output ( dvo ) 6.1 time base timer the time base timer generates time base for key scanning, dynamic displaying, etc. it also provides a time base timer interrupt (inttbt). an inttbt ( time base timer interrupt ) is generated on the first falling edge of source clock ( the divider out- put of the timing generator which is selected by tbtck. ) after time base timer has been enabled. the divider is not cleared by the program; therefore, onl y the first interrupt may be generated ahead of the set interrupt period ( figure 6-2 ). the interrupt frequency (tbtck) must be selected with the time base timer disabled (tbten="0"). (the inter- rupt frequency must not be changed with the disble from the enable state.) both frequency selection and enabling can be performed simultaneously. figure 6-1 time base timer configuration figure 6-2 time base timer interrupt example :set the time base timer frequency to fc/2 16 [hz] and enable an inttbt interrupt. ld (tbtcr) , 00000010b ; tbtck 010 (freq. set) ld (tbtcr) , 00001010b ; tbten 1 (tbt enable) di set (eirl) . 6 ei fc/2 23 ,fc/2 24 fc/2 21 ,fc/2 22 fc/2 16 ,fc/2 17 fc/2 14 ,fc/2 15 fc/2 13 ,fc/2 14 fc/2 12 ,fc/2 13 fc/2 11 ,fc/2 12 fc/2 9 ,fc/2 10 tbtcr tbten tbtck 3 mpx source clock falling edge detector time base timer control register inttbt interrupt request source clock enable tbt interrupt period tbtcr inttbt interrupt request
page 58 6. time base timer (tbt) and divider output (dvo) 6.1 time base timer TMP88FW45FG time base timer is controled by time base timer control register (tbtcr). note 1: fc; high-frequency clock [hz], *; don't care note 2: always set "0" in bit4 on tbtcr register. time base timer control register 7 6543210 tbtcr (00036h) (dvoen) (dvock) 0 tbten tbtck (initial value: 0000 0000) tbten time base timer enable / disable 0: disable 1: enable tbtck time base timer interrupt frequency select : [hz] normal, idle mode r/w dv1ck=0 dv1ck=1 000 fc/2 23 fc/2 24 001 fc/2 21 fc/2 22 010 fc/2 16 fc/2 17 011 fc/2 14 fc/2 15 100 fc/2 13 fc/2 14 101 fc/2 12 fc/2 13 110 fc/2 11 fc/2 12 111 fc/2 9 fc/2 10 table 6-1 time base timer interrupt frequency ( example : fc = 20.0 mhz ) tbtck time base timer interrupt frequency [hz] normal, idle mode dv1ck = 0 dv1ck = 1 000 2.38 1.20 001 9.53 4.78 010 305.18 153.50 011 1220.70 610.35 100 2441.40 1220.70 101 4882.83 2441.40 110 9765.63 4882.83 111 39063.00 19531.25
page 59 TMP88FW45FG 6.2 divider output ( dvo ) approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. divider output is from dvo pin. figure 6-3 divider output the divider output is controlled by the time base timer control register (tbtcr). note 1: selection of divider output frequency (dvock) must be made while divider output is disabled (dvoen="0"). also, in other words, when changing the state of the divider output frequency from enabled (dvoen="1") to disable(dvoen="0"), do not change the setting of the divider output frequency. note 2: in case of using dvo output, set output mode by p1cr register after setting the related port output latch to "1" by p1dr register. note 3: fc; high-frequency clock [hz], *; don't care note 4: be sure to write "0" to tbtcr register bit 4. time base timer control register 7654 321 0 tbtcr (00036h) dvoen dvock "0" (tbten) (tbtck) (initial value: 0000 0000) dvoen divider output enable / disable 0: disable 1: enable r/w dvock divider output ( dvo ) frequency selection: [hz] normal, idle mode r/w dv1ck=0 dv1ck=1 00 fc/2 13 fc/2 14 01 fc/2 12 fc/2 13 10 fc/2 11 fc/2 12 11 fc/2 10 fc/2 11 tbtcr output latch port output latch mpx dvoen tbtcr dvo pin output dvock divider output control register (a) configuration (b) timing chart data output 2 a b c y d s d q dvo pin fc/2 13 ,fc/2 14 fc/2 12 ,fc/2 13 fc/2 11 ,fc/2 12 fc/2 10 ,fc/2 11
page 60 6. time base timer (tbt) and divider output (dvo) 6.2 divider output (dvo) TMP88FW45FG example : 2.44 khz pulse output (fc = 20.0 mhz) port setting ld (tbtcr) , 00000000b ; dvock "00" ld (tbtcr) , 10000000b ; dvoen "1" table 6-2 divider output frequency ( example : fc = 20.0 mhz ) dvock divider output frequency [hz] normal, idle mode dv1ck=0 dv1ck=1 00 2.4415 k 1.22075 k 01 4.8825 k 2.4415 k 10 9.765 k 4.8825 k 11 19.5325 k 9.765 k
page 61 TMP88FW45FG 7. watchdog timer (wdt) the watchdog timer is a fail-safe system to detect rapidl y the cpu malfunctions such as endless loops due to spu- rious noises or the deadlock conditions, and return the cpu to a sy stem recovery routine. the watchdog timer signal for detecting malfunctions can be programmed only once as ?r eset request? or ?pseudo nonmaskable interrupt request?. upon the reset releas e, this signal is initia lized to ?reset request?. when the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic inter- rupt. note: care must be taken in system des ign since the watchdog timer functions are not be operated completely due to effect of disturbing noise. 7.1 watchdog timer configuration figure 7-1 watchdog timer configuration 0034 h overflow wdt output internal reset binary counters wdtout writing clear code writing disable code wdten wdtt 2 0035 h watchdog timer control registers wdtcr1 wdtcr2 intwdt interrupt request interrupt request reset request reset release clock clear 1 2 controller q sr s r q selector fc/2 23 ,fc/2 24 fc/2 21 ,fc/2 22 fc/2 19 ,fc/2 20 fc/2 17 ,fc/2 18
page 62 7. watchdog timer (wdt) 7.2 watchdog timer control TMP88FW45FG 7.2 watchdog timer control the watchdog timer is controlled by the watchdog timer control registers (wdtcr1 and wdtcr2). the watch- dog timer is automatically enabled after the reset release. 7.2.1 malfunction detection me thods using the watchdog timer the cpu malfunction is detected, as shown below. 1. set the detection time, select the output, and clear the binary counter. 2. clear the binary counter repeatedly within the specified detection time. if the cpu malfunctions such as en dless loops or the deadlock condition s occur for some reason, the watch- dog timer output is activated by the binary-counter overflow unless the binary counters are cleared. when wdtcr1 is set to ?1? at this time, the reset request is generated and then internal hardware is initialized. when wdtcr1 is set to ?0?, a watchdog timer interrupt (intwdt) is generated. the watchdog timer temporarily stops counting in the stop mode including the warm-up or idle mode, and automatically restarts (continues counting) when the stop/idle mode is inactivated. note:the watchdog timer consists of an internal divider and a two-stage binary counter. when the clear code 4eh is written, only the binary counter is cleared, but not the internal divider . the minimum binary-counter overflow time, that depends on the timing at which the clear code (4eh) is written to the wdtcr2 register, may be 3/ 4 of the time set in wdtcr1. therefore, writ e the clear code using a cycle shorter than 3/4 of the time set to wdtcr1. example :setting the watchdog timer detection time to 2 21 /fc [s], and resetting the cpu malfunction detection ld (wdtcr2), 4eh : clears the binary counters. ld (wdtcr1), 00001101b : wdtt 10, wdtout 1 ld (wdtcr2), 4eh : clears the binary counters (always clears immediately before and after changing wdtt). within 3/4 of wdt detection time : : ld (wdtcr2), 4eh : clears the binary counters. within 3/4 of wdt detection time : : ld (wdtcr2), 4eh : clears the binary counters.
page 63 TMP88FW45FG note 1: after clearing wdtcr1 to ?0?, the program cannot set it to ?1?. note 2: fc: high-frequency clock [hz], *: don?t care note 3: wdtcr1 is a write-only register and must not be used with any of read-modify-write instructions. if wdtcr1 is read, a unknown data is read. note 4: to activate the stop mode, disable the watchdog timer or clear the counter immediately before entering the stop mode. after clearing the counter, clear the counter again immediately after the stop mode is inactivated. note 5: to clear wdtcr1, set the register in acco rdance with the procedures shown in ?7.2.3 watchdog timer dis- able?. note 6: if the watchdog timer is disabled during watchdog timer in terrupt processing, the watchdog timer interrupt will never be cleared. therefore, clear the watchdog timer ( set the clear co de (4eh) to wdtcr2 ) before disabling it, or disable the watchdog timer a sufficient time before it overflows. note 7: the watchdog timer consists of an internal divider and a two-stage binary counter. when clear code (4eh) is written, onl y the binary counter is cleared, not the internal divider. depending on the timing at which clear code (4eh) is written on the wdtcr2 register, the overflow time of the binary counter may be at minimum 3/4 of the time set in wdtcr1. thus, write the clear c ode using a shorter cycle than 3/4 of the time set in wdtcr1. note 1: the disable code is valid only when wdtcr1 = 0. note 2: *: don?t care note 3: the binary counter of the watchdog timer must not be cleared by the interrupt task. note 4: write the clear code (4eh) using a cycle shorter than 3/4 of the time set in wdtcr1. note 5: wdtcr2 is a write-only register and must not be used with any of read-modify-write instructions. if wdtcr2 is read, a unknown data is read. 7.2.2 watchdog timer enable setting wdtcr1 to ?1? enables the watc hdog timer. since wdtcr1 is initialized to ?1? during reset, the watchdog timer is enabled automatically after the reset release. watchdog timer control register 1 wdtcr1 (0034h) 76543210 wdten wdtt wdtout (initial value: **** 1001) wdten watchdog timer enable/disable 0: disable (writing the disable code to wdtcr2 is required.) 1: enable write only wdtt watchdog timer detection time [s] normal mode write only dv1ck = 0 dv1ck = 1 00 2 25 /fc 2 26 /fc 01 2 23 /fc 2 24 /fc 10 2 21 fc 2 22 fc 11 2 19 /fc 2 20 /fc wdtout watchdog timer output select 0: interrupt request 1: reset request write only watchdog timer control register 2 wdtcr2 (0035h) 76543210 (initial value: **** ****) wdtcr2 write watchdog timer control code 4eh: clear the watchdog timer binary counter (clear code) b1h: disable the watchdog timer (disable code) others: invalid write only
page 64 7. watchdog timer (wdt) 7.2 watchdog timer control TMP88FW45FG 7.2.3 watchdog timer disable to disable the watchdog timer, set the register in accordance with the fo llowing procedures . setting the reg- ister in other procedures causes a malfunction of the microcontroller. 1. set the interrupt master flag (imf) to ?0?. 2. set wdtcr2 to the clear code (4eh). 3. set wdtcr1 to ?0?. 4. set wdtcr2 to the disable code (b1h). note:while the watchdog timer is disabled, the binary counters of the watchdog timer are cleared. note: if the watchdog timer is disabled during watchdog timer inte rrupt processing, the watchdog ti mer interrupt will never be cleared. therefore, clear the watchdog timer ( set the clear c ode (4eh) to wdtcr2 ) before disabling it, or disable the watchdog timer a sufficient time before it overflows. 7.2.4 watchdog time r interrupt (intwdt) when wdtcr1 is cleared to ?0?, a watchdog timer interrupt request (intwdt) is generated by the binary-counter overflow. a watchdog timer interrupt is the non-maskable interr upt which can be accepted regardless of the interrupt master flag (imf). when a watchdog timer interrupt is generated while the other interrupt including a watchdog timer interrupt is already accepted, the new watchdog timer interrupt is processed immediately and the previous interrupt is held pending. therefore, if watchdog timer interrupts are generated continuously without execution of the retn instruction, too many levels of nesting may cause a malfunction of the microcontroller. to generate a watchdog timer interrupt, set the stack pointer before setting wdtcr1. example :disabling the watchdog timer di : imf 0 ld (wdtcr2), 04eh : clears the binary coutner ldw (wdtcr1), 0b101h : wdten 0, wdtcr2 disable code ei : imf 1 table 7-1 watchdog timer detection time (example: fc = 20 mhz) wdtt watchdog timer detection time[s] normal mode dv1ck = 0 dv1ck = 1 00 1.678 3.355 01 419.430 m 838.861 m 10 104.858 m 209.715 m 11 26.214 m 52.429 m
page 65 TMP88FW45FG 7.2.5 watchdog timer reset when a binary-counter overflow occurs while wdt cr1 is set to ?1?, a watchdog timer reset request is generated. when a watchdog timer reset request is generated, the internal hardware is reset. the reset time is maximum 24/fc [s] ( max. 1.2 s @ fc = 20 mhz). figure 7-2 watchdog timer interrupt and reset example :setting watchdog timer interrupt ld sp, 010bfh : sets the stack pointer ld (wdtcr1), 00001000b : wdtout 0 clock binary counter overflow intwdt interrupt request (wdtcr1= "0") 2 17 /fc 2 19 /fc [s] (wdtt=11b) write 4e h to wdtcr2 1 2 30 1 2 3 0 internal reset (wdtcr1= "1") a reset occurs
page 66 7. watchdog timer (wdt) 7.2 watchdog timer control TMP88FW45FG
page 67 TMP88FW45FG 8. 16-bit timercounter 1 (tc1) 8.1 configuration figure 8-1 timercounter 1 (tc1) :::? pin tc1 :w:?::? mett1 start capture clear source clock ppg output mode write to tc1cr 16-bit up-counter clear tc1drb selector tc1dra tc1cr tc1 control register match inttc1 interript tff1 acap1 tc1ck window mode set toggle q 2 toggle set clear q y a d b c s b a y s tc1s clear mppg1 ppg output mode internal reset s enable mcap1 s y a b tc1s 2 set clear command start decoder external trigger start edge detector note: function i/o may not operate depending on i/o port setting. for more details, see the chapter "i/o port". port (note) q pulse width measurement mode falling rising trigger external cmp 16-bit timer register a, b pulse width measurement mode port (note) fc/2 11 , fc/2 12 fc/2 7 , fc/2 8 fc/2 3 , fc/2 4
page 68 8. 16-bit timercounter 1 (tc1) 8.2 timercounter control TMP88FW45FG 8.2 timercounter control the timercounter 1 is controlled by the timercounter 1 control register (tc1cr) and two 16-bit timer registers (tc1dra and tc1drb). note 1: fc: high-frequency clock [hz] note 2: the timer register consists of two shift registers. a va lue set in the timer register becomes valid at the rising edge o f the first source clock pulse that occurs after the upper byte (t c1drah and tc1drbh) is written. therefore, write the lower byte and the upper byte in this order (it is recommended to write the register with a 16-bit acce ss instruction). writing only the lower byte (tc1dral and tc1drbl) does not enable the setting of the timer register. note 3: to set the mode, source clock, ppg output control and timer f/f control, write to tc1cr during tc1cr=00. set the timer f/f1 control until the firs t timer start after setting the ppg mode. note 4: auto-capture can be used only in t he timer, event counter, and window modes. timer register 1514131211109876543210 tc1dra (0011h, 0010h) tc1drah (0011h) tc1dral (0010h) (initial value: 1111 1111 1111 1111) read/write tc1drb (0013h, 0012h) tc1drbh (0013h) tc1drbl (0012h) (initial value: 1111 1111 1111 1111) r ead/write (write enabled only in the ppg output mode) timercounter 1 control register tc1cr (000fh) 76543210 tff1 acap1 mcap1 mett1 mppg1 tc1s tc1ck tc1m read/write (initial value: 0000 0000) tff1 timer f/f1 control 0: clear 1: set r/w acap1 auto capture control 0:auto-capture disable 1:auto-capture enable r/w mcap1 pulse width measure- ment mode control 0:double edge capture 1:single edge capture mett1 external trigger timer mode control 0:trigger start 1:trigger start and stop mppg1 ppg output control 0:continuous pulse generation 1:one-shot tc1s tc1 start control timer extrig- ger event win- dow pulse ppg r/w 00: stop and counter clear oooooo 01: command start o????o 10: rising edge start (ex-trigger/pulse/ppg) rising edge count (event) positive logic count (window) ? ooooo 11: falling edge start (ex-trigger/pulse/ppg) falling edge count (event) negative logic count (window) ? ooooo tc1ck tc1 source clock select [hz] normal, idle mode r/w dv1ck = 0 dv1ck = 1 00 fc/2 11 fc/2 12 01 fc/2 7 fc/2 8 10 fc/2 3 fc/2 4 11 external clock (tc1 pin input) tc1m tc1 operating mode select 00: timer/external trigger timer/event counter mode 01: window mode 10: pulse width measurement mode 11: ppg (programmable pulse generate) output mode r/w
page 69 TMP88FW45FG note 5: to set the timer registers, the following relationship must be satisfied. tc1dra > tc1drb > 1 (ppg output mode), tc1dra > 1 (other modes) note 6: set tc1cr to ?0? in the mode except ppg output mode. note 7: set tc1drb after setting tc1cr to the ppg output mode. note 8: when the stop mode is entered, the start control (tc1cr ) is cleared to ?00? automatically, and the timer stops. after the stop mode is exited, set the tc1cr to use the timer counter again. note 9: use the auto-capture function in the operative condition of tc1. a captured value may not be fixed if it's read after th e execution of the timer stop or auto-capture disable. read the capture value in a capture enabled condition. note 10:since the up-counter value is captured into tc1drb by the source clock of up-counter after setting tc1cr to "1". therefore, to read the captured value, wait at least one cycle of the internal source clock before reading tc1drb for the first time.
page 70 8. 16-bit timercounter 1 (tc1) 8.3 function TMP88FW45FG 8.3 function timercounter 1 has six types of operating modes: timer, external trigger timer, event counter, window, pulse width measurement, programmable pulse generator output modes. 8.3.1 timer mode in the timer mode, the up-counter counts up using the in ternal clock. when a match between the up-counter and the timer register 1a (tc1dra) va lue is detected, an inttc1 interrupt is generated and the up-counter is cleared. after being cleared, the up-c ounter restarts counting. setting tc 1cr to ?1? captures the up- counter value into the timer register 1b (tc1drb) wi th the auto-capture functi on. use the auto-capture function in the operative condition of tc1. a captured valu e may not be fixed if it's read after the execution of the timer stop or auto-capture disabl e. read the capture value in a cap ture enabled condition. since the up- counter value is captured into tc1drb by the source clock of up-counter after setting tc1cr to "1". therefore, to read the captured va lue, wait at least one cy cle of the internal sour ce clock before reading tc1drb for the first time. table 8-1 source clock for timercounter 1 (example: fc = 20 mhz) tc1ck normal, idle mode dv1ck = 0 dv1ck = 1 resolution [ s] maximum time setting [s] resolution [ s] maximum time setting [s] 00 102.4 6.7108 204.8 13.4216 01 6.4 0.4194 12.8 0.8388 10 0.5 26.214 m 0.8 52.428 m example 1 :setting the timer mode with source clock fc/2 11 [hz] and generating an interrupt 1 second later (fc = 20 mhz, cgcr = ?0?) ldw (tc1dra), 2625h ; sets the timer register (1 s 2 11 /fc = 2625h) di ; imf = ?0? set (eird). 2 ; enables inttc1 ei ; imf = ?1? ld (tc1cr), 00000000b ; selects the source clock and mode ld (tc1cr), 00010000b ; starts tc1 example 2 :auto-capture ld (tc1cr), 01010000b ; acap1 1 : : ; wait at least one cycle of the internal source clock ld wa, (tc1drb) ; reads the capture value
page 71 TMP88FW45FG figure 8-2 timer mode timing chart match detect acap1 tc1drb tc1dra inttc1 interruput request source clock counter source clock counter ? (a) timer mode (b) auto-capture ? 7 6 345 0 timer start 12 3 2 1 4 0 counter clear capture n + 1 n n n m + 2 m + 1 m m capture m + 2 m + 1 n + 1 n m ? 1 m ? 1 m ? 2 n ? 1 n ? 1 n ? 1
page 72 8. 16-bit timercounter 1 (tc1) 8.3 function TMP88FW45FG 8.3.2 external trigger timer mode in the external trigger timer mode, the up-counter starts counting by the input pulse triggering of the tc1 pin, and counts up at the edge of the internal clock. for the trigger edge used to start counting, either the rising or falling edge is defined in tc1cr. ? when tc1cr is set to ?1? (trigger st art and stop) when a match between the up-counter and the tc1dra value is detected after the timer starts, the up-counter is cleared and halted and an inttc1 interrupt request is generated. if the edge opposite to trigger edge is detected before detecting a match between the up-counter and the tc1dra, the up-counter is cleared and ha lted without generating an interrupt request. therefore, this mode can be used to det ect exceeding the specified pulse by interrupt. after being halted, the up-count er restarts counting when th e trigger edge is detected. ? when tc1cr is set to ?0? (trigger start) when a match between the up-counter and the tc1dra value is detected after the timer starts, the up-counter is cleared and halted and an inttc1 interrupt request is generated. the edge opposite to the trigger edge has no effect in count up. the trigger edge for the next count- ing is ignored if detecting it before detectin g a match between the up-counter and the tc1dra. since the tc1 pin input has the noise rejection, pulses of 4/fc [s] or less are rejected as noise. a pulse width of 12/fc [s] or more is required to ensure edge detection. example 1 :generating an interrupt 1 ms after the rising edge of the input pulse to the tc1 pin (fc =20 mhz, cgcr = ?1?) ldw (tc1dra), 007dh ; 1ms 2 7 /fc = 7dh di ; imf = ?0? set (eird). 2 ; enables inttc1 interrupt ei ; imf = ?1? ld (tc1cr), 00001000b ; selects the source clock and mode ld (tc1cr), 00111000b ; starts tc1 external trigger, mett1 = 0 example 2 :generating an interrupt when the low-level pulse with 4 ms or more width is input to the tc1 pin (fc =20 mhz, cgcr = ?1?) ldw (tc1dra), 0138h ; 4 ms 2 8 /fc = 0138h di ; imf = ?0? set (eird). 2 ; enables inttc1 interrupt ei ; imf = ?1? ld (tc1cr), 00000100b ; selects the source clock and mode ld (tc1cr), 01110100b ; starts tc1 external trigger, mett1 = 0
page 73 TMP88FW45FG figure 8-3 external tri gger timer mode timing chart inttc1 interrupt request source clock up-counter tc1dra tc1 pin input inttc1 interrupt request source clock up-counter tc1dra tc1 pin input 0 at the rising edge (tc1s = 10) at the rising edge (tc1s = 10) (a) trigger start (mett1 = 0) count start match detect count start 0 1 2 3 4 2 3 n (b) trigger start and stop (mett1 = 1) count start count start 0 1 2 3 m 0 n n 0 count clear note: m < n count clear 1 2 3 1 n m ? 1 n ? 1 match detect count clear
page 74 8. 16-bit timercounter 1 (tc1) 8.3 function TMP88FW45FG 8.3.3 event counter mode in the event counter mode, the up-counter counts up at the edge of the input pulse to the tc1 pin. either the rising or falling edge of the input pulse is se lected as the count up edge in tc1cr. when a match between the up-counter and the tc1dra va lue is detected, an inttc1 interrupt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counting at each edge of the input pulse to the tc1 pin. since a match between the up-counter and the value set to tc1dra is detected at the edge opposite to the selected edge, an inttc1 interrupt request is generated after a match of the value at the edge opposite to the selected edge. two or more machine cycles are required for th e low-or high-level pulse input to the tc1 pin. setting tc1cr to ?1? captures the up-counter value into tc1drb with the auto capture function. use the auto-capture function in the operative condition of tc1. a captured value may not be fixed if it's read after the execution of the timer stop or auto-capture disable. read the captu re value in a captu re enabled condi- tion. since the up-counter value is captured into tc1drb by the source clock of up-counter after setting tc1cr to "1". theref ore, to read the captured value, wait at least one cycle of the internal source clock before reading tc1drb for the first time. figure 8-4 event c ounter mode timing chart table 8-2 input pulth width to tc1 pin minimum pulse width [s] normal, idle mode high-going 2 3 /fc low-going 2 3 /fc at the rising edge (tc1s = 10) inttc1 interrput request tc1 pin input up-counter tc1dra ? 2 1 0 n timer start 2 1 0 n match detect counter clear n ? 1
page 75 TMP88FW45FG 8.3.4 window mode in the window mode, the up-counter counts up at the rising edge of the pulse that is logical anded product of the input pulse to the tc1 pin (window pulse) and the internal source clock. eith er the positive logic (count up during high-going pulse) or negative logic (count up during low-going pulse) can be selected. when a match between the up-counter and the tc1dra va lue is detected, an inttc1 interrupt is generated and the up-counter is cleared. define the window pulse to the frequency which is sufficiently lower than the internal source clock pro- grammed with tc1cr. figure 8-5 window mode timing chart match detect tc1dra inttc1 interrput request interrput request internal clock counter tc1dra tc1 pin input internal clock counter tc1 pin input inttc1 (a) positive logic (tc1s = 10) (b) negative logic (tc1s = 11) ? ? match detect 1 0 7 47 5 46 31 2 1 0 7 5 3 6 2 0 2 3 counter clear timer start 890 1 9 timer start counter clear count start count stop count start count start count stop count start
page 76 8. 16-bit timercounter 1 (tc1) 8.3 function TMP88FW45FG 8.3.5 pulse width measurement mode in the pulse width measurement mode, the up-counter starts counting by the input pulse triggering of the tc1 pin, and counts up at the edge of the internal clock. either the rising or falling edge of the internal clock is selected as the trigger edge in tc1cr< tc1s>. either the single- or double-e dge capture is selected as the trig- ger edge in tc1cr. ? when tc1cr is set to ?1? (single-edge capture) either high- or low-level input pulse width can be measured. to measure the high-level input pulse width, set the rising edge to tc1cr. to measure the low-level input pulse width, set the falling edge to tc1cr. when detecting the edge opposite to the trigger ed ge used to start countin g after the timer starts, the up-counter captures the up-counter value in to tc1drb and generates an inttc1 interrupt request. the up-counter is cleared at this time, a nd then restarts counting wh en detecting the trigger edge used to start counting. ? when tc1cr is set to ?0? (double-edge capture) the cycle starting with either the high- or low-going input pulse can be measured. to measure the cycle starting with the high-going pulse, set the ri sing edge to tc1cr. to measure the cycle starting with the low-going pulse, set the falling edge to tc1cr. when detecting the edge opposite to the trigger ed ge used to start countin g after the timer starts, the up-counter captures the up-counter value in to tc1drb and generates an inttc1 interrupt request. the up-counter continues counting up, a nd captures the up-counter value into tc1drb and generates an inttc1 interrupt request when detecting the trigger edge used to start counting. the up-counter is cleared at this time, and then continues counting. note 1: the captured value must be read from tc1drb until the next trigger edge is detected. if not read, the cap- tured value becomes a don?t care. it is recommended to us e a 16-bit access instruction to read the captured value from tc1drb. note 2: for the single-edge capture, the counter after capt uring the value stops at ?1? until detecting the next edge. therefore, the second captured value is ?1? larger than the captured value i mmediately after counting starts. note 3: the first captured value after the timer starts may be read incorrectively, therefore, ignore the first captured value.
page 77 TMP88FW45FG example :duty measurem ent (resolution fc/2 7 [hz], cgcr = ?0?) clr (inttc1sw). 0 ; inttc1 serv ice switch initial setting address set to convert inttc1sw at each inttc1 ld (tc1cr), 00000110b ; sets the tc1 mode and source clock di ; imf = ?0? set (eird). 2 ; enables inttc1 ei ; imf = ?1? ld (tc1cr), 00100110b ; starts tc1 with an external trigger at mcap1 = 0 : pinttc1: cpl (inttc1sw). 0 ; inttc1 interrupt, inverts and tests inttc1 service switch jrs f, sinttc1 ld a, (tc1drbl) ; reads tc1drb (high-level pulse width) ld w,(tc1drbh) ld (hpulse), wa ; stores high-level pulse width in ram reti sinttc1: ld a, (tc1drbl) ; reads tc1drb (cycle) ld w,(tc1drbh) ld (width), wa ; stores cycle in ram : reti ; duty calculation : vinttc1: dw pinttc1 ; inttc1 interrupt vector width hpulse tc1 pin inttc1 interrupt request inttc1sw
page 78 8. 16-bit timercounter 1 (tc1) 8.3 function TMP88FW45FG figure 8-6 pulse wi dth measurement mode tc1drb inttc1 interrupt request interrupt request tc1 pin input counter internal clock (mcap1 = "1") 23 n count start count start trigger (tc1s = "10") 1 3 2 1 4 0 n 0 capture n - 1 tc1drb inttc1 tc1 pin input counter internal clock (mcap1 = "0") 12 n count start count start (tc1s = "10") 3 2 1 4 0 n capture capture n + 1 m - 2 n + 3 n + 2 n + 1 m - 1 m0 m [application] high-or low-level pulse width measurement [application] (1) cycle/frequency measurement (2) duty measurement (a) single-edge capture (b) double-edge capture
page 79 TMP88FW45FG 8.3.6 programmable pulse generate (ppg) output mode in the programmable pulse generation (ppg) mode, an arbitrary duty pulse is generated by counting per- formed in the internal clock. to start the timer, tc1c r specifies either the edge of the input pulse to the tc1 pin or the command start. tc1cr specifies whether a duty pulse is produced continuously or not (one-shot pulse). ? when tc1cr is set to ?0? (continuous pulse generation) when a match between the up-counter and the tc1drb value is detected after the timer starts, the level of the ppg pin is inverted and an inttc1 interrupt request is generated. the up-counter contin- ues counting. when a match between the up-counter and the tc1dra value is detected, the level of the ppg pin is inverted and an inttc1 interrupt requ est is generated. the up-counter is cleared at this time, and then continues counting and pulse generation. when tc1cr is cleared to ?00? during ppg output, the ppg pin retains the level immedi- ately before the counter stops. ? when tc1cr is set to ?1? (one-shot pulse generation) when a match between the up-counter and the tc1drb value is detected after the timer starts, the level of the ppg pin is inverted and an inttc1 interrupt request is generated. the up-counter contin- ues counting. when a match between the up-counter and the tc1dra value is detected, the level of the ppg pin is inverted and an inttc1 interrupt re quest is generated. tc1cr is cleared to ?00? automatically at this time, and the timer stops. the pulse generated by ppg retains the same level as that when the timer stops. since the output level of the ppg pin can be set with tc1cr when the timer starts, a positive or neg- ative pulse can be generated. since the inverted level of the timer f/f1 output level is output to the ppg pin, specify tc1cr to ?0? to set the high level to the ppg pin, and ?1? to set the low level to the ppg pin. upon reset, the timer f/f1 is initialized to ?0?. note 1: to change tc1dra or tc1drb during a run of the timer, set a value sufficiently larger than the count value of the counter. setting a value smaller than the count value of the counter during a run of the timer may generate a pulse different from that specified. note 2: do not change tc1cr during a run of the ti mer. tc1cr can be set correctly only at initial- ization (after reset). when the timer stops during pp g, tc1cr can not be set correctly from this point onward if the ppg output has the level which is inverted of the level when the timer starts. (setting tc1cr specifies the timer f/f1 to the level inverted of the programmed value.) therefore, the timer f/f1 needs to be initialized to ensure an arbitrar y level of the ppg output. to initialize the timer f/f1, change tc1cr to the timer mode (it is not required to start the timer mode), and then set the ppg mode. set tc1cr at this time. note 3: in the ppg mode, the follow ing relationship must be satisfied. tc1dra > tc1drb note 4: set tc1drb after changing the mode of tc1m to the ppg mode.
page 80 8. 16-bit timercounter 1 (tc1) 8.3 function TMP88FW45FG figure 8-7 ppg output example :generating a pulse which is high-going for 800 s and low-going for 200 s (fc = 20 mhz, cgcr = ?0?) setting port ld (tc1cr), 10001011b ; sets the ppg mode, selects the source clock ldw (tc1dra), 04e2h ; sets the cycle (1 ms 2 4 /fc s = 04e2h) ldw (tc1drb), 00fah ; sets the low-level pulse width (200 s 2 4 /fc = 00fah) ld (tc1cr), 10010111b ; starts the timer q r d ppg pin function output port output enable i/o port output latch shared with ppg output data output toggle set clear q tc1cr write to tc1cr internal reset match to tc1drb match to tc1dra tc1cr clear timer f/f1 inttc1 interrupt request
page 81 TMP88FW45FG figure 8-8 pp g mode timing chart inttc1 tc1dra internal clock counter tc1drb tc1dra ppg pin output 0 inttc1 interrupt request interrupt request 12 m01 2 n m01 n 2 n n + 1 n + 1 m (a) continuous pulse generation (tc1s = 01) tc1drb trigger count start timer start counter internal clock tc1 pin input ppg pin output 0 1m n n n + 1 m 0 (b) one-shot pulse generation (tc1s = 10) match detect note: m > n note: m > n [application] one-shot pulse output
page 82 8. 16-bit timercounter 1 (tc1) 8.3 function TMP88FW45FG
page 83 TMP88FW45FG 9. 16-bit timer (ctc) 9.1 configuration figure 9-1 ctc block diagram ctc1cr2 ctc1cr1 3 2 2 2 3 3 toggle q set clear ? ctc1s ctc1sm ctc1se ctc1cy ctc1e ? rising edge falling edge s a y b ctc pin h a b c d y e s fc/2 11 or fc/2 12 fc/2 7 or fc/2 8 fc/2 5 or fc/2 6 fc/2 3 or fc/2 4 fc/2 2 or fc/2 3 fc/2 or fc/2 2 ctc1ck ctc1s ctc1res extrgdis ctc1reg ctc1ck ctc1ff0 ppgff0 ctc1m ctc1cy ctc1se ctc1e ctc1sm ctc1m ctc1ff0 ppgff0 ctc1m ctc1reg last coincidence interrupt stop trigger clear start start control read/write control and clear interrupt select write register select read register ctc1dra ctc1drb ctc1drc 16-bit up counter intctc1 interrupt ppg2 pin edge detection comparator extrgdis
page 84 9. 16-bit timer (ctc) 9.1 configuration TMP88FW45FG 9.2 control compare timer/counter 1 is controlled using compar e timer/counter 1 control registers (ctc1cr1 and ctc1cr2), as well as three 16-bit timer re gisters (ctc1dra, ctc1drb, and ctc1drc). note: ctc1dra, ctc1drb, and ctc1drc are write-only registers and must not be used with any of the read-modify-write instructions such as set, clr, etc. note 1: *: don?t care note 2: the ctc1cr1 is 0 when read. note 3: use the ldw instruction for write to the ctc1dr h/l registers. set a value equal to or greater than 2. note 4: write to ctc1dr h/l a, b, and c registers as many as set with the ctc1cr2 register ctc1reg bit. note 5: data are written to ctc1dr h/l registers in order of ctc1dra, ctc1drb, and ctc1drc. compare timer registers (ctc1 drh: 00017h, ctc1drl: 00016h) ctc1dra 1514131211109876543210 write only (initial value: ******** ********) ctc1drah ctc1dral ctc1drb 1514131211109876543210 write only (initial value: ******** ********) ctc1drbh ctc1drbl ctc1drc 1514131211109876543210 write only (initial value: ******** ********) ctc1drch ctc1drcl compare timer/counter 1 control registers (ctc1cr2: 00015h, ctc1cr1: 00014h) ctc1cr1 lower address 76543210 r/w (initial value: 00000000) ctc1res ppgff0 ctc1m ctc1cy ctc1se ctc1e ctc1sm ctc1s ctc1cr2 upper address 76543210 r/w (initial value: *0000000) * extrg- dis ctc1reg ctc1ck ctc1ff0
page 85 TMP88FW45FG note 1: fc: clock [hz] note 2: make sure the timer/counter is idle (ctc1cr1 = 00) before setting operation mode, edge, start, source clock, external trigger time r mode control, and ppg output control. note 3: when dv1ck=1, ctc1cr2=100 cannot be used. note 4: when ctc1 input is not used in the ctc1 timer, exte rnal trigger input must be disabled (ctc1cr2 = 1) regardless of the selected mode. note 5: the ctc1drb and ctc1drc registers cannot be accessed for write unless they are set for ppg output mode and specified with ctc1cr2. note 6: ctc1cr1 is effective only when using an external clock as trigger (ctc1cr1). note 7: data must be written to as many data registers as set with ctc1cr2. note 8: to write data to ctc1dra/b/c, use the ldw instruction, or use the ld instruction writing in order of l, h. note 9: data register values must be written to the respective r egisters before starting. to modify the values after starting, w rite the new data within an interval from an intctc1 interrupt to the next intctc1. setting-up the ctc1cr1 register ctc1s control start 0: stop and clear counter 1: command start timer event ppg r/w ?? ?? ctc1sm select start 0: software start 1: external trigger start ?? ? ctc1e select external trigger edge 0: enable one edge 1: enable both edges ?? ? ctc1se select external trigger start edge 0: rising edge 1: falling edge ?? ?? ctc1cy select cycle 0: successive 1: one shot ?? ? ctc1m set operation mode 0: timer/event counter modes 1: ppg (programmable pulse generator) output mode ppgff0 select ppg output 0: forward output immediately after start 1: reverse output immediately after start ctc1res reset all 0: normal operation 1: ctc1 reset setting-up the ctc1cr2 register ctc1ff0 control timer output f/f0 0: clear 1: set r/w ctc1ck select timer/counter clock source unit: hz normal and idle modes dv1ck = 0 dv1ck = 1 timer event ppg 000 fc/2 11 fc/2 12 - 001 fc/2 7 fc/2 8 - 010 fc/2 5 fc/2 6 - 011 fc/2 3 fc/2 4 - 100 fc/2 2 fc/2 3 - note3 101 fc/2 fc/2 2 - 110 - - 111 external clock input (ctc1 pin input) - ctc1reg set registers used by timer/ counter 00: ctc1dra 01: ctc1dra + ctc1drb 10: ctc1dra + ctc1drb + ctc1drc 11: reserved 1reg 2reg 3reg extrgdis external trigger input note4 0: enable external trigger input 1: disable external trigger input
page 86 9. 16-bit timer (ctc) 9.1 configuration TMP88FW45FG note 10:specifying ctc1cr1 = 1 ca uses all conditions to be reset. even when the ctc circuit is operating, they are reset, and the ppg output becomes ?0?. however, only the intctc1 signal is not reset if the signal is being gener- ated. note 11:for event counter mode (when ctc pin input is selected in timer mode), the active edge of the external trigger to count can be selected with ctc1cr1. note 12:disabling external trigger input with ctc1cr2 creates the 0 input state. note 13:to stop the counter by software at trigger start, set ctc1cr2 = 00. note 14:the number of registers set and the values set in the timer registers must meet the conditions shown below. number of registers timer register value conditions ctc1reg 1 register ctc1dra 2 2 register ctc1drb > ctc1dra + 1, and ctc1dra 2 3 register ctc1drc > ctc1drb + 1, ct c1drb > ctc1dra + 1, and ctc1dra 2
page 87 TMP88FW45FG 9.3 function compare timer/counter 1 has three modes: timer, event counter, and programmable pulse generator output modes. 9.3.1 timer mode with software start in this mode, the timer/counter (16-bit counter) counts up synchronously with the internal clock. when the counter value and the set value of compare timer regi ster 1a (ctc1dra) match, an intctc1 interrupt is generated and the counter is cleared. after the coun ter is cleared, it restarts and continues counting up. figure 9-2 timer mode timing chart note:if the ctc input port (p47) is set for input mode, the timer/counter is reset by an input edge on port. when using the timer/counter as an ordinary timer, set ctc1cr2 to 1 or set p47 for output mode. table 9-1 internal clock source for compare timer/counter 1 (example: fc = 20 mhz) ctc1ck normal and idle modes dv1ck = 0 dv1ck = 1 resolution [ s] maximum setting time [s] resolution [ s] maximum setting time [s] 000 102.4 6.71 204.8 13.42 001 6.4 0.419 12.8 0.839 010 1.6 0.105 3.2 0.210 011 0.4 26.21 m 0.8 52.43 m 100 0.2 13.11 m 0.4 26.21 m 101 0.1 6.55 m 0.2 13.11 m 110 - - - - 123 0 n n - 1 2 5 48 39 6 7 1 n timer register a internal clock counter intctc1 interrupt successive
page 88 9. 16-bit timer (ctc) 9.1 configuration TMP88FW45FG 9.3.2 timer mode with ex ternal trigger start in this timer mode, the timer/counter starts counting as triggered by input on ctc pin (rising or falling edge selected with ctc1cr1). the source clock is an internal clock. for succ essive cycles, when the counter value and the set value of the ctc1dra register match, an intctc1 interrupt is generated and the counter is cleared and then restarted. the counter is st opped by a trigger input on ctc pin and restarted by the next trigger input. for a one-shot cycle, when the counter value and the set value of the ctc1dra register match, an intctc1 interrupt is generated and the counte r is cleared and stopped. the counter restarts count- ing up by input on ctc pin. when ctc1cr1 = 1, the counter is cleared and stops counting at an edge on ctc pin input opposite the active edge that tri ggers the counter to start counting. in this mode, an interrupt can be generated by entering a pulse wh ich has a certain width. when ctc1cr1 = 0, opposite edges on ctc input are ignored. figure 9-3 external tr igger mode timing chart 1 2 n - 1 022 11 n34 ctc pin input internal clock counter (i) when rising edge start is selected, with counting enabled on one edge ( ctc1se = 0, ctc1e = 0 ) timer register a count start count start stop intctc1 interrupt n successive clear trigger trigger trigge r 1 2 n - 1 036 05 n4 12 ctc pin input internal clock counter timer register a count start count start intctc1 interrupt n one shot stop trigger trigger t a) successive b) one shot
page 89 TMP88FW45FG figure 9-4 external tr igger mode timing chart 9.3.3 event counter mode in this mode, the timer/counter counts up at the active edge on ctc pin in put (rising or falling edge selected with the ctc1cr1 which is provided for select ing external trigger edge). when the counter value and the set value of the ctc1dra register match, an intctc1 interrupt is generated and the counter is cleared. after the counter is cleared, it restarts and continue s counting up at each edge on ctc pin input. the maximum applied frequency is shown in the table below. because coincidence detection is made at an edge opposite the selected edge, the external clock signal on ctc pin must always be entered. figure 9-5 event c ounter mode timing chart 12 00 1 n - 1 m13 2 n ctc pin input internal clock counter (ii) when rising start edge is selected, with counting enabled on both edges ( ctc1se = 0, ctc1e = 1 ) timer register a count start count stop count start intctc1 interrupt n successive trigger trigger trigger 12 0 3 0 2 n501 34 12 ctc pin input internal clock counter timer register a count start count clear count start intctc1 interrupt n one shot trigger trigger trigger note) m < n a) successive b) one shot 1 0 2 1 n - 1 n 0 n timer register ctc pin input when rising start edge is selected counter command start intctc1 interrupt
page 90 9. 16-bit timer (ctc) 9.1 configuration TMP88FW45FG 9.3.4 programmable pulse generate (ppg) output mode the timer/counter starts counting as a command or edge on ctc pin input (rising/falling edge and one/both edges respectively selected with the ctc1cr1 and ctc1cr1). the source clock is an internal clock. when matched with the ctc1dr a/b/c registers, the tim er output f/f corresponding to each mode is inverted. when matched with the ctc1dr a/b/c registers next time, the timer output f/f is inverted again. an intctc1 interrupt request is generated when the counter value matches the maximum register value set by ctc1cr2. the timer outpu t f/f is cleared to 0 when reset. because ctc1cr2 can be used to set the initial valu e for the timer output f/f, an active-high or active- low pulse whichever is desired can be output. the ctc1drb and ctc1drc registers cannot be accessed for write unless they are set for ppg outp ut mode and the registers used ar e selected with ctc1cr2. the number of registers set can be altered during operation. in this case, however, be sure to set the number of registers used and write values to the data registers before the next ctc1init1 is output after the first ctc1init1 output. even when only altering the data re gister values while leavi ng the number of registers unchanged, be sure to do this within the same period of time. note:when port p47 is set as a ctc input port, an edge i nput resets the timer/counter. when ppg output mode is selected and external trigger start is not used, set ct c1cr2 to "1" or set p47 as an output port. table 9-2 external clock source for compare timer/counter 1 normal and idle modes maximum applied frequency [hz] up to fc/2 2 minimum pulse width 2 2 /fc and over table 9-3 internal clock source for compare timer/counter 1 (example: fc = 20 mhz) ctc1ck normal and idle modes dv1ck = 0 dv1ck = 1 resolution [ s] maximum setting time [s] resolution [ s] maximum setting time [s] 000 ???? 001 ???? 010 ???? 011 ???? 100 0.2 13.11 m ?? 101 0.1 6.55 m 0.2 13.11m 110 ????
page 91 TMP88FW45FG figure 9-6 one register comm and start mode timing chart (i) one register used (ctc1reg = 00) when set to command start. ctc pin input counter timer register a 11 1 n n 0 intctc1 interrupt command start n ppg2 pin output 1 n 1 2 3 n successive
page 92 9. 16-bit timer (ctc) 9.1 configuration TMP88FW45FG figure 9-7 two register one edge trigger star t mode timing chart (ii) two registers used (ctc1reg = 01) when set to the external trigger rising edge start and the one edge enable. ctc pin input counter internal clock timer register a timer register b 1 m m+1 m m+1 1 n 0 intctc1 interrupt start stop m n ppg2 pin output 1 2 0 n successive initial value ctc pin input counter internal clock timer register a timer register b 1 m m+1 0 n 0 intctc1 interrupt start start m n ppg2 pin output 1 one shot a) successive b) one shot
page 93 TMP88FW45FG figure 9-8 two regster both edges trigger start mode timing chart when set to the external trigger rising edge start and the both edges enable. ctc pin input counter internal clock timer register a timer register b 1 m m+1 m 1 n 0 intctc1 interrupt start start stop m n ppg2 pin output 1 0 successive initial value ctc pin input counter internal clock timer register a timer register b 1 m m+1 mn m+1 0 11 n 2 00 0 intctc1 interrupt start m n ppg2 pin output m 1 m+1 0 one shot start start start a) successive b) one shot
page 94 9. 16-bit timer (ctc) 9.1 configuration TMP88FW45FG note: in the single-shot mode, the ppg pin output is not toggled at the last register match; it st ays at the value specified wit h ctc1cr2. figure 9-9 three regi ster command start mode timing chart (iii) three registers used (ctc1reg = 10) when set to command start. ctc pin input counter timer register a timer register b 1 m m+1 s n+1 n 0 intctc1 interrupt command start m n timer register c s ppg2 pin output m+1 m n 1 successive ctc pin input counter timer register a timer register b 1 1 m m m+1 s n+1 n 0 intctc1 interrupt command start command restart m n timer register c s ppg2 pin output m+1 0 one shot a) successive b) one shot
page 95 TMP88FW45FG detail operation at start that varies depending on how ctc1cr2 and ctc1cr1 are set during ppg output. by changing the port-shared output for ppg output before the counter starts counting after setting ctc1cr2, it is possible to determine the initial value of ppg output. table 9-4 varying ppg output timing depending on settings ctc1ff0 = 0 ppgff0 = 0 ctc1ff0 = 1 ppgff0 = 0 ctc1ff0 = 0 ppgff0 = 1 ctc1ff0 = 1 ppgff0 = 1 1 0 2 n n+1 n+3 n+2 3 internal clock counter ppg output ctc1ff0 setting (write to ctc1cr1 register) command start or trigger start 1 0 2 n n + 1 n + 3 n + 2 3 internal clock counter ppg output ctc1ff0 setting (write to ctc1cr1 register) command start or trigger start 1 0 2 n n + 1 n + 3 n + 2 3 internal clock counter ppg output ctc1ff0 setting (write to ctc1cr1 register) command start or trigger start 1 0 2 n n + 1 n + 3 n + 2 3 internal clock counter ppg output ctc1ff0 setting (write to ctc1cr1 register) command start or trigger start
page 96 9. 16-bit timer (ctc) 9.1 configuration TMP88FW45FG
page 97 TMP88FW45FG 10. 8-bit timercounter 3 (tc3) 10.1 configuration note: function input may not operate depending on i/o port setti ng. for more details, see the chapter "i/o port". figure 10-1 timercounter 3 (tc3) tc3ck tc3s fc/2 13 , fc/2 14 fc/2 12 , fc/2 13 fc/2 11 , fc/2 12 fc/2 10 , fc/2 11 fc/2 9 , fc/2 , fc/2 9 , fc/2 8 3 source clock capture clear tc3s inttc3 interrupt tc3 contorol register 8-bit timer register overflow detect h a b c d e f g s tc3m tc3cr edge detector tc3drb tc3dra capture acap tc3s falling rising a y b s match detect y 8-bit up-counter tc3 pin port (note) cmp fc/2 8 fc/2 7 10
page 98 10. 8-bit timercounter 3 (tc3) 10.1 configuration TMP88FW45FG 10.2 timercounter control the timercounter 3 is controlled by the timercounter 3 control register (tc3cr) and two 8-bit timer registers (tc3dra and tc3drb). note 1: fc: high-frequency clock [hz], * : don?t care note 2: set the operating mode and source clock when timercounter stops (tc3cr = 0). note 3: to set the timer registers, the following relationship must be satisfied. tc3dra > 1 (timer/event counter mode) note 4: auto-capture (tc3cr) can be used only in the timer and event counter modes. note 5: when the read instruction is executed to tc3cr, the bit 5 and 7 are read as a don?t care. note 6: do not program tc3dra when the timer is running (tc3cr = 1). note 7: when the stop mode is entered, the start control (tc3cr) is cleared to 0 automatically, and the timer stops. after the stop mode is exited, tc3cr must be set again to use the timer counter. timer register and control register tc3dra (001ch) 76543210 read/write (initial value: 1111 1111) tc3drb (001dh) read only (initial value: 1111 1111) tc3cr (001eh) 76543210 acap tc3s tc3ck tc3m (initial value: *0*0 0000) acap auto capture control 0: ? 1: auto capture r/w tc3s tc3 start control 0: stop and counter clear 1: start r/w tc3ck tc3 source clock select [hz] normal, idle mode r/w dv1ck=0 dv1ck=1 000 fc/2 13 fc/2 14 001 fc/2 12 fc/2 13 010 fc/2 11 fc/2 12 011 fc/2 10 fc/2 11 100 fc/2 9 fc/2 10 101 fc/2 8 fc/2 9 110 fc/2 7 fc/2 8 111 external clock (tc3pin input) tc3m tc3 operating mode select 0: timer/event counter mode 1: capture mode r/w
page 99 TMP88FW45FG 10.3 function timercounter 3 has three types of operating modes: timer, event counter and capture modes. 10.3.1 timer mode in the timer mode, the up-counter counts up using the internal clock. when a match between the up-counter and the timer register 3a (tc3dra) value is detected, an inttc3 interrupt is generated and the up-counter is cleared. after being cleared , the up-counter restarts counting. setting tc3cr to 1 captures the up- counter value into the timer register 3b (tc3drb) with the auto-capture function. the count value during timer operation can be checked by execu ting the read instruction to tc3drb. note:00h which is stored in the up-counter immediately after detection of a match is not captured into tc3drb. (figure 10-2) figure 10-2 auto-capture function table 10-1 source clock for timercounter 3 (example: fc = 20 mhz) tc3ck normal, idle mode dv1ck = 0dv1ck = 1 resolution [ s] maximum time setting [ms] resolution [ s] maximum time setting [ms] 000 409.6 104.45 819.2 208.90 001 204.8 52.22 409.6 104.45 010 102.4 26.11 204.8 52.22 011 51.2 13.06 102.4 26.11 100 25.6 6.53 51.2 13.06 101 12.8 3.06 25.6 6.53 110 6.4 1.63 12.8 3.06 tc3drb note: in the case that tc3drb is c8h clock up-counter match detect c7 c8 tc3dra c8 00 01 c7 c8 c6 c6 01
page 100 10. 8-bit timercounter 3 (tc3) 10.1 configuration TMP88FW45FG figure 10-3 timer mode timing chart match detect tc3cr tc3drb tc3dra inttc3 interrupt source clock counter source clock counter (a) timer mode (b) auto capture ? ? 7 6 3 4 5 0 n timer start 1 2 3 2 1 4 0 n counter clear capture n + 1 n m + 2 m + 1 m m capture m + 2 m + 1 n + 1 n
page 101 TMP88FW45FG 10.3.2 event counter mode in the event counter mode, the up-counter counts up at the rising edge of the input pulse to the tc3 pin. when a match between the up-counter and tc3dra value is detected, an inttc3 interrupt is generated and up-counter is cleared. after being cleared, the up-counter restarts counting at each rising edge of the input pulse to the tc3 pin. since a match is detected at the falling edge of the input pulse to tc3 pin, an inttc3 interrupt request is generated at the falling edge im mediately after the up-counter reaches the value set in tc3dra. the maximum applied frequencies are shown in table 10 -2. the pulse width larger than one machine cycle is required for high-going and low-going pulses. setting tc3cr to 1 captures the up-counter value into tc3drb with the auto-capture function. the count value during a timer operation can be checked by the read instruction to tc3drb. note:00h which is stored in the up-counter immediately after detection of a match is not captured into tc3drb. (figure 10-2) figure 10-4 event count er mode timing chart example :inputting 50 hz pulse to tc3, and generating interrupts every 0.5 s ld (tc3cr), 00001110b : sets the clock mode ld (tc3dra), 19h : 0.5 s 1/50 = 25 = 19h ld (tc3cr), 00011110b : starts tc3. table 10-2 maximum frequencies applied to tc3 minimum pulse width normal, idle mode high-going 2 2 /fc low-going 2 2 /fc n inttc3 interrupt tc3 pin input counter tc3dra match detect counter clear timer start 0 1 2 3 n 0 1 2 3
page 102 10. 8-bit timercounter 3 (tc3) 10.1 configuration TMP88FW45FG 10.3.3 capture mode in the capture mode, the pulse width, frequency and du ty cycle of the pulse input to the tc3 pin are mea- sured with the internal clock. the capture mode is used to decode remote control signals, and identify ac50/60 hz. when the falling edge of the tc3 input is detected afte r the timer starts, the up-co unter value is captured into tc3drb. hereafter, whenever the rising edge is detect ed, the up-counter value is captured into tc3dra and the inttc3 interrupt request is generated. the up-counter is cleared at this time. generally, read tc3drb and tc3dra during inttc3 interrupt processing. after the up-counter is cleared, counting is continued and the next up-counter value is captured into tc3drb. when the rising edge is detected immediately after the timer starts, th e up-counter value is captured into tc3dra only, but not into tc3drb. the inttc3 interrupt request is generated. when the read instruction is executed to tc3drb at this time, the va lue at the completion of the last capture (ff im mediately after a reset) is read. the minimum input pulse width must be larger than one cycle width of the source clock programmed in tc3cr. the inttc3 interrupt request is generated if the up-c ounter overflow (ffh) occurs during capture operation before the edge is detected. tc3dra is set to ffh a nd the up-counter is cleared. counting is continued by the up-counter, but capture operation and overflow detect ion are stopped until tc3dra is read. generally, read tc3drb first because capture operation and ove rflow detection resume by reading tc3dra. figure 10-5 captur e mode timing chart read of tc3dra source clock counter tc3dra tc3 pin input tc3drb inttc3 interrupt request i fe 2 3 1 0 1 k-1 1 capture capture capture capture capture m ff (overflow) k n 0 ff tc3cr i i+1 i-1 0 k m m+1 m-1 n-1 0 n 2 1 3 internal waveform fe overflow timer start
page 103 TMP88FW45FG 11. 8-bit timercounter 4 (tc4) 11.1 configuration figure 11-1 timercounter 4 (tc4) pwm output mode clear 3 2 source clock 8-bit up-counter overflow detect toggle clear timer f/f match detect s y 0 1 y s s 1 0 y pdo mode port (note) ::?:?:? (note) a b c d e f g h y s cmp note: function i/o may not operate depending on i/o port setting. for more details, see the chapter "i/o port". tc4cr tc4dr inttc4 interrupt tc4s tc4s tc4s tc4m tc4ck tc4 pin pwm4 / pdo4 / pin fc/2 11 , fc2 12 fc/2 7 , fc2 8 fc/2 5 , fc2 6 fc/2 3 , fc2 4 fc/2 2 , fc2 3 fc/2, fc2 2 fc, fc/2
page 104 11. 8-bit timercounter 4 (tc4) 11.1 configuration TMP88FW45FG 11.2 timercounter control the timercounter 4 is controlled by the timercounter 4 c ontrol register (tc4cr) and timer registers 4 (tc4dr). note 1: fc: high-frequency clock [hz], * : don?t care note 2: to set the timer registers, the following relationship must be satisfied. 1 tc4dr 255 note 3: to start timer operation (tc4cr = 0 1) or disable timer operation (tc4cr = 1 0), do not change the tc4cr setting. during timer operation (tc4cr = 1 1), do not change it, either. if the setting is programmed during timer operation, counting is not performed correctly. note 4: the event counter and pwm output modes are used only in the nomal and idle modes. note 5: when the stop mode is entered, the start control (tc4s) is cleared to ?0? automatically. note 6: the bit 6 and 7 of tc4cr are read as a don?t care when these bits are read. note 7: in the timer, event counter and pdo modes, do not change the tc4dr setting when the timer is running. note 8: when the high-frequency clock fc exceeds 10 mhz, do not select the source clock of tc4cr< tc4ck> = 110. note 9: for available source clocks depending on the operation mode, refer to the following table. note: o : available source clock timer register and control register tc4dr (001bh) 76543210 read/write (initial value: 1111 1111) tc4cr (001ah) 76543210 tc4s tc4ck tc4m read/write (initial value: **00 0000) tc4s tc4 start control 0: stop and counter clear 1: start r/w tc4ck tc4 source clock select [hz] normal, idle mode r/w dv1ck = 0dv1ck = 1 000 fc/2 11 fc/2 12 001 fc/2 7 fc/2 8 010 fc/2 5 fc/2 6 011 fc/2 3 fc/2 4 100 fc/2 2 fc/2 3 101 fc/2 fc/2 2 110 (fc) note8 (fc/2) note8 111 external clock (tc4 pin input) tc4m tc4 operating mode select 00: timer/event counter mode 01: reserved 10: programmable divider output (pdo) mode 11: pulse width modulation (pwm) output mode r/w tc4ck timer mode event counter mode pdo mode pwm mode 000 o ? o ? 001 o ? o ? 010 o ? o ? 011 o ?? o 100 ? ?? o 101 ??? o 110 ?? ? o 111 ? o ?
page 105 TMP88FW45FG 11.3 function timercounter 4 has four types of operating modes: timer, event counter, programmable divider output (pdo), and pulse width modulation (pwm) output modes. 11.3.1 timer mode in the timer mode, the up-counter counts up using the internal clock. when a match between the up-counter and the tc4dr value is detected, an inttc4 interrupt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counting. 11.3.2 event counter mode in the event counter mode, the up-counter counts up at the rising edge of the input pulse to the tc4 pin. when a match between the up-counter and the tc4dr va lue is detected, an inttc4 interrupt is generated and the up-counter is cl eared. after being cleared, the up-counter restarts counting at rising edge of the tc4 pin. since a match is detected at the falling edge of the input pulse to the tc4 pin, the inttc4 interrupt request is generated at the falling edge immediately after the up-counter reaches the value set in tc4dr. the minimum pulse width applied to the tc4 pin are shown in table 11-2. the pulse width larger than two machine cycles is required for high- and low-going pulses. note:the event counter mode can used in the normal and idle modes only. 11.3.3 programmable divi der output (pdo) mode the programmable divider output (pdo) mode is used to generated a pulse with a 50% duty cycle by count- ing with the internal clock. when a match between the up-counter and the tc4dr value is detected, the logic level output from the pdo4 pin is switched to the opposite state and inttc 4 interrupt request is generated. the up-counter is cleared at this time and then counting is continued. when a match between the up-counter and the tc4dr value is detected, the logic level outp ut from the pdo4 pin is switched to the opposite state again and inttc4 interrupt request is generated. the up-counter is cleared at this time, and then counting and pdo are continued. when the timer is stopped, the pdo4 pin is high. ther efore, if the timer is stopped when the pdo4 pin is low, the duty pulse may be shorter than the programmed value. table 11-1 internal source clock for timercounter 4 (example: fc = 20 mhz) tc4ck normal, idle mode dv1ck = 0 dv1ck = 1 resolution [ s] maximum time setting [ms] resolution [ s] maximum time setting [ms] 000 102.4 26.11 204.8 52.22 001 6.4 1.63 12.8 3.28 010 1.6 0.41 3.2 0.82 011 0.4 0.10 0.8 0.20 table 11-2 external source clock for timercounter 4 minimum pulse width normal, idle mode high-going 2 3 /fc low-going 2 3 /fc
page 106 11. 8-bit timercounter 4 (tc4) 11.1 configuration TMP88FW45FG figure 11-2 pdo mode timing chart 11.3.4 pulse width modul ation (pwm) output mode the pulse width modulation (pwm) output mode is used to generate the pwm pulse with up to 8 bits of res- olution by an internal clock. when a match between the up-counter and the tc4dr value is detected, the logic level output from the pwm 4 pin becomes low. the up-counter continues counting. when the up-counter overflow occurs, the pwm 4 pin becomes high. the inttc4 interrupt request is generated at this time. when the timer is stopped, the pwm4 pin is high. therefore, if the timer is stopped when the pwm4 pin is low, one pmw cycle may be shor ter than the programmed value. tc4dr is serially connected to th e shift register. if tc4dr is programmed during pwm output, the data set to tc4dr is not shifted until one pwm cycle is complete d. therefore, a pulse can be modulated periodically. for the first time, the data written to tc4dr is shif ted when the timer is started by setting tc4cr to 1. note 1: the pwm output mode can be used only in the normal and idel modes. note 2: in the pwm output mode, program tc4dr immedi ately after the inttc4 interrupt request is generated (typically in the inttc4 interrupt service routine.) when the programming of tc4dr and the inttc4 inter- rupt occur at the same time, an unstable value is shif ted, that may result in generation of pulse different from the programmed value until the next inttc4 interrupt request is issued. example :generating 1024 hz pulse (fc = 20.0 mhz and cgcr = 0) ld (tc4cr), 00000110b : sets the pdo mode. (tc4m = 10, tc4ck = 001) set (p2dr), 2 : sets the p22 output latch to 1. ld (tc4dr), 4ch : 1/1024 2 7 /fc 2 (half cycle period) = 4ch ld (tc4cr), 00100110b : start tc4 internal clock counter match detect 0 12 n 0 12 n 0 1 2 n 01 2 n 0 1 n tc4dr pdo4 pin inttc4 interrupt request timer f/f
page 107 TMP88FW45FG figure 11-3 pwm output mode timing chart (tc4) table 11-3 pwm mode (example: fc = 20 mhz) tc4ck normal, idle mode dv1ck = 0 dv1ck = 1 resolution [ns] cycle [ s] resolution [ns] cycle [ s] 000???? 001???? 010???? 011 400 102.4 800 204.8 100 200 51.2 400 102.4 101 100 25.6 200 51.2 110???? internal clock shift register counter n 0 ? ? 1 n + 1 ff 0 1 n n + 1 ff 01 m pwm cycle match detect mp n n m data shift rewrite data shift match detect match detect data shift n n m rewrite rewrite pwm4 pin inttc4 interrupt request timer f/f tc4dr tc4cr
page 108 11. 8-bit timercounter 4 (tc4) 11.1 configuration TMP88FW45FG
page 109 TMP88FW45FG 12. 8-bit timercounter 5,6(tc5, 6) 12.1 configuration figure 12-1 8-bit timercouter 5, 6 8-bit up-counter decode en a y b s a b y c d e f g h s a y b s s a y b toggle q set clear 8-bit up-counter a b y c d e f g h s decode en toggle q set clear pwm mode pdo, ppg mode pdo mode pwm, ppg mode pwm mode pwm mode 16-bit mode 16-bit mode 16-bit mode 16-bit mode timer, event counter mode overflow overflow timer, event couter mode 16-bit mode clear clear fc/2 7 , fc/2 8 fc/2 5 , fc/2 6 fc/2 3 , fc/2 4 pdo, pwm, ppg mode pdo, pwm mode 16-bit mode fc/2 7 , fc/2 8 fc/2 5 , fc/2 6 fc/2 3 , fc/2 4 fc/2 11 , fc/2 12 fc/2 11 , fc/2 12 tc6cr tc5cr ttreg6 pwreg6 ttreg5 pwreg5 tc5 pin tc6 pin tc6s tc5s inttc5 interrupt request inttc6 interrupt request tff6 tff5 pdo 6/pwm 6/ ppg 6 pin pdo 5/pwm 5/ pin tc5ck tc6ck tc5m tc5s tff5 tc6m tc6s tff6 timer f/f6 timer f/f5
page 110 12. 8-bit timercounter 5,6(tc5, 6) 12.1 configuration TMP88FW45FG 12.2 timercounter control the timercounter 5 is controlled by the timercounter 5 control register (tc5cr) and two 8-bit timer registers (ttreg5, pwreg5). note 1: do not change the timer register (t treg5) setting while the timer is running. note 2: do not change the timer register (pwreg5) setting in the operating mode except the 8-bit and 16-bit pwm modes while the timer is running. note 1: fc: high-frequency clock [hz] note 2: do not change the tc5m, tc5ck and tff5 settings while the timer is running. note 3: to stop the timer operation (tc5s= 1 0), do not change the tc5m, tc5ck and tff5 settings. to start the timer oper- ation (tc5s= 0 1), tc5m, tc5ck and tff5 can be programmed. note 4: to use the timercounter in the 16-bit mode, set th e operating mode by programming tc6cr, where tc5m must be fixed to 011. note 5: to use the timercounter in the 16-bit mode, select the source clock by programming tc5ck. set the timer start control and timer f/f control by programming tc6 cr and tc6cr, respectively. note 6: the operating clock settings are limited depending on the timer operating mode. for the detailed descriptions, see table 12-1. timercounter 5 timer register ttreg5 (0022h) r/w 76543210 (initial value: 1111 1111) pwreg5 (0024h) r/w 76543210 (initial value: 1111 1111) timercounter 5 control register tc5cr (0020h) 76543210 tff5 tc5ck tc5s tc5m (initial value: 0000 0000) tff5 time f/f5 control 0: 1: clear set r/w tc5ck operating clock selection [hz] normal, idle mode r/w dv1ck = 0 dv1ck = 1 000 fc/2 11 fc/2 12 001 fc/2 7 fc/2 8 010 fc/2 5 fc/2 6 011 fc/2 3 fc/2 4 100 - - 101 - - 110 - - 111 tc5i pin input tc5s tc5 start control 0: 1: operation stop and counter clear operation start r/w tc5m tc5m operating mode select 000: 001: 010: 011: 1**: 8-bit timer/event counter mode 8-bit programmable divider output (pdo) mode 8-bit pulse width modulation (pwm) output mode 16-bit mode (each mode is selectable with tc6m.) reserved r/w
page 111 TMP88FW45FG note 7: the timer register settings are limited depending on t he timer operating mode. for the detailed descriptions, see table 12- 2.
page 112 12. 8-bit timercounter 5,6(tc5, 6) 12.1 configuration TMP88FW45FG the timercounter 6 is controlled by the timercounter 6 control register (tc6cr) and two 8-bit timer registers (ttreg6 and pwreg6). note 1: do not change the timer register (t treg6) setting while the timer is running. note 2: do not change the timer register (pwreg6) setting in the operating mode except the 8-bit and 16-bit pwm modes while the timer is running. note 1: fc: high-frequency clock [hz] note 2: do not change the tc6m, tc6ck and tff6 settings while the timer is running. note 3: to stop the timer operation (tc6s= 1 0), do not change the tc6m, tc6ck and tff6 settings. to start the timer operation (tc6s= 0 1), tc6m, tc6ck and tff6 can be programmed. note 4: when tc6m= 1** (upper byte in the 16-bit mode), the sour ce clock becomes the tc6 over flow signal regardless of the tc5ck setting. note 5: to use the timercounter in the 16-bit mode, select the operating mode by programming tc6m, where tc5cr must be set to 011. note 6: to the timercounter in the 16-bit mode, select the so urce clock by programming tc5cr. set the timer start control and timer f/f control by prog ramming tc6s and tff6, respectively. timercounter 6 timer register ttreg6 (0023h) r/w 76543210 (initial value: 1111 1111) pwreg6 (0025h) r/ w 76543210 (initial value: 1111 1111) timercounter 6 control register tc6cr (0021h) 76543210 tff6 tc6ck tc6s tc6m (initial value: 0000 0000) tff6 timer f/f6 control 0: 1: clear set r/w tc6ck operating clock selection [hz] normal, idle mode r/w dv1ck = 0 dv1ck = 1 000 fc/2 11 fc/2 12 001 fc/2 7 fc/2 8 010 fc/2 5 fc/2 5 011 fc/2 3 fc/2 3 100 - - 101 - - 110 - - 111 tc6i pin input tc6s tc6 start control 0: 1: operation stop and counter clear operation start r/w tc6m tc6m operating mode select 000: 001: 010: 011: 100: 101: 110: 111: 8-bit timer/event counter mode 8-bit programmable divider output (pdo) mode 8-bit pulse width modulation (pwm) output mode reserved 16-bit timer/event counter mode warm-up counter mode 16-bit pulse width modulation (pwm) output mode 16-bit ppg mode r/w
page 113 TMP88FW45FG note 7: the operating clock settings are limited depending on the timer operating mode. for the detailed descriptions, see table 12-1. note 8: the timer register settings are limited depending on t he timer operating mode. for the detailed descriptions, see table 12- 2. note 1: for 16-bit operations (16-bit timer/event counter, warm- up counter, 16-bit pwm and 16-bit ppg), set its source clock on lower bit (tc5ck). note 2: : available source clock note: n = 5 to 6 table 12-1 operating mode and selectable source clock (normal and idle modes) operating mode fc/2 11 fc/2 7 fc/2 5 fc/2 3 tc5 pin input tc6 pin input 8-bit timer ??? ?? 8-bit event counter ? ? ? ? 8-bit pdo ??? ?? 8-bit pwm ??? ?? 16-bit timer ??? ?? 16-bit event counter ? ? ? ? ? 16-bit pwm ???? ? 16-bit ppg ???? ? table 12-2 constraints on register values being compared operating mode register value 8-bit timer/event counter 1 (ttregn) 255 8-bit pdo 1 (ttregn) 255 8-bit pwm 2 (pwregn) 254 16-bit timer/event counter 1 (ttreg6, 5) 65535 16-bit pwm 2 (pwreg6, 5) 65534 16-bit ppg 1 (pwreg6, 5) < (ttreg6, 5) 65535 and (pwreg6, 5) + 1 < (ttreg6, 5)
page 114 12. 8-bit timercounter 5,6(tc5, 6) 12.1 configuration TMP88FW45FG 12.3 function the timercounter 5 and 6 have the 8-bit timer, 8-bit ev ent counter, 8-bit programmable divider output (pdo), 8- bit pulse width modulation (pwm) output modes. the time rcounter 5 and 6 (tc5, 6) are cascadable to form a 16- bit timer. the 16-bit timer has the operating modes such as the 16-bit timer, 16-bit event counter, 16-bit pulse width modulation (pwm) output and 16-bit programmable pulse generation (ppg) modes. 12.3.1 8-bit timer mode (tc5 and 6) in the timer mode, the up-counter counts up using the internal clock. when a match between the up-counter and the timer register j (ttregj) value is detected, an inttcj interrupt is generated and the up-counter is cleared. after being cl eared, the up-counter restarts counting. note 1: in the timer mode, fix tcjcr to 0. if not fixed, the pdoj, pwmj and ppgj pins may output pulses. note 2: in the timer mode, do not change the ttregj setting while the timer is running. si nce ttregj is not in the shift register configuration in the timer mode, the new value programmed in ttregj is in effect immediately after the programming. therefore, if ttregi is changed while the timer is r unning, an expected operation may not be obtained. note 3: j = 5, 6 figure 12-2 8-bit timer mo de timing chart (tc6) table 12-3 source clock for timercounter 5, 6 (internal clock) source clock resolution repeated cycle normal, idle mode dv1ck = 0 fc = 20 mhz dv1ck = 0 fc = 20 mhz dv1ck = 0 dv1ck = 1 fc/2 11 [hz] fc/2 12 [hz] 128 s 32.6 ms fc/2 7 fc/2 8 8 s2.0 ms fc/2 5 fc/2 6 2 s 510 s fc/2 3 fc/2 4 500 ns 127.5 s example :setting the timer mode with source clock fc/2 7 hz and generating an interrupt 64 s later (timercounter6, fc = 20.0 mhz) ld (ttreg6), 0ah : sets the timer register (80 s 2 7 /fc = 0ah). di set (eirc). ef37 : enables inttc6 interrupt. ei ld (tc6cr), 00010000b : sets the operating cock to fc/2 7 , and 8-bit timer mode. ld (tc6cr), 00011000b : starts tc6. 1 2 3 n-1 n 0 1 n-1 n 2 0 1 2 0 n ? internal source clock counter match detect counter clear match detect counter clear tc6cr ttreg6 inttc6 interrupt request
page 115 TMP88FW45FG 12.3.2 8-bit event counter mode (tc5, 6) in the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the tcj pin. when a match between the up-counter and the ttregj valu e is detected, an inttcj interrupt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counti ng at the falling edge of the input pulse to the tcj pin. two machine cycles are required for the low- or high-level pulse input to the tcj pin. therefore, a maximum frequenc y to be supplied is fc/2 4 hz in the normal or idle mode. note 1: in the event counter mode, fix tcjcr to 0. if not fixed, the pdoj, pwmj and ppgj pins may output pulses. note 2: in the event counter mode, do not change the ttre gj setting while the timer is running. since ttregj is not in the shift register configuration in the event counter mode, the new value programmed in ttregj is in effect immediately after the programming. therefore, if ttregi is changed whil e the timer is running, an expected operation may not be obtained. note 3: j = 5, 6 figure 12-3 8-bit event counter mode ti ming chart (tc6) 12.3.3 8-bit programmable divi der output (pdo ) mode (tc5, 6) this mode is used to generate a pu lse with a 50% duty cycle from the pdoj pin. in the pdo mode, the up-counter counts up using the internal clock. when a match between the up-counter and the ttregj value is detected , the logic level output from the pdoj pin is switched to the opposite state and the up-counter is cleared. the inttcj interrupt request is generated at the time. the logic state opposite to the timer f/fj logic level is output from the pdoj pin. an arbitrary value can be set to the timer f/fj by tcjcr. upon reset, the timer f/fj value is initialized to 0. to use the programmable divider output, set the output latch of the i/o port to 1. note 1: in the programmable divider output mode, do not change the ttregj setting while the timer is running. since ttregj is not in the shift register configur ation in the programmable divider output mode, the new value programmed in ttregj is in effect immediatel y after programming. therefore, if ttregi is changed while the timer is running, an ex pected operation may not be obtained. note 2: when the timer is stopped during pdo output, the pdoj pin holds the output status when the timer is stopped. to change the output status, program tcjcr after the timer is stopped. do not change the tcjcr setting upon stopping of the timer. example: fixing the pdoj pin to the high level when the timercounter is stopped clr (tcjcr).3: stops the timer. clr (tcjcr).7: sets the pdoj pin to the high level. note 3: j = 5, 6 example :generating 1024 hz pulse using tc6 (fc = 20.0 mhz) setting port ld (ttreg6), 3dh : 1/1024 2 7 /fc 2 = 3dh ld (tc6cr), 00010001b : sets the operating clock to fc/2 7 , and 8-bit pdo mode. ld (tc6cr), 00011001b : starts tc6. 1 0 2 n-1 n 0 1 2 0 n ? counter match detect counter clear n-1 n 2 0 1 match detect counter clear tc6cr ttreg6 inttc6 interrupt request tc6 pin input
page 116 12. 8-bit timercounter 5,6(tc5, 6) 12.1 configuration TMP88FW45FG figure 12-4 8-bit pdo m ode timing chart (tc6) 12 0 n 0 n 0 n 0 n 0 1 2 2 1 2 1 2 3 1 0 n ? internal source clock counter match detect match detect match detect match detect held at the level when the timer is stopped set f/f write of "1" tc6cr tc6cr ttreg6 timer f/f6 pdo 6 pin inttc6 interrupt request
page 117 TMP88FW45FG 12.3.4 8-bit pulse width modulat ion (pwm) output mode (tc5, 6) this mode is used to generate a pulse-width modulated (pwm) signals with up to 8 bits of resolution. the up-counter counts up using the internal clock. when a match between the up-counter and the pwregj value is detected, the logic level output from the timer f/fj is switched to the opposite state. the counter continues counting. the logic level output from the timer f/fj is switched to the opposite state again by the up-co unter overflow, and the counter is cleared. the inttcj interrupt request is generated at this time. since the initial value can be set to the timer f/fj by tcjcr, positive and negative pulses can be gen- erated. upon reset, the tim er f/fj is cleared to 0. (the logic level output from the pwmj pin is the opposite to the timer f/fj logic level.) since pwregj in the pwm mode is se rially connected to the shift regist er, the value set to pwregj can be changed while the timer is running. the value set to pwregj during a run of the timer is shifted by the inttcj interrupt request and loaded into pwregj. while the timer is stopped, the value is shifted immedi- ately after the programming of pwre gj. if executing the read instruction to pwregj during pwm output, the value in the shift register is read, but not the valu e set in pwregj. therefore, after writing to pwregj, the reading data of pwregj is previo us value until inttcj is generated. for the pin used for pwm output, the output latch of the i/o port must be set to 1. note 1: in the pwm mode, program the timer register pw regj immediately after the inttcj interrupt request is generated (normally in the inttcj interrupt service r outine.) if the programming of pwregj and the inter- rupt request occur at the same time, an unstable value is shifted, that may result in generation of the pulse different from the programmed value until the next inttcj interrupt request is generated. note 2: when the timer is stopped during pwm output, the pwmj pin holds the output status when the timer is stopped. to change the output status, program tcjcr after the timer is stopped. do not change the tcjcr upon stopping of the timer. example: fixing the pwmj pin to the high level when the timercounter is stopped clr (tcjcr).3: stops the timer. clr (tcjcr).7: sets the pwmj pin to the high level. note 3: to enter the stop mode during pwm output, stop the timer and then enter the stop mode. if the stop mode is entered without stopping the timer when fc or fc/2 is selected as the source clock, a pulse is output from the pwmj pin during the warm-up period time after exiting the stop mode. note 4: j = 5, 6 table 12-4 pwm output mode source clock resolution repeated cycle normal, idle mode dv1ck = 0 fc = 20 mhz dv1ck = 1 fc = 20 mhz dv1ck = 0 fc = 20 mhz dv1ck = 1 fc = 20 mhz dv1ck = 0 dv1ck = 1 fc/2 11 [hz] fc/2 12 [hz] 102.4 s 204.8 s 26.21 ms 52.43 ms fc/2 7 fc/2 8 6.4 s 12.8 s 1.64 ms 3.28 ms fc/2 5 fc/2 6 1.6 s3.2 s 410 s819 s fc/2 3 fc/2 4 0.4 s0.8 s 102 s205 s
page 118 12. 8-bit timercounter 5,6(tc5, 6) 12.1 configuration TMP88FW45FG figure 12-5 8-bit pwm mode timing chart (tc6) 1 0 n n+1 ff 0 n n+1 ff 0 1 m m+1 ff 0 1 1 p n ? internal source clock counter m p mp n ? shift registar shift shift shift shift match detect match detect one cycle period match detect match detect n m p n tc6cr tc6cr pwreg6 timer f/f6 pwm 6 pin inttc6 interrupt request write to pwreg6 write to pwreg6
page 119 TMP88FW45FG 12.3.5 16-bit time r mode (tc5 and 6) in the timer mode, the up-counter counts up using the internal clock. the timercounter 5 and 6 are cascad- able to form a 16-bit timer. when a match between the up-counter and the timer regi ster (ttreg5, ttreg6) valu e is detected after the timer is started by setting tc6cr to 1, an inttc 6 interrupt is generated and the up-counter is cleared. after being cleared, the up-counter continues counting. pr ogram the lower byte and upper byte in this order in the timer register. (programming only the uppe r or lower byte should not be attempted.) note 1: in the timer mode, fix tcjcr to 0. if not fixed, the pdoj , pwmj , and ppgj pins may output a pulse. note 2: in the timer mode, do not change the ttregj setting while the timer is running. si nce ttregj is not in the shift register configuration in the timer mode, the new value programmed in ttregj is in effect immediately after programming of ttregj. therefore, if ttreg j is changed while the time r is running, an expected operation may not be obtained. note 3: j = 5, 6 figure 12-6 16-bit timer m ode timing chart (tc5 and tc6) table 12-5 source clock for 16-bit timer mode source clock resolution maximum time setting normal, idle mode dv1ck = 0 fc = 20 mhz dv1ck = 1 fc = 20 mhz dv1ck = 0 fc = 20 mhz dv1ck = 1 fc = 20 mhz dv1ck = 0 dv1ck = 1 fc/2 11 fc/2 12 102.4 s 204.8 s 6.7 s 13.4 s fc/2 7 fc/2 8 6.4 s 12.8 s 419.4 ms 838.8 ms fc/2 5 fc/2 6 1.6 s3.2 s 104.9 s 209.7 ms fc/2 3 fc/2 4 0.4 s0.8 s 26.2 s52.4 ms example :setting the timer mode with source clock fc/2 7 [hz], and generating an interrupt 240 ms later (fc = 20.0 mhz) ldw (ttreg5), 927ch : sets the timer register (300 ms 2 7 /fc = 927ch). di set (eird). ef28 : enables inttc6 interrupt. ei ld (tc5cr), 13h :sets the operating cock to fc/2 7 , and 16-bit timer mode (lower byte). ld (tc6cr), 04h : sets the 16-bit timer mode (upper byte). ld (tc6cr), 0ch : starts the timer. 1 0 2 3 mn-1 mn 0 1 mn-1 mn 2 0 1 2 0 n ? m ? internal source clock counter match detect counter clear match detect counter clear tc6cr ttreg5 (lower byte) inttc6 interrupt request ttreg6 (upper byte)
page 120 12. 8-bit timercounter 5,6(tc5, 6) 12.1 configuration TMP88FW45FG 12.3.6 16-bit event c ounter mode (tc5 and 6) 12.3.7 16-bit pulse wi dth modulation (pwm) ou tput mode (tc5 and 6) this mode is used to generate a pulse-width modulated (pwm) signals with up to 16 bits of resolution. the timercounter 5 and 6 are cascadable to form the 16-bit pwm signal generator. the counter counts up using the internal clock or external clock. when a match between the up-counter and the timer register (pwreg5, pwreg6) value is detected, the logic level output from the timer f/f6 is switched to the opposite state. the counter continues counting. the logic level output from the timer f/f6 is switched to the opposite state again by the counter overflow, and the counter is cleared. the inttc6 interrupt is generated at this time. two machine cycles are required for the high- or low-level pulse input to the tc5 pin. therefore, a maxi- mum frequency to be supplied is fc/2 4 hz in the normal1 or idle1 mode. since the initial value can be set to the timer f/f6 by tc6cr, positive and negative pulses can be generated. upon reset, the timer f/f6 is cleared to 0. (the logic level output from the pwm 6 pin is the opposite to the timer f/f6 logic level.) since pwreg6 and 5 in the pwm mode are serially connected to the shift register, the values set to pwreg6 and 5 can be changed while the timer is runni ng. the values set to pwreg6 and 5 during a run of the timer are shifted by the inttcj interrupt request and loaded into pwreg6 and 5. while the timer is stopped, the values are shifted i mmediately after the programming of pwreg6 and 5. set the lower byte (pwreg5) and upper byte (pwreg5) in this order to program pwreg6 and 5. (programming only the lower or upper byte of the register should not be attempted.) if executing the read instruction to pwreg6 and 5 during pwm output, the values set in the shift register is read, but not the values set in pwreg6 and 5. therefore, after writing to the pwreg6 and 5, reading data of pwreg6 and 5 is previous value until inttc6 is generated. for the pin used for pwm output, the output latch of the i/o port must be set to 1. note 1: in the pwm mode, program the timer register pwreg6 and 5 immediately after the inttc6 interrupt request is generated (normally in the inttc6 interrupt service routine.) if the programming of pwregj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of pulse different from the programmed value until the next inttc6 interrupt request is generated. note 2: when the timer is stopped during pwm output, the pwm 6 pin holds the output status when the timer is stopped. to change the output status, program tc6cr after the timer is stopped. do not program tc6cr upon stopping of the timer. example: fixing the pwm 6 pin to the high level when the timercounter is stopped clr (tc6cr).3: stops the timer. clr (tc6cr).7 : sets the pwm 6 pin to the high level. in the event counter mode, the up-counter counts up at the falling edge to the tc5 pin. the timercounter 5 and 6 are cascadable to fo rm a 16-bit event counter. when a match between the up-counter and the timer register (ttreg5, ttreg6) value is detected after the timer is started by setting tc6cr to 1, an inttc6 interrupt is generated and the up-counter is cleared. after being cleared, the up-counter rest arts counting at the falling edge of the input pulse to the tc5 pin. two machine cycles are required for the low- or high-level pulse input to the tc5 pin. therefore, a maximum frequency to be supplied is fc/2 4 hz in the normal or idle mode. program the lower byte (ttreg5), and upper byte (ttreg6) in this order in the timer register. (programming only the upper or lower byte should not be attempted.) note 1: note 2: note 3: in the event counter mode, fix tcjcr to 0. if not fixed, the pdoj, pwmj and ppgj pins may output pulses. in the event counter mode, do not change the ttregj setti ng while the timer is running. since ttregj is not in the shift register configuration in the event counter mode, the new value programmed in ttregj is in effect imme- diately after the programming. therefore, if ttregj is changed while the timer is running, an expected operation may not be obtained. j = 5, 6
page 121 TMP88FW45FG note 3: to enter the stop mode, stop the timer and then enter the stop mode. if the stop mode is entered with- out stopping of the timer when fc or fc/2 is select ed as the source clock, a pulse is output from the pwm 6 pin during the warm-up period time after exiting the stop mode. table 12-6 16-bit pwm output mode source clock resolution repeated cycle normal, idle mode dv1ck = 0 fc = 20mhz dv1ck = 1 fc = 20mhz dv1ck = 0 fc = 20 mhz dv1ck = 1 fc = 20 mhz dv1ck = 0 dv1ck = 1 fc/2 11 [hz] fc/2 12 [hz] 102.4 s 204.8 s 6.7 s 13.4 s fc/2 7 fc/2 8 6.4 s 12.8 s 419.4 ms 838.8 ms fc/2 5 fc/2 6 1.6 s3.2 s 104.9 ms 209.7 ms fc/2 3 fc/2 4 0.4 s0.8 s 26.2 ms 52.4 ms example :generating a pulse with 1-ms high-level width and a period of 32.768 ms (fc = 20.0 mhz) setting ports ldw (pwreg5), 07d0h : sets the pulse width. ld (tc5cr), 33h : sets the operating clock to fc/2 3 , and 16-bit pwm output mode (lower byte). ld (tc6cr), 056h : sets tff6 to the initial value 0, and 16-bit pwm signal generation mode (upper byte). ld (tc6cr), 05eh : starts the timer.
page 122 12. 8-bit timercounter 5,6(tc5, 6) 12.1 configuration TMP88FW45FG figure 12-7 16-bit pwm mode timing chart (tc5 and tc6) 1 0 an an+1 ffff 0 an an+1 ffff 0 1 bm bm+1 ffff 0 bm cp b c 1 1 cp n a an ? ? ? internal source clock 16-bit shift register shift shift shift shift counter match detect match detect one cycle period match detect match detect an bm cp an m p tc6cr tc6cr pwreg5 (lower byte) timer f/f6 pwm 6 pin inttc6 interrupt request pwreg6 (upper byte) write to pwreg6 write to pwreg6 write to pwreg5 write to pwreg5
page 123 TMP88FW45FG 12.3.8 16-bit programmable pulse generate (ppg) ou tput mode (tc5 and 6) this mode is used to generate pulses with up to 16- bits of resolution. the timer counter 5 and 6 are cascad- able to enter the 16-bit ppg mode. the counter counts up using the inte rnal clock or external clock. when a match between the up-counter and the timer register (pwreg5, pwreg6 ) value is detected, the logic level output from the timer f/f6 is switched to the opposite state. the counter continues counting. the logic level output from the timer f/f6 is switched to the opposite state again when a match betw een the up-counter and th e timer register (ttreg5, ttreg6) value is detected, and the counter is cleared. the inttc6 interrupt is generated at this time. since the initial value can be set to the timer f/f6 by tc6cr, positive and negative pulses can be generated. upon reset, the timer f/f6 is cleared to 0. (the logic level output from the ppg 6 pin is the opposite to the timer f/f6.) set the lower byte and upper byte in this order to program the timer register. (ttreg5 ttreg6, pwreg5 pwreg6) (programming only the upper or lower byte should not be attempted.) for ppg output, set the output latch of the i/o port to 1. note 1: in the ppg mode, do not change the pwregi and ttregi settings while the timer is running. since pwregi and ttregi are not in the shift register c onfiguration in the ppg mode, the new values pro- grammed in pwregi and ttregi are in effect immediately after progra mming pwregi and ttregi. therefore, if pwregi and ttregi are changed whil e the timer is running, an expected operation may not be obtained. note 2: when the timer is stopped during ppg output, the ppg 6 pin holds the output status when the timer is stopped. to change the output status, program tc6cr after the timer is stopped. do not change tc6cr upon stopping of the timer. example: fixing the ppg 6 pin to the high level when the timercounter is stopped clr (tc6cr).3: stops the timer clr (tc6cr).7: sets the ppg 6 pin to the high level note 3: i = 5, 6 example :generating a pulse with 1-ms high-level width and a period of 16.385 ms (fc = 20.0 mhz) setting ports ldw (pwreg5), 07d0h : sets the pulse width. ldw (ttreg5), 8002h : sets the cycle period. ld (tc5cr), 33h : sets the operating clock to fc/2 3 , and16-bit ppg mode (lower byte). ld (tc6cr), 057h : sets tff6 to the initial value 0, and 16-bit ppg mode (upper byte). ld (tc6cr), 05fh : starts the timer.
page 124 12. 8-bit timercounter 5,6(tc5, 6) 12.1 configuration TMP88FW45FG figure 12-8 16-bit ppg mode timing chart (tc5 and tc60) 1 0 mn mn+1 qr-1 mn qr-1 1 mn mn+1 mn+1 0 qr 0 qr 1 0 internal source clock counter write of "0" match detect match detect match detect mn mn mn match detect match detect ? n m ? ? r q ? held at the level when the timer stops f/f clear tc6cr tc6cr pwreg5 (lower byte) timer f/f6 ppg 6 pin inttc6 interrupt request pwreg6 (upper byte) ttreg5 (lower byte) ttreg6 (upper byte)
page 125 TMP88FW45FG 13. motor control circuit (pmd: programmable motor driver) the TMP88FW45FG contains two channels of motor control circuits used for sinusoidal waveform output. this motor control circuit can control brushless dc motors or ac motors with or without sensors. with its primary func- tions like those listed below incorporated in hardware, it helps to accomp lish sine wave motor control easily, with the software load significantly reduced. 1. rotor position detect function ? can detect the rotor position, with or without sensors ? can be set to determine the rotor position when detection matched a number of times, to prevent erro- neous detection ? can set a position detection inhibit period immediately after pwm-on 2. independent timer and timer capture functions for motor control ? contains one-channel magnitude comparison time r and two-channel coinci dence comparison timers that operate synchronously for position detection 3. pwm waveform generating function ? generates 12-bit pwm with 100 ns resolution ? can set a frequency of pwm interrupt occurrence ? can set the dead time at pwm-on 4. protective function ? provides overload protective function based on protection signal input 5. emergency stop function in case of failure ? can be made to stop in an emergency by emg input or timer overflow interrupt ? not easily cleared by software runaway 6. auto commutation/auto position detection start function ? comprised of dual-buffers, can activate auto commutation synchronously with position detection or timer ? can set a position detection period using the timer f unction and start auto position detection at the set time 7. electrical angle timer function ? can count 360 degrees of electrical angle with a set period in the range of 0 to 383 ? can output the counted el ectrical angle to the wave form arithmetic circuit 8. waveform arithmetic circuit ? calculate the output duty cycle fro m the sine wave data and voltage data which are read from the ram based on the elect rical angle timer ? output the calculation result to the waveform synthesis circuit
page 126 13. motor contro l circuit (pmd: programmable motor driver) TMP88FW45FG 13.1 outline of motor control the following explains the method for controlling a brushless dc motor with sine wave drive. in a brushless dc motor, the rotor windings to which to apply electric current are determined from the rotor?s magnetic pole position, and the current-applied windings are ch anged as the rotor turns. the rotor?s magnetic pole position is determined using a sensor such as a hall ic or by detecting polarity ch ange (zero-cross) points of the induced voltage that devel- ops in the motor windings (sensorless control). for the sens orless case, the induced voltage is detected by applying electric current to two phases and not applying electric current to the remaining other phase. in this two-phase cur- rent on case, there are six current ap plication patterns as shown in table 13-1, which are changed synchronously with the phases of the rotor. in this two-phase current on case, the current on time in each phase is 120 degrees rela- tive to 180 degrees of the induced voltage. note: one of the upper or lower transistors is pwm controlled. for brushless dc motors, the number of revolutions is controlled by an applied voltage, and the voltage applica- tion is controlled by pwm. at this time, the current on wi ndings need to be changed in synchronism with the phases of the voltage induced by revolutions. control timing in cases where the current on wi ndings are changed by means of sensorless control is illustrated in figure 13-4. for thr ee-phase motors, zero-crossing occurs six times during one cycle of the induced voltage (electrical angle 360 degrees), so that the elect rical angle from on e zero-cross point to the next is 60 degrees. assuming that this period comprises one mode, the rotor position can be divided into six modes by zero-cross points. the six current application pa tterns shown above correspond one for one to these six modes. the timing at which the curr ent application patterns are changed (c ommutation) is out of phase by 30 degrees of electrical angle, wi th respect to the position det ection by an induced voltage. mode time is obtained by detecting a zero-cross point at some timing and finding an elapsed time from the preced- ing zero-cross point. because mode time co rresponds to 60 degrees of electrical angle, the following applies for the case illustrated in figure 13-4. 1. current on windings changeover (commutation) timing 30 degrees of electrical angle = mode time/2 2. position detection start timing 45 degrees of electrical angle = mode time 3/4 3. failure determination timing 120 degrees of electrical angle = mode time 2 timings are calculated in this way. the position detection start timing in 2 is needed to prevent erroneous detec- tion of the induced voltage for reasons th at even after current appl ication is turned off, th e current continues flowing due to the motor reactance. control is exercised by calculating the above timings successively for each of the zero-cross points detected six times during 360 degrees of electrical angle and activating commutation, position detection start, and other opera- tions according to that timing. in this way, operations can be synchronized to the phases of the induced voltage of the motor. the timing needed for motor control as in this example can be set freely as desired by using the internal timers of the microcontroller?s pmd unit. also, sine wave control requires controlling the pwm duty cycle for each pulse. co ntrol of pwm duty cycles is accomplished by counting degrees of electrical angle and cal culating the sine wave data and voltage data at the counted degree of electrical angle. table 13-1 current application patterns current application pattern upper transistor lower transistor current on winding uvwxyz mode 0 on off off off on off u v mode 1 on off off off off on u w mode 2 off on off off off on v w mode 3 off on off on off off v u mode 4 off off on on off off w u mode 5 off off on off on off w v
page 127 TMP88FW45FG figure 13-1 conceptual di agram of dc motor control figure 13-2 example of sensorle ss dc motor control timing chart
! " # $
%

% %
&% ' (' %%
)
%
%
& * '
! " # $ %&'() $&% () '% *%

page 128 13. motor contro l circuit (pmd: programmable motor driver) TMP88FW45FG 13.2 configuration of t he motor control circuit the motor control circuit consists of various units. these include a position de tection unit to det ect the zero-cross points of the induced voltage or position sensor signal, a timer unit to generate events at three instances of electrical angle timing, and a three-phase pwm output unit to produ ce three-phase output pwm wave forms. also included are an electrical angle timer unit to count degrees of electrical angle and a waveform arithmetic unit to calculate sinuso- idal waveform output duty cycles. the input/output units ar e configured as shown in the diagram below. when using ports for the pmd function, set the port input/output contro l register (p3cri and p5cri) to 0 for the input ports, and for the output ports, set the data output latch (p3i and p5i) to 1 and then the port input/output control register to 1. other input/output ports can be set in the same way for use of the pmd function. figure 13-3 block diagram of the mo tor control circuit note 1: always use the ldw instruction to set data in the 9, 12 and 16-bit data registers. note 2: the emg circuit initially is ena bled. for pmd output, fix the emg input port (p36 and p51) "h" high level or dis- able the emg circuit before using for pmd output. note 3: the emg circuit initially is enabled. when using port p3 and p5 as input/output io ports, disable emg. note 4: when going to stop mode, be sure to turn all of the pmd functions off before entering stop mode.

! "
page 129 TMP88FW45FG 13.3 position detection unit the position detection unit identifies the motor's rotor position from input patterns on the position signal input port. applied to this position signal input port is the volta ge status of the motor windin gs for the case of sensorless dc motors or a hall element signal fo r the case of dc motors with sensors included. the expect ed patterns corre- sponding to specific rotor positions are set in the pmd ou tput register (mdout) beforehand, and when the input position signal and the expected value ma tch as the rotation, a position detec tion interrupt (intpdc) is generated. also, unmatch detection mode is used to detect the direction of motor rotation, where when the stat us of the position detection input port changes from the status in which it was at start of sampling, a position detection interrupt is gen- erated. for three-phase brushless dc motors, there are six patte rns of position signals, one for each mode, as summarized in table 13-2 from the timing chart in figure 13-2. once a predicted position signal pattern is set in the mdout register, a position detection interrupt is generated the moment the position signal input port goes to mode indicated by this expected value. th e position signals at each phase in the di agram are internal signals which cannot be observed from the outside. table 13-2 position signal input patterns position detection mode u phase (pdu) v phase (pdv) w phase (pdw) mode 0 h l h mode 1 h l l mode 2 h h l mode 3 l h l mode 4 l h h mode 5 l l h
page 130 13. motor contro l circuit (pmd: programmable motor driver) TMP88FW45FG 13.3.1 configuration of the position detection unit figure 13-4 configuration of the position detection circuit ? the position detection unit is controlled by the position detection control register (pdcra, pdcrb). after the position de tection function is enab led, the unit starts sa mpling the position detec- tion port with timer 2 or in software. for the case of ordinary mode, when the status of the position detection input port matches the expected value of the pmd output register, the unit generates a posi- tion detection interrupt and finishes sampling, waiting for start of the next sampling. ? when unmatch detection mode is selected for position detection, the unit stores the sampled status of the position detection port in memory at the time it started sampling. when the port input status changes from the status in which it was at st art of sampling, an interrupt is generated. ? in unmatch detection mode, the port status at start of sampling can be read (pdcrc). ? when starting and stopping position detection synchronously with the timer, position detection is started by timer 2 and position detection is stopped by timer 3. ? sampling mode can be selected from three modes available: mode where sampling is performed only while pwm is on, mode where sens ors such as hall elements are sa mpled regularly, and mode where sampling is performed while the lower side is conducting current (when performing sampling only while pwm is on, duty must be set for all three phas es in common). ? when sampling mode is selected for detecting pos ition while the lower phases are conducting current, sampling is performed for a period from when the set sampling delay time has elapsed after the lower side started conducting current till when the current appli cation is turned off. sampling is performed independently at each phase, and the sampling result is retained while sampling is idle. if while sam- pling at some phase is idle, the input and the expected value at other phase being sampled match, posi- tion is detected and an interrupt is generated.

! " # " "$ $

%$$!& '
%$ ' ' (
'
)

'

'

* ' )

(+ ,-,.,,&,,/,0 0 1 / & 2, -, ., 3 &, , /, 0 ., 2, - (, , "$
page 131 TMP88FW45FG ? a sampling delay is provided for use in modes where sampling is made while pwm is on or the lower phases are conducting current. it he lps to prevent erroneous detection due to noise that occurs immedi- ately after the transistor turns on, by starting sampling a set time after the pwm signal turned on. ? when detecting position while pwm is on or the lowe r phases are conducting current, a method can be selected whether to recount occurrences of matche d position detection after being compared for each pwm signal on (logical sum of three-phase pwm signals ) (e.g., starting from 0 in each pwm cycle) or counting occurrences of matching continuously ( pd crb is used to enable/disable recount- ing occurrences of matching while pwm is on). 13.3.2 position detection circuit regist er functions pdcrc 5, 4 emem hold result of position detec- tion at pwm edge (detect position detected position) these bits hold the comparison result of position detection at falling or rising edge of pwm pulse. bits 5 and 4 are set to 1 when positi on is detected at the falling or the rising edge, respectively. they show whether position is detected in the current pwm pulse, during pwm off, or in the immediately preceding pwm pulse. 3 smon monitor sampling status when read, this bit shows the sampling status. 2 to 0 pdtct hold position signal input sta- tus this bit holds the status of the position signal input at the time position detection started in unmatch mode. pdcrb 7, 6 splck sampling period select fc/2 2 , fc/2 3 , fc/2 4 , or fc/2 5 for the position detection sampling period. 5, 4 splmd sampling mode select one of three modes: sampling only w hen pwm signal is active (when pwm is on), sampling regularly, or sampling when the lower side (x, y, z) phases are conducting cur- rent. 3 to 0 pdcmp sampling count in ordinary mode, when the port status a nd the set expected value match and continu- ously match as many times as the sampling counts set, a position detection signal is out- put and an interrupt is generated. in unmatch detection mode, when the said status and value do not match and continuously unmatch as many times as the sampling counts set, a position detection signal is output and an interrupt is generated. pdcra 7 swstp stop sampling in software sampling can be stopped in software by setting this bit to 1 (e.g., by writing to this regis- ter). sampling is performed before stopping and when position detection results match, a posi- tion detection interrupt is generated, with sampling thereby stopped. 6 swstt start sampling in software sampling can be started by sett ing this bit to 1 (e.g., by writing to this register). 5 sptm3 stop sampling using timer 3 sampling can be stopped by a trigger from timer 3 by setting this bit to 1. sampling is performed before stopping and when position detection results match, a posi- tion detection interrupt is generated, with sampling thereby stopped. 4 sttm2 start sampling using timer 2 sampling can be started by a trigger from timer 3 by setting this bit to 1. 3 pdnum number of position signal input pins select whether to use three pins (pdu/pdv/pdw) or one pin (pdu only) for position sig- nal input. when one pin is selected, the expected values of pdv and pdw are ignored. when performing position detection with two pins or a pin other than pdu, position signal input can be masked as 0 by se tting unused pin(s) for output. 2rcen recount occurrences of matching when pwm is on when performing sampling while pwm is on, occurrences of matching are recounted each time pwm signal turns on by setting th is bit to 1 (when recounting occurrences of matching, the count is reset each time pwm turns off). when this bit is set to 0, occur- rences of matching are counted cont inuously regardless pwm interval. 1 dtmd position detection mode setting this bit to 0 selects ordinary mode w here position is detected when the expected value set in the register and the port input unmatch and then match. setting this bit to 1 selects unmatch detection mode where position is detected at the time the port status changes to another one from the status in which it was when sampling started. 0 pdcen position detection function the position detection fu nction is activated by setting this bit to 1.
page 132 13. motor contro l circuit (pmd: programmable motor driver) TMP88FW45FG figure 13-5 position detect ion sampling timing with the pwmon period selected figure 13-6 detection timing of the position detection position sdreg 6 to 0 sdreg sampling delay set a time for which to stop sampling in orde r to prevent erroneous detection due to noise that occurs immediately after pwm output tu rns on (immediately after the transistor turns on). (figure 13-5)

!! "#$ % %$& '#$ '#$ #( '#$
! " #$ !& ' # () * * * * * ** * (++ % !' # ,- % $ ** * *
page 133 TMP88FW45FG note: when changing setting, keep the pdcen bit reset to ?0? (disable position detection function). note: read-modify-write instructions, such as a bit manipulatio n instruction, cannot access t he pdcra because it contains a write only bit. position detection circuit registers [addresses (pmd1 and pmd2)] pdcrc (01fa2h) (01fd2h) 76543210 ? ? emem smon pdtct (initial value: **00 0000) 5, 4 emem hold result of position detection at pwm edge (detect position detected position) 00: detected in the current pulse 01: detected while pwm off 10: detected in the current pulse 11: detected in the preceding pulse r 3 smon monitor sampling status 0: sampling idle 1: sampling in progress 2 to 0 pdtct hold position signal input sta- tus holds the status of the position signal input during unmatch detection mode. bits 2 to 0 correspond to w, v, and u phases. pdcrb (01fa1h) (01fd1h) 76543210 splck splmd pdcmp (initial value: 0000 0000) 7, 6 splck select sampling input clock 00: fc/2 2 [hz] (200 ns at 20 mhz) 01: fc/2 3 (400 ns at 20 mhz) 10: fc/2 4 (800 ns at 20 mhz) 11: fc/2 5 (1.6 s at 20 mhz) r/w 5, 4 splmd sampling mode 00: sample when pwm is on 01: sample regularly 10: sample when lower phases conducting current 11: reserved 3 to 0 pdcmp position detection matched counts 1 to 15 times (counts 0 and 1 are assumed to be one time.) pdcra (01fa0h) (01fd0h) 76543210 swstp swstt sptm3 sttm2 pdnum rcen dtmd pdcen (initial value: 0000 0000) 7 swstp stop sampling in software 0: no operation 1: stop sampling w 6 swstt start sampling in software 0: no operation 1: start sampling 5 sptm3 stop sampling using timer 3 0: disable 1: enable r/w 4 sttm2 start sampling using timer 2 0: disable 1: enable 3 pdnum number of position signal input pins 0: compare three pins (pdu/pdv/pdw) 1: compare one pin (pdu) only 2 rcen recount occurrences of match- ing when pwm is on 0: continue counting from previously pwm on 1: recount each time pwm turns on 1 dtmd position detection mode 0: ordinary mode 1: unmatch detection mode 0 pdcen enable/disable position detec- tion function 0: disable 1: enable (sampling starts)
page 134 13. motor contro l circuit (pmd: programmable motor driver) TMP88FW45FG note: when changing setting, keep the pdcen bit reset to ?0? (disable position detection function). 13.3.3 outline processing in the position detection unit sdreg (01fa3h) (01fd3h) 76543210 ? d6 d5 d4 d3 d2 d1 d0 (initial value: *000 0000) 6 to 0 sdreg sampling delay 2 3 /fc n bits (n = 0 to 6, maximum 50.8 s, resolution of 400 ns at 20 mhz) r/w

!" !#$ %& !& "'

(

)

*
!"

page 135 TMP88FW45FG 13.4 timer unit figure 13-7 timer circuit configuration the timer unit has an up counter (mode timer) which is cleared by a position detection interrupt (intpdc). using this counter, it can generate three types of timer interrup ts (inttmr1 to 3). these timer interrupts may be used to produce a commutation trigger, position detection start trigger, etc. also, the mode timer has a capture function which automatically captures register data in synchronism with position detection or overload protection. this cap- ture function allows motor revolutions to be calculated by measuring position detection intervals.

!

"# $ "# # % ! !& "# $ # $ &' ( )*+*, *
* * - ,
* * ) . /( 0
0 /( ! ! /( -! /( !

page 136 13. motor contro l circuit (pmd: programmable motor driver) TMP88FW45FG 13.4.1 configuration of the timer unit the timer unit consists mainly of a mode timer, thr ee timer comparator, and mode capture register, and is controlled by timer control regist ers and timer compare registers. ? the mode timer can be reset by a signal from the position detection circuit, timer 3, or overload pro- tective circuit. if the mode timer overflows without being reset, it stops at ffffh and sets an overflow flag in the control register. ? the value of the mode timer during counting can be read by capturing the coun t in software and read- ing the capture register. ? timer 1 and timers 2 and 3 generate an interrup t signal by magnitude comparison and matching com- parison, respectively. therefore, timer 1 can genera te an interrupt signal even when it could not write to the compare register in time a nd the counter value at the time of writing happens to exceed the regis- ter?s set value. ? when any one of timers 1 to 3 interrupts occurs, the next interrupts can be enabled by writing a new value to the respective compare registers (cmp1, cmp2, cmp3). ? when capturing by position detection is enabled, the capture register has the timer value captured in it each time position is detected. in this way, the capture register always holds the latest value.
page 137 TMP88FW45FG 13.4.1.1 timer circuit register functions figure 13-8 dbout de bug output diagram mtcrb 7 dbout debug output debug output can be produced by setting this bit to 1. because interrupt signals to the interrupt control circuit are used for each interrupt, hardware debugging without software delays are possible. see the debug output diagram (figure 13-8). output ports: p67 for pmd1, p77 for pmd2. 5 tmof mode timer overflow this bit shows that the timer has overflowed. 3clcp capture mode timer by over- load protection when this bit is set to 1, the timer valu e can be captured using the overload protection signal (cl) as a trigger. 2swcp capture mode timer in soft- ware when this bit is set to 1, the timer value can be captured in software (e.g., by writing to this register). 1 pdccp capture mode timer by posi- tion detection when this bit is set to 1, the timer value can be captured using the position detection sig- nal as a trigger. mtcra 7, 6, 5 tmck select clock select the timer clock. 4rbtm3 reset mode timer from timer 3 when this bit is set to 1, the mode time r is reset by a trigger from timer 3. 3rbcl reset mode timer by over- load protection when this bit is set to 1, the mode timer is re set by the overload protection signal (cl) as a trigger. 2 swres reset mode timer in software when this bit is set to 1, the mode timer is rese t in software (e.g., by writing to this regis- ter) 1rbpdc reset mode timer by position detection when this bit is set to 1, the mode timer is re set by the position detection signal as a trig- ger. 0 tmen enable/disable mode timer the mode timer is started by setting this bit to 1. therefore, timers 1 to 3 must be set with cmp before setting this bit. if this bit is set to 0 after setting cmp, cmp settings become ineffective. mcap mode capture position detection interval can be read out. cmp1 timer 1 (commutation) timers 1 to 3 are enabled while the mode timer is operating. an interrupt can be gener- ated once by setting the corresponding bit in th is register. the interrupt is disable when an interrupt is generated or the timer is reset. to use the timer again, set the register back again even if data is same. cmp2 timer 2 (position detection start) cmp3 timer 3 (overflow)

page 138 13. motor contro l circuit (pmd: programmable motor driver) TMP88FW45FG note: read-modify-write instructions, such as a bit manipulation instruction, cannot access the mtcrb because it contains a write-only bit. note 1: when changing mtcra setting, keep the mt cra bit reset to ?0? (disable mode timer). note 2: read-modify-write instructions, such as a bit manipulation instruction, cannot access the mtcra because it contains a write-only bit. timer circuit registers [addresses (pmd1 and pmd2)] mtcrb (01fa5h) (01fd5h) 76543210 dbout ? tmof ? clcp swcp pdccp ? (initial value: 0*0*0 000*) 7 dbout debug output 0: disable 1: enable (p67 for pmd1, p77 for pmd2) r/w 5 tmof mode timer overflow 0: no overflow 1: overflowed r 3clcp capture mode timer by over- load protection 0: disable 1: enable r/w 2 swcp capture mode timer in software 0: no operation 1: capture w 1 pdccp capture mode timer by position detection 0: disable 1: enable r/w mtcra (01fa4h) (01fd4h) 76543210 tmck rbtm3 rbcl swres rbpdc tmen (initial value: 0000 0000) 7, 6, 5 tmck select clock 000: fc/2 3 (400 ns at 20 mhz) 010: fc/2 4 (800 ns at 20 mhz) 100: fc/2 5 (1.6 s at 20 mhz) 110: fc/2 6 (3.2 s at 20 mhz) 001: fc/2 7 (6.4 s at 20 mhz) 011: reserved 101: reserved 111: reserved r/w 4 rbtm3 reset mode timer from timer 3 0: disable 1: enable 3rbcl reset mode timer by overload protection 0: disable 1: enable 2 swres reset mode timer in software 0: no operation 1: reset w 1rbpdc reset mode timer by position detection 0: disable 1: enable r/w 0 tmen enable/disable mode timer 0: disable 1: enable timer start mcap (01fa7h, 01fa6h) (01fd7h, 01fd6h) fedcba9876543210 (initial value: 0000 0000 0000 0000) df de dd dc db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mcap mode capture position detection interval r cmp1 (01fa9h, 01fa8h) (01fd9h, 01fd8h) fedcba9876543210 (initial value: 0000 0000 0000 0000) df de dd dc db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cmp2 (01fabh, 01faah) (01fdbh, 01fdah) fedcba9876543210 (initial value: 0000 0000 0000 0000) df de dd dc db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
page 139 TMP88FW45FG note: read-modify-write instructions, such as a bit manipula tion instruction, cannot access the mtcrb or mtcra register because these registers contain write-only bits. 13.4.1.2 outline processing in the timer unit cmp3 (01fadh, 01fach) (01fddh, 01fdch) fedcba9876543210 (initial value: 0000 0000 0000 0000) df de dd dc db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cmp1 timer 1 magnitude comparison compare register r/w cmp2 timer 2 matching comparison compare register cmp3 timer 3 matching comparison compare register

!
" #

# !

# $ $ !

%
&%

'
( !()
*
*

*
*

+
*

+

%

!
%
! ,

page 140 13. motor contro l circuit (pmd: programmable motor driver) TMP88FW45FG 13.5 three-phase pwm output unit the three-phase pwm output unit has the function to generate three-phase pwm waves with any desired pulse width and the commutation function capable of brushless dc motor control. in addition, it has the protective func- tions such as overload prot ection and emergency stop functi ons necessary to protect th e power drive unit, and the dead time adding function which helps to prevent the in-phase upper/lower transistors from getting shorted by simul- taneous turn-on when switched over. for the pwm output pin (u,v,w,x,y,z), set the port register pxdr and pxcr (x = 3,5) to 1. the pwm output initially is set to be active low, so that if the output needs to be used active high, set up the mdcra register accord- ingly. 13.5.1 configuration of the three-phase pwm output unit the three-phase pwm output unit consists of a pulse width modulation circuit, commutation control circuit, protective circuit (emergency stop and over load), and a dead time control circuit. 13.5.1.1 pulse width modulation circuit (pwm waveform generating unit) this circuit produces three-phase independent pw m waveforms with an equal pwm frequency. for pwm waveform mode, triangular wave modulation or sawtooth wave modulation can be selected by using the pmd control register (mdcra) bit 1. the pwm frequency is set by using the pmd period register (mdprd). the following shows the relationshi p between the value of this register and the pwm counter clock set by the mdcrb register, pwmck. the pmd period register (mdprd) is comprised of dual-buffers, so that cmpu, v, w register is updated with pwm period. when the waveform arithmetic ci rcuit is operating, the pwm wavefo rm output unit r eceives calculation results from the waveform arithmetic circuit and by us ing the results as cmpu, v, w register set value, it outputs independent three-phase pwm waveforms. wh en the waveform calculati on function is enabled by the waveform arithmetic circuit and transfer of calculation results into the cmpu to w registers is enabled (with edcra register bit 2), the cmpu to w registers are disa bled against writing. when the waveform calculation func tion is enabled (with edcra regist er bit 1) and transfer of calcu- lation results into the cmpu, v, w registers is disabled (with edcra register bit 4), the calculation results are transferred to the buffers of cmpu, v, w registers, but not output to the port. read-accessing the cmpu, v, and w registers can read the calculation results of the waveform arith- metic circuit that have been input to a buffer. afte r changing the read calculation result data by software, writing the changed data to the cmpu, v, and w regi sters enables an arbitrar y waveform other than a sinusoidal wave to be output. when the registers are r ead after writing, the values written to the registers are read out if accessed before th e calculation results are transferre d after calculation is finished. triangular wave pwm: mdprd register set value 1 pwm frequency hz ] [ 2p wmck ---------------------------------------------------------------------------------------------- = sawtooth wave pwm: mdprd register set value 1 pwm frequency hz ] [ pwmck ------------------------------------------------------------------------------------ - =
page 141 TMP88FW45FG figure 13-9 pwm waveforms the values of the pwm compare registers (cmpu/v/ w) and the carrier wave generated by the pwm counter (mdcnt) are compared for the relative magnitude by the comparator to produce pwm wave- forms. the pwm counter is a 12-bit up/down counter with a 100 ns (at fc = 20 mhz) resolution. for three-phase output control, two methods of generating three-phase pwm waveforms can be set. 1. three-phase independent mode: values are set independently in the three-phase pmd compare registers to produce three-phase independent pwm waveforms. this method may be used to produce sinusoidal or any other desired drive waveforms. 2. three-phase common mode: a valu e is set in only the u-phase pmd compare register to pro- duce three in-phase pwm waveforms using the u ph ase set value. this method may be used for dc motor square wave drive. the three-phase pmd compare regist ers each have a comparison regi ster to comprise a dual-buffer structure. the values of the pmd co mpare registers are loaded into th eir respective comparison registers synchronously with pwm period.

page 142 13. motor contro l circuit (pmd: programmable motor driver) TMP88FW45FG 13.5.1.2 commutation control circuit output ports are controlled depending on the conten ts set in the pmd output register (mdout). the contents set in this register are divided into two, one for selecting the synchronizing signal for port output, and one for setting up port output. the synchronizing signal can be selected from timers 1 or 2, position detection signal, or without sync. port output can be synchronized to this synchronizing signal before being further synchronized to the pwm signal sync. the mdout register's synchronizing signal select bit becomes effective immediately after writing. othe r bits are dual-buffered, and are updated by the selected synchronizing signal. example: commutation timing for one timer period with pwm synchronization specified output on six ports can be set to be active high or active low independently of each other by using the mdcra register bits 5 and 4. furthermore, the u, v, and w phases can individu ally be selected between pwm output and h/l output by using the mdout register bits a to 8 and 5 to 0. when pwm output is selected, pwm waveforms are output; when h/l output is selected, a waveform which is fixed high or low is output. the mdout register bits e to c set the expected position sign al value for the position detection circuit. figure 13-10 pulse width modulation circuit inttmr pwm commutation 3 selector/ latch pwm control pwm interrupt intpwm clock selector pmd period register pmd compare register pwm counter pwm control register ? ? 3, 2, 1 7 60 mdcra b to 0 mdprd b to 0 mdcnt 1 to 0 mdcrb b to 0 cmpu b to 0 cmpw b to 0 cmpv buffer w buffer v buffer u selector/ latch three-phase common/ three-phase up/down pwmu pwmv pwmw stop mdcnt pwm synchronizing clock fc/2
page 143 TMP88FW45FG figure 13-11 commutation control circuit figure 13-12 dead time circuit s selector s selector gate control set reset latch 6 3 2 mdout 5, 4, 3, 2, 1, 0 a, 9, 87, 6 ? b ? , ? , ? mdout sync fc/4 pwm synchronizing clock position detection interrupt intpdc timer 1 interrupt inttmr1 timer 2 interrupt inttmr2 pmd output register u x v y w z pwmu pwmv pwmw

! " # $%& ' ( )% * *(*'*+*,*-*.
page 144 13. motor contro l circuit (pmd: programmable motor driver) TMP88FW45FG 13.5.2 register functions of the waveform synthesis circuit mdcrb pwmck select pwm counter cloc k select pwm counter clock. mdcra 7 hlfint select half-period interrupt when this bit is set to 1, intpwm is generated every half period (at triangular wave peak and valley) in the case of center pwm output and pint = 00. in other cases, this setting has no meaning. 6 dtymd duty mode select whether to set the duty cycle independent ly for three phases using the cmpu to w registers or in common for all three phases by setting the cmpu register only. 5 polh upper-phase port polarity select the upper-phase output port polarity. make sure the waveform synthesis function (mdcra register bit 0) is idle before selecting this port polarity. 4 poll lower-phase port polarity select the lower-phase output port polarity. make sure the waveform synthesis function (mdcra register bit 0) is idle before selecting this port polarity. 3, 2 pint pwm interrupt frequency select the frequency at which to generate a pwm interrupt from four choices available: every pwm period or once every 2, 4, or 8 pwm periods. when setting of this bit is altered while operating, an interrupt may be generated at the time the bit is altered. 1 pwmmd pwm mode select pwm mode. pwm mode 0 is an edge pwm (sawtooth wave), and pwm mode 1 is a center pwm (triangular wave). 0pwmen enable/disable waveform generation circuit when enabling this circuit (for waveform output), be sure to set the output port polarity and other bits of this register (other than mdcra bit 0) beforehand. dtr dtr dead time set the dead time between the upper-phase and lower-phase outputs. mdout f updwn pwm counter flag this bit indicates whether the pwm counter is counting up or down. when edge pwm (sawtooth wave) is selected, it is always set to 0. e, d, c pdexp mode compare register set the data to be compared with the position detection input port. the comparison data is adopted as the expected value simultaneously when port output sync settings made with mdout are reflected in the ports. (this is the expected position detection inpu t value for the output set with mdout next time.) b psync select pw m synchronization select whether or not to synchronize port output to pwm period after being synchronized to the synchronizing signal selected with syncs. if selected to be synchronized to pwm, output is kept waiting for the next pwm after being synchronized with syncs. waveform settings are overwritten if new settings are written to the register during this time, and out- put is generated with those settings. a 9 8 wpwm vpwm upwm control uvw-phase pwm outputs set u, v, and w-phase port outputs. (see the table 13-3) 7, 6 syncs select port output sync signal select the synchronizing signal with which to output uvw-phase settings to ports. the synchronizing signal can be selected from time rs 1 or 2, position detection, or asynchro- nous. select asynchronous when the initial setting, otherwise the above setting isn?t reflected immediately. 5, 4 3, 2 1, 0 woc voc uoc control uvw-phase outputs set u, v, and w-phase port outputs. (see the table 13-3) mdcnt pwm counter this is a 12-bit read-only register used to count pwm periods. mdprd set pwm period this register determines pwm period, and is dual-buffered, allowing pwm period to be altered even while the pwm counter is operating. the buffers are loaded every pwm period. when 100 ns is selected for the pwm counter clock, make sure the least signifi- cant bit is set to 0.
page 145 TMP88FW45FG note: when changing setting, keep the pwmen bit reset to ?0? (disable wave form synthesis function). note: when changing setting, keep the mdcr a bit reset to "0" (disabl e wave form synthesis function). cmpu cmpv cmpw set pwm pulse width this comparison register determines the pulse widths output in the respective uvw phases. this register is dual-buffered, and the pulse widths are determined by comparing the buffer and pwm counter. waveform synthesis circuit registers [addresses (pmd1 and pmd2)] mdcrb (01fafh) (01fdfh) 76543210 ? ? ? ? ? ? pwmck (initial value: **** **00) 1, 0 pwmck pwm counterselect clock 00: fc/2 [hz] (100 ns at 20 mhz) 01: fc/2 2 (200 ns at 20 mhz) 10: fc/2 3 (400 ns at 20 mhz) 11: fc/2 4 (800 ns at 20 mhz) r/w mdcra (01faeh) (01fdeh) 765432 1 0 hlfint dtymd polh poll pint pwmmd pwmen (initial value: 0000 0000) 7 hlfint select half-period interrupt 0: interrupt as specified in pint 1: interrupt every half period when pint = 00 r/w 6 dtymd duty mode 0: u phase in common 1: three phases independent 5 polh upper-phase port polarity 0: active low 1: active high 4 poll lower-phase port polarity 0: active low 1: active high 3, 2 pint select pwm interrupt (trigger) 00: interrupt every period 01: interrupt once every 2 periods 10: interrupt once every 4 periods 11: interrupt once every 8 periods 1 pwmmd pwm mode 0: pwm mode0 (edge: sawtooth wave) 1: pwm mode1 (center: triangular wave) 0pwmen enable/disable waveform syn- thesis function 0: disable 1: enable (waveform output) dtr (01fbeh) (01feeh) 76543210 ? ? d5 d4 d3 d2 d1 d0 (initial value: **00 0000) 5 to 0 dtr dead time 2 3 /fc 6 bit (maximum 25.2 s at 20 mhz) r/w
page 146 13. motor contro l circuit (pmd: programmable motor driver) TMP88FW45FG 13.5.3 port output as se t with uoc/voc/woc bits and upwm/vpwm/wpwm bits mdout (01fb3h, 01fb2h) (01fe3h, 01fe2h) fedcba98 updwn pdexp psync wpwm vpwm upwm 76543210 syncs woc voc uoc (initial value: 00000000 00000000) f updwn pwm counter flag 0: counting up 1: counting down r e, d, c pdexp comparison register for posi- tion detection bit e: w-phase expected value bit d: v-phase expected value bit c: u-phase expected value r/w b psync select pwm synchronization 0: asynchronous 1: synchronized a wpwm w-phase pwm output 0: h/l level output 1: pwm waveform output 9 vpwm v-phase pwm output 0: h/l level output 1: pwm waveform output 8 upwm u-phase pwm output 0: h/l level output 1: pwm waveform output 7, 6 syncs select port output synchronizing signal 00: asynchronous 01: synchronized to position detection 10: synchronized to timer 1 11: synchronized to timer 2 5, 4 woc control w-phase output see the table 1-3 3, 2 voc control v-phase output 1, 0 uoc control u-phase output table 13-3 example of pin output settings u-phase output polarity: active high (polh,poll = 1) u-phase output polarity: active low (polh,poll = 0) uoc upwm uoc upwm 1: pwm output 0: h/l level output 1: pwm output 0: h/l level output u phase x phase u phase x phas e u phase x phase u phase x phase 0 0 pwm pwm l l 0 0 pwm pwm hh 0 1 l pwm l h 0 1 h pwm hl 1 0 pwm l h l 1 0 pwm hlh 1 1 pwm pwm hh 1 1 pwm pwm l l
page 147 TMP88FW45FG mdcnt (01fb5h, 01fb4h) (01fe5h, 01fe4h) fedcba9876543210 (initial value: ****000000000000) ? ? ? ? db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 b to 0 pwm counter pwm period counter value r mdprd (01fb7h, 01fb6h) (01fe7h, 01fe6h) fedcba9876543210 (initial value: ****000000000000) ? ? ? ? db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 b to 0 pwm period pwm period mdprd 010h r/w cmpu (01fb9h, 01fb8h) (01fe9h, 01fe8h) fedcba9876543210 (initial value: ****000000000000) ? ? ? ? db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cmpv (01fbbh, 01fbah) (01febh, 01feah) fedcba9876543210 (initial value: ****000000000000) ? ? ? ? db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cmpw (01fbdh, 01fbch) (01fedh, 01fech) fedcba9876543210 (initial value: ****000000000000) ? ? ? ? db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 b to 0 cmpu pwm compare u register set u-phase duty cycle r/w cmpv pwm compare v register set v-phase duty cycle cmpw pwm compare w register set w-phase duty cycle
page 148 13. motor contro l circuit (pmd: programmable motor driver) TMP88FW45FG 13.5.4 protective circuit this circuit consists of an emg prot ective circuit and ov erload protective ci rcuit. these circ uits are activated by driving their respective port inputs active. figure 13-13 configuration of the protective circuit a. emg protective circuit this protective circuit is used for emergency st op, when the emg protec tive circuit is enabled. when the signal on emg input port goes active (negative edge triggered), the six ports are immedi- ately disabled high-impedance against output and an emg interrupt (intemg) is generated. the emg control register (emgcra) is used to set emg protection. if the emgcra shows the value ?1? when read, it means that the em g protective circuit is operating. to return from the emg protective state, reset the mdout register bits a to 0 and set the emgcra to 1. returning from the emg protectiv e state is effective when the emg protective input has been released back high. to disable the emg functio n, set data ?5ah? and ?a5h?sequentially in the emg disable register (emgrel) and reset th e emgcra to 0. when the emg func- tion is disabled, emg interrupt s (intemg) are not generated. the emg protective circuit is initially enabled. before disabling it, fully study on adequacy. b. overload protective circuit the overload protective circuit is set by using the emg control registers (emgcra/b). to acti- vate overload protection, set the emgcrb to 1 to enable the overlo ad protective circuit. the circuit starts operating when the overload protective input is pulled low. to return from overload st ate, there are three methods to use: return by a timer (emgcrb), return by pwm sync (emgcrb), or return manually (emgcrb). these methods are usable wh en the overload protective input has been released back high. cl detection reset control emg protective control timer 1 interrupt inttmr1 pwm synchronizing clock pwm sync overload protective interrupt intclm overload protective input cl stop mdcnt u x v y w z u' x' v' y' w' z' emg disable code register emg control register 210 ? 7, 6, 5, 4 emgcra 3, 2, 1, 0 7 emgcrb 4 6, 5 emgrel 7, 6, 5, 4, 3, 2, 1, 0 mdout a to 0 2 2 4 4 8 overload protective control set "0" emg emg input intemg emg interrupt under prote- ction
page 149 TMP88FW45FG the number of times the overload protective input is sampled can be set by using the emgcra. the sampling times can be set in the range of 1 to 15 times at 200 ns period (when fc = 20 mhz). if a low level is detected as many times as the specified number, overload pro- tection is assumed. the output disabled phases dur ing overload protection are set by using the emgcrb. this facility allows selecting to disable no phas es, all phases, pwm phases, or all upper phases/all lower phases. when selected to disable all upper phases/all lower phases, port output is determined by their turn-on status immediately before being disabled. when two or more upper phases are active, all upper phases are turned on and all lower phases are turned off; when two or more lower phases are active, all upper ph ases are turned off and all lower phases are turned on. when output phase are cut off, output is inactive (low in the ca se of high active). when the over- load protective circuit is disabled, overload pr otective interrupts (intclm) are not generated. figure 13-14 example of pr otection circuit operation

!! "
page 150 13. motor contro l circuit (pmd: programmable motor driver) TMP88FW45FG 13.5.5 functions of prot ective circuit registers emgrel emg disable the emg protective circuit is disable from t he disabled state by writing ?5ah? and ?a5h? to this register in that order. after that, the emgcra register needs to be set. emgcrb 7rtcl return from overload protec- tive state when this bit is set to 1, the motor control ci rcuit is returned from overload protective state in software (e.g., by writing to this register). also, the current state can be known by read- ing this bit. mdout outputs at return from the overload protective state remain as set before the overload protective input was driven active. 6 rtpwm return by pwm sync when this bit is set to 1, the motor control ci rcuit is returned from overload protective state by pwm sync. if rtcl is set to 1, rtcl has priority. 5 rttm1 return by timer sync when this bit is set to 1, the motor control ci rcuit is returned from overload protective state by timer 1 sync. if rtcl is set to 1, rtcl has priority. 4 clst overload protective state the status of over load protection can be know n by reading this bit. 3, 2 clmd select output disabled phases during overload pro- tection select the phases to be disabled against out put during overload prot ection. this facility allows selecting to disable no phases, all pha ses, pwm phases, or all upper phases/all lower phases. 1cntst stop counter during overload protection can stop the pwm counter during overload protection. 0clen enable/disable overload pro- tection enable or disable the overload protective function. emgcra 7 to 4 clcnt overload protection sampling time set the length of time the overload protective input port is sampled. 2 emgst emg protective state the status of emg protection can be known by reading this bit. 1rte return from emg protective state the motor control circuit is returned from emg protective state by setting this bit to ?1? . when returning, set the mdout register a to 0 bits to ?0? . then set the emgcra reg- ister bit 1 to ?1? and set mdout waveform output. then set up the mdcra register. 0emgen enable/disable emg protec- tive circuit the emg protective circuit is activated by setting this bit to 1. this circuit initially is enabled. (to disable this circuit, make sure key code 5ah and a5h are written to the emgrel1 register beforehand.)
page 151 TMP88FW45FG note: read-modify-write instructions, such as a bit manipulation instruction, cannot access the emgrel register because this register is write only. note: if during overload protection the port output state in two or more upper phases is on, all lo wer phases are disabled and a ll upper phases are enabled for output; when two or more lowe r phases are on, all upper phases are disabled and all lower phases are enabled for output. note 1: an instruction specifying a return from the emg state is invalid if the emg input is ?l?. note 2: read-modify-write instructions, such as a bit manipulation instruction, cannot access the emgcrb or emgcra register because these registers c ontain write-only bits. protective circuit registers [addresses (pmd1 and pmd2)] emgrel (01fbfh) (01fefh) 76543210 d7 d6 d5 d4 d3 d2 d1 d0 (initial value: 0000 0000) 7 to 0 emgrel emg disable can disable by writing 5ah and then a5h. w emgcrb (01fb1h) (01fe1h) 765432 1 0 rtcl rtpwm rttm1 clst clmd cntst clen (initial value: 0000 0000) 7rtcl return from overload protec- tive state 0: no operation 1: return from protective state w 6rtpwm enable/disable return from overload protective state by pwm sync 0: disable 1: enable r/w 5 rttm1 enable/disable return from overload protective state by timer 1 0: disable 1: enable 4 clst overload protective state 0: no operation 1: under protection r 3, 2 clmd select output disabled phases during overload protection 00: no phases disabled against output 01: all phases disabled against output 10: pwm phases disabled against output 11: all upper/all lower phases disabled against output (note) r/w 1 cntst stop pwm counter during over- load protection 0: do not stop 1: stop the counter 0clen enable/disable overload pro- tective circuit 0: disable 1: enable emgcra (01fb0h) (01fe0h) 765432 1 0 clcnt emgst rte emgen (initial value: 0000 *001) 7 to 4 clcnt overload protection sampling number of times. 2 2 /fc n ( n = 1 to 15, 0 and 1 are set as 1 at 20 mhz ) r/w 2 emgst emg protective state 0: no operation 1: under protection r 1 rte return from emg state 0: no operation 1: return from protective state (note 1) w 0emgen enable/disable emg protective circuit 0: disable 1: enable r/w
page 152 13. motor contro l circuit (pmd: programmable motor driver) TMP88FW45FG 13.6 electrical angle timer and waveform arithmetic circuit electrical angle timer figure 13-15 electric al angle timer circuit waveform arithmetic circuit figure 13-16 waveform arithmetic circuit

! " " " #" $ %& !" $" '" #" " (" " " ) *+ , - )
.

. / . .
!"#$ %&' (% !"#$ &
) *+#*) ,
- .*)

/*)

0*)

&'/ &'. &'0
) 1233 $ # " ! 04&5 5% $ # 5( / 5%& #" 6 $ #
page 153 TMP88FW45FG 13.6.1 electrical angle timer and waveform arit hmetic circuit the electrical angle timer finishes counting upon reaching the value set by the period set register (edset). the electrical angle timer counts 360 degrees of electrical angle in the range of 0 to 383 (17fh) and is cleared to 0 upon reaching 383. in this way, it is possible to obtain the elect rical angle of the frequency proportional to the value set by the period set register. the period with which to count up can be corrected by using the period correction register, allowing for fine adjustment of the freque ncy. the electrical angles counted by the electrical angle timer are presented to the waveform arithmetic circuit. an electrical angle timer interrupt signal is gene rated each time the electrical a ngle timer finishes counting. the waveform arithmetic circuit has a sine wave data table, which is used to extract sine wave data based on the electrical angle data received fr om the electrical angle timer. this sine wave data is multiplied by the value of the voltage amplitude register. for 2-phase modulation, the product obtained by this multiplication is presented to the waveform synthesis circuit. for 3- phase modulation, waveform data is further calculated based on the product of multiplication and the electrical angle data and the value of the pwm period register. the calculation is performed each time the electrical angle timer finishes counting or when a value is set in the electrical angle regist er, and the calculation results consisting of the u phase, the v phase ( + 120 degrees), and the w phase ( + 240 degrees) are sequentially presented to the pwm waveform output circuit. the sine wave data table is stored in the ram and requires initialization. ? to correct the period, set the number of times ?n? to be corrected in the period correction register (edset register f to c bits). the period is corrected by adding 1 to electrical angle c ounts 16 for ?n? times. for example, when a value 3 is set in the period correction register, the period for 13 times out of electrical angle counts 16 is the value ?mh? set in the period set register, and that for 3 times is ?m + 1h?. (correction is made almost at equal intervals.) ? because the electrical angle count er (eldeg) can be accessed even while the electrical angle timer is operating, the electri cal angles can be corr ected during operation. ? the electrical angle capture ed cap captures the electrical angle value from the electrical angle counter at the time the position is detected. ? when the waveform calculation func tion is enabled, waveform calcu lation is performed each time the electrical angle counter (eldeg) ar e accessed for write or the electri cal angle timer finishes count- ing. ? the calculation is performed in 35 machine cycl e of execution time, or 7 s (at 20 mhz). ? when transfer of calculation result to the cmp registers is enabled (edcra), the calcula- tion results are transferred to the cmpu to w regi sters. (this applies only when the waveform calcu- lation function is enabled with the edcra.) the cmpu to w registers are disabled against write while the tran sfer remains enabled. the calculation re sults can be read from the cmpu to w registers while the waveform calculation function remains enabled. ? the calculated results can be modifi ed and the modified data can be se t in the cmpu to w registers in software. this makes it possible to output any desired waveform other than sine waves. if a transfer (edcra register bit 2) of the calculated results to th e cmp register is disabled, read- accessing the cmpu to w registers can read the calcu lated results. (before read-accessing these regis- ters, make sure that the calculation is completed.) ? to initialize the entire ram data of the sine wave da ta table, set the addresses at which to set, sequen- tially from 000h to 17fh, in the eldeg register, and write waveform data to the wfmdr register each time. make sure the waveform arithmetic circuit is disabled wh en writing this data. note 1: the value set in the period set register (edset register edt bits) must be equal to or greater than 010h. any value smaller than this is assumed to be 010h. note 2: the sine wave data that is read consists of t he u phase, the v phase whose electrical angle is +120 degrees relative to the u phase, and the w phase whose electrical angle is +240 degrees relative to the u phase. note 3: if a period corresponding to an electrical angle of on e degree is shorter than the required calculation time, the previously calculated results are used.
page 154 13. motor contro l circuit (pmd: programmable motor driver) TMP88FW45FG 13.6.1.1 functions of the electrical angle ti mer and waveform arithmetic circuit registers edcrb 3 calcst start calculation by software forcefully start calculation. when this bit is written while the waveform arithmetic circuit is calculating, the calculation is terminated and then newly started. 2 calcbsy calculation flag by reading this bit, the operation status of the waveform arithmetic circuit can be obtained. 1 edcalen enable/disable calculation start synchronized with elec- trical angle select whether to start calculation when the electrical angle timer finishes counting or when a value is set in the electrical angle r egister. when disabled, calculation is only started when calcst is set to 1. 0 edisel electrical angle interrupt set the electrical angle interrupt signal req uest timing to either when the electrical angle timer finishes counting or upon end of calculation. edcra 7 edcnt electrical angle count up/ down set whether the electrical angle timer counts up or down. 6 edrv select v-, w-phase select phase direction of v-phase and w-phase in relation to u-phase. 5, 4 edck select clock select the clock for the electrical angle time r. this setting can be altered even while the electrical angle timer is operating. 3 c2pen switch between 2-phase and 3-phase modulations select the modulation method with wh ich to perform waveform calculation. two-phase modulation data = ramdata (eldeg) amp note: the sign during 3-phase modulati on changes depending on the electrical angle. + for el ectrical angles 0 to 179 degrees (191) ? for electrical angles 180 (192) to 360 (383) degrees 2rwren auto transfer calculation results to cpm registers enable/disable transfer of calculation results by the waveform arithmetic circuit. when the waveform calculation function is enabled while at the same time transfer is enabled, cal- culation results are set as u, v, and w-phas e duty cycles of the pwm generation circuit and are reflected in the ports. 1calcen enable/disable waveform cal- culation function enable/disable the waveform calculation func tion. calculations are performed by the waveform arithmetic circuit by enabling the waveform calculation function. when the waveform calculation function is enabled, the calculated results can be read from the u, v, and w-phase compare registers (cmpu, v, w) of the pwm generation circuit. 0 edten electrical angle timer enable/disable the electrical angle timer. w hen enabled, the electrical angle timer starts counting; when disabled, the electrical angl e timer stops counting and is cleared to 0. edset f to c edth correct electrical angle period correct the period by adding 1 to electrical angl e counts 16 for ?n? times. the timer counts the electrical angle period set value ?m??for (16 ? n) times and counts (m + 1) for ?n? times b to 0 edt electrical angle period set the electrical angle period. eldeg electrical angle read the electrical angle. this register can also be set to initialize or correct the angle while counting. any value greater than 17fh cannot be set. amp set voltage amplitude set the voltage amplitude. the waveform arithmetic circuit multiplies the data set here by the sine wave data read out from the sine wave ram. the amplitude has its upper limit determined by the set value of the mdprd register when performing this multiplication. edcap capture electrical angle capture the value from the electrical angle timer when the position is detected. wfmdr set sine wave data to initialize the entire ram data of the sine wave table, set the addresses at which to set, sequentially from 000h to 17fh, in the eldeg register, and write waveform data to the wfmdr register each time. make sure the waveform arithmetic circuit is disabled when writing this data. three-phase modulation: data moprd 2 ---------------------- - ramdata eldeg () amp 2 -------------------------------------------------------------------- - =
page 155 TMP88FW45FG typical settings of sine wave data note: during 3-phase modulation, the sign changes at 180 degrees of electrical angle. figure 13-17 typical sett ings of sine wave data

! " " "" " #$#% #&& ( ! " " "" " #$#% #&& (
page 156 13. motor contro l circuit (pmd: programmable motor driver) TMP88FW45FG note: read-modify-write instructions, such as a bit manipulation instruction, cannot access the edcrb register because this reg- ister is write only. note: when changing the edcra setting, keep the edcra bit reset ?0? (disable electrical angle timer). list of the electrical angle timer and waveform arit hmetic circuit registers [addresses (pmd1 and pmd2)] edcrb (01fc1h) (01ff1h) 76543210 ? ? ? ? calcst calcbsy edcalen edisel (initial value: **** 0000) 3 calcst start calculation by software 0: no operation 1: start calculation w 2 calcbsy calculation flag 0: waveform arithmetic circuit stopped 1: waveform arithmetic circuit calculating r 1 edcalen enable/disable calculation start synchronized with electrical angle 0: start calculation insync with electrical angle 1: do notcalculation insync with electrical angle r/w 0 edisel electrical angle interrupt 0: interrupt when the electrical angle timer finishes counting 1: interrupt upon end of calculation edcra (01fc0h) (01ff0h) 765432 1 0 edcnt edrv edck c2pen rwren calcen edten (initial value: 0000 0000) 7 edcnt electrical angle count up/down 0: count up 1: count down r/w 6 edrv select v-, w-phase 0: v = u + 120 , w = u + 240 1: v = u ? 120 , w = u ? 240 5, 4 edck select clock 00: fc/2 3 (400 ns at 20 mhz) 01: fc/2 4 (800 ns at 20 mhz) 10: fc/2 5 (1.6 s at 20 mhz) 11: fc/2 6 (3.2 s at 20 mhz) 3c2pen switch between 2-/3-phase modulations 0: 2-phase modulation 1: 3-phase modulation 2rwren transfer calculation result to cmp registers 0: disable 1: enable 1calc enable/disable waveform cal- culation function 0: disable 1: enable 0edten electrical angleenable/disable mode timer 0: disable 1: enable
page 157 TMP88FW45FG one period of the electrical angle timer, t, is expressed by the equation below. note: read-modify-write instructions, such as a bit manipulation instruction, cannot access the wfmdr register because this register is write only. edset (01fc3h, 01fc2h) (01ff3h, 01ff2h) fedcba9876543210 (initial value: 00000000 00010000) edth edt f to c edth correct period (n) 0 to 15 times r/w b to 0 edt set period (m) 010h eldeg (01fc5h, 01fc4h) (01ff5h, 01ff4h) fedcba9876543210 (initial value: *******0 00000000) ???????d8d7d6d5d4d3d2d1d0 8 to 0 eldeg electrical angle set the initially and the count values of electrical angle. r/w amp (01fc7h, 01fc6h) (01ff7h, 01ff6h) fedcba9876543210 (initial value: ****0000 00000000) ? ? ? ? db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 b to 0 amp set voltage set the voltage to be used during waveform calculation. r/w edcap (01fc9h, 01fc8h) (01ff9h, 01ff8h) fedcba9876543210 (initial value: ******0 00000000) ???????d8d7d6d5d4d3d2d1d0 8 to 0 edcap captured value of electrical angle electrical angle timer val ue when position is detected. r wfmdr (01fcah) (01ffah) 76543210 d7 d6 d5 d4 d3 d2 d1 d0 (initial value: ********) 7 to 0 wfmdr sine wave data write sine wave data to ram of sine wave w tm n 16 ----- - + ?? ?? 384 set clock s [] where m set period, n period correction = = =
page 158 13. motor contro l circuit (pmd: programmable motor driver) TMP88FW45FG 13.6.1.2 list of pmd related control registers (1) input/output pins and input/output control registers pmd1 input/output pins (p3, p4) and port input/output control registers (p3cr, p4cr) pmd2 input/output pins (p5, p1) and port input/output control registers (p5cr, p1cr) note: when using these pins as pmd function or input port, set the output latch (p*dr) to 1. example of the pmd pin port setting name address bit r or w description p3dr 00003h 7 r/w overload protection ( cl1 ) 6 r/w emg input ( emg1 ) 5 to 0 r/w u1/v1/w1/x1/y1/z1 outputs. p4dr 00004h 2 to 0 r/w position signal inputs (pdu1, pdv1, pdw1). p3cr 01f89h 7 to 0 r/w p3 port input/output control (can be set bitwise). 0: input mode 1: output mode p4cr 01f8ah 2, 1, 0 r/w p0 port input/output control (can be set bitwise). 0: input mode 1: output mode name address bit r or w description p5dr 00005h 0 r/w overload protection ( cl2 ) 1 r/w emg input ( emg2 ) 2 to 7 r/w u2/v2/w2/x2/y2/z2 outputs. p1dr 00001h 5 to 7 r/w position signal inputs (pdu2, pdv2, pdw2). p5cr 01f8bh 7 to 0 r/w p3 port input/output control (can be set bitwise). 0: input mode 1: output mode p1cr 0000bh 5, 6, 7 r/w p0 port input/output control (can be set bitwise). 0: input mode 1: output mode input/output p3dr p3cr p4dr p4cr cl1 input * 0 ? ? emg1 input * 0 ? ? u1output11?? pdu1 input ? ? * 0 input/output p5dr p5cr p1dr p1cr cl2 input * 0 ? ? emg2 input * 0 ? ? u2output11?? pdu2 input ? ? * 0
page 159 TMP88FW45FG (2) motor control circu it control registers [address upper stage: pmd1, lower stage: pmd2] position detection control register (pd cr) and sampling delay register (sdreg) name address bit r or w description pdcrc 01fa2h 01fd2h 5, 4 r detect the position-detected position. 00: within the current pulse 01: when pwm is off 10: within the current pulse 11: within the preceding pulse 3r monitor the sampling status. 0: sampling idle 1: sampling in progress 2 to 0 r holds the status of the position signal input during unmatch detection mode. bits 2, 1, and 0: w, v, and u phases pdcrb 01fa1h 01fd1h 7, 6 r/w select the sampling input clock [hz]. 00: fc/2 2 01: fc/2 3 10: fc/2 4 11: fc/2 5 5, 4 r/w sampling mode. 00: when pwm is on 01: regularly 10: when lower phases are turned on 3 to 0 r/w detection position match counts 1 to 15. pdcra 01fa0h 01fd0h 7w 0: no operation 1: stop sampling in software 6w 0: no operation 1: start sampling in software 5r/w stop sampling using timer 3. 0: disable 1: enable 4r/w start sampling using timer 2. 0: disable 1: enable 3r/w number of position signal input pins. 0: compare three pins (pdu/pdv/pdw) 1: compare one pin (pdu) only 2r/w count occurrences of matching when pwm is on. 0: subsequent to matching counts when pwm previously was on 1: eecount occurrences of matching each time pwm is on 1r/w position detection mode. 0: ordinary mode 1: unmatch detection mode 0r/w enable/disable position detection function. 0: disable 1: enable (sampling starts) sdreg 01fa3h 01fd3h 6 to 0 r/w sampling delay. 2 3 /fc n bits (n = 0 to 6, maximum 50.8 s at 20 mhz).
page 160 13. motor contro l circuit (pmd: programmable motor driver) TMP88FW45FG mode timer control register (mtcr), mode ca pture register (mcap), and compare registers (cmp1, cmp2, cmp3) name address bit r or w description mtcrb 01fa5h 01fd5h 7r/w debug output. 0: disable 1: enable (p67 for pmd1, p77 for pmd2) 5r mode timer overflow. 0: no overflow 1: overflowed occurred 3r/w capture mode timer by overload protection. 0: disable 1: enable 2w capture mode timer by software. 0: no operation 1: capture 1r/w capture mode timer by position detection. 0: disable 1: enable mtcra 01fa4h 01fd4h 7, 6, 5 r/w select clock for mode timer [hz]. 000: fc/2 3 (400 ns at 20 mhz) 010: fc/2 4 (800 ns at 20 mhz) 100: fc/2 5 (1.6 s at 20 mhz) 110: fc/2 6 (3.2 s at 20 mhz) 001: fc/2 7 (6.4 s at 20 mhz) 011: reserved 101: reserved 111: reserved 4r/w reset timer by timer 3. 0: disable 1: enable 3r/w reset timer by overload protection. 0: disable 1: enable 2w reset timer by software. 0: no operation 1: reset 1r/w reset timer by position detection. 0: disable 1: enable 0r/w enable/disable mode timer. 0: disable 1: enable (timer starts) mcap 01fa7h, 01fa6h 01fd7h, 01fd6h f to 0 r mode capture register. cmp1 01fa9h, 01fa8h 01fd9h, 01fd8h f to 0 r/w compare register 1. cmp2 01fabh, 01faah 01fdbh, 01fdah f to 0 r/w compare register 2. cmp3 01fadh, 01fach 01fddh, 01fdch f to 0 r/w compare register 3.
page 161 TMP88FW45FG pmd control register (mdcr), dead time register (dtr), and pmd output register (mdout) name address bit r or w description mdcrb 01fafh 01fdfh 1, 0 r/w select clock for pwm counter. 00: fc/2 (100 ns at 20 mhz) 01: fc/2 2 (200 ns at 20 mhz) 10: fc/2 3 (400 ns at 20 mhz) 11: fc/2 4 (800 ns at 20 mhz) mdcra 01faeh 01fdeh 7r/w select half-period interrupt 0: interrupt every period as specified in pint. 1: interrupt every half-period only pint=00. 6r/w duty mode. 0: u phase in common 1: three phases independent 5r/w upper-phase port polarity. 0: active low 1: active high 4r/w lower-phase port polarity. 0: active low 1: active high 3, 2 r/w select pwm interrupt (trigger). 00: interrupt once every period 01: interrupt once 2 periods 10: interrupt once 4 periods 11: interrupt once 8 periods 1r/w pwm mode. 0: pwm mode0 (edge: sawtooth wave) 1: pwm mode1 (center: triangular wave) 0r/w enable/disable waveform synthesis function. 0: disable 1: enable (waveform output) dtr 01fbeh 01feeh 5 to 0 r/w set dead time. 2 3 /fc 6bit (maximum 25.2 s at 20 mhz). mdout 01fb3h, 01fb2h 01fe3h, 01fe2h fr 0: count up 1: count down e, d, c r/w comparison register for position detection. 6: w 5: v 4: u br/w select pwm synchronization. 0: asynchronous with pwm period 1: synchronized ar/w w-phase pwm output. 0: h/l level output 1: pwm waveform output 9r/w v-phase pwm output. 0: h/l level output 1: pwm waveform output 8r/w u-phase pwm output. 0: h/l level output 1: pwm waveform output 7, 6 r/w select port output synchronizing signal. 00: asynchronous 01: synchronized to position detection 10: synchronized to timer 1 11: synchronized to timer 2 5, 4 r/w control w-phase output 3, 2 r/w control v-phase output 1, 0 r/w control u-phase output
page 162 13. motor contro l circuit (pmd: programmable motor driver) TMP88FW45FG pwm counter (mdcnt), pmd period regist er (mdprd), and pm d compare registers (cmpu, cmpv, cmpw) emg disable code register (emgrel) and emg control register (emgcr) name address bit r or w description mdcnt 01fb5h, 01fb4h 01fe5h, 01fe4h b to 0 r read the pwm period counter value. mdprd 01fb7h, 01fb6h 01fe7h, 01fe6h b to 0 r/w pwm period mdprd 010h. cmpu 01fb9h, 01fb8h 01fe9h, 01fe8h b to 0 r/w set u-phase pwm duty cycle. cmpv 01fbbh, 01fbah 01febh, 01feah b to 0 r/w set v-phase pwm duty cycle. cmpw 01fbdh, 01fbch 01fedh, 01fech b to 0 r/w set w-phase pwm duty cycle. name address bit r or w description emgrel 01fbfh 01fefh 7 to 0 w code input for disable emg protection circuit. can be disable by writing 5ah and then a5h. emgcrb 01fb1h 01fe1h 7w return from overload protective state. 0: no operation 1: return from protective state 6r/w condition for returning from overload protective state: synchronized to pwm. 0: disable 1: enable 5r/w enable/disable return from overload protective state by timer 1. 0: disable 1: enable 4r overload protective state. 0: no operation 1: under protection 3, 2 r/w select output disabled phases during overload protection. 00: no phases disabled against output 01: all phases disabled against output 10: pwm phases disabled against output 11: all upper/all lower phases disabled against output 1r/w stop pwm counter (mdcnt) during overload protection. 0: do not stop 1: stop 0r/w enable/disable overload protective circuit. 0: disable 1: enable emgcra 01fb0h 01fe0h 7 to 4 r/w overload protection sampling time. 2 2 /fc n (n = 1 to 15, at 20 mhz) 2r emg protective state. 0: no operation 1: under protection 1w return from emg protective state. 0: no operation 1: return from protective state 0r/w enable/disable fanction of the emg protective circuit. 0: disable 1: enable (this circuit initially is enabled (= 1) . to disable this circuit, make sure key code 5ah and a5h are written to the emgrel1 register before- hand.)
page 163 TMP88FW45FG electrical angle control register (edcr), electrical angle peri od register (e dset), electrical angle set register (eldeg), voltage set regist er (amp), and electrical angle capture register (edcap). name address bit r or w description edcrb 01fc1h 01ff1h 3w 0: no operation 1: start calculation 2r 0: waveform arithmetic circuit stopped 1: waveform arithmetic circuit calculatin 1r/w 0: start calculation insync with electrical angle 1: do not calculation insync with electrical angle 0r/w 0: interrupt when the electrical angle timer finishes counting 1: interrupt upon end of calculation edcra 01fc0h 01ff0h 7r/w 0: count up 1: count down 6r/w 0: v = u + 120 , w = u + 240 1: v = u ? 120 , w = u ? 240 5, 4 r/w select clock. 00: fc/2 3 01: fc/2 4 10: fc/2 5 11: fc/2 6 3r/w switch between 2/3-phase modulations. 0: two-phase modulation 1: three-phase modulation 2r/w transfer calculation result to cmp registers. 0: disable 1: enable 1r/w enable/disable waveform calculation function. 0: disable 1: enable 0r/w electrical angle timer. 0: disable 1: enable edset 01fc3h, 01fc2h 01ff3h, 01ff2h f to c r/w correct period (n) 0 to 15 times. b to 0 r/w set period (1/m counter) 010h eldeg 01fc5h, 01fc4h 01ff5h, 01ff4h 8 to 0 r/w initially set and count values of electrical angle. amp 01fc7h, 01fc6h 01ff7h, 01ff6h b to 0 r/w set voltage used during waveform calculation. edcap 01fc9h, 01fc8h 01ff9h, 01ff8h 8 to 0 r electrical angle timer value when position is detected. wfmdr 01fcah 01ffah 7 to 0 w set sine wave data.
page 164 13. motor contro l circuit (pmd: programmable motor driver) TMP88FW45FG
page 165 TMP88FW45FG 14. asynchronous serial interface (uart1) the TMP88FW45FG has a asynchronous serial interface (uar t) . it can connect the pe ripheral circuits through txd and rxd pin. txd and rxd pin are also used as th e general port. for txd pin, the corresponding general port should be set output mode (set its output control regist er to "1" after its output port latch to "1"). for rxd pin, should be set input mode. the asynchronous serial interface (uar t1) can select the connection pin with the peripheral circuits. rxd1 and txd1 are correspond to p44 and p45 pins, rxd2 and txd2 are to p00 and p01 pins. but the synchronous serial interface (sio) also use p44 and p45 pi ns, therefore these p44 and p45 are not available for uart when sio is on working. 14.1 configuration figure 14-1 uart1 (asynchronous serial interface) counter y a b c s s a b c d y e f g h uart status register uart control register 2 uart pin select register irda output control register uart control register 1 transmit data buffer receive data buffer fc/13 fc/26 fc/52 fc/104 fc/208 fc/416 fc/96 stop bit parity bit fc/2 6 fc/2 7 fc/2 8 rxd1 rxd2 txd1 txd2 baud rate generator transmit/receive clock 2 4 3 2 2 2 noise rejection circuit irda control irdacr uartsel shift register transmit control circuit receive control circuit shift register m p x m p x m p x mpx: multiplexer uartcr1 tdbuf rdbuf inttxd intrxd uartsr uartcr2 inttc4
page 166 14. asynchronous serial interface (uart1) 14.2 control TMP88FW45FG 14.2 control uart1 is controlled by the uart1 control registers (uartcr1, uartcr2). the operating status can be monitored using the uart status register (uartsr). txd pin and rxd pin can be selected a port assi gnment by uart pin select register (uartsel). note 1: when operations are disabled by setting uartcr1 bits to ?0?, the setting becomes valid when data transmit or receive complete. when the transmit data is stor ed in the transmit data buffer, the data are not transmitted. even if data transmit is enabled, until new data are written to the transmit data buffer, the current data are not transmitted. note 2: the transmit clock and the parity are common to transmit and receive. note 3: uartcr1 and uartcr1 should be set to ?0? before uartcr1 is changed. note 4: in case fc = 20mhz, the timer counter 4 (tc4) is available as a baud rate generator. note: when uartcr2 = ?01?, pulses longer than 96/fc [s] are always regarded as signals; when uartcr2 = ?10?, longer than 192/fc [s]; and when uart cr2 = ?11?, longer than 384/fc [s]. uart1 control register1 uartcr1 (01f91h) 76543210 txe rxe stbt even pe brg (initial value: 0000 0000) txe transfer operation 0: 1: disable enable write only rxe receive operation 0: 1: disable enable stbt transmit stop bit length 0: 1: 1 bit 2 bits even even-numbered parity 0: 1: odd-numbered parity even-numbered parity pe parity addition 0: 1: no parity parity brg transmit clock select 000: 001: 010: 011: 100: 101: 110: 111: fc/13 [hz] fc/26 fc/52 fc/104 fc/208 fc/416 input inttc4 fc/96 uart1 control register2 uartcr2 (01f92h) 7654321 0 rxdnc stopbr (initial value: **** *000) rxdnc selection of rxd input noise rejectio time 00: 01: 10: 11: no noise rejection (hysteresis input) rejects pulses shorter than 31/fc [s] as noise rejects pulses shorter than 63/fc [s] as noise rejects pulses shorter than 127/fc [s] as noise write only stopbr receive stop bit length 0: 1: 1 bit 2 bits
page 167 TMP88FW45FG note: when an inttxd is generated, tbep flag is set to "1" automatically. note 1: do not change uartsel register during uart operation. note 2: set uartsel register before performing the setti ng terminal of a i/o port when changing a terminal. uart1 status register uartsr (01f91h) 76543210 perr ferr oerr rbfl tend tbep (initial value: 0000 11**) perr parity error flag 0: 1: no parity error parity error read only ferr framing error flag 0: 1: no framing error framing error oerr overrun error flag 0: 1: no overrun error overrun error rbfl receive data buffer full flag 0: 1: receive data buffer empty receive data buffer full tend transmit end flag 0: 1: on transmitting transmit end tbep transmit data buffer empty flag 0: 1: transmit data buffer full (transmit data writing is finished) transmit data buffer empty uart1 receive data buffer rdbuf (01f93h) 76543210read only (initial value: 0000 0000) uart1 transmit data buffer tdbuf (01f93h) 76543210write only (initial value: 0000 0000) uart pin select register uartsel (01f90h) 76543210 txd sel rxd sel (initial value: **** **00) rxdsel rxd connect pin select 0: 1: rxd1 rxd2 r/w txdsel txd connect pin select 0: 1: txd1 txd2
page 168 14. asynchronous serial interface (uart1) 14.3 transfer data format TMP88FW45FG 14.3 transfer data format in uart1, an one-bit start bit (low level), stop bit (b it length selectable at high level, by uartcr1), and parity (select parity in uartcr1; even- or odd-numbered parity by uartcr1) are added to the transfer data. the transfer da ta formats are shown as follows. figure 14-2 tran sfer data format figure 14-3 caution on c hanging transfer data format note: in order to switch the transfer data format, perfor m transmit operations in the above figure 14-3 sequence except for the initial setting. start bit 0 bit 1 bit 6 bit 7 stop 1 start bit 0 bit 1 bit 6 bit 7 stop 1 stop 2 start bit 0 bit 1 bit 6 bit 7 parity stop 1 start bit 0 bit 1 bit 6 bit 7 parity stop 1 stop 2 pe 0 0 1 1 stbt frame length 0 1 123 89101112 0 1 without parity / 1 stop bit with parity / 1 stop bit without parity / 2 stop bit with parity / 2 stop bit
page 169 TMP88FW45FG 14.4 transfer rate the baud rate of uart1 is set of uartcr1. the example of the baud rate are shown as follows. when inttc4 is used as the uart1 transfer rate (when uartcr1 = ?110?), the transfer clock and transfer rate are de termined as follows: transfer clock [hz] = tc4 sour ce clock [hz] / tc4dr setting value transfer rate [baud] = transfer clock [hz] / 16 14.5 data sampling method the uart1 receiver keeps sampling input using the clock selected by uartcr1 until a start bit is detected in rxd pin input. rt clock star ts detecting ?l? level of the rxd pin. once a start bit is detected, the start bit, data bits, stop bi t(s), and parity bit are sampled at three times of rt7, rt8, and rt9 during one receiver clock interval (rt clock). (rt0 is the position where the bit supposedly starts.) bit is determined according to majority rule (the data are the same twice or more out of three samplings). figure 14-4 data sampling method table 14-1 transfer rate (example) brg source clock 16 mhz 8 mhz 000 76800 [baud] 38400 [baud] 001 38400 19200 010 19200 9600 011 9600 4800 100 4800 2400 101 2400 1200 rt0 1 2 3 4 5 6 7 8 9101112 1314 15 01234567891011 bit 0 start bit bit 0 start bit (a) without noise rejection circuit rt clock internal receive data rt0 1 2 3 4 5 6 7 8 9101112 1314 15 01234567891011 bit 0 start bit bit 0 start bit rt clock internal receive data (b) with noise rejection circuit rxd pin rxd pin
page 170 14. asynchronous serial interface (uart1) 14.6 stop bit length TMP88FW45FG 14.6 stop bit length select a transmit stop bit length (1 bit or 2 bits) by uartcr1. 14.7 parity set parity / no parity by uartcr1 and set parity type (odd- or even-numbered) by uartcr1. 14.8 transmit/receive operation 14.8.1 data transmit operation set uartcr1 to ?1?. read uartsr to check ua rtsr = ?1?, then write data in tdbuf (transmit data buffer). writing data in tdbuf zero- clears uartsr, transfer s the data to the trans- mit shift register and the data are sequentially output from the txd pin. the data output include a one-bit start bit, stop bits whose number is specified in uartcr1 and a parity bit if pari ty addition is specified. select the data transfer baud rate using uartcr1. when data transmit st arts, transmit buffer empty flag uartsr is set to ?1? a nd an inttxd interrupt is generated. while uartcr1 = ?0? and from when ?1? is written to uartcr1 to when send data are written to tdbuf, the txd pin is fixed at high level. when transmitting data, first read uartsr, then write data in tdbuf. otherwise, uartsr is not zero-cleared and tran smit does not start. 14.8.2 data receive operation set uartcr1 to ?1?. when data are received vi a the rxd pin, the receive data are transferred to rdbuf (receive data buffer). at this time, the data transmitted includes a start bit and stop bit(s) and a parity bit if parity addition is specified. when stop bit(s) are received, data only are extracted and transferred to rdbuf (receive data buffer). then the receive buffer full flag ua rtsr is set and an intrxd interrupt is generated. select the data transfer baud rate using uartcr1. if an overrun error (oerr) occurs when data are received, the da ta are not transferre d to rdbuf (receive data buffer) but discarded; data in the rdbuf are not affected. note:when a receive operation is disabled by setting ua rtcr1 bit to ?0?, the setting becomes valid when data receive is completed. however, if a framing error occurs in data receive, the receive-disabling setting may not become valid. if a framing error occurs , be sure to perform a re-receive operation.
page 171 TMP88FW45FG 14.9 status flag 14.9.1 parity error when parity determined using the receive data bits diff ers from the received parity bit, the parity error flag uartsr is set to ?1?. the uartsr is cl eared to ?0? when the rdbuf is read after read- ing the uartsr. figure 14-5 generati on of parity error 14.9.2 framing error when ?0? is sampled as the stop bit in the receive data, framing error flag uartsr is set to ?1?. the uartsr is cleared to ?0? when the rdbuf is r ead after reading the uartsr. figure 14-6 generati on of framing error 14.9.3 overrun error when all bits in the next data are received while unread data are still in rdbuf, overrun error flag uartsr is set to ?1?. in this case, the receive data is discarded; data in rdbuf are not affected. the uartsr is cleared to ?0? when the rdbuf is read af ter reading the uartsr. parity stop shift register pxxxx0 * 1pxxxx0 xxxx0 ** rxd pin uartsr intrxd interrupt after reading uartsr then rdbuf clears perr. final bit stop shift register xxxx0 * 0xxxx0 xxx0 ** rxd pin uartsr intrxd interrupt after reading uartsr then rdbuf clears ferr.
page 172 14. asynchronous serial interface (uart1) 14.9 status flag TMP88FW45FG figure 14-7 generati on of overrun error note:receive operations are di sabled until the overrun error flag uartsr is cleared. 14.9.4 receive data buffer full loading the received data in rdbuf sets receive data buffer full flag uartsr to "1". the uartsr is cleared to ?0? when the rdbuf is read after reading the uartsr. figure 14-8 generat ion of receive data buffer full note:if the overrun error flag uartsr is set during the period between reading the uartsr and reading the rdbuf, it cannot be cleared by only reading the rdbuf. therefore, after reading the rdbuf, read the uartsr again to check whether or not the overrun er ror flag which should have been cleared still remains set. 14.9.5 transmit data buffer empty when no data is in the transmit buffer tdbuf, that is, when data in tdbuf are transferred to the transmit shift register and data transmit starts, transmit data buffer empty flag uartsr is set to ?1?. the uartsr is cleared to ?0 ? when the tdbuf is writte n after reading the uartsr. final bit stop shift register xxxx0 * 1xxxx0 yyyy xxx0 ** rxd pin uartsr intrxd interrupt after reading uartsr then rdbuf clears oerr. rdbuf uartsr final bit stop shift register xxxx0 * 1xxxx0 xxxx yyyy xxx0 ** rxd pin uartsr intrxd interrupt rdbuf after reading uartsr then rdbuf clears rbfl.
page 173 TMP88FW45FG figure 14-9 generation of transmit data buffer empty 14.9.6 transmit end flag when data are transmitted and no data is in tdbuf (uartsr = ?1?), transmit end flag uartsr is set to ?1?. the uartsr is cleared to ?0? when the data transmit is stated after writing the tdbuf. figure 14-10 generation of transmit e nd flag and transmit data buffer empty shift register data write data write zzzz xxxx yyyy start bit 0 final bit stop 1xxxx0 ***** 1 * 1xxxx **** 1x ***** 1 1yyyy0 tdbuf txd pin uartsr inttxd interrupt after reading uartsr writing tdbuf clears tbep. shift register * 1yyyy *** 1 xx **** 1 x ***** 1 stop start 1yyyy0 bit 0 txd pin uartsr uartsr inttxd interrupt data write for tdbuf
page 174 14. asynchronous serial interface (uart1) 14.9 status flag TMP88FW45FG
page 175 TMP88FW45FG 15. asynchronous serial interface (uart2) the TMP88FW45FG has a asynchronous serial interface (uar t) . it can connect the pe ripheral circuits through txd and rxd pin. txd and rxd pin are also used as th e general port. for txd pin, the corresponding general port should be set output mode (set its output control regist er to "1" after its output port latch to "1"). for rxd pin, should be set input mode. rxd3 and txd3 are correspond to p81 and p80 pins as the connection pins with the peripheral circuits in the asynchronous serial interface (uart2). 15.1 configuration figure 15-1 uart2 (asynchronous serial interface) counter y a b c s s a b c d y e f g h uart status register uart control register 2 uart control register 1 transmit data buffer receive data buffer fc/13 fc/26 fc/52 fc/104 fc/208 fc/416 fc/96 stop bit parity bit fc/2 6 fc/2 7 fc/2 8 baud rate generator transmit/receive clock 2 4 3 2 2 2 noise rejection circuit m p x transmit control circuit shift register shift register receive control circuit mpx: multiplexer uartcr21 tdbuf2 rdbuf2 inttxd2 intrxd2 uartsr2 uartcr22 rxd3 txd3 inttc4
page 176 15. asynchronous serial interface (uart2) 15.2 control TMP88FW45FG 15.2 control uart2 is controlled by the uart2 control registers (uartcr21, uartcr22). the operating status can be monitored using the uart status register (uartsr2). note 1: when operations are disabled by setting uartcr21 bits to ?0?, the setting becomes valid when data transmit or receive complete. when the transmit data is stor ed in the transmit data buffer, the data are not transmitted. even if data transmit is enabled, until new data are written to the transmit data buffer, the current data are not transmitted. note 2: the transmit clock and the parity are common to transmit and receive. note 3: uartcr21 and uartcr21 should be set to ?0? before uartcr21 is changed. note 4: in case fc = 20mhz, the timer counter 4 (tc4) is available as a baud rate generator. note: when uartcr22 = ?01?, pulses longer than 96/fc [s] are always regarded as signals; when uartcr22 = ?10?, longer than 192/fc [s]; and when uartcr22 = ?11?, longer than 384/fc [s]. uart2 control register1 uartcr21 (01f70h) 76543210 txe rxe stbt even pe brg (initial value: 0000 0000) txe transfer operation 0: 1: disable enable write only rxe receive operation 0: 1: disable enable stbt transmit stop bit length 0: 1: 1 bit 2 bits even even-numbered parity 0: 1: odd-numbered parity even-numbered parity pe parity addition 0: 1: no parity parity brg transmit clock select 000: 001: 010: 011: 100: 101: 110: 111: fc/13 [hz] fc/26 fc/52 fc/104 fc/208 fc/416 input inttc4 fc/96 uart2 control register2 uartcr22 (01f71h) 7654321 0 rxdnc stopbr (initial value: **** *000) rxdnc selection of rxd input noise rejectio time 00: 01: 10: 11: no noise rejection (hysteresis input) rejects pulses shorter than 31/fc [s] as noise rejects pulses shorter than 63/fc [s] as noise rejects pulses shorter than 127/fc [s] as noise write only stopbr receive stop bit length 0: 1: 1 bit 2 bits
page 177 TMP88FW45FG note: when an inttxd is generated, tbep flag is set to "1" automatically. uart2 status register uartsr2 (01f70h) 76543210 perr ferr oerr rbfl tend tbep (initial value: 0000 11**) perr parity error flag 0: 1: no parity error parity error read only ferr framing error flag 0: 1: no framing error framing error oerr overrun error flag 0: 1: no overrun error overrun error rbfl receive data buffer full flag 0: 1: receive data buffer empty receive data buffer full tend transmit end flag 0: 1: on transmitting transmit end tbep transmit data buffer empty flag 0: 1: transmit data buffer full (transmit data writing is finished) transmit data buffer empty uart2 receive data buffer rdbuf2 (01f72h) 76543210read only (initial value: 0000 0000) uart2 transmit data buffer tdbuf2 (01f72h) 76543210write only (initial value: 0000 0000)
page 178 15. asynchronous serial interface (uart2) 15.3 transfer data format TMP88FW45FG 15.3 transfer data format in uart2, an one-bit start bit (low level), stop bit (b it length selectable at high level, by uartcr21), and parity (select parity in uartcr21; even- or odd-numbered parity by uartcr21) are added to the transfer data. the transfer da ta formats are shown as follows. figure 15-2 tran sfer data format figure 15-3 caution on c hanging transfer data format note: in order to switch the transfer data format, perfor m transmit operations in the above figure 15-3 sequence except for the initial setting. start bit 0 bit 1 bit 6 bit 7 stop 1 start bit 0 bit 1 bit 6 bit 7 stop 1 stop 2 start bit 0 bit 1 bit 6 bit 7 parity stop 1 start bit 0 bit 1 bit 6 bit 7 parity stop 1 stop 2 pe 0 0 1 1 stbt frame length 0 1 123 89101112 0 1 without parity / 1 stop bit with parity / 1 stop bit without parity / 2 stop bit with parity / 2 stop bit
page 179 TMP88FW45FG 15.4 transfer rate the baud rate of uart2 is set of uartcr21. th e example of the baud rate are shown as follows. when inttc4 is used as the uart2 transfer rate (when uartcr21 = ?110?), the transfer clock and transfer rate are de termined as follows: transfer clock [hz] = tc4 sour ce clock [hz] / tc4dr setting value transfer rate [baud] = transfer clock [hz] / 16 15.5 data sampling method the uart2 receiver keeps sampling input using the clock selected by uartcr21 until a start bit is detected in rxd pin input. rt clock star ts detecting ?l? level of the rxd pin. once a start bit is detected, the start bit, data bits, stop bi t(s), and parity bit are sampled at three times of rt7, rt8, and rt9 during one receiver clock interval (rt clock). (rt0 is the position where the bit supposedly starts.) bit is determined according to majority rule (the data are the same twice or more out of three samplings). figure 15-4 data sampling method table 15-1 transfer rate (example) brg source clock 16 mhz 8 mhz 000 76800 [baud] 38400 [baud] 001 38400 19200 010 19200 9600 011 9600 4800 100 4800 2400 101 2400 1200 rt0 1 2 3 4 5 6 7 8 9101112 1314 15 01234567891011 bit 0 start bit bit 0 start bit (a) without noise rejection circuit rt clock internal receive data rt0 1 2 3 4 5 6 7 8 9101112 1314 15 01234567891011 bit 0 start bit bit 0 start bit rt clock internal receive data (b) with noise rejection circuit rxd pin rxd pin
page 180 15. asynchronous serial interface (uart2) 15.6 stop bit length TMP88FW45FG 15.6 stop bit length select a transmit stop bit length (1 bit or 2 bits) by uartcr21. 15.7 parity set parity / no parity by uartcr21 and set parity type (odd- or even-numbered) by uartcr21. 15.8 transmit/receive operation 15.8.1 data transmit operation set uartcr21 to ?1?. read uartsr2 to ch eck uartsr2 = ?1?, then write data in tdbuf2 (transmit data buffer). writing data in tdbuf2 zero-clears uartsr2< tbep>, transfers the data to the transmit shift register and the data are sequentially output from the txd pin. the data output include a one-bit start bit, stop bits whose number is specified in uartcr21 and a par ity bit if parity addition is specified. select the data transfer baud rate us ing uartcr21. when data transmit starts, transmit buffer empty flag uartsr2 is set to ?1? and an inttxd interrupt is generated. while uartcr21 = ?0? and from when ?1? is written to uartcr21 to when send data are written to tdbuf2, the txd pin is fixed at high level. when transmitting data, first read uartsr2, then write data in tdbuf2. otherwise, uartsr2 is not zero-cleared a nd transmit does not start. 15.8.2 data receive operation set uartcr21 to ?1?. when data are received vi a the rxd pin, the receive data are transferred to rdbuf2 (receive data buffer). at this time, the data tran smitted includes a start bit an d stop bit(s) and a parity bit if parity addition is specified. when stop bit(s) are received, data only are extracted and transferred to rdbuf2 (receive data buffer). then the receive buf fer full flag uartsr2 is set and an intrxd interrupt is generated. select the data transfer baud rate using uartcr21. if an overrun error (o err) occurs when data are received, the da ta are not transferre d to rdbuf2 (receive data buffer) but discarded; data in the rdbuf2 are not affected. note:when a receive operation is dis abled by setting uartcr21 bit to ?0?, the setting becomes valid when data receive is completed. however, if a framing error occurs in data receive, the receive-disabling setting may not become valid. if a framing error occurs , be sure to perform a re-receive operation.
page 181 TMP88FW45FG 15.9 status flag 15.9.1 parity error when parity determined using the receive data bits diff ers from the received parity bit, the parity error flag uartsr2 is set to ?1?. the uartsr2 is cleared to ?0? when the rdbuf2 is read after reading the uartsr2. figure 15-5 generati on of parity error 15.9.2 framing error when ?0? is sampled as the stop bit in the receive da ta, framing error flag uartsr2 is set to ?1?. the uartsr2 is cleared to ?0? when th e rdbuf2 is read after reading the uartsr2. figure 15-6 generati on of framing error 15.9.3 overrun error when all bits in the next data are received while unread data are still in rdbuf2, overrun error flag uartsr2 is set to ?1?. in this case, the receive data is discarded; data in rdbuf2 are not affected. the uartsr2 is cleared to ?0? when th e rdbuf2 is read after reading the uartsr2. parity stop shift register pxxxx0 * 1pxxxx0 xxxx0 ** rxd pin uartsr2 intrxd interrupt after reading uartsr2 then rdbuf2 clears perr. final bit stop shift register xxxx0 * 0xxxx0 xxx0 ** rxd pin uartsr2 intrxd interrupt after reading uartsr2 then rdbuf2 clears ferr.
page 182 15. asynchronous serial interface (uart2) 15.9 status flag TMP88FW45FG figure 15-7 generati on of overrun error note:receive operations are di sabled until the overrun error flag uartsr2 is cleared. 15.9.4 receive data buffer full loading the received data in rdbuf2 sets receive data buffer full flag uartsr2 to "1". the uartsr2 is cleared to ?0? when the rdbuf2 is read after reading the uartsr2. figure 15-8 generat ion of receive data buffer full note:if the overrun error flag uartsr2 is set during the period between reading the uartsr2 and read- ing the rdbuf2, it cannot be cleared by only reading t he rdbuf2. therefore, after reading the rdbuf2, read the uartsr2 again to check whether or not the overrun error flag which should have been cleared still remains set. 15.9.5 transmit data buffer empty when no data is in the transmit buffer tdbuf2, that is, when data in tdbuf2 are transferred to the transmit shift register and data transmit starts, transmit data buffer empty flag uartsr2 is set to ?1?. the uartsr2 is cleared to ?0? when the td buf2 is written after reading the uartsr2. final bit stop shift register xxxx0 * 1xxxx0 yyyy xxx0 ** rxd pin uartsr2 intrxd interrupt after reading uartsr2 then rdbuf2 clears oerr. rdbuf2 uartsr2 final bit stop shift register xxxx0 * 1xxxx0 xxxx yyyy xxx0 ** rxd pin uartsr2 intrxd interrupt rdbuf2 after reading uartsr2 then rdbuf2 clears rbfl.
page 183 TMP88FW45FG figure 15-9 generation of transmit data buffer empty 15.9.6 transmit end flag when data are transmitted and no data is in tdbuf2 (uartsr2 = ?1?), transmit end flag uartsr2 is set to ?1?. the uartsr2 is cleared to ?0? when the data transmit is stated after writing the tdbuf2. figure 15-10 generation of transmit e nd flag and transmit data buffer empty shift register data write data write zzzz xxxx yyyy start bit 0 final bit stop 1xxxx0 ***** 1 * 1xxxx **** 1x ***** 1 1yyyy0 tdbuf2 txd pin uartsr2 inttxd interrupt after reading uartsr2 writing tdbuf2 clears tbep. shift register * 1yyyy *** 1 xx **** 1 x ***** 1 stop start 1yyyy0 bit 0 txd pin uartsr2 uartsr2 inttxd interrupt data write for tdbuf2
page 184 15. asynchronous serial interface (uart2) 15.9 status flag TMP88FW45FG
page 185 TMP88FW45FG 16. synchronous serial interface (sio) the TMP88FW45FG has a clocked-synchrono us 8-bit serial interface. serial interface has an 8- byte transmit and receive data buffer that can automatically and continuously transfer up to 64 bits of data. serial interface is connected to outside peripherl devices via so, si, sck port. 16.1 configuration figure 16-1 serial interface sio control / status register serial clock shift clock shift register 3 2 1 0 7 6 5 4 transmit and receive data buffer (8 bytes in dbr) control circuit cpu serial data output serial data input 8-bit transfer 4-bit transfer serial clock i/o buffer control circuit so si sck siocr2 siocr1 siosr intsio interrupt request
page 186 16. synchronous serial interface (sio) 16.2 control TMP88FW45FG 16.2 control the serial interface is controlled by sio control registers (s iocr1/siocr2). the serial interface status can be determined by reading sio status register (siosr). the transmit and receive data buffer is controlled by the siocr2. th e data buffer is assigned to address 01f98h to 01f9fh for sio in the dbr area, and can continuo usly transfer up to 8 words (bytes or nibbles) at one time. when the specified number of word s has been transferred, a buffer empt y (in the transmit mode) or a buffer full (in the receive mode or transmit/receive mode) interr upt (intsio) is generated. when the internal clock is used as the serial clock in the 8-bit receive mode and the 8-bit transmit/receive mode, a fixed interval wait can be applied to the serial clock fo r each word transferred. four different wait times can be selected with siocr2. note 1: fc; high-frequency clock [hz] note 2: set siocr1 to "0" and siocr1 to "1" when setting the transfer mode or serial clock. note 3: siocr1 is write-only register, whic h cannot access any of in read-modify-wri te instruction such as bit operate, etc. sio control register 1 siocr176543210 (1f96h) sios sioinh siom sck (initial value: 0000 0000) sios indicate transfer start / stop 0: stop write only 1: start sioinh continue / abort transfer 0: continuously transfer 1: abort transfer (automatically cleared after abort) siom transfer mode select 000: 8-bit transmit mode 010: 4-bit transmit mode 100: 8-bit transmit / receive mode 101: 8-bit receive mode 110: 4-bit receive mode except the above: reserved sck serial clock select normal, idle mode write only dv1ck = 0 dv1ck = 0 000 fc/2 13 fc/2 14 001 fc/2 8 fc/2 9 010 fc/2 7 fc/2 8 011 fc/2 6 fc/2 7 100 fc/2 5 fc/2 6 101 fc/2 4 fc/2 5 110 reserved 111 external clock (input from sck pin) sio control register 2 siocr276543210 (1f97h) wait buf (initial value: ***0 0000)
page 187 TMP88FW45FG note 1: the lower 4 bits of each buffer are used during 4-bit tr ansfers. zeros (0) are stored to the upper 4bits when receiving. note 2: transmitting starts at the lowest address. received data are also stored starting from the lowest address to the highest address. ( the first buffer address transmitted is 01f98h ). note 3: the value to be loaded to buf is held after transfer is completed. note 4: siocr2 must be set when the serial interface is stopped (siof = 0). note 5: *: don't care note 6: siocr2 is write-only register, whic h cannot access any of in read-modify-wri te instruction such as bit operate, etc. note 7: t f ; frame time, t d ; data transfer time figure 16-2 fr ame time (t f ) and data transfer time (t d ) note 1: after siocr1 is cleared to "0", siosr is cleared to "0" at the termination of transfer or the setting of siocr1 to "1". 16.3 serial clock 16.3.1 clock source internal clock or external clock for the source clock is selected by siocr1. wait wait control always sets "00" except 8-bit transmit / receive mode. write only 00: t f = t d (non wait) 01: t f = 2t d (wait) 10: t f = 4t d (wait) 11: t f = 8t d (wait) buf number of transfer words (buffer address in use) 000: 1 word transfer 01f98h 001: 2 words transfer 01f98h ~ 01f99h 010: 3 words transfer 01f98h ~ 01f9ah 011: 4 words transfer 01f98h ~ 01f9bh 100: 5 words transfer 01f98h ~ 01f9ch 101: 6 words transfer 01f98h ~ 01f9dh 110: 7 words transfer 01f98h ~ 01f9eh 111: 8 words transfer 01f98h ~ 01f9fh sio status register siosr76543210 (1f97h) siof sef (initial value: 00** ****) siof serial transfer operating status moni- tor 0: 1: transfer terminated transfer in process read only sef shift operating status monitor 0: 1: shift operation terminated shift operation in process td tf (output) s ck output
page 188 16. synchronous serial interface (sio) 16.3 serial clock TMP88FW45FG 16.3.1.1 internal clock any of six frequencies can be selected. the serial clock is output to the outside on the sck pin. the sck pin goes high when transfer starts. when data writing (in the transmit mo de) or reading (in the receive mode or the transmit/receive mode) cannot keep up with the serial clock rate, there is a wa it function that automatically stops the serial clock and holds the next shift operation until the read/write processing is completed. note: 1 kbit = 1024 bit (fc = 20 mhz) figure 16-3 automatic wait func tion (at 4-bit transmit mode) 16.3.1.2 external clock an external clock connected to the sck pin is used as the serial clock. in this case, the sck (p43) port should be set to input mode. to ensure shifting, a pulse width of more than 2 4 /fc is required. this pulse is needed for the shift operation to ex ecute certainly. actually, there is necessary processi ng time for inter- rupting, writing, and reading. the minimum pulse is determined by setting the mode and the program. figure 16-4 external clock pulse width table 16-1 serial clock rate normal, idle mode sck clock baud rate 000 fc/2 13 2.44 kbps 001 fc/2 8 78.13 kbps 010 fc/2 7 156.25 kbps 011 fc/2 6 312.50 kbps 100 fc/2 5 625.00 kbps 101 fc/2 4 125.00 kbps 110 - - 111 external external a 1 a 2 b 0 b 1 b 2 b 3 c 0 c 1 a 3 a c b a 0 pin (output) pin (output) written transmit data a utomat i ca ll y wait function sck so t sckl t sckh t sckl , t sckh > 2 4 /fc sck pin (input)
page 189 TMP88FW45FG 16.3.2 shift edge the leading edge is used to transmit, a nd the trailing edge is used to receive. 16.3.2.1 leading edge transmitted data are shifted on the leading ed ge of the serial clock (falling edge of the sck pin input/ output). 16.3.2.2 trailing edge received data are shifted on the trailing edge of the serial clock (rising edge of the sck pin input/out- put). figure 16-5 shift edge 16.4 number of bits to transfer either 4-bit or 8-bit serial transfer can be selected. when 4-bit serial transfer is selected, only the lower 4 bits of the transmit/receive data buffer re gister are used. the upper 4 bits are cleared to ?0? when receiving. the data is transferred in sequence star ting at the least significant bit (lsb). 16.5 number of w ords to transfer up to 8 words consisting of 4 bits of data (4-bit serial tran sfer) or 8 bits (8-bit serial tr ansfer) of data can be trans- ferred continuously. the number of words to be transferred can be selected by siocr2. an intsio interrupt is generated when the specified number of words has been transferred. if the number of words is to be changed during transfer, the serial interf ace must be stopped before ma king the chan ge. the number of words can be changed during automatic- wait operation of an intern al clock. in this case, the serial interface is not required to be stopped. bit 1 bit 2 bit 3 * 321 3210 ** 32 *** 3 bit 0 shift register shift register bit 1 bit 0 bit 2 bit 3 0 *** **** 210 * 10 ** 3210 (a) leading edge (b) trailing edge * ; don?t care so pin si pin sck pin sck pin
page 190 16. synchronous serial interface (sio) 16.6 transfer mode TMP88FW45FG figure 16-6 number of words to transfer (example: 1word = 4bit) 16.6 transfer mode siocr1 is used to select the tr ansmit, receive, or tr ansmit/receive mode. 16.6.1 4-bit and 8-bit transfer modes in these modes, firstly set the sio control register to the transmit mode, and then write first transmit data (number of transfer words to be transfer red) to the data buffer registers (dbr). after the data are written, the transmission is star ted by setting siocr1 to ?1?. the data are then output sequentially to the so pin in synchronous with th e serial clock, starting with the least significant bit (lsb). as soon as the lsb has been output, the data are transferred from the data buffer register to the shift register. when the final data bit has been transferred a nd the data buffer register is empty, an intsio (buffer empty) interrupt is generated to request the next transmitted data. when the internal clock is used, the serial clock will stop and an automatic-wait will be initiated if the next transmitted data are not loaded to the data buffer regist er by the time the number of data words specified with the siocr2 has been transmitted . writing even one word of data can cels the automatic- wait; therefore, when transmitting two or more words, always write the ne xt word before transmission of the previous word is completed. note:automatic waits are also canceled by writing to a dbr not being used as a transmit data buffer register; there- fore, during sio do not use such dbr for other applicati ons. for example, when 3 words are transmitted, do not use the dbr of the remained 5 words. when an external clock is used, the data must be writte n to the data buffer register before shifting next data. thus, the transfer speed is determin ed by the maximum delay time from the generation of the interrupt request to writing of the data to the data buffer register by the interrupt service program. the transmission is ended by clearing siocr1 to ?0? or setting siocr1 to ?1? in buffer empty interrupt service program. a 1 a 2 a 3 a 0 a 1 a 2 a 3 b 0 b 1 b 2 b 3 c 0 c 1 c 2 c 3 a 0 a 1 a 0 a 2 a 3 b 0 b 1 b 2 b 3 c 0 c 1 c 2 c 3 (a) 1 word transmit (b) 3 words transmit (c) 3 words receive so pin intsio interrupt intsio interrupt intsio interrupt so pin si pin sck pin sck pin sck pin
page 191 TMP88FW45FG siocr1 is cleared, the operation will end after all bits of words are transmitted. that the transmission has ended can be determined from the status of siosr becau se siosr is cleared to ?0? when a transfer is completed. when siocr1 is set, the transmission is immediately ended and siosr is cleared to ?0?. when an external clock is used, it is also necessary to clear siocr1 to ?0? before shifting the next data; if siocr1 is not cleared before shift out, dummy data will be transmitted and the operation will end. if it is necessary to change the number of word s, siocr1 should be cleared to ?0?, then siocr2 must be rewritten after confirming that siosr has been cleared to ?0?. figure 16-7 transfer m ode (example: 8bit, 1word tr ansfer, internal clock) figure 16-8 transfer mode (example: 8b it, 1word transfer , external clock) a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a 0 dbr b a clear sios write (a) write (b) sck pin (output) so pin intsio interrupt siocr1 siosr siosr siosr a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a 0 dbr b a clear sios write (a) write (b) sck pin (input) so pin intsio interrupt siocr1 siosr siosr
page 192 16. synchronous serial interface (sio) 16.6 transfer mode TMP88FW45FG figure 16-9 transmiiied data ho ld time at end of transfer 16.6.2 4-bit and 8- bit receive modes after setting the control registers to the receive mode , set siocr1 to ?1? to enable receiving. the data are then transferred to the shift register via the si pin in synchronous with the serial clock. when one word of data has been received, it is tran sferred from the shift register to the data buffer register (dbr). when the number of words specified w ith the siocr2 has been received, an intsio (buffer full) interrupt is generated to request that these data be read out. the da ta are then read from the da ta buffer registers by the interrupt service program. when the internal clock is used, and the previous data are not read from the data buffer register before the next data are received, the serial cloc k will stop and an automatic-wait will be initiated until the data are read. a wait will not be initiated if even one data word has been read. note:waits are also canceled by readi ng a dbr not being used as a received data buffer register is read; therefore, during sio do not use such dbr for other applications. when an external clock is used, the shift operation is synchronized with the extern al clock; therefore, the previous data are read before the next data are transferred to the data buffer register. if the previous data have not been read, the next data will not be transferred to th e data buffer register and th e receiving of any more data will be canceled. when an external clock is used, th e maximum transfer speed is determined by the delay between the time when the interrupt request is gene rated and when the data received have been read. the receiving is ended by clearing si ocr1 to ?0? or setting sio cr1 to ?1? in buffer full interrupt service program. when siocr1 is cleared, th e current data are transferred to the buffer. after siocr1 cleared, the receiving is ended at the ti me that the final bit of the data has been received. that the receiving has ended can be determined from the st atus of siosr. siosr is cleared to ?0? when the receiv- ing is ended. after confirmed the r eceiving termination, the final receiving data is read. when siocr1 is set, the receiving is immediately ended and si osr is cleared to ?0 ?. (the received data is ignored, and it is not required to be read out.) if it is necessary to change the number of words in external clock operation, siocr1 should be cleared to ?0? then siocr2 mu st be rewritten after confirming th at siosr ha s been cleared to ?0?. if it is necessary to change the number of words in internal clock, during automatic-wait operation which occurs after completion of data recei ving, siocr2 must be rewritten before the received data is read out. note:the buffer contents are lost when the transfer mode is switched. if it should become necessary to switch the transfer mode, end receiving by cl earing siocr1 to ?0?, read the last data and then switch the trans- fer mode. msb of last word t sodh = min 3.5/fc [s] (in the normal, idle modes) sck pin so pin siosr
page 193 TMP88FW45FG figure 16-10 receive mode (example: 8b it, 1word transfer, internal clock) 16.6.3 8-bit trans fer / receive mode after setting the sio control register to the 8-bit transmit/recei ve mode, write the data to be transmitted first to the data buffer registers (dbr). after that, enable the transmit/receive by sett ing siocr1 to ?1?. when transmitting, the data are output from the so pin at leading edges of the serial clock. when receiving, the data are input to the si pin at th e trailing edges of the serial clock. wh en the all receive is enabled, 8-bit data are transferred from th e shift register to the data buffer regist er. an intsio interrupt is generated when the number of data words specified with the siocr2 has been tr ansferred. usually, read the receive data from the buffer register in the interrupt service. the data buffer register is used for both transmitting and receiving; therefore, always writ e the data to be transmitted af ter reading the all received data. when the internal clock is used, a wait is initiated until the received data are read and the next transfer data are written. a wait will not be initiated if ev en one transfer data word has been written. when an external clock is used, the shift operation is synchronized with the external clock; therefore, it is necessary to read the received data and write the data to be transmitted next before starting the next shift oper- ation. when an external clock is us ed, the transfer speed is determined by the maximum delay between genera- tion of an interrupt request and the received data are read and the data to be transmitted next are written. the transmit/receive operatio n is ended by clearing siocr1 to ?0? or setting siocr1 to ?1? in intsio interrupt service program. when siocr1 is cleared, the current data ar e transferred to the buff er. after siocr1 cleared, the transmitting/ receiving is ended at the time that the fi nal bit of the data has been transmitted. that the transmitting/ receiving has ended can be determined from the status of siosr. siosr is cleared to ?0? when the transmitting/recei ving is ended. when siocr1 is set, the transmit/receive operation is immediately ended and siosr is cleared to ?0?. if it is necessary to change the number of words in external clock operation, siocr1 should be cleared to ?0?, then sio cr2 must be rewritten after confirmi ng that siosr has been cleared to ?0?. if it is necessary to change the number of words in internal clock, during automatic-wait operation which occurs after completion of transmit/ receive operation, siocr2 must be rewritten before reading and writing of the receive/transmit data. a 1 a 0 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 dbr b a clear sios read out read out sck pin (output) si pin intsio interrupt siocr1 siosr siosr
page 194 16. synchronous serial interface (sio) 16.6 transfer mode TMP88FW45FG note:the buffer contents are lost when the transfer mode is switched. if it should become necessary to switch the transfer mode, end receiving by cl earing siocr1 to ?0?, read the last data and then switch the trans- fer mode. figure 16-11 transfer / receive mode (examp le: 8bit, 1word transfe r, internal clock) figure 16-12 transmitted data hold ti me at end of transfer / receive a 1 a 0 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 c 1 c 0 c 2 c 3 c 4 c 5 c b c 6 c 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 clear sios dbr d a read out (c) write (a) read out (d) write (b) sck pin (output) so pin intsio interrupt siocr1 siosr siosr si pin bit 7 of last word bit 6 t sodh = min 4/fc [s] (in the normal, idle modes) sck pin so pin siosr
page 195 TMP88FW45FG 17. 10-bit ad converter (adc) the TMP88FW45FG have a 10-bit successive approximation type ad converter. 17.1 configuration the circuit configuration of the 10-bit ad converter is shown in figure 17-1. it consists of control register adccra and adccrb, converted value register adcdrh and adcdrl, a da converter, a sample-hold circuit, a compar ator, and a successive comparison circuit. note: before using ad converter, set appropriate value to i/o port register conbining a analog input port. for details, see the sec- tion on "i/o ports". figure 17-1 10-bit ad converter 2 4 10 8 ainds adrs r/2 r/2 r ack amd irefon ad conversion result register 1, 2 ad converter control register 1, 2 adbf eocf intadc sain n successive approximate circuit adccrb adcdrh adcdrl adccra sample hold circuit a s en shift clock da converter analog input multiplexer y reference voltage analog comparator 2 3 control circuit avss varef avdd ain0 ain15
page 196 17. 10-bit ad converter (adc) 17.2 register configuration TMP88FW45FG 17.2 register configuration the ad converter consists of the following four registers: 1. ad converter control register 1 (adccra) this register selects the analog channels and operatio n mode (software start or repeat) in which to per- form ad conversion and controls the ad converter as it starts operating. 2. ad converter control register 2 (adccrb) this register selects the ad conversion time and co ntrols the connection of the da converter (ladder resistor network). 3. ad converted value register 1 (adcdrh) this register used to store the digital value after being converted by the ad converter. 4. ad converted value register 2 (adcdrl) this register monitors the oper ating status of the ad converter. note 1: select analog input channel during ad converter stops (adcdrl = "0"). note 2: when the analog input channel is all use di sabling, the adccra should be set to "1". note 3: during conversion, do not perform port output instruction to maintain a precision for all of the pins because analog inp ut port use as general input port. and for port near to anal og input, do not input intense signaling of change. note 4: the adccra is automatically cleared to "0" after starting conversion. note 5: do not set adccra newly again during ad c onversion. before setting adccra newly again, check adcdrl to see that the conversion is completed or wait until the interrupt signal (intadc) is generated (e.g., interrupt handling routine). note 6: after stop mode is started, ad converter control regi ster1 (adccra) is all initialized and no data can be written in thi s register. therfore, to use ad converter again, se t the adccra newly after returning to normal mode. note 7: after reset, adccra is initialized reserved setti ng. therfore, set the appropriate analog input channel to adc- cra when use ad converter. note 8: after adccra is set to 00h, ad conversion can not be star ted for four cycles. thus, four nops must be inserted before setting the adccra. ad converter control register 1 adccra (0026h) 76543210 adrs amd ainds sain (initial value: 0001 0000) adrs ad conversion start 0: 1: - ad conversion start r/w amd ad operating mode 00: 01: 10: 11: ad operation disable software start mode reserved repeat mode ainds analog input control 0: 1: analog input enable analog input disable sain analog input channel select 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 ain8 ain9 ain10 ain11 ain12 ain13 ain14 ain15
page 197 TMP88FW45FG note 1: always set bit0 in adccrb to "0" and set bit4 in adccrb to "1". note 2: when a read instruction for adccrb, bit6 to 7 in adccrb read in as undefined data. note 3: after stop mode is started, ad converter control regi ster2 (adccrb) is all initialized and no data can be written in thi s register. therfore, to use ad converter again, se t the adccrb newly after returning to normal mode. note 1: setting for " ? " in the above table are inhibited. fc: high frequency oscillation clock [hz] note 2: set conversion time setting should be kept more than the following time by analog reference voltage (varef). ad converter control register 2 adccrb (0027h) 76543210 irefon "1" ack "0" (initial value: **0* 000*) irefon da converter (ladder resistor) connection control 0: 1: connected only during ad conversion always connected r/w ack ad conversion time select (refer to the following table about the con- version time) 000: 001: 010: 011: 100: 101: 110: 111: 39/fc reserved 78/fc 156/fc 312/fc 624/fc 1248/fc reserved table 17-1 ack setting and conversion time (at cgcr="0") condition conversion time 20 mhz 16 mhz 8 mhz ack 000 39/fc - - - 001 reserved 010 78/fc - - - 011 156/fc - - 19.5 s 100 312/fc 15.6 s 19.5 s 39.0 s 101 624/fc 31.2 s 39.0 s 78.0 s 110 1248/fc 62.4 s 78.0 s 156.0 s 111 reserved table 17-2 ack setting and conversion time (at cgcr="1") condition conversion time 20 mhz 16 mhz 8 mhz ack 000 39/fc - - - 001 reserved 010 78/fc - - - 011 156/fc - - 19.5 s 100 312/fc 15.6 s 19.5 s 39.0 s 101 624/fc 31.2 s 39.0 s 78.0 s 110 1248/fc 62.4 s 78.0 s 156.0 s 111 reserved - varef = 4.5 to 5.5 v 15.6 s and more
page 198 17. 10-bit ad converter (adc) 17.2 register configuration TMP88FW45FG note 1: the adcdrl is cleared to "0" when reading the ad cdrh. therfore, the ad conversion result should be read to adcdrl more first than adcdrh. note 2: the adcdrl is set to "1" when ad conversion star ts, and cleared to "0" when ad conversion finished. it also is cleared upon entering stop mode. note 3: if a read instruction is executed for a dcdrl, read data of bit3 to bit0 are unstable. ad converted value register 1 adcdrh (0029h) 76543210 ad09 ad08 ad07 ad06 ad05 ad04 ad03 ad02 (initial value: 0000 0000) ad converted value register 2 adcdrl (0028h) 76543210 ad01 ad00 eocf adbf (initial value: 0000 ****) eocf ad conversion end flag 0: 1: before or during conversion conversion completed read only adbf ad conversion busy flag 0: 1: during stop of ad conversion during ad conversion
page 199 TMP88FW45FG 17.3 function 17.3.1 software start mode after setting adccra to ?01? (software start mode), set adccra to ?1?. ad conver- sion of the voltage at the analog input pin specified by adccra is thereby started. after completion of the ad conversion, the conversion result is stored in ad converted value registers (adcdrh, adcdrl) and at the same time adcdrl is set to 1, the ad conversion finished inter- rupt (intadc) is generated. adrs is automatically cleared afte r ad conversion has started. do not set adccra newly again (restart) during ad convers ion. before setting adccra newly again, check adcdrl to see that the conversion is completed or wait until the interrupt signal (intadc) is generated (e.g., interrupt handling routine). figure 17-2 software start mode 17.3.2 repeat mode ad conversion of the voltage at the analog input pin specified by adccra is performed repeat- edly. in this mode, ad conver sion is started by setting adccra to ?1? after setting adc- cra to ?11? (repeat mode). after completion of the ad conversion, the conversion result is stored in ad converted value registers (adcdrh, adcdrl) and at the same time adcdrl is set to 1, the ad conversion finished inter- rupt (intadc) is generated. in repeat mode, each time one ad conversion is complete d, the next ad conversion is started. to stop ad conversion, set adccra to ?00? (disable mode) by writing 0s. the ad convert operation is stopped immediately. the converted valu e at this time is not stored in the ad converted value register. adcdrh status eocf cleared by reading conversion result conversion result read adcdrl intadc interrupt request adcdrl adccra 1st conversion result 2nd conversion result indeterminate ad conversion start ad conversion start a dcdrh a dcdrl conversion result read conversion result read conversion result read
page 200 17. 10-bit ad converter (adc) 17.3 function TMP88FW45FG figure 17-3 repeat mode 17.3.3 regi ster setting 1. set up the ad converter control register 1 (adccra) as follows: ? choose the channel to ad convert using ad input channel select (sain). ? specify analog input enable fo r analog input control (ainds). ? specify amd for the ad converter control operation mode (software or repeat mode). 2. set up the ad converter control register 2 (adccrb) as follows: ? set the ad conversion time using ad conversion time (ack). for details on how to set the con- version time, refer to figure 17-1, figure 17-2 and ad converter control register 2. ? choose irefon for da converter control. 3. after setting up (1) and (2) above, set ad conversion start (adrs) of ad converter control register 1 (adccra) to ?1?. if software start mode has been selected, ad conversi on starts immediately. 4. after an elapse of the specified ad conversion time, the ad converted value is stored in ad con- verted value register 1 (adcdrh) and the ad conv ersion finished flag (e ocf) of ad converted value register 2 (adcdrl) is set to ?1?, upon which time ad conversion interrupt intadc is gen- erated. 5. eocf is cleared to ?0? by a read of the conversion result. however, if reconverted before a register read, although eocf is cl eared the previous conversi on result is retained until the next conversion is completed. a dcdrh,adcdrl eocf cleared by reading conversion result conversion result read a dcdrl intadc interrupt request conversion operation a dccra indeterminate ad conversion start adccra ?11? ?00? 1st conversion result ad convert operation suspended. conversion result is not stored. 2nd conversion result 3rd conversion result a dcdrh a dcdrl 2nd conversion result 3rd conversion result 1st conversion result conversion result read conversion result read conversion result read conversion result read conversion result read
page 201 TMP88FW45FG 17.4 stop mode du ring ad conversion when standby mode (stop mode) is entered forcibly during ad conversion, the ad convert operation is sus- pended and the ad converter is initialized (adccra and adccrb are initialized to init ial value). also, the con- version result is indeterminate. (conversion results up to the previous operation are cleare d, so be sure to read the conversion results before entering standby mode (stop mode).) when restored from standby mode (stop mode), ad conversion is not automatical ly restarted, so it is necessary to restar t ad conversion. note that since the analog reference voltage is automatically disconnected, there is no possibility of current flowing into the analog reference voltage. example :after selecting the conversion time 15.6 s at 20 mhz and the analog input channel ain4 pin, perform ad con- version once. after checking eocf, read the converted valu e, store the lower 2 bits in address 0009eh and store the upper 8 bits in address 0009fh in ram. the operation mode is software start mode. : (port setting) : ;set port register approrriately before setting ad converter registers. : : (refer to section i/o port in details) ld (adccra) , 00100100b ; select software start mode, analog input enable, and ain4 ld (adccrb) , 00011000b ;select conversion time(312/fc) and operation mode set (adccra) . 7 ; adrs = 1(ad conversion start) sloop : test (adcdrb) . 5 ; eocf= 1 ? jrs t, sloop ld a , (adcdrl) ; read result data ld (9eh) , a ld a , (adcdrh) ; read result data ld (9fh), a
page 202 17. 10-bit ad converter (adc) 17.5 analog input voltage and ad conversion result TMP88FW45FG 17.5 analog input voltage and ad conversion result the analog input voltage is corresponded to the 10-bit dig ital value converted by the ad as shown in figure 17-4. figure 17-4 analog i nput voltage and ad c onversion result (typ.) 1 0 01 h 02 h 03 h 3fd h 3fe h 3ff h 2 3 1021 1022 1023 1024 analog input voltage 1024 ad conversion result varef avss
page 203 TMP88FW45FG 17.6 precautions about ad converter 17.6.1 analog input pin voltage range make sure the analog input pins (ain0 to ain15) are used at voltages within varef to avss. if any volt- age outside this range is applied to one of the analog input pins, the converted value on that pin becomes uncer- tain. the other analog input pins also are affected by that. 17.6.2 analog input shared pins the analog input pins (ain0 to ain15) are shared with input/output ports. when using any of the analog inputs to execute ad conversion, do not execute input/output instructions for all other ports. this is necessary to prevent the accuracy of ad conversi on from degrading. not only these analog input sh ared pins, some other pins may also be affected by noise arising from input/o utput to and from adjacent pins. 17.6.3 noise countermeasure the internal equivalent circuit of the analog input pins is shown in figure 17-5. the higher the output impedance of the analog input source, more easily they are susceptible to no ise. therefore, make sure the out- put impedance of the signal source in your design is 5 k or less. toshiba also recommends attaching a capac- itor external to the chip. figure 17-5 analog i nput equivalent circuit and exam ple of input pin processing da converter aini analog comparator internal resistance permissible signal source impedance internal capacitance 5 k (typ) c = 22 pf (typ.) 5 k (max) note) i = 15 to 0
page 204 17. 10-bit ad converter (adc) 17.6 precautions about ad converter TMP88FW45FG
page 205 TMP88FW45FG 18. 8-bit high-speed pwm ( hpwm0 and hpwm1 ) the TMP88FW45FG contains two-channe ls of high-speed pwm. the high-sp eed pwm works in such a way that when data are written to the data re gisters for the respective channels, wave forms differing from each other can be output. the high-speed pwm is sh ared with ports, p02 ( hpwm0 ) and p03 ( hpwm1 ). when using these pins for high- speed pwm, set the port output latches for p02 and p03 to 1. 18.1 configuration figure 18-1 high-speed pwm ( hpwm0 and hpwm1 ) additional pulse generator circuit fc hpe0 comparator hpe1 hpe1 hpe0 hpwm0 hpwm1 8-bit up counter hpwmcr hpwmdr0 hpwmdr1 x1 pwmst pwmmod hight-speed pwm control register data register data register hpwm1 section hpwm0 section
page 206 18. 8-bit high-speed pwm (hpwm0 and hpwm1) 18.2 control TMP88FW45FG 18.2 control note 1: the pwm output pulse width varies with the clock duty cycle. note 2: for the data registers, set data 10h to f0h. note 3: when hpwmcr = 0, the internal count er is cleared and data ?1? is output to the port. note 4: before selecting pwm mode, make sure hpwmcr = 0. note 5: before entering stop mode, set hpwmcr all to 0. note 6: if hpwmcr is altered in the middle of pwm period, the waveform may be distorted. to avoid waveform distortion, make sure hpwmcr = 0 when enabling hpwm output. 18.3 functional description the high-speed pwm is controlled using the control re gister (hpwmcr) and data registers (hpwmdr0, 1). before writing to these registers, set the hpwmcr = 1 to make them ready for setup. when the hpw- mcr is set to 0, each control register is reset, so that the high-speed pwm can be reset in software. 18.3.1 operation modes the high-speed pwm has the following three modes of operation: ? 8-bit mode: (t = 2 8 clock period, f 78 khz) ? 7-bit mode: (t = 2 7 clock period, f 156 khz) ? 6-bit mode: (t = 2 6 clock period, f 313 khz) note:these values apply to the case wh ere the source clock (x1) is 20 mhz. use the hpwmcr

▲Up To Search▲

Price & Availability of TMP88FW45FG

	To Download TMP88FW45FG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .