mlx90255ba linear optical array mlx90255ba linear optical array page 1 rev 1 . 0 22 / january / 01 features and benefits 128 x 1 sensor - element organization (1 not connected, 1 dummy, 128 real, 1 dummy and 1 dark pixel) 385 do ts - per - inch (dpi) sensor pitch high linearity and uniformity for 256 gray - scale (8 - bit) applications high sensitivity: 1.7v @ 10 uw/cm 2 @ 0.7ms integration time special gain compensation for use with single led light source output referenced to ground low i mage lag single 5v supply replacement for texas instruments tsl1301 & tsl1401 and mlx90255aa operation to 1mhz applications pos ition sensing electrical power assist steering (epas) spectrometer applications ordering information part no. temperature suffi x package option temperature range mlx90255 k la - ba - 40c to 125c automotive mlx90255 k ga - ba - 40c to 125c automotiv e general description the mlx90255ba linear sensor array consists of a 128 x 1 array of photodiodes, associated charge amplifier circuitry and a pixel data - hold function that provides simultaneous - integration start and stop times for all pixels. the pixels measure 200 m m (h) by 66 m m (w) and 8 m m spacing between pixels. operation is simplified by internal control logic that require s only a serial - input (si) signal and a clock. the sensor consists of 128 photodiodes arranged in a linear array. light energy f alling on a photodiode generates photocurrent, which is integrated by the active integration circuitry associated with that pixe l. during the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. the am ount of charge accumulated at each pixel is directly proportional to the light intensity and the integration time. the output an d reset of the integrators is controlled by a 132 - bit shift register and reset logic. an output cycle is initiated by clocking i n a logic 1 on si. this causes all 132 sampling capacitors to be disconnected from their respective integrators and starts an in tegrator reset period. (continued on page 4) functional diagram 3 5 pixel 2 pixel 1 pixel 132 2 1 4 hold q1 q2 q132 switching logic 132-bit shift register integrator reset sample clk si gnd vdd analog out external load
mlx90255ba linear optical array mlx90255ba linear optical array page 2 rev 1 . 0 22 / january / 01 mlx90255 electrical specifications dc operating parameters t a = - 40 o c to 125 o c, v dd = 4.5v to 5.5v (unless otherwise specified) parameter symbol min typ max units supply voltage vdd 4.5 5 5.5 v input voltage, vi 0 vdd v high - level input voltage, vih vdd*0.7 vdd v low - level input voltage, vil 0 vdd*0.3 v hysteris on si and clk 0.2 0.4 0.8 v wavelength of light source 400 1000 nm clock frequency, fclock 64 1024 khz sensor integration time below 60degc (1) tint 0.125 100 ms sensor integration time full temperature range, (2) tint 0.125 2 ms pixel charge transfer time (full temp range) tqt 8 m s setup time, serial input tsu(si) 350 ns hold time, serial input(3) th(si) 40 ns operating free - air temperature ta - 40 125 c clock pulse duration (high) tw (h) 320 ns clock pulse duration (low) tw (l) 320 ns notes: (1) reset until clock pulse 18 (on declining flank) minimum integration time = (132 - 18) * clk period + 10 m s (this is the time the s&h cap needs to follow) at 1mhz clock speed, the minimum integration time becomes 0.125ms (2) at 125c, the integratio n time should be limited to 2ms (3) the si pulse must go low before the rising edge of the next clock pulse
mlx90255ba linear optical array mlx90255ba linear optical array page 3 rev 1 . 0 22 / january / 01 mlx90255ba electrical specifications (0) all tests are made with 0.7ms integration time, at 10 m w/cm 2 light = 100% at 25 c at 880 nm and with a clock speed of 500khz in, 250khz out, and 500khz, unless otherwise specified in the test cond i- tions. 100 % light under test conditions means that the light is set in such a way that there is 2.4v at the output of the chip . parameter symbol test conditions min typ max unit illumination (1) illum 100 at 25 c, 2.4v at output 11.4 14 16 m w/ cm2 average analog output initial offset at 25 c, 0% light 0 0.15 0.3 v average analog output vaodark at 125 c, 0% light 0 0.40 1.4 v highest dark pixel vaodarkmax at 125 c, 0.25ms integration 0.8 v non linearity nlao1 all temp + 0.5% + 1.2% fs pixel response non uniformity (2) prnu all temp, 100% light + 4.0% + 8.5% fs pixel interaction test (3) pit at 25 c 5% fs noise level (4) vn all temp 3 6 mv (rms) hold spec, same as prnu prnuh all temp, 100% light, 62.5 khz + 4.0% + 8.5% fs output settling time ts all temp 450 750 ns array lag (5) alag at 25 c 0.5% fs dark signal non uniformity (6) dsnu at 25 c at 125 c 80 140 120 440 mv mv analog output saturation all temp 3.0 v change in sensitivity with te m- perature at 880nm (7) 0 0.3 0.8 %/ c operating free temp - 40 125 c supply current (8) idd 2 5 8 ma average analog output (1) vaolight at 25 c, 100% light 1.5 1.7 2.1 v (0) after power on, the first integration scan is not guaranteed correct. first scan after power on is needed for initializing digital levels on chip. after a si and 132 proper clk signals, the system is fully initialized and all further scans are valid. the next si will provide a valid scan. (1) absolute light measurements are very test - setup dependent and should be regarded w ith caution. relative measurements are possible with + 1% accuracy. (2) prnu is defined as the worst case deviation of any pix elvalue (pixel 3 till 130) to the average light value. pixelvalue = (vout of a pixel at 100% light ? vout of same pixel at 0% l ight) the 90255ba has a cosign shaped gain: external pixels have 15% more gain than middle pixels (3) pit = (vout of pixel 132 @ 10 w ? vout of pixel 132 @ 0 w) / (vaverage @ 10 w ? vaverage @ 10 w) (4) noise: we compare 5 different measurements, normali ze them and then take the rms value. (5) array lag is defined as: (vaverage 0 w 1 vaverage 0 w 2 ) / ((vaverage 10 w vaverage 0 w 2 ). where 0 w 1 is a 0% light level, 1ms after a 100% light level. (there can still be some light effects). 0 w 2 is a 0% light level, 10ms after a 100% light level, which should be a true dark reference. (6) dsnu is defined as: (max vout of pixel i @ o% light) - (min vout of pixel j @ o% light) for pixels 3 thru 130 (7) sensitivity always increases with rising temperature. ( 8) idd is measured with rload disconnected fron the output pin.
mlx90255ba linear optical array mlx90255ba linear optical array page 4 rev 1 . 0 22 / january / 01 general description (continued from page 1) as the si pulse is clocked through the shift register, the charge stored on the sam pling capacitors is sequentially connected to a charge - coupled output amplifier that generates a voltage on analog output ao. tw o dummy pixel values are shifted out first, then the 128 actual pixel bits, followed by two additional dummy pixel bits, for a t otal of 132 data bits. the integrator reset period ends 18 clock cycles after the si pulse is clocked in. so the light - integrati on starts after the 18 th clk pulse. the light - integration ends at the next si pulse. between the end of the 132 nd clock pulse a nd the next si pulse, a minimum time of 10sec is necessary for an effective s&h function. so the minimum integration time of th e mlx90255ba is (132 - 18) * ts +10s and thus dependent on clock speed. (ts = clock period) after the 132 data bits are clocked o ut, the output becomes high impedance. (see figure) the ao is driven by a source follower that requires an external pulldown res istor. (typically 330 w ) the output is nominally 125mv for no light input and 2.4v for a nominal full - scale output. the pixel gai n is 15% bigger at the edges than in the middle (cosine correction) in order to get a flat output when illuminating the device w ith a single led light source. the mlx90255 is intended for use in a wide variety of applications, including: image scanning, m ark and code reading, optical character recognition (ocr) and contact imaging, edge detection and positioning, and optical linea r and rotary encoding. the mlx90255 is a replacement for the texas instruments' tsl1301 and tsl1401 parts. s tresses beyond those listed under "absolute max i- mum ratings" may cause permanent damage to the device. these are stress ratings only, and functional oper a- tion of the device at these or any other conditions beyond those indicated under "recommended ope r- a t ing conditions" is not implied. exposure to absolute - maximum - rated conditions for extended periods may affect device reliabilit y. supply voltage, vdd +7v digital input current range - 20 to 20 ma operating free - air temper a- ture range, ta - 40c to +125c (automotive compliant optical package) storage temperature range, tstg - 40c to +125c lead temperature 1.6 mm (1/16 inch) from case for 10 seconds 260c absolute maximum ratings
mlx90255ba linear optical array mlx90255ba linear optical array page 5 rev 1 . 0 22 / january / 01 typical photodiode spectral response curve (%), without anti reflection coating* *there is also an option for an anti reflection coating . this will remove the interference ripples in the figure above. with this special anti reflection coating, the sensitivity curve in function of wavelength will be somewhat lower (typically 4%) but will no longer display interference ripples.
mlx90255ba linear optical array mlx90255ba linear optical array page 6 rev 1 . 0 22 / january / 01 la (smd8) pin description pin symbol description 1 si serial input. si defines the start of the data - out sequence 2 clk clock. the clock controls charge transfer, pixel output and reset (together with si) 3 ao analog output 4 vdd supply voltage. supply voltage for both analog and digital ci r- cuits 5, 6, 7, 8 vss ground (substrate). all vss pins are referenced to the substrate. note: all 4 pins are internally connected to form a large ground plane to get better emc characteristics. mlx90255 (smd8) la package dimensions pin 1 2 3 4 5 6 7 8
mlx90255ba linear optical array mlx90255ba linear optical array page 7 rev 1 . 0 22 / january / 01 mlx90255 ga (glp5) package dimensions ga (glp5) pin description pin symbol description 1 si serial input. si defines the start of the data - out sequence 2 clk clock. the clock controls charge transfer, pixel output and reset (together with si) 3 ao analog output 4 vdd supply voltage. supply voltage for both analog and digital ci r- cuits 5 vss ground (substrate). all vss pins are referenced to the substrate. pin 1 2 3 4 5
mlx90255ba linear optical array mlx90255ba linear optical array page 8 rev 1 . 0 22 / january / 01 for the latest version of this document, go to our website at: www.melexis.com or for additional information contact melexis di rect: usa melexis inc. 41 locke road, concord, nh 03301 phone: +1 603 223 2362 fax: +1 603 223 9614 e - mail: sales_usa@melexi s.com united kingdom silicon concepts pcb lynchborough road, hampshire gu30 7sb, united kingdom phone: +44 1428 751 617 fax: +44 1428 751 603 e - mail: sales_uk@melexis.com germany schiess - strasse 55 , 4054 9 d sseldorf, germany phone: +49 211 5360212 f ax: +49 211 5360250 e - mail: sales_de@melexis.com france melexis france tour arago, 5 rue bellini, 92806 puteaux - la - dfense, france. phone: +33 1 47 78 11 34 fax: +33 1 47 78 06 35 e - mail: sales_france@melexis.com italy dimacred irl via papa giovanni xxiii no. 25, 20046 biassono, italy phone: +39 039 249 4856 fax: +39 039 491773 e - mail: sales_italy@melexis.com japan satori electric co., ltd 1 - 14 - 10 shiba, minato - ku, t okyo, japan phone: +81 3 3452 7171 fax: +81 3 3769 2197 e - mail: sales_japan@melexis.com taiwan beechwood int?l taiwan co. r oom 8, 17f, no. 189, taipei, taiwan phone: +886 2 2739 3322 fax: +886 2 2739 3090 e - mail: sales_taiwan@melexis.com mlx90255 leadframes ga (glp5) leadframe la (smd8) leadframe
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