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sp703/704ds/07 sp703/704 low power microprocessor supervisory ? copyright 2000 sipex corporation 1 sp703/sp704 low power microprocessor supervisory with battery switch-over the sp703/704 devices are microprocessor ( m p) supervisory circuits that integrate a myriad of components involved in discrete solutions to monitor power-supply and battery-control functions in m p and digital systems. the series will significantly improve system reliability and operational efficiency when compared to discrete solutions. the features of the sp703/704 devices include a manual reset input, a m p reset and backup-battery switchover, and power- failure warning. the series is ideal for applications in computers, controllers, intelligent instruments and automotive systems. all designs where it is critical to monitor the power supply to the m p and its related digital components will find the series to be an ideal solution. n precision voltage monitor: sp703 at 4.65v sp704 at 4.40v n reset time delay - 200ms n debounced ttl/cmos - compatible manual - reset input n minimum component count n 60 m a maximum operating supply current n 0.6 m a maximum battery backup current n 0.1 m a maximum battery standby current n power switching 250ma output in v cc mode (0.6 w ) 25ma output in battery mode (5 w ) n voltage monitor for power fail or low battery warning n available in 8 pin so and dip packages n reset asserted down to v cc = 1v n pin compatible upgrades to max703/max704 description pinout v out v cc gnd pfi v batt reset mr pfo 1 2 3 4 5 6 7 8 internal block diagram 1.25v 1.25v battery switchover circuitry pfi mr v cc v batt reset generator v out reset pfo ? now available in lead free
sp703/704ds/07 sp703/704 low power microprocessor supervisory ? copyright 2000 sipex corporation 2 absolute maximum ratings these are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifica- tions below is not implied. exposure to absolute maxi- mum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. v cc ........................................................-0.3v to 6.0v v batt .....................................................-0.3v to 6.0v all other inputs......................................-0.3v to (v cc +0.3v) input current: v cc .........................................................250ma v batt ........................................................50ma gnd........................................................20ma output current: v out .....short-circuit protected for up to 10sec all other inputs................................ .20ma rate of rise, v cc ,v batt ................. .100v/ m s continuous power dissipation.......500mw storage temperature.......-65 c to +160 c lead temperature(soldering,10sec).................+300 c esd rating.............................4kv human body model specifications v cc =4.75v to 5.50v for sp703, v cc = 4.50v to 5.50v for sp704, v batt =2.80v, t a =t min to t max , typical specified at 25 o c, unless otherwise noted. s r e t e m a r a p. n i m. p y t. x a ms t i n us n o i t i d n o c , e g n a r e g a t l o v g n i t a r e p o05 . 5s t l o v v c c v r o t t a b 1 e t o n , i , t n e r r u c y l p p u s y l p p u s ,5 30 6 m ai g n i d u l c x e t u o i y l p p u s , e d o m p u k c a b y r e t t a b n i v c c v , v 0 = t t a b v 8 . 2 = 1 0 0 . 06 . 0 m a v t t a b 2 e t o n , t n e r r u c y b d n a t s1 . 0 - 2 0 . 0 m a v c c v > t t a b v 2 . 0 + v t u o t u p t u ov c c 1 . 0 -v c c 3 0 . 0 - v c c 5 1 . 0 - s t l o v i t u o a m 0 5 = i t u o a m 0 5 2 = v t u o e d o m p u k c a b - y r e t t a b n i v c c v < t t a b v 2 . 0 - v t t a b 5 1 . 0 -v t t a b 4 0 . 0 - v t t a b 0 2 . 0 - s t l o v i t u o a m 5 = i t u o a m 5 2 = , d l o h s e r h t h c t i w s y r e t t a b v c c v o t t t a b 0 2 0 2 - v m p u - r e w o p n w o d - r e w o p s i s e r e t s y h r e v o h c t i w s y r e t t a b0 4v mk a e p o t k a e p d l o h s e r h t t e s e r0 5 . 4 5 2 . 4 5 6 . 4 0 4 . 4 5 7 . 4 0 5 . 4 s t l o v 3 0 7 p s 4 0 7 p s
sp703/704ds/07 sp703/704 low power microprocessor supervisory ? copyright 2000 sipex corporation 3 s r e t e m a r a p. n i m. p y t. x a ms t i n us n o i t i d n o c s i s e r e t s y h d l o h s e r h t t e s e r0 4v mk a e p o t k a e p t , h t d i w e s l u p t e s e r s r 0 4 10 0 20 8 2s m e g a t l o v t u p t u o t e s e rv c c 5 . 1 -i e c r u o s 0 0 8 = m a 1 . 0 4 0 0 . 0 4 . 0 3 . 0 s t l o vi k n i s a m 2 . 3 = i k n i s 0 5 = m v , a c c v 0 . 1 = d l o h s e r h t t u p n i r m w o l h g i h0 . 2 8 . 0v h t d i w e s l u p m u m i n i m r m0 5 1s n y a l e d t e s e r o t r m0 5 2s n t n e r r u c p u l l u p r m0 0 10 5 20 0 6a v 0 = r m d l o h s e r h t t u p n i i f p0 0 2 . 10 5 2 . 10 0 3 . 1s t l o v t n e r r u c t u p n i i f p5 2 -1 0 . 05 2a n e g a t l o v t u p t u o o f pv c c 5 . 1 - 1 . 04 . 0 s t l o v i e c r u o s 0 0 8 = m a i k n i s a m 2 . 3 = note 1: either v cc or v batt can go to 0v if the other is greater than 2.0v. note 2: "-" equals the battery-charging current, "+" equals the battery-discharging current. specifications (continued) v cc =4.75v to 5.50v for sp703, v cc = 4.5 0v to 5.50v for sp704, v batt =2.80v, t a =t min to t max , typical specified at 25 o c, unless otherwise noted.
sp703/704ds/07 sp703/704 low power microprocessor supervisory ? copyright 2000 sipex corporation 4 pin assignments pin 1 v out output supply voltage. v out connects to v cc when v cc is greater than v batt and v cc is above the reset thresh- old. when v cc falls below v batt and v cc is below the reset threshold, v out connects to v batt . connect a 0.1 m f ca- pacitor from v out to gnd. pin 2 v cc +5v supply input pin3 gnd ground reference for all signals pin 4 pfi power-fail input. this is the noninverting input to the power-fail com- parator. when pfi is less than 1.25v, pfo goes low. connect pfi to gnd or v out when not used. pin 5 pfo power-fail output. pin 6 mr manual reset input. this input generates a reset pulse when pulled below 0.8v. this active low input is ttl/ cmos compatible and can be shorted to ground with a switch. it has an internal 250 m a (typical) pull-up current. leave this pin floating when not used. pin 7 reset (active low)C reset output. reset output goes low whenever v cc falls below the reset threshold or whenever mr is pulled below 0.8v for longer than 150ns. reset remains low for 200ms after v cc crosses the reset threshold voltage on power-up or after being triggered by mr. pin 8 v batt backup-battery input. when v cc falls below the reset threshold, v batt will be switched to v out if v batt is 20mv greater than v cc . when v cc rises 20mv above v batt , v out will be recon- nected to v cc . the 40mv hysteresis pre- vents repeated switching if v cc falls slowly. pinout internal block diagram v out v cc gnd pfi v batt reset mr pfo 1 2 3 4 5 6 7 8 1.25v 1.25v battery switchover circuitry pfi mr v cc v batt reset generator v out reset pfo
sp703/704ds/07 sp703/704 low power microprocessor supervisory ? copyright 2000 sipex corporation 5 v cc supply current vs. temperature (normal mode) battery supply current vs. temperature (backup mode) 51 47 43 39 35 31 27 23 19 -60 -30 0 30 60 90 120 150 v cc current ( m a) temperature deg. c 2.9 2.4 1.9 1.4 0.9 0.4 -0.1 v batt current ( m a) -60 temperature deg. c -40 -20 0 20 40 60 80 100 120 140 v cc =5v v batt =2.8v v cc =0v v batt =2.8v typical characteristics (25 o c, unless otherwise noted) -60 -30 0 30 60 90 120 150 temperature deg. c pfi threshold vs. temperature 1.256 1.254 1.252 1.250 1.248 1.246 pfi threshold (v) v cc =5v v batt =0 no load on pfo v batt to v out on resistance vs. temperature v cc to v out on resistance vs. temperature 15 10 5 0 resistance (ohms) -60 -30 0 30 60 90 120 150 temperature deg. c 0.9 0.8 0.7 0.6 0.5 0.4 0.3 resistance (ohms) temperature deg. c v batt =2.8v v batt =4.5v v cc =0v v batt =2v reset threshold vs. temperature 4.70 4.69 4.68 4.67 4.66 4.65 4.64 4.63 4.62 4.61 4.60 reset threshold (v) temperature deg. c v batt =0v power down v cc =5v v batt =0v reset output resistance vs. temperature reset delay vs. temperature 600 500 400 300 200 100 0 resistance (ohms) -60 -30 0 30 60 90 120 150 temperature deg. c 212 210 208 206 204 202 200 reset delay (ms) -60 -30 0 30 60 90 120 150 temperature deg. c v cc =5v,v batt =2.8v soucing current v cc =0v to 5v step, v batt =2.8v v cc =0v,v batt =2.8v sink current ie+2 ie+1 ie+0 ie-1 ie-2 ie-3 ie-4 ie-5 ie-6 ie-7 ie-8 v batt current( m a) log scale .0000 5.000 v cc (0.5v/div) battery current vs. v cc voltage v batt =2.8v sp703 -60 -30 0 30 60 90 120 150 -60 -30 0 30 60 90 120 150
sp703/704ds/07 sp703/704 low power microprocessor supervisory ? copyright 2000 sipex corporation 6 figure 1. v cc to v out vs. output current figure 3a. sp703 reset output voltage vs. supply voltage figure 2. v batt to v out vs. output current figure 3b. circuit for the reset output voltage vs. supply voltage gnd reset v cc 330pf v cc 2k w reset v batt = 0v t a = +25 c voltage drop(mv) 1 10 100 1000 iout (ma) v cc =4.5v v batt =0v slope=0.6 w voltage drop(mv) 1 10 100 iout (ma) v batt =4.5v v cc =0v slope=5 w 1000 100 10 1 1000 100 10 1 reset 0v v cc v batt = 0v t a = 25 c o 0v 2v div 1sec/div
sp703/704ds/07 sp703/704 low power microprocessor supervisory ? copyright 2000 sipex corporation 7 figure 4a. sp703 reset response time figure 4b. circuit for the reset response time gnd reset v cc 30pf v cc 10k w t a = +25 c figure 5b. circuit for the power-fail comparator response time (fall) figure 5a. power-fail comparator response time (fall) 30pf 1k w pfo +1.25v +5v pfi v cc = +5v t a = +25 c reset v cc +4v +5v +5v 0v +1.3v +1.2v pfi v cc = 5v v batt = 0v pfo 0v 5v 2 m s/div 500ns/div
sp703/704ds/07 sp703/704 low power microprocessor supervisory ? copyright 2000 sipex corporation 8 figure 6a. power-fail comparator response time (rise) figure 6b. circuit for the power-fail comparator response time (rise) 30pf 1k w pfo +1.25v +5v pfi v cc = +5v t a = +25 c figure 7. timing diagram +1.3v +1.2v pfi v cc = 5v v batt = 0v 3v pfo 0v 2 m s/div v cc reset pfo v out 0v +5v 3.0v 0v 0v 0v +5v +5v +5v t rs v batt = pfi = 3.0v
sp703/704ds/07 sp703/704 low power microprocessor supervisory ? copyright 2000 sipex corporation 9 theory of operation reset output the microprocessor's ( m p's) reset input starts the m p in a known state. when the m p is in an unknown state, it should be held in reset. the sp703/704 assert reset during power-up and prevent code execution errors during power- down or brownout conditions. on power-up, once v cc reaches 1v, reset is guaranteed to be a logic low. as v cc rises, reset remains low. when v cc exceeds the reset threshold, reset will remain low for 200ms, figure 9 . if a brownout condition occurs and v cc dips below the reset threshold, reset is triggered. each time reset is trig- gered, it stays low for the reset pulse width interval. if a brownout condition interrupts a previously initiated reset pulse, the reset pulse continues for another 200ms. on power-down, once v cc goes below the threshold, reset is guaranteed to be logic low until v cc drops below 1v. reset is also triggered by a manual reset features the sp703/704 devices provide four key func- tions: 1. a battery backup switching for cmos ram, cmos microprocessors, or other logic. 2. a reset output during power-up, power-down and brownout conditions. 3. a reset pulse if the manual reset has been pulled below 0.8v for at least 150ns. 4. a 1.25v threshold detector for power-fail warning, low battery detection, or to monitor a power supply other than +5v. the sp703/704 devices differ only in their supply voltage monitor level. the sp703 generates a reset when v cc drops below 4.65v while the sp704 generates a reset below 4.4v. the sp703/704 devices are ideally suited for applications in automotive systems, intelligent instruments, and battery-powered computers and controllers. all designs into an environment where it is critical to monitor the power supply to the m p and its related digital components will find the sp703/704 ideal. figure 8. typical operating circuit gnd gnd reset nmi v cc reset pfo mr v out bus v cc gnd v batt r 2 r 1 unregulated regulated +5v v cc 0.1 m f pfi dc lithium battery 3.6v m p cmos ram pushbutton switch
sp703/704ds/07 sp703/704 low power microprocessor supervisory ? copyright 2000 sipex corporation 10 power-fail comparator the power-fail comparator can be used as an under-voltage detector to signal the failing of a power supply (it is completely separate from the rest of the circuitry and does not need to be dedicated to this function). the pfi input is compared to an internal 1.25v reference. if pfi is less than 1.25v, pfo goes low. the external voltage divider drives pfi to sense the unregu- lated dc input to the +5v regulator. the volt- age-divider ratio can be chosen such that the voltage at pfi falls below 1.25v just before the +5v regulator drops out. pfo then triggers an interrupt which signals the m p to prepare for power-down. when v batt connects to v out , the power-fail comparator is turned off and pfo is forced low to conserve backup-battery power. backup-battery switchover in the event of a brownout or power failure, it may be necessary to preserve the contents of ram. with a backup battery installed at v batt , the ram is assured to have power if v cc fails. as long as v cc exceeds the reset threshold, v out connects to v cc through a 0.6 w pmos power switch. once v cc falls below the reset threshold, v cc or v batt , whichever is higher, switches to v out . v batt connects to v out through a 5 w switch only when v cc is below the reset threshold and v batt is greater than v cc . when v cc exceeds the reset threshold, it is connected to v out , regardless of the voltage applied to v batt figure 9 . during this time, the diode (d1) between v batt and v out will conduct current from v batt to v out if v batt is more than .6v above v out . when v batt connects to v out , backup mode is activated and the internal circuitry will be powered from the battery figure 10 . when v cc is just below v batt , in the backup mode the current drawn from v batt will be typically 30 m a. when v cc drops to more than 1v below v batt , the internal switchover comparator shuts off and the supply current falls to less than 0.6 m a. reset threshold = 4.65v in sp703 reset threshold = 4.40v in sp704 figure 9. backup-battery switchover block diagram sw1 d1 d2 d3 sw2 v batt v cc gnd v out n o i t i d n o c1 w s2 w s v c c d l o h s e r h t t e s e r >n e p od e s o l c v c c d n a d l o h s e r h t t e s e r < v c c v > t t a b n e p od e s o l c v c c d n a d l o h s e r h t t e s e r < v c c v < t t a b d e s o l cn e p o
sp703/704ds/07 sp703/704 low power microprocessor supervisory ? copyright 2000 sipex corporation 11 l a n g i ss u t a t s v c c v m o r f d e t c e n n o c s i d t u o v t u o v o t d e t c e n n o c t t a b h g u o r h t 8 l a n r e t n i n a w h c t i w s s o m p v t t a b v o t d e t c e n n o c t u o t n e r r u c . s i y r e t t a b e h t m o r f n w a r d 6 . 0 n a h t s s e l m s a g n o l s a , a v c c v < t t a b . v 1 - i f p s i r o t a r a p m o c l i a f - r e w o p . d e l b a s i d o f pw o l c i g o l t e s e rw o l c i g o l r md e l b a s i d s i t e s e r l a u n a m using a high capacity capacitor as a backup power source v batt has the same operating voltage range as v cc , and the battery-switchover threshold volt- ages are typically +20mv centered at v batt , allowing use of a capacitor and a simple charg- ing circuit as a backup source (see figure 12) . if v cc is above the reset threshold and v batt is 0.5v above v cc , current flows to v out and v cc from v batt until the voltage at v batt is less than 0.5v above v cc . leakage current through the capacitor charging diode and the sp703/704 internal power diode eventually discharges the capacitor to v cc . also, if v cc and v batt start from 0.5v above the reset threshold and power is lost at v cc , the capacitor on v batt discharges through v cc until v batt reaches the reset threshold; the sp703/704 then switches to battery-backup mode. figure 11. allowable backup-battery voltages figure 10. input and output status in battery-backup mode. to enter the battery-backup mode, v cc must be less than the reset threshold and less than v batt . figure 12. backup power source using high capacity capacitor with sp703 and a +5v 5% supply figure 13. backup power source using high capacity capacitor with sp704 and a +5v 10% supply t r a p r e b m u n m u m i x a m y r e t t a b - p u k c a b ] v [ e g a t l o v 3 0 7 p s0 8 . 4 4 0 7 p s5 5 . 4 v cc +5v gnd v batt v out reset connect to static ram to m p 0.1f connect sp703 v cc +5v gnd v batt v out reset connect to static ram to m p 100k w 0.1f connect sp704
sp703/704ds/07 sp703/704 low power microprocessor supervisory ? copyright 2000 sipex corporation 12 allowable backup power-source batteries lithium batteries work very well as backup batteries due to very low self-discharge rate and high energy density. single lithium batteries with open-circuit voltages of 3.0v to 3.6v are ideal. any battery with an open-circuit voltage less than the minimum reset threshold plus 0.3v can be connected directly to the v batt input of this series with no additional circuitry; see figure 8 . however, batteries with open-circuit voltages that are greater than this value cannot be used for backup, as current is sourced into v out through the diode (d1 in figure 9) when v cc is close to the reset threshold. operation without a backup power source if a backup power source is not used, ground v batt and connect v out to v cc . since there is no need to switch over to any backup power source, v out does not need to be switched. a direct connection to v cc eliminates any voltage drops across the switch which may push v out below v cc . replacing the backup battery the backup battery can be removed while v cc remains valid, without danger of triggering reset/reset. as long as v cc stays above the reset threshold, battery-backup mode cannot be entered. adding hysteresis to the power-fail comparator hysteresis adds a noise margin to the power-fail comparator and prevents repeated triggering of pfo when v in is close to its trip point. figure 14 shows how to add hysteresis to the power-fail comparator. select the ratio of r 1 and r 2 such that pfi sees 1.25v when v in falls to its trip point (v trip ). r 3 adds the hysteresis. it will typically be an order of magnitude greater (about 10 times) than r 1 or r 2 . the current through r 1 and r 2 should be at least 1 m a to ensure that the 25na (max) pfi input current does not shift the trip point. r 3 should be larger than 10k w so it does not load down the pfo pin. capacitor c1 adds additional noise rejection. monitoring a negative voltage the power-fail comparator can be used to monitor a negative supply rail using the circuit of figure 15 . when the negative rail is valid, pfo is low. when the negative supply voltage drops, pfo goes high. this circuit's accuracy is affected by the pfi threshold tolerance, the v cc voltage, and the resistors, r1 and r2. figure 14. adding hysteresis to the power-fail comparator pfi pfo r 3 *c 1 r 2 r 1 v in connect to m p v cc +5v gnd pfo v in +5v v l v h v trip 0v 0v *optional v trip = r 2 r 1 + r 2 v h = r 2 || r 3 r 1 + r 2 || r 3 1.25 r 2 = v l - 1.25 r 1 5.0 - 1.25 r 3 + 1.25 1.25
sp703/704ds/07 sp703/704 low power microprocessor supervisory ? copyright 2000 sipex corporation 13 interfacing to microprocessors with bidirectional reset pins microprocessors with bidirectional reset pins, such as the motorola 68hc11 series, can contend with this series' reset output. if, for example, the reset output is driven high and the m p wants to pull it low, indeterminate logic levels may result. to correct this, connect a 4.7k w resistor between the reset output and the m p reset i/o, as in figure 16 . buffer the reset output to other system components. figure 15. monitoring a negative voltage figure 16. interfacing to microprocessors with bidirectional reset i/o pfi pfo r 2 r 1 v cc +5v gnd pfo v- +5v *v trip 0v 0v 5.0 - 1.25 r 1 1.25 - v trip r 2 v- = *v trip is a negative voltage v cc +5v gnd v cc +5v gnd reset reset 4.7k w m p buffered reset connects to system components
sp703/704ds/07 sp703/704 low power microprocessor supervisory ? copyright 2000 sipex corporation 14 d alternate end pins (both ends) d1 = 0.005" min. (0.127 min.) e package: plastic dual?n?ine (narrow) dimensions (inches) minimum/maximum (mm) a = 0.210" max. (5.334 max). e1 c l a2 a1 = 0.015" min. (0.381min.) b b1 e = 0.100 bsc (2.540 bsc) e a = 0.300 bsc (7.620 bsc) a2 b b1 c d e e1 l 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356) 0.355/0.400 (9.017/10.160) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0? 15 (0?15? 8?in
sp703/704ds/07 sp703/704 low power microprocessor supervisory ? copyright 2000 sipex corporation 15 d eh package: plastic small outline (soic) (narrow) dimensions (inches) minimum/maximum (mm) 8?in a a1 l b e h x 45 a a1 b d e e h h l 0.053/0.069 (1.346/1.748) 0.004/0.010 (0.102/0.249 0.014/0.019 (0.35/0.49) 0.189/0.197 (4.80/5.00) 0.150/0.157 (3.802/3.988) 0.050 bsc (1.270 bsc) 0.228/0.244 (5.801/6.198) 0.010/0.020 (0.254/0.498) 0.016/0.050 (0.406/1.270) 0?8 (0?8?
sp703/704ds/07 sp703/704 low power microprocessor supervisory ? copyright 2000 sipex corporation 16 ordering information model temperature range package types sp703cn..........................................................0 c to +70 c....................................................8-pin nsoic sp703cp........................................................0 c to +70 c.........................................................8-pin pdip sp703en......................................................-40 c to +85 c.....................................................8-pin nsoic sp703ep.......................................................-40 c to +85 c....................................................... 8-pin pdip sp704cn........................................................0 c to +70 c......................................................8-pin nsoic sp704cp........................................................0 c to +70 c......................................................... 8-pin pdip sp704en......................................................-40 c to +85 c................................................... ..8-pin nsoic sp704ep.......................................................-40 c to +85 c....................................................... 8-pin pdip available in lead free packaging. to order, add "-l" suffix to the part number. example: sp6660eu/tr=tape & reel. sp6660eu-l/tr = lead free.

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