View WINBONDELECTRONICSCORP-W9321S_6933316.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

p reliminary w9321 adpcm codec publication release date: may 1999 - 1 - revi sion a1 table of contents- 1. general description ................................ ................................ ................................ ........................... 2 2. features ................................ ................................ ................................ ................................ .................. 2 3. pin configuration ................................ ................................ ................................ ................................ . 3 4. pin descriptions ................................ ................................ ................................ ................................ .... 3 4.1. power control interface ................................ ................................ ................................ ....................... 3 4.2. analog interface ................................ ................................ ................................ ................................ .. 4 4.3. adpcm/pcm serial interface ................................ ................................ ................................ .............. 5 4.4. serial setup port(ssp) interface ................................ ................................ ................................ ......... 5 5. system diagram ................................ ................................ ................................ ................................ ..... 6 5.1 pair gain system ................................ ................................ ................................ ................................ . 6 5.2. cordless phone system ................................ ................................ ................................ ...................... 7 6. block diagram ................................ ................................ ................................ ................................ ....... 8 7. functional descriptions ................................ ................................ ................................ ................... 8 7.1. power supply management system ................................ ................................ ................................ .... 8 7.2. sd codec-filter ................................ ................................ ................................ ................................ ... 9 7.3. dsp engine ................................ ................................ ................................ ................................ ........ 9 7.4. serial setup port (ssp) ................................ ................................ ................................ ..................... 12 7.5. sequence and control ................................ ................................ ................................ ....................... 14 7.6. i/o level ................................ ................................ ................................ ................................ ........... 14 8. control and status registers ................................ ................................ ................................ ...... 14 8.1. introduction ................................ ................................ ................................ ................................ ....... 15 8.2. byte register description ................................ ................................ ................................ .................. 15 9. electrical characteristics ................................ ................................ ................................ ........... 24 9.1. absolute maximum ratings ................................ ................................ ................................ ............... 24 9.2. dc characteristics ................................ ................................ ................................ ............................ 24 9.3. analog transmission characteristics ................................ ................................ ................................ . 25 9.4. analog electrical characteristics ................................ ................................ ................................ ....... 26 9.5. digital switching characteristics ................................ ................................ ................................ ........ 27 10. application information ................................ ................................ ................................ ................ 30 10.1. handset application for wireless communication ................................ ................................ ............ 30 10.2. transformer application for public switching telephone network (pstn) ................................ ........ 30 11. how to program the tone generator ................................ ................................ ...................... 31 11.1. introduction ................................ ................................ ................................ ................................ ..... 31 11.2. tone frequency coefficient calculation ................................ ................................ ........................... 32 11.3. tone attenuation coefficient calculation ................................ ................................ ......................... 32 11.4. frequency coefficients for the dtmf signal ................................ ................................ .................... 32 12. package dimensions ................................ ................................ ................................ ........................ 33
p reliminary w9321 - 2 - 1. general description the winbond adpcm codec is a single channel chip incorporating a sd pcm codec filter with a 32k, 24k, 16k adpcm encoder/decoder complying with the ccitt g.721 and g.726 standards. in addition, this chip also meets the pcm conformance specification of the ccitt g.714 recommendation. this chip allows full-duplex operation over a wide voltage range from 2.7 to 5.25 volts; it's low power consumption makes it ideal for battery or ac powered applications. the chip includes a serial setup port (ssp) interface with a 16 byte setup and status registers. a microcontroller can access many built-in features through the ssp interface. in addition, this chip also consists of some op amplifiers integrated with a sd pcm codec-filter to allow for easy control of the analog interface. this chip can be used on two key applications. one application is for wireless telephone systems such as ct2, dect. another application is for public switch telephone network (pstn) applications such as pair gain. see the section on application information for more details. 2. features single 2.7 to 5.25 volt power supply master clock rate: 10.24 mhz oscillator typically for winbond cordless system typical power consumption of 85 mw for 3 volt; power down of 0.2 mw full-duplex single channel speech codec linear 14 bit sd pcm codec-filter for a/d and d/a converter complete mu-law and a-law companding adpcm transcoder for 64, 32, 24, and 16 kbps bit rates serial pcm/adpcm transfer data rate from 128 to 2048 kbps unive rsal programmable dual tone generator such as dtmf application noise burst detection algorithm for adpcm receive path analog input: differential op amplifier with external gain adjustment for microphone interface programmable transmit gain, receive attenuation, and sidetone gain analog output: - differential power driver with 300 w load and external gain adjustment - differential auxiliary driver with 300 w load for ringer interface 3 volt regulator for digital circuit 5 volt charge pump for a nalog circuit low voltage applications 16 setup and status registers with 8 bits for monitoring microcontroller applications packaged in 28-pin dip/sop
p reliminary w9321 publication release date: may 1999 - 3 - revision a1 3. pin configuration tg ti- ti+ vag ro axo- axo+ v dsp v ext pi po- po+ pdi/reset ssp en v dd fsr bclkr dr c1+ c1- v ss mclk dt bclkt fst ssp rx ssp tx ssp clk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 figure 3-1 4. pin descriptions 4.1. power control interface pin name pin no. i/o function v ext 9 i this pin is the external power supply between 2.7 and 5.25 volt. this pin should be decoupled to v ss with a 0.1 m f capacitor. v dsp 8 o this is the output of the on-chip 3 volt regulator which supplies the digital circuit of the chip. this pin should be decoupled to v ss with a 0.1 m f ceramic capacitor. this pin cannot be used for powering external loads. v dd 28 i/o this is the output of the on-chip 5 volt charge pump which supplies the analog circuit. when v ext = +5v 5%, v dd is an input and should be connected to v ext externally. charge pump capacitor c1+ and c1- should not be used and br0[b2] must be written into logic "1". in this case v ext and v dd can share the same 0.1 m f decoupling capacitor to v ss . when v ext = 2.7 to 5.25 volt, v dd is a 5 volt charge pump output and should not be connected to v ext . v dd should be decoupled to v ss with a 0.1 m f capacitor. this pin cannot be used for powering external loads. v ss 22 i this pin connects the analog and digital ground and is typically connected to 0 volt.
p reliminary w9321 - 4 - 4.1. power control interface, continued pin name pin no. i/o function vag 4 o this is the analog ground output pin which supplies a 2.5 volt reference voltage for all analog signal processing. this pin should be decoupled to v ss with 0.1 m f capacitor. this pin becomes high impedance when the chip enters an analog power down mode. c1+, c1- 23, 24 i the charge pump capacitor pins. when v ext = +5v 5%, these capacitors c1+ and c1- should not be used and br0[b2] must be written into logic "1". when v ext = 2.7 to 5.25 volt, a 0.1 m f capacitor should be placed between c1+ and c1-. pdi/reset 13 i the power down/reset input pin. when at logic 0, the chip enters a power down mode. when it switches from logic 0 to logic 1, this chip is active and resets the adpcm transcoder and all circuits. 4.2. analog interface pin name pin no. i/o function tg 1 o this pin is the analog output of the transmit input amplifier. it can be used to set the gain by external resistors. when the chip is in analog power down mode, this pin is high impedance. ti- 2 i this pin is the inverting input of the transmit input amplifier. connecting this pin and ti+ (pin-3) to v dd will force tg into a high impedance state. ti+ 3 i the non-inverting input of the transmit input amplifier. connecting this pin and ti- (pin-2) to v dd will force tg to be high impedance. note this pin may be connected to the vag pin for an inverting configuration if the input signal is referenced to the vag pin. ro 5 o this pin is the non-inverting analog output of the receive smoothing filter. this pin can typically drive a 2 k w load to 1.13 volt peak referenced to the vag pin. this pin may be dc referenced to either the vag pin or v ext /2 determined by br2 (b7). when the chip is in analog power down mode, this pin is high impedance. axo- 6 o this pin is the auxiliary inverting analog output. this pin can drive a 300 w load differentially. its output can swing between 0.5 volt and v ext . this pin may be dc referenced to either the vag pin or v ext /2 by br2 (b7). when the chip is in analog power down mode, this pin is high impedance. axo+ 7 o this pin is the auxiliary non-inverting analog output. this pin can drive a 300 w load differentially. its output can swing between 0.5 volt and v ext . this pin may be dc referenced to either the vag pin or v ext /2 by br2 (b7). when the chip is in analog power down mode, this pin is high impedance.
p reliminary w9321 publication release date: may 1999 - 5 - revision a1 4.2. analog interface, continued pin name pin no. i/o function pi 10 i this pin is the inverting input to the po- (pin-11) power amplifier. it may be dc referenced to either the vag pin or v ext /2 by br2 (b7). this pin and po- are used to set the gain by using external resistors. connecting this pin to v dd will power down the chip and the po+ and po- outputs will be high impedance. po- 11 o this pin is the inverting power amplifier output. its operation is same as the axo- (pin-6). in the application, this pin can drive the speaker on the receiver. po+ 12 o this pin is the non-inverting power amplifier output. its operation is the same as the axo+ (pin-7). in the application, this pin can drive the speaker of the receiver. 4.3. adpcm/pcm serial interface pin name pin no. i/o function mclk 21 i this pin is the system master clock input pin. it typically accepts 10.24 mhz for winbond cordless applications. this pin is the oscillator input. fst 18 i this pin is an 8 khz pulse train for transmission of frame syncs. this pin synchronizes the output of the dt pin (pin-20). bclkt 19 i the bit clock for transmission. it shifts out the data on the dt pin on the rising edge. the frequency may vary from 128k to 2048 khz. dt 20 o this pin is tri-state output data for transmission controlled by fst and bclkt pin. fsr 27 i this pin is an 8k hz pulse train to receive frame syncs. this pin synchronizes the input of the dr pin (pin-25). bclkr 26 i this pin is the receive bit clock. it shifts data on the dr pin into the chip on the falling edge. the frequency varies from 128k to 2048 khz. dr 25 i this pin is the receive input data controlled by the fsr and bclkr pins. 4.4. serial setup port(ssp) interface pin name pin no. i/o function ssp en 14 i this pin is the enable signal for ssp setup. this pin is held low to select the16 control and status registers. there are two timing controls. one is for double 8 bit transfer mode; the other control is for the single 16 bit transfer mode. see the timing diagram, figure 7-6 to 7-9, in section 7.4.
p reliminary w9321 - 6 - 4.4 serial setup port(ssp) interface, continued pin name pin no. i/o function ssp clk 15 i this pin is the clock for ssp setup. note that data is shifted out of the ssp on the falling edge of this pin, and shifted into the ssp on the rising edge. the ssp clk can be any frequency from 0 to 2048 khz. ssp tx 16 o this pin is the tri-state output data for ssp transmission controlled by the ssp clk pin (pin-15). ssp rx 17 i this pin is the receive input data for the ssp controlled by the ssp clk pin (pin-15). 5. system diagram 5.1 pair gain system applications for this device include the public switching telephone system. one such application is the pair gain system shown in figure 5-1. the figure illustrates how the chip is used in a pair gain system to connect the telephone system between end users and the central office terminal these chips are used on devices installed in both the central office terminal (cot) and in the remote office terminal (rot). if the chip is operating in 32 kbps adpcm mode, the cot and rot must use four chips for 4-channel communication because the u interface chip can support 2b channel, i.e., 128k bps. in the transmission path, the telephone system first sends the analog signal to the adpcm chip in the rot to compress it into a 32 kbps digital signal. the u interface can then build a 2b+d channel, 128 kbps, with four adpcm chip channels, and send the 128 kbps digital signal to the cot. after receiving the digital signal, the u interface in the cot separates the 128 kbps data into four adpcm channels (32 kbps) and sends this data to the chip to execute the adpcm decoder and for reconstruction into an analog signal. the analog signal is then sent to the central office (co) to complete the transmission operation. for the receive path it is the reverse operation of the transmission path mentioned above. in a pair gain system, the analog signal (voice signal, or modem signal) is digitized and compressed to a adpcm signal e.g. 32 kbps adpcm. the subscriber loop, the connection between the end user and the central office, is digitized by the u interface transceiver. this provides two b-channels (2 64 kbps) for data and one d channel for signaling. in short, data can be transmitted and received on the subscriber loop via the u interface transceiver. one b-channel can carry 64 kbps data, i.e. two 32 kbps adpcm channels. therefore the pair gain system can supply four telephones .
p reliminary w9321 publication release date: may 1999 - 7 - revision a1 s interfac e layer 2 u interface 2b+d remote office terminal (rot) u interface 2b+d s interface layer 2 adpcm sd codec central office terminal (cot) channel 1 channel 2 channel 3 channel 4 centeral office (co) analog analog analog analog analog analog analog analog end user telephone system micro-controller micro-controller adpcm sd codec adpcm sd codec adpcm sd codec adpcm sd codec adpcm sd codec adpcm sd codec adpcm sd codec figure 5-1 system diagram for pair gain application 5.2. cordless phone system figure 5-2 shows a cordless phone system block diagram. on the transmission side, the voice is sent to the w9321 adpcm codec from the external microphone. first, the analog speech signal is digitized into a 14-bit linear signal and compressed into 32 kbps adpcm data. the compressed signal is then sent to the w9330f sst which provides all the baseband functions required for an fcc part 15 compliant cordless phone. the sst w9330 will generate the spread spectrum binary sequence for output to an rf modulator. the microprocessor manages the other functions of the cordless phone such as the keypad and display control. on the receive side, the wht9362 rf module converts the received signal to baseband. the w9330 sst then performs the de-correlation and demoulation and sends the 32k bps speech signal into the w9321 adpcm. the w9321 then reconstructs the digital speech signal into an analog signal using the 32k adpcm decoder before sending this analog signal to the speaker. adpcm voice codec w9321 spread spectrum transceiver sst w9330f microprocessor w921e880f microphon e speaker rf module wht9362 antenna figure 5-2 system diagram for cordless phone application
p reliminary w9321 - 8 - 6. block diagram vext vdd c1- vdsp axo+ axo- analog smoothing filter analog lpf digital s d demodulator digital anti-alias intp. filter + -- ro + -- po+ - + po- + - pi vref -- + ti- ti+ tg tx gain control analog sd modulator digital anti-aliasing dec. filter digital hpf charge-pump & 5 volt regulator for analog processing 3 volt regulator for digital signal processor c1+ 2.5v reference voltage vag power supply management system sd codec-filter serial data port (sdp) adpcm decoder adpcm encoder noiseburst detection universal tone generator rx atten. control sidetone gain digital rx gain mu/a law expander or linear mu/a law compressor dsp engine dr fsr bclkr fst bclkt dt serial setup port & 16 * 8 bits setup and status registers sequence and control ssp en ssp clk ssp tx ssp rx mclk pdi/reset + figure 6-1 winbond adpcm sd codec block diagram 7. functional descriptions figure 6-1 illustrates the functional blocks of the winbond adpcm sd codec. the chip can be divided into four subsystems which are described in the following subsections. 7.1. power supply management system in this block two groups comprise the power supply management system. one group is a 5-volt power supply system for all analog signal processing. the second group is a 3-volt power supply system for all digital signal processing. 7.1.1. power supply for all analog signals processing all analog circuits except for output power amplifiers axo and po are supplied with 5-volt power. this voltage may be applied directly to the v dd pin or by the 5 volt charge pump circuit. note that the power drivers axo and po are powered by the v ext pin which is the main positive power supply pin. when v ext = +5v 5% (e.g. base station applications) v dd is an input pin and should be connected externally to the v ext pin. the charge pump capacitor c1+ and c1- should not be used and the br0[b2] must be set as a logic "1" to disable the charge pump circuit. in this case vext and v dd can share the same 0.1 uf decoupling capacitor to v ss . when v ext = 2.7 to 5.25 volts (e.g. battery applications) v dd is a 5 volt charge pump circuit output and should not be connected to v ext . v dd should be decoupled to vss with a 0.1 m f capacitor. this pin cannot be used for powering external loads.
p reliminary w9321 publication release date: may 1999 - 9 - revision a1 7.1.2. power supply for all digital signals processing all digital circuits are supplied by the v dsp pin from a 3-volt regulator circuit. this reduces the chip power consumption. whatever the value on the power supply pin v ext , range from 2.7 to 5 volts, the digital circuits will always be powered by a 3 volt voltage supply. note that the v dsp pin should be decoupled to vss with a 0.1 m f capacitor and that this pin cannot be used for powering external loads. 7.1.3. reference voltage control system all analog reference voltages such as power amplifier ro, axo, po is 2.5 volt or v ext /2 determined by br2(b7). 7.2. sd codec-filter this device has a built in linear 14-bit pcm codec-filter using sd technology. there are two paths in the block, a transmit path and a receive path. 7.2.1. transmit path in sd codec-filter an analog signal input, from a microphone interface, is passed to three terminal operational amplifiers (ti+, ti-, tg) driving a typical 2 k w load externally to amplify the input analog signal. the analog signal can then be set to have further transmission gain from 0 to +7 db, in 1 db steps by the transmit gain control block. the gain is programmed through the ssp port in br1(b2:b0). the sd modulator block oversamples the analog signal at 1.024 mhz with one bit resolution. the next anti- aliasing decimation filter reduces the sampling frequency from 1.024 mhz (1 bit) to 32 khz (15 bit). digital biquad filters perform the decimation from 32k to 8 khz and ccitt low-pass filtering at 3400 hz. the digital hpf block performs the high-pass filtering at 300 hz. in the final step, the 14 bit a/d conversed data is sent by the transmit path to the dsp engine for further signal processing (e.g. by the adpcm encoder). 7.2.2. receive path in sd codec-filter a 14-bit linear digital signal from the rx attenuation control block in the dsp engine is first passed to the digital anti-aliasing interpolation filter block. the interpolation block performs the reverse operation of the decimation filter (described above in the transmit path) and the sampling rate will be increased from 8 khz (14 bits) to 1.024 mhz (14 bits). the digital sd demodulator will then reduce the 14-bit samples (1.024 mhz) to 1 bit (1.024 mhz). the digital output signal will be passed to a 3400 hz switched capacitor low-pass filter with sin(x)/x correction and an analog smoothing filter to reduce the spectral components of the switched capacitor filter. finally, the analog output signal is sent to the power amplifier, ro, which is capable of driving a 2 k w load connected to to the vag pin, and high current analog output driver axo simultaneously with a 300 w differential load. note the device provides another power amplifier, po, connected in a push-pull configuration. the axo and po have different circuit configurations for different applications. the axo is for handset ringer applications, but the po driver can accommodate large gain ranges by adjusting two external resistors for applications such as driving a telephone line or a handset receiver. 7.3. dsp engine this block is the kernel of the adpcm transcoder and tone generator. there are two paths in this block, a transmit path and a receive path.
p reliminary w9321 - 10 - 7.3.1. transmit path in the dsp engine a linear 14 bit sample input from the transmit path of the sd codec-filter block is sent in three processing directions: sidetone gain process, mu/a law compressor/linear, and adpcm encoder/ tone encoder. in the sidetone gain block, the input sample is fedback to the receive path and is summed with the output of the digital receive gain. the value is kept in the -70 db to -8.5 db range by the ssp port in br1(b6:b4).the a/d output is then saved linearly into br9(b7:b0) & br10(b7:b2). the adpcm encoder/tone encoder provides 16 kbps, 24 kbps, or 32 kbps adpcm, or 64 kbps pcm respectively, as determined by the length of the transmit frame sync (pin 18). the length of the frame sync is calculated by the number of falling edges at the bclkt pin when the transmit frame sync fst pin is high. because the frame sync clock is 8 khz, the encode interrupt is performed once every 125 m s. as a default value the transmit adpcm will be delayed by two frames after being requested, i.e. if the current frame request is for adpcm operation, it will be computed in the next frame and the adpcm result is transmitted in the next two frames. for applications such as the signaling channel of t1 frame structure the delay status can be configured to a total of 6 frames by the ssp port in br7(b5). the adpcm output result will be sent to the serial data port (sdp) on the dt pin and the output data rate from 128 khz to 2048 khz will be controlled by the serial data port on the bclkt pin. in the universal tone generator mode, the input of the adpcm encoder comes from the output of the universal tone generator, not from the transmit path in the sd codec-filter. the adpcm encoder outputs the tone adpcm signal through pin dt. 7.3.2. receive path in dsp engine the device receives data from the dr pin via the serial data port (sdp) under the control of the bclkr and fsr pins. the clock of the receive frame sync fsr is 8 khz. the adpcm decoder receives one decode interrupt every 125 m s . the serial data rate in the bclkr is in the 128 khz to 2048 khz range. the input parameter data is sent to the adpcm decoder which also provides 16 kbps, 24 kbps, or 32 kbps adpcm or 64 kbps pcm, is determined by the length of the receive frame sync fsr pin. the length of the frame sync is calculated by the number of falling edges at the bclkr pin when the receive frame sync fsr pin is high. the adpcm decoder consists of a sync adjustment operation for the correction of sync. tandem application, except when the receive digital gain is used for a handset application. the digital receive gain is programmed from -12 db to +12 db through the ssp port in br3(b6:b0). in order to prevent noise from influencing the result of the adpcm decoder, the noise burst detection algorithm can be enabled by setting the br7(b6) register to detect interfering sounds and to mute the receive path. the reconstructed linear pcm will be compressed by the mu/a law compressor block and sent to br11 (b7:b0) on the ssp port after sync. adjustment in g.726 for ccitt test mode. after the control of digital receive gain, the synthesized pcm data will be added to the feedback signal of the transmit path in the sidetone gain block. the sum value is then passed to the rx attenuation control block to protect the output driver, ro, from distortion when the amplitude of the synthesis data is too large (e.g. battery applications). the gain of the rx. attenuation block is programmed through the br2 (b2:b0) register in the ssp port. a receive attenuation range of from 0 to -7 db can be programmed in 1 db steps. if the device enables the universal tone generator, the function of the adpcm decoder will be disabled. different tone types (i.e. tone 1 and tone 2) can be programmed through the br7, br4, and br5 registers in the ssp port. the tone generator can be used to generate dtmf tones, different ringing tones, and call progress tones for handset applications. in telephone line applications, this tone generator can be used for signaling on the line.
p reliminary w9321 publication release date: may 1999 - 11 - revision a1 7.3.3. frame sync. types the frame sync operation uses two industrial control types for the transfer of the adpcm or pcm data words. these two types are the long frame sync and short frame sync. 7.3.3.1. long frame sync the long frame sync types for various data rates are shown in figure 7-1 to 7-4. the bit rate for the adpcm or pcm encoder and decoder is determined by the length of the frame sync pin (fst or fsr). the length of the frame sync is calculated by the number of falling edges at the bclkt or bclkr pin when the frame sync fst or fsr pin is high. for example, if the number of the falling edges on the bclkt or bclkr pin is equal to 2 when the frame sync is high, this corresponds to the 16 kbps bit rate for the encoder and decoder of the adpcm operation. if the number is 8, the device becomes 64 kbps pcm operation. the device shifts out the data on the dt pin at the bclkt rising edge and shifts in the data on the dr pin at the bclkr falling edge. the length of the frame sync may be changed on a frame by frame basis. 7.3.3.2. short frame sync the short frame sync types for 32 kbps adpcm timing is shown in figure 7-5. the bit rate for this type of frame performs only 32 kbps adpcm encoding and decoding. the length of the frame sync is equal to 1. the device shifts out data on the dt pin at the bclkt rising edge and shifts in data on the dr pin at the bclkr falling edge. switching between long frame sync and short frame sync without going through a power down operation is not recommended. d0 d1 d0 bclkt (bclkr) fst (fsr) 1 2 3 4 5 6 7 8 dt dr don't care don't care lsb msb lsb d1 msb figure 7-1 long frame sync for 16 kbps adpcm timing d1 d1 bclkt (bclkr) fst (fsr) 1 2 3 4 5 6 7 8 dt dr d2 don't care d0 d2 msb lsb msb lsb don't care d0 figure 7-2 long frame sync for 24 kbps adpcm timing
p reliminary w9321 - 12 - d3 d2 bclkt (bclkr) fst (fsr) 1 2 3 4 5 6 7 8 dt dr don't care don't care d1 d0 d3 d2 d1 d0 msb lsb msb lsb figure 7-3 long frame sync for 32 kbps adpcm timing d7 d7 d6 bclkt (bclkr) fst (fsr) 1 2 3 4 5 6 7 8 dt dr don't care don't care d5 d4 d3 d2 d1 d0 d6 d5 d4 d3 d2 d1 d0 msb lsb msb lsb figure 7-4 long frame sync for 64 kbps adpcm timing bclkt (bclkr) fst (fsr) 1 2 3 4 5 6 7 dt dr don't care don't care d3 d2 d1 d0 d3 d2 d1 d0 8 msb lsb msb lsb figure 7-5 short frame sync for 32 kbps adpcm timing 7.4. serial setup port (ssp) the w9321 has sixteen 8-bit wide setup and status registers, br0--br15, for controlling and monitoring functions via the serial setup port (ssp). the ssp may be used by an external microcontroller such as the winbond w921e880f. the ssp has a full-duplex four wire interface (marked as ssp tx, ssp rx, ssp clk, and ssp en) for communicating with an external micro-
p reliminary w9321 publication release date: may 1999 - 13 - revision a1 controller. two timing controls, a double 8-bit transfer mode and a single 16-bit transfer mode, are available when ssp en is held low to select the setup registers. the data rate for the ssp clk ranges from 0 to 2048 khz. the data is shifted out of the ssp port on the falling edge of ssp clk, and shifted into the ssp port on the rising edge of the ssp clk. this latch operation is the reverse of the serial data port in the dsp engine. the 16 byte registers are selected by bits 3 to 0 in the first byte from the ssp rx pin as shown in figure 7-6 to 7-9. bit 7 of the first byte indicates whether the status is read (logic 1) or write (logic 0). the second byte is the data word (d7:d0). the description of setup and status registers, br0--br15 is described in greater detail in the next section 8. (control and status registers). ssp en ssp clk ssp tx ssp rx 1 2 3 4 5 6 7 8 a3 a2 a1 a0 1 2 3 4 5 6 7 8 d7 d6 d5 d4 d3 d2 d1 d0 high impedence don't care don't care don't care w figure 7-6 double 8 bit for write operation of ssp register d7 d6 d5 d4 d3 d2 d1 d0 ssp en ssp clk ssp tx ssp rx 1 2 3 4 5 6 7 8 a3 a2 a1 a0 1 2 3 4 5 6 7 8 don't care don't care r figure 7-7 double 8 bit for read operation of ssp register ssp en ssp clk ssp tx ssp rx 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 high impedence a3 a2 a1 a0 don't care d7 d6 d5 d4 d3 d2 d1 d0 don't care w figure 7-8 single 16 bit for write operation of ssp register
p reliminary w9321 - 14 - ssp rx d7 d6 d5 d4 d3 d2 d1 d0 ssp en ssp clk ssp tx 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 don't care a3 a2 a1 a0 don't care r figure 7-9 single 16 bit for read operation of ssp register 7.5. sequence and control this block generates some internal clocks, providing clocks such as 1.024 mhz and 8 khz for sd codec-filter operation. the master clock mclk, which supports the clock of the dsp engine, may be asynchronous to all other blocks. its frequency is typically 10.24 mhz for cordless applications using winbond chips. the sd codec-filter may use the bclkr pin as a direct 1.024 mhz input. the rising edge of this input clock must be approximately aligned with the rising edge of the fst. this mode requires that the adpcm transmit and receive be controlled by the bclkt pin. this is configured by the ssp port through the br0(b7) register. there are two ways of forcing the device into a low power consumption condition in power down mode. one way is the hardware power down mode where the pdi/reset pin is held to logic 0. the other way is the software power down mode where the register br0(b1:b0) is set through the ssp. when the br0(b1) setting initiates an analog power down, all clocks for analog signal processing will be halted. to initiate a digital power down, the br0(b0) register can be programmed to logic 1 to halt all clocks for all digital signal processing. when the chip is powered down, the vag, tg, ro, po, axo, dt and ssp tx outputs are all high impedance. when the power is reactivated from the power down mode, the adpcm algorithm is reset to the ccitt initiate state. 7.6. i/o level digital i/o for the device can be programmed in either mu-law or a-law. full scale and zero words for these two log-pcm forms are shown in table 7-1. for analog signal processing, the maximum transmit level is 3.17 dbm0 for mu-law or 3.14 dbm0 for a-law. these values meet the ccitt g.711specifications. mu-law a-law level sign segment bits step bits sign segment bits step bits + max. scale 1 000 0000 1 010 1010 +zero 1 111 1111 1 101 0101 - zero 0 111 1111 0 101 0101 - max. scale 0 000 0000 0 010 1010 table 7-1 full scale and zero word for mu/a-law
p reliminary w9321 publication release date: may 1999 - 15 - revision a1 8. control and status registers 8.1. introduction there are 16 available byte setup and status registers for the ssp port. the functional description and read/write status of each bit are illustrated in the sections that follow. the read or write status described in table 8-1 is indicated by the symbol r, w, ro. symbol type meaning r/w read/write data may be read from the ssp port or written into the ssp port by micro-processor ro read only data may only be read from the ssp port. writing to this port has no effect. ro/wo read only/write only data may be read or written by an external micro-processor and internal chip simultaneously. the value is written into the bit and read back by the external micro-controller table 8-1 read/write status description in ssp byte register 8.2. byte register description there are 16 byte registers for controlling and monitoring the status of the chip. these registers are labeled br0 to br15. the descriptions are as follows. note that "setting" is corresponding to logic "1 ? and "clearing" is corresponding to logic "0". ?. 8.2.1. byte register 0 (br0) this is a control register. all bits are cleared when the pdi/reset pin is set to logic zero. b7 b6 b5 b4 b3 b2 b1 b0 br0 ext 1024 khz clock r/w mu/a law select r/w analog loopback r/w function mode select[1] r/w function mode select[0] r/w charge pump disable r/w analog power down r/w digital power down r/w external 1024 khz clock (b7): this bit controls a mux. when this bit is cleared, the mux selects the 1024 khz clock from the internal clock generator. when this bit is set, the bclkr pin is used to provide an external 1024 khz clock and the internal bclkr is connected to bclkt; the br0[b1] must be set to "1" for reset codec. mu/a law (b6): when this bit is set to logic zero, the device selects mu-law companding of the log-pcm. setting this bit selects the a-law companding of the log-pcm. analog loopback (b5): setting this bit causes an analog loopback from the receive path to the transmit path. internally the ro output in the receive path is routed to the transmit gain control in the transmit path; the op-amp tg is bypassed.
p reliminary w9321 - 16 - mode select[1:0] (b4:b3): the function modes are shown in table 8-2. the adpcm codec mode performs a combination of pcm codec and adpcm transcoder in full duplex. the pcm codec mode is a subset of the adpcm codec mode, where only the pcm codec is executed. the ccitt test mode uses the ccitt adpcm test vectors to do conformance testing. enabling this mode will remove the sd codec-filter operation. the test vectors go through the ssp port in br9[b7:b0] and br10[b7:b0]. see the br9 and br10 descriptions for more details. the battery test mode allows testing of the voltage present at the v ext pin. in this mode, the hpf output in register br8[b4] must be disabled. note that the steady linear code for the v ext pin will be delayed by about 60 samples. the output result of linear 14 bits is stored in registers br9 and br10. function mode select[1:0] (b4:b3) type 00 adpcm codec 01 pcm codec 10 ccitt test 11 battery test table 8-2 function mode selection charge pump disable (b2): setting this bit disables the 5 volt charge pump. in this mode, the charge pump capacitor c1+ and c1- should not be used and the v dd pin should be connected externally to the v ext pin. analog power down (b1): setting this bit causes an analog power down. in this mode, all clocks for analog processing (e.g. the sd codec) will be halted to reduce power consumption. the analog circuit will not operate normally until this bit is cleared. digital power down (b0): setting this bit causes a digital power down. in this mode, all clocks for digital processing (e.g. the dsp engine) will be halted to reduce power consumption. the digital circuit and the adpcm initialization will not operate until this bit is cleared. 8.2.2. byte register 1 (br1) this register controls the sidetone gain value and transmit gain. this register can also mute the transmit signal. all bits are cleared when the pdi/reset pin is set to logic zero. b7 b6 b5 b4 b3 b2 b1 b0 br1 reserved sidetone gain[2] r/w sidetone gain[1] r/w sidetone gain[0] r/w transmit mute r/w transmit gain[2] r/w transmit gain[1] r/w transmit gain[0] r/w reserved (b7): this bit is reserved.
p reliminary w9321 publication release date: may 1999 - 17 - revision a1 sidetone[2:0] (b6:b4): these three bits control the sidetone attenuation. the sidetone attenuation can range from - ?? to -8.5 db as shown in table 8-3. transmit mute (b3): setting this bit will mute the transmit path in the sd codec-filter block. a send zero is sent to the dsp engine for further processing. transmit gain (b2:b0): these three bits control the transmit gain control as shown in table 8-4. the gain range can be set in the 0 to 6.8 db range in +1 db steps. sidetone[2] (b6) sidetone[1] (b5) sidetone[0] (b4) sidetone atten. (db) 0 0 0 - ?? 0 0 1 -21.5 0 1 0 -18.0 0 1 1 -15.0 1 0 0 -13.5 1 0 1 -11.5 1 1 0 -10.5 1 1 1 -8.0 table 8-3 sidetone attenuation transmit gain[2] (b2) transmit gain[1] (b1) transmit gain[0] (b0) transmit gain control(db) 0 0 0 0 0 0 1 +1.5 0 1 0 +2 0 1 1 +3 1 0 0 +4 1 0 1 +5 1 1 0 +6 1 1 1 +6.8 table 8-4 transmit gain control
p reliminary w9321 - 18 - 8.2.3. byte register 2 (br2) this register controls the operations of the receive path in the sd code-filter block. all bits are cleared when the pdi/reset pin is set to logic zero. b7 b6 b5 b4 b3 b2 b1 b0 br2 reference point select r/w axo enable r/w po disable r/w reserved ro mute r/w receive atten.[2] r/w receive atten.[1] r/w receive atten.[0] r/w reference point select (b7): this bit determines the reference voltage for power amplifiers such as ro, axo, and po. the output of the vag pin is the reference voltage. setting this bit sets the reference voltage to 2.5 volts. when this bit is cleared, the reference voltage is the default value of vext/2. axo enable (b6): this bit determines the status of the power amplifier axo. setting the bit will enable the operation of the axo amplifier. when this bit is cleared, the amplifier axo will be disabled by default. in power down mode, the output pins of axo are high impedance. po disable (b5): this bit determines the status of power amplifier po. setting the bit will disable the operation of po amplifier. when this bit is cleared, the amplifier po is enabled by default. in the power down mode, the output pins of po are high impedance. reserved (b4): this bit is reserved. ro mute (b3): setting this bit will force the input of the ro amplifier to ground. the ro remains offset in order to avoid audible " pops" when turning the block on and off. receive attenuation[2:0] (b2:b0): these three bits control the receive attenuation as shown in table 8-5. the attenuation range can be set from 0 to -7 db in -1 db steps. receive atten.[2] (b2) receive atten.[1] b1) receive atten.[0] (b0) receive attenuation (db) 0 0 0 0 0 0 1 -1 0 1 0 -2 0 1 1 -3
p reliminary w9321 publication release date: may 1999 - 19 - revision a1 continued receive atten.[2] (b2) receive atten.[1] b1) receive atten.[0] (b0) receive attenuation (db) 1 0 0 -4 1 0 1 -5 1 1 0 -6 1 1 1 -7 table 8-5 receive attenuation control 8.2.4. byte register 3 (br3) b7 b6 b5 b4 b3 b2 b1 b0 br3 digital rx gain enable r/w dig. rx gain[6] r/w dig. rx gain[5] r/w dig. rx gain[4] r/w dig. rx gain[3] r/w dig. rx gain[2] r/w dig. rx gain[1] r/w dig. rx gain[0] r/w this register contains information on the digital receive gain. all bits are cleared when the pdi/reset pin is set to logic zero. digital rx gain enable (b7): setting this bit will enable the digital receive gain routine in the dsp engine. the receive gain can be programmed by setting the gain factors defined in this register br3[b6:b0]. when this bit is cleared, the digital receive gain routine is disabled. digital rx gain[6:0](b6:b0): these seven bits show the value of the digital receive gain factor. the gain value is calculated as follows: 2 * b6 + b5+ 1/2 *b4 + 1/4 * b3 + 1/8 *b2 +1/16 *b1 +1/32 * b0 the first two bits (b6:b5) are integers and the last five bits are fractions. the decimal point is placed after bit 5. the gain range can be up to +12 db. 8.2.5. byte register 4 (br4) b7 b6 b5 b4 b3 b2 b1 b0 br4 tonepar[7] r/w tonepar[6] r/w tonepar[5] r/w tonepar[4] r/w tonepar[3] r/w tonepar[2] r/w tonepar[1] r/w tonepar[0] r/w this register holds the parameters for the tone generator. all bits are cleared when the pdi/reset pin is set to logic zero. tone generator parameters[7:0](b7:b0): these seven bits contain the eight lsb frequencies or tone generator attenuation coefficients. the tone generator is enabled when the br7[b3] register is set to 1. the four msb tone parameters are placed in br5[b3:b0]. switching between the frequency and attenuation factor is determined by the br5[b7:b6] register.
p reliminary w9321 - 20 - 8.2.6. byte register 5 (br5) this register holds the parameters for noise burst detection and the tone generator. the noise burst detection and tone generator modes are enabled through the br7(b3) register . all bits are cleared when the pdi/reset pin is set to logic zero . b7 b6 b5 b4 b3 b2 b1 b0 br5 nb thd[7]/ toneaddr[1] r/w nb thd[6]/ toneaddr[0] r/w nb thd[5]/ don't care r/w nb thd[4]/ don't care r/w nb thd[3]/ tonepar[11] r/w nb thd[2]/ tonepar[10] r/w nb thd[1]/ tonepar[9] r/w nbthd[0]/ tonepar[8] r/w noise burst detect threshold[7:0] (b7:b0): when the device is in the noise burst detection mode (i.e. br7[b3] = 0 and br7[b6] = 1) these eight bits contain the threshold for noise burst detection. the detected algorithm use the frequency value to decide whether the noise is present or not. we suggest a threshold value greater than 80 (to be written in decimal format, i.e. 4 khz above). tone generator address[1:0](b7:b6): when the tone generator is enabled, (i.e. br7[b3] = 1), these two bits can be programmed to select the frequency or attenuation factor as shown in table 8-6. tone generator parameters[11:8](b3:b0): these four bits contain the four msb frequencies or tone generator attenuation coefficients. the tone generator is enabled when the br7 (b3) register is set to 1. the last eight lsbs are placed in the br4[b7:b0] register. switching between the frequency and attenuation factor is determined by bit 7 and bit 6. tone address[1] (b7) tone address[0] (b6) tone parameter selection 0 0 frequency of tone 1 0 1 attenuation of tone 1 1 0 frequency of tone 2 1 1 attenuation of tone 2 table 8-6 tone generator address parameters 8.2.7 byte register 6 (br6) b7 b6 b5 b4 b3 b2 b1 b0 br6 reserved reserved reserved reserved reserved reserved reserved reserved this register is reserved. the user should not read or write to this register. 8.2.8. byte register 7 (br7) this register is used to enable noise burst detection and the tone generator. additional options include 2/6 frame delay and writing ready status for the br4 and br5 registers. all bits are cleared when the pdi/reset pin is set to logic zero.
p reliminary w9321 publication release date: may 1999 - 21 - revision a1 b7 b6 b5 b4 b3 b2 b1 b0 br7 ready for br4 & br5 ro nb detect enable ro/wo 2/6 delay r/w don't care tone gen. enable r/w reserved tone1 enable r/w tone 2 enable r/w ready for writing br4 and br5 (b7): this read-only bit indicates whether parameters have been written into the br4 and br5 register. this bit is set after writing to br5. this bit is cleared when the internal dsp engine reads from the br4 and br5 registers. noise burst detect enable (b6): this is a read-only/write-only bit. setting this bit and bit 3 to 0 enables the noise burst detection routine. if noise is detected, this bit is cleared and can be polled by an external micro-controller. this mutes the receive path. 2/6 delay (b5): this bit controls the frame delay status. setting this bit inserts a 6-frame delay between frame control changes. clearing this bit inserts a 2-frame delay between frame control changes. don't care (b4): no effect whenever the bit is read or written to by an external micro-controller. tone generator enable (b3): setting this bit performs the tone generator routine instead of the adpcm decoder. in addition, the noise burst detection will be disabled. the result of the tone generator will be passed to the adpcm encoder to compress the tone and transmit the encoded result to the dt pin. reserved (b2): this bit is reserved. tone 1 enable (b1): setting this bit enables the tone 1 routine for the tone generator. when this bit is cleared, the tone1 routine is disabled. tone 2 enable (b0): setting this bit enables the tone 2 routine for the tone generator. when this bit is cleared, the tone 2 routine is disabled. if dtmf is enabled, the user must set tone 1 and tone 2 to enable. 8.2.9. byte register 8 (br8) this register contains miscellaneous control bits. all bits are cleared when the pdi/reset pin is set to logic zero.
p reliminary w9321 - 22 - b7 b6 b5 b4 b3 b2 b1 b0 br8 s/w encoder reset r/w s/w decoder reset r/w linear codec mode r/w hpf disable r/w reserved reserved reserved reserved software encoder reset (b7): setting this bit forces the device to execute the adpcm encoder initialization every time the encoder receives an interrupt. software decoder reset (b6): setting this bit forces the device to execute the adpcm decoder initialization every time the decoder receives an interrupt. linear codec mode (b5): setting this bit forces the device to perform as an 8 bit linear codec. the 6 lsb linear a/d converted output from the sd codec-filter will be truncated in this mode. hpf disable (b4): setting this bit will disable the high pass filter (hpf) in the transmit path for applications such as battery test mode in br0[b4:b3] = "11" ?. reserved (b3:b0): these bits are reserved and should not be used by the user. caution: reserved bits (b3:b0) must be set to zero at all times for normal operation. 8.2.10. byte register 9 (br9) b7 b6 b5 b4 b3 b2 b1 b0 br9 tx log pcm[7]/ linear pcm[13] ro/wo tx log pcm[6]/ linear pcm[12] ro/wo tx log pcm[5]/ linear pcm[11] ro/wo tx log pcm[4]/ linear pcm[10] ro/wo tx log pcm[3]/ linear pcm[9] ro/wo tx log pcm[2]/ linear pcm[8] ro/wo tx log pcm[1]/ linear pcm[7] ro/wo tx log pcm[0]/ linear pcm[6] ro/wo this register contains the pcm value of the transmit path. if the pcm value comes from the transmit path of the sd codec-filter, then br9 may be internally written into the most siginificant bits of the 14 bit linear pcm (b13:b6). if the device is for applications such as ccitt test mode i.e. br0[b4:b3] = "10" then br9 may read the companding log-pcm from an external micro-controller to be used for the adpcm encoder. in the 14 bit linear mode, the 8 msb are stored into this register and the left 6 lsb will be placed in br10[b7:b2]. see the description of br10 for more details. note that this register is read-only/write-only.
p reliminary w9321 publication release date: may 1999 - 23 - revision a1 8.2.11. byte register 10 (br10) b7 b6 b5 b4 b3 b2 b1 b0 br10 encoder linear pcm[5] ro encoder linear pcm[4] ro encoder linear pcm[3] ro encoder linear pcm[2] ro encoder linear pcm[1] ro encoder linear pcm[0] ro reserved reserved this register contains the 6 lsb of the linear pcm value for the transmit path. the pcm value must come from the transmit path of the sd codec-filter and not from an external micro-controller. the left 8 msb are stored into br9[b7:b0]. see the description of br9 for more details. note that this register is read-only. 8.2.12. byte register 11 (br11) b7 b6 b5 b4 b3 b2 b1 b0 br11 rx log- pcm[7]/ dac pcm[13] ro rx log- pcm[6]/ dac pcm[12] ro rx log- pcm[5]/ dac pcm[11] ro rx log- pcm[4]/ dac pcm[10] ro rx log- pcm[3]/ dac pcm[9] ro rx log- pcm[2]/ dac pcm[8] ro rx log- pcm[1]/ dac pcm[7] ro rx log- pcm[0]/ dac pcm[6] ro this register contains the pcm value of the receive path. the pcm value comes from the companding log-pcm generated by the sync adjustment block of the decoder in ccitt test mode, i.e. br0 (b4:b3) is set to logic "10". note that, this register is read-only. the combined br11 (b7:b0) and br12 (b7:b2) value is the same as sending the d/a converter . 8.2.13. byte register 12 (br12) b7 b6 b5 b4 b3 b2 b1 b0 br12 dac pcm[5] ro dac pcm[4] ro dac pcm[3] ro dac pcm[2] ro dac pcm[1] ro dac pcm[0] ro reserved reserved this register contains the 6 lsb of the linear pcm value for the d/a converter. the pcm value cannot be entered by an external microcontroller. the left 8 msb are stored into br11[b7:b0]. see the description of br11 for more details. note that this register is read-only. 8.2.14. byte register 13 (br13) b7 b6 b5 b4 b3 b2 b1 b0 br13 reserved reserved reserved reserved reserved reserved reserved reserved this register is reserved and should not be used by the user.
p reliminary w9321 - 24 - 8.2.15. byte register 14 (br14) b7 b6 b5 b4 b3 b2 b1 b0 br14 reserved reserved reserved reserved reserved reserved reserved reserved this register is reserved and should not be used by the user. 8.2.16. byte register 15 (br15) this register shows the version number of this device. b7 b6 b5 b4 b3 b2 b1 b0 br15 reserved reserved reserved reserved vers.[3] ro vers.[2] ro vers.[1] ro vers.[0] ro version[3:0] (b3:b0): these four bits determine the manufacturing version number of this chip. 9. electrical characteristics 9.1. absolute maximum ratings (voltage referenced to v ss pin) parameter symbol rating unit power supply voltage v ext , v dd -0.3 to 6 v analog input/output voltage --- -0.3 to v dd + 0.3 v digital input/output voltage --- -0.3 to v ext + 0.3 v operating temperature t op -25 to +85 j storage temperature t stg -85 to +85 j note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. 9.2. dc characteristics (v ss = 0 volt t op = -25 to +85 c) parameter sym. condition min. typ. max. unit operating voltage v ext ----- 2.7 3.0 5.25 v operating current i ext mclk = 10.24 mhz, charge pump "n" no load --- --- 20 ma power down current i pwdn mclk off --- --- 0.5 ma input high voltage v ih all digital input pins v ext -0.5 --- ----- v input low voltage v il all digital input pins 0 ---- 0.5 v
p reliminary w9321 publication release date: may 1999 - 25 - revision a1 9.2. dc characteristics, continued parameter sym. condition min. typ. max. unit output high voltage v oh dt, ssp tx v ext -0.5 ---- ----- v output low voltage v ol dt, ssp tx 0 --- 0.4 v input high current i il v ss vin v ext -10 --- +10 ua input low current i ih v ss vin v ext -10 --- +10 ua input capacitance c in all digital input pins to v ss --- --- 10 pf 9.3. analog transmission characteristics (v dd = +5v 5%, v ss = 0 volt , top = -25 to +85 c; all analog signal referenced to vag; 64 kbps pcm; fst = fsr = 8 khz; bclkt = bclkr = 2.048 mhz; mclk = 10.24 mhz ; unless otherwise noted) 9.3.1. amplitude response for analog transmission performance parameter sym. condition typ. transmit receive unit min. max. min. max. absolute level l abs 0 dbm0 = 0 dbm @ 600 w 0.776 --- --- --- --- vrms max. transmit level t xmax ------ 1.579 --- --- --- --- vpk frequency response, relative to 0 dbm0 @ 1020 hz g rtv 15 hz 50 hz 60 hz 200 hz 300 to 3000 hz 3300 hz 3400 hz 4000 hz 4600 to 100, 000 hz ---- ---- --- --- --- --- --- --- --- ---- --- --- -1.0 -0.20 -0.35 -0.8 --- --- -40 -30 -26 -04 +0.15 +0.15 0 -14 -32 -0.5 -0.5 -0.5 -0.5 -0.20 -0.35 -0.8 --- --- 0 0 0 0 +0.15 +0.15 0 -14 -30 db gain variation vs. level tone (1020 hz relative to -10 dbm0) g lt +3 to -40 dbm0 -40 to -50 dbm0 -50 to -55 dbm0 --- --- --- -0.3 -1.0 -1.6 +0.3 +1.0 +1.6 -0.2 -0.4 -0.8 +0.2 +0.4 +0.8 db 9.3.2. distortion characteristics for analog transmission performance parameter sym. condition typ. transmit receive unit min. max. min. max. absolute group delay d abs 1600 hz --- --- 440 --- --- m s
p reliminary w9321 - 26 - 9.3.2. distortion characteristics for analog transmission performance, continued parameter sym. condition typ. transmit receive unit min. max. min. max. group delay referenced to 1600 hz d rtv 500 to 600 hz 600 to 800 hz 800 to 1000 hz 1000 to 1600 hz 1600 to 2600 hz 2600 to 2800 hz 2800 to 3000 hz --- --- --- --- --- --- --- --- --- --- --- --- --- --- 210 130 70 35 70 95 145 --- --- --- --- --- --- --- --- --- --- --- --- --- --- m s total distortion vs. level tone (1020 hz, mu-law, c- message) d lt +3 dbm0 0 to -30 dbm0 -40 dbm0 -45 dbm0 --- --- --- --- 36 36 29 25 --- --- --- --- 34 36 30 25 --- --- --- --- dbc 9.3.3. noise characteristic for analog transmission performance parameter sym. condition typ. transmit receive unit min. max. min. max. idle channel with equipment noise n ide mu-law, c-message --- --- 19 --- +11 dbrn spurious out-of-band at spko (300 to 3400 hz @ 0 dbm0) n spo 4600 to 7600 hz 7600 to 8400 hz 8400 to 100,000 hz --- --- --- --- --- --- --- --- --- --- --- --- -30 -40 -30 db in-band spurious (1020 hz @ 0 dbm0) n ibs 300 to 3000 hz --- --- -48 --- -48 db crosstalk (1020 hz @ 0 dbm0) n ctk 300 to 3000 hz --- --- -70 --- -70 db 9.4. analog electrical characteristics (op amplifer tg, ro; power amplifer axo, po; v dd = +5v 5%, vss = 0v; top = -25 to +85 c) parameter sym. conditions min. typ. max. unit input offset voltage of tg v ofin ti+, ti- --- --- 25 mv input common mode voltage v cmv ti+, ti- 1.0 --- v dd -2.0 v load capacitance for ro c lro ro --- --- 100 pf load resistance to vag for tg, ro r ld tg, ro 2 --- --- k w vag output voltage v ag to v ss 2.4 2.5 2.6 v
p reliminary w9321 publication release date: may 1999 - 27 - revision a1 9.4. analog electrical characteristics, continued parameter sym. conditions min. typ. max. unit power supply rejection ratio (0 to 100 khz @ 100m vrms to v dd with c-message) psrrdd tg --- 40 --- dbc load capacitance for axo, po clap axo- to axo+; po- to po+ --- ---- 300 pf load resistance differentially for axo, po rldap axo- to axo+; po- to po+ 300 --- ---- w input offset voltage for pi vofpi ref to vag --- ---- 25 mv 9.5. digital switching characteristics 9.5.1. characteristic of serial data port for long frame and short frame (v ext = +2.7 to 5.25v ; vss = 0v; all digital circuits referenced to v ss ; top = -25 to +85 c, c l = 150 pf ) parameter sym. conditions min. typ. max. unit master clock frequency t mast mclk 10.232 10.240 10.247 mhz bit clock frequency t bclk bclkt, bclkr 128 --- 2048 khz frame sync. frequency t sync fst, fsr --- 8 - - khz clock duty cycle d c mclk, bclkt, bclkr 45 50 55 % rise time t ir all digital input pins --- --- 50 ns fall time t if all digital input pins --- --- 50 ns frame sync. pulse width t fsp fst, fsr 100 --- --- ns transmit sync. timing t xs t sx bclkt to fst fst to bclkt 20 80 --- --- --- --- ns receive sync. timing t rs t sr bclkr to fsr fsr to bclkr 20 80 --- --- --- --- ns setup time for dr valid t stdr - 20 --- --- ns hold time for dr valid t hddr - 50 --- --- ns output delay time for dt valid t dv bclkt to dt 10 --- 140 ns output delay time for dt high impedance t dhi bclkt to dt 10 --- 140 ns note: these parameters are shown in figure 9-1 and 9-2.
p reliminary w9321 - 28 - mclk tmast d1 d0 d1 d0 fst bclkt dt fsr bclkr dr tsync tsync 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 tir tif tfsp tfsp txs tsx trs tsr thddr tstdr tdv tdhi msb lsb msb lsb figure 9-1 long frame sync, timing d3 fst bclkt dr tsync tsync 1 2 3 4 5 6 7 1 2 3 4 5 6 7 tfsp tfsp txs tsx trs tsr thddr tstdr tdv tdhi d2 d1 8 8 d3 dt d2 d1 d0 fsr bclkr d0 msb lsb msb lsb figure 9-2 short frame sync, timing
p reliminary w9321 publication release date: may 1999 - 29 - revision a1 9.5.2. characteristic of serial setup port (ssp) 1 2 3 4 5 6 7 8 ssp en ssp clk b7 ssp tx r/wb7 b6 b5 b4 b3 b2 b1 b0 ssp rx tsspc tcen tenc trvb trva tdvc tdhc tcdi tdic b6 b5 b4 b3 b2 b1 b0 figure 9-3 serial setup port (ssp) timing (v ext = +2.7 to 5.25v ; vss = 0v; all digital circuit referenced to v ss ; t op = -25 to +85 c, c l = 150 pf) parameter sym. conditions min. typ. max. unit ssp clock frequency t sspc ssp clk --- -- 2.048 mhz clock duty cycle of ssp d ssp ssp clk 40 50 60 % ssp enable timing t enc t cen sspen to ssp clk ssp clk to ssp en 50 50 --- --- --- --- ns ssp rx valid timing t rvb t rva setup time hold time 50 50 --- --- --- --- ns output delay time for ssp tx valid t dvc ssp clk to ssp tx --- --- 140 ns output delay time for ssp tx high impedance t dhc ssp en rising to ssp tx --- --- 140 ns ssp disable timing t cdi t dic ssp clk to ssp en ssp en to ssp clk 50 50 --- --- --- --- ns note: the parameters are shown in figure 9-3.
p reliminary w9321 - 30 - 10. application information 10.1. handset application for wireless communication for wireless handset applications, v ext is supplied from a 2.7 to 5.25 volt battery power supply. meanwhile the v dd pin, connected with a 1.0 m f capacitor to ground, is a 5 volt output and should not be connected to v ext . the v dsp pin, connected with a 0.1 m f capacitor to ground, is a 3 volt output. the v dd and v dsp pins should not be used to supply any external systems. the chip must also enable the charge pump by clearing the br0[b2] of ssp port. the output power amplifier pins po- and po+ drive the receiver speaker. a ringer is driven by the differential power amplifier outputs axo- and axo+. the input to the transmitter amplifier is from a microphone output. the application circuit, figure 10-1 is as follows. tg ti- ti+ vag ro axo- axo+ vdsp vext pi po- po+ pdi/reset ssp en vdd fsr bclkr dr c1+ c1- vss mclk (scp) dt bclkt fst ssp rx ssp tx ssp clk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 battery power ringer speaker microphone receiver speaker battery power 8 khz frame sync. input 2048 khz data rate adpcm data output system clock = 10.24 mhz adpcm data input micro-controller adpcm chip 150 w 150 w 1 k 1 k 1k 1k 20 k 20 k 20 k 3 k 0.1 uf 0.1 uf 0.1 uf 0.1 uf 1.0 uf 1.0 uf 1.0 uf figure 10-1 typical handset application 10.2. transformer application for public switching telephone network (pstn) for this application, v ext = +5v 5%, v dd is an input and should be connected to v ext externally. the charge pump capacitor c1+ and c1- should not be used and the device must disable the charge pump circuit by setting br0[b2]. here v ext and v dd can share the same 0.1 m f capacitor. the transmitter ti-, ti+ and the receiver po-, po+ are connected to the secondary terminal of the telephone line transformer. the application circuit, figure 10-2 is as follows.
p reliminary w9321 publication release date: may 1999 - 31 - revision a1 tg ti- ti+ vag ro axo- axo+ vdsp vext pi po- po+ pdi/reset ssp en vdd fsr bclkr dr c1+ c1- vss mclk (scp) dt bclkt fst ssp rx ssp tx ssp clk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 22 28 27 26 25 24 23 21 20 19 18 17 16 15 battery power 8 k hz frame sync. input 2048 khz data rate adpcm data output system clock = 10.24 mhz adpcm data input m icro-controller adpcm chip 150 w 10 k 10 k 20 k 3 k r0 = 600 w tip n = 0.5 n = 1 ring n.c. n.c. n.c. n.c. 0.1 uf 0.1 uf 0.1 uf figure 10-2 typical transformer application 11. how to program the tone generator 11.1. introduction the chip can enable the tone generator by setting br7(b3) to logic "1". under this operation, the adpcm decoder will be disabled. the tone generator is implemented by the dsp engine based on the function "c" os(nx) ?. the procedure for programming the w9321 tone generator is as follows. setting br7(b3) to logic "1" turns on the tone generator. in addition, br7(b1:b0) must be set to logic "0" to avoid turning on tone1 or tone2, without first programming the coefficients for freqency and attenuation. setup the 12-bit coefficients for freqency and attenuation once every fsr cycle(125 m s). first the 8 least significant bits(lsb) of 12-bit coefficients must be written into br4(b7:b0); then the 4 most significant bits(msb) of 12-bit coefficients and address parameter will be written into br5(b3:b0) and br5(b7:b6) simultaneously in the same cycle. poll br7(b7) until br7(b7) becomes a logic "0" before writing another 12-bit coefficent for br4 and br5. set br7(b1:b0) to logic "1" selects the tone 1 or tone2 generator.
p reliminary w9321 - 32 - 11.2. tone frequency coefficient calculation the tone frequency coefficient is calculated by the function "cos(2*pi*f/8000 radian)" where pi = 3.14159, and f is frequency (hz). the number will then be converted into a 12-bit coefficient whose msb is the sign and whose remaining 11 bits are the fractional part found by multiplying by 2048 and rounding off the number. for example, if the frequency is 1209 hz, the frequency number is as followed. cos (2*3.14159*1209/8000) = 0.582053 the converted binary number is 010010101000 and the hex number 4a8, where br4 = 4 and br5 = a8. 11.3. tone attenuation coefficient calculation the tone attenuation coefficient is calculated by the function "x/1.579 vp" where x is the amplitude (vp). the number will be converted into a 12-bit coefficient whose msb is the sign and whose remaining 11 bits are the fractional part, found by multiplying by 2048 and rounding off the number. for example, if the attenuation is -14 dbm (600 w ) hz, first change the dbm units into vp format as follows. sqrt[10*exp(-14/10)*600*0.001] * sqrt(2) = 0.218570 vp the attenuation is "0.218570/1.579 = 0.138423" the binary number is 000100011011 and the hex number is 11b where br4 = 1 and br5 = 1b. 11.4. frequency coefficients for the dtmf signal table 11-1 shows the 12-bit frequency coefficients for the dtmf signal. the 8 least significant bits are stored in br4(b7:b0), the 4 most significant bits are stored in br5(b3:b0). table 11-2 illustrates the 12-bit attenuation coefficients for the dtmf signal such as -9 dbm (600 w ) or -6 dbm (600 w ) for column tone and -11 dbm (600 w ) or -8 dbm (600 w ) for row tone. freqency (hz) br5 (hex) br4 (hex) 697 6 d5 770 6 95 852 6 46 941 5 ea 1209 4 a8 1336 3 fc 1477 3 32 1633 2 46 table 11-1 frequency coefficients for the dtmf signal attenuation (dbm@600 w) peak value (vp) br5 (hex) br4 (hex) -11 0.308738 1 90 -9 0.388679 1 f8 -8 0.436105 2 35 -6 0.549023 2 c8 table 11-2 attenuation coefficients for the dtmf signal
p reliminary w9321 publication release date: may 1999 - 33 - revision a1 12. package dimensions 1 14 15 28 e h e b e1 c l l e q d s e a2 a1 a figure12-1 28-lead plastic sop package there are two packages for the w9321. one is a 28-lead plastic sop shown in figure 12-1, the other is a 28-lead plastic dip shown in 12-2. symbol dimension in inch dimension in mm a 0.110 max. 2.794 max. a1 0.004 min. 0.102 min. a2 0.093 0.005 2.362 0.127 b 0.016 +0.004 -0.002 0.406 +0.102 -0.051 c 0.010 +0.004 -0.002 0.254 +0.102 -0.051 d 0.705 typ. (0.725 max.) 17.90 typ. (18.415 max.) e 0.295 0.005 7.493 0.127 e 0.050 0.006 1.270 0.152 e1 0.370 nom. 9.396 nom. he 0.406 0.012 10.312 0.305 l 0.036 0.006 0.914 0.203 le 0.055 0.006 1.397 0.203 s 0.043 max. 0.102 max. q 0 - 10 degree 0 - 10 degree
p reliminary w9321 - 34 - seating plane e a 2 a a c e base plane 1 a 1 e l a s 1 e d 1 b b 28 1 15 14 figure12-2 28-lead plastic dip package symbol dimension in inch dimension in mm a 0.210 max. 5.334 max. a1 0.010 min. 0.254 min. a2 0.155 0.005 3.937 0.127 b 0.018 +0.004 -0.002 0.457 + 0.102 - 0.051 b1 0.06 + 0.004 - 0.002 1.524 +0.102 -0.051 c 0.01 + 0.004 - 0.002 0.254 +0.102 -0.051 d 1.46 typ. (1.47 max.) 37.084 typ. (37.33 max.) e 0.6 0.01 15.24 0.254 e1 0.545 0.005 13.843 0.127 e1 0.100 0.01 2.540 0.254 l 0.130 0.01 3.302 0.254 ea 0.650 0.02 16.51 0.508 s 0.09 max. 2.286 max. a 0 - 15 degree 0 - 15 degree
p reliminary w9321 publication release date: may 1999 - 35 - revision a1 headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792697 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-7197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-7190505 fax: 886-2-7197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2730 orchard parkway, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-9436668 note: all data and specifications are subject to change without notice.

▲Up To Search▲

Price & Availability of WINBONDELECTRONICSCORP-W9321S

	To Download WINBONDELECTRONICSCORP-W9321S Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .