1 dac811 dac811 microprocessor-compatible 12-bit digital-to-analog converter ? 1983 burr-brown corporation pds-503l printed in u.s.a. april, 2000 international airport industrial park ? mailing address: po box 11400, tucson, az 85734 ? street address: 6730 s. tucson bl vd., tucson, az 85706 ? tel: (520) 746-1111 twx: 910-952-1111 ? internet: http://www.burr-brown.com/ ? cable: bbrcorp ? telex: 066-6491 ? fax: (520) 889-1510 ? i mmediate product info: (800) 548-6132 for most current data sheet and other product information, visit www.burr-brown.com bpo v out d/a latch input latch 4 msbs input latch input latch 4 lsbs 12-bit d/a converter voltage reference 10v r f s j r f r bpo description the dac811 is a complete, single-chip integrated- circuit, microprocessor-compatible, 12-bit digital-to- analog converter. the chip combines a precision volt- age reference, microcomputer interface logic, and double-buffered latch, in a 12-bit d/a converter with a voltage output amplifier. fast current switches and a laser-trimmed thin-film resistor network provide a highly accurate and fast d/a converter. microcomputer interfacing is facilitated by a double- buffered latch. the input latch is divided into three 4-bit nibbles to permit interfacing to 4-, 8-, 12-, or 16-bit buses and to handle right-or left-justified data. the 12-bit data in the input latches is transferred to the d/a latch to hold the output value. input gating logic is designed so that loading the last nibble or byte of data can be accomplished simulta- neously with the transfer of data (previously stored in adjacent latches) from adjacent input latches to the d/a latch. this feature avoids spurious analog output values while using an interface technique that saves computer instructions. the dac811 is laser trimmed at the wafer level and is specified to 1/4lsb maximum linearity error (b and k grades) at 25 c and 1/2lsb maximum over the temperature range. all grades are guaranteed mono- tonic over the specification temperature range. the dac811 is available in six performance grades and three package types. dac811j and k are speci- fied over the temperature ranges of 0 c to +70 c; dac811a and b are specified over C25 c to +85 c; dac811j and k are packaged in a reliable 28-pin plastic dip or plastic so package, while dac811a and b are available in a 28-pin 0.6" wide dual-inline hermetically sealed ceramic side-brazed package (h package). features l single integrated circuit chip l microcomputer interface: double-buffered latch l voltage output: 10v, 5v, +10v l monotonicity guaranteed over temperature l 1/2lsb maximum nonlinearity over temperature l guaranteed specifications at 12v and 15v supplies l ttl/5v cmos-compatible logic inputs
dac811 2 DAC811AH, jp, ju dac811bh, kp, ku parameter min typ max min typ max units digital input resolution 12 [ bits codes (1) usb, bob [ digital inputs over temperature range (2) v ih +2 +15 [[ vdc v il 0 +0.8 [[ vdc i ih , v i = +2.7v +10 [ m a i il , v i = +0.4v 20 [ m a digital interface timing over temperature range t wp , wr pulse width 50 [ ns t aw 1, n x and ldac valid to end of wr 50 [ ns t dw , data valid to end of wr 80 [ ns t dh , data valid hold time 0 [ ns accuracy linearity error 1/4 1/2 1/8 1/4 lsb differential linearity error 1/2 3/4 1/4 1/2 lsb gain error (3) 0.1 0.2 [[ % offset error (3, 4) 0.05 0.15 [[ % of fsr (5) monotonicity guaranteed [ power supply sensitivity: +v cc 0.001 0.003 [[ % of fsr/%v cc Cv cc 0.002 0.006 [[ % of fsr/%v cc v dd 0.0005 0.0015 [[ % of fsr/%v dd drift (over specification temperature range) gain 10 30 10 20 ppm/ c unipolar offset 5 10 5 7 ppm of fsr/ c bipolar zero 5 10 5 7 ppm of fsr/ c linearity error over temperature range 1/2 3/4 1/4 1/2 lsb monotonicity over temperature range guaranteed [ settling time (6) (to within 0.01% of fsr of final value; 2k w load) for full scale range change, 20v range 3 4 [[ m s 10v range 3 4 [[ m s for 1lsb change at major carry (7) 1 [ m s slew rate (6) 812 [[ v/ m s analog output voltage range ( v cc = 15v) (8) : unipolar 0 to +10 [ v bipolar 5, 10 [ v output current 5 [ ma output impedance (at dc) 0.2 [ w short circuit to common duration indefinite [ reference voltage voltage +6.2 +6.3 +6.4 [[ [ v source current available for external loads +2 [ ma temperature coefficient 10 30 10 20 ppm/ c short circuit to common duration indefinite [ power supply requirements voltage: +v cc +11.4 +15 +16.5 [[ [ vdc Cv cc C11.4 C15 C16.5 [[ [ vdc v dd +4.5 +5 +5.5 [[ [ vdc current (no load): +v cc +16 +25 [[ ma Cv cc C23 C35 [[ ma v dd +8 +15 [[ ma potential at dcom with respect to acom (9) 0.5 [ v power dissipation 625 800 [[ mw temperature range specification: j, k 0 +70 [[ c a, b C25 +85 [[ c r, s C65 +150 [[ c c storage: j, k C60 +100 [[ c a, b, r, s C65 +150 [[ c [ specification same as DAC811AH, jp, ju. notes: (1) usb = unipolar straight binary; bob = bipolar offset binary. (2) ttl, lsttl and 54/74 hc compatible. (3) adjustable to zero with external trim potentiometer. (4) error at input code 000 16 for both unipolar and bipolar ranges. (5) fsr means full scale range and is 20v for the 10v range. (6) maximum represents the 3 s limit. not 100% tested for this parameter. (7) at the major carry, 7ff 16 to 800 16 and 800 16 to 7ff 16 . (8) minimum supply voltage required for 10v output swing is 13.5v. output swing for 11.4v supplies is at least C8v to +8v. (9) the maximum voltage at which acom and dcom may be separated without affecting accuracy specifications. specifications at t a = +25 c. v cc = 12v or 15v, unless otherwise noted.
3 dac811 minimum relative differential package specification accuracy linearity drawing temperature ordering transport product (lsb) (lsb) package number range number (1) media DAC811AH 1/2 lsb 3/4 cerdip-28 149 C25 c to +85 c DAC811AH rails dac811jp 1/2 lsb 3/4 dip-28 215 0 c to +70 c dac811jp rails dac811ju 1/2 lsb 3/4 so-28 217 0 c to +70 c dac811ju rails "" " "" " dac811ju/1k tape and reel dac811kp 1/4 lsb 1/2 dip-28 215 0 c to +70 c dac811kp rails dac811ku 1/4 lsb 1/2 so-28 217 0 c to +70 c dac811ku rails note: (1) models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /1k indicates 1000 dev ices per reel). ordering 1000 pieces of dac811ju/1k will get a single 1000-piece tape and reel. +v cc ............................................................................................................................... . 0 to +18v Cv cc to acom .......................................................................... 0 to C18v v dd to dcom .............................................................................. 0 to +7v v dd to acom ...................................................................................... 7v acom to dcom .................................................................................. 7v digital inputs (pins 2C14, 16C19) to dcom ...................... C0.4v to +18v external voltage applied to 10v range resistor ............................ 12v ref out ............................................................. indefinite short to acom external voltage applied to dac output ................................ C5v to +5v power dissipation ........................................................................ 1000mw lead temperature (soldering, 10s) ............................................... +300 c max junction temperature ............................................................ +165 c thermal resistance, q j-a : plastic dip and soic ....................... 100 c/w ceramic dip .................................................................................. 65 c/w note: stresses above those listed above may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods may affect device reliability. pin descriptions absolute maximum ratings electrostatic discharge sensitivity this integrated circuit can be damaged by esd. burr-brown recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. package/ordering information the information provided herein is believed to be reliable; however, burr-brown assumes no responsibility for inaccuracies or o missions. burr-brown assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. pr ices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. burr-brown does not authorize or warrant any burr-brown product for use in life support devices and/or systems. pin name function 1+v dd logic supply, +5v. 2 wr write, command signal to load latches. logic low loads latches. 3 ldac load d/a converter, enables wr to load the d/a latch. logic low enables. 4n a nibble a, enables wr to load input latch a (the most significant nibble). logic low enables. 5n b nibble b, enables wr to load input latch b. logic low enables. 6n c nibble c, enables wr to load input latch c (the least significant nibble). logic low enables. 7d 11 data bit 12, msb, positive true. 8d 10 data bit 11. 9d 9 data bit 10. 10 d 8 data bit 9. 11 d 7 data bit 8. 12 d 6 data bit 7. 13 d 5 data bit 6. 14 d 4 data bit 5. 15 dcom digital common, v dd supply return. 16 d 0 data bit 1, lsb. 17 d 1 data bit 2. 18 d 2 data bit 3. 19 d 3 data bit 4. 20 +v cc analog supply input, +15v or +12v. 21 Cv cc analog supply input, C15v or C12v. 22 gain adj to externally adjust gain. 23 acom analog common, v cc supply return. 24 v out d/a converter voltage output. 25 10v range connect to pin 24 for 10v range. 26 sj summing junction of output amplifier. 27 bpo bipolar offset. connect to pin 26 for bipolar operation. 28 ref out 6.3v reference output.
dac811 4 timing diagrams discussion of specifications input codes the dac811 accepts positive-true binary input codes. dac811 may be connected by the user for any one of the following codes: usb (unipolar straight binary), bob (bi- polar offset binary) or, using an external inverter on the msb line, btc (binary twos complement). see table i. drift gain drift is a measure of the change in the full scale range (fsr) output over the specification temperature range. drift is expressed in parts per million per degree centigrade (ppm/ c). gain drift is established by testing the full scale range value (e.g., +fs minus Cfs) at high temperature, +25 c, and low temperature, calculating the error with respect to the +25 c value, and dividing by the temperature change. unipolar offset drift is a measure of the change in output with all 0s on the input over the specification temperature range. offset is measured at high temperature, +25 c, and low temperature. the offset drift is the maximum change in offset referred to the +25 c value, divided by the tempera- ture change. it is expressed in parts per million of full scale range per degree centigrade (ppm of fsr/ c). bipolar zero drift is measured at a digital input of 800 16 , the code that gives zero volts output for bipolar operation. settling time settling time is the total time (including slew time) for the output to settle within an error band around its final value after a change in input. three settling times are specified to 0.01% of full scale range (fsr): two for maximum full scale range changes of 20v and 10v, and one for a 1lsb change. the 1lsb change is measured at the major carry (7ff 16 to 800 16 and 800 16 to 7ff 16 ), the input transition at which worst-case settling time occurs. reference supply dac811 contains an on-chip 6.3v reference. this voltage (pin 28) has a tolerance of 0.1v. the reference output may be used to drive external loads, sourcing at least 2ma. this current should be constant for best performance of the d/a converter. power supply sensitivity power supply sensitivity is a measure of the effect of a power supply change on the d/a converter output. it is defined as a percent of fsr output change per percent of change in either the positive, negative, or logic supply voltages about the nominal voltages. figure 1 shows typical power supply rejection versus power supply ripple frequency. digital input analog output usb bob btc (1) unipolar bipolar binary straight offset twos binary binary complement 111111111111 + full scale + full scale C1lsb 100000000000 + 1/2 full scale zero C full scale 011111111111 + 1/2 full scale C 1lsb C1lsb + full scale 000000000000 zero C full scale zero note: (1) invert msb of the bob code with external inverter to obtain btc code. msb lsb table i. digital input codes. linearity error linearity error as used in d/a converter specifications by burr-brown is the deviation of the analog output from a straight line drawn between the end points (inputs all 1s and all 0s). the dac811 linearity error is specified at 1/4lsb (max) at +25 c for b and k grades, and 1/2lsb (max) for a and j grades. differential linearity error differential linearity error (dle) is the deviation from a 1lsb output change from one adjacent state to the next. a dle specification of 1/2lsb means that the output step size can range from 1/2lsb to 3/2lsb when the input changes from one state to the next. monotonicity requires that dle be less than 1lsb over the temperature range of interest. monotonicity a d/a converter is monotonic if the output either increases or remains the same for increasing digital inputs. all grades of dac811 are monotonic over their specification tempera- ture range. load first rank from data bus: ldac = 1 wr n t aw t dw t dh t wp a , n b , n c db 11 ?b 0 write cycle #1 t set wr 1/2lsb ldac t aw t wp load second rank from first rank: n a , n , n c b = 1 write cycle #2
5 dac811 figure 1. power supply rejection vs power supply ripple frequency. operation dac811 is a complete single ic chip 12-bit d/a converter. the chip contains a 12-bit d/a converter, voltage reference, output amplifier, and microcomputer-compatible input logic as shown in figure 2. interface logic input latches a, b, and c hold data temporarily while a complete 12-bit word is assembled before loading into the d/a register. this double-buffered organization prevents the generation of spurious analog output values. each register is independently addressable. these input latches are controlled by n a , n b , n c , and wr. n a , n b , and n c are internally nored with wr so that the input latches transmit data when both n a (or n b , n c ) and wr are at logic 0. when either n a , (n b , n c ) or wr go to logic 1, the input data is latched into the input registers and held until both n a (or n b , n c ) and wr go to logic 0. figure 2. dac811 block diagram. wr n a n b n c ldac operation 1 x x x x no operation 0 0 1 1 1 enables input latch 4msbs 0 1 0 1 1 enables input latch 4 middle bits 0 1 1 0 1 enables input latch 4lsbs 01 11 0 loads d/a latch from input latches 0 0 0 0 0 makes all latches transparent x = dont care. table ii. dac813 interface logic truth table. gain and offset adjustments figures 3 and 4 illustrate the relationship of offset and gain adjustments to unipolar and bipolar d/a converter output. offset adjustment for unipolar (usb) configurations, apply the digital input code that should produce zero voltage output, and adjust the offset potentiometer for zero output. for bipolar (bob, btc) configurations, apply the digital input code that should produce the maximum negative output voltage and adjust the offset potentiometer for minus full scale voltage. ex- ample: if the full scale range is connected for 20v, the maximum negative output voltage is C10v. see table iii for corresponding codes. the d/a latch is controlled by ldac and wr. ldac and wr are internally nored so that the latches transmit data to the d/a switches when both ldac and wr are at logic 0. when either ldac or wr are at logic 1, the data is latched in the d/a latch and held until ldac and wr go to logic 0. all latches are level-triggered. data present when the con- trol signals are logic 0 will enter the latch. when any one of the control signals returns to logic 1, the data is latched. table ii is a truth table for all latches. frequency (hz) percent of fsr per percent of change of power supply voltage 1 0.1 0.01 0.001 0.0001 10 100 1k 10k 100k +v cc ? cc v dd m 1 d0 bpo sj v out 12-bit d/a converter 12-bit d/a latch 4-bit latch, a 27 26 25 24 7 8 9 10 11 12 13 14 19 18 17 16 d11 d8 d7 reference 2 wr 4 a 5 6 ldac 3 10v range n b n c n d4 d3 acom 23 ref out 28 r bpo r f r f 4-bit latch, b 4-bit latch, c msb lsb
dac811 6 12v operation the dac811 is fully specified for operation on 12v power supplies. however, in order for the output to swing to 10v, the power supplies must be 13.5v or greater. when oper- ating with 12vb supplies, the output swing should be restricted to 8v in order to meet specifications. logic input compatibility the dac811 digital inputs are ttl, lsttl, and 54/74hc cmos-compatible over the operating range of v dd . the input switching threshold remains at the tll threshold over the supply range. the logic input current over temperature is low enough to permit driving the dac811 directly from the outputs of 4000b and 54/74c cmos devices. resistors of 47 w should be placed in series with d0 through d11, wr, n a , n b , n c and ldac if edges are <10ns or if the logic input is driven below ground by undershoot. installation power supply connections for optimum performance and noise rejection, power supply decoupling capacitors should be added as shown in figure 5. these capacitors (1 m f tantalum recommended) should be located close to the dac811. figure 3. relationship of offset and gain adjustments for a unipolar d/a converter. figure 4. relationship of offset and gain adjustments for a bipolar d/a converter. table iii. digital input/analog output. analog output digital input 0 to +10v 5v 10v 111111111111 +9.9976v +4.9976v +9.9951v 100000000000 +5v 0v 0v 011111111111 +4.9976v C0.0024v C0.0049v 000000000000 0v C5v C10v lsb 2.4mv 2.44mv 4.88mv msb lsb gain adjustment for either unipolar or bipolar configurations, apply the digital input that should give the maximum positive voltage output. adjust the gain potentiometer for this positive full scale voltage. see table iii for positive full scale voltages. figure 5. power supply, gain, and offset potentiometer connections. + full scale all bits logic 0 1lsb range of offset adj. offset adjust translates the line digital input all bits logic 1 range of gain adjust analog output gain adjust rotates the line full scale range + full scale all bits logic 0 1lsb range of offset adjust digital input all bits logic 1 analog output full scale range gain adjust rotates the line ?full scale msb on all others off bipolar v offset range of gain adjust offset adj. translates the line ? 0.4% 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 10k to 100k w w dd v bpo v dd summing junction v acom gain adjust dcom +v cc ? cc out 1 f 0.0022 f 1 f 3.9m w 1 f ? cc +v cc +v cc 10k to 100k w w ? cc 1m w connect for bipolar operation
7 dac811 dac811 features separate digital and analog power supply returns to permit optimum connections for low noise and high speed performance. the analog common (pin 23) and digital common (pin 15) should be connected together at one point. separate returns minimize current flow in low level signal paths if properly connected. logic return currents are not added into the analog signal return path. a 0.5v difference between acom and dcom is permitted for specified operation. high frequency noise on dcom with respect to acom may permit noise to be coupled through to the analog output; therefore, some caution is required in applying these common connections. the analog common is the high quality return for the d/a converter and should be connected directly to the analog reference point of the system. the load driven by the output amplifier should be returned to the analog common. external offset and gain adjustment offset and gain may be trimmed by installing external offset and gain potentiometers. connect these potentiom- eters as shown in figure 5. tcr of the potentiometers should be 100ppm/ c or less. the 1m w and 3.9m w resis- tors (20% carbon or better) should be located close to the dac811 to prevent noise pickup. if it is not convenient to use these high value resistors, an equivalent t network, as shown in figure 6, may be substituted in each case. the gain adjust (pin 22) is a high impedance point and a 0.001 m f to 0.01 m f ceramic capacitor should be connected from this pin to analog common to reduce noise pickup in all applications, including those not employing external gain adjustment. excessive capacitance on the gain adjust or offset adjust pin may affect slew rate and settling time. figure 6. equivalent resistances. figure 7. output amplifier voltage range scaling circuit. output digital connect connect range input codes pin 25 to pin 27 to 0 to +10v usb 24 23 5 bob or btc 24 26 10v bob or btc nc 26 table iv. output range connections. applications microcomputer bus interfacing the dac811 interface logic allows easy interface to micro- computer bus structures. the control signal wr is derived from external device select logic and the i/o write or memory write (depending upon the system design) signals from the microcomputer. the latch enable lines n a , n b , n c and ldac determine which of the latches are enabled. it is permissible to enable two or more latches simultaneously, as shown in some of the following examples. the double-buffered latch permits data to be loaded into the input latches of several dac811s and later strobed into the d/a latch of all d/as, simultaneously updating all analog outputs. all the interface schemes shown below use a base address decoder. if blocks of memory are used, the base address decoder can be simplified or eliminated altogether. for instance, if half the memory space is unused, address line a15 of the microcomputer can be used as the chip select control. 4-bit interface an interface to a 4-bit microcomputer is shown in figure 8. each dac811 occupies four address locations. a 74ls139 provides the two-to-four decoder and selects it with the base address. memory write (wr) of the microcomputer is connected directly to the wr pin of the dac811. an 8205 decoder is an alternative to the 74ls139. output range connections internal scaling resistors provided in the dac811 may be connected to produce bipolar output voltage ranges of 10v and 5v or a unipolar output voltage range of 0 to +10v. the 20v range ( 10v bipolar range) is internally connected. refer to figure 7. connections for the output ranges are listed in table iv. 1m w 3.9m w 100k w 100k w 12k w 10k w 180k w 180k w 4.26k w 5.36k w 24 v out 23 analog common from d/a converter from voltage reference 4.26k w 25 10v range 26 summing junction 27 bipolar offset
dac811 8 figure 10. right-justified data bus interface. figure 11. left-justified data bus interface. figure 8. addressing and control for 4-bit microcom- puter interface. figure 9. 12-bit data format for 8-bit systems. d0 d4 d8 d1 d5 d9 d2 d6 d10 d3 d7 d11 16 14 10 17 13 9 18 12 8 19 11 7 db0 db1 db2 db3 wr a a 1 0 microcomputer dac811 base address decoder a a n 2 2 3 4 5 6 wr ldac n n n 1/2 74ls139 a b c 7 6 5 4 1 3 2 cs (chip select) a a 1 0 en y y y y 3 2 1 0 x x x x d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a. right-justified d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 b. left-justified xxxx d0 d8 d1 d9 d2 d10 d3 d11 d4 d5 d6 d7 16 10 17 9 18 8 19 7 14 13 12 11 db0 db1 db2 db3 db4 db5 db6 db7 wr a a 1 0 microcomputer dac811 base address decoder a a 15 2 2 3 4 5 6 wr ldac n n n a b c cs d4 d5 d6 d7 d8 d0 d9 d1 d10 d2 d11 d3 14 13 12 11 10 16 9 17 8 18 7 19 db0 db1 db2 db3 db4 db5 db6 db7 wr a a 1 0 microcomputer dac811 base address decoder a a 15 2 2 3 4 5 6 wr ldac n n n a b c cs 8-bit interface the control logic of dac811 permits interfacing to right- justified data formats, as illustrated in figure 9. when a 12-bit d/a converter is loaded from an 8-bit bus, two bytes of data are required. figures 10 and 11 show an addressing scheme for right-justified and left-justified data respectively. the base address is decoded from the high-order address bits. a 0 and a 1 address the appropriate latches. note that adjacent addresses are used. for the right-justified case, x10 16 loads the 8lsbs, and x01 16 loads the 4msbs and simultaneously transfers input latch data to the d/a latch. addresses x00 16 and x11 16 are not used. left-justified data is handled in a similar manner, shown in figure 11. the dac811 still occupies two adjacent loca- tions in the microcomputer's memory map.
9 dac811 address bus a3 a2 a1 a0 operation 0 0 0 0 load 8 lsb C d/a #1 0 0 0 1 load 4 msb C d/a #1 0 0 1 0 load 8 msb C d/a #2 0 0 1 1 load 4 msb C d/a #2 0 1 0 0 load 8 msb C d/a #3 0 1 0 1 load 4 msb C d/a #3 0 1 1 0 load 8 msb C d/a #4 0 1 1 1 load 4 msb C d/a #4 1 x x x load d/a latchall d/a figure 12. interfacing multiple dac811s to an 8-bit bus. base address decoder wr a a 15 4 a a a 2 1 0 microcomputer a 3 74ls138 c b a g g g 2a 2b 1 wr ldac n n n y0 y1 y2 y3 y4 y5 y6 y7 15 14 13 12 11 10 9 7 3 2 1 4 6 5 cs dac811 (4) c b a wr ldac n n n dac811 (1) c b a wr ldac n n n dac811 (2) c b a interfacing multiple dac811s in 8-bit systems many applications, such as automatic test systems, require that the outputs of several d/a converters be updated simul- taneously. the interface shown in figure 12 uses a 74ls138 decoder to decode a set of eight adjacent addresses, to load the input latches of four dac811s. the example shows a right-justified data format. a ninth address using a 3 causes all dac811s to be updated simultaneously. if a particular dac811 is always loaded lastfor instance, d/a #4a 3 is not needed, thus saving eight address spaces for other uses. incorporate a 3 into the base address decoder, remove the inverter, connect the common ldac line to n c of d/a #4, and connect d1 of the 74ls138 to +5v. 12- and 16-bit microcomputer interface for this application, the input latch enable lines, n a , n b and n c, are tied low, causing the latches to be transparent. the d/a latch, and therefore dac811, is selected by the address decoder and strobed by wr.
|
