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oki semiconductor FEDS82V48540-01 issue date:nov. 8, 2002 ms82v48540 393,216-word 32-bit 4-bank fifo-sgram 1/44 general description the ms82v48540 is a 48-mb it system clock synchronous dynamic rand om access memory. in addition to the conventional random read/write access function, the ms 82v48540 provides the automa tic row address increment function and automatic bank switching function. therefore, if once the row and column addresses are set, continuous serial accesses are possible while banks ar e automatically switched till input of the precharge command. the ms82v48540 is ideal for digital camera and tv buffer memory applications. features ? 393,216 words 32 bits 4 banks memory (1,536 rows 256 columns 32 bits 4 banks) ? single 3.3 v 0.3 v power supply ? lvttl compatible inputs and outputs ? programmable burst length (1, 2, 4, 8 and full page) ? programmable cas latency (2, 3) ? automatic row address increment function and automatic bank switching function ? power down operation a nd clock suspend operation ? 3,072 refresh cycles/64 ms ? auto refresh and self refresh capability ? package: 86-pin 400 mil plastic tsop (ii) (tsopii86-p-400-0.50-k) (product : ms82v48540-xta) x indicates speed rank. product family family max. operating frequency access time package ms82v48540-7 143 mhz 5 ns ms82v48540-8 125 mhz 6 ns 86-pin plastic tsop (ii) (400 mil)
FEDS82V48540-01 oki semiconductor ms82v48540 2/44 pin configuration (top view) 86-pin plastic tsop (ii) (type k) pin name function pin name function a0 ? a10 row address inputs we write enable a0 ? a7 column address inputs dqm0 ? dqm3 dq mask enable ba0, ba1 bank address dq0 ? dq31 data inputs/outputs clk system clock input v cc supply voltage cke clock enable v ss ground cs chip select v cc q supply voltage for dq ras row address strobe v ss q ground for dq cas column address strobe nc no connection note: the same power supply voltage must be provided to every v cc pin and v cc q pin. the same gnd voltage level must be provided to every v ss pin and v ss q pin. 10 11 12 13 9 8 7 6 5 4 3 2 1 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 77 76 75 74 78 79 80 81 82 83 84 85 86 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 v cc dq0 v cc q dq1 dq2 v ss q dq3 dq4 v cc q dq5 dq6 v ss q dq7 nc v cc dqm0 we cas ras cs nc ba0 ba1 a10/ap a0 a1 a2 dqm2 v cc nc dq16 v ss q dq17 dq18 v cc q dq19 dq20 v ss q dq21 dq22 v cc q dq23 v cc v ss dq15 v ss q dq14 dq13 v cc q dq12 dq11 v ss q dq10 dq9 v cc q dq8 nc v ss dqm1 nc nc clk cke a9 a8 a7 a6 a5 a4 a3 dqm3 v ss nc dq31 v cc q dq30 dq29 v ss q dq28 dq27 v cc q dq26 dq25 v ss q dq24 v ss
FEDS82V48540-01 oki semiconductor ms82v48540 3/44 block diagram bank d bank c bank b timing register dq0 to dq31 ras cas a 0 to a10 ba0, ba1 bank controller internal column address counter i/o controller column address buffers internal row address counter row address buffers read data register output buffers input data register input buffers cke clk cs we dqm0 to dqm3 ba0, ba1 11 32 32 32 32 32 bank a column decoders sense amplifiers word drivers 12mb memory cells row decoders 8
FEDS82V48540-01 oki semiconductor ms82v48540 4/44 pin description clk fetches all inputs at the "h" edge. cs disables or enables device operation by asserting or deactivating all inputs except clk, cke, dqm0, dqm1, dqm2 and dqm3. cke masks system clock to deactivate the subsequent clk operation. if cke is deactivated, system clock will be ma sked so that the subs equent clk operation is deactivated. cke should be asserted at l east one cycle prior to a new command. address row & column multiplexed. row address: ra0 ? ra10 column address: ca0 ? ca7 ba0, ba1 selects bank to be activated during row addre ss latch time and selects bank for precharge and read/write during column address latch time. ba0 = ?l?, ba1 = ?l?: bank a ba0 = ?h?, ba1 = ?l?: bank b ba0 = ?l?, ba1 = ?h?: bank c ba0 = ?h?, ba1 = ?h?: bank d ras cas we functionality depends on the combination. for details, see the func tion truth table. dqm0 ? dqm3 masks the read data of two clocks later when dqm0 - dqm3 are set "h" at the "h" edge of the clock signal. masks the write data of the same clock when dqm0 - dqm3 are set "h" at the "h" edge of the clock signal. dqm0 controls dq0 to dq7, dqm1 controls dq8 to dq15, dqm2 cont rols dq16 to dq23, and dqm3 controls dq24 to dq31. dq0 ? dq31 data inputs/ outputs are multiplex ed on the same pin. *notes: 1. when cs is set "high" at a clock transition from "low" to "high", all inputs except clk, cke, dqm0, dqm1, dqm2, and dqm3 are invalid. 2. when issuing an active, read or write command, the bank is selected by ba0 and ba1. ba0 ba1 active, read or write 0 0 bank a 1 0 bank b 0 1 bank c 1 1 bank d 3. the auto precharge function is enabled or di sabled by the a10/ap input when the read or write command is issued. a10/ap ba0 ba1 operation 0 0 0 after the end of burst, bank a holds the active status. 1 0 0 after the end of burst, bank a is precharged automatically. 0 1 0 after the end of burst, bank b holds the active status. 1 1 0 after the end of burst, bank b is precharged automatically. 0 0 1 after the end of burst, bank c holds the active status. 1 0 1 after the end of burst, bank c is precharged automatically. 0 1 1 after the end of burst, bank d holds the active status. 1 1 1 after the end of burst, bank d is precharged automatically.
FEDS82V48540-01 oki semiconductor ms82v48540 5/44 4. when issuing a precharge command, the bank to be precharged is selected by the a10/ap, ba0 and ba1 inputs. a10/ap ba0 ba1 operation 0 0 0 bank a is precharged. 0 1 0 bank b is precharged. 0 0 1 bank c is precharged. 0 1 1 bank d is precharged. 1 all banks are precharged.
FEDS82V48540-01 oki semiconductor ms82v48540 6/44 command operation mode register set command ( cs , ras , cas , we = ?low?) the ms82v48540 has the mode register that defines the operation mode ? cas latency, burst length, burst sequence?. the mode register set command should be executed just after the ms 82v48540 is powered on. before entering this command, all banks must be precharged. next command can be issued after t rsc . auto refresh command ( cs , ras , cas = ?low?, we = ?high?) the auto refresh command performs refresh automatically by the address counter. the refresh operation must be performed 3,072 times within 64 ms and the next command can be issued after t rc from last auto refresh command. before entering this command, all banks must be precharged. self refresh entry/exit command ( cs , ras , cas , cke = ?low?, we = ?high?) the self refresh operation continues after the self refres h entry command is entered, with cke level left ?low?. this operation terminates by making cke level ?high?. the self refresh operation is performed automatically by the internal address counter on the ms82v48540 chip. in self refresh mode, no external refresh control is requir ed. before entering self refresh mode, all banks must be precharged. next command can be issued after t rc . single bank precharge command ( cs , ras , we , a10/ap = ?low?, cas = ?high?) the single bank precharge command triggers bank precharge operation. precharge bank is selected by ba0 and ba1. all banks precharge command ( cs , ras , we = ?low?, cas , a10/ap = ?high?) the all bank precharge command triggers precharge of all banks. if this command is executed during special bank active mode, the special bank active mode is terminated. bank active command ( cs , ras = ?low?, cas , we = ?high?) the bank active command activates the bank selected by ba0 and ba1. the bank active command corresponds to conventional dram's ras falling operation. row addresses ?a0 ? a10, ba0 and ba1? are strobed. write command ( cs , cas , we , a10/ap = ?low?, ras = ?high?) the write command is required to begin burst write oper ation. then burst access initia l bit column address is strobed. write with auto precharge command ( cs , cas , we = ?low?, ras , a10/ap = ?high?) the write with auto precharge command is required to be gin burst write operation with automatic precharge after the burst write. any command that interrupts this operation cannot be issued. read command ( cs , cas , a10/ap = ?low?, ras , we = ?high?) the read command is required to begin burst read oper ation. then burst access initia l bit column address is strobed.
FEDS82V48540-01 oki semiconductor ms82v48540 7/44 read with auto prechaege command ( cs , cas = ?low?, ras , we , a10/ap = ?high?) the read with auto precharge command is required to begin burst read oper ation with auto precharge after the burst read. any command that interrupts this operation cannot be issued. no operation command ( cs = ?low?, ras , cas , we = ?high?) the no operation command does not trigger any operation. device deselect command ( cs = ?high?) the device deselect command disables the ras , cas , we and address input. this command does not trigger any operation. data write/output enable command (dqmi = ?low?) the data write/output enable command enables dq0 - dq31 in read or write. the each dqm0, 1, 2 and 3 corresponds to dq0 - dq7, dq8 - dq15, dq16 - dq23 and dq24 - dq31 respectively. data mask/output disabl e command (dqmi = ?high?) the data mask/output disable command disables dq0 - dq31 in read or write. in read cycle output buffers are disabled after 2 clocks . in write cycle input buffers ar e disabled at the same clock. the each dqm0, 1, 2 and 3 corresponds to dq0 - dq7, dq8 - dq15, dq16 - dq23 and dq24 - dq31 respectively. burst stop command ( cs , we = ?low?, ras , cas = ?high?) the burst stop command stops burst access. after the burst stop command is entered, the output buffer goes into high impedance state.
FEDS82V48540-01 oki semiconductor ms82v48540 8/44 special read/write operation the special read or write operation is activated by execu ting the read or write command after selecting the special page mode with the mode register command. the automatic bank switching and automatic row address increment operations are ac tivated by executing the bank active command during special page mode, and the se rial access starts from the address fetched with the read or write command. the burst op eration starts from the start address toward the column. when the last column address is reached, the bank is automatically switched and the ro w address is also automatically incremented and the serial access continues from the st art column address. the automatic bank switching and automatic row address in crement operations continue until the all bank precharge co mmand is executed each time the last column address is reached. since the bank switching and row addr ess increment are automa tically made during the special read or write operation, the row address proceeds as shown in the following figure. ? ? ? row column start address note) the circled numbers indicate the orders of row address increment. 0 1535 operation is ended by input of all bank precharge command. ? ? ? 0 1535 ? 3071 ? 3072 0 256 0 1535 0 1535 0 256 bank a ba0 = ?l?, ba1 = ?l? bank c ba0 = ?l?, ba1 = ?h? bank b ba0 = ?h?, ba1 = ?l? bank d ba0 = ?h?, ba1 = ?h? 3073 3075 3174 3076 3078 3080 3077 3079 6144 6143 0 256 0 256
FEDS82V48540-01 oki semiconductor ms82v48540 9/44 truth table command truth table address function cs ras cas we ba0, 1 a10/ap a9 ? a0 device deselect h no operation l h h h mode register set l l l l op. code auto refresh l l l h bank activate l l h h ba ra read l h l h ba l ca (a7 ? a0) read with auto precharge l h l h ba h ca (a7 ? a0) write l h l l ba l ca (a7 ? a0) write with auto precharge l h l l ba h ca (a7 ? a0) precharge select bank l l h l ba l precharge all banks l l h l h burst stop l h h l dqm truth table function dqmi data write/output enable l data mask/output disable h
FEDS82V48540-01 oki semiconductor ms82v48540 10/44 function truth table (1/3) note 1 current state cs ras cas we ba address action note h nop l h h h nop l h h l ba illegal 2 l h l ba ca, a10 illegal 2 l l h h ba ra row active l l l l l op-code mode register write l l h l ba a10 nop 4 idle l l l h auto refresh/self refresh 5 h nop l h h nop l h l h ba ca, a10 read l h l l ba ca, a10 write l l h h ba ra illegal 2 l l h l ba a10 precharge active (act) l l l illegal h nop l h h nop l h l h ba ca serial read l h l l ba ca serial write l l h h ba ra illegal l l h l ba a10: l illegal l l h l ba a10: h precharge active (special page mode) (sact) l l l illegal h nop (continue row active after burst ends) l h h h nop (continue row active after burst ends) l h h l burst stop row active l h l h ba ca, a10 term burst, new read 3 l h l l ba ca, a10 term burst, start write 3 l l h h ba ra illegal 2 l l h l ba a10 term burst, execute precharge read (rd) l l l illegal h nop (continue row active after burst ends) l h h h nop (continue row active after burst ends) l h h l burst stop row active l h l h ba ca, a10 term burst, start read 3 l h l l ba ca, a10 term burst, new write 3 l l h h ba ra illegal 2 l l h l ba a10 term burst, execute precharge 3 write (wt) l l l illegal
FEDS82V48540-01 oki semiconductor ms82v48540 11/44 function truth table (2/3) note 1 current state cs ras cas we ba address action note h nop (continue burst to end and enter precharge) l h h h nop (continue burst to end and enter precharge) l h h l illegal l h l h ba ca, a10 illegal l h l l ba ca, a10 illegal l l h h ba ra illegal 2 l l h l ba a10 illegal 2 read with auto precharge (rap) l l l illegal h nop (continue burst to end and enter precharge) l h h h nop (continue burst to end and enter precharge) l h h l illegal l h l h ba ca, a10 illegal l h l l ba ca, a10 illegal l l h h ba ra illegal 2 l l h l ba a10 illegal 2 write with auto precharge (wap) l l l illegal h nop (continue serial read) l h h h nop (continue serial read) l h h l illegal l h l ba ca illegal l l h h ba ra illegal l l h l ba a10: l illegal l l h l ba a10: h precharging read (special page mode) (srd) l l l illegal h nop (continue serial write) l h h h nop (continue serial write) l h h l illegal l h l ba ca illegal l l h h ba ra illegal l l h l ba a10: l illegal l l h l ba a10: h precharging write (special page mode) (swt) l l l illegal h nop idle after t rp l h h h nop idle after t rp l h h l ba illegal 2 l h l ba ca illegal 2 l l h h ba ra illegal 2 l l h l ba a10 nop 4 precharging (pre) l l l illegal
FEDS82V48540-01 oki semiconductor ms82v48540 12/44 function truth table (3/3) note 1 current state cs ras cas we ba address action note h nop idle after t rc l h h h nop idle after t rc l h h l ba illegal l h l ba ca illegal l l h h ba ra illegal l l h l ba a10 illegal refreshing (ref) l l l illegal abbreviations ba = bank address ra = row a ddress ca = column address nop = no operation command notes: 1. all inputs are enabled when cke is set hi gh for at least 1 cycle prior to the inputs. 2. illegal to bank in specified state, but ma y be legal in some cases depending on the state of bank selection. 3. to avoid bus contention, satisfy t ccd and t dpl . 4. nop to bank precharging or in idle stat e. precharges activated bank by ba or a10/ap. 5. illegal if any bank is not idle.
FEDS82V48540-01 oki semiconductor ms82v48540 13/44 function truth table for cke current state (n) cken-1 cken cs ras cas we address action note h invalid l h h exit self refresh abi l h l h h h exit self refresh abi l h l h h l illegal l h l h l illegal l h l l illegal self refresh (sref) l l nop (maintain self refresh) h invalid l h h exit self refresh abi l h l h h h exit self refresh abi l h l h h l illegal l h l h l illegal l h l l illegal power down (pd) l l nop (continue power down mode) h h refer to truth table 6 h l h enter power down 6 h l l h h h enter power down 6 h l l h h l illegal 6 h l l h l illegal 6 h l l l h l illegal 6 h l l l l h enter self refresh 6 h l l l l l illegal 6 all banks idle (abi) l l nop 6 h h refer to truth table h l begin clock suspend next cycle l h enable clock of next cycle any state other than listed above l l continue clock suspension note: 6. power-down and self refresh can be enter ed only when all the banks are in an idle state.
FEDS82V48540-01 oki semiconductor ms82v48540 14/44 mode set address keys operation code cas latency burst type burst length a8 a7 tm a6 a5 a4 cl a3 bt a2 a1 a0 bt = 0 bt = 1 0 0 mode setting 0 0 0 reserved 0 sequential 0 0 0 1 reserved 0 1 0 0 1 reserved 1 interleave 0 0 1 2 reserved 1 0 0 1 0 2 0 1 0 4 4 1 1 vender use only 0 1 1 3 0 1 1 8 8 write burst length *note 1 1 0 0 reserved 1 0 0 reserved reserved a9 length 1 0 1 reserved 1 0 1 reserved reserved 0 burst 1 1 0 reserved 1 1 0 special page reserved 1 single bit 1 1 1 reserved 1 1 1 full page reserved *note 1: to select special page mode, set a9 to ?l?. the write burst length during special page mode is set only for burst. power on sequence 1. with cke = "h", dqm = "h" and the other in puts in nop state, turn on the power supply and start the system clock. 2. after the v cc voltage has reached the spec ified level, pause for 200 s or more with the input kept in nop state. 3. issue the precharge all bank command. 4. apply an auto-refresh 8 or more times. 5. enter the mode register command.
FEDS82V48540-01 oki semiconductor ms82v48540 15/44 burst length and sequence bl = 2 starting address (column address a0, binary) sequential type interleave type 0 0, 1 not supported 1 1, 0 not supported bl = 4 starting address (column address a1, a0, binary) sequential type interleave type 00 0, 1, 2, 3 0, 1, 2, 3 01 1, 2, 3, 0 1, 0, 3, 2 10 2, 3, 0, 1 2, 3, 0, 1 11 3, 0, 1, 2 3, 2, 1, 0 bl = 8 starting address (column address a2 - a0, binary) sequential type interleave type 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 bl = special, full : sequential only
FEDS82V48540-01 oki semiconductor ms82v48540 16/44 read/write command interval read to read command interval write to write command interval write to read command interval clk rd-a dq qb1 0 1 2 3 4 5 6 7 8 qb2 qb3 qa1 rd-b qb4 1cycle bl = 4, cl = 2 hi-z clk wt-a dq da1 0 1 2 3 4 5 6 7 8 db1 db2 db3 wt-b db4 1cycle bl = 4, cl = 2 hi-z clk wt-a dq da1 0 1 2 3 4 5 6 7 8 qb1 qb2 qb3 rd-b qb4 hi-z bl = 4 cl = 2 wt-a dq da1 qb1 qb2 qb3 rd-b qb4 hi-z 1cycle cl = 3
FEDS82V48540-01 oki semiconductor ms82v48540 17/44 read to write command interval clk dq 0 1 2 3 4 5 6 7 8 db1 db2 db3 rd-a wt-b dqm db4 hi-z 1cycle bl = 4, cl = 2, 3 cl = 2, 3 clk dq 0 1 2 3 4 5 6 7 8 qa2 qa3 rd-a wt-b dqm db1 db2 hi-z cl = 2 bl = 4, cl = 2, 3 dq qa1 qa2 rd-a wt-b dqm db1 db2 hi-z cl = 3 qa1 hi-z is necessary hi-z is necessary
FEDS82V48540-01 oki semiconductor ms82v48540 18/44 burst termination burst read termination by precharging in read cycle burst read termination by precharging in write cycle note: d5 data will not be written clk cl = 2 rd dq q1 0 1 2 3 4 5 6 7 8 pre cl = 3 rd dq pre q2 q3 q4 q1 q2 q3 q4 hi-z hi-z bl = 2, 4, 8, full act act t rp t rp clk cl = 2 wt dq d1 0 1 2 3 4 5 6 7 8 pre cl = 3 wt dq pre d2 d3 d4 d1 d2 d3 d4 hi-z hi-z bl = 2, 4, 8, full act act d5 t rp t rp d5
FEDS82V48540-01 oki semiconductor ms82v48540 19/44 read burst stop command write burst stop command clk cl = 2 rd dq q2 0 1 2 3 4 5 6 7 8 bst cl = 3 dq q3 q4 q2 q3 q4 hi-z hi-z bl = 2, 4, 8, full q1 q1 clk cl = 2, 3 wt dq d1 0 1 2 3 4 5 6 7 8 bst d2 d3 hi-z bl = 2, 4, 8, full d4
FEDS82V48540-01 oki semiconductor ms82v48540 20/44 auto precharge read with auto precharge write with auto precharge clk rap dq 0 1 2 3 4 5 6 7 8 q1 q2 q3 q4 hi-z bl = 4 cl = 2 dq q1 q2 q3 q4 hi-z cl = 3 rap auto precharge starts auto precharge starts (t ras is satisfied) clk wap dq 0 1 2 3 4 5 6 7 8 d1 d2 d3 d4 hi-z bl = 4 cl = 2 dq d1 d2 d3 d4 hi-z cl = 3 wap auto precharge starts auto precharge starts (t ras is satisfied)
FEDS82V48540-01 oki semiconductor ms82v48540 21/44 electrical characteristics absolute maximum ratings parameter symbol rating unit voltage on power supply pin relative to gnd v cc ?0.5 to 4.6 v voltage on input pin relative to gnd v in , v out ?0.5 to v cc + 0.5 4.6 v short circuit output current i os 50 ma power dissipation p d * 1 w operating temperature t opr 0 to 70 c storage temperature t stg ?55 to 150 c *: ta = 25 c recommended operating conditions (ta = 0 to 70c) parameter symbol min. typ. max. unit v cc 3.0 3.3 3.6 v power supply voltage v ss 0 0 0 v input high voltage v ih 2.0 ? v cc + 0.3 v input low voltage v il ?0.3 ? 0.8 v capacitance (v cc = 3.3 v 0.3 v, ta = 25c, f = 1 mhz) parameter symbol min. max. unit input capacitance (a0 ? a10, ba0, ba1) c in1 ? 5 pf input capacitance (clk, cke, cs , ras , cas , we dqm 0 ? dqm3) c in2 ? 5 pf output capacitance (dq0 ? dq31) c out ? 6 pf
FEDS82V48540-01 oki semiconductor ms82v48540 22/44 dc characteristics test condition ms82v48540-7 ms82v48540-8 parameter symbol cke other min. max. min. max. unit note output high voltage v oh ? i oh = ?2.0 ma 2.4 ? 2.4 ? v output low voltage v ol ? i ol = 2.0 ma ? 0.4 ? 0.4 v input leakage current i li ? ? ?10 10 ?10 10 a output leakage current i lo ? ? ?10 10 ?10 10 a operating current (1 bank) i cc1 cke v ih t ck = t ck min. t rc = t rc min. no burst ? 200 ? 180 ma 1, 2 i cc2p cke v il t ck = t ck min. ? 2 ? 2 ma precharge standby current in power down mode i cc2ps cke v il clk v il t ck = ? 2 ? 2 ma i cc2n cke v ih cs v ih t ck = t ck min. ? 40 ? 40 ma precharge standby current in non power down mode i cc2ns cke v ih clk v il t ck = ? 20 ? 20 ma i cc3p cke v il t ck = t ck min. ? 3 ? 3 ma active standby current in power down mode i cc3ps cke v il clk v il t ck = ? 3 ? 3 ma i cc3n cke v ih cs v ih t ck = t ck min. ? 50 ? 50 ma active standby current in non power down mode i cc3ns cke v ih clk v il t ck = ? 30 ? 30 ma operating current (burst mode) i cc4 cke v ih t ck = t ck min. ? 240 ? 200 ma 1, 2 refresh current i cc5 cke v ih t rc t rc min. ? 200 ? 180 ma self refresh current i cc6 cke 0.2v ? ? 3 ? 3 ma notes 1. the maximum value of power suppl y current is obtained with the output open. 2. address and data are changed only one time during one cycle.
FEDS82V48540-01 oki semiconductor ms82v48540 23/44 ac characteristics test conditions ? ac measurements assume t t = 1 ns. ? reference level for measuring timing of input signals is 1.4 v. transition times are measured between v ih and v il . ? if t t is longer than 1 ns, reference level for measuring timing of input signals is v ih (min.) and v il (max) . ? an access time is measured at 1.4 v. ? input levels at the ac testing are 2.4 v/0.4 v. t ck t ch t cl t setup t hold t oh clk input output 2.4 v 1.4 v 0.4 v 2.4 v 1.4 v 0.4 v 1.4 v 1.4 v t ac
FEDS82V48540-01 oki semiconductor ms82v48540 24/44 synchronous characteristics ms82v48540-7 ms82v48540-8 parameter symbol min. max. min. max. unit note cas latency = 3 t ck3 7 ? 8 ? ns clock cycle time cas latency = 2 t ck2 12 ? 12 ? ns cas latency = 3 t ac3 ? 5 ? 6 ns 1 access time from clk cas latency = 2 t ac2 ? 8 ? 8 ns 1 clk high level width t ch 2.5 ? 3 ? ns clk low level width t cl 2.5 ? 3 ? ns data-out hold time t oh 2 ? 2 ? ns data-out low-impedance time t lz 0 ? 0 ? ns data-out high-impedance time t hz ? 5 ? 6 ns data-in setup time t ds 2 ? 2 ? ns data-in hold time t dh 1 ? 1 ? ns address setup time t as 2 ? 2 ? ns address hold time t ah 1 ? 1 ? ns cke setup time t cks 2 ? 2 ? ns cke hold time t ckh 1 ? 1 ? ns command ( cs , ras , cas , we , dqm) setup time t cms 2 ? 2 ? ns command ( cs , ras , cas , we , dqm) hold time t cmh 1 ? 1 ? ns note 1. output load. z = 50 ? 1.4 v output 30 pf 50 ?
FEDS82V48540-01 oki semiconductor ms82v48540 25/44 asynchronous characteristics parameter ms82v48540-7 ms82v48540-8 symbol min. max. min. max. unit note ref to ref/act/sact command period t rc 63 ? 72 ? ns act to pre command period t ras 42 120k 48 120k ns sact to pre command period t rass 6 ? 6 ? clk pre to act command period t rp 21 ? 24 ? ns pre-all (special page) to sact command period t rps 9 ? 9 ? clk delay time act/sact to read/write command t rcd 21 ? 24 ? ns act (0) to act (1) command period t rrd 14 ? 16 ? ns read/write to read/write command period t ccd 7 ? 8 ? ns data-in to pre command period t dpl 7 ? 8 ? ns data output to write command input time t owd 14 ? 16 ? ns mode register set cycle time t rsc 14 ? 16 ? ns transition time t t 1 30 1 30 ns refresh time t ref ? 64 ? 64 ms
FEDS82V48540-01 oki semiconductor ms82v48540 26/44 timing waveform read/write cycle (bl = 2, cl = 3) clk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cke cs cas we ba0 add a10 /ap dqm 0 - 3 dq t ck t ch t cl t cms t cmh t cks t as t ah raa t cms t cmh t ac t oh t hz t lz t ds t dh caa raa cab dab1 dab2 rda rda qaa1 qaa2 t ckh hi-z t rcd t ras t rc t dpl t rp act-a rd-a wt-a pre-a act-d ras t owd ba1
FEDS82V48540-01 oki semiconductor ms82v48540 27/44 special read cycle (bl = special page, cl = 3) raa caa raa q a a 4 rda rda hi-z t rcd t rass t rps sact-a srd-a special read start pre-all sact-d l h qn-1 qn qn+1 qn+2 q a a 1 q a a 2 q a a3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke cs cas we ba0 add a10 /ap dqm 0 - 3 dq ras ba1
FEDS82V48540-01 oki semiconductor ms82v48540 28/44 special write cycle (bl = special page, cl = 3) raa caa raa daa4 rba rba hi-z t rcd t rass t rps sact-a swt-a special write start pre-all sact-b l h daa5 dn-2 dn-1 dn daa1 daa2 daa3 t dpl 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke cs cas we ba0 add a10 /ap dqm 0 - 3 dq ras ba1
FEDS82V48540-01 oki semiconductor ms82v48540 29/44 mode register set hi-z pre-all h mra act t rsc t rp 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke cs cas we ba add a10 /ap dqm 0 - 3 dq ras
FEDS82V48540-01 oki semiconductor ms82v48540 30/44 auto reflesh hi-z t rc pre-all l h ref ref act t rc t rp 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke cs cas we ba add a10 /ap dqm 0 - 3 dq ras
FEDS82V48540-01 oki semiconductor ms82v48540 31/44 self reflesh (entry and exit) hi-z t rc pre-all l h self entry act t rc t rp self exit self entry self exit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke cs cas we ba add a10 /ap dqm 0 - 3 dq ras
FEDS82V48540-01 oki semiconductor ms82v48540 32/44 burst termination by precharging (bl = 8, cl = 3) hi-z act-a l h wt-a pre command termination raa caa raa rab rab pre-a daa1 daa2 qab1 qab2 qab3 qab4 cab rd-a act-a pre-a pre command termination 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke cs cas we ba0 add a10 /ap dqm 0 - 3 dq ras ba1
FEDS82V48540-01 oki semiconductor ms82v48540 33/44 auto precharging (bl = 4, cl = 3) hi-z act-a l h rap-a ap-a raa caa raa rba rba act-b qaa1 qaa2 qaa3 qaa4 dba1 dba2 dba3 dba4 cba ap-b wap-b 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke cs cas we ba0 add a10 /ap dqm 0 - 3 dq ras ba1
FEDS82V48540-01 oki semiconductor ms82v48540 34/44 power down mode and clock suspension (bl = 4, cl = 2) hi-z act-a l pd entry pd exit clock mask start pre-a raa raa caa active standby rd-a qaa2 qaa3 qaa4 clock mask end pd entry pd exit precharge standby t cks qaa1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke cs cas we ba0 add a10 /ap dqm 0 - 3 dq ras ba1
FEDS82V48540-01 oki semiconductor ms82v48540 35/44 clock suspend exit & power down exit 1) clock suspend (= active power down) exit 2) power down (= precharge power down) exit notes: 1. active power down: one or both bank active state. 2. precharge power down: both bank precharge state. 3. nop should be issued. and new command can be issued after 1 clock. clk internal clk command rd cke t cks note 1 clk act cke t cks note 3 nop internal clk command note 2
FEDS82V48540-01 oki semiconductor ms82v48540 36/44 byte read/write operation (by dqm) (bl = 4, cl = 3) dqm1 dq 0 - 7 act-b rba rba cba h dqm0 dq 8 - 15 rd-b cbb byte of dq8-15 not read byte of dq24-31 not read wt-b byte of dq16-23 not write byte of dq0-7 not write byte of dq24-31 not write dqm3 dqm2 dq 16 - 23 dq 24 - 31 byte of dq16-23 not read byte of dq0-7 not read byte of dq8-15 not write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke cs cas we ba0 add a10 /ap ras ba1 qba1 qba3 qba3 qba2 qba2 qba4 dbb3 dbb1 dbb2 dbb3 dbb4 qba1 qba4 qba3 qba2 qba1 qba4 dbb3 dbb1 dbb2 dbb2 dbb4 dbb4 dbb1
FEDS82V48540-01 oki semiconductor ms82v48540 37/44 burst read and single write (bl = 4, cl = 3) hi-z act-b l h rd-b raa caa raa single wt-b qaa1 qaa2 qaa3 qaa4 dbb dbc cbb single wt-b pre-b cbb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke cs cas we ba0 add a10 /ap dqm 0 - 3 dq ras ba1
FEDS82V48540-01 oki semiconductor ms82v48540 38/44 random column read (continuous read of same bank) (bl = 4, cl = 3) act-a raa raa caa qaa1 qaa3 h rd-a qaa2 qab1 qaa4 cab qab2 qac2 qac1 rai rai pre-a act-a l rd-a rd-a cac qac4 qac3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke cs cas we ba0 add a10 /ap dqm 0 - 3 dq ras ba1
FEDS82V48540-01 oki semiconductor ms82v48540 39/44 random column write (continuous writ e of same bank) (bl = 4, cl = 3) act-b rba rba cba dba1 dba3 h wt-b dba2 dbb1 dba4 cbb cbc dbb2 dbc2 dbc1 rbi rbi pre-b act-b l dbc4 dbc3 wt-b wt-b 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke cs cas we ba0 add a10 /ap dqm 0 - 3 dq ras ba1
FEDS82V48540-01 oki semiconductor ms82v48540 40/44 interleaved column read (bl = 4, cl = 3) act-a raa raa caa cba cbb qaa1 qaa3 h rd-a qaa2 qba1 qaa4 cab qba2 qbc2 qbb1 pre-b pre-a rba rba qab2 qab1 act-b rd-b t rcd t rrd l qab4 qab3 rd-a rd-b 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke cs cas we ba0 add a10 /ap dqm 0 - 3 dq ras ba1
FEDS82V48540-01 oki semiconductor ms82v48540 41/44 interleaved column write (bl = 4, cl = 3) act-c rca rca dca1 dca3 h wt-c dca2 dda1 dca4 dda2 ddb2 ddb1 pre-d pre-c dcb2 dcb1 act-d wt-d wt-c t rcd t rrd l cca cda cdb ccb rda rda wt-d dcb4 dcb3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke cs cas we ba0 add a10 /ap dqm 0 - 3 dq ras ba1
FEDS82V48540-01 oki semiconductor ms82v48540 42/44 package dimensions tsop(2)86-p-400-0.50-k mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5m) package weight (g) 0.53 typ. 5 rev. no./last revised 1/jul. 14, 1998 notes for mounting the surface mount type package the surface mount type packages ar e very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform refl ow mounting, contact oki?s respons ible sales person for the product name, package name, pin number, package code a nd desired mounting conditions (reflow method, temperature and times). (unit: mm)
FEDS82V48540-01 oki semiconductor ms82v48540 43/44 revision history page document no. date previous edition current edition description ? ? first edition changed the speed rank indication in ?package? of the features section from ?xx to ?x?. 1 1 changed the device names in the family column in the table of the product family section. 22 22 changed the names of the family devices in the table of the dc characteristics section. 24 24 changed the names of the family devices in the table of the synchronous characteristics section. FEDS82V48540-01 nov. 8, 2002 25 25 changed the names of the family devices in the table of the asynchronous characteristics section.
FEDS82V48540-01 oki semiconductor ms82v48540 44/44 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circu it, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improp er installation, repair, alteration or accident, improp er handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third part y?s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communicati on equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for us e in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and auto motive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2002 oki electric industry co., ltd.

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