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k6610168 rev.1 nov 19, 2004 - 1 - oem manual hard disk drive specifications travelstar c4k60-60/40/30/20 rev.1 models: htc426060g9at00 htc426040g9at00 HTC426030G7AT00 htc426020g7at00 caution for safety read safety descrip tions carefully. read and recommend drive usage c autions to your end user. keep this manual with care. (total 146 pages) h i t a c h i ? 2004, hitachi global storage tec hnologies. all rights reserved.
k6610168 rev.1 nov 19, 2004 - 2 - rev.0: aug 26, 2004 preliminary rev.1: nov 19, 2004
k6610168 rev.1 nov 19, 2004 - 3 - to use this product safely this manual is for the original purc haser of travelstar c4k60-60/ 4030/20 and intendes to provide information about handling, installation, specifications, principles of operation and interface command implementation. to use the product, read safety descriptions below and understand thoroughly. keep this manual with care to insure unlimited use. z general caution for safety the followings are general cautions for safe use of this product. (caution before product use) - please read and follow all instructi ons and cautions described on ?safet y instructions? (page 5) and ?1.2 general caution? (page 12) before attempting to use this product. - follow all instructions and cauti ons indicated throughout this manual and the product. failure to follow these instructions and c autions may cause injury , fire and product damage. z advise your end user of the safety caution read and recommend that your end users read t he caution for drive usage in this manual. z protect yourself the safety instructions in this manual were thor oughly considered, but unexpect ed situations can occur. not only follow the instructions on this manual, but also be careful for t he safety of yourself. z headline of safety caution safety instructions and cautions are indicated as the following headline, wh ich consists a word of ?caution?. the indication and meaning are as follows: caution: this symbol indicates that potential danger may exist which may cause slight or medium grade bodily injury ,if safety instructions are not followed. caution: this symbol indicates that potentia l danger may exist which may cause damage to the pr oduct or to the neighboring property ,if safe ty instructions are not followed. z safety caution in this manual followings are the cautions and c ontents described in this manual. items of indicating caution : - safety instructions page 5 items of indicating caution : - general caution sec. 1.2, page 12 - power supply requirement s sec.3.1, page 15 - data reliability sec. 3.2, page 16 - mounting hdd sec. 4.2.1, page 20 - attention for hdd installa tion sec. 4.2.3, page 22 - packing sec. 5.1, page 24 - handling sec. 5.2, page 25
k6610168 rev.1 nov 19, 2004 - 4 - to use this product safely (continued) z environmental circumstance although this product partially scatters electro-magnetic field into the air, it has been inspected and was installed under electro-magnetic regulations of resident ar eas, such as emc standard en55022 (corresponding to fcc part 15 class b, etc.). howe ver, anything other than this product, such as an interface cable, is excluded. ther efore, the following cases require a system side improvement for the electro-magnetic fi eld regulations. 1) disturbance of operations of other products or equipment in resident area 2) disturbance caused by other produc t, such as cabling, to operations of other products or equipment. only hitachi trained persons shoul d change this product hitachi assu mes no responsibility for products which have been changed by anyone else. z safety regulations this product meets the following safety regulations, but the system side s hould consider the safety of the system with this product. regulations: - ul1950 third edition dated july 28, 1995 - csa c22.2 n0.950-m95 - iec60950 a4: 1996 - en60950 a11: 1992 warranty and limited liability this product is sold with a limited wa rranty and specific remedies are available to the original purchaser in the event the product fails to confor m to the limited warranty. hitachi?s liability may be further limited in accordance with its sales contact. in general, hitachi shall not be responsible for product damages caused by natural di sasters, fire, static discharge, misuse, abuse, neglect, improper handling or installation, unauthorized repair, alteration or accident. in no event will hitachi be liable for loss of data stored on product. hitachi shall not be liable for any special, inci dental or consequential damages, even if informed of the possi bility thereof in advance. please see your sales contract for a complete statement of warranty rights, remedies and limitat ion of liability.
k6610168 rev.1 nov 19, 2004 - 5 - safety instructions 1. the product is not authorized for us e in life support devices or systems or other applicati ons that pose a significant risk of personal injury. 2. since the drive uses glass m edia for the disk platter, opening of metal head disk assembly (hda) may cause bodily injury. warranty void in case of opened hda or any broken hda seals. don?t open the hda or break any hda seals. 3. dropping of the hdd may cause bod ily injury. handle with care. 4. do not hit the interface connecto r pins against other objects. do not make contact with the interface connector pins. contact causes pin dent, electrical discharge distraction or cont act failure. also, pins or hda corners may cause bodily injury. handle with care. 5. observe clause 3.3 ?drive us age condition specificati ons?. since reliabilit y and product life depends on usage conditions, please consult our sales or application engineers. 6. keep usage conditions within specifications (power s upply, environment, etc.). if the conditions are not kept within the specificat ions, failures may occur. 7. hot swapping (power-on swapping) can damage the dr ive. the drive shall be swapped during power off only. 8. electro static discharge (esd) can damage the drive. protect the drive from esd during handling. 9. voltage rise time 5 - 100 ms at power on is requir ed for power supply. the pow er supply voltage must not be under ?0.3v at power off. 10. this product is required over current protection for possible com bustion due to circuit or component failure. secondary over current protection shall be prepared by the system. t he requirement of the current limitation is max. 10 a for the protection. 11. improper insertion of connector or wrong jumper setti ng may cause catastrophic failures. referring to this manual prior to the connector insertion or jumper setting can help to insure correct insertion. 12. if a foreign conductive substance (metallic powder, fluid, etc.) adheres to active metal of the drive (printed pattern, component lead, etc. on pcba), it may cause catastrophic failures. customer should protect the drive from the above condition. 13. the pcba side of the drive should be covered with in sulation sheet if the active metal of host system may contact to the pcba of the drive. if the insulation sheet is not provided for t he possible contact of the live metal, failures may occur. 14. shock can result in permanent damage to the drive and/or loss of data. prevent shocks, which is often incurred by dropping, knocking over, or hitting the drive. 15. to fix the drive, use the size of screws and the torque recommended in this manual. if non-recommended size screws and torque are used, it may cause catastrophic failures. 16. do not press top cover. it may cause catastrophic failures. in case of steel plate installation on hdd cover side, the spacing between hdd cover and steel plate should be kept more than 2 mm. if this spacing is not kept for the steel plate, it may affect load/unload mechanism. 17. do not push the bottom pcba of the dr ive. it may cause catastrophic failures. caution caution
k6610168 rev.1 nov 19, 2004 - 6 - safety instructions (continued) 18. prevent humidity when the drive is packed in a box. 19. use original packages during drive tr ansportation to protect from any damage. (keep some extra packages for the drive transportation) 20. recorded data on the disk may be lost due to a ccidents such as disasters, shock damage during handling or drive failure. to prepare for accident s, back up data. hitachi does not perform data recovery. 21. data may be lost due to unexpected or a ccidental power loss during write operation. note to users while every effort has been made to ensure that the info rmation provided herein is co rrect please feel free to notify us in the event of an error or inconsistency. hitachi makes no representations or warranties with re spect to the contents hereof and specifically disclaims any implied warranties or merchantab ility or fitness for any purpose. further hitachi reserves the right to revise this pub lication and to make changes from time to time in the content hereof without obligat ion to notify any person of such revisions or changes. caution
k6610168 rev.1 nov 19, 2004 - 7 - oem m anual ..................................................................................................................... .............................. 1 to use this product sa fely..................................................................................................... ........................... 2 1.0 gener al........................................................................................................................ ......................... 2 1.1. intr oducti on .............................................................................................................. ............................. 2 1.2. general caut ion........................................................................................................... ......................... 2 2.0 component s ..................................................................................................................... .................... 2 3.0 specificati on summa ry .......................................................................................................... ............... 2 3.1. principal specific ations .................................................................................................. ....................... 2 3.2. environmental specif ications and reliab ility.............................................................................. ........... 2 3.3. drive usage condi tion specif ications ...................................................................................... ............. 2 3.4. load/unload s pecificat ions ................................................................................................ .................. 2 3.4.1. normal load/un load ...................................................................................................... ................ 2 3.4.2. emer gency un load........................................................................................................ ................. 2 3.4.3. required po wer off sequenc e............................................................................................. .......... 2 4.0 installa tion ................................................................................................................... ......................... 2 4.1. installati on direct ion.................................................................................................... .......................... 2 4.2. mount ing hdd .............................................................................................................. ........................ 2 4.2.1. mounting hdd with screws ................................................................................................ ............ 2 4.2.2. single hdd test c ondition ............................................................................................... ............. 2 4.2.3. attention fo r hdd insta llation .......................................................................................... ............... 2 4.3. device address setting (drive 0/drive 1) .................................................................................. ...... 2 4.4. dim ensi ons ................................................................................................................ ........................... 2 5.0 packing and h andlin g........................................................................................................... ................ 2 5.1. pa cking ................................................................................................................... .............................. 2 5.2. h andlin g.................................................................................................................. .............................. 2 6.0 physical in terface ............................................................................................................. .................... 2 6.1. power interface........................................................................................................... .......................... 2 6.2. physical interface ........................................................................................................ ......................... 2 6.2.1. connecto r ...................................................................................................................... ................. 2 6.2.2. connector pin assi gnment................................................................................................ ............. 2 6.2.3. description of the interfac e signal s.................................................................................... ............ 2 7.0 logical inte rface .............................................................................................................. ..................... 2 7.1. i/o r egisters............................................................................................................. ............................ 2 7.1.1. data regi ster........................................................................................................... ........................ 2 7.1.2. erro r regi ster .......................................................................................................... ........................ 2 7.1.3. featur es regi ster....................................................................................................... .................... 2 7.1.4. sector count r egister ................................................................................................... ................. 2 7.1.5. lba low register (s ector number register) ............................................................................... .. 2 7.1.6. lba mid register (cylinder low register) ................................................................................ ..... 2 7.1.7. lba high register (cylinder high register).............................................................................. ..... 2 7.1.8. device /head regi ster .................................................................................................... ................ 2 7.1.9. status regi ster......................................................................................................... ...................... 2
k6610168 rev.1 nov 19, 2004 - 8 - 7.1.10. comm and regi ster ....................................................................................................... ............... 2 7.1.11. alternate status r egister .............................................................................................. ............... 2 7.1.12. device c ontrol r egister ................................................................................................ ............... 2 7.2. general operat ions........................................................................................................ ....................... 2 7.2.1. 48-bit addre ssing featur e set........................................................................................... ............. 2 7.2.2. powe r managem ent ........................................................................................................ ............... 2 7.2.3. smar t feat ure ........................................................................................................... .................. 2 7.2.4. security mode f eature ................................................................................................... ................ 2 7.2.5. protect ed area f eature .................................................................................................. ................ 2 7.2.6. address offset f eature (vendor specific)................................................................................ ...... 2 7.2.7. device configur ation overla y feature .................................................................................... ....... 2 7.2.8. write cache and auto rea llocation....................................................................................... ......... 2 7.3. command protoc ol .......................................................................................................... ..................... 2 7.3.1. pio data in co mmand ..................................................................................................... .............. 2 7.3.2. pio data out co mmand .................................................................................................... ............ 2 7.3.3. dma data in/out command ................................................................................................. ......... 2 7.3.4. non-da ta co mmand ........................................................................................................ .............. 2 7.3.5. comm and bsy ti ming...................................................................................................... ............. 2 7.4. comm and summa ry ........................................................................................................... .................. 2 7.5. command descrip tions...................................................................................................... ................... 2 7.5.1. check powe r mode [98h, e5h]............................................................................................. .......... 2 7.5.2. device configurat ion identify [b 1h, s ub 02h] ............................................................................ ..... 2 7.5.3. device configurati on freeze lock [b 1h, s ub 01h] ......................................................................... 2 7.5.4. device configurat ion restore [b 1h, s ub 00h] ............................................................................. ... 2 7.5.5. device configur ation set [b 1h, s ub 03h] ................................................................................. ...... 2 7.5.6. execute devi ce diagnosti c [90h]......................................................................................... ........... 2 7.5.7. flush cache [e7h]....................................................................................................... ................... 2 7.5.8. flush ca che ext [eah] ................................................................................................... .............. 2 7.5.9. format track [ 50h] (vendor s pecific).................................................................................... ......... 2 7.5.10. identify device [ech].................................................................................................. .................. 2 7.5.11. idle [97h, e3h] ........................................................................................................ ...................... 2 7.5.12. idle immediate [95h,e 1h] / unload imm ediate [e 1h] .................................................................... 2 7.5.13. initialize devi ce paramete rs [91h] ..................................................................................... ........... 2 7.5.14. read buffer [e4h]...................................................................................................... ................... 2 7.5.15. read dm a [c8h, c9h].................................................................................................... .............. 2 7.5.16. read dm a ext [25h] ..................................................................................................... .............. 2 7.5.17. read log ext [2fh]..................................................................................................... ................ 2 7.5.18. read long [22h, 23h]................................................................................................... ................ 2 7.5.19. read mu ltiple [c4h].................................................................................................... .................. 2 7.5.20. read mult iple ext [29h] ................................................................................................ .............. 2 7.5.21. read max a ddress comm and [f 8h] ......................................................................................... ... 2 7.5.22. read max addre ss ext comm and [27h] .................................................................................... 2 7.5.23. read sect ors [20h, 21h]................................................................................................ ............... 2
k6610168 rev.1 nov 19, 2004 - 9 - 7.5.24. read sect ors ext [24h]................................................................................................. .............. 2 7.5.25. read veri fy [40h, 41h]................................................................................................. ................. 2 7.5.26. read verify sectors ext [42h].......................................................................................... ........... 2 7.5.27. recalib rate [1 xh]...................................................................................................... .................... 2 7.5.28. security di sable passw ord [f 6h]........................................................................................ .......... 2 7.5.29. security erase prepar e [f3h] ........................................................................................... ............ 2 7.5.30. security erase unit [f4h] .............................................................................................. ............... 2 7.5.31. security freeze lo ck [f5h] ............................................................................................. ............. 2 7.5.32. security set passwor d [f1h] ............................................................................................ ............ 2 7.5.33. security unlock [f2h] .................................................................................................. ................. 2 7.5.34. seek [7xh]............................................................................................................. ....................... 2 7.5.35. set feat ures [e fh] ..................................................................................................... .................. 2 7.5.36. set max address command [f9h, sub 00h] ................................................................................ 2 7.5.37. set max addr ess ext co mmand [ 37h]...................................................................................... .. 2 7.5.38. set max freeze lo ck command [f9h, sub 04h].......................................................................... 2 7.5.39. set max lock command [f9h, sub 02h].................................................................................... .. 2 7.5.40. set max set passwor d command [f9h, sub 01h] ....................................................................... 2 7.5.41. set max unlock command [f9h, sub 03h] .................................................................................. 2 7.5.42. set mult iple m ode [c 6h] ................................................................................................ ............... 2 7.5.43. sleep [99h,e 6h]........................................................................................................ .................... 2 7.5.44. smart disable oper ations [b0h, sub d9h] ................................................................................ 2 7.5.45. smart enable/disable auto matic off-line [b 0h, sub dbh]......................................................... 2 7.5.46. smart enable/disable attr ibute autosave [b0h, sub d 2h].................................................... 2 7.5.47. smart enable oper ations [b0h, sub d8h] ................................................................................. 2 7.5.48. smart execute off-line immediate [b0h, sub d 4h] ................................................................... 2 7.5.49. smart read log se ctor [b0h, sub d 5h]................................................................................... .2 7.5.50. smart return st atus [b0h, sub da h] ..................................................................................... ... 2 7.5.51. smart save attribut e values [b0h, sub d 3h] ............................................................................ 2 7.5.52. smart write log se ctor [b0h, sub d 6h].................................................................................. .. 2 7.5.53. standby [96h, e2h]..................................................................................................... .................. 2 7.5.54. standby imm ediate [94h, e0h] ........................................................................................... .......... 2 7.5.55. write buffer [e8h] ..................................................................................................... .................... 2 7.5.56. write dm a [cah, cbh] ................................................................................................... .............. 2 7.5.57. write dma ext [35h] .................................................................................................... ............... 2 7.5.58. write dma fua ext [3dh] ................................................................................................ .......... 2 7.5.59. write log ext [3 fh].................................................................................................... ................. 2 7.5.60. write long [32h, 33h] .................................................................................................. ................. 2 7.5.61. write mu ltiple [c5h] ................................................................................................... ................... 2 7.5.62. write mult iple ext [39h]............................................................................................... ................ 2 7.5.63. write multip le fua ext [ceh] ........................................................................................... .......... 2 7.5.64. write se ctors [ 30h, 31h]............................................................................................... ................ 2 7.5.65. write se ctors ext [34h]................................................................................................ ............... 2 8.0 interface si gnal ti ming ........................................................................................................ ................. 2
k6610168 rev.1 nov 19, 2004 - 10 - 8.1. data tr ansfer ti ming ...................................................................................................... ...................... 2 8.2. ultra dma data transfer timing............................................................................................ ............... 2 8.3. power on and hard ware rese t timing ........................................................................................ ........ 2
k6610168 rev.1 nov 19, 2004 - 11 - 1.0 general 1.1. introduction the travelstar c4k60-60/40/30/20 disk drives reach high capacities in a 1.8 type form factor by applying the latest high-density recording technology. capacity product name model name (forma tted) height interface travelstar c4k60-60 htc426060g9at 00 60.011 gb 9.5 mm ata-6(ide) travelstar c4k60-40 htc426040g9at 00 40.007 gb 9.5 mm ata-6(ide) travelstar c4k60-30 htc426030g7at 00 30.005 gb 7.0 mm ata-6(ide) travelstar c4k60-20 htc426020g7at 00 20.003 gb 7.0 mm ata-6(ide) [features] - gmr head - id-less format - me 2 prml read channel - data transfer rate (host-device) -16.6 mb/sec: pio mode-4/multiword dma mode-2 - 100 mb/sec: ultra dma mode-5 (device-buffer) - 18.4 to 34.0 mb/s(60/30gb), 15.9 to 29.7 mb/sec(40/20gb) - cdr (constant density recording) - on-the-fly ecc correction - buffer: 2mb - read-ahead cache/write cache - auto read reassign/auto write reassign - smart - average access time 15 ms - embedded sector servo - fdb(fluid dynamics bearing) motor - rotary actuator - load/unload mechanism - 62grams(60/40gb), 47 grams(30/20gb) - low power consumption: 0.25w at idle mode, 0.08w at standby mode (3.3v operation) - advanced power management(apm) - non-operating shock: 11,760m/s 2 (1200g, 1ms, half-sine wave) - operating shock: 4,900m/s 2 (500g, 2ms, half-sine wave) [identify device information for setup] table 1.1 identify device information (addressing) product name word 1 number of cyl. word 3 number of hd word 6 number of spt word 60 ? 61 * 1 word 100 - 103 total lba htc426060g9at00 16383 *2 16 63 117,210,240 htc426040g9at00 16383 *2 16 63 78,140,160 HTC426030G7AT00 16383 *2 16 63 58,605,120 htc426020g7at00 16383 *2 16 63 39,070,080 * 1 : words 60-61 reflect the total number of user addressable sectors in lba mode. *2 : maximum capacity in chs mode is 8,455mb.
k6610168 rev.1 nov 19, 2004 - 12 - 1.2. general caution adhere to the following cautions. (a) warranty void if metal head disk assembly ( hda) is opened, or any hda seal/label is broken. (b) hot swapping (power on) damages the drive. the drive should be swapped during power off only. (c) shock can result in permanent dam age to the drive and/or loss of data. prevent shocks often incurred by dropping, knocking over, or hitting the drive. (dropping) (knocking over) (hitting) (hitting) figure 1.1 caution prevent shocks caution
k6610168 rev.1 nov 19, 2004 - 13 - 2.0 components travelstar c4k60-60/4030/20 disk drive figure 2.1 overview of travel star c4k60-60/4030/20 (7.0mm height)
k6610168 rev.1 nov 19, 2004 - 14 - 3.0 specification summary 3.1. principal specifications table 3.1 principal specifications specifications no. item travelstar c4k60-60 travelstar c4k60-40 travelstar c4k60-30 travelstar c4k60-20 units model name htc426060g9at00 htc426040g9at00 HTC426030G7AT00 htc426020g7at00 1 capacity per drive (formatted) 60.011 40.007 30.005 20.003 gb capacity per sector 512 bytes disks 2 1 heads 4 4 2 2 2 seek time average 15 *1 ms (nominal full stroke 26 *1 ms value) track to track 3 ms 3 average latency 7.1 ms disk rotational speed 4,200 rpm 4 recording density (max.) 32.8 (832) 28. 1 (713) 32.8 (832) 28.1 (713) mbpm(kbpi) track density 4.65 (118.0) 4.13 (105.0) 4.65 (118.0) 4.13 (105.0) mtpm(ktpi) recording method me 2 prml, id-less format 5 interface ata-6(ide) data transfer rate (disk-buffer) 18.4 - 34. 0 15.9 ? 29.7 18.4 - 34.0 15.9 ? 29.7 mb/sec data transfer rate (host-buffer) max. 16.6 mb/sec (pio mode 4/ multiword dma mode 2) max. 100 (ultra dma mode 5) mb/sec buffer size 2,048 kb 6 power on - ready *2 5 (typical) *3 sec sleep/standby - ready *2 3 (typical) *3 sec 7 dimensions (w h d) 70 9.5 60 70 7.0 60 mm weight (approximate value) 62 47 grams 8 dc power requirements *4 supply voltage - start up (max.) * 5 - idle (ave.) * 6 - active idle (ave.) * 7 - seek (ave.) * 8 - read (ave.) * 9 - write (ave.) * 9 - standby (ave.) - sleep (ave.) 5.0v 5% or 3.3v 5%, ripple noise 100mvp-p 5.0v / 3.3v 2.1 / 1.4 0.38 / 0.25 0.68 / 0.45 1.7 / 1.1 1.5 / 1.0 1.7 / 1.1 0.12 / 0.08 0.11 / 0.07 w
k6610168 rev.1 nov 19, 2004 - 15 - *1 :average time of seek is ca lculated under the following condition. (read/write ratio: read only) average of 10,000 random seeks, volt age 5.0v or 3.3v, temperature 25 c. full stroke time of seek is calc ulated under the following condition. average of 1,000 full stroke seeks, voltage 5.0v or 3.3v, temperature 25 c. this maximum time is not included the seek time by seek retry. *2 :periodically, during start up, the drive may perform a spin up retry operation. when this operation occurs, the start up sound will change slightly and the ready timing will also be altered from typical time. *3 :power on to ready time could take up to 10 se conds in case of spin up retries under certain conditions of the voltage specifications(tabl e 3.1) and environmental s pecifications(table 3.2). *4 :for dc power input, the average current is measured at the connector of the pc ba of this drive and in the nominal condition in which the power volt age and the temperature ar e 5.0v or 3.3v and 25 c, respectively. the dc power input has to be burst free (common mode). the average current may have some tolerance after power-on. the current measurement is recommended at 5 minutes later after power-on. voltage rise time 5 - 100 ms at power on is required for power supply. the power supply voltage must not be under -0.3v at power off. this product is required over current protection for possible combustion due to circuit or component failure. secondary over current protection shall be prepared by the system. the requirement of the curr ent limitation is max. 10 a for the protection. *5 :10ms averaged peak. for more inform ation, refer to section 6.1. *6 :this value is at low power idle mode. the heads are unloaded. *7 :power mode automatically enters to active idle mode after read/write operation. *8 : measured during random seek at t he rate of three seeks per 100 msec. *9 :measured while reading or writing 16 sector s of data located on the same track. caution caution
k6610168 rev.1 nov 19, 2004 - 16 - 3.2. environmental specifications and reliability table 3.2 environmental specification and reliability no. item specification travelstar c4k60-60 travelstar c4k60-40 travelstar c4k60-30 travelstar c4k60-20 model name htc426060g9at00 htc426040g9at00 HTC426030G7AT00 htc426020g7at00 1 ambient *1 operational 5 to 60 c temperature non-operational -40 to 70 c temperature gradient max. 20 c /hour 2 relative humidity operational 5 to 90 % non-operational 5 to 95 % maximum wet operational 29 c (without condensation) bulb non-operational 40 c (without condensation) *2 3 vibration operational 1.0mm p-p or less (5 - 22hz) 9.8 m/s 2 (1.0g) or less m/s 2 (22 ? 500hz) non-operational 5mm p-p or less (5 ? 22hz) 49m/s 2 (5g) or less (22 ? 500hz) 4 shock *5 operational 4,900m/s 2 (500g) or less (2 ms, half sine wave) non-operational 11,760m/s 2 (1200g) or less (1 ms, half sine wave) 5 atmospheric condition without corrosive vapors, salt or organic-metal compound. (ex. organic silicon, organic tin) 6 acoustic-noise *3 idle(typ.) 1.8bels 1.6 bels seek(typ.) 2.4 bels 2.2 bels 7 height operational 3,000m or less (altitude) non-operational 12,000m or less height gradient max. 300m/min.(3.1kpa/min.) 8 data reliability (with retries and ecc) less than 1 non-recoverable error in 10 e 13 bits read *4 9 external magnetic field 1,500 micro tesla (dc) or less *1 : ambient temperature should be meas ured at point 10 mm away from t he nameplate of the drive. if the maximum operational ambient tem perature cannot be measured at a point 10 mm away from the nameplate, a substitution method is stipulated in the table below. ambient temperature temperature at cover (point a) 60 c 65 c 5 c 5 c *2 : in case of the maximum wet bulb 40 c , the drive should be packed in hdd package box with esd bag and desiccant. please see specificat ion 5.1 packing for reference. if the drive is not packed in the hdd package box with esd bag and desiccant, maximum wet bulb 29 c is applied. *3 : 3.0 bels are the maximum sound power levels with a-weighted. this value is specified at product measurement point ( point a )
k6610168 rev.1 nov 19, 2004 - 17 - shipment, except during power on, load, unload or pow er down. clicking noise of magnet latch operation occurs at loading and unloading operati on of the magnetic heads. also, t he clicking noise of the magnet latch occurs at emergency unloading operations. measurements are to be taken in accordance with iso 7779. at seek mode, randomly select a cylinder and seek operation of the actuator with a delay time at each cylinder. seek rate for the driv e can be calculated as shown below. seek rate = 0.4/(average access time + average la tency) = 0.4/(average access time + 60/rpm/2) *4 : data reliability is not to be used to compromise the host system data backup. *5 :these shock specifications ar e defined for each axis. for non-oper ating rotational shock, the specification is 50k radian/sec 2 or less (2 ms, half sine wave). 3.3. drive usage c ondition specifications the drive is designed for usage under the following conditions. since reliab ility and product life depends on usage conditions, please cons ult our sales representatives or app lication engineers if the drive may be operated outside t hese conditions. -power on hours (poh) : less than 333 hours/month poh includes sleep and standby modes. the heads are unloaded during power off, standby, sleep or low power idle modes. the spindle motor is stopped during standby and sleep modes. this drive is not designed or intended to be used for 24/7 applications. conti nuous motor spinning should be limited to 48 hours period. in case of continuous poh condition, the transition to standby mode or sleep mode must occur at least once every 48 hours period. -operating (seek/write : less than 20% of poh read operations) -motor start/stop count : max. 300,000 times. this number includes standby, sleep and power-on/off count. -environment : with in environmental specificat ions given in table 3.2 -power requirement : within dc power require ment specifications given in table 3.1 ?principal specifications? -drive grounding : drive frame shoul d be grounded to system ground with four screws electrically. grounding noise should be less than 500mvp-p. the grounding noise should be measured between electrical ground and system frame ground without the drive. grounding ac current (measuring between two of side mounting holes) should be less than 50 map-p (frequency range: less than 12mhz). the grounding current should be measured through 50 ohm resistor. -external magnetic field : within specifications gi ven in table 3.2 -mounting : mount with recommended screws and regular torque. -physical/electrical interface: ata-6 -handling : do not add electrical static disc harge, and vibration and shock to the drive. do not press top cove r and bottom pcba surface of the drive. caution
k6610168 rev.1 nov 19, 2004 - 18 - 3.4. load/unload specifications load /unload is a mechanism to load/ unload the heads on the disk surfaces. 3.4.1. normal load/unload normal load/unload operations are limited to maximum 600,000 times during hdd life. the normal unload operation is performed by the following commands. - standby - standby immediate - sleep also, the normal unload is automatically performed by control software, during idle mode. the above normal unload time does not include an emergency unload as explained in sec. 3.4.2. 3.4.2. emergency unload the emergency unload is occurred by unexpected power down, and is limited to maximum 20,000 times during hdd life. since normal unload c an not be performed by the software control after power off, the heads are unloaded by a hardware control. the maximum number of em ergency unload is defined separately. 3.4.3. required power off sequence to operate the load/unload normally, t he following bios sequence is requir ed by host system before power off. [sequence #1]: execute one of following commands. - standby - standby immediate - sleep note: such as soft reset, flush cache comm and or check power mode command does not unload the heads. [sequence #2]: check the status register, and wait the command complete. note: the head is unload by the sequence #1 command, and the command completion normally takes about 1sec. considering the e rror retries, bios timer should be set to over 30 sec by the host side. [sequence #3]: power off the drive above sequence is required for t he host system at power off, suspend and hibernation operations.
k6610168 rev.1 nov 19, 2004 - 19 - 4.0 installation 4.1. installation direction the travelstar c4k60-60/4030/20 can be installed in the 6 di rections as shown below. figure 4.1 installation
k6610168 rev.1 nov 19, 2004 - 20 - 4.2. mounting hdd 4.2.1. mounting hdd with screws mount the hdd with the screws according to the following instruction to optimize the performance. (a) mount the hdd with m2.5 screws. take care not to add any distorting forc e to the hdd when mounting. using 4 screws holes, secure the hdd. (b) use screws with the following spec ifications when t he hdd is mounted. i) m2.5 (screw engagement of 2.8mm max. however, do not use both bottom and side screw hole at the same position simultaneously.) ii) the torque for fixing the screws is 2.5 0.5kgcm(2.2 0.4 lb. inch) (c) consider an appropriate cooling to keep the te mperature of center of hdd top cover less than 65 c. (d) the inertia of the chassis around the z-axis of the grav ity center of the devic e must be more than 3 x 10 -4 kg m 2 . note) in case of general sub-notebook pc(weight: 1.7k g), the inertia of the c hassis around the z-axis of the gravity center of the device is greater than 100 x 10 -4 kg m 2 . therefore, the required inertia level has no problem with the general electronic equipment. figure 4.2 mounting the hdd caution figure 4-2 mounting the hdd 4-m2.5 0.45 chassis hdd 0.2 (unit:mm)
k6610168 rev.1 nov 19, 2004 - 21 - (unit: mm) (80) (10) (70) hdd axis direction axis direction weight: (m=0.42kg, i=4.2 10 -6 kgm 2 ) abs-sheet: (t=5mm) 4.2.2. single hdd test condition to optimize the performanc e, keep the following instructions. 1) for the single hdd test, hdd should be placed on an abs-sheet. hdd should be place with no movement by external force min. 0.25n for x axis and y-axis directions. 2) don?t place hdd on a soft sponge sheet or hard surface at hdd tes t. if the hdd is placed on the soft sponge sheet or slippery hard desk surface, the hdd has unstable conditions such as hdd self-vibration at seek operations or spi ndle motor rotation. it may c ause performance reduction or some errors. also, hdd floating by tension of i/f cabling may cause the similar symptom. the hdd should be placed without any floating. don?t test the hdd under t hese unstable conditions. 3) if the hdd cannot be fixed by the required holdi ng torque above item 1), put a body weight on the hdd as shown in figure 4-3. the body wei ght is provided for preventi ng the hdd movement or hdd floating by tension of i/f cabling. figure 4.3 single hdd test condition
k6610168 rev.1 nov 19, 2004 - 22 - 4.2.3. attention for hdd installation (1) in case of steel plate installa tion on hdd cover side, the spacing between hdd cover and steel plate should be kept more than 2 mm. if this spacing is not kept for the steel plate, it may affect load/unload mechanism. (2) the pcba side of the drive should be cover ed with insulation sheet if the active metal of host system may contact to t he pcba of the drive. if the insulation sheet is not provided for the possible contact of the live metal, failures may occur. (3) do not push the bottom pcba. it may cause catastrophic failures. 4.3. device address setting (drive 0/drive 1) when the device is connected to the host bus, device address se tting is necessary to configure a device as drive 0 or drive 1. the device address setting is established between drives on the interface connector by usi ng jumper 0-2 (pin # a, b, d) the drive 0 is assigned to device address 0, and the drive 1 is assigned to device address 1. caution steel plate pcba insulation sheet more than 2mm (recommended type of jumper socket) vender: iriso electronics co., ltd. vender part number: 9721hj-gf o - - - - - - - - o o o o o - - - - - - - - o o o o 43 5 3 1 c a 44 6 4 2 d b o - - - - - - - - o o o o o - - - - - - - - o o o o 43 5 3 1 c a 44 6 4 2 d b o - - - - - - - - o o o o o - - - - - - - - o o o o 43 5 3 1 c a 44 6 4 2 d b 1) drive 0 (or single) 2) drive 1 3) csel selection if all of pins a,b, d are open, the drive is drive 0(or single). if jumper position a-b is used, the drive is drive 1. if jumper position b-d is used, drive 0 or drive 1 setting is determined by the condition of csel signal (pin# 28).
k6610168 rev.1 nov 19, 2004 - 23 - 4.4. dimensions figure 4.4 dimensions (unit : mm)
k6610168 rev.1 nov 19, 2004 - 24 - 5.0 packing and handling 5.1. packing when you package the device, clean it and execute the fo llowing procedures to prevent humidity and handling damage and c ontamination. (1) pack the device in an esd protective bag with desiccant. (2) use the original hitachi cardboard box and the cushioning materials or equivalent cushioning structures to surround the above bag. (3) never stack or package drives next to each ot her with at the proper cushion material separating them. (4) indicate which side is ups ide or downside on the exterior of the package box and attach notes requesting careful treatment and prev enting the box from bei ng turned upside down. (5) prevent excessive pressure from being app lied on the top and bottom of the drive(top cover and pcba side) when packing, unpacking, and transporting. (6) remember, mishandling of a dr ive can void the drive?s warranty. (7) packing materials, i.e. esd protective bag, ca rdboard box, cushion, etc., s hould not contain corrosive vapors, salt or organic-metal compound. (ex. organic silicon, organic tin) prevent humidity when the drive is packed in a box. caution caution
k6610168 rev.1 nov 19, 2004 - 25 - 5.2. handling mount the hdd with the screws according to the following instructi ons to optimize the performance. it is necessary to prevent vibrati on, shock, and static electricity to the drive because it will damage the precision parts. in particular, prev ent vibration or shock generated by dr opping, knocking over, or hitting the drive. also, avoid touching the el ectrical components directly, which can discharge electrostatic energy and damage the drive. (dropping) (knocking over) (hitting) (hitting) figure 5.1 caution
k6610168 rev.1 nov 19, 2004 - 26 - 6.0 physical interface 6.1. power interface figures 6.1 shows typical power curr ent transitions after turning on the power. supply voltage : 3.3v supply voltage : 5.0v figure 6.1 power current transition 0.1sec/div 0.1a/div 0.1sec/div 0.1a/div
k6610168 rev.1 nov 19, 2004 - 27 - 6.2. physical interface 6.2.1. connector figure 6.2 connector location table 6.1 recommended socket connector drive interface connector recommended socket connector ddk : kks-pd50a-r23-fg or equivalent ddk : kks-rts44-342n or equivalent pins removed(key) pin1 pin20 removed(key) pin44
k6610168 rev.1 nov 19, 2004 - 28 - 6.2.2. connector pin assignment jumper0 jumper2 key(removed) dd7 reset- dd6 dd5 dd4 dd3 dd2 dd1 dd0 gnd dmarq diow- dior- iordy dmack- da1 da0 cs0- dasp- 3.3 / 5vdc(logic) gnd(logic) a c e 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 b d f 2 4 6 8 10 12 14 18 16 20 22 24 28 32 26 30 34 36 38 40 42 44 jumper1 jumper3 key(removed) gnd dd8 dd9 dd10 dd11 dd12 dd13 dd14 dd15 key(removed) gnd gnd gnd csel gnd iocs16- pdiag- da2 cs1- gnd(motor) 3.3 / 5vdc(motor) reserved intrq pcb
k6610168 rev.1 nov 19, 2004 - 29 - 6.2.3. description of the interface signals the interface is an ata(ide) interface. reserv ed pins should be left unconnec ted. the signal names and the pin numbers are shown in table 6.2. table 6.2 shows signal definitions. "i" of i/o type represents an input signal from t he device and "o" represents an output signal from the device. table 6.2 signal list(1/3) signal name pin i/o type description reset- 1 i this is a reset signal out put from the host system and to be used for interface logic circuit. dd0-dd15 3-18 i/o this is a 16-bit bi-dir ectional data bus. the lower 8 bits are used for register access other than data register. diow- 23 i the rising edge of this writ e strobe signal clocks data from the host data bus into a r egister on the device. stop *1 assertion of this signal by the host during an ultra dma burst signals the termination of the ultra dma burst. dior- 25 i activating this read strobe signal enables data from a register on the device to be clocked ont o the host data bus. the rising edge of this signal latc hes data at the host. hdmardy- *1 this signal is a flow control signal for ultra dma read. host asserts this signal, and indica tes that the host is ready to receive ultra dma read data . hstrobe *1 this signal is write data st robe signal from the host for an ultra dma write. both the rising and falling edge latch the data from dd(15:0) into the device. iordy 27 o this signal is used to tem porarily stop the host register access (read or write) when the device is not ready to respond to a data transfer request. ddmardy- *1 this signal is a flow control signal for ultra dma write. device asserts this signal, and indicates that the device is ready to receive ultra dma write data . dstrobe *1 this signal is the data in st robe signal from the device for an ultra dma read. both the rising and falling edge latch the data from dd(15:0) into the host. *1 : signal name in ultra dma mode
k6610168 rev.1 nov 19, 2004 - 30 - table 6.2 signal list(2/3) signal name pin i/o type description csel 28 i this signal is used to conf igure a device as either drive 0 or drive1 when csel mode is selected. this signal is pulled up inside the drive. intrq 31 o this is an interrupt signal for the host system. this signal is asserted by a selected device when the nien bit in the device control register is "0". in other cases, this signal should be a high impedance state. iocs16- 32 o this signal indicates to the host that the 16- bit data port has been addressed and a 16-bit word can be r ead or written to the device. da0-2 33,35,36 i this is a register address signal from the host system. pdiag-:cblid- *2 34 i/o the pdiag- signal is asserted by device 1 to indicate to device 0 that it has completed diagnostics. this signal is pulled up inside the device. the host may sample cblid- after a power-on or hardware reset in order to detect the presence or absence of an 80- conductor cable assembly by performing the following steps: a) the host shall wait until the power on or hardware reset sequence is complete for a ll devices on the cable; b) if device 1 is present, the hos t should issue identify device or identify packet device and use the returned data to determine that device 1 is comp liant with ata-3 or subsequent standards. any device compliant with ata-3 or subsequent standards releases pdiag- no later than after the first command following a power on or hardware reset sequence. if the host detects that cblid- is connected to ground, an 80- conductor cable assembly is inst alled in the system. if the host detects that this signal is not connected to ground, an 80-conductor cable assembly is not installed in the system. cs0- 37 i this device chip selection signal is used to select the command block registers from the host system. cs1- 38 i this device chip selection signal is used to select the control block registers from the host system. *2 : pdiag-:cblid- (passed diagnostics: cable assembly type identifier
k6610168 rev.1 nov 19, 2004 - 31 - table 6.2 signal list(3/3) signal name pin i/o type description dasp- 39 i/o this signal indicates that a devic e is active or that drive 1 is present when the power is turned on. upon receipt of a command from t he host, the device asserts this signal. at command completion, the device de-asserts this signal. dmarq 21 o the device shall assert th is signal, used for dma data transfers between host and device, when it is ready to transfer data. dmack- 29 i the host in response to dm arq to either acknowledge that data has been accepted, or t hat data is available shall use this signal. jumper0,1,2 pin-a,b,d - see sec. 4.3 ? drive address setting (drive 0/drive 1)? for the detail. the i/o signal levels are as follows. (1) input signal high level + 2.0v to vcc + 0.5v low level ? 0.5v to + 0.8v (2) output signal high level + 2.4v to + 5.25v or an open circuit low level + 0.4v or less (iol=2ma), + 0.5v or less (iol=12ma) note) the i/f cable should be no longer than 50cm(20 inches) including the ci rcuit pattern length in the host system. if the cable length is not within this specification, it may cause factional degradat ions or some errors.
k6610168 rev.1 nov 19, 2004 - 32 - 7.0 logical interface 7.1. i/o registers communication between the host sy stem and the device is done thr ough i/o registers. the command block registers are used for sending commands to t he device or posting device status. the control block registers are used for controlling the device or posti ng device status. table 7.1 register list addresses functions cs0- cs1- da2 da1 da0 read(dior-) write(diow-) command block registers 0 1 0 0 0 data data 0 1 0 0 1 error features 0 1 0 1 0 sector count sector count 0 1 0 1 1 lba low (sector number) lba low (sector number) 0 1 1 0 0 lba mid (cylinder low) lba mid (cylinder low) 0 1 1 0 1 lba high (cylinder high) lba high (cylinder high) 0 1 1 1 0 device/head device/head 0 1 1 1 1 status command control block registers 1 0 1 1 0 alt. status device control invalid or not used 0 0 invalid address 0 1 data bus high impedance (not used) 1 0 0 data bus high impedance (not used) 1 0 1 0 data bus high impedance (not used) '0' is low signal level. '1' is high signal level. 7.1.1. data register a 16-bit register to be used for transferring dat a blocks between the hdd's data buffer and the host.
k6610168 rev.1 nov 19, 2004 - 33 - 7.1.2. error register this register stores device st atus when the last command has been completed or diagnostic codes when a self-diagnostic process has been completed. t he contents of this register are valid when the error bit (err) is set in the status register. the contents of this register are diagnostic codes when the device has just completed a self-diagnostic process requested when turning on the power or resetting. bit 7 6 5 4 3 2 1 0 name icrc unc 0 idnf 0 abrt 0 amnf ? amnf(address mark not found): this bit indicates that the device is unable to execute smart command due to a invalid data structure. ? abrt(aborted command): this bit indicates that execution of a command is interrupted due to a device error(e.g. not ready and write fault) or an invalid command code. ? idnf (id not found): this bit indicates that an id field of the requested sect or is not found. ? unc(uncorrectable data error): this bit indicates that an uncorrectable error or an data address mark not found has occurred. ? icrc(interface crc error): this bit indicates that an interface crc error was occurred. this bit is not applied for multiword dma transfers. 7.1.3. features register by combining with the set features command, this register is used for enabling or disabling each feature. 7.1.4. sector count register the register contains the number of sectors of data requested to be tr ansferred on a read or write operation between the host and the device. if val ue in the register is set to 0, a count of 256 sectors in 28-bit addressing or 65,536 sectors in 48- bit addressing is specified. when a command has been completed and the value of this register is "0", it r epresents that the command has been executed successfully. if the command has not been executed successfully, th is register indicates the number of the sectors yet to be processed. this definition cannot be applied to all commands. for more information on commands, refer to the corresponding sections.
k6610168 rev.1 nov 19, 2004 - 34 - 7.1.5. lba low register (sector number register) this register in chs mode contains the starting sector number for any disk data access. this number may be from 1 to the maximum number of sectors per tra ck. in lba mode and 28-bit addressing, the register contains bits 7-0 of the lba addre ss. when 48-bit addressing commands are used, the most recently written content contains "lba bits 7-0", and the previous content c ontains lba bits 31-24. the contents of the register are defined otherwise on some commands. these definitions ar e given in the command descriptions. 7.1.6. lba mid register (cylinder low register) this register in chs mode contains the lower 8 bits of the starting cy linder address for any disk access. in lba mode and 28-bit addressing, the register cont ains bits 15-8 of the lba address. when 48-bit addressing commands are used, the mo st recently written content c ontains "lba bits 15-8", and the previous content contains lba bits 39-32. the contents of the regi ster are defined otherwise on some commands. these definitions are given in the command descriptions. 7.1.7. lba high register (cylinder high register) this register in chs mode contains the higher 8 bits of the starting cylinder address for any disk access. in lba mode and 28-bit addressing, the register cont ains bits 23-16 of the lba address. when 48-bit addressing commands are used, the mo st recently written content c ontains "lba bits 23-16", and the previous content contains lba bits 47-40. the contents of the register are defined otherwise on some commands. these definitions are given in the command descriptions. 7.1.8. device/head register this register has the binary coded address of device and head selected. the head numbers begins with "0". bit 7 6 5 4 3 2 1 0 name - l - drv hs3 hs2 hs1 hs0 ? bits hs3 to hs0 are head addresses to be select ed. hs3 is the highest bit. the address of the currently selected head is displayed in this register when a command is completed. in case of lba mode and 28-bit addressing mode, t hese bits hs3 to hs0 are applied to lba bits 27 - 24. ? drv is a device selection bi t. 0=device 0, 1=device 1 ? l is the sector address mode select: 0=chs mode, 1= lba mode (28-bit addressing or 48-bit addressing)
k6610168 rev.1 nov 19, 2004 - 35 - 7.1.9. status register the current device status is reflec ted in this register. the contents are updated at the completion of each command. if bsy=1, no other bits in this register ar e valid. when bsy is cleared, the other bits in this register is valid within 400 ns. if the host reads this r egister when an interrupt is pending, it is considered to be the interrupt acknowledge, and t he pending interrupt is then cleared. bit 7 6 5 4 3 2 1 0 name bsy drdy dwf dsc drq corr idx err ? err (error): this bit indicates that an error occurs during the execution of a command. for more information, refer to t he description of the error register. ? idx (index): this bit is set once per disk revolution. ? corr (corrected data): this bit reports always "1" ? drq (data request): this bit indicates that the device is ready to transfer data between t he host and the device. ? dsc (device seek complete): this bit indicates that the device head is located on the specified track. if an error has occurred, the value of this bit is not changed until the host reads the status register. ? dfw (device write fault): this bit indicates that an error has occurred during a write operation. if an error has occurred, the value of this bit is not changed until the host reads the status register. ? drdy (device ready): this bit indicates that the device is ready to respond any command. if an error has occurred, the value of this bit is not changed unt il the host reads the status regist er. this bit is cleared when the power is turned on and then kept cleared until t he device gets ready to accept any command. ? bsy (busy): this bit is specified when the device accesses the command block registers. when bsy is 1,the host cannot access the command block registers. if the command block registers are read when bsy is "1", all contents of the status register are returned.
k6610168 rev.1 nov 19, 2004 - 36 - 7.1.10. command register the command code is sent to this register . after it is written, execution begins. 7.1.11. alternate status register the information in this register is a dup licate of that in t he status register. reading this register will not clear the interrupt. 7.1.12. device control register bit 7 6 5 4 3 2 1 0 name hob - - - - srst nien '0' ? hob (high order byte): this bit is defined by 48-bit addressing feature: hob = 1: the host can read the pr evious content of the featur es, sector count, lba low, lba mid, and lba high registers. hob = 0: the host can read the most recently written content of the above registers. the device clears hob bit to zero by a write to any command block register. ? nien(interrupt enable): if the device is selected when nien is 0, the in trq signal is enabled. when nien is 1 or when the device is not selected, the intrq signal is in a high impedance state. ? srst (software reset): when this bit is set, the device is reset. when this bit is cleared, the device exits from the reset state. when two devices are c onnected through one line in the daisy chain mode, they are reset simultaneously.
k6610168 rev.1 nov 19, 2004 - 37 - 7.2. general operations 7.2.1. 48-bit addressing feature set the 48-bit addressing feature set allows devic e with capacities up to 281,474,976,710.655 sectors (144,115,188,075,855,360 bytes). in additi on, the number of sectors that may be transferred by a single command are increased by increasing the allowable sect or count to 16-bits. commands unique to the 48-bit address feature set are: ? flush cache ext ? read sectors ext, read multiple ext, read verify sectors ext, read dma ext ? read native max address ext ? set max address ext ? write dma fua ext, write multiple fua ext ? write sector ext, write multiple ext, write dma ext ? read log ext, write log ext the 48-bit address feature operates in lba only. device also implements commands set using 28-bit addressing. 28-bit and 48-bit commands may be intermixed. in the device, the features regi ster, the sector count register, the lba low register, the lba mid register, and the lba high register are each a two by te deep fifo. each time one of these registers is written, the new content wri tten is placed into the ?most recently written? location and the previous content of the register is moved to ?p revious content? location. the host may read the ?previous cont ent? of the sector count, lba low, lba mid, and lba high registers by first setting the high order bit (hob, bit 7) of the device control register to one and then reading the desired register. if hob (bit 7) in the device control register is cleared to zero the host reads the ?most recently written? content when the register is read. a write to any command block register causes the device to clear the hob bit to zero in the device control r egister. the ?most recently wr itten? content always gets written by a register write regardl ess of the state of hob (bit 7) in the device control register. support of the 48-bit address feature set is indica ted in the identify devi ce command response bit 10 word 83. in addition, the maximum user lba addr ess accessible by 48-bit addressable commands is contained in identify device response words 100 through 103. when the 48-bit address feature set is implemented, the native maximum address is the value returned by a read native max address ext command. if the nat ive maximum address is equal to or less than 268,435,455, a read native max address command retu rns the native maximum address. if the native maximum address is greater than 268,435,455, a r ead native max address command returns a value of 268,435,455.
k6610168 rev.1 nov 19, 2004 - 38 - 7.2.2. power management supported commands and functions: ? idle command, idle immediata command ? sleep command ? standby command, standby immediate command ? advanced power management (apm) ? standby timer 7.2.2.1. low power consumption modes the drive supports the following low power consumption modes: - active mode: the spindle motor is rotated. seek and read/write operations are activated. - active idle mode: heads are loaded, and kept on outer cylinder. - low power idle mode: heads are unloaded outside of the disk platters and t he spindle motor is rotating. this mode is lower power mode than active idle mode. - standby mode: state of ready to receive commands. state of ready to receive commands, but the spindle motor is stopped. if the device receive a command with seek operation, the spindle mo tor is rotated and the command is executed. - sleep mode: this mode is the lowest power mode. the spindl e motor is stopped. the dev ice can not receive the command except hardware reset and software reset. standby, standby immediate and sl eep commands are executed with the following process: - wait write command completion - unload heads - clear bsy bit and enable intrq signal - stop the spindle motor - move to a low power mode 7.2.2.2. standby timer standby timer is provided for automat ic power saving control. the dev ice automatically moves to the standby mode if the host does not iss ue a command within the timer peri od. the standby timer is disabled at power-on. the standby timer value is changeable using idle and standby commands. the timer can be set up to 30 minutes.
k6610168 rev.1 nov 19, 2004 - 39 - 7.2.2.3. advanced power management the host can select the power saving control patte rn by advanced power m anagement (apm). the device performs an intelligent power saving contro l based on the selected pattern by host. using set feature command and sector count register can set the apm operation mode. the sector count value is related to the performance level and the power c onsumption level. if the sect or counter value is set to 01h, the power consumption is ge tting better, but the performance is getting worse. if the large sector count register is set to feh, t he performance is getting better sacrif icing the power c onsumption. the device has five levels of apm operation mode (apm mode 0,1,2,3 and 4) depending on the sector counter values from 01h to feh. using the following command, t he apm control can be set t he mode and reset the mode. - set feature command, enable adv anced power management sub-command. (command code = efh, features = 05h) - set feature command, disable ad vanced power management sub-command. (command code = efh, features = 85h) the enable advanced power managem ent sub-command enables the apm operation set by the sector count register. the disable ad vanced power management sub-command disables the apm operation. if the apm operation is disabled, the device performs apm mode 0. table 7.2 low power consum ption mode transition time operation mode apm value *1 operation apm mode 0 c0h - feh move to low power idle mode apm mode 1 a0h ? bfh move to low power idle mode apm mode 2 80h ? 9fh move to low power idle mode (power on default) apm mode 3 20h ? 7fh move to standby mode *2 apm mode 4 01h ? 1fh *1 : this value is set by sector count register of enable advanced power management sub-command. if non-defined values 00h and ffh are set, t he device returns aborted command. *2 : apm function does not affect on the standby ti mer value. the standby timer and the standby mode transition control of apm function is operated independently.
k6610168 rev.1 nov 19, 2004 - 40 - 7.2.3. smart feature the intent of self-monitoring, analysis, and reporting technology (sma rt) is to protect user data and minimize the likelihood of unsc heduled system downtime that may be caused by predictable degradation and/or fault of the device. by m onitoring and storing critical perform ance and calibration parameters, smart devices attempt to predict the lik elihood of near-term degradation or f ault condition. providing the host system the knowledge of a negative reli ability condition, allows the host sy stem to warn the user of the impending risk of a data loss and advise the user of appropriate action. support of this feature set is indicated in bit 0 of word 82 of the identify de vice response. the smart commands use a single command code and ar e differentiated by t he value placed in the features register. the commands s upported by this feature set are: ? smart enable operations command, smart disable operations command ? smart return status command ? smart enable/disable attribute autosave command ? smart save attribute values command ? smart enable/disable au tomatic offline command ? smart execute offline immediate command ? smart read log sector command, smart write log sector command 7.2.3.1. attribute parameters attributes are the specific performance or calibration parameters that are used in analyzing the status of the device. attributes are selected by t he device manufacturer based on that attribute?s abilit y to contribute to the prediction of degrading or fault conditions for that particular device. the s pecific set of attributes being used and the identity of these attributes is vendor s pecific and proprietary. attribute values are used to represent the relative reliability of individual performance or calibration attributes. higher attribute values indicate t hat the analysis algorithm s being used by the device are predicting a lower probability of a degrading or fault conditi on existing. accordingly, lower attr ibute values indicate that the analysis algorithms being used by t he device are predicting a higher probability of a degrading or fault condition existing. each attribute value has a corresponding attribute thres hold limit that is used for direct comparison to the attribute value to indicate the ex istence of a degrading or fault condition. the dev ice manufacturer through design and reliability testing and analysis determine the numerical values of the attribute thresholds. each attribute threshold represents the lo west limit to which its correspondi ng attribute value can be equal while still retaining a positive reliability stat us. attribute thresholds are set at the device manufacturer?s factory and cannot be changed in the field. if one or more attribut e values are less than or equal to their corresponding attribute thresholds, then the devic e reliability status indicates an impending degrading or fault condition.
k6610168 rev.1 nov 19, 2004 - 41 - 7.2.3.2. smart device error log reporting the intent of smart device erro r log reporting feature is to augment the smart feature set to provide additional diagnostic information on device that have generated error c onditions. the device retains a specified amount of previ ously executed commands, and wr ite this data along with the time of a triggered error condition to the existi ng smart read logging sectors. the errors that device reported ar e gathered at all times the device is powered on except that logging of errors when in reduced power modes ?standby mode and sleep mode?. the last five errors that device reported are gathered in summary smart error log, and the last 255 errors t hat device reported are gathered in comprehensive smart error log. the summa ry smart error log duplicates the five error entries in the comprehensive smart error log. a host can deliver the error info rmation using the smart read log sector command. if smart is disabled by the host, the device does not disable smart device error log. disabling smart w ill only disable the delivering of e rror log information via the smart read log sector command. if a device receives a firmware modification, all erro r log data will be discarded and the device error count for the life of the device will be reset to ze ro by client software ?download utility?. 7.2.3.3. smart operation with power management modes when used in a system that is utilizing the power management f eature set, a smart enabled device automatically saves its attribute values upon receip t of an idle immediate, standby immediate, or sleep command. if the device has been set to utilize the standby timer, the device automatically perform a smart save attribute values function prior to goi ng from an idle state to the standby state. 7.2.3.4. smart function default setting the device is shipped from the device manufacturer's factory wi th smart feature disabled. the system manufacturer or the applications shall enable smart.
k6610168 rev.1 nov 19, 2004 - 42 - 7.2.4. security mode feature the security mode feature set is a password system that restricts access to user data stored on a device. the system has two passwords, user and master and two securi ty levels, high and maximum. the security system is enabled by sending a user password to the device with the security set password command. when the security system is enabled, access to user data on t he device is denied after a power cycle until the user password is sent to the device wi th the security unlock command. a master password may be set in a addition to the user password. the purpose of the master password is to allow an administrator to establish a password that is k ept secret from the user, and which may be used to unlock the device if the user password is lost. setting the master password does not enable the password system. the security level is set to high or maximum with the security set password command. the security level determines device behavior when the master password is us ed to unlock the device. when the security level is set to high the device requires the security unlock command and the master password to unlock. when the security level is set to maximum the device requires a security erase prepare command and a security erase unit command with the master password to unlock. the security freeze lock command prevents changes to passwords until a following power cycle. the purpose of the security freeze lock command is to prevent password setting attacks on the security system. the security mode features allow a host to implement a security pa ssword system to prevent unauthorized access to the internal disk device. the commands supported by this feature set are: ? security set password command ? security unlock command ? security erase prepare command ? security erase unit command ? security freeze lock command ? security disable password command support of the security mode feature set is i ndicated in identify devi ce response word 128. 7.2.4.1. security mode default setting the device is shipped with the master password se t to 20h value (ascii space ) and the lock function disabled. the system manufacture r/dealer may set a new master password using the security set password command, without enabling or disabling the lock function.
k6610168 rev.1 nov 19, 2004 - 43 - 7.2.4.2. initial setting of the user password when a user password is set, the device automatically enters lock m ode the next time the device is powered-on or hardware reset. 7.2.4.3. security mode operation from power-on or hardware reset when lock is enabled, the device reject media a ccess commands until a security unlock command is successfully completed. power-on locked mode unlock erase media access non-media prepare access no password erase reject match? unit command execute command yes unit erased unlock mode lock function disabled normal operation, all commands are available freeze lock normal operation, frozen mode commands are available
k6610168 rev.1 nov 19, 2004 - 44 - 7.2.4.4. user password lost if the user password is lost and high level security is set, the device does not allow the user to access data. the device is unlocked usi ng the master password. if the user password is lost and maxi mum security level is set, data a ccess is impossible. however, the device is unlocked using the se curity erase unit command with the master password to unlock the device and erase all user data. user password lost high level? unlock with master password maximum erase prepare normal operation erase unit with master password normal operation but data lost
k6610168 rev.1 nov 19, 2004 - 45 - 7.2.4.5. security mode command action the following table defines executable commands in each lock mode state. table 7.3 command table for device lock operation command locked mode unlocked mode frozen mode read max address, read max address ext executable executable executable set max address, set max address ext aborted executable executable security disable password security set password aborted executable aborted security unlock security erase prepare security erase unit executable executable aborted security freeze lock aborted executable executable smart automatic enable/disable offline smart execute offline immediate smart disable operations smart enable/disable autosave smart enable operations smart return status smart save attribute values smart read log sector, smart write log sector executable executable executable recalibrate, seek read buffer, write buffer initial device parameters, identify device execute device diagnostics set multiple mode set feature idle, idle immediate standby, standby immediate sleep read dma, read long, read multiple read sector, read verify aborted executable executable read dma ext, read multiple ext, read sector ext read verify sectors ext read log ext write dma, write long, format track write multiple, write sector, flush cache write dma ext, write sectors ext write multiple ext, flush cache ext write dma fua ext, write multiple fua ext write log ext device configuration freeze lock device configuration identify device configuration set device configuration restore
k6610168 rev.1 nov 19, 2004 - 46 - 7.2.5. protected area feature a reserved area for data storage outside the normal operat ing system is required for several specialized applications. systems may wish to st ore configuration data or save memo ry to disk data in a location that operation system can not c hange. following commands are def ined in this feature. ? read max address command and set max address command for 28-bit addressing ? read max address ext command and set max address ext command for 48-bit addressing ? set max set password command ? set max lock command ? set max freeze lock command ? set max unlock command the read native max address or read native max address ext command allows the host to determine the maximum native address space of the device even when a pr otected area has been allocated. the set max address or set max address ext comm and allows the host to redefine the maximum address of the user accessible address space. that is, when the set max address or set max address ext command is issued with a maximum addr ess less than the native maximum address, the device reduces the user accessible address space to the maximum specif ied by the command, providing a protected area above that maximum address. the set max address or set max address ext command is immediately preceded by a read na tive max address or read native max address ext command. after the set max address or set max address ext command has been issued, the device reports only the reduced user address space in response to an identify device command in words 60, 61, 100, 101, 102, and 103. any read or write command to an address above the maximum address specified by the set max address or set max address ext command causes command completion with the idnf bit set to one and err set to one, or command aborted. a volatility bit in the sector count register allows t he host to specify if the maxi mum address set is preserved across power-on or hardware reset cycles. on powe r-on or hardware reset the device maximum address returns to the last non-volatile address setting regardless of subs equent volatile set max address or set max address ext commands. if the set max address or set max address ext command is issued with a value that exceeds the native maximum addre ss command aborted is returned. when the 48-bit address feature set is implemented, the native maximum address is the value returned by a read native max address ext command. if the nat ive maximum address is equal to or less than 268,435,455, a read native max address command retu rns the native maximum address. if the native maximum address is greater than 268,435,455, a r ead native max address command returns a value of 268,435,455.
k6610168 rev.1 nov 19, 2004 - 47 - if a protected area has been creat ed using the set max address command, all set max address ext commands result in command aborted until the prot ected area is eliminated by use of the set max address command with the address value returned by the read native max address command. if a protected area has been cr eated using the set max address ext command, all set max address commands result in command aborted until t he protected area is e liminated by use of the set max address ext command with the addre ss value returned by the read native max address ext command. the set max set password command allows the host to define the password to be used during the current power-on cycle. the password does not persist over a power cycle but does persist over a hardware or software reset. this password is not related to the password used for the security mode feature set. when the password is set the device is in the set max unlocked mode. the set max lock command allows the host to disable the set max commands (except set max unlock) until the next power cycle or the issuance and accept ance of the set max unlock command. when this command is accepted the device is in the set max locked mode. the set max unlock command changes the device from the set max locked mode to the set max unlocked mode. the set max freeze lock command allows the host to disable the set max commands (including set max unlock) until the next power cycle. when this command is accepted the device is in the set max frozen mode. 7.2.6. address offset feature (vendor specific) computer systems perform initial code booting by reading from a predefined address on a disk drive. to allow an alternate bootable operating system to exis t in a reserved area on disk drive, address offset feature provides a set feature func tion to temporarily offset the driv e address space. the offset address space wraps around so that the entire disk drive address space rema ins addressable in offset mode. the set max pointer is set to the end of the reserved area to protect the data in the user area when operating in offset mode. this protecti on can be removed by a set max address / set max address ext command to move the set max pointer to the end of the drive. set feature command subcommand code 09h ?enabl e address ofset mode sub command? offsets address lba 0(cylinder 0, head 0, sector 1) to the start of a non-volatile re served area established using the set max address / set max address ext command. the offset condition is cleared by set feature command subcommand 89h ?disable address offset mode?, software reset, hardware reset or power on reset. upon entering offset mode t he capacity of the drive re turned in the identify device data is the size of the former rese rved area. a subsequent set max address / set max address ext command using the address retur ned by read max address / readmax address ext command allows access to the entire drive. addre sses wrap so the entire drive remains addressable.
k6610168 rev.1 nov 19, 2004 - 48 - if a non-volatile reserved area has not been estab lished before the device receives a set features enable address offset mode sub command, the command fails with abort error status. disable address offset mode removes the address offset and sets the size of the drive reported by the identify device command back to the size specifi ed in the last non-volatile set max address / set max address ext command. identify device word 83 bit 7.indicates the device supports the set features address offset mode. identify device word 86 bit 7 indicates the device is in address offset mode. before enable address offset mode a reserved area has been created using a non-vola tile set max address command or set max address ext command. user accessible area reserved area lba 0 lba r lba m after enable address offset mode the former reserved area is now the user accessible area. the former user accessible area is now the reserved area. user accessible area (former reserved area) reserved area (former user accessible area) lba 0 lba m-r lba m after set max address/set max address ext comma nd using the value returned by read max address command/read max address ext command user accessible area lba 0 lba m set feature disable address offset mode, hardware or power on reset retu rns the device to address offset mode disabled. software reset returns the device to a ddress offset mode disable if set features disable reverting to power on defaults has not been set.
k6610168 rev.1 nov 19, 2004 - 49 - 7.2.7. device configuration overlay feature the device configuration overlay feature set allows a utility program to modify some of the commands, modes, and features sets that a dev ice reports as supported in the identify device command response as well as the capacity r eported. commands unique to the device c onfiguration overlay feature set use a single command code and are differentiat ed from one another by the value pl aced in the features register. these commands are: ? device configuration freeze lock command ? device configuration identify command ? device configuration restore command ? device configuration set command the device configuration overlay feature set affe cts the identify device command responses. certain bits in these words that indicate that a command, mode, capacity, or feature set is supported and enabled can be cleared by a device configuration set comm and. since a host protec ted area may be lost if the capacity of the device is reduced, an attempt to modify the maximum capacity when a host protected area is set will cause the device configurati on set command to return command aborted. if a device configuration freeze lock command has been issued since the device powered-up, the device configuration restore set command re turns command aborted. the settings made by a device configuration set command are ma intained over power-down and power-up. a device configuration identify command indi cates the selectable co mmands, modes, capacity and feature sets that the device is capable of supporting. after the ex ecution of device configuration set command this information is no longer ava ilable from an identify device command. a device configuration restore command disabl es an overlay that has been set by a device configuration set command and returns the identify device command response to that indicated by the device configuration identify command. since a host protected ar ea may be lost if the capacity of the device is reduced, an attempt to modify the maximu m capacity when a host protected area is set will cause the device configuration rest ore command to return command aborted. if a device configuration freeze lock command has been issued since the device powered-up, the device configuration restore command returns command aborted. a device configuration freeze lock command prevent s accidental modification of the state of the device configuration overlay feature set. a device al ways powers-up with configuration freeze lock not set. after a successful device configuration fr eeze lock command is executed, all device configuration set, device configuration identify, and device configuration restore commands are aborted by the device unt il the device is powered-down and powered-up again. the freeze locked state is not affe cted by hardware or software reset.
k6610168 rev.1 nov 19, 2004 - 50 - 7.2.8. write cache and auto reallocation 7.2.8.1. loss of data in write cache write cache is a performance enhancem ent whereby the device reports as completion the write commands to the host as soon as the device has received all of the data into it s cache buffer memory. this means that there is a possibility that power off even after writ e command completion might c ause the loss of the data that the device has not written onto the media. therefore it is recommended that some other co mmand except write command shall be executed before powering the device off. 7.2.8.2. error report and auto write reallocation in case of write cache mode, the device reports the write command comple tion after receiving all data from host immediately. after this command completion, the device automatically reallocates the error sector when the device cannot recover the error in write operation. by this auto r eallocation, the unrecoverable error sector is reassigned to a spare sector, and the data of t he error sector are written on the spare sector. if the device cannot recover the data by th is auto write reallocation, the dev ice reports the error as follows: a) the error occurred when the command execution is on going, the error is reported for the current command. b) the error occurred when the command execution is not on going, the error is reported for by the next command. in case of non-write cache mode, the device reports the write command completion after the completion of write operation on the media. if an error occurr ed during write operation on the media, the device automatically reallocates the error sector when the device cannot recover the e rror in write operation and reports the command completion. the auto write reallocation cannot be disabled. 7.2.8.3. read auto reallocation non recovered read errors: when a read operation fails after error recovery is fully carried out, an error is reported to the host. this error location is registered internally as a candidate for the read reallocation. when the error location is specified as a termite of subsequent writ e operation, the error location is reallocated automatically. recovered read errors: when a read error operation for a sector failed once and re covered at the certain retry step, the recovered sector of the data is r eallocated automatically.
k6610168 rev.1 nov 19, 2004 - 51 - 7.3. command protocol 7.3.1. pio data in command execution includes the transfer of one or more 512 byte sectors of data from the device to the host. 1) the host writes any required parameters to the features, sector count, lba low (sector number), lba mid (cylinder low), lba high (cy linder high), and device/head registers. 2) the host writes the comm and code to the command register. 3) the device sets bsy and prepares for data transfer. 4) when a sector(block) of data is available, the device sets drq and clears bsy prior to asserting intrq. 5) after detecting intrq, the host reads the status register, then reads one sector (block) of data via the data register. in response to the status register being read, t he device negates intrq. 6) the device clears drq. if transfer of another sector (block) is required, the device also sets bsy and the above sequence is repeated from 4). 7.3.2. pio data out command execution includes the transfer of one or more 512-byte sectors of dat a from the host to the device. 1) the host writes any required parameters to the features, sector count, lba low (sector number), lba mid (cylinder low), lba high (cylinder high), and device/head registers. 2) the host writes the comm and code to the command register. 3) the device sets the drq when it gets ready to accept the first sector(block) of data. 4) the host writes one sector blo ck of data to the data register. 5) the device clears drq and sets bsy. 6) when the device has process ed the sector(block), it clears bsy and set the intrq signal to "on". the device sets drq again if anot her sector is required to transfer. 7) after detecting intrq, the host reads the status register. 8) the device clears the interrupt. 9) if another sector (block) is required to be tr ansferred, the above steps 3) to 8) are repeated.
k6610168 rev.1 nov 19, 2004 - 52 - 7.3.3. dma data in/out command the read dma and write dma commands execute data transfer using t he slave-dma channel. the host is required to enable the slave- dma feature, if us ing these commands. 1) the host initializes the slave-dm a feature, if using these commands. 2) the host write any required parameters to the feat ures, sector count, lba low (sector number), lba mid (cylinder low), lba high (cylinder high), and device/head registers. 3) the host writes the comm and code to the command register. 4) the device sets the dmarq when it gets ready to transfer. 5) the slave-dma channel shall re spond by negating cs0- and cs1-, a sserting dmack- signal. and it shall begin data transfer using dma transfer protocol. cs0- and cs1- shall remain negated as long as dmack- is asserted, and dmarq and dmack- signal s hall remain asserted until at least one word of data has been transferred. the r egister contents are not valid during a dma data phase. 6) the device generates the interrupt to t he host, when the data trans fer has completed. 7) the host resets the slave-dma channel. 8) the host reads the status regi ster. in response to the status register being read, the device negates intrq. 7.3.4. non-data command execution of these co mmands does not involv e any data transfer: 1) the host writes any requir ed parameters to the registers. 2) the host writes the command code to the command registers. 3) the device sets bsy. 4) when the device has completed proc essing, it clears bsy and asserts intrq. 5) the host reads the status register. 6) the device negates intrq. 7.3.5. command bsy timing the manner in which a command is accepted varies by the three cl asses of command acceptance all predicated on the fact that to receive a command, bsy=0. the following describes by the conditions under which busy is set after receipt of a command. class 1 - the device sets busy within 400 ns. class 2 - the device will set bsy within 400 ns, then sets up the sector buffer for a write operation, then sets drq, and clears bsy within 400 ns of setting drq. note : drq may be set so quickly on classes 2 that the bsy transition is too short for bsy=1 to be recognized.
k6610168 rev.1 nov 19, 2004 - 53 - 7.4. command summary commands are issued to the device first loading the command block registers with any information needed for the command. then a command code is writt en to the command register, which starts the execution of the command. table 7.4 command codes parameter setup command description protocol class 48-bit lba code fr sc lba low lba mid lba hi dh read commands read buffer pi 1 e4h d read sectors pi 1 20h, 21h v v v v v read long pi 1 22h, 23h v v v v v read multiple pi 1 c4h v v v v v read dma dm 1 c8h, c9h v v v v v read verify nd 1 40h, 41h v v v v v read sectors ext pi 1 v 24h v v v v ld read multiple ext pi 1 v 29h v v v v ld read dma ext dm 1 v 25h v v v v ld read verify sectors ext nd 1 v 42h v v v v ld write commands write buffer po 2 e8h d write sectors po 2 30h, 31h v v v v v write long po 2 32h, 33h v v v v v write multiple po 2 c5h v v v v v write dma dm 2 cah,cbh v v v v v format track po 2 50h v v v v flush cache nd 1 e7h d write sector ext po 2 v 34h v v v v ld write multiple ext po 2 v 39h v v v v ld write dma ext dm 2 v 35h v v v v ld write multiple fua ext po 2 v ceh v v v v ld write dma fua ext dm 2 v 3dh v v v v ld flush cache ext nd 1 v eah d seek commands recalibrate nd 1 1xh d seek nd 1 7xh v v v
k6610168 rev.1 nov 19, 2004 - 54 - table 7.4 command codes(continued) parameter setup command description protocol class 48-bit lba code fr sc lba low lba mid lba hi dh mode set/check, diagnostic execute device diagnostic nd 1 90h d initialize device parameters nd 1 91h v v identify device pi 1 ech d set features nd 1 efh v d set multiple mode nd 1 c6h v d power control check power mode nd 1 98h, e5h v d idle nd 1 97h, e3h v d idle immediate nd 1 95h, e1h d sleep nd 1 99h, e6h d standby nd 1 96h, e2h v d standby immediate nd 1 94h, e0h d unload immediate nd 1 e1h 44h 00h 4ch 4eh 55h d smart commands smart enable/disable auto save nd 1 b0h d2h v v d smart save attribute values nd 1 b0h d3h v d smart enable operations nd 1 b0h d8h v d smart disable operations nd 1 b0h d9h v d smart return status nd 1 b0h dah v d smart enable/disable automatic off-line nd 1 b0h dbh v v d smart execute off-line immediate nd 1 b0h d4h v d smart read log sector pi 1 b0h d5h v v v d smart write log sector po 2 b0h d6h v v v d general purpose logging read log ext pi 1 v 2fh v v v d write log ext po 2 v 3fh v v v d
k6610168 rev.1 nov 19, 2004 - 55 - table 7.4 command codes(continued) parameter setup command description protocol class 48-bit lba code fr sc lba low lba mid lba hi dh security commands security disable password po 2 f6h d security erase prepare nd 1 f3h d security erase unit po 2 f4h d security freeze lock nd 1 f5h d security set password po 2 f1h d security unlock po 2 f2h d protected area commands read max address nd 1 f8h d read native max address ext nd 1 v 27h ld set max address nd 1 f9h 00h v v v v d set max address ext nd 1 v 37h v v v v ld set max set password po 2 f9h 01h d set max lock nd 1 f9h 02h d set max unlock po 2 f9h 03h d set max freeze lock nd 1 f9h 04h d device configuration overlay device configuration restore nd 1 b1h c0h d device configuration freeze lock nd 1 b1h c1h d device configuration identif y pi 1 b1h c2h d device configuration set po 2 b1h c3h d pi: pio data in po: pio data out nd: non-data dm: dma data in/out 48-bit lba: 48-bit addressing feature sc: sector count register lba low: lba low register (sector number register) lba mid: lba mid register (cylinder low register) lba hi: lba high register (cylinder high register) dh: device/head register fr: features register v : valid parameter register for this command d : bit 4 drv of the device/head register is valid. ld: bit 4 drv and bit 6 l of the device/head register are valid.
k6610168 rev.1 nov 19, 2004 - 56 - 7.5. command descriptions 7.5.1. check power mode [98h, e5h] task file register 7 6 5 4 3 2 1 0 command 98h or e5h lba high xx lba mid xx lba low xx device/head x x x drv x x x x sector count xx features xx this command posts the power mode of the device. if the device is in, going into, or recovering from the standby mode, the device sets bsy bit and set the sect or count register to 00h. the device then clears bsy and generates an interrupt. if the device is in the idle mode, the device sets bsy, set the sector count register to ffh, clear bsy, and generate an interrupt. if t he device is in the active mode, the device sets bsy, set the sector count register to ffh, clear bsy, and generate an interrupt. 7.5.2. device configurati on identify [b1h, sub 02h] task file register 7 6 5 4 3 2 1 0 command b1h lba high xx lba mid xx lba low xx device/head x x x drv x x x x sector count xx features 02h the device configuration identify command retu rns a 512 byte data structure via pio data-in transfer. the content of this data structure indicates the selectable co mmands, modes, and feat ure sets that the device is capable of supporting. if a device config uration set command has been issued reducing the capabilities, the res ponse to an identify device comm and will reflect the reduced set of capabilities, while the device configuration id entify command will reflect the entire set of selectable capabilities. the format of the device configuration overlay data structure is shown in table 7.5. if the device has executed a prev ious device configuration fr eeze lock command since power- up, this device returns command aborted.
k6610168 rev.1 nov 19, 2004 - 57 - table 7.5 device configuration identify data structure word description value (hex.) 0 data structure revision 0002h 1 multiword dma modes supported bit 15 - 3 0 = reserved bit 2 1 = multiword dma mode 2 and below are supported bit 1 1 = multiword dma mode 1 and below are supported bit 0 1 = multiword dma mode 0 is supported 0007h 2 ultra dma modes supported bit 15 - 6 0 = reserved bit 5 1 = ultra dma mode 5 and below are supported bit 4 1 = ultra dma mode 4 and below are supported bit 3 1 = ultra dma mode 3 and below are supported bit 2 1 = ultra dma mode 2 and below are supported bit 1 1 = ultra dma mode 1 and below are supported bit 0 1 = ultra dma mode 0 is supported 003fh 3 - 6 maximum lba address this is the highest address accept ed by the device in the factory default condition. if no device configuration set command has been executed modifying the factory default condition 60gb: 06fc 7c7fh 40gb: 04a8 52ffh 30gb: 037e 3e3fh 20gb: 0254 297fh 7 command set / feature set supported bit 15 - 9 0 = reserved bit 14 0 = reserved bit 13 0 = reserved bit 12 1 = smart selective self-test supported bit 11 1 = forced unit access feature set supported bit 10 0 = reserved bit 9 0 = reserved bit 8 1 = 48-bit addressing feature set supported bit 7 1 = host protected area feature set supported bit 6 0 = reserved bit 5 0 = reserved bit 4 0 = reserved bit 3 1 = security feature set supported bit 2 1 = smart error log supported bit 1 1 = smart self-test supported bit 0 1 = smart feature set supported 198fh 8 - 254 reserved 0000h 255 integrity word bit 15 - 8 checksum the checksum is the two?s complement of the sum of all byte in words 0 through 254 and the byte consis ting of bits 7:0 of word 255. each byte is added with unsigned arithmetic, and overflow is ignored. bit 7 - 0 signature code ?a5h? xxa5h
k6610168 rev.1 nov 19, 2004 - 58 - 7.5.3. device configurati on freeze lock [b1h, sub 01h] task file register 7 6 5 4 3 2 1 0 command b1h lba high xx lba mid xx lba low xx device/head x x x drv x x x x sector count xx features 01h the device configuration freeze lock command pr events accidental modification of the device configuration overlay settings. after successful ex ecution of a device configuration freeze lock command, all device configuration set, d evice configuration freeze lock, device configuration identify, and device configura tion restore commands are aborted by the device. the device configuration freeze lock c ondition is cleared by a power-down. the device configuration freeze lock condition is not cleared by hardware or software reset. if the device has executed a prev ious device configuration fr eeze lock command since power- up, the device returns command aborted. 7.5.4. device configuration restore [b1h, sub 00h] task file register 7 6 5 4 3 2 1 0 command b1h lba high xx lba mid xx lba low xx device/head x x x drv x x x x sector count xx features 00h the device configuration restore command disabl es any setting previously made by a device configuration set command and returns the content of the identify device command response to the original settings as indicated by the data returned from the exec ution of a device configuration identify command. if device configuration freeze lock is set or if a host protected area has been set by a set max address command or a set max address ext co mmand, the device returns command aborted.
k6610168 rev.1 nov 19, 2004 - 59 - 7.5.5. device configuration set [b1h, sub 03h] task file registers 7 6 5 4 3 2 1 0 command b1h lba high xx lba mid xx lba low xx device/head x x x drv x x x x sector count xx features 03h the device configuration set command allows a device manufacturer or a personal computer system manufacturer to reduce the set of optional commands, modes, or feature sets supported by a device as indicated by a device configuration iden tify command. the device configuration set command transfers an overlay that modifies some of the bits set in the identify device command response. when the bits in thes e words are cleared, the device no l onger support the indicated command, mode, or feature set. if a bit is set in the overlay transmitted by the device that is not set in the overlay received from a device configuration identi fy command, no action is taken for that bit. the format of the overlay transmitted by the device is described in following table. table 7.6 device configuration set command data structure word description 0 data structure revision word 0 contains the value 0002h. 1 multiword dma modes supported bit 15 - 3 0 = reserved bit 2 1 = multiword dma mode 2 and below are supported bit 2 is cleared to select no support for multiword dma mode 2. this bit shall not be cleared if multiword dma mode 2 is currently selected. bit 1 1 = multiword dma mode 1 and below are supported bit 1 is cleared to select no support for multiword dma mode 1. this bit shall not be cleared if multiword dma mode 2 is supported or multiword dma mode 1 or 2 is selected. bit 0 1 = multiword dma mode 0 is supported bit 0 shall not be cleared.
k6610168 rev.1 nov 19, 2004 - 60 - table 7.6 device configuration set command data structure(continued) word description 2 ultra dma modes supported bit 15 - 6 0 = reserved bit 5 1 = ultra dma mode 5 and below are supported bit 5 is cleared to select no support for ul tra dma mode 5. this bit shall not be cleared if ultra dma mode 5 is currently selected. bit 4 1 = ultra dma mode 4 and below are supported bit 4 is cleared to select no support for ul tra dma mode 4. this bit shall not be cleared if ultra dma mode 5 is support ed or if ultra dma mode 5 or 4 is selected. bit 3 1 = ultra dma mode 3 and below are supported bit 3 is cleared to select no support for ul tra dma mode 3. this bit shall not be cleared if ultra dma mode 5 or 4 is suppor ted or if ultra dma mode 5, 4, or 3 is selected. bit 2 1 = ultra dma mode 2 and below are supported bit 2 is cleared to select no support for ul tra dma mode 2. this bit shall not be cleared if ultra dma mode 5, 4, or 3 is supported or if ultra dma mode 5, 4, 3, or 2 is selected. bit 1 1 = ultra dma mode 1 and below are supported bit 1 is cleared to select no support for ul tra dma mode 1. this bit shall not be cleared if ultra dma mode 5, 4, 3, or 2 is supported or if ultra dma mode 5, 4, 3, 2, or 1 is selected. bit 0 1 = ultra dma mode 0 is supported bit 0 is cleared to select no support for ul tra dma mode 0. this bit shall not be cleared if ultra dma mode 5, 4, 3, 2, or 1 is supported or if ultra dma mode 5, 4, 3, 2, 1, or 0 is selected. 3 ? 6 maximum lba address words 3 - 6 define the maximum lba address. this shall be the highest address accepted by the device after execution of the command. when this val ue is changed, t he content of identify device command are changed to refl ect the maximum address set with this command. this value does not be changed and command aborted is returned if a host protected area has been estab lished by the execution of a set max address command or a set max address ext command.
k6610168 rev.1 nov 19, 2004 - 61 - table 7.6 device configuration set command data structure(continued) word description 7 command set / feature set supported bit 15 - 13 0 = reserved bit 12 1= smart selective self-test supported bit 12 is cleared to select no support for smart selective self-test feature set bit 11 1 = forced unit access feature set supported bit 11 is cleared to select no support for forced unit access feature set bit 10 - 9 0 = reserved bit 8 1= 48-bit addressing feature set supported bit 8 is cleared to select no support for 48-bit addressing feature set bit 7 1 = host protected area feature set supported bit 7 is cleared to select no support for the host protected area feature set. if a host protected area has been established by use of a set max address command or a set max address ext command, the device returns command aborted. bit 6 - 4 0 = reserved bit 3 1 = security feature set supported bit 3 is cleared to select no support for t he security feature set this these bits shall not be cleared if the secu rity feature set has been enabled. bit 2 1 = smart error log supported bit 2 is cleared to select no support for the smart error logging bit 1 1 = smart self-test supported bit 1 is cleared to select no support for the smart self-test bit 0 1 = smart feature set supported bit 0 is cleared to select no support for the smart feature set if bits 1, 2 and 12 of word 7 are not cleared to zero or if the smart feature set has been enabled by use of the smart enable operations command, these bits shall not be cleared and the device returns command aborted. 8 ? 254 reserved 255 integrity word bit 15 - 8 checksum the checksum shall be the two?s complement of the sum of all byte in words 0 through 254 and the byte consis ting of bits 7:0 of word 255. each byte shall be added with unsigned arithmetic, and overflow shall be ignored. bit 7 - 0 signature code bits 7:0 of this word s hall contain the value a5h.
k6610168 rev.1 nov 19, 2004 - 62 - error outputs: if device configuration freeze lock is set or if any of the bit modification restrictions described are violated, the device returns command aborted. registers 7 6 5 4 3 2 1 0 lba high word location number lba mid bit location number bit15 - 8 lba low bit location number bit 7 - 0 sector count xx (vendor unique) sector count register: this register contains vendor unique value by the device. lba mid register (cylinder low register), l ba low register (sector number register): if the command was aborted because an attempt was made to modify a mode or feature that cannot be modified with the device in its current state, these registers c ontain bits (15:0) set in the bit positions that correspond to the bits in the device configuration overlay dat a structure words 1, 2, or 7 for each mode or feature that cannot be c hanged. if not, the value is 00h. lba high register (cylinder high register): if the command was aborted because an attempt was made to modify a bit that cannot be modified with the device in its current state, this register contains the offset of the word that cannot be changed. if not, the value is 00h.
k6610168 rev.1 nov 19, 2004 - 63 - 7.5.6. execute devi ce diagnostic [90h] task file registers 7 6 5 4 3 2 1 0 command 90h lba high xx lba mid xx lba low xx device/head x x x drv x x x x sector count xx features xxh this command allows the device to perform a self-d iagnostics. when device 0 and device 1 are connected in the daisy chain mode, this comm and is executed for both of the devic es. when the device receives this command, it sets bsy=1 and execut es the self-diagnostic operation. then the device registers the diagnostic result in the error regist er, clears bsy, and generates an interrupt. table 7.7 diagnostic codes code contents 01 no error 02 controller error 03 sector buffer error 05 cpu error 8x drv1 error
k6610168 rev.1 nov 19, 2004 - 64 - 7.5.7. flush cache [e7h] task file registers 7 6 5 4 3 2 1 0 command e7h lba high xx lba mid xx lba low xx device/head x l x drv x x x x sector count xx features xx the flush cache command is to che ck the device if write cache data were written on the disk or not. bsy is set until all write cache data are written on the di sk or a write error is occurred. maximum time to write the cache data on the disk is 30 seconds. in case of write faul t, the command is aborted and status register bit 5 dwf (device write fault) is set to one. for device/head register bit 6 l=0 (chs mode), a logical chs address, which had the first error during wr ite cache, is reported on task file register. for device/head register bit 6 l=1 (lba mode), a lba address, which had the first error during write cache, is reported on task file register. 7.5.8. flush cache ext [eah] task file register 7 6 5 4 3 2 1 0 command eah feature previous setting xx current setting xx lba high previous setting xx current setting xx lba mid previous setting xx current setting xx lba low previous setting xx current setting xx sector count previous setting xx current setting xx device x x x dev x x x x the flush cache ext command to used by the host to request the device to fl ush the write cache. if there is data in the write cache, t hat data is written to the media. t he bsy bit remains set to one until all data has been successfully written or an error occurs. maxi mum time to write the cache data on the disk is 30 seconds. an unrecoverable error encountered while writ ing data results in the te rmination of the command and the command block registers cont ain the 48-bit address of the sect or where the first unrecoverable error occurred.
k6610168 rev.1 nov 19, 2004 - 65 - 7.5.9. format track [50h] (vendor specific) task file registers 7 6 5 4 3 2 1 0 command 50h lba high logical cylinder number bit 15 - 8 lba mid logical cylinder number bit 7 - 0 lba low xx device/head x 0 x drv logical head number sector count xxh features xxh the format track command formats a single track on the device. each good sector of data on the track will be initialized to zero with the write operation. the logical track address and head address are specified in the lba high (cylinder high), lba low (cylinder low) and device/head registers. when the command is accepted, the device sets the drq bi t and waits for the host fill the sector buffer. when the sector buffer is filled with 512 bytes of data, the device clear s drq, sets bsy, and begins the command execution (transferred single sector data is ignored). this command is used only in t he physical mode, but the physical mode is not released. if t he device is not in the physical m ode, the device ex ecutes a vendor specific operation. 7.5.10. identify device [ech] task file registers 7 6 5 4 3 2 1 0 command ech lba high xx lba mid xx lba low xx device/head x x x drv x x x x sector count xxh features xxh the identify device command enables the host to re ceive parameter information from the device. when the command is issued, the devic e sets bsy, stores the required parameter information in the sector buffer, sets drq, and generates an interrupt. the host then reads the information from the sector buffer through the data register. t he parameter words are defined in table 7.8 and table 7.9 all reserved bits or words is zero.
k6610168 rev.1 nov 19, 2004 - 66 - table 7.8 identify device information word description value (hex.) 0 general configuration bit 15 1 = atapi device, 0 = ata device bit 14 - 8 0 = retired bit 7 1 = removable media, 0 = fixed media device bit 6 1 = fixed device bit 5 - 3 0 = retired bit 2 1 = identify device data incomplete bit 1 0 = retired bit 0 0 = reserved 0040h 1 number of logical cylinders see table 7.9 2 specific configuration c837h 3 number of logical heads see table 7.9 4 ? 5 retired 0000h 6 number of logical sectors per logical track see table 7.9 7-9 vendor specific 10-19 serial number (20 ascii characters) 20 retired 0000h 21 retired 0000h 22 number of ecc bytes passed on read/write long commands 0004h 23-26 firmware revision (8 ascii characters) 27-46 model number(40 ascii characters) 47 number of sectors on multiple commands bit 15 - 8 80h (fixed) bit 7 - 0 number of sectors on multiple command 8010h 48 reserved 0000h 49 capabilities bit 15 ? 14 0 = reserved bit 13 1 = standby timer values as specified in ata spec supported bit 12 0 = reserved bit 11 1 = iordy supported bit 10 1 = iordy can be disabled bit 9 1 = lba supported bit 8 1 = dma supported bit 7 ? 0 0 = retired 0b00h
k6610168 rev.1 nov 19, 2004 - 67 - table 7.8 identify device information(continued) word description value (hex.) 50 capabilities bit 15 0 (fixed) bit 14 1 (fixed) bit 13 - 1 0 = reserved bit 0 1 = minimum value of standby timer is device specific 4000h 51 bit 15 - 8 pio data transfer cycle timing mode bit 7 - 0 vendor specific 0200h 52 obsolete 0000h 53 field validity bit 15 - 3 0 = reserved bit 2 1 = the field reported in word 88 is valid bit 1 1 = the fields reported words 64-70 are valid bit 0 1 = the fields reported words 54-58 are valid 0007h 54 number of current cylinders 55 number of current heads 56 number of current sectors per track 57-58 current capacity in sectors 59 multiple sector setting bit 15-9 0 = reserved bit 8 1 = multiple sector setting is valid bit 7 - 0 current setting for number of sectors that can be transferred per interrupt on r/w multiple command 60-61 total addressable lba see table 7.9 62 obsolete 0000h 63 multi-word dma transfer bit 15 - 8 multi-word dma transfer mode active bit 7 - 0 multi-word dma transfer mode supported 64 flow control pio transfer modes supported bit 15 - 2 0 = reserved bit 1 1 = pio mode 4 supported bit 0 1 = pio mode 3 supported 0003h 65 minimum multi-word dma transfer cycle time per word(ns) 0078h 66 manufacturer's recommended multi-word dma cycle time(ns) 0078h 67 minimum pio transfer cycle time without flow control(ns) 00f0h 68 minimum pio transfer cycle time with iordy(ns) 0078h 69-74 reserved 0000h 75 queue depth bit 15 - 5 0 = reserved bit 4 - 0 maximum queue depth 0000h 76-79 reserved 0000h
k6610168 rev.1 nov 19, 2004 - 68 - table 7.8 identify device information(continued) word description value (hex.) 80 ata interface major version number bit 15 - 8 0 = reserved bit 7 1 = supports ata-7 bit 6 1 = supports ata-6 bit 5 1 = supports ata-5 bit 4 1 = supports ata-4 bit 3 1 = supports ata-3 bit 2 0 = obsolete bit 1 0 = obsolete bit 0 0 = reserved 0078h 81 ata interface minor version number 0019h 82 command set supported bit 15 0 = reserved bit 14 1 = nop command supported bit 13 1 = read buffer command supported bit 12 1 = write buffer command supported bit 11 0 = reserved bit 10 1 = host protected area feature set supported bit 9 1 = device reset command supported bit 8 1 = service interrupt supported bit 7 1 = release interrupt supported bit 6 1 = look-ahead supported bit 5 1 = write cache supported bit 4 1 = packet command feature set supported bit 3 1 = power management feature set supported bit 2 1 = removable feature set supported bit 1 1 = security feature set supported bit 0 1 = smart feature set supported 746bh 83 command set supported bit 15 0 (fixed) bit 14 1 (fixed) bit 13 1 = flush cache ext command supported bit 12 1 = flush cache command supported bit 11 1 = device configuration overlay feature set supported bit 10 1 = 48-bit address feature set supported bit 9 1 = automatic acoustic management bit 8 1 = set max security extension supported bit 7 1 = address offset mode feature supported bit 6 1 = set features subcommand required to spin-up bit 5 1 = power-up in standby feature set supported bit 4 1 = removable media status notification feature set supported bit 3 1 = advanced power management feature set supported bit 2 1 = cfa feature set supported bit 1 1 = read/w rite dma queued supported bit 0 1 = download microcode command supported 7d88h
k6610168 rev.1 nov 19, 2004 - 69 - table 7.8 identify device information(continued) word description value (hex.) 84 command set/feature supported extension bit 15 0 (fixed) bit 14 1 (fixed) bit 13 1 = unload immediate command supported bit 12 0 = reserved bit 11 0 = reserved bit 10 1 = write stream urg bit supported bit 9 1 = read stream urg bit supported bit 8 1 = 64-bit world wide name supported bit 7 1 = write dma queued fua ext command supported bit 6 1 = write dma/multiple fua ext command supported bit 5 1 = general purpose logging feature set supported bit 4 0 = streaming feature set supported bit 3 1 = media card path though command feature set supported bit 2 1 = media serial number supported bit 1 1 = smart self-test supported bit 0 1 = smart error logging supported 60e3h 85 command set/feature enabled bit 15 0 = reserved bit 14 1 = nop command supported bit 13 1 = read buffer command supported bit 12 1 = write buffer command supported bit 11 0 = reserved bit 10 1 = host protected area feature set supported bit 9 1 = device reset command supported bit 8 1 = service interrupt enabled bit 7 1 = release interrupt enabled bit 6 1 = read look-ahead enabled bit 5 1 = write cache enabled bit 4 1 = supports packet command feature set bit 3 1 = supports power management feature set bit 2 1 = supports removable feature set bit 1 1 = supports security mode feature enabled bit 0 1 = supports smart feature enabled 7468h (at shipment)
k6610168 rev.1 nov 19, 2004 - 70 - table 7.8 identify device information(continued) word description value (hex.) 86 command set/feature enabled bit 15 ?14 0 = reserved bit 13 1 = flush cache ext command supported bit 12 1 = flush cache command supported bit 11 1 = device configuration overlay supported bit 10 1 = 48-bit address features set supported bit 9 1 = automatic acoustic management feature set enabled bit 8 1 = set max security extension enabled by set max password bit 7 1 = address offset mode feature enabled bit 6 1 = set features subcommand required to spin-up bit 5 1 = power-up in standby feature set enabled bit 4 1 = removable media status notification feature set enabled bit 3 1 = advanced power management feature set enabled bit 2 1 = cfa feature set supported bit 1 1 = read/write dma queued supported bit 0 1 = download microcode command supported 3c08h 87 command set/feature default bit 15 0 (fixed) bit 14 1 (fixed) bit 13 1 = idle immediate with unload feature supported bit 12 - 11 0 = reserved bit 10 1 = write strem urg bit supported bit 9 1 = read stream urg bit supported bit 8 1 = 64 bit world wide name supported bit 7 1 = write dma queued fua ext command supported bit 6 1 = write dma/multiple fua ext commands supported bit 5 1 = general purpose logging feature set supported bit 4 1 = valid configure stream command has been executed bit 3 1 = media card pass through command feature set enabled bit 2 1 = media serial number is valid bit 1 1 = smart self-test supported bit 0 1 = smart error logging supported 6063h 88 ultra dma transfer bit 15 ? 14 0 = reserved bit 13 0 = ultra dma mode 5 is selected bit 12 0 = ultra dma mode 4 is selected bit 11 0 = ultra dma mode 3 is selected bit 10 0 = ultra dma mode 2 is selected bit 9 0 = ultra dma mode 1 is selected bit 8 0 = ultra dma mode 0 is selected bit 7 ? 6 0 = reserved bit 5 1 = ultra dma mode 5 and below are supported bit 4 1 = ultra dma mode 4 and below are supported bit 3 1 = ultra dma mode 3 and below are supported bit 2 1 = ultra dma mode 2 and below are supported bit 1 1 = ultra dma mode 1 and below are supported bit 0 1 = ultra dma mode 0 and below are supported xx3fh
k6610168 rev.1 nov 19, 2004 - 71 - table 7.8 identify device information(continued) word description value (hex.) 89 time required for security erase unit completion word 89 specifies the time required for the security erase unit command to completion. if word 90 is 0000h, the time is not specified. security erase unit completion time = value x 2[minutes] 00xxh 90 time required for enhanced security erase unit completion word 90 specifies the time requi red for the enhanced security erase unit command to completion. enhanced security erase unit completion time = value x 2[minutes]. if word 90 is 0000h, the time is not specified. 00xxh 91 current advanced power management level value word 91 contains the current advanced power management level settings. 40xxh 92 master password revision code word 92 contains the value of the ma ster password revision code set when the master password was last changed. xxxxh 93 hardware reset result bit 15 0 (fixed) bit 14 1 (fixed) bit 13 1 = device detected cblid- above v ih 0 = device detected cblid- below v il bit 12 - 8 device 1 hardware reset result. device 1 clears these bits to zero. device 1 sets these bits as follows: bit 12 0 = reserved bit 11 1 = device 1 asserted pdiag- bit 10 - 9 these bits indicate how device 1 determined the device number: 00, 11 = reserved 01 = a jumper was used 10 = the csel signal was used bit 8 1 (fixed) bit 7 - 0 device 0 hardware reset result. device 1 clears these bits to zero. device 0 sets these bits as follows: bit 7 0 = reserved bit 6 1 = device 0 responds when device 1 is selected bit 5 1 = device 0 detected the assertion of dasp- bit 4 1 = device 0 detected the assertion of pdiag0 bit 3 1 = device 0 passed diagnostic bit 2 - 1 these bits indicate how device 0 determined the device number: 00, 11 = reserved 01 = a jumper was used 10 = the csel signal was used bit 0 1 (fixed) xxxxh
k6610168 rev.1 nov 19, 2004 - 72 - table 7.8 identify device information(continued) word description value (hex.) 94 - 99 reserved 0000h 100 - 103 maximum user lba for 48-bit addressing feature set see table 7.9 104 - 126 reserved 0000h 127 removable media status notification feature set support bit 15 ? 2 0 = reserved bit 1 ? 0 00 = removable media status notification feature not supported 01 = removable media status notification feature supported 10, 11 = reserved 0000h 128 security status bit 15 ? 9 0 = reserved bit 8 security level 0 = high, 1 = maximum bit 7 ? 6 0 = reserved bit 5 1 = enhanced security erase supported bit 4 1 = security count expired bit 3 1 = security frozen bit 2 1 = security locked bit 1 1 = security enabled bit 0 1 = security supported 0xxxh 129-159 vendor specific 160-254 reserved 0000h 255 integrity word bit 15 - 8 checksum. the checksum is the two?s complement of the sum of all bytes in word 0 through 254 and the byte consisting of bit 7:0 in word 255. each byte is added with unsigned arithmetic, and overflow is ignored. bit 7 - 0 signature code ?a5h? xxa5h table 7.9 identify device information (addressing) product name (model name) word 1 number of cyl. word 2 number of hd word 3 number of spt word 60 - 61 *1 word 100 - 103 total lba htc426060g9at00 16383 *2 (3fffh) 16 (0010h) 63 (3fh) 117,210,240 (6fc 7c80h) htc426040g9at00 16383 *2 (3fffh) 16 (0010h) 63 (3fh) 78,140,160 (4a8 5300h) HTC426030G7AT00 16383 *2 (3fffh) 16 (0010h) 63 (3fh) 58,605,120 (37e 3e40h) htc426020g7at00 16383 *2 (3fffh) 16 (0010h) 63 (3fh) 39,070,080 (254 2980h) *1: words 60-61 reflect the total number of user addressable sectors in lba mode. *2: maximum capacity in chs mode is 8,455mb.
k6610168 rev.1 nov 19, 2004 - 73 - 7.5.11. idle [97h, e3h] task file registers 7 6 5 4 3 2 1 0 command 97h or e3h lba high xx lba mid xx lba low xx device/head x x x drv x x x x sector count standby timer value features xx the idle command causes the device to enter to the active idle mode. t he sector count register sets the standby timer value. by the power on def ault, the standby timer is disabled. table 7.10 standby timer sector count value standby timer value sc = 0 disabled (power on default) 0 < sc 240 sc x 5 sec (5 sec to 20 minutes) 241 < sc 251, 253 30 minutes 252 21 minutes 254, 255 21 minutes 15 sec default (power on) disabled
k6610168 rev.1 nov 19, 2004 - 74 - 7.5.12. idle immediate [95h,e 1h] / unload immediate [e1h] default function: task file registers 7 6 5 4 3 2 1 0 command 95h or e1h lba high xx lba mid xx lba low xx device/head x x x drv x x x x sector count xx features xx unload feature (unload immediate command): task file registers 7 6 5 4 3 2 1 0 command e1h lba high 55h lba mid 4eh lba low 4ch device/head x x x drv x x x x sector count 00h features 44h default function: the idle immediate command allows the host to immedi ately place the device in the active idle mode. the device clears bsy and generates an interrupt after transition to active idle mode. unload feature (unload immediate command): the device retracts the heads onto t he ramp position as soon as rece iving the unload feature of the idle immediate command. intrq is asserted and bsy is cleared after the heads are completely retracted onto the ramp pos ition and latched. the time to complete the unload operation is typically within 500 milliseconds of receiving the co mmand. the unload controlling method by the unload feature of the idle immediate command is the same as that by power mode transition, and does not effect the specification of normal load/ unload times per device life. the device stops read look-ahead operation if it is in process. if the device is performing a write operation, the device suspends writi ng cached data onto the medi a as soon as possible. and the device keeps unwritten sectors stored in the cache buffer until rece iving a software reset, a hardware reset, or a any new command except idle immediate with unload feature (unload immediate command). after completion of this command, the device stays at low power idle mode, does not go into standby mode and does not load the heads onto the media until receiving a new command. if a device receives this command while the heads are currently on ramp, no physical action is needed. power consumption of the device is higher than normal low power id le mode moved by power management feature.
k6610168 rev.1 nov 19, 2004 - 75 - 7.5.13. initialize device parameters [91h] task file registers 7 6 5 4 3 2 1 0 command 91h lba high xx lba mid xx lba low xx device/head x 0 x drv number of heads minus 1 per cylinder sector count number of sectors per track features xx these parameters allow the host to set the number of sectors per track and the number of heads per cylinder. upon receipt of the command, the device sets bsy, saves the specified parameters, clears bsy, and generates an interrupt. the only two register values that this command uses are the sector count register that specifies the number of sectors per tr ack, and the device/head regi ster that specifies the number of heads minus 1. the sector count and head values are not check ed for validity by this command. if they are invalid, no error will be posted until an illegal access is made by some other command. 7.5.14. read buffer [e4h] task file registers 7 6 5 4 3 2 1 0 command e4h lba high xx lba mid xx lba low xx device/head x x x drv x x x x sector count xx features xx the read buffer command enables the host to read the current contents of the device's sector buffer. when this command is issued, the device sets bsy, sets up the sect or buffer for a read operation, sets drq, clears bsy, and generates an interrupt. t he host then reads up to 512 bytes of data from the sector buffer.
k6610168 rev.1 nov 19, 2004 - 76 - 7.5.15. read dma [c8h, c9h] task file registers 7 6 5 4 3 2 1 0 command c8h or c9h lba high l = 0: cylinder number bit 15 - 8 l = 1: 28-bit lba address bit 23 - 16 lba mid l = 0: cylinder number bit 7 - 0 l = 1: 28-bit lba address bit 15 - 8 lba low l = 0: sector number l = 1: 28-bit lba address bit 7 - 0 device/head x l x drv l = 0: head number l = 1: 28-bit lba address bit 27-24 sector count sector count features xx this command executes in a similar manner to t he read sectors command except for the following: - the host initializes a slave-dma c hannel prior to issuing the command. - data transfers are qualified by dmarq and are performed by the slave-dma channel. - the device issues only one interrupt per command indicating that data tr ansfer has terminated and status is valid. if an error occurs, the read terminates at the se ctor where the error occurred. the command block registers contain the cylinder, head, and sector numbers or 28-bit lba address where the error occurred.
k6610168 rev.1 nov 19, 2004 - 77 - 7.5.16. read dma ext [25h] task file register 7 6 5 4 3 2 1 0 command 25h feature previous setting xx current setting xx lba high previous setting lba bit 47 - 40 current setting lba bit 23 - 16 lba mid previous setting lba bit 39 - 32 current setting lba bit 15 - 8 lba low previous setting lba bit 31 - 24 current setting lba bit 7 - 0 sector count previous setting sector count bit 15 - 8 current setting sector count bit 7 - 0 device x 1 x dev x x x x this command executes in a similar manner to the read sectors ext command except for the following: - the host initializes a slave-dma c hannel prior to issuing the command. - data transfers are qualified by dmarq and are performed by the slave-dma channel. - the device issues only one interrupt per command indicating that data tr ansfer has terminated and status is valid. if an error occurs, the read terminates at the se ctor where the error occurred. the command block registers contain 48-bit lba address where the error occurred.
k6610168 rev.1 nov 19, 2004 - 78 - 7.5.17. read log ext [2fh] task file register 7 6 5 4 3 2 1 0 command 2fh feature previous setting xx current setting xx lba high previous setting reserved current setting reserved lba mid previous setting sector offset bit 15 - 8 current setting sector offset bit 7 - 0 lba low previous setting reserved current setting log sector address sector count previous setting sector count bit 15 - 8 current setting sector count bit 7 - 0 device x x x drv x x x x the read log ext command returns the specified log to the host. if the feature set associated with the log specified in the lba low register is not supported or enabled, or if the va lues in the features, sector count, lba mid, or lba high registers are in valid, the device returns command aborted. - sector count register: specifies the number of sectors to be read from t he specified log. the log transferred by the device starts at the sector in the specif ied log at the specified offset, regardless of the sector count requested. - lba low register: specifies the log to be returned as described in table 7.11. - lba mid register: specifies the first sector of the log to be read.
k6610168 rev.1 nov 19, 2004 - 79 - table 7.11 log sector address definition log sector address content sector size smart read log sector command smart write log sector command read log ext command write log ext command 00h smart log directory general purpose log directory 1 read only read only 01h summary smart error log 1 read only x 02h comprehensive smart error log 51 read only x 03h extended comprehensive smart error log 64 x read only 06h smart self-test log 1 read only x 07h extended smart self-test log 1 x read only 09h smart selective self-test log 1 read/write 23h delayed lba log 96 x read only 80h - 9fh host vendor specific 16 read/write a0h device vendor specific 1 read only, host shall not use a1h - a2h device vendor specific 96 read only, host shall not use a3h ? bfh device vendor specific 1 read/write, host shall not use x: the device reports command abort to the host 7.5.17.1. general purpose log directory [log sector address = 00h] the general purpose log directory is reported size of each log sector addr ess. the following table defines 512 bytes that make up the general purpose log directory. table 7.12 general purpose log directory byte description 0 - 1 smart logging version '0001h' 2 - 3 number of sectors in the log at log sector address 01h 4 - 5 number of sectors in the log at log sector address 02h : : 510 - 511 number of sectors in the log at log sector address ffh 7.5.17.2. extended comprehensive smart error log [log sector address = 03h] the errors that device reported ar e gathered in extended comprehensive smart error log. only 28-bit error entries contain in the comp rehensive smart log, both 28-bit error ent ries and 48-bit error entries contain in the extended comprehensive smart error log. table 7.13 defines the format of each of the sectors that comprise the extended comprehensive smart error log. this error log data structures include unc errors, idnf errors for which the address requested was valid, se rvo errors, write fault e rrors, etc. error log data structures do not include errors attr ibuted to the receipt of faulty commands such as command codes not implemented by the device or requests with invalid paramet ers or invalid addresses.
k6610168 rev.1 nov 19, 2004 - 80 - table 7.13 extended comprehensive smart error log sector byte description first 0 smart error log version '01h' . sector 1 reserved 2 - 3 error log index indicates the error log data structure representing the most recent error 4 - 127 1st extended error log data structure 128 - 251 2nd extended error log data structure 252 - 375 3rd extended error log data structure 376 - 499 4th extended error log data structure 500 - 501 device error count contains the total number of errors attributable to the device that have been reported by the device during the life of t he device. if the maximum value for this field is reached, the count remains at the maximum value when additional errors are encountered and logged. 502 - 510 reserved 511 data structure checksum two's complement of the sum of the first 511 bytes in the first sector. subsequent 0 - 3 reserved sector 4 - 127 (4n + 1) extended error log data structure n 128 - 251 (4n + 2) extended error log data structure 252 - 375 (4n + 3) extended error log data structure 1 < n < 63 376 - 499 (4n + 4) extended error log data structure 500 - 510 reserved 511 data structure checksum two's complement of the sum of the first 511 bytes in the subsequent sector. (1) extended error log data structure the error log is viewed as a circular buffer. the error log index indica tes the most recent error log data structure. unused error log data struct ures are filled with zeros. the cont ent of the error log data structure entries is defined in table 7.14. table 7.14 extended error log data structure byte descriptions n ~ n+17 1st command data structure n+18 ~ n+35 2nd command data structure n+36 ~ n+53 3rd command data structure n+54 ~ n+71 4th command data structure n+72 ~ n+89 5th command data structure n+90 ~ n+123 error data structure
k6610168 rev.1 nov 19, 2004 - 81 - (2) command data structure the fifth command data structure cont ains the command or reset for wh ich the error is being reported. the fourth command data structur e contains the command or rese t that preceded the command or reset for which the error is being reported, the th ird command data structure contains the command or reset preceding the one in the fourth command data structure, etc. if fe wer than four commands and resets preceded the command or reset for which the error is being reported, the unused command data structures are filled zero. if the command data structure represent s a command or software reset, the content of the command data structure is as show n in table 7.15 if the command dat a structure represents a hardware reset, the content of byte n is ffh , the content of bytes n+1 through n+ 13 are not valid and the content of bytes n+14 through n+17 contain the timestamp. table 7.15 command data structure byte descriptions n content of the device control register when the command register was written. n+1 ~ n+2 content of the features register when the command register was written. n+3 ~ n+4 content of the sector count register when the command register was written. n+5 ~ n+6 content of the lba low register w hen the command register was written. n+7 ~ n+8 content of the lba mid register w hen the command register was written. n+9 ~ n+10 content of the lba high register w hen the command register was written. n+11 content of the device/head register w hen the command register was written. n+12 content of the command register w hen command register was written. n+13 reserved n+14 ~ n+17 timestamp (time since power-on in millis econds when command acceptance occurred) (3) error data structure the error data structure contains the error description of the command for which an error was reported as described in table 7.16. table 7.16 error data structure byte description n reserved n+1 content of the error register after command completion occurred. n+2 ~ n+3 content of the sector count r egister after command completion occurred. n+4 ~ n+5 content of the lba low (sector num ber) register after command completion occurred. n+6 ~ n+7 content of the lba mid (cylinder low ) register after command completion occurred. n+8 ~ n+9 content of the lba high (cylinder hi gh) register after command completion occurred. n+10 content of the device/head regist er after command completion occurred. n+11 content written to the status regi ster after command completion occurred. n+12 ~ n+30 extended error info rmation (vendor specific) n+31 this contains a value indi cating the state of the device when command was written to the command register or the reset occurred as described below. 01h: sleep 02h: standby 03h: active/idle with bsy cleared to zero 04h: executing smart off-line or self-test n+32 ~ n+33 life timestamp power-on lifetime of the device in hours when command completion occurred.
k6610168 rev.1 nov 19, 2004 - 82 - 7.5.17.3. extended smart self-test log [log sector address = 07h] the results of smart short self-test routine, ex tended self-test routine and sm art selective self-test routine are gathered in extended smart se lf-test log. this log is viewed as a circular buffer. all unused self- test descriptors are filled with zeros. only 28-bit error entries contain in the smart self-test log, both 28-bit error entries and 48-bit error entries contain in the extended smart self -test log. table 7.17 defines the format of each of the sectors that comp rise the extended smart self-test log. table 7.17 extended smart self-test log byte description 0 self-test log data struct ure revision number "01h" 1 reserved 2 - 3 self-test descriptor index the index points to the most recent entry. when t he log is empty, the index is set to zero. 4 - 29 1 st descriptor entry 30 - 55 2 nd descriptor entry : : 446 - 471 18 th descriptor entry 472 - 499 vendor specific 500 -510 reserved 511 data structure checksum (1) extended self-test log descriptor entry table 7.18 self-test log descriptor entry byte description n content of the lba low (sector number) register this contains the c ontent of the lba low (sector num ber) register when the nth self- test subcommand was issued. n+1 content of the self-tes t execution status byte this contains the result of self-test r outine when the nth self -test was completed. n+2 ~ n+3 life timestamp this contains the power-on lifetime of the device in hours when the nth self-test subcommand was completed. n+4 content of the self-tes t failure checkpoint byte this contains additional in formation about the self-tes t routine that failed. n+5 ~ n+10 falling lba the failing lba is the lba of the uncorrectable sector that caused the test to fail. if the device encountered more than one uncorrectable sector during the test, this field indicates the lba of the first uncorrectable sector encountered. if the test passed or the test failed for some reason other than an uncorre ctable sector, the value of this field is undefined. n+11 ~ n+29 vendor specific
k6610168 rev.1 nov 19, 2004 - 83 - 7.5.17.4. smart selective self-t est log [log sector address = 09h] see 7.5.49.5 smart selective self-t est log [log sector address = 09h] 7.5.17.5. delayed lba log [log sector address = 23h] the delayed lba log contains all sector addresse s which have been moved from their normal physical location using auto-reallocation featur e set. table 7.19 defines the form at of each of the sectors that comprise the delayed lba log. if the maximum size of the delayed lba log is reached and an additional delayed lba is detected by the devic e, the most recent delayed lba is added to the log. the log is returned to the host ordered by timestamp, the most recently added entry is las t. the delayed lba log is non-volatile, it is preserved acro ss power cycles and hardware reset. table 7.19 delayed lba log sector byte decription first 0 delayed lba log version "01h" sector 1 reserved 2 - 3 number of delayed lba entries contain the total count of delayed lba entries 4 - 9 1st entry lba address of 1st re-assigned sector 10 - 11 power-on lifetime of the device, in hours, when the 1st sector was reallocated. : : 500 - 505 lba address of 63rd re-assigned sector 500 - 507 63rd entry power-on lifetime of the device, in hours, when the 63rd sector was reallocated. 508 - 510 reserved 511 data structure checksum two's complement of the sum of the first 511 bytes in the subsequent sector. subsequent 0 - 3 reserved sector 4 - 11 (63n+1) entry (63n + 1) reassigned sector entry n 12 - 19 (63n+2) entry (63n + 2) reassigned sector entry : : : 0 < n < 95 500 - 507 (63n+63) entry (63n + 63) reassigned sector entry 508 - 510 reserved 511 data structure checksum two's complement of the sum of the first 511 bytes in the subsequent sector.
k6610168 rev.1 nov 19, 2004 - 84 - 7.5.18. read long [22h, 23h] task file registers 7 6 5 4 3 2 1 0 command 22h or 23h lba high l = 0: cylinder number bit 15 - 8 l = 1: 28-bit lba address bit 23 - 16 lba mid l = 0: cylinder number bit 7 - 0 l = 1: 28-bit lba address bit 15 - 8 lba low l = 0: sector number l = 1: 28-bit lba address bit 7 - 0 device/head x l x drv l = 0: head number l = 1: 28-bit lba address bit 27-24 sector count 01h features xx the read long command performs similarly to the r ead sectors command except that it returns the data and the ecc bytes contained in the data field of the desired sect or. during a read long command, the device does not check the ecc byte s to determine if there has been a dat a error. only single sector read long operations are support ed. the number of ecc bytes transferr ed will be 4 bytes (default). if the ecc transfer length is changed by f eature register 44h, 68 bytes of ecc will be transferred.
k6610168 rev.1 nov 19, 2004 - 85 - 7.5.19. read multiple [c4h] task file registers 7 6 5 4 3 2 1 0 command c4h lba high l = 0: cylinder number bit 15 - 8 l = 1: 28-bit lba address bit 23 - 16 lba mid l = 0: cylinder number bit 7 - 0 l = 1: 28-bit lba address bit 15 - 8 lba low l = 0: sector number l = 1: 28-bit lba address bit 7 - 0 device/head x l x drv l = 0: head number l = 1: 28-bit lba address bit 27-24 sector count sector count features xx the read multiple command is similar to the r ead sectors command, except interrupts are not generated on every sector, but on the transfer of a block which contains the number of sectors defined by a set multiple mode command. the number of sect ors defined by a set multiple mode command is transferred without intervening interrupts. drq qualification of the transfer is required only at the start of the data block, not on each sector. the set multiple mo de command, which must be executed prior to the read multiple command, sets the block count of sectors to be transferred. when the read multiple command is issued, the sector count register contains the number of sectors (not the number of blocks or the block count) requested. if the number of requested sectors is not evenly divisible by the block count, as many full blocks as po ssible are transferred, followed by a final, partial block transfer for n sectors, where n = residue of {sector count / sector count per block}. disk errors encountered during read multiple comm ands are posted at the begi nning of the block or partial block transfer, but drq is still set and the dat a transfer should be executed as it normally would, including transfer of corrupted data, if any. subsequent blocks or partial blocks are transferred only if the error was a correctable data error. all other errors cause the command to st op after transfer of the block that contained the error. interrupts are gener ated when drq is set at the beginning of each block or partial block.
k6610168 rev.1 nov 19, 2004 - 86 - 7.5.20. read multiple ext [29h] task file register 7 6 5 4 3 2 1 0 command 29h feature previous setting xx current setting xx lba high previous setting lba bit 47 - 40 current setting lba bit 23 - 16 lba mid previous setting lba bit 39 - 32 current setting lba bit 15 - 8 lba low previous setting lba bit 31 - 24 current setting lba bit 7 - 0 sector count previous setting sector count bit 15 - 8 current setting sector count bit 7 - 0 device x 1 x dev x x x x the read multiple ext command is similar to t he read sectors ext command, except interrupts are not generated on every sector, but on the transfer of a block which contains the number of sectors defined by a set multiple mode command. the number of sectors defined by a set multiple mode command is transferred without interv ening interrupts. drq qualification of the transfer is required only at the start of the data block, not on each sector. the set multiple mode command, which must be executed prior to the read multiple ext command, se ts the block count of sectors to be transferred. when the read multiple ext command is issued, the sector count register contains the number of sectors (not the number of blocks or the block count ) requested. if the number of requested sectors is not evenly divisible by the block count, as many full blocks as possible are transferred, followed by a final, partial block transfer for n sectors, where n = residue of {sector count / sector count per block}. disk errors encountered during read multiple ext commands are posted at t he beginning of the block or partial block transfer, but drq is still set and the data transfer should be execut ed as it normally would, including transfer of corrupted data, if any. subsequent blocks or partial blocks are transferred only if the error was a correctable data error. all other errors cause the command to st op after transfer of the block that contained the error. interrupts are gener ated when drq is set at the beginning of each block or partial block.
k6610168 rev.1 nov 19, 2004 - 87 - 7.5.21. read max address command [f8h] task file registers 7 6 5 4 3 2 1 0 command f8h lba high xx lba mid xx lba low xx device/head x l x drv x x x x sector count xx features xx the read native max command returns the native maxi mum 28-bit lba or cylinders of the device which is not affect by set max address command or set max address ext command. the data returned in the command block registers is the maximum device size as shown in the following tables. task file registers 7 6 5 4 3 2 1 0 lba high l = 0: native maximum cylinder bit 15 - 8 l = 1: native maximum lba bit 23 - 16 lba mid l = 0: native maximum cylinder bit 7 - 0 l = 1: native maximum lba bit 15 - 8 lba low l = 0: native maximum sector number l = 1: native maximum lba bit 7 - 0 device/head - l - drv l = 0: native max head l = 1: native max lba bit 27 - 24 sector count xx if the 48-bit address feature set is supported and t he 48-bit native max address is greater than 268,435,455, the read native max address command returns a maximum 28-bit lba value of 268,435,454.
k6610168 rev.1 nov 19, 2004 - 88 - 7.5.22. read max address ext command [27h] task file register 7 6 5 4 3 2 1 0 command 27h feature previous setting xx current setting xx lba high previous setting xx current setting xx lba mid previous setting xx current setting xx lba low previous setting xx current setting xx sector count previous setting xx current setting xx device x 1 x dev x x x x the read native max ext command returns the native maximum 48-bit lba of the device which is not affect by set max address ext command or set max address ext command. the data returned in the command block registers is the maximum device size as shown in the following tables. task file register 7 6 5 4 3 2 1 0 lba high hob = 1 maximum lba bit 47 - 40 hob = 0 maximum lba bit 23 - 16 lba mid hob = 1 maximum lba bit 39 - 32 hob = 0 maximum lba bit 15 - 8 lba low hob = 1 maximum lba bit 31 - 24 hob = 0 maximum lba bit 7 - 0
k6610168 rev.1 nov 19, 2004 - 89 - 7.5.23. read sectors [20h, 21h] task file registers 7 6 5 4 3 2 1 0 command 20h or 21h lba high l = 0: cylinder number bit 15 - 8 l = 1: 28-bit lba address bit 23 - 16 lba mid l = 0: cylinder number bit 7 - 0 l = 1: 28-bit lba address bit 15 - 8 lba low l = 0: sector number l = 1: 28-bit lba address bit 7 - 0 device/head x l x drv l = 0: head number l = 1:28-bit lba address bit 27-24 sector count sector count features xx this command reads sectors as spec ified in the sector count regist er. the read operation begins at the sector specified in the lba high, lba mid and lba low registers. drq is set prior to data transfer regardless of the presence or abs ence of an error condition. at co mmand completion, the command block registers contain the 28-bit lba address or cylinder/head/ sector numbers of the last sector read. if an error occurs, the read terminates at the sector where the error occurred. the command block registers contain the 28-bit lba address or the cylinder/head/se ctor numbers where the error occurred. 7.5.24. read sectors ext [24h] task file register 7 6 5 4 3 2 1 0 command 24h feature previous setting xx current setting xx lba high previous setting lba bit 47 - 40 current setting lba bit 23 - 16 lba mid previous setting lba bit 39 - 32 current setting lba bit 15 - 8 lba low previous setting lba bit 31 - 24 current setting lba bit 7 - 0 sector count previous setting sector count bit 15 - 8 current setting sector count bit 7 - 0 device x 1 x dev x x x x the read sectors ext command reads sectors as s pecified in the sector count register. the read operation begins at the sector specified in the lba high, lba mid and lba low registers. drq is set prior to data transfer regardless of the presence or absence of an error condition. at command completion, the command block registers contain the 48-bit lba address of the last sector read. if an error occurs, the read terminates at the sector where the error occurred. the command block registers contain the 48-bit lba address where the error occurred.
k6610168 rev.1 nov 19, 2004 - 90 - 7.5.25. read verify [40h, 41h] task file registers 7 6 5 4 3 2 1 0 command 40h or 41h lba high l = 0: cylinder number bit 15 - 8 l = 1: 28-bit lba address bit 23 - 16 lba mid l = 0: cylinder number bit 7 - 0 l = 1: 28-bit lba address bit 15 - 8 lba low l = 0: sector number l = 1: 28-bit lba address bit 7 - 0 device/head x l x drv l = 0: head number l = 1: 28-bit lba address bit 27-24 sector count sector count features xx the read verify command is same as the read sec tors command, except that drq is never set and no data is transferred to the host. when the reques ted sectors have been verified, the device clears bsy and generates an interrupt. upon command completion, the command block registers contain the 28- bit lba address or cylinder/head/sector numbers of the la st sector verified. if an error occurs, the verify terminates at the sector where the error occurs . the command block registers contain the 28-bit lba address or cylinder/head/sector numbers of the sector w here the error occurred. the sector count register contains the number of se ctors not yet verified.
k6610168 rev.1 nov 19, 2004 - 91 - 7.5.26. read verify sectors ext [42h] task file register 7 6 5 4 3 2 1 0 command 42h feature previous setting xx current setting xx lba high previous setting lba bit 47 - 40 current setting lba bit 23 - 16 lba mid previous setting lba bit 39 - 32 current setting lba bit 15 - 8 lba low previous setting lba bit 31 - 24 current setting lba bit 7 - 0 sector count previous setting sector count bit 15 - 8 current setting sector count bit 7 - 0 device x 1 x dev x x x x the read verify sectors ext command is same as the read sectors ext command, except that drq is never set and no data is transferred to the host. when the requested sect ors have been verified, the device clears bsy and generates an interrupt. upon co mmand completion, the command block registers contain the 48-bit lba address of the last sector verifi ed. if an error occurs, the ve rify terminates at the sector where the error occurs. the command block regi sters contain the 48-bit lba address of the sector where the error occurred. the sector count register contains the number of sectors not yet verified.
k6610168 rev.1 nov 19, 2004 - 92 - 7.5.27. recalibrate [1xh] task file registers 7 6 5 4 3 2 1 0 command 1xh lba high xx lba mid xx lba low xx device/head x x x drv x x x x sector count xx features xx the recalibrate command performs no operation. upon receipt of the command, the devic e clears bsy and generates an interrupt. 7.5.28. security disable password [f6h] task file registers 7 6 5 4 3 2 1 0 command f6h lba high xx lba mid xx lba low xx device/head x x x drv x x x x sector count xx features xx the security disable password command requests a trans fer of a single sector of data from the host. the following table defines the content of this sector of info rmation. then the device checks the transferred password. if the user password or the ma ster password match, the device disables the lock function. this command does not c hange the master password that may be reactivated later by setting a user password. table 7.20 password data format word contents 0 control word bit 15-1 reserved bit 0 identifier 0 = compare user password, 1 = compare master password 1-16 password (32bytes) 17-255 reserved device returns aborted command error if the device is in locked mode, or the dev ice is in frozen mode.
k6610168 rev.1 nov 19, 2004 - 93 - 7.5.29. security erase prepare [f3h] task file registers 7 6 5 4 3 2 1 0 command f6h lba high xx lba mid xx lba low xx device/head x x x drv x x x x sector count xx features xx the security erase prepare command shall be i ssued immediately befor e the security erase unit command to enable device erasing and unlocking. this command is to prevent accidental erasure of the device. device returns aborted command error if the device is in frozen mode. 7.5.30. security erase unit [f4h] task file registers 7 6 5 4 3 2 1 0 command f4h lba high xx lba mid xx lba low xx device/head x x x drv x x x x sector count xx features xx the security erase unit command requests a transfer of a single sector of data from the host. the following table defines the c ontent of this sector of information. if the password does not match, then the device rejects the command with an aborted error. table 7.21 password data format word contents 0 control word bit 15-1 reserved bit 0 identifier 0 = compare user password, 1 = compare master password 1-16 password(32bytes) 17-255 reserved
k6610168 rev.1 nov 19, 2004 - 94 - the security erase unit command erases all us er data. the security erase prepare command shall be completed immediately prior to the se curity erase unit command. if the device receives a security erase unit command without an immedi ately prior security erase prepare command, the device aborts the se curity erase unit command this command disables the device lo ck function, however, the master pa ssword is still stored internally within the device and may be reactivated later when a new user password is set. the device returns aborted command error if the devic e is in frozen mode. the execution time of th is command is shown below. - htc426060g9at00 54 minutes - htc426040g9at00 40 minutes - HTC426030G7AT00 27 minutes - htc426020g7at00 20 minutes 7.5.31. security freeze lock [f5h] task file registers 7 6 5 4 3 2 1 0 command f5h lba high xx lba mid xx lba low xx device/head x x x drv x x x x sector count xx features xx the security freeze lock command sets the device to frozen mode. after this command is completed any other commands which update the device lock functions are rejected. frozen mode is quit by power-off or hardware reset. if security fr eeze lock is issued when the device is in frozen mode, the command executes and the device remains in frozen mode. the device returns abor ted command if the device is in locked mode. commands disabled by security freeze lock are: ? security set password command ? secuirty unlock command ? security disable password command ? security erase unit command
k6610168 rev.1 nov 19, 2004 - 95 - 7.5.32. security set password [f1h] task file registers 7 6 5 4 3 2 1 0 command f1h lba high xx lba mid xx lba low xx device/head x x x drv x x x x sector count xx features xx the security set password command requests a transfer of a single sector of data from the host. the following table defines the content of this sector of info rmation. the data transferred c ontrols the function of this command. the revision code field is returned in the iden tify device word 92. the valid revision codes are 0000h to fffdh. the initial factory shipped value of mast er password revision code is fffeh. value ffffh is revised. table 7.22 password data format word contents 0 control word bit 15-9 reserved bit 8 security level 0 = high, 1 = maximum bit 7 reserved bit 0 identifier 0 = set user password, 1 = set master password 1-16 password(32bytes) 17 mater password revision code (valid if word 0 bit 0 = 1) 18 - 255 reserved the following table defines t he interaction of the identifier and security level bits. table 7.23 security level and identifier identifier security level command result user high the password supplied with the command is saved as the new user password. the lock function will be enabled from the next power-on or hardware reset. the device will then be unlocked by either the user password or the previously set master password. user maximum the password supplied with the command is saved as the new user password. the lock function will be enabled from the next power-on or hardware reset. the device will then be unlocked by only the user password. the master password previous ly set is still stored in the device but shall not be used to unlock the device. master high or maximum this combination set a mater password, but will not enable the security mode feature. the security level is not changed. master password revision code set to the value in master password revision code field. the device returns aborted command error if t he device is in locked mode or frozen mode.
k6610168 rev.1 nov 19, 2004 - 96 - 7.5.33. security unlock [f2h] task file registers 7 6 5 4 3 2 1 0 command f2h lba high xx lba mid xx lba low xx device/head x x x drv x x x x sector count xx features xx the security unlock command requests a transfer of a single sector of data from the host. the following table defines t he content of this sector of information. table 7.24 password data format word contents 0 control word bit 15-1 reserved bit 0 identifier 0 = compare user password, 1 = compare master password 1-16 password(32bytes) 17-255 reserved if the identifier bit is set to master and the device is in high security level, then the password supplied is compared with the stored master password. if the devic e is in maximum security level, then the security unlock command is rejected. if the i dentifier bit is set to user, then the device compares the supplied password with the stored user password. if the password compare fails then the device return s an abort error to the host and decrements the unlock counter. this counter is initially set to five and is decrement for each passw ord mismatch when security unlock command is issued and the dev ice is locked. when this count er reaches zero then security unlock and security erase unit commands are abort ed until a power-on reset or a hard reset. security unlock command issued when the device is unlocked have no effect on the unlock counter. the device returns aborted command error if the device is in frozen mode.
k6610168 rev.1 nov 19, 2004 - 97 - 7.5.34. seek [7xh] task file registers 7 6 5 4 3 2 1 0 command 7xh lba high l = 0: cylinder number bit 15 - 8 l = 1: 28-bit lba address bit 23 - 16 lba mid l = 0: cylinder number bit 7 - 0 l = 1: 28-bit lba address bit 15 - 8 lba low l = 0: sector number l = 1: 28-bit lba address bit 7 - 0 device/head x l x drv l = 0: head number l = 1: 28-bit lba address bit 27-24 sector count xx features xx the seek command initiates a seek operation to the tra ck specified in the command block registers. the device returns the interrupt before completion of a seek operation. if another command is issued to the device while a seek operation is bei ng executed, the device sets bsy, wa its for the seek to complete, and then begins executi on of the command.
k6610168 rev.1 nov 19, 2004 - 98 - 7.5.35. set features [efh] task file registers 7 6 5 4 3 2 1 0 command efh lba high xx lba mid xx lba low xx device/head x x x drv x x x x sector count refer to table 7.25 features refer to table 7.25 this command is used to spec ify the parameters shown in table 7.25 and table 7.26. table 7.25 set feature register definition features code *1 description default 03h set transfer mode based on value in sector count register see table 7.26. 05h enable advanced power management *2 09h enable address offset mode *3 33h disable retries 44h enable vendor unique ecc byte length(24 bytes) transfer 55h disable read look-ahead feature 66h disable reverting to power on defaults 77h disable ecc 85h disable advanced power management *2 88h enable ecc 89h disable address offset mode *3 99h enable retries aah enable read look-ahead feature bbh enable 4 bytes ecc transfer cch enable reverting to power on defaults 02h enable write cache 82h disable write cache *1 : if the code is not suppor ted, the device returns aborted command error. *2 : see sec. 7.2.2.3 advanced po wer management for the details. *3 : see sec. 7.2.6 address offset feat ure (vendor specific )for the details. table 7.26 transfer mode code definition sector count register transfer mode 2xh multi-word dma mode (x: 0, 1, 2) : 0: mode 0(4.1 mb/s), 1: mode 1( 13.3 mb/s), 2: mode 2(16.6 mb/s) 4xh ultra dma mode (x: 0, 1, 2, 3, 4, 5) : 0: mode 0(16.6 mb/s), 1: mode 1( 25.0 mb/s), 2: mode 2(33.3 mb/s) 3: mode 3(44.4 mb/s), 4: mode 4( 66.6 mb/s), 5: mode 5(100.0 mb/s)
k6610168 rev.1 nov 19, 2004 - 99 - 7.5.36. set max address command [f9h, sub 00h] task file registers 7 6 5 4 3 2 1 0 command f9h lba high l = 0: maximum cylinder bit 15 - 8 l = 1: maximum lba bit 23 - 16 lba mid l = 0: maximum cylinder bit 7 - 0 l = 1: maximum lba bit 15 - 8 lba low l = 0: unused l = 1: maximum lba bit 7 - 0 device/head x l x drv l = 0: unused l = 1: maximum lba bit 27-24 sector count xx b features 00h the set max address command overwrites the maximum 28-bit lba address or cylinder of the device in a range of actual device capacity (head number and sector number are ignored, the def ault value is used for that). once the device receives this command, all accesses beyond t hat lba or cylinder are rejected. identify device command returns the lba or cy linder, which is set via this command as default. bit 0 "b" of sector count register is option bit fo r selection whether nonvolatile. when b = 1, maximum lba or maximum cylinder which is set by set max a ddress command is preserved over power-on, hardware reset, software reset. when b = 0, maximum lba or maximum cylinder which is set by set max address command will be lost by power-on or hardware reset. b se t to one is not valid when the device is in address offset mode. abrt is set if b set to one w hen the device is in address offset mode. read nax address command should be issued and comple ted immediately prior to issuing set max address command. if the device receives set m ax address command without a prior read max address command, the device aborts the set max a ddress command. after successful completion of this command, all accesses beyond that lba or cylinder will be rejected with setting id not found error. if the device receives a second nonvolatile set max a ddress command (b=1) after a power on or hardware reset, the device reports an id not found error. if the maximum value to be set exceeds the capacity of the devic e, or the device is in the set max locked or set max frozen state, then the device returns co mmand aborted. if a protect ed area has been established by a set max address ext command, the device returns command aborted.
k6610168 rev.1 nov 19, 2004 - 100 - after a successful command completion, identi fy device response word 60-61 and word 100-103 reflect the maximum address set with this command. the address returned in the command block registers is the maximum device size as shown in the following tables: output parameters to the device: task file registers 7 6 5 4 3 2 1 0 lba high l = 0: maximum cylinder bit 15 - 8 l = 1: maximum lba bit 23 - 16 lba mid l = 0: maximum cylinder bit 7 - 0 l = 1: maximum lba bit 15 - 8 lba low l = 0: maximum sector number (*1) l = 1: maximum lba bit 7 - 0 device/head x l x drv l = 0: maximum head number (*1) l = 1: maximum lba bit 27-24 *1: maximum sector number and maximum head number ar e fixed values, and the values are 16 and 63.
k6610168 rev.1 nov 19, 2004 - 101 - 7.5.37. set max address ext command [37h] task file register 7 6 5 4 3 2 1 0 command 37h feature previous setting xx current setting xx lba high previous setting maximum lba bit 47 - 40 current setting maximum lba bit 23 - 16 lba mid previous setting maximum lba bit 39 - 32 current setting maximum lba bit 15 - 8 lba low previous setting maximum lba bit 31 - 24 current setting maximum lba bit 7 - 0 sector count previous setting xx current setting xx b device x 1 x dev x x x x the set max address ext command overwrites the maximum 48-bit lba address of the device in a range of actual device capac ity. once the device receives this command, all accesses beyond that lba or cylinder are rejected. identify device command retu rns the lba or cylinder, which is set via this command as default. bit 0 "b" of sector count register is option bit fo r selection whether nonvolatile. when b = 1, maximum lba which is set by set max address ext command is pr eserved over power-on, hardware reset, software reset. when b = 0, maximum lba which is set by set max address ext command will be lost by power-on or hardware reset. b set to one is not valid when the device is in addr ess offset mode. abrt is set if b set to one when the device is in address offset mode. read nax address ext command should be issued and co mpleted immediately prior to issuing set max address ext command. if the device receives set max address ext command without a prior read max address ext command, the device abor ts the set max address ext command. after successful completion of this comm and, all accesses beyond that lba w ill be rejected with setting id not found error. if the device receives a second nonvol atile set max address ext command (b=1) after a power on or hardware reset, the device reports an id not found error. if the maximum value to be set exceeds the capacity of the devic e, or the device is in the set max locked or set max frozen state, then the device returns co mmand aborted. if a protect ed area has been established by a set max address command, the device returns command aborted.
k6610168 rev.1 nov 19, 2004 - 102 - after a successful command completion, identi fy device response word 60-61 and word 100-103 reflect the maximum address set with this command. the address returned in the command block registers is the maximum device size as shown in the following tables: output parameters to the device: task file register 7 6 5 4 3 2 1 0 lba high hob = 1 maximum lba bit 47 - 40 hob = 0 maximum lba bit 23 - 16 lba mid hob = 1 maximum lba bit 39 - 32 hob = 0 maximum lba bit 15 - 8 lba low hob = 1 maximum lba bit 31 - 24 hob = 0 maximum lba bit 7 - 0 7.5.38. set max freeze lock command [f9h, sub 04h] task file registers 7 6 5 4 3 2 1 0 command f9h lba high xx lba mid xx lba low xx device/head x x x drv x x x x sector count xx features 04h the set max freeze lock command sets the dev ice to set max frozen state. after command completion any subsequent set max commands are re jected. commands disabled by set max freeze lock are: ? set max address command ? set max address ext command ? set max set password command ? set max lock command ? set max unlock command a set max set password command shall previously have been successfully completed. this command shall not be immediately preceded by a read max address command. if this command is immediately preceded by a read max address command, it is interpreted as a set max address command. if the device is in the set max unlocked st ate, the device repor ts command aborted.
k6610168 rev.1 nov 19, 2004 - 103 - 7.5.39. set max lock command [f9h, sub 02h] task file registers 7 6 5 4 3 2 1 0 command f9h lba high xx lba mid xx lba low xx device/head x x x drv x x x x sector count xx features 02h the set max lock command sets the device into set max locked state. after th is command is completed any other set max commands except set max unlock command and set max freeze lock command are rejected. the device remains in this stat e until a power cycle or the acceptance of a set max unlock or set max freeze lock command. this command shall not be immedi ately preceded by a read max address command. if this command is immediately preceded by a read max address comm and, it is interpreted as a set max address command. if the device is not in the set max lo cked state, the device reports command aborted. 7.5.40. set max set password command [f9h, sub 01h] task file registers 7 6 5 4 3 2 1 0 command f9h lba high xx lba mid xx lba low xx device/head x x x drv x x x x sector count xx features 01h the set max set password command requests a transfer of a single sector of data from the host. table 7.27 defines the c ontent of this sector of information. t he password is retained by the device until the next power cycle. when the device accepts this co mmand the device is in se t max unlocked state. table 7.27 set max password data format word content 0 reserved 1- 16 password for set max security extension 17 - 255 reserved
k6610168 rev.1 nov 19, 2004 - 104 - this command shall not be immedi ately preceded by a read max address command. if this command is immediately preceded by a read max address comm and, it is interpreted as a set max address command. if the device is in the set max locked or set max frozen state, the device returns command aborted. 7.5.41. set max unlock command [f9h, sub 03h] task file registers 7 6 5 4 3 2 1 0 command f9h lba high xx lba mid xx lba low xx device/head x x x drv x x x x sector count xx features 01h this command requests a transfer of a single sector of data from the host. table 7.27 defines the content of this sector of information. the password supplied in the sector of data transfe rred is compared with the stored set max password. if the password compare fails, then the device retu rns command aborted and decrem ents the unlock counter. on the acceptance of the set max lo ck command, this counter is set to a value of five and is decrement for each password mismatch when set max unlock command is issued and the device is locked. when this counter reaches zero, then the set max unlock command returns command aborted until a power cycle. if the password compare matches, then the devic e makes a transition to the set max unlocked state and all set max commands are accepted. this command shall not be immedi ately preceded by a read max address command. if this command is immediately preceded by a read max address comm and, it is interpreted as a set max aaddress command. if the device is not in the set max lo cked state, the device reports command aborted.
k6610168 rev.1 nov 19, 2004 - 105 - 7.5.42. set multiple mode [c6h] task file registers 7 6 5 4 3 2 1 0 command c6h lba high xx lba mid xx lba low xx device/head x x x drv x x x x sector count sector per block features xx the set multiple mode command allows the device to specify the number of sectors per block to perform read multiple and write multiple comm and operations. the sector count register is loaded with the number of sectors per block. block size s of 1, 2, 4, 8, and 16 sectors are supported. upon receipt of the command, the device sets bsy=1 and checks the sector count register. if the sector count register contains a valid val ue, then the value is loaded for a ll subsequent multiple commands and execution of those commands is enabled. if an invalid value is s pecified, an abort ed command error is posted and execution of the multiple commands is disabled. t he multiple commands cannot be executed in the default mode at power on or after a hardware reset. 7.5.43. sleep [99h,e6h] task file registers 7 6 5 4 3 2 1 0 command 99h or e6h lba high xx lba mid xx lba low xx device/head x x x drv x x x x sector count xx features xx the sleep command causes the dev ice to be spun down and enter t he sleep mode. when the rotation stops, bsy is cleared, an interruption is generated, and the inte rface becomes inactive. software reset or hardware reset allows the device to recover from the sleep mode.
k6610168 rev.1 nov 19, 2004 - 106 - 7.5.44. smart disable operations [b0h, sub d9h] task file registers 7 6 5 4 3 2 1 0 command b0h lba high c2h lba mid 4fh lba low xx device/head x x x drv x x x x sector count xx features d9h the smart disable operations command disables a ll smart capabilities within the device including any and all timer functions related excl usively to this feature. after re ceipt of this command the device will disable all smart operations. attri bute values will no longer be monitor ed or saved by the device. the device will preserve the state of smart (eit her enabled or disabled) across power cycles. if smart is not enabled, or if the values in the f eatures, lba mid (cylinder low) or lba high (cylinder high) registers are invalid, an a borted command error is posted. upon receipt of the smart disable operations comm and from the host, the devic e sets bsy, disables smart capabilities and functions, clears bsy, and asserts intrq. after receipt of this command by the device, all other smart commands, with the exception of smart enable operations, are disabled and invalid and are aborted by the device (including smart disable operations commands), retu rning the aborted command error.
k6610168 rev.1 nov 19, 2004 - 107 - 7.5.45. smart enable/disable au tomatic off-line [b0h, sub dbh] task file registers 7 6 5 4 3 2 1 0 command b0h lba high c2h lba mid 4fh lba low xx device/head x x x drv x x x x sector count 00h: di sable, f8h: enable features dbh smart enable / disable automatic off-line comm and enables and disables the automatic off-line feature. if automatic off-line is enabled, the device automatically correct attribute data in an off-line mode periodically and save the attribute data on the disk. - the sector count register is set to 00h to disable automatic collection of off-line data - the sector count register is set to f 8h to enable automatic collection of off-line data the following tests are performed for the automatic off-line feature: a) raw read error rate measurement partial read scanning and raw read error rate measurement is performed. this event is occurred every 24 poh? s and 2 minutes of host inactivity. b) automatic sector r eallocation in off-line read scanning for entire lba. this event occurs every 168 poh?s and 2 minutes of host inactivity. enable state is preserved until rece iving a disable automatic off-line command. upon receipt of the smart enable/disable automatic off-line co mmand, the device sets bsy to one, enabl es or disables the automatic off-line data correction feature, clear bsy to zero and asserts intrq. during execution of its off-line data collection activities and saving t he data on the disk, drdy and bsy are set to zero. a command is issued during execution of its off-line dat a collection activities and saving t he data on the disk, the device will respond to the host within two seconds.
k6610168 rev.1 nov 19, 2004 - 108 - 7.5.46. smart enable/disable attr ibute autosave [b0h, sub d2h] task file registers 7 6 5 4 3 2 1 0 command b0h lba high c2h lba mid 4fh lba low xx device/head x x x drv x x x x sector count 00h: di sable, f1h: enable features d2h the smart enable/disable attribute autosave co mmand enables and disables the attribute auto save feature of the device. the st ate of the attribute auto save feat ure (either enable or disable) will be preserved by the device across power cycles. a value of zero written by the host into the sector c ount register before issuing this command will cause this feature to be disabled. disabling th is feature does not prec lude the device from saving attribute values to non-volatile memory during some other normal operation. a value of f1h written by the host into the sector count register before issuing this comm and will cause this feature to be enabled. upon receipt of the command from the host, the device se ts bsy, enables or disables the auto save feature, clears bsy, and asserts intrq. during execution of the auto save routine the device does not assert bsy nor de-assert drdy. if the device receives a command from the host while executing its auto save routine, the device will respond to the host within two seconds.
k6610168 rev.1 nov 19, 2004 - 109 - 7.5.47. smart enable operations [b0h, sub d8h] task file registers 7 6 5 4 3 2 1 0 command b0h lba high c2h lba mid 4fh lba low xx device/head x x x drv x x x x sector count xx features d8h the smart enable operations command enables access to all smart capabilities within the device. prior to receipt of this command attribute values are neither monitored nor saved by the device. the device will preserve the state of smart (either enabled or disabled) across power cycles. once enabled, the receipt of subsequent smart enable o perations commands does not affect any of the attribute values. if the values in the features, lba mid (cylinder low), or lba high (cylinder high) registers are invalid, an aborted command error is posted. upon receipt of this command from the host, t he device sets bsy, enables smart capabilities and functions, clears bsy, and asserts intrq.
k6610168 rev.1 nov 19, 2004 - 110 - 7.5.48. smart execute off-line immediate [b0h, sub d4h] task file registers 7 6 5 4 3 2 1 0 command b0h lba high c2h lba mid 4fh lba low sub command specific device/head x x x drv x x x x sector count xx features d4h the smart execute off-line immediate command caus es the device to imm ediately initiate the optional set of off-line data collecti on activities that collect attribut e data in an off-line mode and then save this data to the device, or execut e a self-diagnostic test routine in either captive or off-line mode. the device reports command aborted if sm art is not enabled, if register val ues are invalid, or if a self-test fails while executing a sequence in c aptive mode. also, the device sets f4h to lba mid register and sets 2ch to lba high register when the subcommand specified a captive self-test rout ine which has failed during execution. the device sets 4fh to lba mid register and sets c2h to lba high register when the subcommand specified a captive self-test routine and some erro r other than a self-test routine failure occurred. table 7.28 11 smart execute off-line immediate lba low register values value description of subcommand to be executed 0 execute smart off-line routi ne immediately in off-line mode 1 execute smart short self-test r outine immediately in off-line mode 2 execute smart extended self-test r outine immediately in off-line mode 3 reserved 4 execute smart selective self-test routine immediately in off-line mode 5 - 63 reserved 64 - 125 reserved (vendor specific) 126 abort off-line mode off-li ne routine (vendor specific) 127 abort off-line mode self-test routine 128 reserved 129 execute smart short self-test r outine immediately in captive mode 130 execute smart extended self-test r outine immediately in captive mode 131 reserved 132 execute smart selective self-test routine immediatel y in captive mode 133- 191 reserved 192 - 255 reserved (vendor specific)
k6610168 rev.1 nov 19, 2004 - 111 - 7.5.48.1. off-line mode the following describes the protocol for exec uting a smart execute off-line immediate sub command routine (including a self-tes t routine) in the off-line mode. a) the device executes command completion before executing the subcommand routine. b) after clearing bsy to zero and setting drdy to one after receiving the comm and, the device does not set bsy nor clears drdy during execut ion of the subc ommand routine. c) if the device is in the process of performing the sub command routine and is interrupted by any new command from the host except a sleep, sm art disable operations, smart execute off- line immediate or standby immediate comm and, the device suspends or aborts the sub command routine and services the host within two seconds after receipt of the new command. after servicing the interrupting command from t he host the device immedi ately resumes the sub command routine without any addi tional commands from the host. d) if the device is in the process of performing a off-line routine and is interrupted by a sleep command from the host, the device suspends the off-line routine and services the host after receipt of the command. if the device is in the process of perform ing any self-test routine and is interrupted by a sleep command from the host, the device aborts the self-test routine and se rvices the host after receipt of the command. e) if the device is in the process of performing the subcommand routine and is interrupted by a smart disable operations command from the host, t he device aborts the s ubcommand routine and services the host within two seconds after receipt of the command. f) if the device is in the process of performing the subcommand routine and is interrupted by a smart execute off-line immediate command from the host, the device aborts t he subcommand routine and services the host within two seconds after rece ipt of the command. the device then services the new smart execute off-line immediate subcommand. g) if the device is in the process of performing the off-line routine and is interrupted by a standby immediate command from the host, the device sus pends the subcommand rout ine, and services the host within two seconds after rece ipt of the command. after receivi ng a new command that causes the device to exit a power saving mode, the device re sumes the off-line routine without any additional commands from the host unless these ac tivities were aborted by the host. h) if the device is in the process of performing t he self-test routine and is interrupted by a standby immediate command from the host, the device aborts the self-test routine, and services the host within two seconds after receipt of the command. i) while the device is performing the subcommand routine it does not automatica lly change power states (e.g., as a result of its standby timer expiring). if an error occurs while a device is performing a self-test routine the device disc ontinues the testing and places the test results in the self-test execution status byte.
k6610168 rev.1 nov 19, 2004 - 112 - 7.5.48.2. captive mode when executing a self-test in capt ive mode, the device sets bsy to one and executes the se lf-test routine after receipt of the command. at the end of the routine the devic e places the results of this routine in the self-test execution status byte and executes command completion. if an error occurs while a device is performing the routine the dev ice discontinues its testing, place the results of this routine in the self-test execution status byte, and complete the command. 7.5.48.3. smart off-line routine this routine only is performed in the off- line mode. the following tests are performed: a) raw read error rate measurement partial read scanning and raw read error rate measurement is performed. b) automatic sector r eallocation in off-line read scanning for entire lba. 7.5.48.4. smart short self-test routine depending on the value in the lba low (sector number) regi ster, this self-test routi ne is performed in either the captive or the off-line or mode. th is self-test routine should take on t he order of two minutes to complete. the following tests are performed for t he smart short self-test routine: a) read test - partial read scanning and raw r ead error rate measurement is performed. b) write test - a part of the factory data area is used. write and read test is performed for each head. c) servo test - position error signal is checked for certain rotati ons in order to analyze rro and settling accuracy. - load and unload function is tested. - servo data on the outer track of each zone for each head is verified. d) partial read scan test for the firs t 500mb and the last 300mb 0f the device. e) random read test - average seek time and th roughput performance are measured in this test. f) ram test - diagnoses buffer ram and sdram. g) smart parameter verify - dete cts a threshold exceed condition. h) smart error log check - read scanning for sm art error log sector and verify validity. 7.5.48.5. smart extended self-test routine depending on the value in the lba low (sector number) register, this self-test routine is performed in either the captive or the off- line mode. this self-test rout ine takes on the order of tens of minutes to complete. smart extended self-test routine performs read scanning test for entire lba in addition to the above smart short self-test routine (exc ept the partial read scan test). 7.5.48.6. smart select ive self-test routine depending on the value in the lba low (sector number) register, this self-test routine is performed in either the captive mode or the off- line mode. in addition to the above smar t short self-test routine (except the partial read scan test), smart se lective self-test routine performs r ead scanning test for up to five areas of the media specified by user. to do this, a user shall set the test s pans desired in selective self-test log (log sector address # 09h) using write smart log co mmand. after the scan of the selected areas, the user may wish to have the rest of media read scanned as an off-line scan. in this case, the user shall set the flag of selective self-test log to enable off-line scan.
k6610168 rev.1 nov 19, 2004 - 113 - 7.5.49. smart read log sector [b0h, sub d5h] task file registers 7 6 5 4 3 2 1 0 command b0h lba high c2h lba mid 4fh lba low log address device/head x x x drv x x x x sector count number of sector to be read features d5h the smart read log sector command returns the indicated log to the host. lba low (sector number) register indicates the log to be returned as described in table 7.11. the host vendor specific logs may be used by the host to store any data des ired. if a host vendor specific log has never been written by the host, when read the content of the log is zeros. device vendor specific logs are used by the device vendor to store any data.
k6610168 rev.1 nov 19, 2004 - 114 - 7.5.49.1. smart log directory [log sector address = 00h] the smart log directory is reported si ze of each log sector address. the following table defines 512 bytes that make up the smart log directory. the va lue of the smart logging version word is 01h. table 7.29 smart log directory byte description 0 - 1 smart logging version 2 number of sectors in the log at log sector address 01h 3 reserved : : 510 number of sectors in the log at log sector address ffh 511 reserved 7.5.49.2. summary smart error log [log sector address = 01h] the last five 28-bit error entries t hat device reported are gathered in summa ry smart error log. only 28-bit error entries contain in summary smart error log. the following table defines the 512 bytes that make up the summary smart error log. error log data struct ure includes unc errors, idnf errors for which the address requested was valid, servo errors, write fault erro rs, etc. they do not include errors attributed to the receipt of faulty commands such as command codes not implemented by the device or requests with invalid parameters or invalid addresses. table 7.30 summary smart error log byte description 0 smart error log version the value of the smart error log version is 01h. 1 error log index the error log index indicates the error log data structure represent ing the most recent error. only values 1 through 5 are valid. 2-91 first error log data structure 92-181 second error log data structure 182-271 third error log data structure 272-361 fourth error log data structure 362-451 fifth error log data structure 452-453 device error count this contains the total number of errors attributable to the device that have been reported by the device during the life of t he device. these errors include unc errors, idnf errors for which the address requested wa s valid, servo errors, write fault errors, etc. this count is not include errors attri buted to the receipt of faulty commands such as commands codes not implemented by the device or requests with invalid parameters or invalid addresses. if the maxi mum value for this field is reached, the count remains at the maximum value when additional errors are encountered and logged. 454-510 reserved 511 data structure checksum this is the two's complement of the sum of the first 511 bytes in the data structure. each byte is added with unsigned arit hmetic, and overflow is ignored.
k6610168 rev.1 nov 19, 2004 - 115 - (1) error log data structure an error log data structure is presented for each of the last five errors r eported by the device. these error log data structure entries are view ed as a circular buffer. that is, the fi rst error creates the first error log data structure; the second error, the se cond error log structure; etc. the sixth error creates an error log data structure that replaces t he first error log data structure; the sev enth error replaces the second error log structure, etc. the error log pointer indicates the most recent error log structure. if fewer than five errors have occurred, the unused error log st ructure entries are zero filled. the following table describes the content of a valid erro r log data structure. table 7.31 error log data structure byte description n ~ n+11 first command data structure n+12 ~ n+23 second command data structure n+24 ~ n+35 third command data structure n+36 ~ n+47 fourth command data structure n+48 ~ n+59 fifth command data structure n+60 ~ n+89 error data structure (2) command data structure the fifth command data structure cont ains the command or reset for whic h the error is being reported. the fourth command data structure cont ains the command or reset that preceded the command or reset for which the error is being reported, the third comm and data structure contains the command or reset preceding the one in the fourth co mmand data structure, etc. if fewe r than four commands and resets preceded the command or reset for which the error is being reported, the unused command data structures are zero filled. if the command data structure represents a command or software reset, the content of the command data structure is as shown in followi ng table. if the command data structur e represents a hardware reset, the content of byte n is ffh, the cont ent of bytes n+1 through n+7 are not valid, and the content of bytes n+8 through n+11 contains the timestamp. table 7.32 command data structure byte description n content of device control register when the command register was written. n+1 content of features register w hen the command register was written. n+2 content of sector count register when the command register was written. n+3 content of lba low (sector number) regi ster when the command register was written. n+4 content of lba mid (cylinder low) regist er when the command register was written. n+5 content of lba high (cylinder high) regi ster when the command register was written. n+6 content of device/head register w hen the command register was written. n+7 content written to the command register. n+8 ~ n+11 timestamp this is the time since power-on in m illiseconds when command a cceptance occurred.
k6610168 rev.1 nov 19, 2004 - 116 - (3) error data structure the error data structure contains the error description of the command for which an error was reported as described in following. table 7.33 error data structure byte description n reserved n+1 content of the error register after command completion occurred. n+2 content of the sector count regi ster after command completion occurred. n+3 content of the lba low (sector number) register after command completion occurred. n+4 content of the lba mid (cylinder low) register after command completion occurred. n+5 content of the lba high (cylinder high) register after command completion occurred. n+6 content of the device/head regist er after command completion occurred. n+7 content written to the status regi ster after command completion occurred. n+8 ~ n+25 extended error info rmation (vendor specific) n+27 state this contains a value indica ting the state of the device w hen command was written to the command register or the reset occurred as described below. 01h: sleep 02h: standby 03h: active/idle with bsy cleared to zero 04h: executing smart off-line or self-test n+28 ~ n+29 life timestamp this contains the power- on lifetime of the device in hours when command completion occurred.
k6610168 rev.1 nov 19, 2004 - 117 - 7.5.49.3. comprehensive smart erro r log [log sector address = 02h] the last 255 errors that device repor ted are gathered in comprehensive smart error log. only 28-bit error entries contain in comprehensive sm art error log. following table def ines the format of each of the sectors that comprise the comprehensive smart e rror log. the maximum size of the comprehensive smart error log is 51 sectors. the comprehensive smart error log data structures include unc errors, idnf errors for which the address requested was valid, servo errors, write fault errors, etc. comprehensive smart error log data structures do not include errors attributed to the re ceipt of faulty commands such as command codes not supported by the device or requests with inva lid parameters or invalid addresses. the error log is viewed as a circular buffer. when the last supported erro r log sector has been filled, the next error creates an error log data structur e that replaces the firs t error log data structure in sector zero. the next error after that creates an error log data structure that replaces t he second error log data structure in sector zero. the sixth error after the log has filled repl aces the first error log data structure in sector one, and so on. unused error log data structures are filled with zeros. the content of the error l og data structure entries is defined in table 7.31. table 7.34 comprehensive smart error log sector byte description first sector 0 smart error log version the value of the smart error log version is 01h. 1 error log index the error log index indicates the error log data structure representing the most recent error. only values 1 through 255 are valid. 2 - 91 first error log data structure 92 - 181 second error log data structure 182 - 271 third error log data structure 272 - 361 fourth error log data structure 362 - 451 fifth error log data structure 452 - 453 device error count this contains the total number of errors attributable to the device that have been reported by the device during the life of t he device. if the maximum value for this field is reached, the count remains at the maximum value when additional errors are encountered and logged. 454 - 510 reserved 511 data structure checksum the data structure checksum is the two's complement of the sum of the first 511 bytes in the first sector. subsequent 0 - 2 reserved sector 2 - 91 (5n + 1) error log data structure n 92 -181 (5n + 2) error log data structure 182 - 271 (5n + 3) error log data structure 272 - 361 (5n + 4) error log data structure 362 - 451 (5n + 5) error log data structure 452 - 510 reserved 511 data structure checksum the data structure checksum is the two's complement of the sum of the first 511 bytes in the subsequent sector.
k6610168 rev.1 nov 19, 2004 - 118 - 7.5.49.4. smart self-test log [log sector address = 06h] the last twenty-first results of smart short self-tes t routine, extended self-test routine and smart selective self-test routine are gathered in smart self-test log. only 28-bit entries c ontain in the smart self-test log. following table defines the 512 bytes that make up the smart self-test log. table 7.35 smart self-test log byte description 0 - 1 self-test log data structure revision number the value of self-test log data structure revision number is 0001h 2 - 25 1 st descriptor entry 26 - 49 2 nd descriptor entry : : 482 - 505 21 st descriptor entry 506 - 507 vendor specific 508 self test index the self-test index points to the most recent entry. initially, w hen the log is empty, the index is set to zero. it is set to one when the first entry is made, two for the second entry, etc., until the 22nd entry, when the index is reset to one. 509 - 510 reserved 511 data structure checksum (1) self-test log descriptor entry this log is viewed as a circular buffe r. the first entry begins at byte 2, the second entry begins at byte 26, and so on until the twenty-second entry, t hat replaces the first entry. then, the twenty-third entry replaces the second entry, and so on. if fewer than 21 self-t ests have been performed by the device, the unused descriptor entries are filled with zeros. the content of the self-test descripto r entry is shown in following table. table 7.36 self-test log descriptor entry byte description n content of the lba low (sector number) register this contains the cont ent of the lba low (sector numbe r) register when the nth self-test subcommand was issued. n+1 content of the self-tes t execution status byte this contains the result of self-test r outine when the nth self -test was completed. n+2 ~ n+3 life timestamp this contains the power-on lifetime of the device in hours when the nth self-test subcommand was completed. n+4 content of the self-test failure checkpoint byte (vendor specific) this contains additional in formation about the self-tes t routine that failed. n+5 ~ n+8 falling lba the failing lba is the lba of the uncorrectable sector that caused the test to fail. if the device encountered more than one unc orrectable sector during the test, this field indicates the lba of the first uncorrectabl e sector encountered. if the test passed or the test failed for some reason other than an uncorrectable sector , the value of this field is undefined. n+9 ~ n+23 vendor specific
k6610168 rev.1 nov 19, 2004 - 119 - 7.5.49.5. smart select ive self-test log [log sector address = 09h] the smart selective self-test log is a log that may be both written and r ead by the host. this log allows the host to select the parameters for the self-test and to monitor the progress of the self-test. following table defines the content of the se lective self-test log. the smart selective self-test log provides for the definition of up to five test spans. the starting lba for each test span is the lba of the first sector tested in the test span and the ending lba for each test s pan is the last lba tested in the test span. if the starting and ending lba values for a test span are both zero, a test s pan is not defined and not test ed. these values shall be written by the host. the host shall not write the smart selective self-t est log while the execution of a selective self-test routine is in progress. table 7.37 smart selective self-test log byte description 0 - 1 data structure revision number - this field shall be written as ?01h? by the host. 2 - 9 starting lba for test span #1 10 - 17 ending lba for test span #1 : : 66 - 73 starting lba for test span #5 74 - 81 ending lba for test span #5 82 - 337 reserved - this bit shall be written as zeros by the host 338 - 491 vendor specific - this bit s hall be written as zeros by the host 492 - 499 current lba under test read as the self-test progresses, the device modifies this value to contain the beginning lba of the 65,536 sector block currently being tested. when the self-test including the off-line scan between test spans has been completed, a zero value is placed in this field. this field shall be written with a value of zero by the host. 500 - 501 current span under test read as the self-test progresses, the device modifies th is value to contain the test span number of the current span being tested. if an off-line scan betw een test spans is selected, a value greater then five is placed in this field during the off- line scan. when the self-test including the off-line scan between test spans has been completed, a zero value is placed in this field. this field shall be written with a value of zero by the host. 502 - 503 feature flags bit 15 - 5 reserved - these bits shall be written as zeros by the host bit 4 off-line scan active flag when set to one, off-line scan after selective test is active. this bit shall be written as zeros by the host and the device modifies t hem as the test progresses. bit 3 off-line scan pending flag when set to one, off-line scan after selective test is pending. this bit shall be written as zeros by the host and the device modifies them as the test progresses. bit 2 vendor specific - this bit s hall be written as zeros by the host bit 1 perform off-line read scan after selective self-test when set to one, perform off-line scan after select ive test. this bit shall be written by the host and returned unmodified by the device bit 0 vendor specific - this bit s hall be written as zeros by the host 504 - 507 vendor specific - this bit s hall be written as zeros by the host 508 - 510 selective self-test pending time this field is the time in minutes from power-on to the resumption of the off-line testing if the pending bit is set. at the expiration of this time, se ts the active bit to one, and resumes the off-line scan that had begun before power-down. 511 data structure checksum this field is the two's complement of the sum of the first 511 bytes in the sector .
k6610168 rev.1 nov 19, 2004 - 120 - 7.5.50. smart return status [b0h, sub dah] task file registers 7 6 5 4 3 2 1 0 command b0h lba high c2h lba mid 4fh lba low xx device/head x x x drv x x x x sector count xx features dah the smart return status command is used to communica te the reliability status of the device to the host at the host?s request. upon receipt of this co mmand the device sets bsy, saves any updated attribute values to non-volatile memory, and compares the updat ed attribute values to t he attribute thresholds. if the device has not detected a thre shold exceeded condition, the device sets the lba mid (cylinder low) register to 4fh and the lba high (cylinder high) regi ster to c2h. if the devic e has detected a threshold exceeded condition, the device sets t he lba mid (cylinder low) register to f4h and the lba high (cylinder high) register to 2ch. if smart is disabled or if the values in the features, lba mid (cylinder low), or lba high (cylinder high) registers are inva lid, an aborted command error is posted. 7.5.51. smart save attribute values [b0h, sub d3h] task file registers 7 6 5 4 3 2 1 0 command b0h lba high c2h lba mid 4fh lba low xx device/head x x x drv x x x x sector count xx features d3h the smart save attribute values command causes the device to immediately save any updated attribute values to the device?s non-volatile memory regar dless of the state of the attribute auto save timer. upon receipt of this command from the host, the devic e sets bsy, writes any updated attribute values to non-volatile memory, clears bsy, and asse rts intrq. if smart is disabled or if the values in the features, lba mid (cylinder low), or lba high (cylinder high) registers are invalid, an aborted command error is posted.
k6610168 rev.1 nov 19, 2004 - 121 - 7.5.52. smart write log sector [b0h, sub d6h] task file registers 7 6 5 4 3 2 1 0 command b0h lba high c2h lba mid 4fh lba low log address device/head x x x drv x x x x sector count number of sector to be written features d6h the smart write log sector command writes an indi cated number of 512 byte data sector to the indicated log sector. host vendor s pecific logs are used by the host to store any data desired using the smart write log sector command. lba low (sector nu mber) register indicated the log to be written as described in table 7.11. if the host attempts to write to a read only log address, the device returns command aborted. 7.5.53. standby [96h, e2h] task file registers 7 6 5 4 3 2 1 0 command 96h or e2h lba high xx lba mid xx lba low xx device/head x x x drv x x x x sector count standby timer value features xx the standby command causes the devic e to enter the standby mode. the se ctor count register sets the standby timer value (refer to table 7.10). by the power on default, the standby timer is disabled.
k6610168 rev.1 nov 19, 2004 - 122 - 7.5.54. standby immediate [94h, e0h] task file registers 7 6 5 4 3 2 1 0 command 94h or e0h lba high xx lba mid xx lba low xx device/head x x x drv x x x x sector count xx features xx the standby immediate command causes the device to be spun down and enter the standby mode. the device returns an interrupt before it has complete transition to the standby mode.
k6610168 rev.1 nov 19, 2004 - 123 - 7.5.55. write buffer [e8h] task file registers 7 6 5 4 3 2 1 0 command e8h lba high xx lba mid xx lba low xx device/head x x x drv x x x x sector count xx features xx the write buffer command allows the host to write 512 by tes of data to the sector buffer of the device. when the write buffer command and the read bu ffer command are issued consecutively, the same data is read. 7.5.56. write dma [cah, cbh] task file registers 7 6 5 4 3 2 1 0 command cah or cbh lba high l = 0: cylinder number bit 15 - 8 l = 1: 28-bit lba address bit 23 - 16 lba mid l = 0: cylinder number bit 7 - 0 l = 1: 28-bit lba address bit 15 - 8 lba low l = 0: sector number l = 1: 28-bit lba address bit 7 - 0 device/head x l x drv l = 0: head number l = 1:28-bit lba address bit 27-24 sector count sector count features xx this command executes in a similar manner to t he write sectors command except for the followings: - the host initializes a slave-dma c hannel prior to issuing the command. - data transfers are qualified by dmarq and are performed by the slave-dma channel. - the device issues only one interrupt per command to indicate that data tr ansfer has terminated and status is valid. if an error occurs, the write terminates at the se ctor where the error occurred. the command block registers contain the cylinder, head, and sector numbers or 28-bit lba address where the error occurred.
k6610168 rev.1 nov 19, 2004 - 124 - 7.5.57. write dma ext [35h] task file register 7 6 5 4 3 2 1 0 command 35h feature previous setting xx current setting xx lba high previous setting lba bit 47 - 40 current setting lba bit 23 - 16 lba mid previous setting lba bit 39 - 32 current setting lba bit 15 - 8 lba low previous setting lba bit 31 - 24 current setting lba bit 7 - 0 sector count previous setting sector count bit 15 - 8 current setting sector count bit 7 - 0 device x 1 x dev x x x x this command executes in a similar manner to the write sectors ext command except for the followings: - the host initializes a slave-dma c hannel prior to issuing the command. - data transfers are qualified by dmarq and are performed by the slave-dma channel. - the device issues only one interrupt per command to indicate that data tr ansfer has terminated and status is valid. if an error occurs, the write terminates at the se ctor where the error occurred. the command block registers contain the 48-bit lba address where the error occurred. 7.5.58. write dma fua ext [3dh] task file register 7 6 5 4 3 2 1 0 command 3dh feature previous setting xx current setting xx lba high previous setting lba bit 47 - 40 current setting lba bit 23 - 16 lba mid previous setting lba bit 39 - 32 current setting lba bit 15 - 8 lba low previous setting lba bit 31 - 24 current setting lba bit 7 - 0 sector count previous setting sector count bit 15 - 8 current setting sector count bit 7 - 0 device x 1 x dev x x x x the write dma fua ext command provides the same function as the write dma ext command except that regardless of whether wr ite caching in the device is enabled or not, the user data is written to the media before ending status fo r the command is reported.
k6610168 rev.1 nov 19, 2004 - 125 - 7.5.59. write log ext [3fh] task file register 7 6 5 4 3 2 1 0 command 3fh feature previous setting xx current setting xx lba high previous setting reserved current setting reserved lba mid previous setting sector offset bit 15 - 8 current setting sector offset bit 7 - 0 lba low previous setting reserved current setting log sector address sector count previous setting sector count bit 15 - 8 current setting sector count bit 7 - 0 device x x x drv x x x x the write log ext command writes a specified number of 512 byte data se ctors to the specified log. if the feature set associated with the log specified in the lba low register is not supported or enabled, or if the values in the features, sector count, lba mid, or lba high registers are invalid, the device returns command aborted. if the host attempts to write to a read only (ro) log address, the device returns command aborted. - sector count register: specifies the number of sectors that shall be written to the specified log. if the number is greater than the number indicated in the log directory (which is available in log number zero), the device returns command aborted. the log transferred to the device is stored by the devic e starting at the first sector in the specified log. - lba low register: specifies the log to be written as described in tabl e 7.11. if the host attempts to write to a read only (ro) log address, the device returns command aborted. - lba mid register: specifies the first sector of the log to be written.
k6610168 rev.1 nov 19, 2004 - 126 - 7.5.60. write long [32h, 33h] task file registers 7 6 5 4 3 2 1 0 command 32h or 33h lba high l = 0: cylinder number bit 15 - 8 l = 1: 28-bit lba address bit 23 - 16 lba mid l = 0: cylinder number bit 7 - 0 l = 1: 28-bit lba address bit 15 - 8 lba low l = 0: sector number l = 1: 28-bit lba address bit 7 - 0 device/head x l x drv l = 0: head number l = 1: 28-bit lba address bit 27-24 sector count 01h features xx the write long command is similar to the write sec tors command, except t hat it writes the data and the ecc bytes directly from t he host; the device does not generate t he ecc bytes itself. only single sector write long operations are suppor ted. the transfer of the ecc byte s shall be 8-bits wide. the number of ecc bytes transferred will be 4 bytes (default). if the ecc transfer length is changed by features register = 44h, 68 bytes of ecc will be transferred. 7.5.61. write multiple [c5h] task file registers 7 6 5 4 3 2 1 0 command c5h lba high l = 0: cylinder number bit 15 - 8 l = 1: 28-bit lba address bit 23 - 16 lba mid l = 0: cylinder number bit 7 - 0 l = 1: 28-bit lba address bit 15 - 8 lba low l = 0: sector number l = 1: 28-bit lba address bit 7 - 0 device/head x l x drv l = 0: head number l = 1: 28-bit lba address bit 27-24 sector count sector count features xx
k6610168 rev.1 nov 19, 2004 - 127 - the write multiple command is similar to the wr ite sectors command, except interrupts are not generated on every sector, but on the tr ansfer of a block which contains the number of sectors defined by the set multiple mode command. the number of sectors defined by the set multiple mode command is transferred without interv ening interrupts. drq qualification of the transfer is required only at the start of the data block, not on each sector. the set multiple mode command, which must be executed prior to the write multiple command, sets the block count of sectors to be transferred. when the write multiple command is issued, the sector count register contains the number of sectors (not the number of blocks or the block count) requested. if the number of requested sector is not evenly divisible by the block count, as many full blocks as po ssible are transferred, followed by a final, partial block transfer. the partial block transfer shall be for n sector s, where n = residue of {sec tor count / (sector count per block)} disk errors encountered during write multiple commands are posted after the attempted disk write of the block or partial block transferred. the write operati on ends with the sector in error, regardless of the position in the block. s ubsequent blocks are not transferred in the ev ent of an error. interrupts are generated when drq is set at the beginning of transfe r of each block, except first block. 7.5.62. write multiple ext [39h] task file register 7 6 5 4 3 2 1 0 command 39h feature previous setting xx current setting xx lba high previous setting lba bit 47 - 40 current setting lba bit 23 - 16 lba mid previous setting lba bit 39 - 32 current setting lba bit 15 - 8 lba low previous setting lba bit 31 - 24 current setting lba bit 7 - 0 sector count previous setting sector count bit 15 - 8 current setting sector count bit 7 - 0 device x 1 x dev x x x x the write multiple ext command is similar to t he write sectors ext command, except interrupts are not generated on every sector, but on the transfer of a block which contains the number of sectors defined by the set multiple mode command. the number of sectors defined by the set multiple mode command is transferred without intervening interr upts. drq qualification of the transfer is required only at the start of the data blo ck, not on each sector. the set mult iple mode command, which must be executed prior to the write multiple ext command, se ts the block count of sectors to be transferred. when the write multiple ext command is issued, the sector count register contains the number of sectors (not the number of blocks or the block count ) requested. if the number of requested sector is not
k6610168 rev.1 nov 19, 2004 - 128 - evenly divisible by the block count, as many full blocks as possible are transferred, followed by a final, partial block transfer. the partial block transfer shall be for n sectors, where n = residue of {sector count / (sector count per block)} disk errors encountered during write multiple ext co mmands are posted after the attempted disk write of the block or partial block transferred. the write operat ion ends with the sector in error, regardless of the position in the block. s ubsequent blocks are not transferred in the ev ent of an error. interrupts are generated when drq is set at the beginning of transfe r of each block, except first block. 7.5.63. write multiple fua ext [ceh] task file register 7 6 5 4 3 2 1 0 command ceh feature previous setting xx current setting xx lba high previous setting lba bit 47 - 40 current setting lba bit 23 - 16 lba mid previous setting lba bit 39 - 32 current setting lba bit 15 - 8 lba low previous setting lba bit 31 - 24 current setting lba bit 7 - 0 sector count previous setting sector count bit 15 - 8 current setting sector count bit 7 - 0 device x 1 x dev x x x x the write multiple fua ext command provides t he same function as the write multiple ext command except that regardless of whether write cach ing in the device is enabled or not, the user data is written to the media before ending st atus for the command is reported.
k6610168 rev.1 nov 19, 2004 - 129 - 7.5.64. write sectors [30h, 31h] task file registers 7 6 5 4 3 2 1 0 command 30h or 31h lba high l = 0: cylinder number bit 15 - 8 l = 1: 28-bit lba address bit 23 - 16 lba mid l = 0: cylinder number bit 7 - 0 l = 1: 28-bit lba address bit 15 - 8 lba low l = 0: sector number l = 1: 28-bit lba address bit 7 - 0 device/head x l x drv l = 0: head number l = 1: 28-bit lba address bit 27-24 sector count sector count features xx the write sectors command transfers one or more se ctors from the host to the device. the data is then written to the media, beginning at the specified in the lba high (cy linder high), lba mid (cylinder low) and lba low (sector number) registers. at command completion, the command block register s contain the cylinder, head, and sector numbers or lba address of the last sector written. if an error o ccurs during a write of more than one sector, writing terminates at the sector where the error occurs. the command block registers contain the cylinder, head, and sector numbers or lba address of t he sector where the error occurred.
k6610168 rev.1 nov 19, 2004 - 130 - 7.5.65. write sectors ext [34h] task file register 7 6 5 4 3 2 1 0 command 34h feature previous setting xx current setting xx lba high previous setting lba bit 47 - 40 current setting lba bit 23 - 16 lba mid previous setting lba bit 39 - 32 current setting lba bit 15 - 8 lba low previous setting lba bit 31 - 24 current setting lba bit 7 - 0 sector count previous setting sector count bit 15 - 8 current setting sector count bit 7 - 0 device x 1 x dev x x x x the write sectors ext command transfers one or more sectors from the host to the device. the data is then written to the media, beginni ng at the specified in the lba hi gh, lba mid and lba low registers. at command completion, the command block registers cont ain 48-bit lba address of the last sector written. if an error occurs during a write of more than one sector , writing terminates at t he sector where the error occurs. the command block registers contain 48-bit l ba address of the sector where the error occurred.
k6610168 rev.1 nov 19, 2004 - 131 - 8.0 interface signal timing 8.1. data transfer timing figures 8-1, 8-2, and 8-3 show the timing fo r asserting interface signals for transferring 16-bit and 8-bit data. figure 8.1 pio data transfer timing (mode 4) *1 device address consists of signals cs0-, cs1-, and da2-0 *2 data consists of dd0-15(16 bit) or dd0-7(8 bit) symbol description min(ns) max(ns) t 0 cycle time 120 t 1 address valid to dior-/diow- setup 25 t 2 dior-/diow- pulse width 70 t 2 i dior-/diow- recovery 25 t 3 diow- data setup 20 t 4 diow- data hold 10 t 5 dior- data setup 20 t 6 dior- data hold 5 t 6z dior- data tristate 30 t 7 addr valid to iocs16- assertion(max) 40 t 8 addr valid to iocs16- negation (max) 30 t 9 dior-/diow- to address valid hold 10 t 1 t 9 t 7 t 2 t 3 t 5 t 4 t 6 addr valid *1 dior-/diow- write data valid *2 read data valid *2 iocs16- t 8 t 0 t 2i t 6z
k6610168 rev.1 nov 19, 2004 - 132 - figure 8.2 iordy timing symbol description min(ns) max(ns) t a iordy setup time 35 t b iordy pulse width 1250 t rd read data valid to iordy active 0 tc iordy assertion to release 5 t a t b dior-/diow- iordy t rd read data valid t c
k6610168 rev.1 nov 19, 2004 - 133 - figure 8.3 multi-word dma data transfer timing (mode 2) *3 data consists dd(15:0) symbol description min(ns) max(ns) t 0 cycle time 120 t d dior- /diow- pulse width 70 t e dior- data access 50 t f dior- data hold 5 t gr dior- data setup 20 t gw diow- data setup 20 t h diow- data hold 10 t i dmack to dior- / diow- setup 0 t j dior- / diow- to dmack hold 5 t k dior- / diow- negated pulse width 25 t l dior- / diow- to dmarq delay 35 t m cs(1:0) valid to dior-/diow- 25 t n cs(1:0) hold 10 t z dmack- to tristate 25 t m t 0 t l t i t d t k t j t gw t gr t h t f dmarq dmack- dior-/diow- write data valid *3 read data valid *3 cs0-/cs1- t n t e t z
k6610168 rev.1 nov 19, 2004 - 134 - 8.2. ultra dma data transfer timing figure 8.4 initiating an ultra dma read dmarq (device) dmack- (host) stop (host) hdmardy- (host) dstrobe (device) dd(15:0) t zad da0, da1, da2, cs0-, cs1- t ui t zad t ack t ack t env t env t ziordy t fs t fs t dvs t az t dvh t ack t dzfs t zfs note: the definitions for the stop, hdmardy and ds trobe signal lines are not in effect until dmarq and dmack are asserted. mode 0(ns) mode 1(ns) mode 2(ns) mode3(ns) mode4(ns) mode5(ns ) description symbol min max min max min max min max min max min max t dvs 70 48 31 20 6.7 4.8 data valid setup time at sender t dvh 6.2 6.2 6.2 6.2 6.2 4.8 data valid hold time at sender t fs 230 200 170 130 120 90 first strobe t ui 0 0 0 0 0 0 unlimited interlock t az 10 10 10 10 10 10 maximum time allowed for output drivers to release t zad 0 0 0 0 0 0 maximum delay time for output drivers turning on t env 20 70 20 70 20 70 20 55 20 55 20 50 envelope time t ziordy 0 0 0 0 0 0 minimum time waiting before driving iordy t zfs 0 0 0 0 0 35 time from strobe output released-to-driving until the first transition of critical timing t dzfs 70 48 31 20 6.7 25 time from data output released- to-driving until the first transition of critical timing t ack 20 20 20 20 20 20 setup and hold times before assertion and negation of dmack_
k6610168 rev.1 nov 19, 2004 - 135 - figure 8.5 sustained ultra dma read data t dvh dstrobe at device dd(15:0) at device dstrobe at host dd(15:0) at host t dvh t cyc t cyc t dvs t dvs t dh t ds t dh t ds t 2cyc t dh t dvh t 2cyc t dvhic t dvsic t dvhic t dvsic t dvhic t dhic t dsic t dhic t dsic t dhic note: dd(15:0) and dstrobe signals are shown at bot h the host and the device to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device. mode 0(ns) mode 1(ns) mode 2(ns) mode3(ns) mode4(ns) mode5(ns) description symbol min max min max min max min max min max min max t cyc 112 73 54 39 25 16.8 cycle time allowing for asymmetry and clock variation t2 cyc 230 153 115 86 57 38 two cycle time allowing for clock variation t ds 15 10 7 7 5 4 data setup time at recipient t dh 5 5 5 5 5 4.6 data hold time at recipient t dvs 70 48 31 20 6.7 4.8 data valid setup time at sender t dvh 6.2 6.2 6.2 6.2 6.2 4.8 data valid hold time at sender t dsic 14.7 9.7 6.8 6.8 4.8 2.3 recipient ic data setup time t dhic 4.8 4.8 4.8 4.8 4.8 2.8 recipient ic data hold time t dvsic 72.9 50.9 33.9 22.6 9.5 6.0 sender ic data valid setup time t dvhic 9.0 9.0 9.0 9.0 9.0 6.0 sender ic data valid hold time
k6610168 rev.1 nov 19, 2004 - 136 - figure 8.6 host pausing an ultra dma read dmarq (device) dmack- (host) stop (host) hdmardy- (host) dstrobe (device) dd(15:0) (device) t rfs t rp note: the host asserts stop to request termi nation of the ultra dma burst no sooner than t rp after hdmardy- is negated. mode 0(ns) mode 1(ns) mode 2(ns) mode3(ns) mode4(ns) mode5(ns) description symbol min max min max min max min max min max min max t rfs 75 70 60 60 60 50 ready-to-final strobe time t rp 160 125 100 100 100 85 ready-to-pause time
k6610168 rev.1 nov 19, 2004 - 137 - figure 8.7 device termination an ultra dma read t az t iordyz crc dmarq (device) dmack- (host) stop (host) hdmardy- (host) dstrobe (device) dd(15:0) da0, da1, da2, cs0-, cs1- t ack t li t mli t cvs t li t ack t ack t zah t cvh t ss t li note: the definitions for the stop, hdmardy and dstrobe signal lines are no longer in effect after dmarq and dmack are negated. mode 0(ns) mode 1(ns) mode 2(ns) mode3(ns) mode4(ns) mode5(ns) description symbol min max min max min max min max min max min max t cvs 70 48 31 20 6.7 10 crc word valid setup time at sender t cvh 6.2 6.2 6.2 6.2 6.2 10 crc word valid hold time at sender t li 0 150 0 150 0 150 0 100 0 100 0 75 limited interlock time t mli 20 20 20 20 20 20 interlock time with minimum t az 10 10 10 10 10 10 maximum time allowed for output drivers to release t zah 20 20 20 20 20 20 minimum delay time for output drivers turning on t iordyz 20 20 20 20 20 20 maximum time before releasing iordy t ack 20 20 20 20 20 20 setup and hold times before assertion and negation of dmack_ t ss 50 50 50 50 50 50 time from strobe edge to negation of dmarq or assertion of stop
k6610168 rev.1 nov 19, 2004 - 138 - figure 8.8 host terminating an ultra dma read t cvh crc t az dmarq (device) dmack- (host) stop (host) hdmardy- (host) dstrobe (device) dd(15:0) da0, da1, da2, cs0-, cs1- t ack t mli t li t li t iordyz t ack t ack t zah t mli t cvs t rfs t rp note: the definitions for the stop, hdmardy and ds trobe signal lines are no longer in effect after dmarq and dmack are negated. mode 0(ns) mode 1(ns) mode 2(ns) mode3(ns) mode4(ns) mode5(ns ) description symbol min max min max min max min max min max min max t cvs 70 48 31 20 6.7 10 crc word valid setup time at sender t cvh 6.2 6.2 6.2 6.2 6.2 10 crc word valid hold time at sender t li 0 150 0 150 0 150 0 100 0 100 0 75 limited interlock time t mli 20 20 20 20 20 20 interlock time with minimum t az 10 10 10 10 10 10 maximum time allowed for output drivers to release t zah 20 20 20 20 20 20 minimum delay time for output drivers turning on t rfs 75 70 60 60 60 50 ready-to-final-strobe time t rp 160 125 100 100 100 85 ready-to-pause time t iordyz 20 20 20 20 20 20 maximum time before releasing iordy t ack 20 20 20 20 20 20 setup and hold times before assertion and negation of dmack_
k6610168 rev.1 nov 19, 2004 - 139 - figure 8.9 initiating an ultra dma write dmarq (device) dmack- (host) stop (host) ddmardy- (device) hstrobe (host) dd(15:0) (host) da0, da1, da2, cs0-, cs1- t ui t ack t env t ziordy t li t dvs t dvh t ack t ack t ui t dzfs note: the definitions for the stop, ddmardy and hstrobe signal lines are not in effect until dmarq and dmack are asserted. mode 0(ns) mode 1(ns) mode 2(ns) mode3(ns) mode4(ns) mode5(ns) description symbol min max min max min max min max min max min max t dvs 70 48 31 20 6.7 4.8 data valid setup time at sender t dvh 6.2 6.2 6.2 6.2 6.2 4.8 data valid hold time at sender t li 0 150 0 150 0 150 0 100 0 100 0 75 limited interlock time t ui 0 0 0 0 0 0 unlimited interlock t env 20 70 20 70 20 70 20 55 20 55 20 50 envelope time t ziordy 0 0 0 0 0 0 minimum time before driving iordy t ack 20 20 20 20 20 20 setup and hold times before assertion and negation of dmack_ t dzfs 70 48 31 20 6.7 25 time from data output released-to-driving until the first transition of critical timing
k6610168 rev.1 nov 19, 2004 - 140 - figure 8.10 sustained ultra dma write data t dh t ds t dvh hstrobe at host dd(15:0) at host hstrobe at device dd(15:0) at device t dvh t cyc t cyc t dvs t dvs t ds t dh t 2cyc t dh t dvh t 2cyc t dvhic t dvsic t dvhic t dvsic t dvhic t dhic t dsic t dhic t dsic t dhic note: dd(15:0) and hstrobe signals are shown at bot h the device and the host to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host. mode 0(ns) mode 1(ns) mode 2(ns) mode 3(ns) mode 4(ns) mode5(ns) description symbol min max min max min max min max min max min max t cyc 112 73 54 39 25 16.8 cycle time allowing for asymmetry and clock variation t2 cyc 230 153 115 86 57 38 two cycle time allowing for clock variation t ds 15 10 7 7 5 4 data setup time at recipient t dh 5 5 5 5 5 4.6 data hold time at recipient t dvs 70 48 31 20 6.7 4.8 data valid setup time at sender t dvh 6.2 6.2 6.2 6.2 6.2 4.8 data valid hold time at sender t dsic 14.7 9.7 6.8 6.8 4.8 2.3 recipient ic data setup time t dhic 4.8 4.8 4.8 4.8 4.8 2.8 recipient ic data hold time t dvsic 72.9 50.9 33.9 22.6 9.5 6.0 sender ic data valid setup time t dvhic 9 9 9 9 9 6 sender ic data valid hold time
k6610168 rev.1 nov 19, 2004 - 141 - figure 8.11 device pausing an ultra dma write dmarq (device) dmack- (host) stop (host) ddmardy- (device) hstrobe (host) dd(15:0) (host) t rfs t rp note: the device negates dmarq to request termi nation of the ultra dma burst no sooner than t rp after ddmardy- is negated. mode 0(ns) mode 1(ns) mode 2(ns) mode 3(ns) mode 4(ns) mde5(ns) description symbol min max min max min max min max min max min max t rfs 75 70 60 60 60 50 ready-to-final strobe time t rp 160 125 100 100 100 85 ready-to-pause time
k6610168 rev.1 nov 19, 2004 - 142 - figure 8.12 host terminating an ultra dma write dmarq (device) dmack- (host) stop (host) ddmardy- (device) hstrobe (host) dd(15:0) (host) da0, da1, da2, cs0-, cs1- t ack t li t mli t cvs t li t li t ack t iordyz t ack crc t cvh t ss note: the definitions for the stop, ddmardy and hstrobe signal lines are no longer in effect after dmarq and dmack are negated. mode 0(ns) mode 1(ns) mode 2(ns) mode 3(ns) mode 4(ns) mode5(ns) description symbol min max min max min max min max min max min max t cvs 70 48 31 20 6.7 10 crc word valid setup time at sender t cvh 6.2 6.2 6.2 6.2 6.2 10 crc word valid hold time at sender t li 0 150 0 150 0 150 0 100 0 100 0 75 limited interlock time t mli 20 20 20 20 20 20 interlock time with minimum t az 10 10 10 10 10 10 maximum time allowed for output drivers to release t iordyz 20 20 20 20 20 20 maximum time before releasing iordy t ack 20 20 20 20 20 20 setup and hold times for dmack_ t ss 50 50 50 50 50 50 time from strobe edge to negation of dmarq or assertion of stop
k6610168 rev.1 nov 19, 2004 - 143 - figure 8.13 device terminating an ultra dma write dmarq (device) dmack- (host) stop (host) ddmardy- (device) hstrobe (host) dd(15:0) (host) da0, da1, da2, cs0-, cs1- t ack t mli t cvs t li t li t ack crc t cvh t ack t iordyz t mli t rp t rfs note: the definitions for the stop, ddmardy and hstrobe signal lines are no longer in effect after dmarq and dmack are negated. mode 0(ns) mode 1(ns) mode 2(ns) mode 3(ns) mode 4(ns) mode5(ns) description symbol min max min max min max min max min max min max t cvs 70 48 31 20 6.7 10 crc word valid setup time at sender t cvh 6.2 6.2 6.2 6.2 6.2 10 crc word valid hold time at sender t li 0 150 0 150 0 150 0 100 0 100 0 75 limited interlock time t mli 20 20 20 20 20 20 interlock time with minimum t rfs 75 70 60 60 60 50 ready-to-final- strobe time t rp 160 125 100 100 100 85 ready-to-pause time t iordyz 20 20 20 20 20 20 maximum time before releasing iordy t ack 20 20 20 20 20 20 setup and hold times for dmack_
k6610168 rev.1 nov 19, 2004 - 144 - 8.3. power on and hardware reset timing figure 8.14 power on and hardware reset timing symbol description min max units t m reset- pulse width 25 s t n0 drv 0 reset negation to bsy bit set to one, release pdiag- 400 ns t p0 drv 0 release dasp- 1 ms t r0 drv 0 sample of dasp- 1 450 ms t s drv 0 sample of pdiag- 1ms 31s - t r1 drv 1 assert dasp- 400 ms t n1 drv 1 negate pdiag- if asserted 1 ms t q drv 1 assert pdiag- 30 sec t m t n0 reset- bsy bit drv 0 t p0 t r0 dasp- drdy pdiag- t q drv 1 bsy bit t r1 t s dasp- pdiag- drdy t n1 dasp- ( out ) (in) (out) ( out ) (out) (device 0) ( device 1 )
k6610168 rev.1 nov 19, 2004 - 145 - < glossary > ata at attachment abrt aborted command amnf am not found apm advanced power management bios basic input-output system bpi bit per inch bsy busy cdr constant density recording chs cylinder head sector corr corrected data crc cyclic redundancy check css contact start/stop cyl cylinder dma direct memory accessing drv drive drdy drive ready drq data request dsc drive seek complete dwf drive write fault ecc error checking and correction err error gnd ground gb 1000,000,000 bytes hd head hda head/disk assembly hdd hard disk drive i/o input/output icrc interface crc error ide intelligent device electronics idnf id not found idx index mb 1000,000 bytes me 2 prml modified, extended, extended part ial response maximum likelihood pcba printed circuit board assembly pio programmed input-output p-p peak to peak rpm rotation per minute sc sector count register sec second smart self-monitoring, analys is and reporting technology spt sector per track srst software reset tk0nf track 0 not found tpi track per inch typ. typical unc uncorrectable ecc error
k6610168 rev.1 nov 19, 2004 - 146 - factory packaging the structure of the factory packaging is described in this reference. (1) packaging components no. name materials quantity 1 package box card box 1 2 hdd cushion card board 1 3 upper cushion card board 1 4 side cushion . card board 4 5 desiccant silica gel 50 6 vinyl package esd protective bags 50 (2) standard ident ification label the label is indicated on the exterior of the package. the following items will be based on user request. (a) hdd type (b) hdd serial number (c) package serial number (d) quantity

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