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128m gddr sdram k4d261638f - 1 - rev 1.5 (mar. 2005) 128mbit gddr sdram revision 1.5 march 2005 samsung electronics reserves the right to chan ge products or specification without notice. information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about samsu ng products, contact your nearest samsung office. 2. samsung products are not intended for use in life suppor t, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.
128m gddr sdram k4d261638f - 2 - rev 1.5 (mar. 2005) revision history revision 1. 5(march 17, 2005) ? added full output driver impedance in the emrs spec. revision 1. 4 (february 2, 2005) ? added -tc5a speed in the spec revision 1.3 (november 2, 2004) ? added ns scale bas ed ac spec table. ? removed -tc25 from the spec revision 1.2 (january 30, 2004) ? changed twr & twr_a of k4d261638f-tc25/2a/33/36 from 3tck to 4tck ? changed trc of k4d261638f-tc25 from 17tck to 18tck ? changed trc of k4d261638f-tc2a/33/36 from 15tck to 16tck ? changed tras of k4d261638f-tc25 from 12tck to 13tck. ? changed tras of k4d261638f-tc2a/33/36 from 10tck to 11tck. ? changed tdal of k4d261638f-tc 25/2a/33/36 from 8tck to 9tck revision 1.1 (january 7, 2004) ? added k4d261638f-tc25 in the spec. revision 1.0 (december 5, 2003) revision 0.9 (october 14, 2003) - preliminary spec ? defined dc spec revision 0.1 (octobe r 2, 2003) - target spec ? added lead free package part number in the datasheet revision 0.0 (augus t 6, 2003) - target spec ? defined target specification
128m gddr sdram k4d261638f - 3 - rev 1.5 (mar. 2005) the k4d261638f is 134,217,728 bits of hyper synchronous da ta rate dynamic ram organized as 4 x 2,097,152 words by 16 bits, fabricated with samsung ? s high performance cmos technology. synchronous features with data strobe allow extremely high performance up to 1.4gb/s/ chip. i/o transactions are possible on both edges of the clock cycle. range of operating frequencies, programmable burst length and program mable latencies allow the device to be useful for a variety of high performance memory system applications. ? 2.5v + 5% power supply for device operation ? 2.5v + 5% power supply for i/o interface ? sstl_2 compatible inputs/outputs ? 4 banks operation ? mrs cycle with address key programs -. read latency 3, 4 and 5(clock) -. burst length (2, 4 and 8) -. burst type (sequential & interleave) ? all inputs except data & dm are sampled at the positive going edge of the system clock ? differential clock input ? no wrtie-interrupted by read function general description features ? 2 dqs?s ( 1dqs / byte ) ? data i/o transactions on both edges of data strobe ? dll aligns dq and dqs tr ansitions with clock transition ? edge aligned data & data strobe output ? center aligned data & data strobe input ? dm for write masking only ? auto & self refresh ? 32ms refresh period (4k cycle) ? 66pin tsop-ii ? maximum clock frequency up to 350mhz ? maximum data rate up to 700mbps/pin for 2m x 16bit x 4 bank ddr sdram 2m x 16bit x 4 banks graphic do uble data rate synchronous dram with bi-directional data strobe and dll ordering information k4d261638f-lc is the lead free package part number. for the k4d261638f-tc2a, vdd & vddq = 2.8v+ 0.1v for the k4d261638f-tc5a, vdd & vddq = 2.4v to 2.7v part no. max freq. max data rate interface package k4d261638f-tc2a 350mhz 700mbps/pin sstl_2 66pin tsop-ii k4d261638f-tc33 300mhz 600mbps/pin k4d261638f-tc36 275mhz 550mbps/pin k4d261638f-tc40 250mhz 500mbps/pin k4d261638f-tc50 200mhz 400mbps/pin k4d261638f-tc5a 200mhz 400mbps/pin
128m gddr sdram k4d261638f - 4 - rev 1.5 (mar. 2005) pin configuration (top view) pin description ck,ck differential clock input ba 0 , ba 1 bank select address cke clock enable a 0 ~a 11 address input cs chip select dq 0 ~ dq 15 data input/output ras row address strobe v dd power cas column address strobe v ss ground we write enable v ddq power for dq ? s l(u)dqs data strobe v ssq ground for dq ? s l(u)dm data mask nc no connection rfu reserved for future use 1 66 pin tsop(ii) (400mil x 875mil) 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13 27 26 25 24 23 22 21 54 53 52 51 50 49 48 47 46 45 44 43 35 36 37 38 39 40 41 42 55 56 57 58 59 60 34 (0.65 mm pin pitch) 33 32 31 30 29 28 61 62 63 64 65 66 v dd dq 0 v ddq dq 1 dq 2 v ssq dq 3 dq 4 v ddq dq 5 dq 6 v ssq ba 0 cs ras cas we ldm v ddq dq 7 v dd a 3 a 2 a 1 a 0 ap/a 10 ba 1 nc ldqs nc nc nc v dd v ss dq 15 v ssq dq 14 dq 13 v ddq dq 12 dq 11 v ssq dq 10 dq 9 v ddq a 11 cke ck udm v ref v ssq dq 8 v ss a 4 a 5 a 6 a 7 a 8 a 9 nc udqs nc v ss ck nc nc
128m gddr sdram k4d261638f - 5 - rev 1.5 (mar. 2005) input/output functional description *1 : the timing reference point for the differential clocking is the cross point of ck and ck. for any applications using the single ended clocking, apply v ref to ck pin. symbol type function ck, ck *1 input the differential system clock input. all of the inputs are sampled on the rising edge of the clock except dq ? s and dm ? s that are sampled on both edges of the dqs. cke input activates the ck signal when high and deactivates the ck signal when low. by deactivating the cl ock, cke low indicates the power down mode or self refresh mode. cs input cs enables the command decoder when low and disabled the com- mand decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras input latches row addresses on the posi tive going edge of the ck with ras low. enables row access & precharge. cas input latches column addresses on the positive going edge of the ck with cas low. enables column access. we input enables write operation and row precharge. latches data in starting from cas , we active. ldqs,udqs input/output data input and output are synchronized with both edge of dqs. for the x16, ldqs corresponds to the data on dq0-dq7 ; udqs corresponds to the data on dq8-dq15. ldm,udm input data in mask. data in is masked by dm latency=0 when dm is high in burst write. for the x16, ldm corresponds to the data on dq0-dq7 ; udm correspons to the data on dq8-dq15. dq 0 ~ dq 15 input/output data inputs/outputs are multiplexed on the same pins. ba 0 , ba 1 input selects which bank is to be active. a 0 ~ a 11 input row/column addresses are mult iplexed on the same pins. row addresses : ra 0 ~ ra 11 , column addresses : ca 0 ~ ca 8 . v dd /v ss power supply power and ground for the input buffers and core logic. v ddq /v ssq power supply isolated power supply and ground for the output buffers to provide improved noise immunity. v ref power supply reference voltage for inputs, used for sstl interface. nc/rfu no connection/ reserved for future use this pin is recommended to be le ft "no connection" on the device
128m gddr sdram k4d261638f - 6 - rev 1.5 (mar. 2005) block diagram (2mbit x 16i/o x 4 bank) bank select timing register address register refresh counter row buffer row decoder col. buffer data input register serial to parallel 2mx16 2mx16 2mx16 2mx16 sense amp 2-bit prefetch output buffer i/o control column decoder latency & burst length programming register strobe gen. ck,ck addr lcke ck,ck cke cs ras cas we ldm ldmi ck,ck lcas lras lcbr lwe lwcbr lras lcbr ck, ck 32 16 16 lwe ldmi x16 dqi data strobe intput buffer dll udm
128m gddr sdram k4d261638f - 7 - rev 1.5 (mar. 2005) ? power-up sequence ddr sdrams must be powered up and initialized in a predef ined manner to preven t undefined ope rations. 1. apply power and keep cke at low state (all other inputs may be undefined) - apply vdd before vddq . - apply vddq before vref & vtt 2. start clock and maintain stable condition for minimum 200us. 3. the minimum of 200us after stable power and clock(ck,ck ), apply nop and take cke to be high . 4. issue precharge command for all banks of the device. 5. issue a emrs command to enable dll *1 6. issue a mrs command to reset dll. the add itional 200 clock cycles ar e required to lock the dll. * 1,2 7. issue precharge command for all banks of the device. 8. issue at least 2 or more auto-refresh commands. 9. issue a mode register set comma nd with a8 to low to in itialize the mode register. *1 the additional 200cycles of clo ck input is required to lock the dll after enabling dll. *2 sequence of 6&7 is regardless of the order. functional description power up & initialization sequence command 0 1 2 3 4 5 6 7 8 9 10111213141516171819 trp 2 clock min. precharge all banks 2nd auto refresh mode register set any command t rfc 1st auto refresh t rfc emrs mrs 2 clock min. dll reset ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ precharge all banks t rp inputs must be stable for 200us ~ ~ 200 clock min. ~ ~ 2 clock min. ck,ck * when the operating frequency is changed, dll reset should be required again. after dll reset again, the minimum 200 cycles of clock input is needed to lock the dll.
128m gddr sdram k4d261638f - 8 - rev 1.5 (mar. 2005) the mode register stores the data fo r controlling the various oper ating modes of ddr sdram. it programs cas latency, addressing mode, burst length, test mode, dll reset and vari ous vendor specific options to make ddr sdram useful for variety of different applications. the default value of the mode register is not defined, therefore the mode register must be written after emrs setting for proper operation. th e mode register is written by asserting low on cs , ras , cas and we (the ddr sdram should be in active mode with cke already high prior to writing into the mode register). the state of address pins a 0 ~ a 11 and ba 0 , ba 1 in the same cycle as cs , ras , cas and we going low is written in the mode register. minimum two clock cycles are requested to complete the write operation in the mode register. the mode register contents can be changed using the same command an d clock cycle requirements during operati on as long as all banks are in the idle state. the mode register is divided into various fiel ds depending on functionality. the burst length uses a 0 ~ a 2 , addressing mode uses a 3 , cas latency(read la tency from column address) uses a 4 ~ a 6 . a 7 is used for test mode. a 8 is used for dll reset. a 7, a 8 , ba 0 and ba 1 must be set to low for normal mrs operation. refer to the table for specific codes for various burst length, addressing modes and cas latencies. mode register set(mrs) address bus mode register cas latency a 6 a 5 a 4 latency 0 0 0 reserved 0 0 1 reserved 0 1 0 reserved 011 3 100 4 101 5 1 1 0 reserved 1 1 1 reserved burst length a 2 a 1 a 0 burst type sequential interleave 0 0 0 reserve reserve 001 2 2 010 4 4 011 8 8 1 0 0 reserve reserve 1 0 1 reserve reserve 1 1 0 reserve reserve 1 1 1 reserve reserve burst type a 3 type 0 sequential 1 interleave * rfu(reserved for future use) should stay "0" during mrs cycle. mrs cycle command *1 : mrs can be issued only at all banks precharge state. *2 : minimum t rp is required to issue mrs command. ck, ck precharge nop nop mrs nop nop 2 01 5 34 8 67 any nop all banks command t rp t mrd =2 t ck ba 1 ba 0 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 rfu 0 rfu dll tm cas latency bt burst length ba 0 a n ~ a 0 0mrs 1emrs dll a 8 dll reset 0no 1yes test mode a 7 mode 0normal 1test nop
128m gddr sdram k4d261638f - 9 - rev 1.5 (mar. 2005) the extended mode register stores the data for enabl ing or disabling dll and selecting output driver strength. the default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling dll. the extended mode register is written by assert- ing low on cs , ras , cas , we and high on ba0(the ddr sdram should be in all bank precharge with cke already high prior to writing into the extended mode regi ster). the state of address pins a0, a2 ~ a5, a7 ~ a11 and ba1 in the same cycle as cs , ras , cas and we going low are written in the extended mode register. a1 and a6 are used for setting driver strength to norma l, weak or matched impedance. two clock cycles are required to complete the write operation in the extended mode register. the mode register contents can be changed using the same command and cl ock cycle requirements during operation as long as all banks are in the idle state. a0 is used for dll enable or disable. "high" on ba0 is used for emrs. all the other address pins except a0,a1,a6 and ba0 must be set to low for pr oper emrs operation. refer to the table for specific codes. a 0 dll enable 0 enable 1 disable ba 0 a n ~ a 0 0mrs 1emrs extended mode register set(emrs) address bus extended *1 : rfu(reserved for future use) should stay "0" during emrs cycle. *2 : samsung would like to recommend "weak" output driver impedance in point-to-point application. but it?s possible to use by "full", if user system can support "full" output driver impedance. a 6 a 1 output driver impedence control *2 00 full 01 weak 11 matched rfu 1 rfu *1 d.i.c rfu d.i.c dll ba 1 ba 0 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 mode register
128m gddr sdram k4d261638f - 10 - rev 1.5 (mar. 2005) permanent device damage may occur if abso lute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. note : power & dc operating co nditions(sstl_2 in/out) recommended operating conditions(voltage referenced to v ss =0v, t a =0 to 65 c) parameter symbol min typ max unit note device supply voltage v dd 2.375 2.50 2.625 v 1, 7 output supply voltage v ddq 2.375 2.50 2.625 v 1, 7 reference voltage v ref 0.49*v ddq - 0.51*v ddq v2 termination voltage vtt v ref -0.04 v ref v ref +0.04 v 3 input logic high voltage v ih(dc) v ref +0.15 - v ddq +0.30 v 4 input logic low voltage v il(dc) -0.30 - v ref -0.15 v 5 output logic high voltage v oh vtt+0.76 - - v i oh =-15.2ma output logic low voltage v ol - - vtt-0.76 v i ol =+15.2ma input leakage current i il -5 - 5 ua 6 output leakage current i ol -5 - 5 ua 6 absolute maximum ratings parameter symbol value unit voltage on any pin relative to vss v in , v out -0.5 ~ 3.6 v voltage on v dd supply relative to vss v dd -1.0 ~ 3.6 v voltage on v dd supply relative to vss v ddq -0.5 ~ 3.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 2.0 w short circuit current i os 50 ma 1. under all conditions v ddq must be less than or equal to v dd . 2. v ref is expected to equal 0.50*v ddq of the transmitting device and to track variat ions in the dc level of the same. peak to peak noise on the v ref may not exceed + 2% of the dc value. thus, from 0.50*v ddq , v ref is allowed + 25mv for dc error and an additional + 25mv for ac noise. 3. v tt of the transmitting device must track v ref of the receiving device. 4. v ih (max.)= v ddq +1.5v for a pulse width and it can not be greater than 1/3 of the cycle rate. 5. v il (mim.)= -1.5v for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. for any pin under test input of 0v < v in < v dd is acceptable. for all other pins that are not under test v in =0v. 7. for the k4d261638f-tc2a, vdd & vddq = 2.8v+ 0.1v for the k4d261638f-tc5a, vdd & vddq = 2.4v to 2.7v note :
128m gddr sdram k4d261638f - 11 - rev 1.5 (mar. 2005) dc characteristics note : 1. measured with outputs open. 2. refresh period is 32ms. parameter symbol test condition version unit note -2a -33 -36 -40 -50 -5a operating current (one bank active) i cc1 burst lenth=2 t rc t rc (min) i ol =0ma, t cc = t cc (min) 210 190 180 170 150 tbd ma 1 precharge standby current in power-down mode i cc2 p cke v il (max), t cc = t cc (min) 60 45 tbd ma precharge standby current in non power-down mode i cc2 n cke v ih (min), cs v ih (min), t cc = t cc (min) 90 75 70 65 60 tbd ma active standby current power-down mode i cc3 p cke v il (max), t cc = t cc (min) 75 65 60 55 50 tbd ma active standby current in in non power-down mode i cc3 n cke vih(min), cs vih(min), t cc = t cc (min) 135 100 100 95 90 tbd ma operating current ( burst mode) i cc4 t rc t rfc (min) t rc t rfc (min) page burst, all banks activated. 400 290 275 260 245 tbd ma refresh current i cc5 t rc t rfc (min) 245 210 200 195 190 tbd ma 2 self refresh current i cc6 cke 0.2v 4 tbd ma recommended operating conditions unless otherwise noted, t a =0 to 65 c) 1. v id is the magnitude of the difference between t he input level on ck and the input level on ck 2. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same 3. for the k4d261638f-tc2a, vdd & vddq = 2.8v+ 0.1v. for the k4d261638f-tc5a, vdd & vddq = 2.4v to 2.7v note : ac input operating conditions recommended operating conditions(voltage referenced to v ss =0v, v dd =2.5v+ 5%, v ddq =2.5v+ 5%,t a =0 to 65 c) parameter symbol min typ max unit note input high (logic 1) voltage; dq v ih v ref +0.35 - - v input low (logic 0) voltage; dq v il --v ref -0.35 v clock input differential voltage; ck and ck v id 0.7 - v ddq +0.6 v 1 clock input crossing point voltage; ck and ck v ix 0.5*v ddq -0.2 - 0.5*v ddq +0.2 v 2
128m gddr sdram k4d261638f - 12 - rev 1.5 (mar. 2005) r t =50 ? output c load =30pf (fig. 1) output load circuit z0=50 ? v ref =0.5*v ddq v tt =0.5*v ddq decoupling capacitance guide line recommended decoupling capacitance added to power line at board. parameter symbol value unit decoupling capacitance between v dd and v ss c dc1 0.1 + 0.01 uf decoupling capacitance between v ddq and v ssq c dc2 0.1 + 0.01 uf 1. v dd and v ddq pins are separated each other. all v dd pins are connected in chip. all v ddq pins are connected in chip. 2. v ss and v ssq pins are separated each other all v ss pins are connected in chip. all v ssq pins are connected in chip. note : ac operating test conditions (v dd =2.5v 5%, t a = 0 to 65 c) 1.for the k4d261638f-tc2a, vdd & vddq = 2.8v+ 0.1v. for the k4d261638f-tc5a, vdd & vddq = 2.4v to 2.7v parameter value unit note input reference voltage for ck(for single ended) 0.50*v ddq v ck and ck signal maximum peak swing 1.5 v ck signal minimum slew rate 1.0 v/ns input levels(v ih /v il )v ref +0.35/v ref -0.35 v input timing measurement reference level v ref v output timing measurement reference level v tt v output load condition see fig.1 capacitance (v dd =2.5v, t a = 25 c, f=1mhz) parameter symbol min max unit input capacitance( ck, ck )c in1 1.0 5.0 pf input capacitance(a 0 ~a 11 , ba 0 ~ba 1 )c in2 1.0 4.0 pf input capacitance ( cke, cs , ras ,cas , we ) c in3 1.0 4.0 pf data & dqs input/output capacitance(dq 0 ~dq 15 )c out 1.0 6.5 pf input capacitance(dm0 ~ dm3) c in4 1.0 6.5 pf
128m gddr sdram k4d261638f - 13 - rev 1.5 (mar. 2005) ac characteristics(i) parameter symbol -2a -33 -36 unit note min max min max min max ck cycle time cl=3 tck - 10 - 10 - 10 ns cl=4 2.86 3.3 3.6 ns cl=5 - ns ck high level width tch 0.45 0.55 0.45 0.55 0.45 0.55 tck ck low level width tcl 0.45 0.55 0.45 0.55 0.45 0.55 tck dqs out access time from ck tdqsck -0.6 0.6 -0.6 0.6 -0.6 0.6 ns output access time from ck tac -0.6 0.6 -0.6 0.6 -0.6 0.6 ns data strobe edge to dout edge tdqsq - 0.35 - 0.35 - 0.40 ns 1 read preamble trpre 0.9 1.1 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 tck ck to valid dqs-in tdqss 0.85 1.15 0.85 1.15 0.85 1.15 tck dqs-in setup time twpres 0 - 0 - 0 - ns dqs-in hold time twpreh 0.35 - 0.35 - 0.35 - tck dqs write postamble twpst 0.4 0.6 0.4 0.6 0.4 0.6 tck dqs-in high level width tdqsh 0.4 0.6 0.4 0.6 0.4 0.6 tck dqs-in low level width tdqsl 0.4 0.6 0.4 0.6 0.4 0.6 tck address and control input setup tis 0.9 - 0.9 - 0.9 - ns address and control input hold tih 0.9 - 0.9 - 0.9 - ns dq and dm setup time to dqs tds 0.35 - 0.35 - 0.40 - ns dq and dm hold time to dqs tdh 0.35 - 0.35 - 0.40 - ns clock half period thp tclmin or tchmin - tclmin or tchmin - tclmin or tchmin -ns 1 data output hold time from dqs tqh thp-0.35 - thp-0.35 - thp-0.4 - ns 1
128m gddr sdram k4d261638f - 14 - rev 1.5 (mar. 2005) ac characteristics(i) _continued parameter symbol -40 -50 -5a unit note min max min max min max ck cycle time cl=3 tck 4.0 10 5.0 10 5.0 10 ns cl=4 - - - ns cl=5 - - - ns ck high level width tch 0.45 0.55 0.45 0.55 0.45 0.55 tck ck low level width tcl 0.45 0.55 0.45 0.55 0.45 0.55 tck dqs out access time from ck tdqsck -0.6 0.6 -0.7 0.7 -0.7 0.7 ns output access time from ck tac -0.6 0.6 -0.7 0.7 -0.7 0.7 ns data strobe edge to dout edge tdqsq - 0.4 - 0.45 - 0.45 ns 1 read preamble trpre 0.9 1.1 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 tck ck to valid dqs-in tdqss 0.85 1.15 0.8 1.2 0.8 1.2 tck dqs-in setup time twpres 0 - 0 - 0 - ns dqs-in hold time twpreh 0.35 - 0.3 - 0.3 - tck dqs write postamble twpst 0.4 0.6 0.4 0.6 0.4 0.6 tck dqs-in high level width tdqsh 0.4 0.6 0.4 0.6 0.4 0.6 tck dqs-in low level width tdqsl 0.4 0.6 0.4 0.6 0.4 0.6 tck address and control input setup tis 0.9 - 1.0 - 1.0 - ns address and control input hold tih 0.9 - 1.0 - 1.0 - ns dq and dm setup time to dqs tds 0.4 - 0.45 - 0.45 - ns dq and dm hold time to dqs tdh 0.4 - 0.45 - 0.45 - ns clock half period thp tclmin or tchmin - tclmin or tchmin - tclmin or tchmin -ns1 data output hold time from dqs tqh thp-0.4 - thp-0.45 - thp-0.45 - ns 1 note 1 : - the jedec ddr specification cu rrently defines the ou tput data valid window(tdv) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - the previously used definition of tdv(=0.35tck) artifi cially penalizes system timing budgets by assuming the worst case output vaild window even then the clock duty cycle applied to the device is better than 45/55% - a new ac timing term, tqh which stands for data output hold time from dqs is difined to account for clock duty cycle variation and replaces tdv - tqhmin = thp-x where . thp=minimum half clock period for any given cycle an d is defined by clock high or clock low time(tch,tcl) . x=a frequency dependent timing allowance account for tdqsqmax
128m gddr sdram k4d261638f - 15 - rev 1.5 (mar. 2005) ac characteristics (iii) (unit : number of clock) ac characteristics (ii) note : 1. for normal write operation, even numbers of din are to be written inside dram 2. trcdwr should be always greater or equal to 2tck parameter symbol -2a -33 -36 unit note min max min max min max row cycle time trc 45.8 - 52.8 - 57.6 - ns refresh row cycle time trfc 48.6 - 56.1 - 61.2 - ns row active time tras 31.5 100k 36.3 100k 39.6 100k ns ras to cas delay for read trcdrd 14.3 - 16.5 - 14.4 - ns ras to cas delay for write trcdwr 8.6 - 9.9 - 7.2 - ns 2 row precharge time trp 14.3 - 16.5 - 18 - ns row active to row active trrd 8.6 - 9.9 - 10.8 - ns last data in to row precharge @normal precharge twr 4-4-4 -tck1 last data in to row precharge @auto precharge twr_a 4-4-4 -tck1 last data in to read command tcdlr 3 - 3 -2-tck1 col. address to col. address tccd 1 - 1 - 1 - tck mode register set cycle time tmrd 2 - 2 - 2 - tck auto precharge write recovery + pre- charge tdal 9-9-9-tck exit self refresh to read command txsr 200 - 200 - 200 - tck power down exit time tpdex 3tck +tis - 3tck +tis - 3tck +tis -ns refresh interval time tref 7.8 - 7.8 - 7.8 - us k4d261638f-tc33 frequency cas latency trc trfc tras trcdrd trcdwr trp trrd tdal unit 300mhz ( 3.3ns ) 4 16 17 11 5 3 5 3 9 tck 275mhz ( 3.6ns ) 4 16 17 11 4 2 5 3 9 tck 250mhz ( 4.0ns ) 3 13 15 9 4 2 4 3 7 tck 200mhz ( 5.0ns ) 3 12 14 8 4 2 4 3 7 tck k4d261638f-tc2a frequency cas latency trc trfc tras trcdrd trcdwr trp trrd tdal unit 350mhz ( 2.86ns ) 4 16 17 11 5 3 5 3 9 tck k4d261638f-tc36 frequency cas latency trc trfc tras trcdrd trcdwr trp trrd tdal unit 275mhz ( 3.6ns ) 4 16 17 11 4 2 5 3 9 tck 250mhz ( 4.0ns ) 3 13 15 9 4 2 4 3 7 tck 200mhz ( 5.0ns ) 3 12 14 8 4 2 4 3 7 tck
128m gddr sdram k4d261638f - 16 - rev 1.5 (mar. 2005) ac characteristics (iii)_continued (unit : number of clock) ac characteristics (ii)_continued note : 1. for normal write operation, even numbers of din are to be written inside dram 2. trcdwr should be always greater or equal to 2tck parameter symbol -40 -50 -5a unit note min max min max min max row cycle time trc 52 - 60 - 55 -ns refresh row cycle time trfc 60 - 70 - 70 ns row active time tras 36 100k 40 100k 40 100k ns ras to cas delay for read trcdrd 16 - 20 - 15 -ns ras to cas delay for write trcdwr 8 - 10 - 10 -ns2 row precharge time trp 16 - 20 - 15 -ns row active to row active trrd 12 - 15 - 10 ns last data in to row precharge @normal precharge twr 3 - 3 - 3 - tck 1 last data in to row precharge @auto precharge twr_a 3 - 3 - 3 - tck 1 last data in to read command tcdlr 2 - 2 - 2 - tck 1 col. address to col. address tccd 1 - 1 - 1 - tck mode register set cycle time tmrd 2 - 2 - 2 - tck auto precharge write recovery + pre- charge tdal 7-7-6-tck exit self refresh to read command txsr 200 - 200 - 200 - tck power down exit time tpdex 3tck +tis - 3tck +tis - 3tck +tis -ns refresh interval time tref 7.8 - 7.8 - 7.8 - us k4d261638f-tc50 frequency cas latency trc trfc tras trcdrd trcdwr trp trrd tdal unit 200mhz ( 5.0ns ) 3 12 14 8 4 2 4 3 7 tck k4d261638f-tc40 frequency cas latency trc trfc tras trcdrd trcdwr trp trrd tdal unit 250mhz ( 4.0ns ) 3 13 15 9 4 2 4 3 7 tck 200mhz ( 5.0ns ) 3 12 14 8 4 2 4 3 7 tck * 166/133mhz were supported in k4d261638f-tc5a k4d261638f-tc5a frequency cas latency trc trfc tras trcdrd trcdwr trp trrd tdal unit 200mhz ( 5.0ns ) 3 11 14 8 3 2 3 2 6 tck 166mhz ( 6.0ns ) 3 10 12 7 3 2 3 2 5 tck 133mhz ( 7.5ns ) 3 8 10 6 2 2 2 2 4 tck
128m gddr sdram k4d261638f - 17 - rev 1.5 (mar. 2005) simplified timing @ bl=4 normal write burst (@ bl=4) multi bank interleaving write burst (@ bl=4) 012345678 13 14 15 16 17 18 19 20 21 9101112 22 com dqs dq we dm ck, ck a8/ap addr (a0~a7 ba[1:0] da0da1da2da3 da0 da1 da2 da3 db0 db1 db2 db3 act_a wr_a prech act_a wr_a act_b wr_b t rcd t ras t rp t rc t rrd baa baa baa baa baa bab bab rb rb ca cb ra ra ra ca ra ,a9~a11)
128m gddr sdram k4d261638f - 18 - rev 1.5 (mar. 2005) package dimensions (66pin tsop-ii) units : millimeters 0.30 0.08 0.65typ (0.71) 22.22 0.10 0.125 (0.80) 10.16 0.10 0 ~8 #1 #33 #66 #34 (1.50) (1.50) 0.65 0.08 1.00 0.10 1.20max (0.50) (0.50) (10.76) 11.76 0.20 (10 ) (10 ) +0.075 -0.035 (0.80) 0.10 max 0.075 max [] 0.05 min (10 ) (10 ) ( r 0 . 1 5 ) 0.210 0.05 0.665 0.05 ( r 0.1 5 ) ( 4 ) ( r 0 . 2 5 ) (r0 .2 5) 0.45~0.75 0.25typ note 1. ( ) is reference 2. [ ] is ass ? y out quality
-1- part number decoder last updated : august 2006 1. memory (k) 2. dram : 4 3. small classification d : gddr sdram n : gddr2 sdram j : gddr3 sdram u : gddr4 sdram 4~5. density,refresh 26 : 128m, 4k/32ms 28 : 128m, 4k/64ms 51 : 512m, 8k/64ms 52 : 512m, 8k/32ms 54 : 256m, 16k/16ms 55 : 256m, 4k/32ms 56 : 256m, 8k/64ms 62 : 64m, 2k/16ms 64 : 64m, 4k/64ms 6~7. organization 16 : x16 32 : x32 8. bank 2 : 2bank 3 : 4bank 4 : 8bank 9. interface, vdd, vddq 2 : lvttl, 3.3v, 3.3v 4 : lvttl, 2.5v, 2.5v 5 : sstl2, 1.8v, 1.8v, lp 6 : sstl2, 1.5v, 1.5v 8 : sstl2, 2.5v, 2.5v a : sstl2, 2.5v, 1.8v h : sstl2, 3.3v, 2.5v q : sstl2, 1.8v, 1.8v r : sstl2, 2.8v, 2.8v 10. generation m : 1st generation a : 2nd generation b : 3rd generation c : 4th generation e : 5th generation f : 7th generation g : 8th generation h : 9th generation i : 10th generation k : 12th generation 11. " ? 12. package q : tqfp u : tqfp ( lead free ) g : 84/144ball fbga z : 84ball fbga ( lead free) v : 144ball fbga ( lead free ) a : 136ball fbga b : 136ball fbga( lead free) t : tsop l : tsop ( lead free ) j : fbga ( ddp ) e : fbga ( ddp, lead free ) 13. temp, power c : commercial normal l : commercial low 14~15. speed ( wafer/chip biz/bgd : 00 ) 06 : 0.625ns ( 1600mhz ) 07 : 0.714ns ( 1400mhz ) 7a : 0.77ns( 1300mhz ) 08 : 0.83ns ( 1200mhz ) 09 : 0.91ns ( 1100mhz ) 1b : 0.95ns ( 1050mhz ) 1a : 1.0ns ( 1000mhz ) 11 : 1.1ns ( 900mhz ) 12 : 1.25ns ( 800mhz ) 14 : 1.429ns ( 700mhz ) 16 : 1.667ns ( 600mhz ) 18 : 1.818ns ( 550mhz ) 20 : 2.0ns ( 500mhz ) 22 : 2.2ns ( 450mhz ) 25 : 2.5ns ( 400mhz ) 2a : 2.86ns ( 350mhz ) 2c : 2.66ns ( 375mhz ) 33 : 3.3ns ( 300mhz ) 36 : 3.6ns ( 275mhz ) 40 : 4ns ( 250mhz ) 45 : 4.5ns ( 222mhz ) 50/5a : 5ns ( 200mhz ) 55 : 5.5ns ( 183mhz ) 60 : 6ns ( 166mhz ) graphics memory code information(1/2) k 4 x x x x x x x x - x x x x x x x 1234 5 6 7 8 9 10 11 12 13 14 15 16 17 18
-2- part number decoder last updated : august 2006 - common to all products, except of mask rom - divided into tape & reel(in mask rom, divided into tray, ammo packing separately) graphics memory code information(2/2) k 4 x x x x x x x x - x x x x x x x 1234 5 6 7 8 9 10 11 12 13 14 15 16 17 18 m module other packing p module tape & reel module a ammo packing y tray component ( mask rom ) s stack 0 ( number) other ( tray, tube, jar ) t tape & reel component new marking packing type divide 16. packing "packing type reference" 17~18. customer "customer list reference"

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