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CXD3406GA timing generator and signal processor for frame readout ccd image sensor description the CXD3406GA is a timing generator and ccd signal processor ic for the icx252/262 ccd image sensor. features timing generator functions horizontal drive frequency 12 to 18mhz (base oscillation frequency 24 to 36mhz) supports frame readout/draft (sextuple speed)/ af (auto focus drive) high-speed/low-speed shutter function horizontal and vertical drivers for ccd image sensor ccd signal processor functions correlated double sampling programmable gain amplifier (pga) allows gain adjustment over a wide range (? to +42db) 10-bit a/d converter chip scale package (csp): csp allows vast reduction in the ccd camera block footprint applications digital still cameras structure silicon gate cmos ic applicable ccd image sensors icx252 (1/1.8", 3240k pixels) icx262 (1/1.8", 3240k pixels) absolute maximum ratings supply voltage v dd a, v dd b, v dd c, v dd dv ss ?0.3 to +7.0 v v dd e, v dd f, v dd gv ss ?0.3 to +4.0 v vl ?0.0 to v ss v vh vl ?0.3 to +26.0 v input voltage (analog) v in v ss ?0.3 to v dd + 0.3 v input voltage (digital) v i v ss ?0.3 to v dd + 0.3 v output voltage v o1 v ss ?0.3 to v dd + 0.3 v v o2 vl ?0.3 to v ss + 0.3 v v o3 vl ?0.3 to vh + 0.3 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +125 ? recommended operating conditions supply voltage v dd b 3.0 to 5.5 v v dd a, v dd c, v dd d 3.0 to 3.6 v vm 0.0 v vh 14.5 to 15.5 v vl ?.0 to ?.0 v v dd e, v dd f, v dd g 3.0 to 3.6 v operating temperature topr ?0 to +75 ? ?1 e00z02a26 sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 96 pin lflga (plastic)
?2 CXD3406GA block diagram c7 c3 a1 nc a2 nc d8 c2 d7 c1 b8 av dd3 b6 av dd4 b9 av ss3 a6 av ss4 c5 av ss5 a3 sck2 a4 ssi2 b4 sen2 a5 test3 c4 test4 b5 test5 e2 dv dd1 f2 dv ss3 f3 dv dd2 e3 dv ss1 f1 b3 dv ss2 d0 (lsb) latch serial port register dac pga cds adc preblanking dummy pixel auto zero pulse generator v driver serial port register black level auto zero b2 d1 b1 d2 c3 d3 c2 d4 c1 d5 d3 d6 d2 d7 d1 d8 e1 d9 (msb) g1 adclki g2 clpobi g3 clpdmi l3 v ss4 h1 adclk h2 clpob h3 clpdm j3 v ss5 l1 osci k1 osco j1 cki j2 cko k2 mcko n8 sncsl l2 ssi1 m6 vl l4 vm m5 vh m9 wen n9 id j7 v ss3 j9 h2 j8 h1 h9 v dd3 k9 v ss2 k8 rg k7 v dd2 h8 v dd4 h7 xrs g7 pblk g8 xshd g9 xshp f7 pblki f8 xshdi e7 av ss2 f9 xshpi d9 av ss1 e8 av dd2 e9 av dd1 c9 ccdin c6 c9 a7 c8 b7 c7 a8 av ss6 a9 av dd5 c8 c4 m1 sck1 n1 sen1 n3 v ss6 l7 v ss1 k3 v dd5 l9 v dd1 m2 vd n2 hd n7 sub n4 v4 n6 v3b v3a l6 v2 m4 n5 v1b m7 test2 m3 test1 m8 rst ssg l8 ssgsl l5 v1a latch selector selector 1/2
3 CXD3406GA pin configuration (top view) nc d2 d5 d8 d9 dv ss2 adclki adclk cki osco osci sck1 sen1 a b c d e f g h j k l m n nc d1 d4 d7 dv dd1 dv ss3 clpobi clpob cko mcko ssi1 vd hd sck2 d0 d3 d6 dv ss1 dv dd2 clpdmi clpdm v ss5 v dd5 v ss4 test1 v ss6 ssi2 sen2 test4 vm v2 v4 test3 test5 av ss5 v1a vh v1b av ss4 av dd4 c9 v3a vl v3b c8 c7 c3 c1 av ss2 pblki pblk xrs v ss3 v dd2 v ss1 test2 sub av ss6 av dd3 c4 c2 av dd2 xshdi xshd v dd4 h1 rg ssgsl rst sncsl av dd5 av ss3 ccdin av ss 1 av dd1 xshpi xshp v dd3 h2 v ss2 v dd1 wen id 12345 6789
4 CXD3406GA pin description no connected. no connected. ccd signal processor block serial interface clock input. (schmitt trigger) ccd signal processor block serial interface data input. (schmitt trigger) ccd signal processor block test input 3. connect to dv ss . ccd signal processor block analog gnd. capacitor connection. ccd signal processor block analog gnd. ccd signal processor block analog power supply. adc output. adc output. adc output (lsb). ccd signal processor block serial interface enable input. (schmitt trigger) ccd signal processor block test input 5. connect to dv dd . ccd signal processor block analog power supply. capacitor connection. ccd signal processor block analog power supply. ccd signal processor block analog gnd. adc output. adc output. adc output. ccd signal processor block test input 4. connect to dv ss . ccd signal processor block analog gnd. capacitor connection. capacitor connection. capacitor connection. ccd output signal input. adc output. adc output. adc output. capacitor connection. capacitor connection. ccd signal processor block analog gnd. adc output (msb). ccd signal processor block digital power supply. (power supply for adc) a1 a2 a3 a4 a5 a6 a7 a8 a9 b1 b2 b3 b4 b5 b6 b7 b8 b9 c1 c2 c3 c4 c5 c6 c7 c8 c9 d1 d2 d3 d7 d8 d9 e1 e2 nc nc sck2 ssi2 test3 av ss4 c8 av ss6 av dd5 d2 d1 d0 sen2 test5 av dd4 c7 av dd3 av ss3 d5 d4 d3 test4 av ss5 c9 c3 c4 ccdin d8 d7 d6 c1 c2 av ss1 d9 dv dd1 i i i o o o i i o o o i i o o o o pin no. symbol i/o description
5 CXD3406GA ccd signal processor block digital gnd. (gnd for adc) ccd signal processor block analog gnd. ccd signal processor block analog power supply. ccd signal processor block analog power supply. ccd signal processor block digital gnd. ccd signal processor block digital gnd. ccd signal processor block digital power supply. pulse input for horizontal and vertical blanking period pulse cleaning. (schmitt trigger) ccd data level sample-and-hold pulse input. (schmitt trigger) ccd precharge level sample-and-hold pulse input. (schmitt trigger) clock input for analog/digital conversion. (schmitt trigger) ccd optical black signal clamp pulse input. (schmitt trigger) ccd dummy signal clamp pulse input. (schmitt trigger) pulse output for horizontal and vertical blanking period pulse cleaning. ccd data level sample-and-hold pulse output. ccd precharge level sample-and-hold pulse output. clock output for analog/digital conversion. ccd optical black signal clamp pulse output. ccd dummy signal clamp pulse output. sample-and-hold pulse output for analog/digital conversion phase alignment. timing generator block digital power supply. (power supply for cds block) timing generator block 3.0 to 5.0v power supply. (power supply for h1/h2) inverter input. inverter output. timing generator block digital gnd. timing generator block digital gnd. ccd horizontal register clock output. ccd horizontal register clock output. inverter output for oscillation. when not used, leave open or connect a capacitor. system clock output for signal processor ic. timing generator block digital power supply. (power supply for common logic block) timing generator block digital power supply. (power supply for rg) ccd reset gate pulse output. timing generator block digital gnd. inverter input for oscillation. when not used, fix to low. e3 e7 e8 e9 f1 f2 f3 f7 f8 f9 g1 g2 g3 g7 g8 g9 h1 h2 h3 h7 h8 h9 j1 j2 j3 j7 j8 j9 k1 k2 k3 k7 k8 k9 l1 dv ss1 av ss2 av dd2 av dd1 dv ss2 dv ss3 dv dd2 pblki xshdi xshpi adclki clpobi clpdmi pblk xshd xshp adclk clpob clpdm xrs v dd4 v dd3 cki cko v ss5 v ss3 h1 h2 osco mcko v dd5 v dd2 rg v ss2 osci i i i i i i o o o o o o o i o o o o o o i pin no. symbol i/o description
6 CXD3406GA timing generator block serial interface data input. schmitt trigger input/no protective diode on power supply side. timing generator block digital gnd. timing generator block digital gnd. (gnd for vertical driver) ccd vertical register clock output. ccd vertical register clock output. timing generator block digital gnd. internal ssg enable. high: internal ssg valid, low: external sync valid (with pull-down resistor) timing generator block digital power supply.(power supply for common logic block) timing generator block serial interface clock input. schmitt trigger input/no protective diode on power supply side. vertical sync signal input/output. timing generator block test input 1. normally fix to gnd. (with pull-down resistor) ccd vertical register clock output. timing generator block 15.0v power supply. (power supply for vertical driver) timing generator block 7.5v power supply. (power supply for vertical driver) timing generator block test input 2. normally fix to gnd. (with pull-down resistor) timing generator block reset input. high: normal operation, low: reset control normally apply reset during power-on. schmitt trigger input/no protective diode on power supply side memory write timing pulse output. timing generator block serial interface strobe input. schmitt trigger input/no protective diode on power supply side horizontal sync signal input/output. timing generator block digital gnd. ccd vertical register clock output. ccd vertical register clock output. ccd vertical register clock output. ccd electronic shutter pulse output. control input used to switch sync system. high: cki sync, low: mcko sync (with pull-down resistor) vertical direction line identification pulse output. l2 l3 l4 l5 l6 l7 l8 l9 m1 m2 m3 m4 m5 m6 m7 m8 m9 n1 n2 n3 n4 n5 n6 n7 n8 n9 ssi1 v ss4 vm v1a v3a v ss1 ssgsl v dd1 sck1 vd test1 v2 vh vl test2 rst wen sen1 hd v ss6 v4 v1b v3b sub sncsl id i o o i i i/o i o i i o i i/o o o o o i o pin no. symbol i/o description
7 CXD3406GA electrical characteristics timing generator block electrical characteristics dc characteristics (within the recommended operating conditions) v dd2 v dd3 v dd4 v dd1 , v dd5 rst ssi1, sck1, sen1 test1, test2 sncsl, ssgsl vd, hd h1, h2 rg xshp, xshd, xrs, pblk, clpob, clpdm, adclk cko mcko id, wen v1a, v1b, v3a, v3b, v2, v4 sub v dd a v dd b v dd c v dd d v i + v i v i + v i v ih1 v il1 v ih2 v il2 v ih3 v il3 v oh1 v ol1 v oh2 v ol2 v oh3 v ol3 v oh5 v ol5 v oh6 v ol6 v oh7 v ol7 i ol i om1 i om2 i oh i osl i osh 3.0 3.0 3.0 3.0 0.8v dd d 0.8v dd d 0.7v dd d 0.7v dd d 0.8v dd d v dd d 0.8 v dd b 0.8 v dd a 0.8 v dd d 0.8 v dd d 0.8 v dd d 0.8 10.0 5.0 5.4 3.3 3.3 3.3 3.3 3.6 5.5 3.6 3.6 0.2v dd d 0.2v dd d 0.2v dd d 0.3v dd d 0.2v dd d 0.4 0.4 0.4 0.4 0.4 0.4 5.0 7.2 4.0 v v v v v v v v v v v v v v v v v v v v v v v v v v ma ma ma ma ma ma feed current where i oh = 1.2ma pull-in current where i ol = 2.4ma feed current where i oh = 22.0ma pull-in current where i ol = 14.4ma feed current where i oh = 3.3ma pull-in current where i ol = 2.4ma feed current where i oh = 6.9ma pull-in current where i ol = 4.8ma feed current where i oh = 3.3ma pull-in current where i ol = 2.4ma feed current where i oh = 2.4ma pull-in current where i ol = 4.8ma v1a/b, v2, v3a/b, v4 = 8.25v v1a/b, v2, v3a/b, v4 = 0.25v v1a/b, v3a/b = 0.25v v1a/b, v3a/b = 14.75v sub = 8.25v sub = 14.75v supply voltage 1 supply voltage 2 supply voltage 3 supply voltage 4 input voltage 1 ? 1 input voltage 2 ? 2 input voltage 3 ? 3 input voltage 4 ? 4 input/output voltage output voltage 1 output voltage 2 output voltage 3 output voltage 4 output voltage 5 output voltage 6 output current 1 output current 2 item pins symbol conditions min. typ. max. unit ? 1 this input pin is a schmitt trigger input and it does not have protective diode of the power supply side in the ic. ? 2 these input pins are schmitt trigger inputs. ? 3 these input pins are with pull-down resistor in the ic. ? 4 these input pins are with pull-down resistor in the ic and they do not have protective diode of the power supply side in the ic. note) the above table indicates the condition for 3.3v drive. v oh4 feed current where i oh = 3.3ma v dd c 0.8 v v ol4 pull-in current where i ol = 2.4ma 0.4 v
8 CXD3406GA inverter i/o characteristics for oscillation (within the recommended operating conditions) item logical vth input voltage output voltage feedback resistor oscillation frequency pins osci osci osco osci, osco osci, osco symbol lvth v ih v il v oh v ol rfb f conditions feed current where i oh = 3.6ma pull-in current where i ol = 2.4ma v in = v dd d or v ss min. 0.7v dd d v dd d 0.8 500k 20 typ. v dd d/2 2m max. 0.3v dd d 0.4 5m 50 unit v v v v v ? mhz item logical vth input voltage input amplitude pins cki symbol lvth v ih v il v in conditions fmax 50mhz sine wave min. 0.7v dd d 0.3 typ. v dd d/2 max. 0.3v dd d unit v v v vp-p item rise time fall time output noise voltage symbol ttlm ttmh ttlh ttml tthm tthl vclh vcll vcmh vcml conditions vl to vm vm to vh vl to vh vm to vl vh to vm vh to vl min. 200 200 30 200 200 30 typ. 350 350 60 350 350 60 max. 500 500 90 500 500 90 1.0 1.0 1.0 1.0 unit ns ns ns ns ns ns v v v v inverter input characteristics for base oscillation clock duty adjustment (within the recommended operating conditions) note) input voltage is the input voltage characteristics for direct input from an external source. input amplitude is the input amplitude characteristics in the case of input through a capacitor. switching characteristics (vh = 15.0v, vm = gnd, vl = 7.5v) notes) 1. the mos structure of this ic has a low tolerance for static electricity, so full care should be given for measures to prevent electrostatic discharge. 2. for noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1f or more) between each power supply pin (vh, vl) and gnd. 3. to protect the ccd image sensor, clamp the sub pin output at vh before input to the ccd image sensor.
9 CXD3406GA switching waveforms v1a (v1b, v3a, v3b) v2 (v4) sub ttmh tthm vh vm vl vm vl vh vl 90% 10% 90% 10% ttlm ttlm 90% 10% 90% 10% ttlh tthl 90% 90% 10% 10% ttml 90% 10% ttml 90% 10% waveform noise vcmh vcml vm vl vclh vcll
10 CXD3406GA measurement circuit n1 n2 l4 l5 l6 n7 l7 n8 n9 m1 m2 m3 n4 n5 n6 m4 n3 l2 k2 k9 k8 k7 k1 l1 k3 j9 j8 j7 j3 j2 j1 h9 h8 h7 h3 h2 l3 g9 g8 g7 a2 a1 a3 a4 a5 a6 a7 a8 a9 b1 b2 b3 b4 b5 b6 b7 b9 b8 c1 c2 c3 c4 c5 c6 m5 m6 e1 l8 l9 m7 m8 m9 e8 d8 d7 d3 d2 d1 c9 c8 c7 f3 f2 g1 e9 d9 e7 g3 g2 h1 f9 f8 f7 f1 e3 e2 vd CXD3406GA v2 vh vl d9 ssgsl v dd1 sck1 vd test1 v4 v1b v3b test2 rst wen sen1 hd vm v1a v3a sub v ss1 sncsl id clpdmi clpobi adclk xshpi xshdi pblki dv dd2 dv ss3 adclki av dd1 av ss1 av ss2 dv ss2 dv ss1 dv dd1 av dd2 c2 c1 d6 d7 d8 ccdin c4 c3 v ss6 ssi1 mcko v ss2 rg v dd2 osco osci v dd5 h2 h1 v ss3 v ss5 cko cki v dd3 v dd4 xrs clpdm clpob v ss4 xshp xshd pblk nc nc sck2 ssi2 test3 av ss4 c8 av ss6 av dd5 d2 d1 d0 sen2 test5 av dd4 c7 av ss3 av dd3 d5 d4 d3 test4 av ss5 c9 serial interface data hd +3.3v +15.0v 7.5v c2 c2 c2 c2 c2 r1 r1 r1 r2 r1 r1 r1 c2 c2 c2 c2 c2 c2 c2 c2 c2 c1 c1 c1 c1 c1 c1 c2 c3 cki c6 c4 c5 c5 c6 c6 c1 3300pf c2 560pf c3 820pf c4 30pf c5 215pf c6 10pf r1 30 ? r2 10 ?
11 CXD3406GA ac characteristics ac characteristics between the serial interface clocks ssi1 0.2v dd d 0.2v dd d 0.8v dd d ts2 th1 ts1 ts3 0.8v dd d 0.8v dd d sck1 sen1 sen1 symbol t s1 t h1 t s2 t s3 definition ssi1 setup time, activated by the rising edge of sck1 ssi1 hold time, activated by the rising edge of sck1 sck1 setup time, activated by the rising edge of sen1 sen1 setup time, activated by the rising edge of sck1 min. typ. max. 20 20 20 20 unit ns ns ns ns serial interface clock internal loading characteristics (1) (within the recommended operating conditions) th1 enlarged view example: during frame mode 0.2v dd d ts1 0.2v dd d v1a vd hd hd v1a sen1 0.8v dd d symbol t s1 t h1 definition sen1 setup time, activated by the falling edge of hd sen1 hold time, activated by the falling edge of hd min. typ. max. 0 102 unit ns s ? be sure to maintain a constantly high sen1 logic level near the falling edge of the hd in the horizontal period during which v1a/b and v3a/b values take the ternary value and during that horizontal period. (within the recommended operating conditions)
12 CXD3406GA serial interface clock output variation characteristics normally, the serial interface data is loaded to the CXD3406GA at the timing shown in "serial interface clock internal loading characteristics (1)" above. however, one exception to this is when the data such as stb is loaded to the CXD3406GA and controlled at the rising edge of sen1. see "description of operation". 0.8v dd d sen1 output signal tpdpulse symbol tpdpulse definition output signal delay, activated by the rising edge of sen1 min. typ. max. 100 5 unit ns (within the recommended operating conditions) serial interface clock internal loading characteristics (2) th1 enlarged view 0.2v dd d ts1 0.2v dd d vd hd vd hd sen1 0.8v dd d example: during frame mode symbol t s1 t h1 definition sen1 setup time, activated by the falling edge of vd sen1 hold time, activated by the falling edge of vd min. typ. max. 0 200 unit ns ns ? be sure to maintain a constantly high sen1 logic level near the falling edge of vd. (within the recommended operating conditions)
13 CXD3406GA rst 0.2v dd d tw1 0.8v dd d vd, hd mcko ts1 th1 0.2v dd d 0.8v dd d 0.2v dd d rst loading characteristics symbol t w1 definition rst pulse width min. typ. max. 35 unit ns (within the recommended operating conditions) vd and hd loading characteristics symbol t s1 t h1 definition vd and hd setup time, activated by the rising edge of mcko vd and hd hold time, activated by the rising edge of mcko min. typ. max. 20 5 unit ns ns mcko load capacitance = 10pf (within the recommended operating conditions) 0.8v dd d mcko wen, id tpd1 wen and id load capacitance = 10pf (within the recommended operating conditions) symbol tpd1 definition time until the above outputs change after the rise of mcko min. typ. max. 60 20 unit ns output variation characteristics
14 CXD3406GA ccd signal processor block electrical characteristics dc characteristics (fc = 18msps, dv dd1 , 2 = av dd1 , 2 , 3 , 4 , 5 = 3.3v, ta = 25 c) item supply voltage 1 supply voltage 2 supply voltage 3 analog input capacitance input voltage a/d clock duty output voltage pins dv dd1 dv dd2 av dd1 , av dd2 , av dd3 , av dd4 , av dd5 ccdin sck2, ssi2, sen2, test3, test4, xshdi, xshpi, adclki, clpobi, clpdmi, pblki adclki d0 to d9 symbol v dd e v dd f v dd g c in v i + v i v oh v ol conditions feed current where i oh = 2.0ma pull-in current where i ol = 2.0ma min. 3.0 3.0 3.0 v dd e 0.9 typ. 3.3 3.3 3.3 15 1.8 1.1 50 max. 3.6 3.6 3.6 0.4 unit v v v pf v v % v v analog characteristics (fc = 18msps, dv dd1 , 2 = av dd1 , 2 , 3 , 4 , 5 = 3.3v, ta = 25 c) item ccdin input voltage amplitude pga maximum gain pga minimum gain adc resolution adc maximum conversion rate adc integral non-linearity error adc differential non-linearity error signal-to-noise ratio ccdin input voltage clamp level ccd optical black signal clamp level symbol v in gmax gmin fc max e l e d snr ? 1 clp ob conditions pga gain = 0db, output full scale pga gain setting data = "3ffh" pga gain setting data = "000h" pga gain = 0db pga gain = 0db ccdin input connected to gnd via a coupling capacitor pga gain = 0db oblvl = "8h" pga gain = 0db min. 900 18 typ. 42 6 10 1.0 0.5 62 1.5 32 max. 1100 5.0 1.0 unit mv db db bit mhz lsb lsb db v lsb ? 1 snr = 20 log (full-scale voltage/rms noise)
15 CXD3406GA ac characteristics ac characteristics between the serial interface clocks ssi2 0.2v dd 0.2v dd 0.8v dd ts2 th1 ts1 ts3 0.8v dd 0.8v dd sck2 sen2 sen2 symbol t p1 t s1 t h1 t s2 t s3 definition sck2 clock period ssi2 setup time, activated by the rise of sck2 ssi2 hold time, activated by the rise of sck2 sck2 setup time, activated by the rise of sen2 sen2 setup time, activated by the rise of sck2 min. typ. max. 100 30 30 30 30 unit ns ns ns ns ns (fc = 18msps, dv dd1 , 2 = av dd1 , 2 , 3 , 4 , 5 = 3.3v, ta = 25 c) ? the setting values are reflected to the operation 5 or 6 adclki clocks after the serial data is loaded at the rise of sen2.
16 CXD3406GA cds/adc timing chart n n + 1 n 10 ccdin xshpi xshdi adclki d0 to d9 n 9n 8n 7 tw1 dl n + 2 n + 3 symbol t w1 dl definition adclki clock period adclki clock duty data latency min. typ. max. 50 9 54 unit ns % clocks (fc = 18msps, dv dd1 , 2 = av dd1 , 2 , 3 , 4 , 5 = 3.3v, ta = 25 c) ? set the input pulse polarity setting data d13, d14 and d15 of the serial interface data to "0". preblanking timing chart 11 clocks 11 clocks pblki adclki d0 to d9 all "0"
17 CXD3406GA description of operation pulses output from the CXD3406GA's timing generator block are controlled mainly by the rst pin and by the serial interface data. the pin status table is shown below, and the details of serial interface control are described on page 19 and thereafter. pin status table pin no. a1 a2 a3 a4 a5 a6 a7 a8 a9 b1 b2 b3 b4 b5 b6 b7 b8 b9 c1 c2 c3 c4 c5 c6 c7 c8 c9 d1 d2 nc nc sck2 ssi2 test3 av ss4 c8 av ss6 av dd5 d2 d1 d0 sen2 test5 av dd4 c7 av dd3 av ss3 d5 d4 d3 test4 av ss5 c9 c3 c4 ccdin d8 d7 d3 d7 d8 d9 e1 e2 e3 e7 e8 e9 f1 f2 f3 f7 f8 f9 g1 g2 g3 g7 g8 g9 h1 h2 h3 h7 h8 h9 j1 d6 c1 c2 av ss1 d9 dv dd1 dv ss1 av ss2 av dd2 av dd1 dv ss2 dv ss3 dv dd2 pblki xshdi xshpi adclki clpobi clpdmi pblk xshd xshp adclk clpob clpdm xrs v dd4 v dd3 cki act l l h act l l act act l l act act l l act act l l h act l l h act l l act act act act act symbol pin no. symbol cam slp rst stb cam slp rst stb
18 CXD3406GA ? 1 it is for output. for input, all items are "act". note) act means that the circuit is operating, and dis means that loading is stopped. l indicates a low output level, and h a high output level in the controlled status. also, vh, vm and vl indicate the voltage levels applied to vh (pin m5), vm (pin l4) and vl (pin m6), respectively, in the controlled status. pin no. j2 j3 j7 j8 j9 k1 k2 k3 k7 k8 k9 l1 l2 l3 l4 l5 l6 l7 l8 cko v ss5 v ss3 h1 h2 osco mcko v dd5 v dd2 rg v ss2 osci ssi1 v ss4 vm v1a v3a v ss1 ssgsl act act l act act l l act act l l act act act act act act act l act act l l act act act act act act act act dis act vh vh vm act vh vh vl act act act act l9 m1 m2 m3 m4 m5 m6 m7 m8 m9 n1 n2 n3 n4 n5 n6 n7 n8 n9 v dd1 sck1 vd ? 1 test1 v2 vh vl test2 rst wen sen1 hd ? 1 v ss6 v4 v1b v3b sub sncsl id act act act dis act l l h act vm vm vm act act act l act l l l act act act dis act l l h act vm vm vl act vh vh vm act vh vh vl act vh vh vl act act act act act l l l symbol pin no. symbol cam slp rst stb cam slp rst stb
19 CXD3406GA timing generator block serial interface control the CXD3406GA's timing generator block basically loads and reflects the timing generator block serial interface data sent in the following format in the readout portion at the falling edge of hd. here, readout portion specifies the horizontal period during which v1a/b and v3a/b, etc. take the ternary value. note that some items reflect the timing generator block serial interface data at the falling edge of vd or the rising edge of sen1. 00 01 02 03 04 05 06 07 41 42 43 44 45 46 47 ssi1 sck1 sen1 there are two categories of timing generator block serial interface data: CXD3406GA timing generator block drive control data (hereafter "control data") and electronic shutter data (hereafter "shutter data"). the details of each data are described below.
20 CXD3406GA control data data d00 to d07 d08 to d09 d10 to d12 d13 to d14 d15 d16 to d23 d24 to d33 d34 d35 d36 to d37 d38 to d39 d40 to d47 symbol chip ctg mode smd ptsg cdat ldad stb function chip enable category switching drive mode switching electronic shutter mode switching internal ssg output pattern switching af drive control data adclk logic phase switching standby control data = 0 data = 1 10000001 enabled other values disabled see d08 to d09 ctg. see d10 to d12 mode. see d13 to d14 smd. ntsc equivalent pal equivalent see d16 to d23 cdat. see d36 to d37 ldad. see d38 to d39 stb. rst all 0 all 0 all 0 all 0 0 all 0 all 0 1 0 all 0 all 0 1 0
21 CXD3406GA shutter data data d00 to d07 d08 to d09 d10 to d19 d20 to d31 d32 to d41 d42 to d47 symbol chip ctg svd shd spl function chip enable category switching electronic shutter vertical period specification electronic shutter horizontal period specification high-speed shutter position specification data = 0 data = 1 10000001 enabled other values disabled see d08 to d09 ctg. see d10 to d19 svd. see d20 to d31 shd. see d32 to d41 spl. rst all 0 all 0 all 0 all 0 all 0 all 0
22 CXD3406GA detailed description of each data shared data: d08 to d09 ctg [category] of the data provided to the CXD3406GA by the timing generator block serial interface, the CXD3406GA loads d10 and subsequent data to each data register as shown in the table below according to the combination of d08 and d09 . d09 0 0 1 d08 0 1 x description of operation loading to control data register loading to shutter data register test mode d11 0 0 1 1 0 1 d12 0 0 0 0 1 1 d10 0 1 0 1 x x description of operation draft mode (sextuple speed: default) frame mode (a field readout) frame mode (b field readout) frame mode af1 mode af2 mode note that the CXD3406GA can apply these categories consecutively within the same vertical period. however, care should be taken as the data is overwritten if the same category is applied. control data: d10 to d12 mode [drive mode] the CXD3406GA timing generator block drive mode can be switched as follows. however, the drive mode bits are loaded to the CXD3406GA and reflected at the falling edge of vd. control data: d15 ptsg [internal ssg output pattern] the CXD3406GA internal ssg output pattern can be switched as follows. however, the drive mode bits are loaded to the CXD3406GA and reflected at the falling edge of vd. d15 0 1 description of operation ntsc equivalent pattern pal equivalent pattern the vd period in each pattern is defined as follows for each drive mode. ? 1 only 944h and 945h are 1208ck period. see the timing charts for the actual operation. ntsc equivalent pattern pal equivalent pattern frame mode 918h + 1716ck 945h ? 1 draft mode 262h + 1144ck 314h + 1568ck af1 mode 131h + 572ck 157h + 784ck af2 mode 65h + 1430ck 78h + 1536ck
23 CXD3406GA control data: d36 to d37 ldad [adclk logic phase] this indicates the adclk logic phase adjustment data. the default is 90 relative to mcko. control data: d38 to d39 stb [standby] the operating mode of the timing generator block is switched as follows. however, the standby bits are loaded to the CXD3406GA and control is applied immediately at the rising edge of sen1. d37 0 0 1 1 d36 0 1 0 1 degree of adjustment ( ) 0 90 180 270 d39 x 0 1 d38 0 1 1 symbol cam slp stb operating mode normal operating mode sleep mode standby mode see the pin status table for the pin status in each mode.
24 CXD3406GA the frame shift data is expressed as shown in the table below using d16 to d23 cdat. msb lsb d23 d22 d21 d20 d19 d18 d17 d16 0110 6 1001 9 cdat is expressed as 69h . its definition area is specified as follows. af1 mode: 00h cdat ffh (11 to 23h) af2 mode: 00h cdat ffh (14 to 27h) control data: [af drive] the CXD3406GA controls the drive of the vertical cut-out area of the line in af1/af2 mode by using control data d16 to d23 cdat. this mode has a function on purpose to raise frame rate for auto focus (af), and cannot support operation such as electrical image stabilization. the af drive bits are loaded to the CXD3406GA and reflected at the falling edge of vd. as shown in the figure below, first, the fixed stage is swept at high speed, and it goes to readout period and vertical ob period. then normal transfer is performed equivalent to draft mode from the frame shift to the stage specified by the serial interface data to the timing of the falling edge of the next vd. therefore, the number of frame shift stages applied to cdat and the control by vd period are conditions for its application. vd 0 v1a vck mode 00h ffh cdat 4 0 00h frame shift normal transfer high-speed sweep the number of high-speed sweep are different according to the selected mode. they are specified as follows. af1 mode: 138 stages (0 to 7h) af2 mode: 208 stages (0 to 11h)
25 CXD3406GA control data/shutter data: [electronic shutter] the CXD3406GA realizes various electronic shutter functions by using control data d13 to d14 smd and shutter data d10 to d19 svd, d20 to d31 shd and d32 to d41 spl. these functions are described in detail below. first, the various modes are shown below. these modes are switched using control data d13 to d14 smd. d14 0 0 1 1 d13 0 1 0 1 description of operation electronic shutter stopped mode high-speed/low-speed shutter mode htsg control mode the electronic shutter data is expressed as shown in the table below using d20 to d31 shd as an example. however, msb (d31) is a reserve bit for the future specification, and it is handled as a dummy on this ic. msb lsb d29 d28 d31 d30 d27 d26 d25 d24 d23 d22 d21 d20 1100 c x001 1 0011 3 shd is expressed as 1c3h . [electronic shutter stopped mode] during this mode, all shutter data items are invalid. sub is not output in this mode, so the shutter speed is the accumulation time for one field. [high-speed/low-speed shutter mode] during this mode, the shutter data items have the following meanings. the period during which svd and shd are specified together is the shutter speed. concretely, when specifying high-speed shutter, svd is set to "000h". (see the figure.) during low-speed shutter, or in other words when svd is set to "001h" or higher, the serial interface data is not loaded until this period is finished. the vertical period indicated here corresponds to one field in each drive mode. in addition, the number of horizontal periods applied to shd can be considered as (number of sub pulses 1). however, in the frame mode a field, it matches (number of sub pulses + 1). this is a specification for flickerless when the same mode is repeated. but this change may not occur because of flickerless depending on the conditions during low-speed shutter. note) the bit data definition area is assured in terms of the CXD3406GA functions, and does not assure the ccd characteristics. symbol svd shd spl data d10 to d19 d20 to d31 d32 to d41 description number of vertical periods specification (000h svd 3ffh) number of horizontal periods specification (000h shd 7ffh) vertical period specification for high-speed shutter operation (000h spl 3ffh)
26 CXD3406GA vd shd 01 v1a sub wen smd 000h 002h svd 050h 10fh shd 01 svd vd spl shd 01 v1a sub wen smd 000h 001h spl 000h 002h svd 0a3h 10fh shd 10 svd further, spl can be used during this mode to specify the sub output at the desired vertical period during the low-speed shutter period. in the case below, sub is output based on shd at the spl vertical period out of (svd + 1) vertical periods. incidentally, spl is counted as "000h", "001h", "002h" and so on in conformance with svd. using this function, it is possible to achieve smooth exposure time transitions when changing from low-speed shutter to high-speed shutter or vice-versa.
27 CXD3406GA vd v1a sub wen 01 11 exposure time 01 smd vck [htsg control mode] during this mode, all shutter data items are invalid. the v1a/b and v3a/b ternary level outputs are stopped, so the shutter speed is the value obtained by adding the shutter speed specified in the preceding vertical period to the vertical period during which these readout pulses are stopped as shown in the figure.
28 CXD3406GA vd sub clpob clpdm v1a c high-speed sweep block high-speed sweep block c v1b v2 v3a v3b v4 ccd out 1547 1549 1542 1544 1546 1548 1550 1539 1541 1543 1545 3 1 57 24682 6 4 81012 13579111315 pblk id wen a field b field hd 918 1 29 34 12834 918 810 810 a b ? the number of sub pulses is determined by the serial interface data. this chart shows the case where sub pulses are output in e ach horizontal period. ? id is low for lines where ccd out contains the r component, and high for lines where ccd out contains the b component. ? vd of this chart is ntsc equivalent pattern (918h + 1716ck units). for pal equivalent pattern, it is 945h units, but 1208ck per iod only for 944h and 945h. chart-1 vertical direction timing chart mode frame mode applicable ccd image sensor icx252/262
29 CXD3406GA vd hd sub v1a v2 v3a v3b v4 clpob clpdm id pblk v1b ccd out 15 10 3 6 22 27 34 13 8 1 4 20 546 539 534 527 544 537 532 525 549 25 32 10 3 6 15 22 27 34 8 1 4 13 20 25 32 546 539 534 527 544 537 532 525 549 wen 2 1 262 261 2 1 262 261 d d ? the number of sub pulses is determined by the serial interface data. this chart shows the case where sub pulses are output in e ach horizontal period. ? id is low for lines where ccd out contains the r component, and high for lines where ccd out contains the b component. ? vd of this chart is ntsc equivalent pattern (262h + 1144ck units). for pal equivalent pattern, it is 314h + 1568ck units. chart-2 vertical direction timing chart mode draft mode applicable ccd image sensor icx252/262
30 CXD3406GA vd ccd out 6 4 6 4 wen hd id clpob clpdm pblk v1a v1b v2 v3b v4 sub v3a 10 25 1 8 131 10 25 1 8 131 high-speed sweep block high-speed sweep block frame shift block fd g frame shift block f d g ? the number of sub pulses is determined by the serial interface data. this chart shows the case where sub pulses are output in e ach horizontal period. ? id is low for lines where ccd out contains the r component, and high for lines where ccd out contains the b component. ? 138 stages are fixed for high-speed sweep block ; 0 to 255 stages can be specified by the serial interface for the frame shift block. ? vd of this chart is ntsc equivalent pattern (131h + 572ck units). for pal equivalent pattern, it is 157h + 784ck units. chart-3 vertical direction timing chart mode af1 mode applicable ccd image sensor icx252/262
31 CXD3406GA vd ccd out 6 4 6 4 wen hd id clpob clpdm pblk v1a v1b v2 v3b v4 sub v3a f high-speed sweep block frame shift block dg f high-speed sweep block frame shift block d g 14 29 1 12 65 14 29 1 12 65 ? the number of sub pulses is determined by the serial interface data. this chart shows the case where sub pulses are output in e ach horizontal period. ? id is low for lines where ccd out contains the r component, and high for lines where ccd out contains the b component. ? 208 stages are fixed for high-speed sweep block ; 0 to 255 stages can be specified by the serial interface for the frame shift block. ? vd of this chart is ntsc equivalent pattern (65h + 1430ck units). for pal equivalent pattern, it is 78h + 1536ck units. chart-4 vertical direction timing chart mode af2 mode applicable ccd image sensor icx252/262
32 CXD3406GA 148 hd mcko h1 h2 v1a/b v2 v3a/b v4 sub pblk clpob clpdm (2288) 050 52 100 150 110 70 99 47 10 174 90 52 70 200 250 id wen 198 172 198 157 128 110 110 138 52 ? hd of this chart indicates the actual CXD3406GA load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.9 to 9.5s (when the drive frequency is 18mhz). this chart shows a period of 115ck (6.4s). internal ssg is at this timing. ? sub is output at this timing shown above when output is controlled by the serial interface data. ? id and wen are output at this timing shown above at the position shown in chart-1. chart-5 horizontal direction timing chart mode frame mode applicable ccd image sensor icx252/262
33 CXD3406GA hd mcko h1 h2 v1a/b v2 v3a/b v4 sub pblk clpob clpdm (2288) 050 52 100 150 70 106 93 66 47 10 174 52 200 250 id wen 198 172 198 84 120 75 110 110 140 52 88 79 102 151 111 147 97 156 129 115 61 71 142 57 138 124 133 ? hd of this chart indicates the actual CXD3406GA load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.9 to 9.5s (when the drive frequency is 18mhz). this chart shows a period of 115ck (6.4s). internal ssg is at this timing. ? sub is output at this timing shown above when output is controlled by the serial interface data. ? id and wen are output at this timing shown above at the position shown in charts-2, 3 and 4. chart-6 horizontal direction timing chart mode draft/af1/af2 mode applicable ccd image sensor icx252/262
34 CXD3406GA hd mcko h1 h2 v1a/b v2 v3a/b v4 sub pblk clpob clpdm (2288) 050 52 100 150 52 139 110 197 71 70 200 250 id wen 172 100 129 138 52 81 100 129 110 168 187 274 158 168 226 158 139 #4 #3 #2 #1 81 255 274 245 216 187 71 216 245 197 255 226 ? hd of this chart indicates the actual CXD3406GA load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.9 to 9.5s (when the drive frequency is 18mhz). this chart shows a period of 115ck (6.4s). internal ssg is at this timing. ? sub is output at this timing shown above when output is controlled by the serial interface data. ? high-speed sweep of v1a/b, v2, v3a/b and v4 is performed up to 26h of 768ck(#1038). chart-7 horizontal direction timing chart (high-speed sweep: c) mode frame mode applicable ccd image sensor icx252/262
35 CXD3406GA hd mcko h1 h2 v1a/b v2 v3a/b v4 sub pblk clpob clpdm (2288) 050 52 100 150 71 52 109 90 147 64 47 10 52 200 250 id wen 172 83 121 140 71 105 110 140 52 90 128 83 102 140 159 197 254 109 147 166 102 159 178 216 223 261 280 273 128 204 242 121 235 273 261 216 223 178 185 166 64 185 204 242 197 #2 #1 235 254 219 71 ? hd of this chart indicates the actual CXD3406GA load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.9 to 9.5s (when the drive frequency is 18mhz). this chart shows a period of 115ck (6.4s). internal ssg is at this timing. ? sub is output at this timing shown above when output is controlled by the serial interface data. ? wen is output at this timing shown above at the position shown in chart-3 and 4. ? high-speed sweep of v1a/b, v2, v3a/b and v4 is performed up to 6h of 2056ck (#138) in af1 mode and 10h of 884ck (#208) in af2 mode. ? frame shift of v1a/b, v2, v3a/b and v4 receives the output control by the serial interface data and can specify up to #255 for both of af1/af2 mode. ? id is output at the timing shown with dotted line during frame shift. chart-8 horizontal direction timing chart (high-speed sweep: f) (frame shift: g) mode af1/af2 mode applicable ccd image sensor icx252/262
36 CXD3406GA hd [a field] [b field] [a] [b] v3b v4 v3b v4 v1a v1b v2 v3a v1a v1b v2 v3a (2288) 0 52 70 110 90 128 99 148 157 181 211 241 (2288) 0 52 70 128 90 148 99 110 157 1100 1130 1160 1190 1280 1310 1250 logic alignment portion ? hd of this chart indicates the actual CXD3406GA load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.9 to 9.5s (when the drive frequency is 18mhz). this chart shows a period of 115ck (6.4s). internal ssg is at this timing. chart-9 horizontal direction timing chart mode frame mode applicable ccd image sensor icx252/262
37 CXD3406GA 52 57 61 66 70 75 79 84 88 93 97 102 106 111 115 120 124 129 133 138 142 147 151 156 52 57 61 66 70 75 79 84 88 93 97 102 106 111 115 120 124 129 133 138 142 147 151 156 hd [d] v3b v4 v1a v1b v2 v3a (2288) 0 (2288) 0 1130 1160 1190 1010 1040 1070 1100 1220 1250 1280 1310 1340 1370 1400 1430 ? hd of this chart indicates the actual CXD3406GA load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.9 to 9.5s (when the drive frequency is 18mhz). this chart shows a period of 115ck (6.4s). internal ssg is at this timing. chart-10 horizontal direction timing chart mode draft/af1/af2 mode applicable ccd image sensor icx252/262
38 CXD3406GA chart-11 high-speed phase timing chart mode applicable ccd image sensor icx252/262 hd hd' cki cko adclk mcko h1 h2 rg xshp xshd xrs 172 52 1 ? hd' indicates the hd which is the actual CXD3406GA load timing. ? the phase relationship of each pulse shows the logical position relationship. for the actual output waveform, a delay is added to each pulse. ? the logical phase of adclk can be specified by the serial interface data.
39 CXD3406GA chart-12 vertical direction sequence chart mode draft frame draft applicable ccd image sensor icx252/262 vd v1a v1b v2 v3a v3b v4 sub mechanical shutter exposure time ccd out mode smd shd close open abc ee f 0 0000 3 3 0 0 01 01 01 01 01 00 00 01 01 050h 050h 050h 050h 050h 000h 000h 050h 050h abcde f ? this chart is a driving timing chart example of electronic shutter normal operation. ? data exposed at d includes blooming component. for details, see the ccd image sensor data sheet. ? the CXD3406GA does not generate the pulse to control mechanical shutter operation. ? the switching timing of the drive mode and the electronic shutter data is not the same.
40 CXD3406GA ccd signal processor block serial interface control the CXD3406GA's ccd signal processor block basically loads the ccd signal processor block serial interface data sent in the following format at the rising edge of sen2, and the setting values are then reflected to the operation 6 adclki clocks after that. ccd signal processor block serial interface control requires clock input to adclki in order to load and reflect the serial interface data to operation, so this should normally be performed when the timing generator block is in the normal operation mode. 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 ssi2 sck2 sen2 there are four categories of ccd signal processor block serial interface data: standby control data, pga gain setting data, ob clamp level setting data, and input pulse polarity setting data. note that when data from multiple categories is loaded consecutively, the data for the category loaded last is valid and data from other categories is lost. when transferring data from multiple categories, raise sen2 for each category and wait until the setting value 6 adckli clocks after that has been reflected to operation, then transmit the next category. the detail of each data are described below. standby control data data d00 d01 to d03 d04 to d14 d15 symbol test ctg fixed stb function test code category switching standby control data = 0 data = 1 set to 0. d01 to d03 ctg set to all 0. normal operating mode standby mode data d00 d01 to d03 d04 to d05 d06 to d15 symbol test ctg fixed gain function test code category switching pga gain setting data data = 0 data = 1 set to 0. d01 to d03 ctg set to all 0. see d06 to d15 gain. pga gain setting data
41 CXD3406GA data d00 d01 to d03 d04 to d11 d12 to d15 symbol test ctg fixed oblvl function test code category switching ob clamp level setting data data = 0 data = 1 set to 0. d01 to d03 ctg set to all 0. see d12 to d15 oblvl. ob clamp level setting data data d00 d01 to d03 d04 to d12 d13 to d15 symbol test ctg fixed pol function test code category switching input pulse polarity setting data data = 0 data = 1 set to 0. d01 to d03 ctg set to all 0. set to all 0. input pulse polarity setting data
42 CXD3406GA detailed description of each data shared data: d01 to d03 ctg [category] of the data provided to the CXD3406GA by the ccd signal processor block serial interface, the CXD3406GA loads d04 and subsequent data to each data register as shown in the table below according to the combination of d01 to d03 . pga gain setting data: d06 to d15 gain [pga gain] the CXD3406GA can set the programmable gain amplifier (pga) gain from 6db to +42db in 1024 steps by using pga gain setting data d06 to d15 gain. the pga gain setting data is expressed as shown in the table below using d06 to d15 gain. d01 0 0 0 0 1 d02 0 0 1 1 x d03 0 1 0 1 x description of operation loading to standby control data register loading to pga gain setting data register loading to ob clamp level setting data register loading to input pulse polarity setting data register access prohibited standby control data: d15 stb [standby] the operating mode of the ccd signal processor block is switched as follows. when the ccd signal processor block is in standby mode, only the serial interface is valid. d15 0 1 description of operation normal operating mode standby mode msb lsb d06 d07 d08 d09 d10 d11 d12 d13 d14 d15 1100 c 01 1 0011 3 gain is expressed as 1c3h . for example, when gain is set to "000h", "080h", "220h", "348h" and "3ffh", the respective pga gain setting values are 6db, 0db, +20db, +34db and +42db.
43 CXD3406GA ob clamp level setting data: d12 to d15 oblvl [ob clamp level] the CXD3406GA can set the opb clamp output value from 0 to 60lsb in 4lsb steps by using ccd signal processor block control data d12 to d15 oblvl. the opb clamp output setting data is expressed as shown in the table below using d12 to d15 oblvl. msb lsb d12 d13 d14 d15 0110 6 oblvl is expressed as 6h . for example, when oblvl is set to "0h", "1h", "8h" and "fh", the respective opb clamp output setting values are 0lsb, 4lsb, 32lsb and 60lsb.
44 CXD3406GA application circuit block diagram sen2 sck2 ssi2 f9 f8 f7 g2 g3 g9 g8 g7 h2 h1 g1 b7 a7 c6 b3 a1 a2 b2 b1 c3 c2 c1 d3 d2 d1 e1 j2 k2 m2 n2 n9 m9 m8 n8 l8 m4 n5 l5 k8 j9 j8 c8 c7 d8 d7 c9 n4 l5 n7 n6 a3 b4 a4 m1 n1 l2 b5 c4 l1 j1 k1 a5 m7 m3 h3 ccd icx252/262 tg/cds/pga/adc CXD3406GA controller ssi1 sen1 sck1 test5 test4 test3 test2 test1 osco cki osci d1 vd hd d0 (lsb) signal processor block d2 nc nc d3 d4 d5 d6 d7 d8 d9 (msb) mcko cko ssgsl sncsl rst wen id 0.1f c7 xshpi xshdi pblki clpdmi clpobi xshp xshd pblk clpdm clpob adclk adclki 0.1f c8 0.1f c9 1f c1 1f ccdin ccdout 390pf c2 390pf c3 240pf c4 h1 h2 rg v1a v1b v2 v3a v3b v4 sub application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same . this block diagram illustrates connections with each circuit block, and is not an actual circuit diagram. see the ccd image sensor data sheet for an example of specific circuit connections with the ccd image sensor.
45 CXD3406GA notes on operation 1. be sure to start up the timing generator block vl and vh pin power supplies at the timing shown in the figure below in order to prevent the sub pin of the ccd image sensor from going to negative potential. in addition, start up the timing generator block v dd1 , v dd2 , v dd3 , v dd4 and v dd5 pin and ccd signal processor block dv dd1 , dv dd2 , av dd1 , av dd2 , av dd3 , av dd4 and av dd5 pin power supplies at the same time either before or at the same time as the vh pin power supply is started up. 2. reset the timing generator block and ccd signal processor block during power-on. the timing generator block is reset by inputting the reset signal to the rst pin. the ccd signal processor block is reset by initializing the serial data. 3. separate the timing generator block v dd1 , v dd2 , v dd3 , v dd4 and v dd5 pins from the ccd signal processor block dv dd1 , dv dd2 , av dd1 , av dd2 , av dd3 , av dd4 and av dd5 pins. also, the adc output driver stage is connected to the dedicated power supply pin dv dd1 . separating this pin from other power supplies is recommended to avoid affecting the internal analog circuits. 4. the difference in potential between the timing generator block v dd4 pin supply voltage 3 v dd c and the ccd signal processor block dv dd1 , dv dd2 , av dd1 , av dd2 , av dd3 , av dd4 and av dd5 pin supply voltages 1 v dd e, 2 v dd f and 3 v dd g should be 0.1v or less. 5. the timing generator block and ccd signal processor block ground pins should use a shared ground which is connected outside the ic. when the set ground is divided into digital and analog blocks, connect the timing generator block ground pins to the digital ground and the ccd signal processor block ground pins to the analog ground. the difference in potential between the timing generator block v ss1 , v ss2 , v ss3 , v ss4 , v ss5 , v ss6 and vm and the ccd signal processor block dv ss1 , dv ss2 , dv ss3 , av ss1 , av ss2 , av ss3 , av ss4 , av ss5 and av ss6 should be 0.1v or less. 6. do not perform serial communication with the ccd signal processor block during the effective image period, as this may cause the picture quality to deteriorate. in addition, using sck2, ssi2 and sen2, which are used by the ccd signal processor block, use of the dedicated ports is recommended. when using these pins as shared ports with the timing generator block or other ics, be sure to thoroughly confirm the effects on picture quality before use. t1 t2 15.0v 0v 7.5v 20% 20% t2 t1
46 CXD3406GA package outline unit: mm 96pin lflga package mass package structure organic substrate 0.3 g package material terminal treatment terminal material gold plating nickel plating sony code eiaj code jedec code lflga-96p-02 p-lflga96-12x8-0.8 1.3 max s 0.10 detail x s s 0.2 pin 1 index x b b 0.2 12.0 s 8.0 a 0.2 s 0.15 x4 0.8 b d e f g h j k l c a m n 123456789 0.8 m sab 96 - 0.45 0.05 a 0.5 0.5 3 0.50 0.5 0.9 0.9 1.2 0.8 0.10max 0.5 0.08 (0.3) (0.3) (0.3) (0.3) sony corporation 96pin lflga package mass package structure organic substrate 0.3g package material terminal treatment terminal material sony code eiaj code jedec code lflga-96p-051 p-lflga96-12.0x8.0-0.8 1.3 max s 0.10 detail x s s 0.2 pin 1 index x b b 0.2 12.0 s 8.0 a 0.2 s 0.15 x4 0.8 b d e f g h j k l c a m n 123456789 0.8 m sab 96 - 0.45 0.05 a 0.5 0.5 3 0.50 0.5 0.9 0.9 1.2 0.8 0.10max 0.5 0.08 (0.3) (0.3) (0.3) (0.3) nickel & gold plating copper oita ass'y hitachi tokyo ass'y

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