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hm514265c series hm51s4265c series 262,144-word 16-bit dynamic random access memory ade-203-309a (z) rev. 1.0 jul. 21, 1995 description the hitachi hm51(s)4265c is a cmos dynamic ram organized 262,144-word 16-bit. hm51(s)4265c has realized higher density, higher performance and various functions by employing 0.8 m m cmos process technology and some new cmos circuit design technologies. the hm51(s)4265c offers extended data out (edo) page mode as a high speed access mode. multiplexed address input permits the hm51(s)4265c to be packaged in standard 400-mil 40-pin plastic soj and standard 400-mil 44-pin plastic tsopii. internal refresh timer enables hm51s4265c self reflesh operation. features single 5 v ( 10%) (hm51(s)4265c-6/7/8) ( 5%) (hm51(s)4265c-6r) high speed access time: 60 ns/70 ns/80 ns (max) low power dissipation active mode: 825 mw/788 mw/770 mw/688 mw (max) standby mode: 11 mw (max) (hm51(s)4265c-6/7/8) 10.5 mw (max) (hm51(s)4265c-6r) 1.1 mw (max) (l-version) (hm51(s)4265cl-6/7/8) 1.05 mw (max) (l-version) (hm51(s)4265cl-6r) edo page mode capability 512 refresh cycles : 8 ms 128 ms (l-version) 2 variations of refresh ras -only refresh cas -before- ras refresh ? cas -byte control battery backup operation (l-version) self refresh operation (hm51s4265c)
hm514265c, hm51s4265c series 2 ordering information type no. access time package hm514265cj-6 hm514265cj-6r hm514265cj-7 hm514265cj-8 60 ns 60 ns 70 ns 80 ns 400-mil 40-pin plastic soj (cp-40da) hm514265clj-6 hm514265clj-6r hm514265clj-7 hm514265clj-8 60 ns 60 ns 70 ns 80 ns hm51s4265cj-6 hm51s4265cj-6r hm51s4265cj-7 hm51s4265cj-8 60 ns 60 ns 70 ns 80 ns hm51s4265clj-6 HM51S4265CLJ-6R hm51s4265clj-7 hm51s4265clj-8 60 ns 60 ns 70 ns 80 ns hm514265ctt-6 hm514265ctt-6r hm514265ctt-7 hm514265ctt-8 60 ns 60 ns 70 ns 80 ns 400-mil 44-pin plastic tsopii (ttp-44/40db) hm514265cltt-6 hm514265cltt-6r hm514265cltt-7 hm514265cltt-8 60 ns 60 ns 70 ns 80 ns hm51s4265ctt-6 hm51s4265ctt-6r hm51s4265ctt-7 hm51s4265ctt-8 60 ns 60 ns 70 ns 80 ns hm51s4265cltt-6 hm51s4265cltt-6r hm51s4265cltt-7 hm51s4265cltt-8 60 ns 60 ns 70 ns 80 ns
hm514265c, hm51s4265c series 3 pin arrangement v i/o0 i/o1 i/o2 i/o3 v i/o4 i/o5 i/o6 i/o7 nc nc we ras nc a0 a1 a2 a3 v cc cc cc v i/o15 i/o14 i/o13 i/o12 v i/o11 i/o10 i/o9 i/o8 nc lcas ucas oe a8 a7 a6 a5 a4 v ss ss ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 (top view) hm514265ctt/clttseries hm51s4265ctt/clttseries (top view) v i/o0 i/o1 i/o2 i/o3 v i/o4 i/o5 i/o6 i/o7 nc nc we ras nc a0 a1 a2 a3 v cc cc cc v i/o15 i/o14 i/o13 i/o12 v i/o11 i/o10 i/o9 i/o8 nc lcas ucas oe a8 a7 a6 a5 a4 v ss ss ss 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 32 31 30 29 28 27 26 25 24 23 hm514265cj/clj series hm51s4265cj/clj series pin description pin name function a0 a8 address input row address a0 a8 column address a0 a8 refresh address a0 a8 i/o0 i/o15 data-in/data-out ras row address strobe ucas , lcas column address strobe we read/write enable oe output enable v cc power (+5 v) v ss ground nc no connection
hm514265c, hm51s4265c series 4 block diagram 256 k memory array mat i/o bus & column decoder 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat i/o bus & column decoder peripheral circuit i/o bus & column decoder i/o bus & column decoder 256 k memory array mat i/o bus & column decoder 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat i/o bus & column decoder peripheral circuit i/o bus & column decoder i/o bus & column decoder row decoder row decoder row decoder row decoder row decoder row decoder row decoder row decoder selector selector selector selector peripheral circuit we ras ucas oe i/o12 buffer i/o13 buffer i/o14 buffer i/o15 buffer i/o0 buffer i/o1 buffer selector selector selector selector i/o2 buffer i/o3 buffer i/o4 buffer i/o12 i/o13 i/o14 i/o15 i/o0 i/o1 i/o2 i/o3 i/o4 address a0,a1,a2,a3 address a4,a5 a6,a7,a8 row decoder row decoder row decoder row decoder row decoder row decoder row decoder row decoder i/o5 buffer i/o5 i/o6 buffer i/o6 i/o7 buffer i/o7 i/o11 i/o10 i/o9 i/o8 i/o11 buffer i/o10 buffer i/o9 buffer i/o8 buffer lcas
hm514265c, hm51s4265c series 5 operation mode the hm51(s)4265c series has the following 11 operation modes. 1. read cycle 2. early write cycle 3. delayed write cycle 4. read-modify-write cycle 5. ras -only refresh cycle 6. cas -before- ras refresh cycle 7. self refresh cycle (hm51s4265c) 8. edo page mode read cycle 9. edo page mode early write cycle 10. edo page mode delayed write cycle 11. edo page mode read- modify-write cycle inputs ras lcas ucas we oe output operation h h h d d open standby h l l h l valid standby l l l h l valid read cycle llll *2 d open early write cycle llll *2 h undefined delayed write cycle l l l h to l l to h valid read-modify-write cycle l h h d d open ras -only refresh cycle h to l h l d d open cas -before- ras refresh cycle l h self refresh cycle (hm51s4265c) ll l h to l h to l h l valid edo page mode read cycle l h to l h to l l *2 d open edo page mode early write cycle l h to l h to l l *2 h undefined edo page mode delayed write cycle l h to l h to l h to l l to h valid edo page mode read-modify-write cycle l l l h h open read cycle (output disabled) notes: 1. h: high(inactive) l: low(active) d: h or l 2. t wcs 3 0 ns early write cycle t wcs < 0 ns delayed write cycle 3. mode is determined by the or function of the ucas and lcas . (mode is set by the earliest of ucas and lcas active edge and reset by the latest of ucas and lcas inactive edge.) however write operation and output hiz control are done independently by each ucas , lcas . ex. if ras = h to l, lcas = l, ucas = h, then cas -before- ras refresh cycle is selected.
hm514265c, hm51s4265c series 6 absolute maximum ratings parameter symbol value unit voltage on any pin relative to v ss v t 1.0 to +7.0 v supply voltage relative to v ss v cc 1.0 to +7.0 v short circuit output current iout 50 ma power dissipation p t 1.0 w operating temperature topr 0 to +70 c storage temperature tstg 55 to +125 c recommended dc operating conditions (ta = 0 to +70 c) parameter symbol min typ max unit notes supply voltage v ss 000v v cc (hm51(s)4265c-6/7/8) 4.5 5.0 5.5 v 1, 2 v cc (hm51(s)4265c-6r) 4.75 5.0 5.25 v 1, 2 input high voltage v ih 2.4 6.5 v 1 input low voltage v il 1.0 0.8 v 1 notes: 1. all voltage referred to v ss . 2. the supply voltage with all v cc pins must be on the same level. the supply voltage with all v ss pins must be on the same level.
hm514265c, hm51s4265c series 7 dc characteristics (ta = 0 to 70 c, v cc = 5 v 5%, v ss = 0 v) (hm51(s)4265c-6r) (ta = 0 to +70 c, v cc = 5 v 10%, v ss = 0 v) (hm51(s)4265c-6/7/8) hm514265c, hm51s4265c -6/6r -7 -8 parameter symbol min max min max min max unit test conditions operating current *1, *2 i cc1 150 140 125 ma ras cycling ucas or lcas cycling t rc = min standby current i cc2 2 2 2 ma ttl interface ras , ucas , lcas = v ih dout = high-z 1 1 1 ma cmos interface ras , ucas , lcas , we , oe 3 v cc 0.2 v dout = high-z standby current (l- version) i cc2 200 200 200 m a cmos interface ras , ucas , lcas , we , oe 3 v cc 0.2 v dout = high-z ras -only refresh current *2 i cc3 140 130 110 ma t rc = min standby current *1 i cc5 5 5 5ma ras = v ih , ucas or lcas = v il dout = enable cas -before- ras refresh current *2 i cc6 140 130 110 ma t rc = min edo page mode current *1, *3 i cc4 180 150 130 ma t hpc = min battery backup current *4 (standby with cbr refresh) (l-version) i cc10 300 300 300 m a standby: cmos interface dout = high-z cbr refresh: t rc = 250 m s t ras 1 m s, ucas , lcas = v il we , oe = v ih self-refresh mode current (hm51s4265c) i cc11 1 1 1 ma cmos interface ras , ucas , lcas 0.2 v, dout = high-z self-refresh mode current (hm51s4265cl) i cc11 200 200 200 m a cmos interface ras , ucas , lcas 0.2 v, dout = high-z input leakage current i li 10 10 10 10 10 10 m a 0 v vin 7 v output leakage current i lo 10 10 10 10 10 10 m a 0 v vout 7 v dout = disable output high voltage v oh 2.4 v cc 2.4 v cc 2.4 v cc v high iout = 2 ma
hm514265c, hm51s4265c series 8 hm514265c, hm51s4265c -6/6r -7 -8 parameter symbol min max min max min max unit test conditions output low voltage v ol 0 0.4 0 0.4 0 0.4 v low iout = 2 ma notes: 1. i cc depends on output load condition when the device is selected. i cc max is specified at the output open condition. 2. address can be changed twice or less while ras = v il . 3. address can be changed once or less within one edo page cycle. 4. v ih 3 v cc 0.2 v, 0 v il 0.2 v, address can be changed once or less while ras = v il . 5. all the v cc pins should be supplied with the same voltage. and all the v ss pins should be supplied with the same voltage. capacitance (ta = +25 c, v cc = 5 v 5%) (hm51(s)4265c-6r) (ta = +25 c, v cc = 5 v 10%) (hm51(s)4265c-6/7/8) parameter symbol typ max unit notes input capacitance (address) c i1 5pf1 input capacitance (clocks) c i2 7pf1 output capacitance (data-in, data-out) c i/o 10 pf 1, 2 notes: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. ras , ucas and lcas = v ih to disable dout. ac characteristics (ta = 0 to +70 c, v cc = 5 v 5%, v ss = 0 v) (hm51(s)4265c-6r) *1, *14, *15, *17, *18 (ta = 0 to +70 c, v cc = 5 v 10%, v ss = 0 v) (hm51(s)4265c-6/7/8) *1, *14, *15, *17, *18 test conditions input rise and fall time : 2 ns input level : v il = 0 v, v ih = 3.0 v input timing reference levels : 0.8 v, 2.4 v output timing reference levels : 0.8 v, 2.0 v output load : 1 ttl gate + c l (50 pf) (including scope and jig)
hm514265c, hm51s4265c series 9 read, write, read-modify-write and refresh cycles (common parameters) hm514265c, hm51s4265c -6/-6r -7 -8 parameter symbol min max min max min max unit notes random read or write cycle time t rc 104 124 144 ns ras precharge time t rp 40 50 60 ns ras pulse width t ras 60 10000 70 10000 80 10000 ns 27 cas pulse width t cas 10 10000 13 10000 15 10000 ns 28 row address setup time t asr 0 0 0 ns row address hold time t rah 10 10 10 ns column address setup time t asc 0 0 0 ns 19 column address hold time t cah 10 13 15 ns 19 ras to cas delay time t rcd 20 45 20 50 20 60 ns 8 ras to column address delay time t rad 15 30 15 35 15 40 ns 9 ras hold time t rsh 15 18 20 ns cas hold time t csh 48 58 68 ns 29 cas to ras precharge time t crp 10 10 10 ns 20 oe to din delay time t odd 15 18 20 ns oe delay time from din t dzo 0 0 0 ns cas setup time from din t dzc 0 0 0 ns transition time (rise and fall) t t 250 250 250 ns7 refresh period t ref 8 8 8ms refresh period (l-version) t ref 128 128 128 ms
hm514265c, hm51s4265c series 10 read cycle hm514265c, hm51s4265c -6/-6r -7 -8 parameter symbol min max min max min max unit notes access time from ras t rac 60 70 80 ns 2, 3 access time from cas t cac 15 20 20 ns 3, 4, 13 access time from address t aa 30 35 40 ns 3, 5, 13 access time from oe t oac 15 20 20 ns 23 read command setup time t rcs 0 0 0 ns 19 read command hold time to cas t rch 0 0 0 ns 16, 19 read command hold time to ras t rrh 0 0 0 ns 16 column address to ras lead time t ral 30 35 40 ns column address to cas lead time t cal 18 23 28 ns output buffer turn-off time t off1 15 15 15 ns 6, 25 output buffer turn-off time to oe t off2 15 15 15 ns 6 cas to din delay time t cdd 15 18 20 ns ras to din delay time t rdd 15 18 20 ns we to din delay time t wdd 15 18 20 ns oe pulse width t oep 15 20 20 ns 23 turn-off to ras t ofr 15 15 15 ns 6, 25 turn-off to we t wez 15 15 15 ns 6 output data hold time t oh 5 5 5 ns output data hold time from ras t ohr 5 5 5 ns read command hold time from ras t rchr 60 70 80 ns read command hold time from cas t rchc 15 18 20 ns read command hold time from column address t rcha 30 35 40 ns
hm514265c, hm51s4265c series 11 write cycle hm514265c, hm51s4265c -6/-6r -7 -8 parameter symbol min max min max min max unit notes write command setup time t wcs 0 0 0 ns 10, 19 write command hold time t wch 10 13 15 ns 19 write command pulse width t wp 10 10 10 ns write command to ras lead time t rwl 10 13 15 ns write command to cas lead time t cwl 10 13 15 ns 21 data-in setup time t ds 0 0 0 ns 11 data-in hold time t dh 10 13 15 ns 11 read-modify-write cycle hm514265c, hm51s4265c -6/-6r -7 -8 parameter symbol min max min max min max unit notes read-modify-write cycle time t rwc 133 159 183 ns ras to we delay time t rwd 77 90 102 ns 10 cas to we delay time t cwd 32 38 42 ns 10 column address to we delay time t awd 47 55 62 ns 10 oe hold time from we t oeh 15 18 20 ns refresh cycle hm514265c, hm51s4265c -6/-6r -7 -8 parameter symbol min max min max min max unit notes cas setup time (cbr refresh cycle) t csr 10 10 10 ns 19 cas hold time (cbr refresh cycle) t chr 10 10 10 ns 20 ras precharge to cas hold time t rpc 10 10 10 ns 19 cas precharge time in normal mode t cpn 10 13 15 ns 22
hm514265c, hm51s4265c series 12 edo page mode cycle hm514265c, hm51s4265c -6/-6r -7 -8 parameter symbol min max min max min max unit notes edo page mode cycle time t hpc 25 30 35 ns 24 edo page mode cas precharge time t cp 10 13 15 ns edo page mode ras pulse width t rasc 100000 100000 100000 ns 12 access time from cas precharge t acp 35 40 45 ns 3, 13, 17 ras hold time from cas precharge t rhcp 35 40 45 ns output data hold time from cas low t doh 3 3 3 ns 26 cas hold time referred oe t col 10 13 20 ns cas to oe setup time t cop 5 5 5 ns read command hold time from cas precharge t rchp 35 40 45 ns edo page mode read-modify-write cycle hm514265c, hm51s4265c -6/-6r -7 -8 parameter symbol min max min max min max unit notes edo page mode read-modify-write cycle time t hpcm 66 77 86 ns edo page mode read-modify-write cycle cas precharge to we delay time t cpw 52 60 67 ns 10 self refresh mode hm51s4265c -6/-6r -7 -8 parameter symbol min max min max min max unit notes ras pulse width (self refresh) t rass 100 100 100 ns 30, 31, 32 ras precharge time (self refresh) t rps 110 130 150 ns cas hold time (self refresh) t chs 50 50 50 ns 21
hm514265c, hm51s4265c series 13 notes: 1. ac measurements assume t t = 2 ns. 2. assumes that t rcd t rcd (max) and t rad t rad (max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. 3. measured with a load circuit equivalent to 1 ttl loads and 50 pf. 4. assumes that t rcd 3 t rcd (max) and t rad t rad (max). 5. assumes that t rcd t rcd (max) and t rad 3 t rad (max). 6. t off1 (max), t off2 (max), t ofr (max) and t wez (max) define the time at which the output achieves the open circuit condition and is not referred to output voltage levels. 7. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also, transition times are measured between v ih and v il . 8. operation with the t rcd (max) limit insures that t rac (max) can be met, t rcd (max) is specified as a reference point only, if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . 9. operation with the t rad (max) limit insures that t rac (max) can be met, t rad (max) is specified as a reference point only, if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . 10. t wcs , t rwd , t cwd and t awd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only: if t wcs 3 t wcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t rwd 3 t rwd (min), t cwd 3 t cwd (min), t awd 3 t awd (min) and t cpw 3 t cpw (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. these parameters are referred to cas leading edge in an early write cycle and to we leading edge in a delayed write or a read-modify-write cycle. 12. t rasc defines ras pulse width in edo page mode cycles. 13. access time is determined by the longest among t aa , t cac and t acp . 14. an initial pause of 100 m s is required after power up followed by a minimum of eight initialization cycles ( ras -only refresh cycle or cas -before- ras refresh cycle). if the internal refresh counter is used, a minimum of eight cas -before- ras refresh cycles is required. 15. in delayed write or read-modify-write cycles, oe must disable output buffer prior to applying data to the device. 16. either t rch or t rrh must be satisfied for a read cycle. 17. when both ucas and lcas go low at the same time, all 16-bit data are written into the device. ucas and lcas cannot be staggered within the same write/read cycles. 18. all the v cc and v ss pins shall be supplied with the same voltages. 19. t asc , t cah , t rcs , t rch , t wcs , t wch , t csr and t rpc are determined by the earlier falling edge of ucas or lcas . 20. t crp , t chr , t acp , t rch and t cpw are determined by the later rising edge of ucas or lcas . 21. t cwl , t dh , t ds and t chs should be satisfied by both ucas and lcas . 22. t cpn and t cp are determined by the time that both ucas and lcas are high. 23. when output buffers are enabled once, sustain the low impedance state until valid data is obtained. when output buffer is turned on and off within a very short time, generally it causes large v cc /v ss line noise, which causes to degrade v ih min/v il max level. 24. t hpc (min) can be achieved during a series of edo page mode early write cycles or edo page mode read cycles. if both write and read operation are mixed in a edo page mode ras cycle (edo page mode mix cycle (1), (2)), minimum value of cas cycle t hpc (t cas + t cp + 2t t ) becomes greater than the specified t hpc (min) value. 25. t off1 and t ofr are determined by the later rising edge of ras or cas . 26. t doh defines the time at which the output level satisfies the output timing reference levels. measured with the test conditions.
hm514265c, hm51s4265c series 14 27. t ras (min) = t rwd (min) + t rwl (min) + t t in read-modify-write cycle. 28. t cas (min) = t cwd (min) + t cwl (min) + t t in read-modify-write cycle. 29. t csh (min) can be achieved when t rcd t csh (min) t cas (min). 30. if you use distributed cbr refresh mode with 15.6 m s interval in normal read/write cycle, cbr refresh should be executed within 15.6 m s immediately after exiting from and before entering into self refresh mode. 31. if you use ras only refresh or cbr burst refresh mode in normal read/write cycle, 512 cycles of distributed cbr refresh with 15.6 m s interval should be executed within 8 ms immediately after exiting from and before entering into the self refresh mode. 32. repetitive self refresh mode without refreshing all memory is not allowed. once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 33. @ @ ? ? @ @ ? ? @ @ ? ? @ @ ? ? @ @ ? ? h or l (h: v ih (min) v in v ih (max), l: v il (min) v in v il (max)) invalid dout
hm514265c, hm51s4265c series 15 notes concerning 2 cas control 1. each of the ucas / lcas should satisfy the timing specifications individually. 2. different operation mode for upper/lower byte is not allowed; such as following. ras ucas lcas we delayed write early write 3. closely separated upper/lower byte control is not allowed. however when the condition (t cp t ul ) is satisfied, fast page mode can be performed. ras ucas lcas t ul
hm514265c, hm51s4265c series 16 timing waveforms *33 read cycle ras ucas lcas address we dout oe din t rc t ras t rp t crp t rcd t rsh t cas t t t rad t ral t asc t cah t asr row column t rah t rcs t rrh t dzc high-z dout t dzo t odd t rac t oep t aa t cac t off1 t csh t cdd t off2 t oac t cal t rdd t ofr t wdd t wez t rchr t rcha t oh t ohr t rch t rchc
hm514265c, hm51s4265c series 17 early write cycle ras ucas lcas address we din dout t rc ** t ras t rp t crp t csh t rcd t rsh t cas t t t asr t rah t asc t cah column row t wcs t wch t ds t dh din * oe t wcs wcs (min) high-z* t : h or l
hm514265c, hm51s4265c series 18 delayed write cycle address ucas lcas ras we din oe dout t rc t ras t rp t csh t rcd t rsh t cas t crp t t column row t asr t rah t asc t cah t rcs t cwl t rwl t wp t dzc t ds t dh t dzo t odd t oeh t off2 * din invalid dout comes out, when oe is low level. invalid dout* * high-z
hm514265c, hm51s4265c series 19 read-modify-write cycle address ras din dout oe we ucas lcas t rwc t ras t rp t crp t cas t rcd t t t rad t asr tt asc t cah column row t rcs t cwd t cwl t awd t rwd t rwl t wp t dzc t dh t ds din high-z t dzo t odd t t oep t cac t aa t oac t rac t off2 oeh rah dout
hm514265c, hm51s4265c series 20 edo page mode read cycle (t hpc minimum cycle operation) we din oe dout address ucas lcas ras t rasc t rhcp t rp t t t csh t rcd t cas t cp t cas t hpc t rsh t cp t cas t crp t ral t cah t asc t t asc t t rad t asr t rah t t rrh t rch t cdd t wez t high-z t t aa t t acp t t rac t aa t cac t cac t cac dout 3 dout 2 dout 1 row column 3 cah cah rcs asc t dzc t off1 t off2 t oac t dzo column 2 column 1 t rchp t rchc t rcha t oh t ohr t doh t doh t ofr acp aa t cal t cal t cal odd
hm514265c, hm51s4265c series 21 edo page mode read cycle (high-z control by we and oe ) din oe dout we address ras ucas lcas t cp t cp t cp t t t rch t rrh t dzc t cdd t rdd high-z t ofr t off2 t off1 t oh t ohr t t col t t acp t aa t cac t cac t oac t aa t rac t aa t cac t acp t t oac t off2 t aa t cac t t rasc cop t rp t cas t cas t cas t csh t hpc t hpc crp t t asr t rah column 1 column 2 column 3 column 4 t t cah t asc t cah t cah t asc t cah t asc t wdd t ral t cal t cal t cal row dout 2 dout 4 acp dout 1 t cas t rcs t t rcs dout 3 t doh t rhcp t hpc t cal t oac t wez dzo t odd dout 2 off2 rch t rchr t rchp t rchc t rcha t rchc asc
hm514265c, hm51s4265c series 22 edo page mode early write cycle (t hpc minimum cycle operation) *oe ras ucas lcas address we din dout t rasc t rp t t t csh t hpc t rsh t crp t cas t cp t cas t cp t cas t rcd t asr t rah t asc t cah t asc t cah t asc t cah row t wcs t wcs t wcs t wch t wch t wch t ds t dh t ds t dh t ds t dh din din din high-z column column column : h or l
hm514265c, hm51s4265c series 23 edo page mode delayed write cycle din we address ras dout ucas lcas t rasc t rp t t t csh t hpc t rsh t cas t rcd t cp t cas t cp t cas t crp t asr t rah t asc t t asc t cah t asc t cah row column t t rcs tt wp t cwl t cwl t t t t ds t t ds t dh din din din t rwl t rcs wp cah t rcs wp cwl dh ds dh oe t odd t oeh high-z column column
hm514265c, hm51s4265c series 24 edo page mode read-modify-write cycle din dout address ras t rasc t t cp t hpcm t t t rcd t t cp t rad t asr t asc t t t rah t t cah t t cpw t t cpw t cwl t rwd t awd t awd t awd t cwd t t cwd t cwd t rcs t wp t t wp t ds t t dh t t ds t dzc t dh t odd t dh t t dzo t oeh t oeh t oeh t aa t t off2 din din din t rp t rwl t oac t odd t off2 t t odd t dzo t off2 t t t dzo aa t we ucas lcas oe dout dout dout t cah t ds column column column row rac cwl acp wp cwl t crp asc acp t asc rcs high-z high-z oac t dzc dzc rcs oac t cas t cas t cas aa t t oep t oep t oep cah cac cac high-z cac
hm514265c, hm51s4265c series 25 edo page mode mix cycle (1) *24 din oe dout we address ras ucas lcas t cp t cp t cp t t t rch t rrh t cdd t rdd high-z t ofr t off2 t off1 t oh t t cac t aa t cac t t t aa t oac t t rasc t rp t cas t cas t cas crp t t asr t rah column 1 column 2 column 3 column 4 t asc t cah t asc t cah t cah t cah t ral t cal t cal t cal row dout 2 dout 4 acp t cas t wcs dout 3 t doh t wp t wch t wdd t wez t ds t dh t ds t dh din 3 din 1 t cal t oac t odd t cac t asc t cpw t awd off2 acp aa t acp rchp t dzo t rchc t rcha t t csh t asc
hm514265c, hm51s4265c series 26 edo page mode mix cycle (2) *24 din oe dout we address ras ucas lcas t cp t cp t cp t t t rch t rrh t cdd t rdd high-z t ofr t off2 t off1 t oh t acp t aa t cac t aa t cac t off2 t aa t oac t t rasc t rp t cas t cas t cas t csh crp t t asr t rah column 1 column 2 column 3 column 4 t asc t cah t asc t cah t cah t asc t cah t ral t cal t cal t cal row dout 1 dout 4 acp t cas dout 3 t wdd t wez t ds t dh t ds t din 3 din 2 t cal t oac t t cac t asc t wcs t rch t rcs t wch t rac t odd t dzo t oac t off2 dh odd t rchr t cpw t wp t cwl t rchp t rchc t rcha t dzo
hm514265c, hm51s4265c series 27 cas -before- ras refresh cycle ras address dout t rc t rc t rp t ras t rp t ras t rp t rpc t t t cpn t csr t chr t cpn t csr t rpc t chr t crp t off1 high-z * we : h or l ** do not extend t > t (max). untested self refresh mode may be activated and loss of data may be resulted (hm514265c). ras ras ** _ ** lcas ucas
hm514265c, hm51s4265c series 28 ras -only refresh cycle ucas lcas ras address ** * we t rc t ras t rp t t t crp t rpc t crp t asr t rah row high-z refresh address : a0 ?a8 (ax0 ?ax8) dout : h or l
hm514265c, hm51s4265c series 29 self refresh cycle ras address dout t rp t rass t rps t rpc t t t cpn t csr t chs t crp t off1 high-z * we, oe ucas lcas : h or l the low self refresh current is achieved by introducing extremely long internal refresh cycle. therefore some care needs to be taken on the refresh. 1.please do not use t rass timing, 10 ? t rass 100 ?. during this period, the device is in transition state from normal operation mode to self refresh mode. if t rass 3 100 ?, then ras precharge time should use t rps instead of t rp . 2.if you use ras only refresh or cbr burst refresh mode in normal read/write cycle, 512 cycles of distributed cbr refresh with 15.6 ? interval should be executed within 8 ms immediately after exiting from and before entering into the self refresh mode. 3. if you use distributed cbr refresh mode with 15.6 ? interval in normal read/write cycle, cbr refresh should be executed within 15.6 ? immediately after exiting from and before entering into self refresh mode. 4.repetitive self refresh mode without refreshing all memory is not allowed. once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again.
hm514265c, hm51s4265c series 30 package dimension hm514265cj/clj series (cp-40da) unit: mm 9.40 ?0.25 1 20 0.43 ?0.10 3.50 ?0.26 21 40 26.16 max 25.80 0.74 10.16 ?0.13 11.18 ?0.13 1.30 max 2.85 ?0.12 0.10 0.80 +0.25 ?.17 1.27
hm514265c, hm51s4265c series 31 hm514265ctt/cltt series (ttp-44/40db) unit: mm 0.13 m 0.80 44 23 122 18.41 18.81 max 0.27 ?0.07 1.20 max 10.16 11.76 ?0.20 0 ?5 0.145 +0.075 ?.025 1.005 max 10 13 32 35 0.10 0.50 ?0.10 0.68 0.80 0.13 ?0.05

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