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data sheet february 2002 t7504 and t5504 quad pcm codecs with filters features n 5 v only n low-power, latch-up-free cmos technology 37 mw/channel typical operating power dissipation 1 mw/channel typical powerdown dissipation n automatic master clock frequency selection 2.048 mhz or 4.096 mhz n on-chip sample and hold, autozero, and precision voltage reference n differential architecture for high noise immunity and power supply rejection n flexible time-slotted pcm interface 2.048 mhz or 4.096 mhz data rate n meets or exceeds itu-t g.711g.712 require- ments and vf characteristics of d3/d4 (as per agere systems inc.s pub43801) n operating temperature range: C40 c to +85 c n -law/a-law companding selectable description the t7504 and t5504 devices are single-chip, four- channel -law/a-law pcm codecs with filters. these integrated circuits provide analog-to-digital and digital-to-analog conversion. they provide the transmit and receive filtering necessary to interface a voice telephone circuit to a time-division multiplexed system. these devices are available in 28-pin plccs. the t7504 is also available in a 44-pin mqfp. the t5504 differs from the t7504 in its timing mode. the t5504 operates in the nondelay timing mode (digital data valid when frame sync goes high), and the t7504 operates in the delayed timing mode (digital data is valid one clock cycle after frame sync goes high) (see figures 69). figure 1. block diagram for 28-pin dip and 28-pin plcc 5-3579 (f).d gs x 0 vf x in0 vf r op0 gs x 1 vf x in1 vf r o1 C + filter encoder channel 0 2.4 v decoder pcm powerdown internal timing bias channel 1 d x d r psx0 mclk vf r on0 gnda (4) (plcc only) network interface control and control circuitry and reference v dd (2) filter network psx1 psx2 psx3 psep gndd asel v dd (2) (mqfp only) gnda (5) (mqfp only) channel 2 channel 3 gs x 3 vf x in3 vf r o3 gs x 2 vf x in2 vf r o2
2 2 agere systems inc. data sheet february 2002 t7504 and t5504 quad pcm codecs with filters functional description four channels of pcm data input and output are passed through only two ports, d x and d r , so some type of time-slot assignment is necessary. the scheme used here is to utilize timing modes of 32 or 64 time slots corresponding to master clock frequencies of either 2.048 mhz or 4.096 mhz, respectively. each device has four transmit frame sync (fs x ) inputs, one for each channel. during a single 125 s frame, each transmit frame sync input is supplied a single pulse. the timing of the pulse indicates the beginning of the time slot during which the data for that channel is clocked out of the device. during a frame, transmit frame sync pulses must be separated from each other by one or more time slots. a channel is placed in a standby (low-power) mode if its fs x input has been low for 500 s. there is a single frame sync separation input (fsep). the number of negative clock edges minus one that occurs while fsep is high is the delay (in clock periods) that is placed between the rising edge of a transmit frame sign bit and the falling edge used by the receiver to sample the sign bit. there must always be a pulse on the fsep input since this input provides the 8 khz signal required to maintain internal timing. if the fsep pulse is one clock period or less, the device makes the transmit edges and receive sampling edges one half clock period apart. the entire device is placed in a powerdown mode if fsep remains low for 500 s. time slot zero is defined as starting on the first rising mclk edge after fsep = 1 is detected by a negative mclk edge. in the t7504, mclk negative-going edges that detect the start of fsep and fs x n must be integer multiples of eight mclk periods apart (zero multiples are allowed). since fsep is assumed to define time slot 0, the number of multiples separating fs x n and fsep is the time-slot number. in the t5504, fs x n for time slot 0 nominally starts on the mclk positive edge following the negative edge which detects fsep. the frequency of the master clock must be either 2.048 mhz or 4.096 mhz. internal circuitry determines the master clock frequency during the powerup reset interval. powerdown is not guaranteed if mclk is lost unless the device is already in the powerdown mode due to fsep low for at least 500 s. the analog input section in figure 2 includes an on- chip op amp that is used in conjunction with external, user-supplied resistors to vary encoder passband gain. the feedback resistance (r f ) should range from 10 k? to 200 k? and capacitance from gsx to ground should be kept to less than 50 pf. the input signal at vf x in should be ac coupled. for best performance, the maxi- mum gain of this op amp should be limited to 20 db or less. figure 2. typical analog input section vf x in to 2.4 v gs x r i r f C + codec filters gain = r x r i 5-3786 (f)
agere systems inc. 3 data sheet february 2002 t7504 and t5504 quad pcm codecs with filters pin information figure 3. 28-pin plcc pin diagram figure 4. 44-pin mqfp pin diagram fsx0 v dd gnda0 vfxin0 gsx0 vf r o0 asel vfxin2 gsx2 vf r o2 5 6 7 8 9 10 11 4212827 3 12 14 15 16 17 18 13 25 24 23 22 21 20 19 fsep gnda3 vf r o3 vf r o1 gsx1 vfxin3 gsx3 vfxin1 t-7504 - - - ml v dd mclk gnda2 gnda1 fsx2 fsx3 gndd dx d r 26 fsx1 t-5504 - - - ml 5-3580 (f).b 5-4770 (f) fsx0 nc v dd v dd a nc nc 44 42 41 40 39 43 33 32 31 30 29 28 27 gndd t-7504 - - - ml gnda0 nc nc nc dx d r 38 nc 37 36 35 fsep fsx2 fsx3 34 fsx1 vfxin0 gsx0 vf r o0 26 25 24 23 gnda1 mclk asel v dd v dd a nc nc 1 2 3 4 5 6 7 nc vfxin2 gsx2 vf r o2 8 9 10 11 gnda2 22 20 19 18 17 21 vfxin1 nc gnda4 gsx1 vf r o1 nc 16 gnda3 15 14 13 vfxin3 vf r o3 gsx3 12 nc
4 agere systems inc. data sheet february 2002 t7504 and t5504 quad pcm codecs with filters pin information (continued) * i d indicates a pull-down device is included on this lead. table 1. pin descriptions symbol pin type * name/function plcc mqfp vf x in3 vf x in2 vf x in1 vf x in0 14 8 16 22 15 8 19 26 i voice frequency transmitter input. analog inverting input to the uncommitted operational amplifier at the transmit filter input. connect the signal to be digitized to this pin through a resistor r i (see figure 2 ). gs x 3 gs x 2 gs x 1 gs x 0 13 9 17 21 14 9 20 25 o gain set for transmitter. output of the transmit uncommitted operational amplifier. the pin is the input to the transmit differential filters. connect the pin to its corresponding vf x in through a resistor r f (see figure 2 ). vf r o3 vf r o2 vf r o1 vf r o0 12 10 18 20 13 10 21 24 o voice frequency receiver output. this pin can drive 2000 ? (or greater) loads. v dd [1:0] v dda [1:0] 7, 24 3, 31 4, 30 5 v digital and analog power supplies . all pins must be connected on the circuit board. each pin should be bypassed to ground with at least 0.1 f of capacitance as close to the device as possible. for the dip and plcc packages, v dd serves both analog and digital internal circuits. gnda4 gnda3 gnda2 gnda1 gnda0 15 11 19 23 18 16 11 23 27 analog grounds . all ground pins must be connected on the circuit board. d r 4 44 i receive pcm data input . the data on this pin is shifted into the device on the fall- ing edges of mclk. data is only entered for valid time slots as defined by the rela- tionship of the pulses on the fs x inputs and the pulse on the fsep input. d x 3 43 o transmit pcm data output . this pin remains in the high-impedance state except during active transmit time slots. an active transmit time slot is defined as one in which a pulse is present on one of the fsx inputs. data is shifted out on the rising edge of mclk. mclk 5 1 i master clock input . the frequency must be 2.048 mhz or 4.096 mhz. this clock serves as the bit clock for all pcm data transfer. a 40% to 60% duty cycle is re- quired. gndd 2 41 digital ground . ground connection for the digital circuitry. all ground pins must be connected on the circuit board. fs x 3 fs x 2 fs x 1 fs x 0 28 27 26 25 36 35 34 33 i d transmit frame sync . this signal is an edge trigger and must be high for a min- imum of one mclk cycle. this signal must be derived from mclk. the division ra- tio is 1:256 or 1:512 (fs x :mclk). each fs x input must have a pulse present at the start of the desired active output time slot. pulses on the various fs x inputs must be separated by one or more integer multiples of time slots. an internal pull-down device is included on each fs x . asel 6 2 i d a-law/-law select . a logic low selects -law coding. a logic high selects a-law coding. a pull-down device is included. fsep 1 37 i frame sync separation . the pulse width of this 8 khz signal defines the timing offset between the transmit and receive frames. internally generated receive frame sync pulses are delayed from the corresponding transmit frame sync pulse rising edge by one less than the fsep pulse width in negative mclk edges. if the pulse width is one mclk period or less, the transmit and receive frame syncs are made coincident. loss of fsep causes the device to powerdown. if the master clock fre- quency is 2.048 mhz or 4.096 mhz, delays of 255 or 511 clock pulses are not al- lowed, respectively. timing relationships between fsep, fs x n, and time slot 0 are given in figures 69 .
agere systems inc. 5 data sheet february 2002 t7504 and t5504 quad pcm codecs with filters absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are absolute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. handling precautions although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (esd) during handling and mounting. agere employs a human-body model (hbm) and a charged-device model (cdm) for esd susceptibility testing and protection design evaluation. esd voltage thresholds are dependent on the circuit parameters used to define the model. no industry-wide standard has been adopted for cdm. however, a standard hbm (resistance = 1500 ?, capacitance = 100 pf) is widely used and, therefore, can be used for comparison purposes. the hbm esd threshold presented here was obtained by using these circuit parameters: electrical characteristics specifications apply for t a = C40 c to +85 c, v dd = 5 v 5%, mclk = either 2.048 mhz or 4.096 mhz, and gnd = 0 v, unless otherwise noted. dc characteristics table 2. digital interface parameter symbol min max unit storage temperature range t stg C55 150 c power supply voltage v dd 6.5 v voltage on any pin with respect to ground C0.5 0.5 + v dd v maximum power dissipation (package limit) p d 600 mw hbm esd threshold voltage device rating t7504 >2000 v t5504 >2000 v parameter symbol test conditions min typ max unit input low voltage v il all digital inputs 0.8 v input high voltage v ih all digital inputs 2.0 v output low voltage v ol d x , i l = 3.2 ma 0.4 v output high voltage v oh d x , i l = C3.2 ma 2.4 v d x , i l = C320 a 3.5 v input current, pins without pull-down i i any digital input gnd < v in < v dd C10 10 a input current, pins with pull-down i i any digital input gnd < v in < v dd 150 a output current in high-impedance state i oz d x C30 30 a input capacitance c i 5 pf
6 agere systems inc. data sheet february 2002 t7504 and t5504 quad pcm codecs with filters electrical characteristics (continued) table 3. power dissipation power measurements are made at mclk = 4.096 mhz, outputs unloaded. transmission characteristics table 4. analog interface parameter symbol test conditions min typ max unit powerdown current i dd0 mclk present, fs x [3:0] = 0.4 v, fsep = 0.4 v 0.2 1 ma powerup current i dd1 mclk, fs x [3:0], fsep present 30 40 ma standby current i dds mclk, fsep present; fs x [3:0] = 0.4 v 6 10 ma parameter symbol test conditions min typ max unit input resistance, vf x in r vfxi 0.25 v < vfxi < 4.75 v 1.0 m? input leakage current, vf x in i bvfxi 0.25 v < vfxi < 4.75 v 2.4 a dc open-loop voltage gain, gs x a vol 5000 open-loop unity gain bandwidth, gs x f o 1 3 mhz load capacitance, gs x cl x1 50 pf load resistance, gs x rl x1 10 k? input voltage, vf x in v ix relative to ground 2.25 2.35 2.5 v load resistance, vf r o rl vf r o 2000 ? load capacitance, vf r o cl vf r o 100 pf output resistance, vf r o ro vf r o 0 dbm0, 1020 hz pcm code applied to d r 20 ? partial powerdown fs x = 0 for channel under test 3000 10000 ? output voltage, vf r o vo r alternating zero -law pcm code applied to d r 2.25 2.35 2.5 v output voltage, vf r o, standby vo rpd fs x [3:0] = 0.4 v, fsep = active, no load 2.15 2.4 2.65 v output leakage current, vf r o, pow- erdown io vf r o fsep = 0.4 v C30 30 a output voltage swing, vf r o v swr rl = 2000 ? 3.2 vp-p
agere systems inc. 7 data sheet february 2002 t7504 and t5504 quad pcm codecs with filters transmission characteristics (continued) ac transmission characteristics unless otherwise noted, the analog input is a 0 dbm0, 1020 hz sine wave; the input amplifier is set for unity gain. the digital input is a pcm bit stream equivalent to that obtained by passing a 0 dbm0, 1020 hz sine wave through an ideal encoder. the output level is sin(x)/x-corrected. table 5. absolute gain table 6. gain tracking table 7. distortion parameter symbol test conditions min typ max unit encoder milliwatt response (transmit gain toler- ance) emw signal input of 0.775 vrms, -law or a-law C0.25 0.25 dbm0 decoder milliwatt response (receive gain toler- ance) dmw measured relative to 0.775 vrms, -law or a-law, pcm input of 0 dbm0 1020 hz rl = 10 k? C0.25 0.25 dbm0 parameter symbol test conditions min typ max unit transmit gain tracking error sinusoidal input -law/a-law gt x +3 dbm0 to C37 dbm0 C37 dbm0 to C50 dbm0 C0.25 C0.50 0.25 0.50 db db receive gain tracking error sinusoidal input -law/a-law gt r +3 dbm0 to C37 dbm0 C37 dbm0 to C50 dbm0 C0.25 C0.50 0.25 0.50 db db parameter symbol test conditions min typ max unit transmit signal to distortion sd x -law 3 dbm0 vf x i C30 dbm0 a-law 3 dbm0 vf x i C30 dbm0 36 35 db db -law C30 dbm0 vf x i C40 dbm0 a-law C30 dbm0 vf x i C40 dbm0 30 29 db db -law C40 dbm0 vfxi C45 dbm0 a-law C40 dbm0 vfxi C45 dbm0 25 25 db db receive signal to distortion sd r -law 3 dbm0 vf r o C30 dbm0 a-law 3 dbm0 vf r o C30 dbm0 36 35 db db -law C30 dbm0 vf r o C40 dbm0 a-law C30 dbm0 vf r o C40 dbm0 30 29 db db -law C40 dbm0 vf r o C45 dbm0 a-law C40 dbm0 vf r o C45 dbm0 25 25 db db single frequency distortion, transmit sfd x 200 hz3400 hz, 0 dbm0 input, output any other single frequency 3400 hz C38 dbm0 single frequency distortion, receive sfd r 200 hz3400 hz, 0 dbm0 input, output any other single frequency 3400 hz C40 dbm0 intermodulation distortion imd transmit or receive, two frequencies in the range (300 hz3400 hz) at C6 dbm0 C42 dbm0
8 agere systems inc. data sheet february 2002 t7504 and t5504 quad pcm codecs with filters transmission characteristics (continued) table 8. envelope delay distortion * varies as a function of time slots chosen. overload compression figure 5 shows the region of operation for encoder signal levels above the reference input power (0 dbm0). figure 5. overload compression parameter symbol test conditions min typ max unit t x delay, absolute* d xa f = 1600 hz 175 to 425 s t x delay, relative to 1600 hz d xr f = 500 hz600 hz f = 600 hz800 hz f = 800 hz1000 hz f = 1000 hz1600 hz f = 1600 hz2600 hz f = 2600 hz2800 hz f = 2800 hz3000 hz 220 145 75 40 75 105 155 s s s s s s s r x delay, absolute* d ra f = 1600 hz 150 to 405 s r x delay, relative to 1600 hz d rr f = 500 hz1000 hz f = 1000 hz1600 hz f = 1600 hz2600 hz f = 2600 hz2800 hz f = 2800 hz3000 hz C40 C30 90 125 175 s s s s s round trip delay, absolute* d rta any time slot/channel to any time slot/channel f = 1600 hz 325 to 650 s 1 2 3 4 5 6 7 8 9 123456789 acceptable region fundamental input power (dbm) fundamental output power (dbm) 5-3586 (f)
agere systems inc. 9 data sheet february 2002 t7504 and t5504 quad pcm codecs with filters transmission characteristics (continued) table 9. noise table 10. receive gain relative to gain at 1.02 khz table 11. transmit gain relative to gain at 1.02 khz parameter symbol test conditions min typ max unit transmit noise -law n xc 18 dbrnc0 input amplifier gain = 20 db 19 dbrnc0 transmit noise a-law n xp C68 dbm0p receive noise -law n rc pcm code is alternating positive and negative zero 13 dbrnc0 receive noise a-law n rp pcm code is a-law positive one C75 dbm0p noise, single frequency f = 0 khz100 khz n rs vf x in = 0 vrms, measurement at vf r o, d r = d x C53 dbm0 power supply rejection transmit psr x v dd = 5.0 vdc + 100 mvrms: f = 0 khz4 khz f = 4 khz50 khz 36 30 db db power supply rejection receive psr x pcm code is positive one lsb v dd = 5.0 vdc + 100 mvrms: f = 0 khz4 khz f = 4 khz25 khz f = 25 khz50 khz 36 40 30 db db db spurious out-of-band signals at vf r o relative to input sos 0 dbm0, 300 hz3400 hz input pcm code applied: 4600 hz7600 hz 7600 hz8400 hz 8400 hz50 khz C30 C40 C30 db db db frequency (hz) min typ max unit below 3000 C0.150 0.04 0.150 db 3140 C0.570 0.04 0.150 db 3380 C0.885 C0.58 0.010 db 3860 C10.7 C9.4 db 4600 and above C28 db frequency (hz) min typ max unit 16.67 C50 C30 db 40 C34 C26 db 50 C36 C30 db 60 C50 C30 db 200 C1.8 C0.5 0 db 300 to 3000 C0.150 0.04 0.150 db 3140 C0.570 0.04 0.150 db 3380 C0.885 C0.58 0.010 db 3860 C10.7 C9.4 db 4600 and above C32 db
10 agere systems inc. data sheet february 2002 t7504 and t5504 quad pcm codecs with filters transmission characteristics (continued) table 12. interchannel crosstalk (between channels) r f = 200 k? (see note below.) table 13. intrachannel crosstalk (within channels) r f = 200 k? (see note below.) note: for tables 11 and 12, crosstalk into the transmit channels (vf x in) can be significantly affected by parasitic capacitive feeds from gs x and vf r o outputs. pwb layouts should be arranged to keep these parasitics low. the resistor value of r f (from gs x to vf x in) should also be kept as low as possible (while maintaining the load on gs x above 10 k? per table 4) to minimize crosstalk. parameter symbol test conditions min typ max unit transmit to receive crosstalk 0 dbm0 transmit levels ct xx-ry f = 300 hz3400 hz idle pcm code for channel under test; 0 dbm0 into any other single channel vf x in C95 C75 db receive to transmit crosstalk 0 dbm0 receive levels ct rx-xy f = 300 hz3400 hz vf x in = 0 vrms for channel under test; 0 dbm0 code level on any other single channel d r C92 C75 db transmit to trans- mit crosstalk 0 dbm0 transmit levels ct xx-xy f = 300 hz3400 hz 0 dbm0 applied to any single channel vf x in except channel under test, which has vf x in = 0 vrms C90 C75 db receive to receive crosstalk 0 dbm0 receive levels ct rx-ry f = 300 hz3400 hz 0 dbm0 code level on any single channel d r except channel under test, which has idle code applied C95 C75 db parameter symbol test conditions min typ max unit transmit to receive crosstalk 0 dbm0 transmit levels ct xx-rx f = 300 hz3400 hz idle pcm code for channel under test; 0 dbm0 into vf x in C95 C65 db receive to transmit crosstalk 0 dbm0 receive levels ct rx-xx f = 300 hz3400 hz vf x in = 0 vrms for channel under test; 0 dbm0 code level on d r C73 C65 db
agere systems inc. 11 data sheet february 2002 t7504 and t5504 quad pcm codecs with filters timing characteristics table 14. clock section (see figures 6, 7, 8, and 9.) table 15. t7504 transmit section (see figure 6.) * timing parameter tmcldz is referenced to a high-impedance state. table 16. t5504 transmit section (see figure 8.) * timing parameter tmchdz is referenced to a high-impedance state. symbol parameter test conditions min typ max unit tmchmcl1 clock pulse width 97 ns tcdc duty cycle, mc 40 60 % tmch1mch2 tmcl2mcl1 clock rise and fall time 0 15 ns symbol parameter test conditions min typ max unit tmchdv data enabled on ts entry 0 < c load < 100 pf 0 60 ns tmchdv1 data delay from mc 0 < c load < 100 pf 0 60 ns tmcldz* data float on ts exit c load = 0 15 100 ns tfshmcl frame-sync hold time 50 ns tmclfsh frame-sync high setup 50 ns tfslmcl frame-sync low setup 50 ns tfshfsl frame-sync pulse width 0.1 125 C tmchmch s symbol parameter test conditions min typ max unit tfshdv data enabled on ts entry 0 < c load < 100 pf 0 80 ns tmchdv1 data delay from fs x 0 < c load < 100 pf 0 60 ns tmchdz* data float on ts exit c load = 0 0 30 ns tfshmcl frame-sync hold time 50 ns tmclfsh frame-sync high setup 50 ns tfslmcl frame-sync low setup 50 ns tfshfsl frame-sync pulse width 0.1 125 C tmchmch s
12 agere systems inc. data sheet february 2002 t7504 and t5504 quad pcm codecs with filters timing characteristics (continued) table 17. t7504 and t5504 receive section (see figures 6, 7, 8, and 9.) figure 6. t7504 transmit and receive timing, fsep = 1 mclk figure 7. t7504 receive timing, fsep > 1 mclk symbol parameter test conditions min typ max unit tdvmcl receive data setup 30 ns tmcldv receive data hold 15 ns tsphmcl frame separation hold time 50 ns tmclsph frame separation high setup 50 ns tsplmcl frame separation low setup 50 ns 5-3581 (c) 5-3582 (c)
agere systems inc. 13 data sheet february 2002 t7504 and t5504 quad pcm codecs with filters timing characteristics (continued) figure 8. t5504 transmit and receive timing, fsep = 1 mclk figure 9. t5504 receive timing, fsep > 1 mclk 5-3581 (c).a 5-3582 (c).a
14 agere systems inc. data sheet february 2002 t7504 and t5504 quad pcm codecs with filters timing characteristics (continued) figure 10. typical frame sync timing (2 mhz operation) applications figure 11. typical t7504 and t5504/slic interconnection 5-3583 (c).a 5-3584 (f) slic t7504 t5504 vf r on acin vf x inn v tr gs x n zhb zt1 zrcv zt2 0.1 f 0.1 f rf rg
agere systems inc. 15 data sheet february 2002 t7504 and t5504 quad pcm codecs with filters outline diagrams 28-pin plcc controlling dimensions are in inches. 1.27 typ 0.330/0.533 0.10 seating plane 0.51 min typ 4.572 max 12 18 11 5 4126 25 19 12.446 0.127 pin #1 identifier zone 11.506 0.076 11.506 0.076 12.446 0.127 5-2608 (f).r5
16 agere systems inc. data sheet february 2002 t7504 and t5504 quad pcm codecs with filters outline diagrams (continued) 44-pin mqfp controlling dimensions are in inches. 44 1 10.00 0.20 13.20 0.20 10.00 0.20 13.20 0.20 pin #1 identifier zone 11 12 22 23 33 34 0.80 typ detail a 2.35 max 0.10 seating plane 1.95/2.10 detail b 0.25 max 0.30/0.45 0.20 m 0.130/0.230 detail b 0.25 0.73/1.03 1.60 ref gage plane seating plane detail a 5-2111 (f).r12
agere systems inc. 17 data sheet february 2002 t7504 and t5504 quad pcm codecs with filters ordering information device code package temperature timing mode comcode t - 7504 - - - ml 28-pin, plcc C40 c to +85 c delayed 107203184 t - 7504 - - - jl-db 44-pin, mqfp dry pack tray C40 c to +85 c delayed 107740466 t - 7504 - - - ml-tr 28-pin, plcc tape and reel C40 c to +85 c delayed 107231680 t - 5504 - - - ml 28-pin, plcc C40 c to +85 c nondelayed 107364044 t - 5504 - - - ml-tr 28-pin, plcc tape and reel C40 c to +85 c nondelayed 107364051
agere systems inc. reserves the right to make changes to the product(s) or information contained herein without notice. no liab ility is assumed as a result of their use or application. copyright ? 2002 agere systems inc. all rights reserved februar y 2002 ds02-149alc (replaces ds99-201alc) for additional information, contact y our a g ere s y stems account mana g er or the followin g : internet: http://www.agere.com e-mail: docmaster@agere.com n. america: a g ere s y stems inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18109-3286 1-800-372-2447 , fax 610-712-4106 ( in canada: 1-800-553-2448 , fax 610-712-4106 ) asia: a g ere s y stems hon g kon g ltd., suites 3201 & 3210-12, 32/f, tower 2, the gatewa y , harbour cit y , kowloon tel. (852) 3129-2000 , fax ( 852 ) 3129-2020 china: (86) 21-5047-1212 ( shan g hai ) , (86) 10-6522-5566 ( bei j in g) , (86) 755-695-7224 ( shenzhen ) japan: (81) 3-5421-1600 ( to k y o ) , korea: (82) 2-767-1850 ( seoul ) , singapore: (65) 778-8833 , taiwan: (886) 2-2725-5858 ( taipei ) europe: tel. (44) 7000 624624 , fax ( 44 ) 1344 488 045

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