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zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 1 of 34 member of the family applications ? low voltage, high density systems with intermediate bus architectures (iba) ? point-of-load regulators for high performance dsp, fpga, asic, and microprocessor applications ? desktops, servers, and portable computing ? broadband, networking, optical, and communications systems ? active memory bus terminators benefits ? integrates digital power conversion with intelligent power management ? eliminates the need for external power management components ? completely programmable via industry-standard i 2 c communication bus ? one part that covers all applications ? reduces board space, system cost and complexity, and time to market features ? rohs lead free and lead-solder-exempt products are available ? wide input voltage range: 3v?13.2v ? high continuous output current: 15a ? wide programmable output voltage range: 0.5v?5.5v ? active digital current share ? single-wire serial communication bus for frequency synchronization, programming, and monitoring ? optimal voltage positioning with programmable slope of the vi line ? overcurrent, overvoltage, undervoltage, and overtemperature protections with programmable thresholds and types ? programmable fixed switch ing frequency 0.5-1.0mhz ? programmable turn-on and turn-off delays ? programmable turn-on and turn-off voltage slew rates with tracking protection ? programmable feedback loop compensation ? power good signal with programmable limits ? programmable fault management ? start up into the load pre-biased up to 100% ? full rated current sink ? real time voltage, current, and temperature measurements, monitoring, and reporting ? small footprint smt package: 8x32mm ? low profile of 14mm ? compatible with conventional pick-and-place equipment ? wide operating temperature range ? ul60950 recognized, csa c22.2 no. 60950-00 certified, and tuv en60950-1:2001 certified description power-one?s point-of-load converters are recommended for use with regulated bus converters in an intermediate bus architecture (iba). the zy7115 is an intelligent, fully programmable step-dow n point-of-load dc-dc module integrating digital power c onversion and intelligent powe r management. when used wi th zm7000 series digital power managers, the zy7115 completely eliminates the n eed for external components for sequencing, tracking, protection, monitoring, and reporting. all parameters of the zy7115 are programmable via the industry-standard i 2 c communication bus and can be changed by a user at any time during product development and service.
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 2 of 34 reference documents: ? zm7xxx digital power manager. data sheet ? zm7xxx digital power manager. programming manual ? z-one ? graphical user interface ? zm00056-kit usb to i 2 c adapter kit. user manual 1. ordering information zy 71 15 x y ? zz product family: z-one module series: intelligent pol converter output current: 15a output voltage setpoint accuracy: l ? 1.2% or 20mv, whichever is greater. h 1 ? 1.0% or 10mv, whichever is greater rohs compliance: no suffix - rohs compliant with pb solder exemption 2 g - rohs compliant for all six substances dash packaging option 3 : t1 ? 500pcs t&r t2 ? 100pcs t&r t3 ? 50pcs t&r q1 ? 1pc sample for evaluation only ______________________________________ 1 contact factory for availability. 2 the solder exemption refers to all the restricted materials exc ept lead in solder. these materials are cadmium (cd), hexavalen t chromium (cr6+), mercury (hg), polybrominated biphenyls (pbb), polybromi nated diphenylethers (pbde), and lead (pb) used anywhere except in solder. 3 packaging option is used only for orde ring and not included in the part number printed on the pol converter label. 4 the evaluation board is available in onl y one configuration: zm7300-kit-hks. example: zy7115hg-t2 : a 100-piece reel of rohs compliant pol c onverters with the output voltage setpoint of 1.0% or 10mv, whichever is greater. each pol converter is labeled zy7115hg. 2. absolute maximum ratings stresses in excess of the absolute maximum ratings ma y cause performance degradation, adversely affect long- term reliability, and cause permanent damage to the converter. parameter conditions/description min max units operating temperature controller case temperature -40 105 ? c input voltage 250ms transient 15 vdc output current (see output current derating curves) -15 15 adc 3. environmental and mechanical specifications parameter conditions/description min nom max units ambient temperature range -40 85 ? c storage temperature (ts) -55 125 ? c weight 15 grams mtbf calculated per telcordia technologies sr-332 4.82 mhrs peak reflow temperature zy7115 zy7115g 245 220 260 ? c ? c lead plating zy7115 and zy7115g 100% matte tin or 1.5m ag over 1.5m ni moisture sensitivity level zy7115 zy7115g 2 3
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 3 of 34 4. electrical specifications specifications apply at the input voltage from 3v to 13.2v, output load from 0 to 15a, ambient temperature from -40c to 85c, 100 ? f output capacitance, and defau lt performance parameters settings unless otherwise noted. 4.1 input specifications parameter conditions/description min nom max units input voltage (v in ) at v in <4.75v, vldo pin needs to be connected to an external voltage source higher than 4.75v 3 13.2 vdc input current (at no load) v in ? 4.75v, vldo pin connected to vin 50 madc undervoltage lockout (vldo connected to vin) ramping up ramping down 4.2 3.75 vdc vdc undervoltage lockout (vldo connected to v aux =5v) ramping up ramping down 3.0 2.5 vdc vdc external low voltage supply connect to vldo pin when v in <4.75v 4.75 13.2 vdc vldo input current current drawn from the external low voltage supply at v ldo =5v 50 madc 4.2 output specifications parameter conditions/description min nom max units output voltage range (v out ) programmable 1 default (no programming) 0.5 0.5 5.5 vdc vdc output voltage setpoint accuracy v in =12v, i out =0.5*i out max , f sw =500khz, room temperature (see ordering information) output current (i out ) v in min to v in max -15 2 15 adc line regulation v in min to v in max 0.3 %v out load regulation 0 to i out max 0.2 %v out dynamic regulation peak deviation settling time slew rate 2.5a/ ? ? f, f sw =1mhz to 10% of peak deviation 100 50 mv ? s output voltage peak-to-peak ripple and noise bw=20mhz full load v in =5.0v, v out =0.5v, f sw =500khz v in =13.2v, v out =0.5v, f sw =500khz v in =5.0v, v out =2.5v, f sw =500khz v in =13.2v, v out =2.5v, f sw =500khz v in =13.2v, v out =5.0v, f sw =500khz 10 15 10 25 35 mv mv mv mv mv mv temperature coefficient v in =12v, i out =0.5*i out max 20 ppm/c switching frequency default programmable, 250khz steps 500 500 1,000 khz khz duty cycle limit default programmable, 1.56% steps 0 90.5 95 % % 1 zy7115 is a step-down converter, thus the output voltage is always lower than the input voltage as show in figure 1. 2 at the negative output current (bus termi nator mode) efficiency of the zy7115 degrades resulting in increased internal power d issipation. therefore maximum allowable negative current under specific cond itions is 20% lower than the current determined from the derati ng curves shown in paragraph 5.5.
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 4 of 34 figure 1. output voltage as a function of input voltage and output current 4.3 protection specifications parameter conditions/description min nom max units output overcurrent protection type default programmable non-latching, 130ms period latching/non-latching threshold default programmable in 11 steps 60 170 170 %i out %i out threshold accuracy -25 25 %i ocp.set output overvoltage protection type default programmable non-latching, 130ms period latching/non-latching threshold default programmable in 10% steps 110 1 130 130 %v o.set %v o.set threshold accuracy measured at v o.set =2.5v -2 2 %v ovp.set delay from instant when threshold is exceeded until the turn-off command is generated 6 s
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 5 of 34 output undervoltage protection type default programmable non-latching, 130ms period latching/non-latching threshold default programmable in 5% steps 75 75 85 %v o.set %v o.set threshold accuracy measured at v o.set =2.5v -2 2 %v uvp.set delay from instant when threshold is exceeded until the turn-off command is generated 6 s overtemperature protection type default programmable non-latching, 130ms period latching/non-latching turn off threshold temperature is increasing 130 ? c turn on threshold temperature is decreasing after the module was shut down by otp 120 ? c threshold accuracy -5 5 ? c delay from instant when threshold is exceeded until the turn-off command is generated 6 s tracking protection (when enabled) type default programmable disabled latching/non-latching, 130ms period threshold enabled during output voltage ramping up ? 250 mvdc threshold accuracy -50 50 mvdc delay from instant when threshold is exceeded until the turn-off command is generated 6 s overtemperature warning threshold always enabled, report ed in status register 120 ? c threshold accuracy -5 5 ? c hysteresis 3 ? c delay from instant when threshold is exceeded until the warning signal is generated 6 s power good signal (pgood pin) logic v out is inside the pg window v out is outside the pg window high low n/a lower threshold default programmable in 5% steps 90 90 95 %v o.set %v o.set upper threshold 110 %v o.set delay from instant when threshold is exceeded until status of pg signal changes 6 s threshold accuracy measured at v o.set =2.5v -2 2 %v o.set ___________________ 1 minimum ovp threshold is 1.0v
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 6 of 34 4.4 feature specifications parameter conditions/description min nom max units current share type active, single line maximum number of modules connected in parallel i out min 20%*i out nom 10 maximum number of modules connected in parallel i out min =0 4 current share accuracy i out min 20%*i out nom 20 %i out interleave interleave (phase shift) default programmable in 11.25 ? steps 0 0 348.75 degree degree sequencing turn on delay default programmable in 1ms steps 0 0 255 ms ms turn off delay default programmable in 1ms steps 0 0 63 ms ms tracking turn on slew rate default programmable in 7 steps 0.1 0.1 8.33 1 v/ms v/ms turn off slew rate default programmable in 7 steps -0.1 -0.1 -8.33 1 v/ms v/ms optimal voltage positioning load regulation default programmable in 7 steps 0 0 6.27 mv/a mv/a feedback loop compensation zero1 (effects phase lead and increases gain in mid-band) programmable 0.05 50 khz zero 2 (effects phase lead and increases gain in mid-band) programmable 0.05 50 khz pole 1 (integrato r pole, effects loop gain) programmable 0.05 50 khz pole 2 (effects phase lag and limits gain in mid-band) programmable 1 1000 khz pole 3 (high frequency low- pass filter to limit pwm noise) programmable 1 1000 khz monitoring voltage monitoring accuracy 1 lsb=22mv -2%v out ? 1 lsb 2%v out + 1 lsb mv current monitoring accuracy 20%*i out nom < i out < i out nom -20 +20 %i out temperature monitoring accuracy junction temperature of pol controller -5 +5 ? c remote voltage sense (+vs and ?vs pins) voltage drop compensation between +vs and vout 300 mv voltage drop compensation between -vs and pgnd 100 mv ___________________ 1 achieving fast slew rates under specific line and load conditions may require feedback loop adjustment
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 7 of 34 4.5 signal specifications parameter conditions/description min nom max units vdd internal supply voltage 3.15 3.3 3.45 v sync/data line (sd pin) vil_sd low level input voltage -0.5 0.3 x vdd v vih_sd high level input voltage 0.75 x vdd vdd + 0.5 v vhyst_sd hysteresis of input schmitt trigger 0.25 x vdd 0.45 x vdd v vol low level sink current @ 0.5v 14 60 ma tr_sd maximum allowed rise time 10/90%vdd 300 ns cnode_sd added node capacitance 5 10 pf ipu_sd pull-up current source at vsd=0v 0.3 1.0 ma freq_sd clock frequency of external sd line 475 525 khz tsynq sync pulse duration 22 28 % of clock cycle t0 data=0 pulse duration 72 78 % of clock cycle inputs: addr0?addr4, en, im vil_x low level input voltage -0.5 0.3 x vdd v vih_x high level input voltage 0.7 x vdd vdd+0.5 v vhyst_x hysteresis of input schmitt trigger 0.1 x vdd 0.3 x vdd v rdnl_addr external pull down resistance addrx forced low 10 kohm power good and ok inputs/outputs iup_pg pull-up current source input forced low pg 25 110 a iup_ok pull-up current source input forced low ok 175 725 a vil_x low level input voltage -0.5 0.3 x vdd v vih_x high level input voltage 0.7 x vdd vdd+0.5 v vhyst_x hysteresis of input schmitt trigger 0.1 x vdd 0.3 x vdd v iol low level sink current at 0.5v 4 20 ma current share bus (cs pin) iup_cs pull-up current source at vcs = 0v 0.84 3.1 ma vil_cs low level input voltage -0.5 0.3 x vdd v vih_cs high level input voltage 0.75 x vdd vdd+0.5 v vhyst_cs hysteresis of input schmitt trigger 0.25 x vdd 0.45 x vdd v iol low level sink current at 0.5v 14 60 ma tr_cs maximum allowed rise time 10/90% vdd 100 ns
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 8 of 34 5. typical performance characteristics 5.1 efficiency curves 70 75 80 85 90 95 0 1.5 3 4.5 6 7.5 9 10.5 12 13.5 15 output current, a efficiency, % vout=0.5v vout=1.2v vout=2.5v figure 2. efficiency vs. load. vin=3.3v, fsw=500khz 70 75 80 85 90 95 100 01.534.567.5910.51213.515 output current, a efficiency, % vout=0.5v vout=1.2v vout=2.5v vout=3.3v figure 3. efficiency vs. load. vin=5v, fsw=500khz 50 55 60 65 70 75 80 85 90 95 01.534.567.5910.51213.515 output current, a efficiency, % vout=0.5v vout=1.2v vout=2.5v vout=3.3v vout=5.0v figure 4. efficiency vs. load. vin=12v, fsw=500khz 65 70 75 80 85 90 95 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 output voltage, v efficiency, % vin=3.3v vin=5v vin=12v figure 5. efficiency vs. output voltage, iout=15a, fsw=500khz
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 9 of 34 65 70 75 80 85 90 95 3456789101112 input voltage, v efficiency, % vout=0.5v vout=1.2v vout=2.5v vout=3.3v figure 6. efficiency vs. input voltage. iout=15a, fsw=500khz 88 89 90 91 92 93 94 95 01.534.567.5910.51213.515 output current, a efficiency 500khz 750khz 1mhz figure 7. efficiency vs. load. vin=3.3v, vout=2.5v 76 78 80 82 84 86 88 90 0 1.5 3 4.5 6 7.5 9 10.5 12 13.5 15 output current, a efficiency 500khz 750khz 1mhz figure 8. efficiency vs. load. vin=5v, vout=1.2v 83 85 87 89 91 93 95 0 1.5 3 4.5 6 7.5 9 10.5 12 13.5 15 output current, a efficiency 500khz 750khz 1mhz figure 9. efficiency vs. load. vin=12v, vout=5v
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 10 of 34 80 82 84 86 88 90 92 94 500 750 1000 switching frequency, khz efficiency 3.3vin/2.5vout 5vin/1.2vout 12vin/5vout figure 10. efficiency vs. switching frequency. iout=15a 5.2 turn-on characteristics figure 11. tracking turn-on. rising slew rate is programmed at 0.5v/ms. vin=12v, ch1 ? v1, ch2 ? v2, ch3 ? v3 figure 12. turn-on with different rising slew rates. rising slew rates are programmed as follows: v1- 1v/ms, v2-0.5v/ms, v3-0.2v/ms. vin=12v, ch1 ? v1, ch2 ? v2, ch3 ? v3 figure 13. sequenced turn-on. rising slew rate is programmed at 1v/ms. v2 delay is 2ms, v3 delay is 4ms. vin=12v, ch1 ? v1, ch2 ? v2, ch3 ? v3
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 11 of 34 figure 14. turn on with sequencing and tracking. rising slew rate programmed at 0.2v/ms, v1 and v3 delays are programmed at 20ms. vin=12v, ch1 ? v1, ch2 ? v2, ch3 ? v3 figure 15. turn on into prebiased load. v3 is prebiased by v2 via a diode. vin=12v, ch1 ? v1, ch2 ? v2, ch3 ? v3 5.3 turn-off characteristics figure 16. tracking turn-off. falling slew rate is programmed at 0.5v/ms. vin=12v, ch1 ? v1, ch2 ? v2, ch3 ? v3 figure 17. turn-off with tracking and sequencing. falling slew rate is programmed at 0.5v/ms. vin=12v, ch1 ? v1, ch2 ? v2, ch3 ? v3
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 12 of 34 5.4 transient response the pictures below show the deviation of the output voltage in response to the 50-100-50% step load at 2.5a/ s. in all tests the pol converters were operating at 1mhz and had 6x47 f ceramic capacitors connected across the output pins. bandwidth of the feedback loop was programmed for faster transient response. figure 18. vin=12v, vout=1v. bandwidth is 40khz figure 19. vin=12v, vout=5v. bandwidth is 40khz figure 20. vin=5v, vout=1v. bandwidth is 40khz figure 21. vin=5v, vout=2.5v. bandwidth is 40khz figure 22. vin=3v, vout=1v. bandwidth is 30khz
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 13 of 34 5.5 thermal derating curves 5 6 7 8 9 10 11 12 13 14 15 45 50 55 60 65 70 75 80 85 temperature, 'c output current, a nc 100 lfm 200 lfm 400 lfm 600 lfm figure 23. thermal derating curves. vin=13.2v, vout=2.5v, fsw=500khz 5 6 7 8 9 10 11 12 13 14 15 45 50 55 60 65 70 75 80 85 temperature, 'c output current, a 0 lfm 100 lfm 200 lfm 400 lfm 600 lfm figure 24. thermal derating curves. vin=13.2v, vout=5v, fsw=500khz
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 14 of 34 5 6 7 8 9 10 11 12 13 14 15 45 50 55 60 65 70 75 80 85 temperature, 'c output current, a 0 lfm 100 lfm 200 lfm 400 lfm 600 lfm figure 25. thermal derating curves. vin=13.2v, vout=5v, fsw=1,000khz 6. typical application zy7115 v1 v2 v3 cs sd ok_a ok_b addr addr addr addr dpm i 2 c intermediate voltage bus zy7115 zy7115 zy7115 ok_c figure 26. block diagram of typical multiple output application with digital power manager and i 2 c interface the block diagram of a typical applicatio n of zy7115 point-of-load converters (pol) is shown in figure 26. the system includes multiple pols and a zm7000 series digita l power manager (dpm). all pols are connected to the dpm and to each other via a single-wire sd (sync/data) line. the line provides synchronization of all pols to the master clock generated by the dpm and simultaneously performs bidirectional data transfer between pols and the dpm. each pol has a unique 5-bit address pr ogrammed by grounding respective address pins. to enable the current share, cs pins of pols connected in parallel are linked together. there are three groups of pols in the application, group s a, b, and group c. a group is defined as a number of pols interconnected via ok pins. grouping of pols en ables users to program, control, and monitor multiple pols simultaneously and execute advanced fault management schemes.
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 15 of 34 the complete schematic of the application is shown in figure 27. figure 27. complete schematic of the application shown in figure 26. intermediate bus voltage is from 4.75v to 13.2v.
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 16 of 34 7. pin assignments and description pin name pin number pin type buffer type pin description notes vldo 1 p low voltage dropout connect to an external voltage source higher than 4.75v, if v in <4.75v. connect to v in , if v in 4.75v im 2 not used leave floating nc 3 not used leave floating nc 4 not used leave floating nc 5 not used leave floating nc 6 not used leave floating nc 7 not used leave floating nc 8 not used leave floating vref 9 not used leave floating en 10 connect to pgnd connect to pgnd ok 11 i/o pu fault/status condition connect to ok pin of other z-pol and/or dpm. leave floating, if not used sd 12 i/o pu sync/data line connect to sd pin of dpm pgood 13 i/o pu power good trim 14 not used leave floating cs 15 i/o pu current share connect to cs pin of other z-pols connected in parallel addr4 16 i pu pol address bit 4 tie to pgnd for 0 or leave floating for 1 addr3 17 i pu pol address bit 3 tie to pgnd for 0 or leave floating for 1 addr2 18 i pu pol address bit 2 tie to pgnd for 0 or leave floating for 1 addr1 19 i pu pol address bit 1 tie to pgnd for 0 or leave floating for 1 addr0 20 i pu pol address bit 0 tie to pgnd for 0 or leave floating for 1 -vs 21 i pu negative voltage sense connect to the negative point close to the load +vs 22 i pu positive voltage sense connec t to the positive point close to the load vout 23 p output voltage pgnd 24 p power ground vin 25 p input voltage legend: i=input, o=output, i/o=input/output, p=power, a=analog, pu=internal pull-up
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 17 of 34 8. programmable features performance parameters of zy7115 pol converters can be programmed via the industry standard i 2 c communication bus without replacing any components or rewiring pcb traces. each parameter has a default value stored in the volatile memory registers detailed in table 1. the setup registers 00h through 14h are programmed at the system power-up. when the user programs new performance parameters, the values in the registers are overwritten. upon removal of the input voltage, the default values are restored. table 1. zy7115 memory registers register content address pc1 protection configuration 1 00h pc2 protection configuration 2 01h pc3 protection configuration 3 02h don turn-on delay 05h dof turn-off delay 06h tc tracking configuration 03h int interleave configuration and frequency selection 04h run run register 15h st status register 16h vos output voltage setpoint 07h cls current limit setpoint 08h dcl duty cycle limit 09h b1 dig controller denominator z - 1 coefficient 0ah b2 dig controller denominator z - 2 coefficient 0bh b3 dig controller denominator z - 3 coefficient 0ch c0l dig controller numerator z 0 coefficient, low byte 0dh c0h dig controller numerator z 0 coefficient, high byte 0eh c1l dig controller numerator z - 1 coefficient, low byte 0fh c1h dig controller numerator z - 1 coefficient, high byte 10h c2l dig controller numerator z - 2 coefficient, low byte 11h c2h dig controller numerator z - 2 coefficient, high byte 12h c3l dig controller numerator z - 3 coefficient, high byte 13h c3h dig controller numerator z - 3 coefficient, low byte 14h vom output voltage monitoring 17h iom output current monitoring 18h tmp temperature monitoring 19h zy7115 converters can be programmed using the graphical user interface or directly via the i 2 c bus by using high and low level commands as described in the ??dpm programming manual?. zy7115 parameters can be reprogrammed at any time during the system operation and service except for the digital filter coefficients, the switching frequency and the duty cycle limit, that can only be changed when the pol is turned off. 8.1 output voltage the output voltage can be programmed in the gui output configuration window shown in the figure 28 or directly via the i 2 c bus by writing into the vos register shown in figure 29. figure 28. output configuration window vos7 vos6 vos5 vos4 vos2 vos1 vos0 bit 7 bit 0 r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bit 7:0 v os[7:0] , output voltage setting 00h: corresponds to 0.5000v 01h: corresponds to 0.5125v ? 77h: corresponds to 1.9875v 78h: corresponds to 2.0000v 79h: corresponds to 2.025v ? f9h: corresponds to 5.225v fah: corresponds to 5.250v fbh: corresponds to 5.300v ? ffh: corresponds to 5.500v vos3 figure 29. output voltage setpoint register vos
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 18 of 34 8.1.1 output voltage setpoint the output voltage programmi ng range is from 0.5v to 5.5v. within this range, there are 256 predefined voltage setpoints. to improve resolution of the output voltage settings, the voltage range is divided into three sub-ranges as shown in table 2. table 2. output voltage adjustment resolution v out min , v v out max , v resolution, mv 0.500 2.000 12.5 2.025 5.25 25 5.3 5.5 50 8.1.2 output voltage margining if the output voltage needs to be varied by a certain percentage, the margining function can be utilized. the margining can be programmed in the gui output configuration windo w or directly via the i 2 c bus using high level commands as described in the ??dpm programming manual?. in order to properly margin pols that are connected in parallel, the pols must be members of one of the parallel buses. refer to the gui system configuration window shown in figure 56. 8.1.3 optimal voltage positioning optimal voltage positioning increases the voltage regulation window by properly positioning the output voltage setpoint. positioning is determined by the load regulation that can be programmed in the gui output configuration wind ow shown in figure 28 or directly via the i 2 c bus by writing into the cls register shown in figure 39. figure 30 illustrates optimal voltage positioning concept. if no load regulation is programmed, the headroom (voltage differential between the output voltage setpoint and a regulation limit) is approximately half of the voltage regulation window. when load regulation is programmed, the output voltage will decrease as the output current increases, so the vi c haracteristic will have a negative slope. therefore, by properly selecting the operating point, it is possible to increase the headroom as shown in the picture. upper regulation limit lower regulation limit light load v out i out v i curve without load regulation v i curve with load regulation heavy load headroom without load regulation operating point headroom with load regulation figure 30. concept of optimal voltage positioning increased headroom allows tolerating larger voltage deviations. for example, the step load change from light to heavy load will cause the output voltage to drop. if the optimal voltage positioning is utilized, the output voltage will stay within the regulation window. otherwise, the output voltage will drop below the lower regulation limit. to compensate for the voltage drop external output capacitance will need to be added, thus increasing cost and complexity of the system. the effect of optimal voltage positioning is shown in figure 31 and figure 32. in this case, switching output load causes large peak-to-peak deviation of the output voltage. by programming load regulation, the peak to peak deviation is dramatically reduced. figure 31. transient response without optimal voltage positioning
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 19 of 34 figure 32. transient response with optimal voltage positioning 8.2 sequencing and tracking turn-on delay, turn-off delay, and rising and falling output voltage slew rates can be programmed in the gui sequencing/tracking window shown in figure 33 or directly via the i 2 c bus by writing into the don, dof, and tc registers, respectively. the registers are shown in figure 34, figure 35, and figure 37. figure 33. sequencing/tracking window 8.2.1 turn-on delay turn-on delay is defined as an interval from the application of the turn-on command until the output voltage starts ramping up. don7 don6 don5 don4 don2 don1 don0 bit 7 bit 0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bit 7:0 don[7:0] : turn-on delay time 00h: corresponds to 0ms delay after turn-on command has occurred ? ffh: corresponds to 255ms delay after turn-on command has occurred don3 figure 34. turn-on delay register don 8.2.2 turn-off delay --- --- dof5 dof4 dof2 dof1 dof0 bit 7 bit 0 u u r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bit 7:6 unimplemented , read as ?0? bit 5:0 dof[5:0] : turn-off delay time 00h: corresponds to 0ms delay after turn-off command has occurred ? 3fh: corresponds to 63ms delay after turn-off command has occurred dof3 figure 35. turn-off delay register dof turn-off delay is defined as an interval from the application of the turn-off command until the output voltage reaches zero (if the falling slew rate is programmed) or until both high side and low side switches are turned off (if the slew rate is not programmed). therefore, for the slew rate controlled turn-off the ramp-down time is included in the turn-off delay as shown in figure 36. turn-off command internal ramp-down command v out user programmed turn-off delay, t df calculated delay t d time ramp-down time, t f falling slew rate dv f /dt figure 36. relationship between turn-off delay and falling slew rate as it can be seen from the figure, the internally calculated delay t d is determined by the equation below. dt dv v t t f out df d ? ? , for proper operation t d shall be greater than zero. the appropriate value of the turn-off delay needs to be programmed to satisfy the condition.
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 20 of 34 if the falling slew rate contro l is not utilized, the turn- off delay only determines an interval from the application of the turn-off command until both high side and low side switches are turned off. in this case, the output voltage ramp-down process is determined by load parameters. 8.2.3 rising and falling slew rates the output voltage tracking is accomplished by programming the rising and falling slew rates of the output voltage. to achieve programmed slew rates, the output voltage is being changed in 12.5mv steps where duration of each step determines the slew rate. for example, ramping up a 1.0v output with a slew rate of 0.5v/ms will require 80 step s duration of 25 s each. duration of each voltage step is calculated by dividing the master clock frequency generated by the dpm. since all pols in the system are synchronized to the master clock, the matching of voltage slew rates of different outputs is very accurate as it can be seen in figure 11 and figure 16. during the turn on process, a pol not only delivers current required by the load (i load ), but also charges the load capacitance. the charging current can be determined from the equation below: dt dv c i r load chg ? ? where, c load is load capacitance, dv r /dt is rising voltage slew rate, and i chg is charging current. when selecting the rising slew rate, a user needs to ensure that ocp chg load i i i ? ? where i ocp is the overcurrent protection threshold of the zy7115. if the condition is not met, then the overcurrent protection will be triggered during the turn-on process. to avoid this, dv r /dt and the overcurrent protection threshold should be programmed to meet the condition above. figure 37. tracking configuration register tc 8.3 protections zy7115 series converters have a comprehensive set of programmable protections. the set includes the output over- and undervoltage protections, overcurrent protection, overtemperature protection, tracking protection, overtemperature warning, and power good signal. status of protections is stored in the st register shown in figure 38. figure 38. protection status register st thresholds of overcurrent , over- and undervoltage protections, and power good limits can be programmed in the gui output configuration window or directly via the i 2 c bus by writing into the cls and pc2 registers shown in figure 39 and figure 40. --- r2 r1 r0 f2 f1 f0 bit 7 bit 0 r = readable bi t w = writable bit u = unimplemented bit, read as ?0? -n = value at por rese t u r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 bit 7 unimplemented , read as ?0? bit 6:4 r[2:0] : value of vo rising slope 0: corresponds to 0.1v/ms (default) 1: corresponds to 0.2v/ms 2: corresponds to 0.5v/ms 3: corresponds to 1.0v/ms 4: corresponds to 2.0v/ms 5: corresponds to 5.0v/ms 6: corresponds to 8.3v/ms 7: corresponds to 8.3v/ms bit 3 sc , slew rate control at turn-of f 0: slew rate control is disabled 1: slew rate control is enabled bit 2:0 f[2:0] : value of vo falling slope 0: corresponds to -0.1v/ms (default) 1: corresponds to -0.2v/ms 2: corresponds to -0.5v/ms 3: corresponds to -1.0v/ms 4: corresponds to -2.0v/ms 5: corresponds to -5.0v/ms 6: corresponds to ?8.3v/ms 7: corresponds to ?8.3v/ms sc tp pg tr ot uv ov pv bit 7 bit 0 r= readable bit w = writable bit u= unimplemented bit, read as ?0? -n = value at por rese t r-1 r-0 r-1 r-1 r-1 r-1 r-1 r-1 bit 7 tp : temperature warning bit 6 pg : power good warning bit 5 tr : tracking fault bit 4 ot : overtemperature fault bit 3 oc : overcurrent fault bit 2 uv : undervoltage fault bit 1 o v : overvoltage error bit 0 p v : phase voltage erro r note: - an activated warning/fault/error is encoded as ?0? oc
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 21 of 34 lr2 lr1 lr0 tce cls2 cls1 cls0 bit 7 bit 0 r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset r/w-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-1 r/w-1 r/w-1 bit 7:5 lr[2:0] , load regulation configuration 000: 0 v/a/ohm 001: 0.39 v/a/ohm 010: 0.78 v/a/ohm 011: 1.18 v/a/ohm 100: 1.57 v/a/ohm 101: 1.96 v/a/ohm 110: 2.35 v/a/ohm 111: 2.75 v/a/ohm bit 4 tce , temperature compensation enable 0: disabled 1: enabled bit 3:0 cls[3:0] , current limit setting 0h: corresponds to 37% 1h: corresponds to 47% ? bh: corresponds to 140% values higher than bh are translated to bh (140%) cls3 figure 39. current limit setpoint register cls --- --- --- pgll ovpl0 uvpl1 uvpl0 bit 7 bit 0 r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset u u u r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 bit 7:5 unimplemented , read as ?0? bit 4 pgll : set power good low level 1 = 95% of vo 0 = 90% of vo (default) bit 3:2 ovpl[1:0] : set over voltage protection level 00 = 110% of vo 01 = 120% of vo 10 = 130% of vo (default) 11 = 130% of vo bit 1:0 uvpl[1:0] : set under voltage protection level 00 = 75% of vo (default) 01 = 80% of vo 10 = 85% of vo ovpl1 figure 40. protection configuration register pc2 note that the overvoltage and undervoltage protection thresholds and power good limits are defined as percentages of the output voltage. therefore, the absolute levels of the thresholds change when the output voltage setpoint is changed either by output voltage adjustment or by margining. in addition, a user can change type of protections (latching or non-latching) or disable certain protections. these settings are programmed in the gui fault management window shown in figure 41 or directly via the i 2 c by writing into the pc1 register shown in figure 42. figure 41. fault management window figure 42. protection configuration register pc1 if the non-latching protection is selected, a pol will attempt to restart every 130ms until the condition that triggered the protection is removed. when restarting, the output voltages follow tracking and sequencing settings. if the latching type is selected, a pol will turn off and stay off. the pol can be turned on after 130ms, if the condition that caused the fault is removed and the respective bit in the st register was cleared, or the turn on command was recycled, or the input voltage was recycled. tre pve trp otp uvp ovp pvp bit 7 bit 0 r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por rese t r/w-0 r/w-1 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 r/w-0 bit 7 tre : tracking fault enable 1 = enabled 0 = disabled bit 6 pve : phase voltage error enable 1 = enabled 0 = disabled bit 5 trp : tracking fault protection 1 = latching 0 = non latching bit 4 otp : overtemperature protection configuration 1 = latching 0 = non latching bit 3 ocp : overcurrent protection configuration 1 = latching 0 = non latching bit 2 uvp : undervoltage protection configuration 1 = latching 0 = non latching bit 1 ovp : overvoltage protection configuration 1 = latching 0 = non latching bit 0 pvp : phase voltage protection 1 = latching 0 = non latching ocp
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 22 of 34 all protections can be classified into three groups based on their effect on sy stem operation: warnings, faults, and errors. 8.3.1 warnings this group includes overtemperature warning and power good signal. the warnings do not turn off pols but rather generate signals that can be transmitted to a host controller via the i 2 c bus. 8.3.1.1 overtemperature warning the overtemperature warning is generated when temperature of the contro ller exceeds 120c. the overtemperature warning changes the pt bit of the status register st to 0 and sends the signal to the dpm. reporting is enabled in the gui fault management window or directly via the i 2 c by writing into the pc3 register shown in figure 44. when the temperature falls below 117c, the pt bit is cleared and the overtemperature warning is removed. 8.3.1.2 power good power good is an open collector output that is pulled low, if the output voltage is outside of the power good window. the window is formed by the power good high threshold that is equal to 110% of the output voltage and the power good low threshold that can be programmed at 90 or 95% of the output voltage. the power good protection is only enabled after the output voltage reaches its steady state level. the pgood pin is pulled low during transitions of the output voltage from one level to other as shown in figure 43. the power good warning pulls the power good pin low and changes the pg bit of the status register st to 0. it sends the signal to the dpm, if the reporting is enabled. when the output voltage returns within the power good window, the pg pin is pulled high, the pg bit is cleared and the power good warning is removed. the power good pin can also be pulled low by an external circuit to initiate the power good warning. note : to retrieve status information, status monitoring in the gui pol group configuration window should be enabled (refer to digital power manager data sheet). the dpm will retrieve the status information from each pol on a continuous basis. 8.3.2 faults this group includes overcurrent, overtemperature, undervoltage, and tracking protections. triggering any protection in this gr oup will turn off the pol. 8.3.2.1 overcurrent protection overcurrent protection is active whenever the output voltage of the pol exceeds the prebias voltage (if any). when the output current reaches the oc threshold, the output voltage will start decreasing. as soon as the output voltage decreases below the undervoltage protection threshold, the oc fault signal is generated, the pol turns off and the oc bit in the register st is changed to 0. both high side and low side switches of the pol are turned off instantly (fast turn-off). the temperature compensation is added to keep the oc threshold approximately constant at temperatures above room te mperature. note that the temperature compensation can be disabled in the gui output configurati on window or directly via the i 2 c by writing into the cls register. however, it is recommended to keep the temperature compensation enabled. 8.3.2.2 undervoltage protection the undervoltage protection is only active during steady state operation of the pol to prevent nuisance tripping. if the output voltage decreases below the uv threshold and there is no oc fault, the uv fault signal is genera ted, the pol turns off, and the uv bit in the register st is changed to 0. the output voltage is ramped down according to sequencing and tracking settings (regular turn-off). 8.3.2.3 overtemperature protection overtemperature protection is active whenever the pol is powered up. if temperature of the controller exceeds 130c, the ot fault is generated, pol turns off, and the ot bit in the regi ster st is changed to 0. the output voltage is ramped down according to sequencing and tracking settings (regular turn-off). if non-latching otp is programmed, the pol will restart as soon as the temperature of the controller decreases below the overtemperature warning threshold of 120c.
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 23 of 34 8.3.2.4 tracking protection tracking protection is active only when the output voltage is ramping up. the purpose of the protection is to ensure that the voltage differential between multiple rails being tracked does not exceed 250mv. this protection eliminates the need for external clamping diodes between different voltage rails which are frequently recommended by asic manufacturers. when the tracking protection is enabled, the pol continuously compares actual value of the output voltage to its programmed value as defined by the output voltage and its rising slew rate. if absolute value of the difference exceeds 250mv, the tracking fault signal is generated, the pol turns off, and the tr bit in the register st is changed to 0. both high side and low side switches of the pol are turned off instantly (fast turn-off). the tracking protection can be disabled, if it contradicts requirements of a particular system (for example turning into high capacitive load where rising slew rate is not important). it can be disabled in the gui fault management window or directly via the i 2 c bus by writing into the pc1 register. figure 43. protections enable conditions 8.3.3 errors the group includes overvoltage protection and the phase voltage error. the phase voltage error is not available in zy7115. 8.3.3.1 overvoltage protection the overvoltage protection is active whenever the output voltage of the pol exceeds the pre-bias voltage (if any). if the output voltage exceeds the overvoltage protection threshold, the overvoltage error signal is generated, the pol turns off, and the ov bit in the register st is changed to 0. the high side switch is turned off instantly, and simultaneously the low side switch is turned on to ensure reliable protection of sensitive loads. the low side switch provides low impedance path to quickly dissipate energy stored in the ou tput filter and achieve effective voltage limitation. the ov threshold can be programmed from 110% to 130% of the output voltage setpoint, but not lower than 1.0v. 8.3.4 faults and errors propagation the feature adds flexibility to the fault management scheme by giving users cont rol over propagation of fault signals within and outside of the system. the propagation means that a fault in one pol can be programmed to turn off other pols and devices in the system, even if they are not directly affected by the fault. 8.3.4.1 grouping of pols z-series pols can be arranged in several groups to simplify fault management. a group of pols is defined as a number of pols with interconnected ok pins. a group can include from 1 to 32 pols. if ovp threshold out p ut volta g e time v o 1.0 v enable command 0 1 ocp enabled 0 1 prebiased output otp continuousl y enabled ovp threshold ovp threshold uvp threshold uvp threshold uvp threshold pg low threshold pg low threshold pg low threshold pg high=110%v out pg high=110%v out pg high=110%v out out p ut volta g e out p ut volta g e power good signal 1 0 tracking thresholds
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 24 of 34 fault propagation within a group is desired, the propagation bit needs to be checked in the gui fault management window. the parameters can also be programmed directly via the i 2 c bus by writing into the pc3 register shown in figure 44. when propagation is enabled, the faulty pol pulls its ok pin low. a low ok line initiates turn-off of other pols in the group. figure 44. protection configuration register pc3 in addition, the ok lines can be connected to the dpm to facilitate propagation of faults and errors between groups. one dpm can control up to 4 independent groups. to enable fault propagation between groups, the respective bit needs to be checked in the gui fault and error propagation window shown in figure 45. figure 45. fault and error propagation window in this case low ok line will signal dpm to pull other ok lines low to initiate shutdown of other pols as programmed in the gui fault and error propagation window. if an error is propagated, the dpm can also generate commands to turn off a front end (a dc-dc converter generating the intermediate bus voltage) and trigger an optional crowbar protection to accelerate removal of the ibv voltage. 8.3.4.2 propagation process propagation of a fault (ocp, uvp, otp, and trp) initiates regular turn-off of other pols. the faulty pol in this case performs either the regular or the fast turn-off depending on a specific fault as described in section 8.3.2. propagation of an error initiates fast turn-off of other pols. the faulty pol performs the fast turn-off and turns on its low side switch. example of the fault propagation is shown in figure 46 - figure 47. in this three-output system (refer to the block diagram in figure 26), the pol powering the output v3 (ch 1 in t he picture) encounters the undervoltage fault after the turn-on. when the fault propagation is not enabled, the pol turns off and generates the uv fault signal. because the uv fault triggers the regular turn off, the pol meets its turn- off delay and falling slew rate settings during the turn-ff process as shown in figure 46. since the uv fault is programmed to be non-latching, the pol will attempt to restart every 130ms, repeating the process described above until the condition causing the undervoltage is removed. if the fault propagation between groups is enabled, the pol powering the output v3 pulls its ok line low and the dpm propagates the signal to the pol powering the output v1 that belongs to other group. ptm pgm trp otp uvp ovp pvp bit 7 bit 0 r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por rese t r/w-0 r/w-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 bit 7 ptm : temperature warning message 1 = enabled 0 = disabled bit 6 pgm : power good message 1 = enabled 0 = disabled bit 5 trp : tracking fault propagation 1 = enabled 0 = disabled bit 4 otp : overtemperature fault propagation 1 = enabled 0 = disabled bit 3 ocp : overcurrent fault propagation 1 = enabled 0 = disabled bit 2 uvp : undervoltage fault propagation 1 = enabled 0 = disabled bit 1 ovp : overvoltage error propagation 1 = enabled 0 = disabled bit 0 pvp : phase voltage error propagation 1 = enabled 0 = disabled ocp
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 25 of 34 the pol powering the output v1 (ch3 in the picture) executes the regular turn -off. since both v1 and v3 have the same delay and slew rate settings they will continue to turn off and on synchronously every 130ms as shown in figure 47 until the condition causing the undervoltage is removed. the pol powering the output v2 continues to ramp up until it reaches its steady state level. 130ms is the interval from the instant of time when the output voltage ramps down to zero until the output voltage starts to ramp up again. therefore, the 130ms hiccup interval is guaranteed regardless of the turn-off delay setting. figure 46. turn-on into uvp on v3. the uv fault is programmed to be non-latching. ch1 ? v3 (group c), ch2 ? v2, ch3 ? v1 (group a) figure 47. turn-on into uvp on v3. the uv fault is programmed to be non-latching and propagate from group c to group a. ch1 ? v3 (group c), ch2 ? v2, ch3 ? v1 (group a) summary of protections, their parameters and features are shown in table 3 table 3. summary of protections parameters and features code name type when active turn off low side switch propagation disable pt temperature warning warning whenever v in is applied no n/a sends signal to dpm no pg power good warning during steady state no n/a sends signal to dpm no tr tracking fault during ramp up fast off regular turn off yes ot overtemperature fault whenever v in is applied regular off regular turn off no oc overcurrent fault when v out exceeds prebias fast off regular turn off no uv undervoltage fault during steady state regular off regular turn off no ov overvoltage error when v out exceeds prebias fast on fast turn off no
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 26 of 34 8.4 pwm parameters z-series pols utilize the digital pwm controller. the controller enables users to program most of the pwm performance parameter s, such as switching frequency, interleave, duty cycle, and feedback loop compensation. 8.4.1 switching frequency the switching frequency can be programmed in the gui pwm controller window shown in figure 48 or directly via the i 2 c bus by writing into the int register shown in figure 49. note that the content of the register can be changed only when the pol is turned off. switching actions of all pols connected to the sd line are synchronized to the master clock generated by the dpm. each pol is equipped with a pll and a frequency divider so they can operate at multiples (including fractional) of the master clock frequency as programmed by a user. the pol converters can operate at 500 khz, 750 khz, and 1 mhz. although synchronized, switching frequencies of different pols are independent of each other. it is permissible to mix pols operating at different frequencies in one system. it allows optimizing efficiency and transient response of each pol in the system individually. figure 48. pwm controller window figure 49. interleave configuration register int 8.4.2 interleave interleave is defined as a phase delay between the synchronizing slope of the master clock on the sd pin and pwm signal of a pol. the interleave can be programmed in the gui pwm controller window or directly via the i 2 c bus by writing into the int register. every pol generates switching noise. if no interleave is programmed, all pols in the system switch simultaneously and noise reflected to the input source from all pols is added together as shown in figure 50. figure 50. input voltage noise, no interleave frq2 frq1 frq0 int4 int2 int1 int0 bit 7 bit 0 r= readable bit w = writable bit u= unimplemented bit, read as ?0? -n = value at por rese t r/w-0 r/w-0 r/w-0 r/w-0 1) r/w-0 1) r/w-0 1) r/w-0 1) r/w-0 1) bit 7:5 frq[2:0] : pwm frequency selection 000: 500khz 001: 750khz 010: 1000lhz 011: 1250khz 100: 1250khz 101: 1500khz 110: 1750khz 111: 2000khz bit 4:0 int[4:0] : interleave position 00h: ton starts with 0.0 phase lag to sd line 01h: ton starts wi th 11.25 phase lag to sd line 02h: ton starts with 22.50 phase lag to sd line ? 1fh: ton starts with 348.75 phase lag to sd line 1) initial value depends on the state of the interleave mode ( im ) input: im=open: a t por reset the 5 corresponding address bits are loaded im=low: a t por reset a 0 is loaded int3
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 27 of 34 figure 51 shows the input voltage noise of the three- output system with programmed interleave. instead of all three pols switching at the same time as in the previous example, the pols v1, v2, and v3 switch at 67.5, 180, and 303.75, respectively. noise is spread evenly across the switching cycle resulting in more than 1.5 times reduction. to achieve similar noise reduction without the interleave will require the addition of an external lc filter. figure 51. input voltage noise with interleave similar noise reduction can be achieved on the output of pols connected in parallel. figure 52 and figure 53 show the output noise of two zy7115s connected in parallel without and with 180 interleave, respectively. resulting noise reduction is more than 2 times and is equivalent to doubling switching frequency or adding extra capacitance on the output of the pols. figure 52. output voltage noise, full load, no interleave figure 53. output voltage noise, full load, 180 ? interleave the zy7115 interleave feature is similar to that of multiphase converters, however, unlike in the case of multiphase converters, interleave does not have to be equal to 360/n, where n is the number of pols in a system. zy7115 interleave is independent of the number of pols in a system and is fully programmable in 11.25 ? steps. it allows maximum output noise reduction by intelligently spreading switching energy. note : due to noise sensitivity issues that may occur in limited cases, it is recommended to avoid phase lag settings of 112.5 and 123.75 degrees, otherwise false pg and/or ov indications may occur. 8.4.3 duty cycle limit the zy7115 is a step-down converter therefore v out is always less than v in . the relationship between the two parameters is characterized by the duty cycle and can be estimated from the following equation: min in out v v dc . ? , where, dc is the duty cycle, v out is the required maximum output voltage (including margining), v in.min is the minimum input voltage. it is good practice to limit the maximum duty cycle of the pwm controller to a somewhat higher value compared to the steady-state duty cycle as expressed by the above equation. this will further protect the output from excessive voltages. the duty cycle limit can be programmed in the gui pwm
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 28 of 34 controller window or directly via the i 2 c bus by writing into the dcl register shown in figure 54. dcl5 dcl4 dcl3 dcl2 dcl0 hi lo bit 7 bit 0 r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 bit 7:2 dcl[5:0] , duty cycle limitation 00h: 0 01h: 1/64 ? 3fh: 63/64 bit 1: hi , adc high saturation feed-forward 0: disabled 1: enabled bit 0: lo , adc low saturation feed-forward 0: disabled 1: enabled dcl1 figure 54. duty cycle limit register 8.4.4 adc saturation feedforward to speed up the pwm response in case of heavy dynamic loads, the duty cycl e can be forced either to 0 or the duty cycle limit depending on the polarity of the transient. this function is equivalent to having two comparators defining a window around the output voltage setpoint. when an error signal is inside the window, it will produce gradual duty cycle change proportional to the error signal. if the error signal goes outside the window (usually due to large output current steps), the duty cycle will change to its limit in one switching cycle. in most cases this will significantly improve transient response of the controller, reducing amount of required external capacitance. under certain circumstances, usually when the maximum duty cycle limit significantly exceeds its nominal value, the adc saturation can lead to the overcompensation of the output error. the phenomenon manifests itself as low frequency oscillations on the output of the pol. it can usually be reduced or eliminated by disabling the adc saturation or limiting the maximum duty cycle to 120- 140% of the calculated value. it is not recommended to use adc saturation for output voltages higher than 2.0v. the adc saturation feedforward can be programmed in the gui pwm controller window or directly via the i 2 c bus by writing into the dcl register. 8.4.5 feedback loop compensation feedback loop compensation can be programmed in the gui pwm controller window by setting frequency of poles and zeros of the transfer function. the transfer function of the pol converter is shown in figure 55. it is a third order function with two zeros and three poles. pole 1 is the integrator pole, pole 2 is used in conjunction with zero 1 and zero 2 to adjust the phase lead and limit the gain increase in mid band. pole 3 is used as a high frequency low- pass filter to limit pwm noise. z1 p1 z2 p2 p3 0.1 1 10 100 1000 freq [khz] magnitude[db] 10 20 30 40 50 0.1 1 10 100 1000 freq [khz] -90 -45 -135 -180 0 +45 phase [] p1: pole 1 p2: pole 3 p3: pole 3 z1: zero 1 z2: zero 2 figure 55. transfer function of pwm positions of poles and zeroes are determined by coefficients of the digital filter. the filter is characterized by four numerator coefficients ( c 0 , c 1 , c 2 , c 3 ) and three denominator coefficients ( b 1 , b 2 , b 3 ). the coefficients are automatically calculated when desired frequency of poles and zeros is entered in the gui pwm controller window. the coefficients are stored in the c0h, c0l, c1h, c1l, c2h, c2l, c3h, c3l, b1, b2, and b3 registers. note : the gui automatically transforms zero and pole frequencies into the digital filter coefficients. it is strongly recommended to use the gui to determine the filter coefficients. programming feedback loop compensation allows optimizing pol performance for various application conditions. for example, increase in bandwidth can significantly improve dynamic response.
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 29 of 34 8.5 current share the pol converters are equipped with the digital current share function. to activate the current share, interconnect the cs pins of the pols connected in parallel. the digital signal transmitted over the cs line sets output currents of all pols to the same level. when pols are connected in parallel, they must be included in the same parallel bus in the gui system configuration window shown in figure 56. in this case, the gui automatically copies parameters of one pol onto all pols connected to the parallel bus. it makes it impossible to configure different performance parameters for pols connected in parallel except for interleave and load regulation settings that are independent. the interleave allows to reduce and move the output noise of the converters connected in parallel to higher frequencies as shown in figure 52 and figure 53. the load regulation allows controlling the current share loop gain in case of small signal oscillations. it is recommended to always add a small amount of load regulation to one of the converters connected in parallel to reduce loop gain and therefore improve stability. 8.6 performance parameters monitoring the pol converters can monitor their own performance parameters such as output voltage, output current, and temperature. the output voltage is measured at the output sense pins, output current is measured using the esr of the output inductor and tem perature is measured by the thermal sensor built into the controller ic. output current readings are adjusted based on temperature readings to compensate for the change of esr of the inductor with temperature. an 8-bit analog to digital converter (adc) converts the output voltage, output current, and temperature into a digital signal to be transmitted via the serial interface. the adc allows a minimum sampling frequency of 1 khz for all three values. monitored parameters are stored in registers (vom, iom, and tmon) that are continuously updated. if the retrieve monitoring bits in the gui group configuration window shown in figure 57 are checked, those registers are being copied into the ring buffer located in the dpm. contents of the ring buffer can be displayed in the gui ibs monitoring window shown in figure 58 or it can be read directly via the i 2 c bus using high and low level commands as described in the ??dpm programming manual?.
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 30 of 34 figure 56. gui system configuration window
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 31 of 34 figure 57. pol group configuration window 9. safety the zy7115 pol converters do not provide isolation from input to output. the input devices powering zy7115 must provide relevant isolation requirements according to all iec60950 based standards. nevertheless, if the system using the converter needs to receive safety agency approval, certain rules must be followed in the design of the system. in particular, all of the creepage and clearance requirements of the end-use safety requirements must be observed. these requirements are included in ul60950 - csa60950- 00 and en60950, although specific applications may have other or additional requirements. the zy7115 pol converters have no internal fuse. if required, the external fuse needs to be provided to protect the converter from catastrophic failure. refer to the ?input fuse selection for dc/dc converters? application note on www.power-one.com for proper selection of the input fuse. both input traces and the
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 32 of 34 chassis ground trace (if applicable) must be capable of conducting a current of 1.5 times the value of the fuse without opening. the fuse must not be placed in the grounded input line. abnormal and component failure tests were conducted with the pol input protected by a fast- acting 65 v, 15 a, fuse. if a fuse rated greater than 15 a is used, additional testing may be required. in order for the output of the zy7115 pol converter to be considered as selv (safety extra low voltage), according to all iec60950 based standards, the input to the pol needs to be supplied by an isolated secondary source providing a selv also. figure 58. ibs monitoring window
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 33 of 34 10. mechanical drawings all dimensions are in mm tolerances: 0.5-10 ? 0.1 10-100 ? 0.2 pin coplanarity: 0.1 max 1.5 10 3.4 0.25 10.25 12 9.75 9.1 12 15.75 8.250.3 3.25 pin 1 3.5 smt pickup center point 1.50.1 0.4 (x20) 27.94 320.3 13.4 140.3 2.03 1.27 (x10) 0.6 2.54 1.27 (x10) 4.3 2.5 0.6 smt pickup tab tilt specification: <5 from vertical, after assembly figure 59. mechanical drawing figure 60. pinout diagram (bottom view)
zy7115 15a dc-dc intellig ent pol data sheet 3v to 13.2v input ? 0.5v to 5.5v output mds-0006 rev. 3.6, 02-jul-10 www.power-one.com page 34 of 34 6 9 8.6 32 10 10 6 0.8 2 (x 22) pin 1 1.27 (x 10) 1.27 (x 10) 2.54 2.03 1.8 1.2 4 (x 3) unexposed thermal copper area associated with each pad must be free from other traces figure 61. recommended pad sizes figure 62. recommended pcb layout for multilayer pcbs notes: 1. nuclear and medical applications - power-one products are not designed, intended for use in, or authorized for use as critic al components in life support systems, equipment used in hazardous envi ronments, or nuclear control systems without the express wr itten consent of the respecti ve divisional president of power-one, inc. 2. technical revisions - the appearance of products, including safety agency certifications pictured on labels, may change depe nding on the date manufactured. specifications are subject to change without notice. i 2 c is a trademark of philips corporation.

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