 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| hd66763 384-channel segment driver with internal ram for 256-color displays rev.1.0 july, 2001 description th e hd 66763, 384-channel segment driver lsi, displays 128rgb-by-176-dot graphics on stn displays in 256 colors. it is for driving stn color lcd displays to a maximum of 128rgb by 176 dots, in combination with the hd66764 common driver. the hd66763?s bit-operation functions, 16- bit high-speed bus interface, and high-speed ram-write functions enable efficient data transfer and high-speed rewriting of data to the graphics ram. th e hd 66763 and hd66764 have various functions for reducing the power consumption of an lcd sy st em . th e hd 66763 has a low-voltage operation (1.8 v min.) and an internal ram to display a ma ximum of 128rgb-by-176-dot color, and the hd66764 has a step-up circuit to generate the lcd- drive voltage, a bleeder resistor for the drive interface with the lcd, and voltage-followers. since the hd 66763 incorporates a circuit that interfaces with the hd66764, it can set instructions for the hd 66764. in add ition, precise power control can be achieved by combining these hardware functions w ith software functi ons, such as a partial display that only requires a low drive-voltage duty, and st a ndby and sleep modes. this lsi is suitable for any medium-sized or small portable battery-driven product requiring long-term driving capabil ities, such as digital cellular phones supporting a www browser, bidirectional pagers, and small pdas. features ? 128rgb x 176-dot graphics display lcd controller/driver for 256 stn colors (when hd66764 is used) ? low-voltage drive and flickerless pwm grayscale drive ? 16-/8-bit high-speed bus interface and serial peripheral interface (spi) ? high-speed burst-ram write function ? writing to a window-ram address area by using a window-address function ? bit-operation functions for graphics processing: ? write-data mask function in bit units ? swap function of upper and lower bytes
hd66763 2 ? logical operation in pixel unit and conditional write function ? various color-display control functions: ? 256 of the 4,096 possible colors can be displayed at the same time (grayscale palette included) ? vertical scroll display function in raster-row units ? low-power operation supports: ? vcc = 1.8 to 3.6 v (low-voltage range) ? vlcd = 2.0 to 4.0 v (liquid crystal drive voltage) ? power-save functions such as the standby mode and sleep mode ? partial lcd drive of two screens in any position ? programmable drive duty ratios (1/16?1/176) and bias values (1/4?1/13) displayed on lcd ? maximum 12-times step-up circuit for liquid crystal drive voltage (hd66764) ? vo ltage followers to decrease direct curren t flow in the lcd dr ive blee der-resistors (hd66764) ? 128-step contrast adjuster (hd66764) ? built-in circuit for interfacing with the hd66764 common driver ? maximum 128rgb-by-176-dot display in combination with the hd66764 common driver ? internal ram capacity: 21,504 bytes ? 384-segment liquid crystal display driver ? n-raster-row ac liquid-crystal drive (c-pattern waveform drive) ? internal oscillation and hardware reset ? shift change of segment driver type number type number external appearance hd66763tb0 bending tcp HCD66763BP au-bump chip 3 hd66763 block diagram index register (ir) vcc osc1 osc2 im2-1, im0/id cs* cl1 flm m dcclk seg1 to seg384 disptmg rs e/wr*/scl r w/rd* db0/sdi, db1/sdo, to db15 ccs* ccl cda reset* test 716 16 16 16 14 16 64 16 16 16 system interface 16 bits 8 bits serial peripheral (spi) common driver interface (serial) segment driver latch circuit gnd vsl vsh grayscale selection circuit latch circuit control register (cr) address counter (ac) bit operation w rite data latch read data latch palette register (rk, gk, bk) pwm grayscale circuit t iming generator cpg graphics ram (gram) 21,504 bytes hd66763 4 hd66763 pad arrangement hd66763 5 rev 1.1 hd66763 osc 2 osc 1 y x vcc vcc vcc g nd g nd g nd e/wr*/ sc l cs * reset gnddum2 v cc dum 1 test seg1 seg2 seg32 seg34 seg33 dummy1 dummy34 dummy3 5 dummy70 - chip size : 17.96mm x 2.38mm - chip thickness : 550um (typ.) - pad coordinates : pad center - coordinate origin : chip center - au bump size (pad number is shown in the bracket) : (1) 80um x 80um dummy1(1) to dummy34(96) dummy35(130), dummy70(483) (2) 42um x 80um seg336(146) to seg351(131) seg34(482) to seg49(467) (3) 80um x 42um seg352(129) to seg384(97) seg1(516) to seg33(484) (4)32um x 80um seg50(466) to seg192(324) dummy36(290) to dummy69(323) seg193(289) to seg335(147) - a u bu m p h e i g ht : 1 5u m ( t yp . ) vcc g nd seg35 seg49 seg48 seg51 seg50 seg336 seg33 7 seg3 51 seg350 seg384 seg383 seg353 seg352 seg33 5 seg334 v s h v s h v s h v s h g nd g nd vcc vcc vsh vsh dummy28 db15 dummy3 im0/id im1 im 2 cl 1 flm m disptm ccs ccl cda rw/rd* r s dummy 2 2 reset dcclk db14 db13 dummy4 db12 db11 dummy5 db10 db 9 dummy6 db8 db7 g nddum1 db6 db5 dummy7 db4 db3 dummy8 db2 db1/ s d o dummy9 db0/sdi dummy1 0 dummy11 g nd g nd g nd g nd g nd dummy 1 2 dummy1 3 dummy1 4 dummy 1 5 dummy 1 6 dummy 1 7 dummy 1 8 dummy 1 9 dummy 2 0 dummy 21 dummy23 dummy24 dummy25 dummy2 6 dummy2 7 dummy33 dummy29 dummy30 dummy3 1 dummy32 seg 193 seg 194 s e g 192 s e g 191 dummy36 dummy37 dummy68 dummy69 dummy2 no.1 no.516 n o.2 no.483 no484 n o.482 no.96 no.97 n o. 95 no.130 no.129 no.131 hd66763 type code (top view) hd66763 6 hd66763 pad coordinate no. pad name x y no. pad name x y no. pad name x y no. pad name x y no. pad name x y 1 dummy1 -8854 -1047 105 seg376 8854 -457 209 seg273 4690 1060 313 dummy59 -310 1060 417 seg99 -5309 1060 2 dummy2 -8620 -1047 106 seg375 8854 -400 210 seg272 4643 1060 314 dummy60 -357 1060 418 seg98 -5357 1060 3 reset -8411 -1047 107 seg374 8854 -343 211 seg271 4595 1060 315 dummy61 -405 1060 419 seg97 -5404 1060 4 dummy3 -8202 -1047 108 seg373 8854 -286 212 seg270 4547 1060 316 dummy62 -452 1060 420 seg96 -5452 1060 5d b15 -7993 -1047 109 seg372 8854 -228 213 seg269 4500 1060 317 dummy63 -500 1060 421 seg95 -5500 1060 6d b14 -7685 -1047 110 seg371 8854 -171 214 seg268 4452 1060 318 dummy64 -548 1060 422 seg94 -5547 1060 7 dummy4 -7476 -1047 111 seg370 8854 -114 215 seg267 4405 1060 319 dummy65 -595 1060 423 seg93 -5595 1060 8d b13 -7267 -1047 112 seg369 8854 -57 216 seg266 4357 1060 320 dummy66 -643 1060 424 seg92 -5643 1060 9d b12 -6959 -1047 113 seg368 8854 0 217 seg265 4309 1060 321 dummy67 -690 1060 425 seg91 -5690 1060 10 dummy5 -6750 -1047 114 seg367 8854 57 218 seg264 4262 1060 322 dummy68 -738 1060 426 seg90 -5738 1060 11 db11 -6541 -1047 115 seg366 8854 114 219 seg263 4214 1060 323 dummy69 -786 1060 427 seg89 -5785 1060 12 db10 -6233 -1047 116 seg365 8854 171 220 seg262 4166 1060 324 seg192 -881 1060 428 seg88 -5833 1060 13 dummy6 -6024 -1047 117 seg364 8854 228 221 seg261 4119 1060 325 seg191 -929 1060 429 seg87 -5881 1060 14 db9 -5815 -1047 118 seg363 8854 286 222 seg260 4071 1060 326 seg190 -976 1060 430 seg86 -5928 1060 15 db8 -5507 -1047 119 seg362 8854 343 223 seg259 4024 1060 327 seg189 -1024 1060 431 seg85 -5976 1060 16 gnddum1 -5298 -1047 120 seg361 8854 400 224 seg258 3976 1060 328 seg188 -1071 1060 432 seg84 -6024 1060 17 db7 -5089 -1047 121 seg360 8854 457 225 seg257 3928 1060 329 seg187 -1119 1060 433 seg83 -6071 1060 18 db6 -4781 -1047 122 seg359 8854 514 226 seg256 3881 1060 330 seg186 -1167 1060 434 seg82 -6119 1060 19 dummy7 -4572 -1047 123 seg358 8854 571 227 seg255 3833 1060 331 seg185 -1214 1060 435 seg81 -6166 1060 20 db5 -4363 -1047 124 seg357 8854 628 228 seg254 3786 1060 332 seg184 -1262 1060 436 seg80 -6214 1060 21 db4 -4055 -1047 125 seg356 8854 685 229 seg253 3738 1060 333 seg183 -1309 1060 437 seg79 -6262 1060 22 dummy8 -3846 -1047 126 seg355 8854 742 230 seg252 3690 1060 334 seg182 -1357 1060 438 seg78 -6309 1060 23 db3 -3637 -1047 127 seg354 8854 800 231 seg251 3643 1060 335 seg181 -1405 1060 439 seg77 -6357 1060 24 db2 -3329 -1047 128 seg353 8854 857 232 seg250 3595 1060 336 seg180 -1452 1060 440 seg76 -6404 1060 25 dummy9 -3120 -1047 129 seg352 8854 914 233 seg249 3547 1060 337 seg179 -1500 1060 441 seg75 -6452 1060 26 db1/sdo -2911 -1047 130 dummy35 8854 1060 234 seg248 3500 1060 338 seg178 -1548 1060 442 seg74 -6500 1060 27 db0/sdi -2603 -1047 131 seg351 8598 1060 235 seg247 3452 1060 339 seg177 -1595 1060 443 seg73 -6547 1060 28 dummy10 -2394 -1047 132 seg350 8538 1060 236 seg246 3405 1060 340 seg176 -1643 1060 444 seg72 -6595 1060 29 rw/rd* -2185 -1047 133 seg349 8478 1060 237 seg245 3357 1060 341 seg175 -1690 1060 445 seg71 -6643 1060 30 e/wr*/scl -1877 -1047 134 seg348 8417 1060 238 seg244 3309 1060 342 seg174 -1738 1060 446 seg70 -6690 1060 31 dummy11 -1668 -1047 135 seg347 8357 1060 239 seg243 3262 1060 343 seg173 -1786 1060 447 seg69 -6738 1060 32 rs -1459 -1047 136 seg346 8297 1060 240 seg242 3214 1060 344 seg172 -1833 1060 448 seg68 -6785 1060 33 cs* -1151 -1047 137 seg345 8237 1060 241 seg241 3167 1060 345 seg171 -1881 1060 449 seg67 -6833 1060 34 gnd -931 -1047 138 seg344 8177 1060 242 seg240 3119 1060 346 seg170 -1928 1060 450 seg66 -6881 1060 35 gnd -831 -1047 139 seg343 8117 1060 243 seg239 3071 1060 347 seg169 -1976 1060 451 seg65 -6928 1060 36 gnd -731 -1047 140 seg342 8057 1060 244 seg238 3024 1060 348 seg168 -2024 1060 452 seg64 -6976 1060 37 gnd -630 -1047 141 seg341 7997 1060 245 seg237 2976 1060 349 seg167 -2071 1060 453 seg63 -7023 1060 38 gnd -530 -1047 142 seg340 7937 1060 246 seg236 2928 1060 350 seg166 -2119 1060 454 seg62 -7071 1060 39 gnd -430 -1047 143 seg339 7877 1060 247 seg235 2881 1060 351 seg165 -2167 1060 455 seg61 -7119 1060 40 gnd -330 -1047 144 seg338 7817 1060 248 seg234 2833 1060 352 seg164 -2214 1060 456 seg60 -7166 1060 41 gnd -230 -1047 145 seg337 7756 1060 249 seg233 2786 1060 353 seg163 -2262 1060 457 seg59 -7214 1060 42 gnd -130 -1047 146 seg336 7696 1060 250 seg232 2738 1060 354 seg162 -2309 1060 458 seg58 -7262 1060 43 gnd -30 -1047 147 seg335 7642 1060 251 seg231 2690 1060 355 seg161 -2357 1060 459 seg57 -7309 1060 44 gnd 70 -1047 148 seg334 7595 1060 252 seg230 2643 1060 356 seg160 -2405 1060 460 seg56 -7357 1060 45 vcc 228 -1047 149 seg333 7547 1060 253 seg229 2595 1060 357 seg159 -2452 1060 461 seg55 -7404 1060 46 vcc 328 -1047 150 seg332 7500 1060 254 seg228 2547 1060 358 seg158 -2500 1060 462 seg54 -7452 1060 47 vcc 428 -1047 151 seg331 7452 1060 255 seg227 2500 1060 359 seg157 -2547 1060 463 seg53 -7500 1060 48 vcc 528 -1047 152 seg330 7404 1060 256 seg226 2452 1060 360 seg156 -2595 1060 464 seg52 -7547 1060 49 vcc 629 -1047 153 seg329 7357 1060 257 seg225 2405 1060 361 seg155 -2643 1060 465 seg51 -7595 1060 50 vcc 729 -1047 154 seg328 7309 1060 258 seg224 2357 1060 362 seg154 -2690 1060 466 seg50 -7642 1060 51 vsh 886 -1047 155 seg327 7262 1060 259 seg223 2309 1060 363 seg153 -2738 1060 467 seg49 -7696 1060 52 vsh 986 -1047 156 seg326 7214 1060 260 seg222 2262 1060 364 seg152 -2786 1060 468 seg48 -7756 1060 53 vsh 1087 -1047 157 seg325 7166 1060 261 seg221 2214 1060 365 seg151 -2833 1060 469 seg47 -7817 1060 54 vsh 1187 -1047 158 seg324 7119 1060 262 seg220 2167 1060 366 seg150 -2881 1060 470 seg46 -7877 1060 55 vsh 1287 -1047 159 seg323 7071 1060 263 seg219 2119 1060 367 seg149 -2928 1060 471 seg45 -7937 1060 56 vsh 1387 -1047 160 seg322 7023 1060 264 seg218 2071 1060 368 seg148 -2976 1060 472 seg44 -7997 1060 57 osc2 1607 -1047 161 seg321 6976 1060 265 seg217 2024 1060 369 seg147 -3024 1060 473 seg43 -8057 1060 58 dummy12 1816 -1047 162 seg320 6928 1060 266 seg216 1976 1060 370 seg146 -3071 1060 474 seg42 -8117 1060 59 osc1 2025 -1047 163 seg319 6881 1060 267 seg215 1928 1060 371 seg145 -3119 1060 475 seg41 -8177 1060 60 gnddum2 2234 -1047 164 seg318 6833 1060 268 seg214 1881 1060 372 seg144 -3167 1060 476 seg40 -8237 1060 61 im2 2443 -1047 165 seg317 6785 1060 269 seg213 1833 1060 373 seg143 -3214 1060 477 seg39 -8297 1060 62 dummy13 2652 -1047 166 seg316 6738 1060 270 seg212 1786 1060 374 seg142 -3262 1060 478 seg38 -8357 1060 63 im1 2861 -1047 167 seg315 6690 1060 271 seg211 1738 1060 375 seg141 -3309 1060 479 seg37 -8417 1060 64 dummy14 3070 -1047 168 seg314 6643 1060 272 seg210 1690 1060 376 seg140 -3357 1060 480 seg36 -8478 1060 65 im0/id 3279 -1047 169 seg313 6595 1060 273 seg209 1643 1060 377 seg139 -3405 1060 481 seg35 -8538 1060 66 vccdum1 3488 -1047 170 seg312 6547 1060 274 seg208 1595 1060 378 seg138 -3452 1060 482 seg34 -8598 1060 67 test 3697 -1047 171 seg311 6500 1060 275 seg207 1548 1060 379 seg137 -3500 1060 483 dummy70 -8854 1060 68 dummy15 3907 -1047 172 seg310 6452 1060 276 seg206 1500 1060 380 seg136 -3547 1060 484 seg33 -8854 914 69 dcclk 4116 -1047 173 seg309 6404 1060 277 seg205 1452 1060 381 seg135 -3595 1060 485 seg32 -8854 857 70 dummy16 4325 -1047 174 seg308 6357 1060 278 seg204 1405 1060 382 seg134 -3643 1060 486 seg31 -8854 800 71 cl1 4534 -1047 175 seg307 6309 1060 279 seg203 1357 1060 383 seg133 -3690 1060 487 seg30 -8854 742 72 dummy17 4743 -1047 176 seg306 6262 1060 280 seg202 1309 1060 384 seg132 -3738 1060 488 seg29 -8854 685 73 flm 4952 -1047 177 seg305 6214 1060 281 seg201 1262 1060 385 seg131 -3786 1060 489 seg28 -8854 628 74 dummy18 5161 -1047 178 seg304 6166 1060 282 seg200 1214 1060 386 seg130 -3833 1060 490 seg27 -8854 571 75 m 5370 -1047 179 seg303 6119 1060 283 seg199 1167 1060 387 seg129 -3881 1060 491 seg26 -8854 514 76 dummy19 5579 -1047 180 seg302 6071 1060 284 seg198 1119 1060 388 seg128 -3928 1060 492 seg25 -8854 457 77 disptmg 5788 -1047 181 seg301 6024 1060 285 seg197 1071 1060 389 seg127 -3976 1060 493 seg24 -8854 400 78 dummy20 5997 -1047 182 seg300 5976 1060 286 seg196 1024 1060 390 seg126 -4024 1060 494 seg23 -8854 343 79 ccs 6206 -1047 183 seg299 5928 1060 287 seg195 976 1060 391 seg125 -4071 1060 495 seg22 -8854 286 80 dummy21 6415 -1047 184 seg298 5881 1060 288 seg194 929 1060 392 seg124 -4119 1060 496 seg21 -8854 228 81 ccl 6624 -1047 185 seg297 5833 1060 289 seg193 881 1060 393 seg123 -4166 1060 497 seg20 -8854 171 82 dummy22 6833 -1047 186 seg296 5785 1060 290 dummy36 786 1060 394 seg122 -4214 1060 498 seg19 -8854 114 83 cda 7042 -1047 187 seg295 5738 1060 291 dummy37 738 1060 395 seg121 -4262 1060 499 seg18 -8854 57 84 dummy23 7251 -1047 188 seg294 5690 1060 292 dummy38 690 1060 396 seg120 -4309 1060 500 seg17 -8854 0 85 reset 7460 -1047 189 seg293 5643 1060 293 dummy39 643 1060 397 seg119 -4357 1060 501 seg16 -8854 -57 86 dummy24 7669 -1047 190 seg292 5595 1060 294 dummy40 595 1060 398 seg118 -4405 1060 502 seg15 -8854 -114 87 dummy25 7775 -1047 191 seg291 5547 1060 295 dummy41 548 1060 399 seg117 -4452 1060 503 seg14 -8854 -171 88 dummy26 7881 -1047 192 seg290 5500 1060 296 dummy42 500 1060 400 seg116 -4500 1060 504 seg13 -8854 -228 89 dummy27 7987 -1047 193 seg289 5452 1060 297 dummy43 452 1060 401 seg115 -4547 1060 505 seg12 -8854 -286 90 dummy28 8092 -1047 194 seg288 5404 1060 298 dummy44 405 1060 402 seg114 -4595 1060 506 seg11 -8854 -343 91 dummy29 8198 -1047 195 seg287 5357 1060 299 dummy45 357 1060 403 seg113 -4643 1060 507 seg10 -8854 -400 92 dummy30 8304 -1047 196 seg286 5309 1060 300 dummy46 310 1060 404 seg112 -4690 1060 508 seg9 -8854 -457 93 dummy31 8409 -1047 197 seg285 5262 1060 301 dummy47 262 1060 405 seg111 -4738 1060 509 seg8 -8854 -514 94 dummy32 8515 -1047 198 seg284 5214 1060 302 dummy48 214 1060 406 seg110 -4785 1060 510 seg7 -8854 -571 95 dummy33 8621 -1047 199 seg283 5166 1060 303 dummy49 167 1060 407 seg109 -4833 1060 511 seg6 -8854 -628 96 dummy34 8854 -1047 200 seg282 5119 1060 304 dummy50 119 1060 408 seg108 -4881 1060 512 seg5 -8854 -685 97 seg384 8854 -914 201 seg281 5071 1060 305 dummy51 71 1060 409 seg107 -4928 1060 513 seg4 -8854 -742 98 seg383 8854 -857 202 seg280 5024 1060 306 dummy52 24 1060 410 seg106 -4976 1060 514 seg3 -8854 -800 99 seg382 8854 -800 203 seg279 4976 1060 307 dummy53 -24 1060 411 seg105 -5024 1060 515 seg2 -8854 -857 100 seg381 8854 -742 204 seg278 4928 1060 308 dummy54 -71 1060 412 seg104 -5071 1060 516 seg1 -8854 -914 101 seg380 8854 -685 205 seg277 4881 1060 309 dummy55 -119 1060 413 seg103 -5119 1060 102 seg379 8854 -628 206 seg276 4833 1060 310 dummy56 -167 1060 414 seg102 -5166 1060 103 seg378 8854 -571 207 seg275 4785 1060 311 dummy57 -214 1060 415 seg101 -5214 1060 104 seg377 8854 -514 208 seg274 4738 1060 312 dummy58 -262 1060 416 seg100 -5262 1060 hd66763 7 pin functions table 1 pin functional description signals number of pins i/o connected to functions im2-1, im0/id 3i gnd or v cc selects the mpu interface mode: im1 gnd gnd vcc vcc im0/id gnd vcc gnd vcc mpu interface mode 68-system 16-bit bus interface 68-system 8-bit bus interface 80-system 16-bit bus interface 80-system 8-bit bus interface im2 gnd gnd gnd gnd vcc gnd id serial peripheral interface (spi) when a serial interface is selected, the im0 pin is used as the id setting for a device code. cs* 1 i mpu selects the hd66763: low: hd66763 is selected and can be accessed high: hd66763 is not selected and cannot be accessed must be fixed at gnd level when not in use. rs 1 i mpu selects the register. low: index/status high: control e/wr*/scl 1 i mpu for a 68-system bus interface, serves as an enable signal to activate data read/write operation. for an 80-system bus interface, serves as a write strobe signal and writes data at the low level. for a synchronous clock interface, serves as the synchronous clock signal. rw/rd* 1 i mpu for a 68-system bus interface, serves as a signal to select data read/write operation. low: write high: read for an 80-system bus interface, serves as a read strobe signal and reads data at the low level. db0/sdi 1 i/o mpu serves as a 16-bit bidirectional data bus. for an 8-bit bus interface, data transfer uses db15- db8; fix unused db7-db0 to the vcc or gnd level. for a clock-synchronous serial interface, serves as the serial data input pin (sdi). the input level is read on the rising edge of the scl signal. hd66763 8 table 1 pin functional description (cont) signals number of pins i/o connected to functions db1/sdo 1 i/o mpu serves as a 16-bit bidirectional data bus. for an 8-bit bus interface, data transfer uses db15- db8; fix unused db7-db0 to the vcc or gnd level. for a clock-synchronous serial interface, serves as a serial data output pin (sdo). successive bit values are output on the falling edge of the scl signal. db2-db15 14 i/o mpu serves as a 16-bit bidirectional data bus. for an 8-bit bus interface, data transfer uses db15- db8; fix unused db7-db0 to the vcc or gnd level. seg1?se g384 384 o lcd output signals for segment drive. in the display-off period (d1?0 = 00, 01) or standby mode (stb = 1), all pins output gnd level. the sgs bit can change the shift direction of the segment signal. for example, if sgs = 0, ram address 0000 is output from seg1. if sgs = 1, it is output from seg384. seg1, seg4, seg7, ... display red (r), seg2, seg5, seg8, ... display green (g), and seg3, seg6, seg9, ... display blue (b) (sgs = 0). cl1 1 o hd66764 the one-raster-row-cycle pulse is output. m1 o hd66764 the ac-cycle signal is output. flm 1 o hd66764 the frame-start pulse is output. disptmg 1 o hd66764 outputs the display period signal. dcclk 1 o hd66764 outputs clocks for the step-up. ccl 1 o hd66764 clock signal for a serial transfer of register setting values to the common driver. data is output on the falling edge of this clock. cda 1 o hd66764 data signal for serial transfer as register setting values to the common driver. ccs* 1 o hd66764 chip-select for the hd66763. low: the hd66763 is selected and can receive a serial transfer. high: the hd66763 is not selected and cannot receive a serial transfer. vsh 1 i hd66764 input for the lcd-drive voltage for the segment driver, which can be provided by the hd66764?s on-chip power supply. vsh 4.0 v v cc , gnd 2 ? power supply v cc : + 1.8 v to + 3.6 v; gnd (logic): 0 hd66763 9 table 1 pin functional description (cont) signals number of pins i/o connected to functions osc1, osc2 2i or o oscillation- resistor connect an external resistor for r-c oscillation. when providing clocks from outside, open osc2. reset* 1 i mpu or external r-c circuit reset pin. initializes the lsi when low. must be reset after power-on. vccdum o input pins outputs the internal v cc level; shorting this pin sets the adjacent input pin to the v cc level. gnddum o input pins outputs the internal gnd level; shorting this pin sets the adjacent input pin to the gnd level. dummy ? ? dummy pad. must be left disconnected. test 1 i gnd test pin. must be fixed at gnd level. hd66763 10 block function description system interface the hd66763 has five high-speed system interfaces: an 80-system 16-bit/8-bit bus, a 68-system 16-bit/8- bit bus, and a serial peripheral (spi: serial peripheral interface port). the interface mode is selected by the im2-0 pins. the hd66763 has three 16-bit registers: an index register (ir), a write data register (wdr), and a read data register (rdr). the ir stores index information from the control registers and the gram. the wdr temporarily stores data to be written into control registers and the gram, and the rdr temporarily stores data read from the gram. data written into the gram from the mpu is first written into the wdr and then is automatically written into the gram by internal operation. data is read through the rdr when reading from the gram, and the first read data is invalid and the second and the following data are normal. when a logic operation is performed inside of the hd66763 by using the display data set in the gram and the data written from the mpu, the data read through the rdr is used. accordingly, the mpu does not need to read data twice nor to fetch the read data into the mpu. this enables high-speed processing. execution time for instruction excluding oscillation start is 0 clock cycle and instructions can be written in succession. table 2 register selection (8/16 parallel interface) 80-system bus 68-system bus wr bits rd bits r/w bits rs bits operations 01 00 writes indexes into ir 10 10 reads internal status 01 01 writes into control registers and gram through wdr 10 11 reads from gram through rdr table 3 register selection (serial peripheral interface) start bytes r/w bits rs bits operations 00 writes indexes into ir 10 reads internal status 01 writes into control registers and gram through wdr 11 reads from gram through rdr hd66763 11 bit operation the hd66763 supports the following functions: a swap function that writes the data written from the mpu into the gram by reversing the display position vertically in byte units, a write data mask function that selects and writes data into the gram in bit units, and a logic operation function that performs logic operations or conditional determination on the display data set in the gram and writes into the gram. with the 16-bit bus interface, these functions can greatly reduce the processing loads of the mpu graphics software and can rewrite the display data in the gram at high speed. for details, see the graphics operation function section. address counter (ac) the address counter (ac) assigns addresses to the gram. when an address set instruction is written into the ir, the address information is sent from the ir to the ac. after writing into the gram, the ac is automatically incremented by 1 (or decremented by 1). after reading from the data, the ac is not updated. a window address function allows for data to be written only to a window area specified by gram. graphics ram (gram) the graphics ram (gram) has eight bits/pixel and stores the bit-pattern data of 128 x 176 bytes. pwm grayscale circuit the pwm grayscale circuit generates a pwm signal that corresponds to the grayscale levels as specified in the grayscale palette register. any 256 of the 4,096 possible colors can be displayed at the same time. for details, see the grayscale palette section. grayscale selection circuit the grayscale selection circuit reads data from the gram and controls the signal generated in the pwm grayscale circuit. pwm (pulse width modulation) is used to control each color in the display. for details, see the grayscale palette section. timing generator the timing generator generates timing signals for the operation of internal circuits such as the gram. the ram read timing for display and internal operation timing by mpu access are generated separately to avoid interference with one another. the timing generator generates the interface signals (m, flm, cl1, disptmg, and dcclk) for the common driver. oscillation circuit (osc) the hd66763 can provide r-c oscillation simply through the addition of an external oscillation-resistor between the osc1 and osc2 pins. the appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the external-resistor value. clock pulses can also be supplied externally. since r-c oscillation stops during the standby mode, current consumption can be reduced. for details, see the oscillation circuit section. hd66763 12 liquid crystal display driver circuit the liquid crystal display driver circuit consists of 384 segment signal drivers (seg1 to seg384). display pattern data is latched when 384-bit data has arrived. the latched data then enables the segment signal drivers to generate drive waveform outputs. the shift direction of 384-bit data can be changed by the sgs bit by selecting an appropriate direction for the device mounting configuration. when multiplexing drive is not used, or during standby mode, all of the common and segment signal drivers listed above, and the common drivers from the hd66764, output the gnd level, halting the display. interface with common driver a se ri al in te rf ac e ci rc uit provides an interface with the hd66764 common driver. when sending an in st ru c ti on setting from the hd66763 to a common driver, a register setting value from within the hd 66763 is transferred via the serial interface circuit. a transfer is started by se tting a serial tran sfer en ab le in th e hd 66763. however, transfer to and reading from the common driver are not possible during standby. for details, see the common serial transfer section. hd66763 13 table relationship between gram address and display position (sgs=0, swp=0) cms=0 seg/com pins seg1 cms=1 db 15 db 8 db 7 db 0 com1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 com176 "0000"h "0001"h "0100"h "0101"h "0200"h "0201"h "0300"h "0301"h "0400"h "0401"h "0500"h "0501"h "0600"h "0601"h "0700"h "0701"h "0800"h "0801"h "0900"h "0901"h "0a00"h "0a01"h "0b00"h "0b01"h "0c00"h "0c01"h "0d00"h "0d01"h "0e00"h "0e01"h "0f00"h "0f01"h "1000"h "1001"h "1100"h "1101"h "1200"h "1201"h "1300"h "1301"h "a800"h "a801"h "a900"h "a901"h "aa00"h "aa01"h "ab00"h "ab01"h "ac00"h "ac01"h "ad00"h "ad01"h "ae00"h "ae01"h "af00"h "af01"h "003e"h "003f"h "013e"h "013f"h "023e"h "023f"h "033e"h "033f"h "043e"h "043f"h "053e"h "053f"h "063e"h "063f"h "073e"h "073f"h "083e"h "083f"h "093e"h "093f"h "0a3e"h "0a3f"h "0b3e"h "0b3f"h "0c3e"h "0c3f"h "0d3e"h "0d3f"h "0e3e"h "0e3f"h "0f3e"h "0f3f"h "103e"h "103f"h "113e"h "113f"h "123e"h "123f"h "133e"h "133f"h "a83e"h "a83f"h "a93e"h "a93f"h "aa3e"h "aa3f"h "ab3e"h "ab3f"h "ac3e"h "ac3f"h "ad3e"h "ad3f"h "ae3e"h "ae3f"h "af3e"h "af3f"h com2 com175 com3 com174 com4 com173 com5 com172 com6 com171 com7 com170 com8 com169 com9 com168 com10 com167 com11 com166 com12 com165 com13 com164 com14 com163 com15 com162 com16 com161 com17 com160 com18 com159 com19 com158 com20 com157 com169 com8 com170 com7 com171 com6 com172 com5 com173 com4 com174 com3 com175 com2 com176 com1 seg373 seg374 seg375 seg376 seg377 seg378 seg379 seg380 seg381 seg382 seg383 seg384 db 15 db 8 db 7 db 0 db 15 db 8 db 7 db 0 db 15 db 8 db 7 db 0 table relationship between gram data and output pin (sgs=0) gram data db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 selected palette rk palette gk palette bk palette rk palette gk palette bk palette output pin seg (6n+1) seg (6n+2) seg (6n+3) seg (6n+4) seg (6n+5) seg (6n+6) n = lower 6-bits address (0 to 63) hd66763 14 table relationship between gram address and display position (sgs=1, swp=0) cms=0 seg/com pins seg1 cms=1 db 0 db 7 db 8 db 15 com1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 "0000"h "0001"h "0100"h "0101"h "0200"h "0201"h "0300"h "0301"h "0400"h "0401"h "0500"h "0501"h "0600"h "0601"h "0700"h "0701"h "0800"h "0801"h "0900"h "0901"h "0a00"h "0a01"h "0b00"h "0b01"h "0c00"h "0c01"h "0d00"h "0d01"h "0e00"h "0e01"h "0f00"h "0f01"h "1000"h "1001"h "1100"h "1101"h "1200"h "1201"h "1300"h "1301"h "003e"h "003f"h "013e"h "013f"h "023e"h "023f"h "033e"h "033f"h "043e"h "043f"h "053e"h "053f"h "063e"h "063f"h "073e"h "073f"h "083e"h "083f"h "093e"h "093f"h "0a3e"h "0a3f"h "0b3e"h "0b3f"h "0c3e"h "0c3f"h "0d3e"h "0d3f"h "0e3e"h "0e3f"h "0f3e"h "0f3f"h "103e"h "103f"h "113e"h "113f"h "123e"h "123f"h "133e"h "133f"h com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com8 com7 com6 com5 com4 com3 com2 com1 seg373 seg374 seg375 seg376 seg377 seg378 seg379 seg380 seg381 seg382 seg383 seg384 db 0 db 7 db 8 db 15 db 0 db 7 db 8 db 15 db 0 db 7 db 8 db 15 com176 com175 com174 com173 com172 com171 com170 com169 com168 com167 com166 com165 com164 com163 com162 com161 com160 com159 com158 com157 com169 com170 com171 com172 com173 com174 com175 com176 "a800"h "a801"h "a900"h "a901"h "aa00"h "aa01"h "ab00"h "ab01"h "ac00"h "ac01"h "ad00"h "ad01"h "ae00"h "ae01"h "af00"h "af01"h "a83e"h "a83f"h "a93e"h "a93f"h "aa3e"h "aa3f"h "ab3e"h "ab3f"h "ac3e"h "ac3f"h "ad3e"h "ad3f"h "ae3e"h "ae3f"h "af3e"h "af3f"h table relationship between gram data and output pin (sgs=1) gram data db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 selected palette rk palette gk palette bk palette rk palette gk palette bk palette output pin seg (384-6n) seg (383-6n) seg (382-6n) seg (381-6n) seg (380-6n) seg (379-6n) n = lower 6-bits address (0 to 63) hd66763 14 instructions outline the hd66763 uses the 16-bit bus architecture. before the internal operation of the hd66763 starts, control information is temporarily stored in the registers described below to allow high-speed interfacing with a high-performance microcomputer. the internal operation of the hd66763 is determined by signals sent from the microcomputer. these signals, which include the register selection signal (rs), the read/write signal (r/w), and the data bus signals (db15 to db0), make up the hd66763 instructions. there are nine categories of instructions that: ? specify the index ? read the status ? control the display ? control power management ? process the graphics data ? set internal gram addresses ? transfer data to and from the internal gram ? set grayscale level for the internal grayscale palette table ? i nterface with the common driver normally, instructions that write data are used the most. however, an auto-update of internal gram addresses after each data write can lighten the microcomputer program load. because instructions are executed in 0 cycles, they can be written in succession. hd66763 15 instruction descriptions index the index instruction specifies the ram control indexes (r00h to r39h). it sets the register number in the range of 00000 to 111001 in binary form. however, r40 to r44 are disabled since they are test registers. w0 ******* * id4 id3 id2 id1 id0 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 * id6 id5 figure 1 index instruction status read the status read instruction reads the internal status of the hd66763. l7?0: indicate the driving raster-row position where the liquid crystal display is being driven. c6?0: read the contrast setting values (ct6?0). r0 l6 l5 l4 l3 l2 l1 l0 0 c6 c5 c4 c3 c2 c1 c0 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 l7 figure 2 status read instruction start oscillation (r00h) the start oscillation instruction restarts the oscillator from the halt state in the standby mode. after issuing this instruction, wait at least 10 ms for oscillation to stabilize before issuing the next instruction. (see the standby mode section.) if this register is read forcibly, *763h is read. w1 * * * * * * * 1 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 * * * * * * * * r1 1 1 0 0 0 1 1 0 1 1 1 0 0 0 0 0 figure 3 start oscillation instruction hd66763 16 driver output control (r01h) w1 cms sgs r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 nl0 nl1 nl2 nl3 nl4 0 0 0 0 0 0 0 0 0 0 0 0 figure 4 driver output control instruction cms: selects the output shift direction of a common driver. when cms = 0, com1 shifts to com168. when cms = 1, com168 shifts to com1. sgs: selects the output shift direction of a segment driver by using with the swp bit. when sgs = 0 and swp = 0, seg1 shifts to seg384. when sgs = 1 and swp=1, seg384 shifts to seg1. when sgs = 0 and swp = 0, the seg1 pin assigns the color display to r, g, or b. when sgs = 1 and swp = 1, the seg384 pin assigns r, g, or b to the color display. re-write to the ram when intending to change the sgs bit. note: the cms bit is for setting the common driver. control according to the bit?s value is executed by the common driver. for details, see the data sheet for the common driver. nl4?0: specify the lcd drive duty ratio. the duty ratio can be adjusted for every eight raster-rows. gram address mapping does not depend on the setting value of the drive duty ratio. hd66763 17 table 8 nl bits and drive duty nl4 nl3 nl2 nl1 nl0 display size lcd drive duty common driver used 0 0 0 0 0 setting disabled setting disabled setting disabled 0 0 0 0 1 384 x 16 dots 1/16 duty com1?com16 0 0 0 1 0 384 x 24 dots 1/24 duty com1?com24 0 0 0 1 1 384 x 32 dots 1/32 duty com1?com32 0 0 1 0 0 384 x 40 dots 1/40 duty com1?com40 0 0 1 0 1 384 x 48 dots 1/48 duty com1?com48 0 0 1 1 0 384 x 56 dots 1/56 duty com1?com56 0 0 1 1 1 384 x 64 dots 1/64 duty com1?com64 0 1 0 0 0 384 x 72 dots 1/72 duty com1?com72 0 1 0 0 1 384 x 80 dots 1/80 duty com1?com80 0 1 0 1 0 384 x 88 dots 1/88 duty com1?com88 0 1 0 1 1 384 x 96 dots 1/96 duty com1?com96 0 1 1 0 0 384 x 104 dots 1/104 duty com1?com104 0 1 1 0 1 384 x 112 dots 1/112 duty com1?com112 0 1 1 1 0 384 x 120 dots 1/120 duty com1?com120 0 1 1 1 1 384 x 128 dots 1/128 duty com1?com128 1 0 0 0 0 384 x 136 dots 1/136 duty com1?com136 1 0 0 0 1 384 x 144 dots 1/144 duty com1?com144 1 0 0 1 0 384 x 152 dots 1/152 duty com1?com152 1 0 0 1 1 384 x 160 dots 1/160 duty com1?com160 1 0 1 0 0 384 x 168 dots 1/168 duty com1?com168 1 0 1 0 1 384 x 176 dots 1/176 duty com1?com176 hd66763 18 lcd-driving-waveform control (r02h) w1 nw1 nw0 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 nw2 nw3 nw4 nw5 0 0 0 0 0 0 00 eor b/c figure 5 lcd-driving-waveform control instruction b/c: when b/c = 0, a b-pattern waveform is generated and alternates in every frame for lcd drive. when b/c = 1, a c-pattern waveform is generated and alternates in each raster-row specified by bits eor and nw4?nw0 in the lcd-driving-waveform control register. for details, see the n-raster-row reversed ac drive section. eor: when the c-pattern waveform is set (b/c = 1) and eor = 1, the odd/even frame-select signals and the n-raster-row reversed signals are eored for alternating drive. eor is used when the lcd is not alternated by combining the set values of the lcd drive duty ratio and the n raster-row. for details, see the n-raster-row reversed ac drive section. n w5?0: spec ify the number of raster-rows n that will alternate at the c-pattern waveform setting (b/c = 1). nw4?nw0 alternate for every set value + 1 raster-row, and the first to the 64th raster-rows can be selected. power control 1 (r03h) power control 2 (r0ch) w1 0 dc2 dc1 dc0 ap1 ap0 slp stb r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 bt0 bt1 bt3 bs0 bs1 bs2 0 w1 vc0 vc1 vc2 0 0 0 0 0 0 0 0 0 0 0 0 0 bt2 figure 6 power control instruction bs2?0: the lcd drive bias value is set. the lcd drive bias value can be selected according to its drive duty ratio and voltage. bt3?0: the output factor of step-up is switched. the lcd drive voltage level can be selected according to its drive duty ratio and bias. lower amplification of the step-up circuit consumes less current. dc2?0: the operating frequency in the step-up circuit is selected. when the step-up operating frequency is high, the driving ability of the step-up circuit and the display quality become high, but the current consumption is increased. adjust the frequency considering the display quality and the current consumption. ap1?0: the amount of fixed current from the fixed current source in the operational amplifier for the lcd is adjusted. when the amount of fixed current is large, the lcd driving ability and the display quality become high, but the current consumption is increased. adjust the fixed current considering the display quality and the current consumption. hd66763 19 during no display, when ap1?0 = 00, the current consumption can be reduced by ending the operational amplifier and step-up circuit operation. vc2-0: sets an adjustment factor for the vci voltage (vc2-0). slp: when slp = 1, the hd66763 enters the sleep mode, where the internal display operations are halted except for the r-c oscillator, thus reducing current consumption. only the following instructions can be executed during the sleep mode. power control (bs2?0, bt3?0, dc2?0, ap1?0, slp, and stb bits) common interface control (te, idx) during the sleep mode, the other gram data and instructions cannot be updated although they are retained. note: bs2-0, bt 3-0, dc2-0, ap1-0, vc2-0 and slp bits are for setting the common driver. control ac cor ding to the bits? values is exe cuted by the common dr iver. for de tails, se e the da ta sheet for the common driver. stb: when stb = 1, the hd66763 enters the standby mode, where display operation completely stops, halting all the internal operations including the internal r-c oscillator. further, no external clock pulses are supplied. for details, see the standby mode section. only the following instructions can be executed during the standby mode. a. standby mode cancel (stb = 0) b. start oscillation du ri ng the standby mode, the gram data and instructions may be lost. to prevent this, they must be set ag ai n after the standby mode is canceled. serial transfer to the common driver is not possible when it is in standby mode. transfer the data again after it has been released from standby mode. contrast control (r04h) w1 ct1 ct0 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 ct2 ct3 ct4 ct5 ct6 vr2 vr3 0 0 0 0 0 vr0 vr1 figure 7 contrast control instruction ct 6?0: th es e b its c ont ro l th e lc d drive voltage (potential difference betw een v1 and gnd) to adjust 128-step contrast. for details, see the contrast adjuster section. vr3?0: these bits adjust the output voltage in the lcd drive reference generator. note: ct6-0 and vr 3-0 bits are for setting the common driver. control according to the bits? values is executed by the common driver. for details, see the data sheet for the common driver. hd66763 20 entry mode (r05h) compare register (r06h) w1 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 lg0 lg1 lg2 i/d0 am hwm 0 w1 cp1 cp0 cp2 0 0 0 0 0 0 0 swp 0 0 i/d1 0 0 0 0 00 cp7 cp6 cp5 cp4 cp3 figure 8 entry mode and compare register instruction the write data sent from the microcomputer is modified in the hd66763 and written to the gram. the display data in the gram can be quickly rewritten to reduce the load of the microcomputer software processing. for details, see the graphics operation function section. hwm: when hwm=1, data can be written to the gram at high speed. in high-speed write mode, four words of data are written to the gram in a single operation after writing to ram four times. write to ram four times, otherwise the four words cannot be written to the gram. thus, set the lower 2 bits to 0 when setting the ram address. for details, see high-speed ram write mode section. swp: when swp = 1, the upper and lower bytes in the two-byte data sent from the microcomputer are swapped and written to the gram. when swp = 0, this bit directly writes the two-byte data sent from the microcomputer to the gram. this swap processing is performed only for the data sent from the microcomputer before logical operation. when swp = 1, the upper and lower bytes in the write data mask (wm15?0) are swapped to be executed with the write data. i/d1-0: when i/d1-0 = 1, the address counter (ac) is automatically incremented by 1 after the data is written to the gram. when i/d1-0 = 0, the ac is automatically decremented by 1 after the data is written to the gram. the increment/decrement setting of the address counter by i/d1-0 is done independently for the upper (ad15-8) and lower (ad5-0) addresses. the direction of moving through the addresses when the gram is written to is set by the am bit. am: set the automatic update method of the ac after the data is written to the gram. when am = 0, the data is continuously written in parallel. when am = 1, the data is continuously written vertically. when window address range is specified, the gram in the window address range can be written to according to the i/d1-0 and am settings. hd66763 21 am = "0" horizontal 0000h af3fh 0000h af3fh 0000h af3fh i/d1-0 = "00" horizontal: decrement ve r tical: decrement note: when a window address range has been set, the gram can only be witten to within that range. i/d1-0 = "10" horizontal: decrement ve r tical: increment i/d1-0 = "11" horizontal: increment ve r tical: increment i/d1-0 = "01" horizontal: increment ve r tical: decrement am = "1" ve r tical 0000h af3fh 0000h af3fh 0000h af3fh 0000h af3fh 0000h af3fh direction settings figure 9 address direction settings lg2?0: compare the data read from the gram by the microcomputer with the compare registers (cp7?0) by a compare/logical operation and write the results to gram. for details, see the logical/compare operation function. cp 7?0: se t the compare register for the compare operation with the data read from the gram or written by the microcomputer. hd66763 22 0001 1 db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db1 2 db1 3 db14 db15 10 0 111 00 0 11 log ica l o p eration (read data and write data) lg2 -0 = "0 00 ": re plac emen t lg2 -0 = "0 01 ": or lg2 -0 = "0 10 ": an d lg2 -0 = "0 11 ": eo r wr i te da ta m a sk (w m1 5?0) gram writ e dat a se nt from the micr oco mput er (db1 5? 0) swp = "1 " swap o f up per an d lower byt es log ic a l/c omp are ope rat ion (l g2? 0) writ e dat a m ask* (wm1 5?0 ) 11100011 00011100 compa re op erat i on ( wit h c omp are r eg i st er ) lg 2 - 0 = "10 0" : repl acement of matched read data lg 2 - 0 = "10 1" : repl acement of unmatched read data lg 2 - 0 = "11 0 ": r ep l acement of matched write data lg 2 - 0 = "111" : rep la ceme nt o f unm at ch ed w ri t e d at a not es: 1. t he write data mas k (wm 15 ?0) is s et b y the re gist er in the ram w rite dat a m ask s ect ion. 2. whe n swp = 1 , t he up per a nd lowe r byte s in the write d ata m a sk are swa ppe d to b e exe cuted wit h the writ e data. figure 10 logical/compare operation and swapping for the gram display control (r07h) w1 d0 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 vle 2 0 0 0 0 00d1 rev 0 00 vle 1 spt 0 figure 11 display control instruction vle2?1: when vle1 = 1, a vertical scroll is performed in the 1st screen. when vle2 = 1, a vertical scroll is performed in the 2nd screen. vertical scrolling on the two screens can be independently controlled. spt: when spt = 1, the 2-division lcd drive is performed. for details, see the screen-division driving function section. rev: displays all character and graphics display sections with reversal when rev = 1. for details, see the reversed display function section. since the grayscale level can be reversed, display of the same data is enabled on normally-white and normally-black panels. d1?0: display is on when d1 = 1 and off when d1 = 0. when off, the display data remains in the gram, and can be displayed instantly by setting d1 = 1. when d1 is 0, the display is off with all of the seg/com pin outputs set to the gnd level. because of this, the hd66763 can control the charging current for the lcd with ac driving. hd66763 23 when d1?0 = 01, the internal display of the hd66763 is performed although the display is off. when d1-0 = 00, the internal display operation halts and the display is off. table 9 d bits and operation d1 d0 seg/com output hd66763 internal display operation master/slave signal (cl1, flm, m, and disptmg) 00 gnd halt halt 01 gnd operate operate 10 unlit display operate operate 11 display operate operate notes: 1. writing from the microcomputer to the gram is independent from d1?0. 2. in the sleep and standby modes, d1?0 = 00. however, the register contents of d1?0 are not modified. note: spt and d1 b its are for setting the common driver. control according to the bits? values is executed by the common driver. for details, see the data sheet for the common driver. com driver interface control (r0ah) w r 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 te te 0 0 0 0 0 0 0 0 0 0 idx2 idx2 idx1 idx1 idx0 r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 idx0 figure 12 com driver interface control instruction i dx2-0 : i ndex bits that select instructions for the common driver. the instruction that corresponds to the se tting made here is transferred, with the index, to the common driver via the serial interface. these in st ru c ti ons are transferred in bit rows as shown below. the upper 3 bits correspond to idx2-0. the idx2-0 setting at the time of transfer selects the instruction for the common driver as listed below. to ch a nge an instruction setting on the common driver, first change the instruction bit on the hd66763, select the instruction, which includes the changed instruction bit, from the list below, by setting idx2-0 as re quired. the instruction is transferred to the common driver as the transfer starts (te=1), and is the executed . te: ser ial tra nsf er enable for the comm on driver. when te=0, serial transfer is possible. do not change the instruct i on during transfer. when te=1, transfer starts. te returning to 0 indicates the end of the transfer. note that, serial transfer to the common dr iver re quires 18 clock cycles at most. do not change the instruction during the transfer. * new instructions should be transferred to the common driver soon after they have been set on the hd66763. hd66763 24 00 bs2 bs1 bs0 bt3 bt2 bt1 bt0 dc2 dc1 dc0 ap1 ap0 slp idx1 idx2 ta b le of common driver (hd66764) instructions idx0 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 01 00 000 00000 vc2 vc1 vc0 10 0 vr3 vr2 vr1 vr0 0 ct6 ct5 ct4 ct3 ct2 ct1 ct0 11 00 d1 cms spt ss17 ss16 ss15 ss14 ss13 ss12 ss11 ss10 00 00 000 se17 se16 se15 se14 se13 se12 se11 se10 01 00 000 ss27 ss26 ss25 ss24 ss23 ss22 ss21 ss20 10 00 000 se27 se26 se25 se24 se23 se22 se21 se20 0 0 0 0 1 1 1 instruction setting change index set r0ah instruction read specify the idx2 to 0 in the hd66764 instruction including a changed instruction bit common side index (idx2 to 0) te = 1 (transfer start) te = "0" no (during transfer) yes (transfer can be executed) tr ansfer to the common driver must be executed immediately after setting up the instruction change the instruction bit setting corresponding to the hd66763 notes: 1. transfer to the common driver must take place immediately after setting up the instruction. 2. the serial transfer period takes a maximum of 1/fosc x 18 clock cycles (sec). 3. serial transfer cannot be executed in standby mode. if the chip enters standbymode during transfer, the serial transfer is forcibly suspended. transfer must be executed again because correct transfer is not guaranteed in this situation. 4. serial transfer can be forcibly suspended by writing te = 0. transfer must be executed again becaus e correct transfer is not guaranteed in this situation. 5. do not enter standby mode during transfer or forcibly terminate transfer except in case of emergency. before executing, confirm that the transfer is completed. figure 13 common interface: serial transfer sequence hd66763 25 frame cycle control (r0bh) w1 rt n 0 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 rtn 1 000 rtn 3 0 0 0 0 00 rtn 2 div1div0 0 figure 14 frame cycle control instruction rtn3-0: set the line retrac e peri od (rtn3-0) to be added to raster-row cycles. the raster-row cycle becomes longer according to the number of clocks set at rtn3-0. div1-0: set the di vision ratio of clocks for internal operation (div1-0). internal operations are driven by cloc ks which are frequency divided according to the div1-0 setting. frame frequency can be adjusted al ong with the line retrace period (rtn3-0). when changing the drive-duty cycle, adjust the frame frequency. for details, see the frame frequency adjustment function section. table 10 rtn bits and clock cycles rtn3 rtn2 rtn1 rtn0 line retrace period (clock cycles) clock cycles per raster-row 0000 0 17 0001 1 18 0010 2 19 0011 3 20 :::: : : 1110 14 31 1111 15 32 table 11 div bits and clock frequency div1 div0 division ratio internal operation clock frequency 00 1 fosc / 1 01 2 fosc / 2 10 4 fosc / 4 11 8 fosc / 8 * fosc = r-c oscillation frequency hd66763 26 formula for the frame frequency fosc frame frequency = [h z] clock cycles per raster-row division ratio 1/duty cycle fosc: r-c oscillation frequency duty: drive duty (nl bit) division ratio: div bit clock cycles per raster-row: (rtn + 17) clock cycles vertical scroll control (r11h) vl17?10: specify the display-start raster-row at the 1st screen display for vertical smooth scrolling. any raster-row from the first to 176th can be selected. after the 176th raster-row is displayed, the display restarts from the first raster-row. the display-start raster-row (vl17?10) is valid only when vle1 = 1. the raster-row display is fixed when vle1 = 0. (vle1 is the 1st-screen vertical-scroll enable bit.) vl27?20: specify the display-start raster-row at the 2nd screen display. the display-start raster-row (vl27?20) is valid only when vle2 = 1. the raster-row display is fixed when vle2 = 0. (vle2 is the 2nd-screen vertical-scroll enable bit.) the vertical scroll for the 1st and 2nd screens can be independently set. w1 vl 11 vl 10 vl 12 vl 17 vl 16 vl 15 vl 14 vl 13 vl 21 vl 20 vl 22 vl 27 vl 26 vl 25 vl 24 vl 23 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 figure 15 vertical scroll control instruction table 22 vl bits and display-start raster-row vl27 vl17 vl26 vl16 vl25 vl15 vl24 vl14 vl23 vl13 vl22 vl12 vl21 vl11 vl20 vl10 display-start raster-row 0000 000 0 1st raster-row 0000 000 1 2nd raster-row 0000 001 0 3rd raster-row :::: ::: :: 1010 111 0 175th raster-row 1010 111 1 176th raster-row note: do not set over the 176th (afh) raster-row. hd66763 27 1st screen driving position (r14h) 2nd screen driving position (r15h) w1 ss11 ss10 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 ss12 ss17 ss16 ss15 ss14 ss13 w1 ss21 ss20 ss22 ss27 ss26 ss25 ss24 ss23 se11 se10 se12 se17 se16 se15 se14 se13 se21 se20 se22 se27 se26 se25 se24 se23 figure 16 1st screen driving position and 2nd screen driving position instructions ss17?0: specify the driving start position for the first screen in a line unit. the lcd driving starts from the 'set value + 1' common driver. se17?0: specify the driving end position for the first screen in a line unit. the lcd driving is performed to the 'set value + 1' common driver. for instance, when ss17?10 = 07h and se17?10 = 10h are set, the lcd driving is performed from com8 to com17, and non-selection driving is performed for com1 to com7, com18, and others. ensure that ss17?10 se17?10 afh. for details, see the screen-division driving function section. ss27?0: specify the driving start position for the second screen in a line unit. the lcd driving starts from the 'set value + 1' common driver. the second screen is driven when spt = 1. se27?0: specify the driving end position for the second screen in a line unit. the lcd driving is performed to the 'set value + 1' common driver. for instance, when spt = 1, ss27?20 = 20h, and se27?20 = afh are set, the lcd driving is performed from com33 to com80. ensure that ss17?10 se17?10 ss27?20 se27?20 4fh. for details, see the screen-division driving function section. hd66763 28 horizontal ram address position (r16h) vertical ram address position (r17h) w1 hsa 1 hsa 0 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 hsa 2 00 hsa 5 hsa 4 hsa 3 w1 vsa 1 vsa 0 vsa 2 vsa 7 vsa 6 vsa 5 vsa 4 vsa 3 hea 1 hea 0 hea 2 00 hea 5 hea 4 hea 3 vea 1 vea 0 vea 2 vea 7 vea 6 vae 5 vea 4 vea 3 figure 17 horizontal/vertical ram address position instruction hsa5-0/h ea5- 0: sp eci fy th e horizontal start/end positions of a window for access in memory. data can be wr itten to the gram from the address specified by hea5-0 from the address specified by hsa5-0. note that an address must be set before ram is written to. ensure 00h hsa5-0 hea5-0 3fh. vsa7-0/vea7-0: sp ec if y the vertical start/end positions of a window for access in memory. data can be wri tten to the gram from the address specified by ve a7-0 fr om the a ddress specified by vsa7-0. note that an address must be set before ram is written to. ensure 00h vsa7-0 vea7-0 afh. vsa vea hsa gram address space 0000h af3fh hea window address window address setting range "00"h hsa5-0 hea5-0 "3f"h "00"h vsa7-0 vea7-0 "af"h note: 1. ensure that the window address area is within the gram address space. 2. in high-speed write mode, data are written to gram in four-words. thus, dummy write operations should be inserted depending on the window address area. for details, see the high-speed burst ram write function section. figure 18 window address setting range hd66763 29 ram write data mask (r20h) w1 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 wm 7 wm 6 wm 5 wm 4 wm 3 wm 2 wm 1 wm 0 wm 15 wm 14 wm 13 wm 12 wm 11 wm 10 wm 9 wm 8 figure 19 ram write data mask instruction wm15?0: in w rit i ng to the gram, these bits mask writing in a bit unit. when wm15 = 1, this bit ma sk s th e wr it e data of db15 and does not write to the gram. similarly, the wm14?0 bits mask the wr it e data of db14?0 in a bit unit. when swp = 1, the upper and lower bytes in the write data mask are swapped. for details, see the graphics operation function section. ram address set (r21h) w1 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 ad 10 ad9 ad8 0 0 ad5 ad4 ad3 ad2 ad1 ad0 ad 12 ad 13 ad 14 ad 11 ad 15 figure 20 ram address set instruction ad15?0: initially set gram addresses to the address counter (ac). once the gram data is written, the ac is automatically updated according to the am and i/d bit settings. this allows consecutive accesses without resetting addresses. once the gram data is read, the ac is not automatically updated. gram address setting is not allowed in the standby mode. ensure that the address is set within the specified window address. table 13 gram address range in eight-grayscale mode ad14?ad0 gram setting "0000"h?"003f"h bitmap data for com1 "0100"h?"013f"h bitmap data for com2 "0200"h?"023f"h bitmap data for com3 "0300"h?"033f"h bitmap data for com4 : : "ac00"h?"ac3f"h bitmap data for com173 "ad00"h?"ad3f"h bitmap data for com174 "ae00"h?"ae3f"h bitmap data for com175 "af00"h?"af3f"h bitmap data for com176 hd66763 30 write data to gram (r22h) w1 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 wd 15 wd 14 wd 13 wd 12 wd 11 wd 10 wd 9 wd 8 wd 7 wd 6 wd 5 wd 4 wd 3 wd 2 wd 1 wd 0 figure 21 write data to gram instruction wd15?0 : write 16-bit data to the gram. this data calls each grayscale palette. after a write, the address is automatically updated according to the am and i/d bit settings. during the standby mode, the gram cannot be accessed. wd 15 wd 14 wd 13 wd 12 wd 11 wd 10 wd 9 wd 8 wd 7 wd 6 wd 5 wd 4 wd 3 wd 2 wd 1 wd 0 r2 r1 r0 g2 g1 g0 b1 b0 r2 r1 r0 g2 g1 g0 b1 b0 db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 [eight-grayscale mode] [gram write data] 1 pixel figure 22 gram write data instruction table 14 gram data in the eight-grayscale mode (r grayscale palette) gram data setting r2 r1 r0 hd66763 31 table 15 gram data in the eight-grayscale mode (g grayscale palette) gram data setting g2 g1 g0 hd66763 32 address: n set dummy read (invalid data) gram -> read-data latch read (data of address n) read-data latch -> db15-0 first word second word i ) data read to the microcom p uter ii ) lo g ical o p eration p rocessin g in the hd66763 address: m set dummy read (invalid data) gram -> read-data latch read (data of address) read-data latch -> db15-0 first word second word sets the i/d, am, hsa/hse, and vsa/vea bits address: n set dummy read (invalid data) gram -> read-data latch sets the i/d, am, hsa/hse, and vsa/vea bits read (data of address n) db15-0 -> gram dummy read (invalid data) gram -> read-data latch write (data of address n) db15-0 -> gram automatic address update: n + first word second word first word second word figure 24 gram read sequence hd66763 33 grayscale palette control (r30h to r39h) w1 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 00 00 rk 12 rk 11 rk 10 000 0 rk 02 rk 01 rk 00 w1 00 00 rk 32 rk 31 rk 30 0 000 rk 22 rk 21 rk 20 w1 00 00 rk 52 rk 51 rk 50 0 000 rk 42 rk 41 rk 40 w1 00 00 rk 72 rk 71 rk 70 0 000 rk 62 rk 61 rk 60 r30 r31 r32 r33 w1 00 00 gk 12 gk 11 gk 10 0 000 gk 02 gk 01 gk 00 w1 00 00 gk 32 gk 31 gk 30 0 000 gk 22 gk 21 gk 20 w1 00 00 gk 52 gk 51 gk 50 0 000 gk 42 gk 41 gk 40 w1 00 00 gk 72 gk 71 gk 70 0 000 gk 62 gk 61 gk 60 r34 r35 r36 r37 w1 00 00 bk 12 bk 11 bk 10 0 000 bk 02 bk 01 bk 00 w1 00 00 bk 32 bk 31 bk 30 0 000 bk 22 bk 21 bk 20 r38 r39 rk 13 rk 33 rk 53 rk 73 gk 13 gk 33 gk 53 gk 73 bk 13 bk 33 rk 03 rk 23 rk 43 rk 63 gk 03 gk 23 gk 43 gk 63 bk 03 bk 23 figure 25 grayscale palette control instruction rk73?00: specify the r-grayscale level for eight palettes from the 16-grayscale level. for details, see the grayscale palette and grayscale palette table sections. gk73?00: specify the g-grayscale level for eight palettes from the 16-grayscale level. for details, see the grayscale palette and grayscale palette table sections. bk33?00: specify the b-grayscale level for four palettes from the 16-grayscale level. for details, see the grayscale palette and grayscale palette table sections. hd66763 34 hd66763 35 reset function the hd66763 is internally initialized by reset input. reset the common driver as its settings are not automatically reinitialized when the hd66763 is reset. the reset input must be held for at least 1 ms. do not access the gram or initially set the instructions until the r-c oscillation frequency is stable after power has been supplied (10 ms). instruction set initialization: 1. start oscillation executed 2. driver output control (nl4?0 = 10101, sgs = 0, cms = 0) 3. b-pattern waveform ac drive (b/c = 0, ecr = 0, nw5?0 = 00000) 4. power control 1 (dc2?0 = 000, ap1?0 = 00: lcd power off, stb = 0: standby mode off, slp = 0, bs2-0 = 000, bt2-0 = 000) 5. contrast control (weak contrast (vr3-0 = 0000, ct6?0 = 0000000)) 6. entry mode set (hwm = 0, swp = 0, i/d1-0 = 11: increment by 1, am = 0: horizontal move, lg2?0 = 000: replace mode) 7. compare register (cp7?0: 00000000) 8. display control (vle2?1 = 00: no vertical scroll, spt = 0, rev = 0, d1?0 = 00: display off) 9. com driver interface control (te = 0, idx2-0 = 000) 10. frame cycle control (div1-0 = 00: 1-divided clock, rtn2-0: no retrace line period) 11. power control 2 (vc2-0 = 000) 12. vertical scroll (vl27?20 = 00000000, vl17?10 = 00000000) 13. 1st screen division (se17-10 = 11111111, ss17-10 = 00000000) 14. 2nd screen division (se27-20 = 11111111, ss27-20 = 00000000) 15. horizontal ram address position (hea5-0 = 111111, hsa5-0 = 000000) 16. vertical ram address position (vea7-0 = 10101111, vsa7-0 = 00000000) 17. ram write data mask (wm15?0 = 0000h: no mask) 18. ram address set (ad14?0 = 0000h) 19. grayscale palette (rk03?00 = 0000, rk13?10 = 0011, rk23?20 = 0101, rk33?30 = 0111, rk43?40 = 1001, rk53?50 = 1011, rk63?60 = 1101, rk73?70 = 1111, gk03?00 = 0000, gk13?10 = 0011, gk23?20 = 0101, gk33?30 = 0111, gk43?40 = 1001, gk53?50 = 1011, gk63?60 = 1101, gk73?70 = 1111, bk03?00 = 0000, bk23?20 = 0101, bk43?40 = 1001, bk63?60 = 1111) gram data initialization: this is not automatically initialized by reset input but must be initialized by software while display is off (d1?0 = 00). output pin initialization: 1. lcd driver output pins (seg/com): output gnd level 2. oscillator output pin (osc2): outputs oscillation signal 3. common interface signals (ccs*, ccl, and cda): halt 4. timing signals (cl1, m, flm, disptmg, and dcclk): halt hd66763 36 parallel data transfer 16-bit bus interface setting the im2/1/0 (interface mode) to the gnd/gnd/gnd level allows 68-system e-clock- synchronized 16-bit parallel data transfer. setting the im2/1/0 to the gnd/vcc/gnd level allows 80- system 16-bit parallel data transfer. when the number of buses or the mounting area is limited, use an 8- bit bus interface. csn* a1 hwr* (rd*) d15?d0 cs* rs wr* (rd*) db 15?db0 h8/ 2245 hd66763 16 figure 26 interface to 16-bit microcomputer 8-bit bus interface setting the im2/1/0 (interface mode) to the gnd/gnd/vcc level allows 68-system e-clock-synchronized 8-bit parallel data transfer using pins db15?db8. setting the im1/0 to the vcc/vcc level allows 80- system 8-bit parallel data transfer. the 16-bit instructions and ram data are divided into eight upper/lower bits and the transfer starts from the upper eight bits. fix unused pins db7?db0 to the vcc or gnd level. note that the upper bytes must also be written when the index register is written to. csn* a1 hwr* (rd*) d15?d8 cs* rs wr* (rd*) db 15?db8 db 7?0 h8/2245 hd66763 8 8 gn d figure 27 interface to 8-bit microcomputer note: transfer synchronization function for an 8-bit bus interface the hd66763 supports the transfer synchronization function which resets the upper/lower counter to count upper/lower 8-bit data transfer in the 8-bit bus interface. noise causing transfer mismatch between the eight upper and lower bits can be corrected by a reset triggered by consecutively writing a 00h instruction four times. the next transfer starts from the upper eight bits. executing synchronization function periodically can recover any runaway in the display system. hd66763 37 00 h 0 0 h 00 h 0 0h rs r/ w e db15? db8 upper lower (8-bit tr ansfer synchronization) (1 ) ( 2 ) (3 ) ( 4) up pe r / lo wer figure 28 8-bit transfer synchronization hd66763 38 serial data transfer se tti ng th e im 1 pi n to th e gnd level and the im2 pin to the vcc level allows standard clock- s ynchronized serial data (spi) transfer, using the chip select line (cs*), serial transfer clock line (scl), se ri al i nput data (sdi), and serial output data (sdo). for a serial interface, the im0/id pin function uses an id pin. if the chip is se t up for serial interface, the db15-2 pins which are not used must be fixed at vcc or gnd. th e hd 66763 initiates serial data transfer by transferring the start byte at the fa lli ng edge of cs* input. it ends serial data transfer at the rising edge of cs* input. th e hd 66763 is selected when the 6-bit chip address in the start byte transferred from the transm itting device matches the 6-bit device identification code assigned to the hd66763. the hd66763, when select ed, r ece ives the subseque nt data string. the least significant bit of the identification code can be determined by the id pin. the five upper bits must be 01110. two different chip addresses must be a ssi gned to a single hd66763 because the seventh bit of the start byte is used as a register select bit (rs): that is, when rs = 0, data can be written to the index register or status can be read, and when rs = 1, an instruction ca n be issued or data can be written to or read from ram. read or write is selected according to the eighth bit of the start byte (r/w bit). the data is received when the r/w bit is 0, and is transmitted when the r/w bit is 1. af te r re ce iv i ng the start byte, the hd66763 receives or transmits the subsequent data byte-by-byte. the data is transferred with the msb first. all hd66763 instructions are 16 bits. two bytes are received with the msb first (db15 to 0), then th e instruc tions ar e inte rnally e xec ute d. afte r the star t byte has be en re ce iv ed , th e fi rs t byte is fetched internally as the upper eight bits of the instruction and the second byte is fetched internally as the lower eight bits of the instruction. fi ve bytes of ram read data after the start byte are invalid. the hd66763 starts to read correct ram data from the sixth byte. table 18 start byte format transfer bit s 1 2 3 4 5 6 7 8 start byte format transfer start device id code rs r/w 011 10id note: id bit is selected by the im0/id pin. table 19 rs and r/w bit function rs r/w function 00 sets index register 01 reads status 10 writes instruction or ram data 11 reads instruction or ram data hd66763 39 1 "0" "0" id rs rs rw r/w db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 "1" "1" "1" cs* (input) device id code msb lsb start byte index register setting, instruction, ram data write status read, instruction read, ram data read tr ansfer start tr a n sfer end scl (input) sdi (input) sdo (output) 23 4 5 6 78 910 11 12 13 14 21 22 23 24 15 16 17 18 19 20 a) timing of basic data-transfer through clock-synchronized serial bus interface 12345 6 78 91011121314 21222324 15 16 1718 19 20 31 32 25 26 2728 29 30 cs* (input) scl (input) start byte note: the first byte after the start byte is always the upper eight bits. instruction 1: execution time end start instruction 1: upper eight bits sdi (input) instruction 2: upper eight bits instruction 1: lower eight bits b) timing of consecutive data-transfer through clock-synchronized serial bus interface cs* (input) scl (input) start byte rs = 1, r/w = 1 note: five bytes of the ram read data after the start byte are invalid. the hd66763 starts to read the correct ram data from the sixth byte. sdi (input) dummy read 1 dummy read 2 dummy read 3 dummy read 4 dummy read 5 ram read: upper eight bits ram read: lower eight bits c) ram-data read-transfer timing sdo (output) start end figure 29 procedure for transfer on clock-synchronized serial bus interface hd66763 40 cs* (input) scl (input) start byte rs = 0, r/w = 1 note: one byte of the read data after the start byte are invalid. the hd66763 starts to read the correct data from the second byte. sdi (input) sdo (output) start end dummy read 1 status read: upper eight bits status read: lower eight bits d) status read/instruction read figure 29 procedure for transfer on clock-synchronized serial bus interface (cont) hd66763 41 high-speed burst ram write function th e hd 66763 has a high-speed burst ram-write function that can be used to write data to ram in one- f ourth the access time required for an equivalent standard ram-write operation. this function is espe cially su itable for a pplications which require the high-speed rewriting of the display data, for example, display of color animations, etc. whe n th e hi gh-speed ram-write mode (hwm) is selected, data for writing to ram is once stored to the hd 66763 internal register. when data is selected four times per word, all data is written to the on-chip ram. wh ile this is taking place, the ne xt data can be written to an internal register so that high-speed and consecutive ram writing can be executed for animated displays, etc. microcomputer register 1 "0000"h "0001"h "0002"h "0003"h 16 16 register 2 gram register 3 register 4 address counter (ac) 64 figure 30 flow of operation in high-speed consecutive writing to ram cs* (input) e (input) index (r22h) ram data 1 to 4 "0000"h "0004"h "0008"h "000a"h ram write data (64 bits) ram address (ac15 to 0) index ram data 1 ram data 2 ram data 3 ram data 4 123 412 341234 ram data 5 ram data 6 ram data 7 ram data 8 ram data 9 ram data 10 ram data 11 ram data 12 note: when a high-speed ram write is canceled, the next instruction must only be executed after the ram write execution time has elapsed. ? the lower two bits of the address must be set in the following way in high-speed write mode. when id0 becomes 0, the lower two bits of the address must be set to 11 when id1 becomes 1, the lower two bits of the address must be set to 00. ram write execution time db15-0 (input/output) ram write execution time ram write execution time ram data 5 to 8 ram data 9 to 12 * figure 31 example of the operation of high-speed consecutive writing to ram hd66763 42 when high-speed ram write mode is used, note the following. notes: 1. the logical and compare operations cannot be used. 2. data is wr itten to ram each four words. when an address is set, the lower two bits in the address must be set to the following values. *when id0=0, the lower two bits in the address must be set to 11 and be written to ram. *when id0=1, the lower two bits in the address must be set to 00 and be written to ram. 3. da ta is written to ram each four words. if less than four words of data is written to ram, the last data will not be written to ram. 4. when the index register and ram data write (22h) have been selected, the data is always wr i tte n first. ram cannot be written to and read from at the same time. hwm must be set to 0 while ram is being read. 5. high-speed and normal ram write operations cannot be executed at the same time. the mode must be switched and the address must then be set. 6. when high-speed ram write is used with a window address-range specified, dummy write operation may be required to suit the window address range-specification. refer to the high- speed ram write in the window address section. table 20 comparison between normal and high-speed ram write operations normal ram write (hwm=0) high-speed ram write (hwm=1) logical operation function can be used cannot be used compare operation function can be used cannot be used swap function can be used can be used write mask function can be used can be used ram address set can be specified by word id0 bit=0: set the lower two bits to 11 id0 bit=1: set the lower two bits to 00 ram read can be read by word cannot be used ram write can be written by word dummy write operations may have to be inserted according to a window address-range specification window address can be set by word can be set by word hd66763 43 high-speed ram write in the window address wh en a wi ndow address range is specified, ram data which is in an optional window area can be re wr itten consecutively and quickly by inserting dummy write operations so that ram access c ounts become 4n as shown in the tables below. dummy wr ite operations may have to be inserted as the first or last operations for a row of data, depending on the horizontal window-address range specification bits (hsa1 to 0, hea1 to 0). number of dummy write operations of a row must be 4n. table 21 number of dummy write operations in high-speed ram write (hsa bits) hsa1 hsa0 number of dummy write operations to be inserted at the start of a row 000 011 102 113 table 22 number of dummy write operations in high-speed ram write (hea bits) hea1 hea0 number of dummy write operations to be inserted at the end of a row 003 012 101 110 each row of access must consist of 4 n operations, including the dummy writes. horizontal access count = first dummy write count + write data count + last dummy write count = 4 n hd66763 44 an example of high-speed ram write with a window address-range specified is shown below. th e wi ndow address-range can be rewr itten to consecutively and quickly by inserting two dummy writes at th e st ar t of a row and three dummy writes at the end of a row, as determined by using the window address-range specification bits (hsa1 to 0 = 10, hea1 to 0 = 00). writing in the horizontal direction am = 0, id0 = 1 window address-range setting hsa = h12, hea = h30 vsa = h80, vea = ha0 high-speed ram write mode setting hwm = 1 address set ad = h0810* dummy ram write 2 dummy ram write 3 h0000 gram address map h08012 ha0030 haf3f window address-range specification (rewrite area) window address-range setting hsa = h12, hea = h30 vsa = h80, vea = ha0 note: the address set for the high-speed ram write must be 00 or 11 according to the value of the id0 bit. only ram in the specified window address-range will be overwritten. ram write 31 152 figure 32 example of the high-speed ram write with a window address-range specification hd66763 45 window address function wh en da ta is written to the on-chip gram, a wi ndow address-range which is specified by the horizontal a ddress register (start: hsa5 to 0, end: hea 5 to 0) or the vertical address register (start: vsa7 to 0, end: vea7 to 0) can be written to consecutively. data is wr itten to addresses in the direction specified by the am bit (increment/decrement). when image data, etc. is being written, data can be written consecutively without thinking a data wrap by doing this. th e wi ndow must be specified to be within the gram address area described below. addresses must be set within the window address. [restriction on window address-range settings] ( horizontal direction) 00h hsa5 to 0 hea5 to 0 3fh ( vertical direction) 00h vsa7 to 0 vea7 to 0 afh [restriction on address settings during the window address] (ram address) hsa5 to 0 ad5 to 0 hea5 to 0 vsa7 to 0 ad15 to 8 vea7 to 0 note : in hi gh-speed ram-write mode, the lower two bits of the address must be set as shown below according to the value of the id0 bit. id0 = 0: the lower two bits of the address must be set to 11. id0 = 1: the lower two bits of the address must be set to 00. hd66763 46 gram address map "2010"h "2110"h "202f"h "212f"h ?window address-range specification area hsa5 to 0 = 10h, hse5 to 0 = 2fh vsa7 to 0 = 20h, vea7 to 0 = 5fh i/d = 1 (increment) am = 0 (horizontal writing) "5f2f"h "5f10"h "0000"h "003f"h "af3f"h "af00"h window address area figure 33 example of address operation in the window address specification hd66763 47 graphics operation function th e hd 66763 can greatly reduce the load of the microcomputer graphics software processing through the 16-bit bus architecture and internal graphics-bit operation function. this function supports the following: 1. a swap function that exchanges the upper and lower bytes in the 16-bit data sent from the microcomputer. 2. a write data mask function that selectively rewrites some of the bits in the 16-bit write data. 3. a logical operation write function that writes the data sent from the microcomputer and the original ram data by a logical operation. 4. a conditional write function that compares the or iginal ram data or write data and the compare- bit data and writes the data sent from the microcomputer only when the conditions match. even if the display size is large, the display data in the graphics ram (gram) can be quickly rewritten. the gr a phics bit operation can be controlled by combining the entry mode register, the bit set value of the ram-write-data mask register, and the read/write from the microcomputer. table 23 graphics operation bit setting operation mode i/d am lg2?0 operation and usage write mode 1 0/1 0 000 horizontal data replacement, horizontal-border drawing write mode 2 0/1 1 000 vertical data replacement, vertical-border drawing write mode 3 0/1 0 110 111 conditional horizontal data replacement, horizontal- border drawing write mode 4 0/1 1 110 111 conditional vertical data replacement, vertical-border drawing read/write mode 1 0/1 0 001 010 011 horizontal data write with logical operation, horizontal-border drawing read/write mode 2 0/1 1 001 010 011 vertical data write with logical operation, vertical- border drawing read/write mode 3 0/1 0 100 101 conditional horizontal data replacement, horizontal- border drawing read/write mode 4 0/1 1 100 101 conditional vertical data replacement, vertical-border drawing hd66763 48 read-data latch swap processing logical/compare operation (lg2?0:) write bit mask write-data latch graphics ram (gram) 000: replacement, 001: or, 010: and, 011: eor, 100: replacement with matched read, 101: replacement with unmatched read, 110: replacement with matched write, 111: replacement with unmatched write microcomputer address counter (ac) swap bit (swp) logical operation bit (lg2?0) 3 1 16 16 write-mask register (wm15?0) 16 15 +1/-1 +256 16 16 16 compare bit (cp7?0) 8 16 figure 34 data processing flow of the graphics operation hd66763 49 swap function th e hd 66763 has a byte-wise swap function that exchanges the upper and lower bytes in the two-byte data sent from the microcomputer. when swp = 0, the da t a wr itten by the microcomputer is directly transferred to the inside. when swp = 1, the data written by the microcomputer is internally transferred by exchanging the upper and lower bytes. db15 r 02 r 01 r 00 g 02 g 01 g 00 b 02 b 01 db8 r 12 r 11 r 10 g 12 g 11 g 10 b 12 b 11 db7 db0 upper byte lower byte i) swp = "0": db15 r 02 r 01 r 00 g 02 g 01 g 00 b 02 b 01 db8 r 12 r 11 r 10 g 12 g 11 g 10 b 12 b 11 db7 db0 upper byte lower byte ii) swp = "1": db15 r 02 r 01 r 00 g 02 g 01 g 00 b 02 b 01 db8 r 12 r 11 r 10 g 12 g 11 g 10 b 12 b 11 db7 db0 upper byte lower byte data written by the microcomputer lower byte (db7?) upper byte (db15?) upper byte lower byte r 0 g 0 b 0 r 1 g 1 b 1 upper byte lower byte r 0 g 0 b 0 r 1 g 1 b 1 gram data lcd display upper byte (db15?) lower byte (db7?) figure 35 example of swap function operation hd66763 50 write-data mask function th e hd 66763 has a bit-wise write-data mask function that controls writing the two-byte data from the mic ro co m puter to the gram. bits that are 0 in the write-data mask register (wm15?0) cause the co rr es ponding db bit to be written to the gram. bits that are 1 prevent writing to the corresponding gram bit to the gra m ; t he da ta in the gram is retained. this f unction can be used when only one- pixel data is rewritten or the particular display color is selectively rewritten. db15 db8 db7 db0 upper byte lower byte write-data mask wm15 wm8 wm7 wm0 i) swp = "0": db15 r 02 r 01 r 00 g 02 g 01 g 00 b 02 b 01 db8 db7 db0 upper byte lower byte ii) swp = "1": db15 r 02 r 01 r 00 g 02 g 01 g 00 b 02 b 01 db8 r 12 r 11 r 10 g 12 g 11 g 10 b 12 b 11 db7 db0 upper byte lower byte 000 1 1 100 i) gram data (swp = "0"): db15 * * * * * * * * db8 r 12 r 11 r 10 * * * b 12 b 11 db7 db0 upper byte lower byte ii) gram data (swp = "1"): db15 * * * db8 * * * * db7 db0 upper byte lower byte data written by the microcomputer r 02 r 01 r 00 g 02 g 01 g 00 b 02 b 01 r 12 r 11 r 10 g 12 g 11 g 10 b 12 b 11 r 12 r 11 r 10 g 12 g 11 g 10 b 12 b 11 1 1 1 1 1 1 1 1 r 12 r r 11 10 b 12 b 11 * * ** * figure 36 example of write-data mask function operation hd66763 51 logical/compare operation function th e hd 66763 performs a logical operation or conditional replacement between the two-byte write data sent from the microcomputer a nd the read data from the gram. the logical operation function has four t ypes: replacement, or, and, and eor. the conditional replacement performs a compare operation for th e se t value of the compare register (cp7?0) and the read data value from the gram, and rewrites only the pixel data in the gram that satisfies the conditi ons (in a byte unit). this function can be used when a par tic ular color is selectively rewritten. the swap function or write-data mask function can be effectively used. table 24 logical/compare operation bit setting lg2 lg1 lg0 description of logical/compare operation function 000 writes the data written from the microcomputer directly to the gram. only write processing is performed since the data in the read-data latch is not used. 001 ors the data in the read-data latch and the data written by the microcomputer. writes the result to gram. read, modify, or write processing is performed. 010 ands the data in the read-data latch and the data written by the microcomputer. writes the result to gram. 011 eors the data in the read-data latch and the data written by the microcomputer. writes the result to gram. 100 compares the data in the read-data latch and the set value of the compare register (cp7?0). when the read data matches cp7?0, the data from the microcomputer is written to the gram. only the particular color specified in the compare register can be rewritten. read, modify, or write processing is performed. 101 compares the data in the read-data latch and the set value of the compare register (cp7?0). when the read data does not match cp7?0, the data from the microcomputer is written to the gram. colors other than the particular one specified in the compare register can be rewritten. read, modify, or write processing is performed. 110 compares the data written to the gram by the microcomputer and the set value of the compare register (cp7?0). when the write data matches cp7?0, the data from the microcomputer is written to the gram. only write processing is performed. 111 compares the data written to the gram by the microcomputer and the set value of the compare register (cp7?0). when the write data does not match cp7?0, the data from the microcomputer is written to the gram. only write processing is performed. hd66763 52 graphics operation processing 1. write mode 1: am = 0, lg2?0 = 000 th is mode is used when the data is horizontally written at high speed. it can also be used to initialize the gr a phics ram (gram) or to draw borders. the swap function (swp) and write-data mask f unction (wm15?0) are also enabled in these operations. after writing, the address counter (ac) auto matically increments by 1 (i/d = 1) or decrements by 1 (i/d = 0), and automatically jumps to the counter edge one-raster-row below after it has reached the left or right edge of the gram. wm15 wm0 operation examples: 1) i/d = "1", am = "0", lg2-0 = "000", swp = "0" 2) wm15? = "1f1f"h 3) ac = "0000"h write-data mask: 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 db15 db0 write data (1): 1 0 0 1 1 0 0 1 0 1 0 0 0 0 1 1 write data (2): 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 1 0 0 * * * * * 0 1 0 * * * * * 1 1 0 * * * * * 0 0 0 * * * * * "0000"h "0001"h "0002"h write data (1) write data (2) gram *write mask for plain g and b. note: the bits in the gram indicated by '*' are not changed. figure 37 writing operation of write mode 1 hd66763 53 2. write mode 2: am = 1, lg2?0 = 000 this mode is used when the data is vertically written at high speed. it can also be used to initialize the gr am, de velop the font pattern in the vertical direction, or draw borders. the swap function (s wp ) a nd write-data mask function (wm15?0) are also enabled in these operations. after writing, th e a ddress counter (ac) automatically increments by 256, and automatically jumps to the upper-right e dge (i/d = 1) or upper-left edge (i/d = 0) following the i/d bit after it has reached the lower edge of the gram. wm15 wm0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 db15 db0 1 0 0 1 1 0 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 0 1 1 1 1 1 "0000"h gram swap "0100"h "0200"h * * * * * * * * * * * * swap swap 10 0 110 0 1 0 100 00 1 1 11 00 00 1 1 00 00 1 100 01 11 0 10 0 0 0 0 1 1 1 1 1 * * * * * * * * * * * * operation examples: 1) i/d = "1", am = "1", lg2-0 = "000", swp = "1" 2) wm15?0 = "00ff"h 3) ac = "0000"h write-data mask: write data (1): write data (2): write data (3): write data (1) write data (2) write data (3) notes: 1. the bit area data in the gram indicated by '*' is not changed. 2. after writing to address 4f00h, the ac jumps to 0001h. 111 1 00 00 1 1 1 1 0000 11 11 0 00 0 figure 38 writing operation of write mode 2 hd66763 54 3. write mode 3: am = 0, lg2?0 = 110/111 this mode is used when the data is horizontally written by comparing the write data and the set value of the compare register (cp7?0). when the result of the comparison in a byte unit satisfies the c ond ition, the write data sent from the microcomputer is written to the gram. in this operation, the sw ap f unction (swp) and write-data mask function (wm15?0) are also enabled. after wr iting, the a ddress counter (ac) automatically increments by 1 (i/d = 1) or decrements by 1 (i/d = 0), and au to ma tic al ly ju mp s to th e c ounter edge one-raster-row below after it has reached the left or right edge of the gram. wm15 wm0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 db15 db0 "0000"h "0001"h "0002"h gram 1 0 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 1 1 0 * 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 * compare operation compare operation compare operation matched replacement of write data (1) cp7 cp0 compare register: 0 1 0 1 0 0 1 1 replacement conditional replacement conditional replacement c c c r r r * (matched) (matched) matched replacement of write data (3) ******* *************** conditional replacement ******* replacement * 0 1 0 1 0 0 1 1 ******* * *************** 0 1 0 1 0 0 1 1 * ** ** ** * operation examples: 1) i/d = "1", am = "0", lg2-0 = "110" (matched write), swp = "0" 2) cp7?0 = 53h 3) wm15?0 = "0000"h 4) ac = "0000"h write-data mask: write data (1): write data (2): write data (3): figure 39 writing operation of write mode 3 hd66763 55 4. write mode 4: am = 1, lg2?0 = 110/111 this m ode is used when a vertical comparison is performed between the write data and the set value of the compare register (cp7?0) to write the data. when the result by the comparison in a byte unit sa tis fi es th e c ondition, the write data sent from the microcomputer is written to the gram. in this operation, the swap function (swp) and write-data mask function (wm15?0) are also enabled. after wr i ti ng, the address counter (ac) automatically increments by 256, and automatically jumps to the upper-right edge (i/d = 1) or upper-left edge (i/d = 0) following the i/d bit after it has reached the lower edge of the gram. wm15 wm0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 db15 db0 1 0 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 1 1 0 cp7 cp0 0 1 0 1 0 0 1 1 c c c r r r (unmatched) (unmatched) (unmatched) (unmatched) 1 0 0 1 1 0 0 1 * 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 * "0000"h write data (1) gram "0080"h "0100"h write data (2) write data (3) "4f00"h "0000"h "0001"h ******* ******* 1 0 0 1 1 0 0 1 * 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 * ******* ******* compare register: operation examples: 1) i/d = "1", am = "1", lg2-0 = "111" (unmatched write), swp = "0" 2) cp7?0 = 53h 3) wm15?0 = "0000"h 4) ac = "0000"h write-data mask: write data (1): write data (2): write data (3): compare operation compare operation compare operation conditional replacement conditional replacement conditional replacement notes: 1. the bits in the gram indicated by '*' are not changed. 2. after writing to address 4f00h, the ac jumps to 0001h. figure 40 writing operation of write mode 4 hd66763 56 5. read/write mode 1: am = 0, lg2?0 = 001/010/011 this m ode is used when the data is horizontally written at high speed by performing a logical operation with the original data. it reads the display data (original data), which has already been wri tten in the gram, performs a logical operation with the w ri t e data se nt from the microcomputer, a nd rewrites the data to the gram. this mode reads the data during the same access-pulse width ( 68-system: enabled high level, 80-system: rd* low level) as the write operation since reading the original data does not latch the re ad data in to the microcomputer but temporarily holds it in the read- data latch. however, the bus cycle requires the same time as the read operation. the swap function (s wp ) or write-data mask function (wm15?0) are also enabled in these operations. after writing, the a ddress counter (ac) automatically increments by 1 (i/d = 1) or decrements by 1 (i/d = 0), and au to ma tic al ly ju mp s to th e c ounter edge one-raster-row below after it has reached the left or right edges of the gram. wm15 wm0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 db15 db0 write data (1): 1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 1 write data (2): 1 1 0 0 0 0 1 1 1 0 0 0 1 1 0 0 write data (3): 0 1 1 1 0 1 0 0 0 0 0 1 1 1 1 1 "0000"h "0001"h "0002"h read data (1) + write data (1) gram read data (1): 1 0 0 1 1 0 0 1 0 1 0 0 0 0 1 1 read data (2): 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 read data (3): 0 0 0 0 1 1 1 0 1 0 0 0 0 1 1 0 1 0 1 1 1 1 0 1 0 1 1 0 0 0 1 1 1 1 0 0 1 1 1 1 1 0 0 0 1 1 0 0 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 logical operation (or) logical operation (or) logical operation (or) 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 1 1 1 0 1 0 1 1 0 0 0 1 1 read data (2) + write data (2) read data (3) + write data (3) operation examples: 1) i/d = "1", am = "0", lg2-0 = "001" (or), swp = "0" 2) wm15? = "0000"h 3) ac = "0000"h write-data mask: figure 41 writing operation of read/write mode 1 hd66763 57 6. read/write mode 2: am = 1, lg1?0 = 001/010/011 this mode is used when the data is vertically wr itten at hi gh speed by performing a logical operation w ith the original data. it reads the display data (original data), which has already been written in the gram, performs a l ogical operation with the write data sent from the microcomputer, and rewrites the data to the gram. this mode can read the data during the same access-pulse width (68-system: ena bled high level, 80-system: rd* low level) as for the write operation since the read operation of the original data does not latch the read data into the microcom puter and temporarily holds it in the re ad -d at a la tch. however, the bus cycle requires the same time as the read operation. the swap f unction (swp) or write-data mask function (wm15?0) are also enabled in these operations. after wr i ti ng, the address counter (ac) automatically increments by 256, and automatically jumps to the upper-right edge (i/d = 1) or upper-left edge (i/d = 0) following the i/d bit after it has reached the lower edge of the gram. wm15 wm0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 db15 db0 1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 0 1 1 1 1 1 1 0 0 0 1 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 1 1 1 0 0 1 1 0 "0000"h gram "0080"h "0100"h * * swap swap swap 0 1 0 0 111111100 1 1 1 0 1 1 1 111 000 111 1 0 0 1 1 1 1 11 11 10 11 0 0 0 0 "4f00"h 1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 0 1 1 1 1 1 * * * * * * 1 1 1 1 1 0 0 1 1 0 0 0 1 1 1 1 1 1 1 0 1 0 "0000"h "0001"h write data (1): write data (2): write data (3): read data (1) + write data (1) read data (1): read data (2): read data (3): logical operation (or) read data (2) + write data (2) read data (3) + write data (3) operation examples: 1) i/d = "1", am = "1", lg2-0 = "001" (or), swp = "1" 2) wm15?0 = "ff00"h 3) ac = "0000"h write-data mask: logical operation (or) logical operation (or) notes: 1. the bits in the gram indicated by '*' are not changed. 2. after writing to address 4f00h, the ac jumps to 0001h. * 0 * * * * * * * * * * * * ** * * * 0 *** * * * * * figure 42 writing operation of read/write mode 2 hd66763 58 7. read/write mode 3: am = 0, lg2?0 = 100/101 this mode is used when the data is horizontally written by comparing the original data and the set value of compare register (cp7?0). it reads the display data (original data), which has already been wri tten in the gram, compares the original data and the set value of the compare register in byte units, and writes the data sent from the microcomputer to the gram only when the result of the compa r ison satisfies the condition. this mode reads the data during the same access-pulse width (68- system: enab led high level, 80-system: rd* low level) as write operation since reading the original data does not latch the read data into the microcomputer but temporarily holds it in the read-data latch. however, th e bus cycle requires the same time as the read operation. the swap function (s wp ) a nd write-data mask function (wm15?0) are also enabled in these operations. after writing, th e a ddress counter (ac) automatically increments by 1 (i/d = 1) or decrements by 1 (i/d = 0), and au to ma tic al ly ju mp s to th e c ounter edge one-raster-row below after it has reached the left or right edges of the gram. wm15 wm0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 db15 db0 1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 0 0 1 1 1 1 0 1 0 0 0 0 0 1 1 1 1 1 "0000"h "0001"h "0002"h gram 1 0 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 0 0 0 1 1 0 compare operation compare operation compare operation matched replacement of write data (1) cp7 cp0 compare register: 0 1 0 1 0 0 1 1 conditional replacement conditional replacement conditional replacement c c c r r r 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 (matched) (matched) 1 0 0 1 1 0 0 1 0 1 1 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 0 1 0 0 0 0 1 1 0 matched replacement of write data (3) write data (1): write data (2): write data (3): read data (1): read data (2): read data (3): operation examples: 1) i/d = "1", am = "0", lg2-0 = "100" (matched write), swp = "0" 2) cp7?0 = "53h" 3) wm15?0 = "0000"h 4) ac = "0000"h write-data mask: figure 43 writing operation of read/write mode 3 hd66763 59 8. read/write mode 4: am = 1, lg2?0 = 100/101 this mode is used when the data is vertically written by comparing the original data and the set value of the compare register (cp7?0). it reads the display data (original data), which has already been wri tten in the gram, compares the original data and the set value of the compare register in byte units, and writes the data sent from the microcomputer to the gram only when the result of the compa re oper ati on satisfies the condition. this mode reads the data during the same access-pulse widt h (68-system: enabled high level, 80-system: rd* low level) as the write operation since reading the original data does not latch the read data into the microc omputer but temporarily holds it in the re ad -d at a la tch. however, the bus cycle requires the same time as the read operation. the swap f unction (swp) and write-data mask function (wm15?0) are also enabled in these operations. after wr i ti ng, the address counter (ac) automatically increments by 256, and automatically jumps to the upper-right edge (i/d = 1) or upper-left edge (i/d = 0) following the i/d bit after it has reached the lower edge of the gram. notes: 1. the bits in the gram indicated by '*' are not changed. 2. after writing to address 4f00h, the ac jumps to 0001h. wm15 wm0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 db15 db0 1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 0 0 1 1 1 1 0 1 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 1 1 0 cp7 cp0 0 1 0 1 0 0 1 1 c c c r r r (unmatched) (unmatched) (unmatched) (unmatched) 1 0 1 1 1 1 0 0 0 1 0 1 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 1 "0000"h write data (1) gram "0080"h "0100"h write data (2) write data (3) "4f00"h "0000"h "0001"h 1 0 1 1 1 1 0 0 0 1 0 1 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 1 compare operation compare operation compare operation compare register: conditional replacement conditional replacement conditional replacement write data (1): write data (2): write data (3): read data (1): read data (2): read data (3): operation examples: 1) i/d = "1", am = "1", lg2-0 = "101" (unmatched write), swp = "0" 2) cp7?0 = "53h" 3) wm15?0 = "0000"h 4) ac = "0000"h write-data mask: figure 44 writing operation of read/write mode 4 hd66763 60 grayscale palette the hd66763 incorporates a grayscale palette to simultaneously display 256 of the 4,096 possible colors. the r and g grayscales consist of eight four-bit palettes, and the b grayscale consists of four four-bit palettes. the 16-stage grayscale levels can be selected from the four-bit palette data. for the display data of r and g, the three-bit data in the gram written from the microcomputer is used. for the display data of b, the two-bit data in the gram is used. in this palette, a pulse-width control system (pwm) is used to eliminate flicker in the lcd display. the time over which the lcds are switched on is adjusted according to the level and grayscales are displayed so that flicker is reduced and grayscales are clearly displayed. hd66763 61 r 2 r 1 r 0 g 2 g 1 g 0 b 1 b 0 display data msb lsb graphics ram (gram) rk 02 rk 01 rk 00 rk 12 rk 11 rk 10 rk 22 rk 21 rk 20 rk 72 rk 71 rk 70 "000" "001" "010" "111" palette r gk 02 gk 01 gk 00 gk 12 gk 11 gk 10 gk 22 gk 21 gk 20 gk 72 gk 71 gk 70 "000" "001" "010" "111" palette g bk 02 bk 01 bk 00 bk 12 bk 11 bk 10 bk 22 bk 21 bk 20 "00" "01" "10" "11" palette b 3 3 2 16-grayscale control hd66763 62 grayscale palette table the grayscale register that is set for each palette register (rk, gk, or bk) can be set to any level. 16- grayscale lighting levels can be set according to palette values (0000 to 1111). table 25 grayscale control level palette register value (rk, gk, or bk) grayscale control level 0000 unlit level *1 0001 2/16 level 0010 3/16 level 0011 4/16 level 0100 5/16 level 0101 6/16 level 0110 7/16 level 0111 8/16 level 1000 9/16 level 1001 10/16 level 1010 11/16 level 1011 12/16 level 1100 13/16 level 1101 14/16 level 1110 15/16 level 1111 all-lit level *2 notes: 1. the unlit level corresponds to a black display when a normally-black color-lcd panel is used, and a white display when a normally-white color-lcd panel is used. 2. the all-lit level corresponds to a white display when a normally-black color-lcd panel is used, and a black display when a normally-white color-lcd panel is used. hd66763 63 common driver interface th e hd 66763 and the hd66764 common driver can drive displays of up to 128 (rgb) 176 dots in si ze . si gna ls to set instructions for cr oscillation, the display timing signal, and the common driver are s upplied from the hd66763 to the common driver. the lcd drive voltage is generated by the common driver. the lcd segment drive leve l (vsh) is also supplied from the common driver. on/off control of the display is re quired to be controlled by both the common and segment driver. follow the on/off sequence of the display. seg1 to 384 (segment driver) osc1 note: the oscillation resistance (rf) must be located near the master chip. osc2 vsh cl1 flm m disptmg dcclk ccs* ccl cda vsh cl1 flm m disptmg dcclk ccs* ccl cda rf hd66763 com1 to 176 (common driver) hd66764 figure 46 connection to the common driver hd66763 64 common driver serial transfer th e hd 66763 has an on-chip serial circuit to interface with the common driver (hd66764). registers of th e co mm on driver can be set by transferring register settings from the hd66763. the serial interface consists of the seria l chip se lec t (ccs*), se rial tr ansfe r clock (ccl) , and seria l transf er data (cda ) lines. th e hd 66763 serial interface circuit is only for transm itting, and ca nnot be used for receiving data from the common driver. se ri al tr an sf er is st ar te d by setting the serial transfer register (te) in the hd66763 to 1. after te has been set to 1, cda will be output in synchronization with ccs*, ccl, and ccl. transfer is in 16-bit blocks. the data transferred consists of a common driver index register (idx2 to 0) and an instruction for a re giste r se lecte d by idx2 to 0. for more inf orm at i on on the common driver indices and instructions, re fe r to th e co mm on-driver data sheet. serial transfer is independent of the hd66763 s in ternal operation, so ot her instructions can be executed during transfer. serial transfer to the common driver requires a maximum of 18 clock cycles. whe n th e serial transfer is fini shed, te is au tomatically cleared to 0. after reading the register to confirm that te=0, serial transfer of the next instruction may be started. mpu hd66763 cs* wr* rd* ccs* ccl cda ccs* ccl cda rs db15-0 16 hd66764 a) example of interface with common driver hd66764 1 idx2 idx1 idx0 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 ccs* (output) msb lsb index instruction data tr ansfer start tr ansfer end cda (output) ccl (output) 2345 6789 10 11 12 13 14 15 16 b) basic serial transfer figure 47 common driver serial transfer hd66763 65 instruction setting change index set r0ah instruction read specify the idx2 to 0 in the common side instruction including a changed instruction bit common side index (idx2 to 0) te = 1 (transfer start) te = "0" no (during transfer) yes (transfer can be executed) tr ansfer to the common driver must be executed immediately after setting up the instruction change the instruction bit setting corresponding to the hd66763 c) serial transfer sequence figure 47 common driver serial transfer (cont) notes: 1. transfer to the common driver must take place immediately after setting up the instruction. 2. the serial transfer period takes a maximum of 1/fosc 18 clock cycles (sec). 3. serial transfer cannot be executed in standby mode. if the chip enters standby mode during transfer, the serial transfer is forcibly susp e nded. transfer must be executed again after standby has been canceled because correct transfer is not guaranteed in this situation. 4. serial transfer can be forcibly suspended by writing te=0. transfer must be executed again because correct transfer is not guaranteed in this situation. 5. the instruction bit for the common driver is not executed when it is not transferred to the common driver. when the setting is changed, transfer must be executed again. whe n tr ansfer to the common driver is executed, the tr ansfe r is ex ecuted by using one of the following common driver (hd66764) instructions, corresponding to the value set by the idx2 to 0. hd66763 66 table 26 common driver (hd66764) instructions 00 bs2 bs1 bs0 bt3 bt2 bt1 bt0 dc2 dc1 dc0 ap1 ap0 slp idx1 idx2 idx0 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 01 00 000 00000 vc2 vc1 vc0 10 0 vr3 vr2 vr1 vr0 0 ct6 ct5 ct4 ct3 ct2 ct1 ct0 11 00 d1 cms spt ss17 ss16 ss15 ss14 ss13 ss12 ss11 ss10 00 00 000 se17 se16 se15 se14 se13 se12 se11 se10 01 00 000 ss27 ss26 ss25 ss24 ss23 ss22 ss21 ss20 10 00 000 se27 se26 se25 se24 se23 se22 se21 se20 0 0 0 0 1 1 1 hd66763 67 instruction setting flow wh en th e co mm on driver hd66764 is used, follow the below about each instruction setting. the instruction setting for the common driver is executed by the serial interface. when the instruction for the comm on driver is se t, the serial transfer must be executed to the common driver. the transfer to the common driver must be executed immediately after the instruction set. follow the below serial transfer flow about each setting and then transfer must be executed. [display on/off] [duty setting] [partial setting] po w er off (ap1 to 0 = 00) po w er setting pa r tial setting duty setting, etc. display off (d1 to 0 = 00) serial transfer serial transfer serial transfer serial transfer display on (d1 to 0 = 10) display on (d1 to 0 = 11) w ait at least one frame note: for more information on the flow for power settings, refer to the common-driver data sheet. [standby] display off flow oscillation start standby cancel (stb = "0") standby set (stb = "1") w ait 10 ms display on flow po w er setting [sleep] display off flow serial transfer serial transfer sleep set (slp = "1") sleep cancel (slp = "0") display on flow po w er setting flow display off display on standby set standby cancel sleep set sleep cancel figure 48 instruction setting flow hd66763 68 oscillation circuit the hd66763 can oscillate between the osc1 and osc2 pins using an internal r-c oscillator with an external oscillation resistor. note that in r-c oscillation, the oscillation frequency is changed according to the external resistance value, wiring length, or operating power-supply voltage. if rf is increased or power supply voltage is decrease, the oscillation frequency decreases. for the relationship between rf resistor value and oscillation frequency, see the electric characteristics notes section. clock (200 khz) osc1 osc2 hd66763 damping resistance (2 k ? ) 1) external clock mode rf osc1 osc2 hd66763 note: the rf resistance must be located near the osc1/osc2 pin on the master side. 2) external resistance oscillation mode figure 49 oscillation circuits wh en using the hd66763 with the hd66764 common driver, the relationship between the seg and com output levels is as shown in the following figure. the lcd drive level (vsh, vsl) which is used by the hd66763 is supplied from the hd66764 common driver. while the display is off, seg and com outputs go to gnd level. m vch lit lit lit no lit no lit no lit seg waveform vsh vm vsl (gnd) vcl com waveform figure 50 relationship with seg/com output level hd66763 69 frame-frequency adjustment function th e hd 66763 has an on-chip frame-frequency adjustment function. the frame frequency can be adjusted by the instruction setting (div, rtn) during the lcd drive as the oscillation frequency is always same. when the display duty is changed, the frame frequency can be adjusted to be the same. if the oscillation frequency is set to high, an animation or a static image can be displayed in suitable ways by changing the frame frequency. when a static image is displayed, the frame frequency can be set low a nd the low-power consumption mode can be entered. when high-speed screen switching, for an animated display, etc. is required, the frame frequency can be set high. relationship between lcd drive duty and frame frequency the rela ti onship between the lcd drive duty and the frame frequency is calculated by the following e xpression. the frame frequency can be adjusted in the retrace-line period bit (rtn) and in the operation clock division bit (div) by the instruction. (formula for the frame frequency) fosc frame frequency = [hz] clock cycles per raster-row division ratio 1/duty cycle fosc: r-c oscillation frequency duty: drive duty (nl bit) division ratio: div bit clock cycles per raster-row: (rtn + 17) clock cycles hd66763 70 example calculation 1 to set the maximum frame frequency to 60 hz display duty: 1/168 retrace-line period: 0 clock (rtn3 to 0 = 0000) operation clock division ratio: 1 division fosc = 60 hz (0 + 17) clock 1 division 168 lines = 171 (khz) in th is ca se , th e cr oscillation frequency becomes 171 khz. the external resistance value of the cr os c illator must be adjusted to be 171 khz. the display duty can be changed by the partial display, etc. and the frame frequency can be the same by setting the rnt bit and div bit to achieve the following. partial display display duty: 1/40 retrace-line period: 1 clock (rtn3 to 0 = 0001) operation clock division ratio: 4 division frame frequency = 171 khz/ ((1 + 17) clock 4 division 40 lines) = 59.3 (hz) example calculation 2 switching the frame frequency to suit animation/static image display (animation display) frame frequency: 120 hz display duty: 1/168 retrace-line period: 0 clock (rtn3 to 0 = 0000) operation clock division ratio: 1 division fosc = 120 hz (0 + 17) clock 1 division 168 lines = 342 (khz) (static image display) frame frequency: 60 hz display duty: 1/168 retrace-line period: 0 clock (rtn3 to 0 = 0000) operation clock division ratio: 1 division frame frequency: 342 khz/ ((0 + 17) clock 2 division 168 lines) = 59.8 (hz) hd66763 71 n-raster-row reversed ac drive the hd66763 supports not only the lcd reversed ac drive in a one-frame unit (b-pattern waveform) but also the n-raster-row reversed ac drive which alternates in an n-raster-row unit from one to 64 raster- rows (c-pattern waveform). when a problem affecting display quality occurs, such as crosstalk at high- duty driving of more than 1/64 duty, the n-raster-row reversed ac drive (c-pattern waveform) can improve the quality. determine the number of raster-rows n (nw bit set value + 1) for alternating after confirmation of the display quality with the actual lcd panel. however, if the number of ac raster-rows is reduced, the lcd alternating frequency becomes high. because of this, the charge or discharge current is increased in the lcd cells. 12 3 4 5678910111213 79801234 5 678910111 213 7980 1 2 3 b-pat t ern wa veform drive ? 1/80 duty 1 fr ame 1 frame c- pat tern wav eform drive ? 1 /80 duty ? 11-raster-row r evers al ? with out eors c- pat tern wav eform drive ? 1/ 80 duty ? 11-rast er-row r eversal ? wi th eors not e: specify t he numb er of ac drive rast er-rows and the necess ity of e or so t hat the dc bias is not generated f the liquid crys tal. figure 51 example of an ac signal under n-raster-row reversed ac drive hd66763 72 screen-division driving function th e hd 66763 can select and drive two screens at any position with the screen-driving position registers (r 14h and r15h). any two screens required for display are selectively driven and a duty ratio is lowered by lcd-driving duty setting (nl4-0), thus reducing lcd-driving voltage and power consumption. for the 1s t di vision screen, start line (ss17-10) and end line (se17-10) are specified by the 1st screen- driving position register (r14h). for the 2nd division screen, start line (ss27-20) and end line (se27-20) ar e sp eci fi ed by the 2nd screen-driving position register (r15h). the 2nd screen control is effective when th e sp t bit is 1. the total count of selection-driving lines for the 1st and 2nd screens must correspond to the lcd-driving duty set value. 1st screen : 7 raster-row driving 2nd screen : 17 raster-row driving 1/24 duty driving on 2 screen - driving duty : nl4-0 = "00010" (1/24 duty) - 1st screen setting : ss17-10 = "00"h, se17-10 = "06"h - 2nd screen setting : ss27-20 = "19"h, se27-20 = "29"h, spt = "1" com1 com17 always applying non-selection level always applying non-selection level com26 com42 figure 52 display example in 2-screen division driving hd66763 73 restrictions on the 1st/2nd screen driving position register settings the following restrictions must be satisfied when setting the start line (ss17-10) and end line (se17-10) of the 1st screen driving position register (r14) and the start line (ss27-20) and end line (se27-20) of the 2nd screen driving position register (r15) for the hd66763. note that incorrect display may occur if the restrictions are not satisfied. table 27 restrictions on the 1st/2nd screen driving position register settings 1st screen driving (spt = 0) 2nd screen driving (spt = 1) register setting ss17-10 se17-0 afh ss17-10 se17-10 < ss27-20 se27-20 afh display operation ? time-sharing driving for com pins (ss1+1) to (se1+1) ? non-selection level driving for others ? time-sharing driving for com pins (ss1+1) to (se1+1) and (ss2+1) to (se2+1) ? non-selection level driving for others notes: 1. when the total line count in screen division driving settings is less than the duty setting, non- selection level driving is performed without the screen division driving setting range. 2. when the total line count in screen division driving settings is larger than the duty setting, the start line, the duty-setting line, and the lines between them are displayed and non-selection level driving is performed for other lines. 3. for the 1st screen driving, the ss27-20 and se27-20 settings are ignored. hd66763 74 absolute maximum ratings item symbol unit value notes* power supply voltage (1) v cc v ?0.3 to +4.6 1, 2 power supply voltage (2) v sh ? gnd v ?0.3 to +4.6 1, 3 input voltage vt v ?0.3 to v cc + 0.3 1 operating temperature topr c ?40 to +85 1, 4 storage temperature tstg c ?55 to +110 1, 5 notes: 1. if the lsi is used above these absolute maximum ratings, it may become permanently damaged. using the lsi within the following electrical characteristics limits is strongly recommended for normal operation. if these electrical characteristic conditions are also exceeded, the lsi will malfunction and cause poor reliability. 2. vcc > gnd must be maintained. 3. vsh > gnd must be maintained. 4. for die and wafer products, specified up to 85 ? c. 5. this temperature specifications apply to the tcp package. hd66763 75 dc characteristics (v cc = 1.8 to 3.6 v, ta = ?40 to +85c* 1 ) item symbol min typ max unit test condition notes input high voltage v ih 0.7 v cc ?v cc vv cc = 1.8 to 3.6 v 2, 3 input low voltage v il ?0.3 ? 0.15 v cc vv cc = 1.8 to 3.6 v 2, 3 output high voltage (1) (db0-15 pins) v oh1 0.75 v cc ??vi oh = ?0.1 ma 2 output low voltage (1) (db0-15 pins) v ol1 ?? 0.2 v cc vv cc = 1.8 to 2.4 v, i ol = 0.1 ma 2 ?? 0.15 v cc vv cc = 2.4 to 3.6 v, i ol = 0.1 ma 2 driver on resistance (seg pins) r seg ? 0.35 3 k ? id = 0.05 ma, v sh = 3 v 4 i/o leakage current i li ?1 ? 1 a vin = 0 to v cc 5 current consumption during normal operation (v cc ? gnd) i op ? 140 200 a r-c oscillation, v cc = 3.0v, ta = 25 c, f osc = 180 khz (1/176 duty) writing to ram: checker 6, 7 current consumption during standby mode (v cc ? gnd) i st ? 0.1 5 a v cc = 3.0 v, ta = 25c 6, 7 lcd drive power supply current (v sh ? gnd) i lcd ?406 0av cc = 3 v, v lcd = 4 v, r-c oscillation; f osc = 180 khz (1/176 duty), ta = 25 c, writing to ram: checker 7 lcd drive voltage (v sh ? gnd) v lcd 2.0 ? 4.0 v 8 note: for the numbered notes, refer to the electrical characteristics notes section following these tables. hd66763 76 ac characteristics (v cc = 1.8 to 3.6 v, ta = ?40 to +85c* 1 ) clock characteristics (v cc = 1.8 to 3.6 v) item symbol min typ max unit test condition notes external clock frequency fcp 140 210 315 khz v cc = 1.8 to 3.6 v 9 external clock duty ratio duty 45 50 55 % v cc = 1.8 to 3.6 v 9 external clock rise time trcp ? ? 0.2 s v cc = 1.8 to 3.6 v 9 external clock fall time tfcp ? ? 0.2 s v cc = 1.8 to 3.6 v 9 r-c oscillation clock f osc 168 210 252 khz rf = 220 k ? , v cc = 3 v 10 note: for the numbered notes, refer to the electrical characteristics notes section following these tables. hd66763 77 68-system bus interface timing characteristics hd66763 78 hd66763 79 80-system bus interface timing characteristics hd66763 80 hd66763 81 clock synchronized serial interface timing characteristics ( vcc = 1.8 to 2.4 v) item symbol min typ max unit test condition serial clock cycle time at write (receive) t scyc 0.1 ? 20 us figure 60 at read (send) t scyc 0.25 ? 20 us figure 60 serial clock high-level pulse width at write (receive) t sch 40 ? ? ns figure 60 at read (send) t sch 120 ? ? ns figure 60 serial clock low-level pulse width at write (receive) t scl 40 ? ? ns figure 60 at read (send) t scl 120 ? ? ns figure 60 serial clock rise/fall time t scr , t scf ?? 20 ns figure 60 cs* setup time t csu 20 ? ? ns figure 60 cs* hold time t ch 60 ? ? ns figure 60 serial input data setup time t sisu 30 ? ? ns figure 60 serial input data hold time t sih 30 ? ? ns figure 60 serial output data delay time t sod ?? 200 ns figure 60 serial output data hold time t soh 5? ?n s figure 60 hd66763 82 ( vcc = 2.4 to 3.6 v) item symbol min typ max unit test condition serial clock cycle time at write (receive) t scyc 0.1 ? 20 us figure 60 at read (send) t scyc 0.15 ? 20 us figure 60 serial clock high-level pulse width at write (receive) t sch 40 ? ? ns figure 60 at read (send) t sch 70 ? ? ns figure 60 serial clock low-level pulse width at write (receive) t scl 40 ? ? ns figure 60 at read (send) t scl 70 ? ? ns figure 60 serial clock rise/fall time t scr , t scf ?? 20 ns figure 60 cs* setup time t csu 20 ? ? ns figure 60 cs* hold time t ch 60 ? ? ns figure 60 serial input data setup time t sisu 30 ? ? ns figure 60 serial input data hold time t sih 30 ? ? ns figure 60 serial output data delay time t sod ?? 130 ns figure 60 serial output data hold time t soh 5? ?n s figure 60 reset timing characteristics (v cc = 1.8 to 3.6 v) item symbol min typ max unit test condition reset low-level width t res 1? ?m s figure 61 reset rise time t r res ?? 10 us figure 61 hd66763 83 electrical characteristics notes 1. for bare die and wafer products, specified up to 85 ? c. 2. the following three circuits are i/o pin configurations. reset*, cs*, e/wr*, rw/rd*, rs, osc1, opoff, im2-1, im0/id, test (tri-state output circuit) output data output enable (input circuit) vcc pmos nmos gnd vcc pmos nmos gnd vcc pmos nmos gnd vcc pmos nmos gnd pins : db15-db2, db1/sdo, db0/sdi pins : osc2, cl1, flm, m, disptmg, ccl, cda, ccs pins : figure 53 i/o pin configuration hd66763 84 3. the test pin must be grounded and the im2/im1/0 pins must be grounded or connected to vcc. 4. applies to the resistor value (rseg) between power supply pins vsh, gnd and segment signal pins. 5. this excludes the current flowing through output drive moss. 6. this excludes the current flowing through the input/output units. the input level must be fixed high or low because through current increases if the cmos input is left floating. 7. the following shows the relationship between the operation frequency and current consumption. cr oscillation frequency?ffosc (khz) 150 100 50 0 iop (?a) vcc = 3v 100 180 140 220 260 300 200 vcc = 3v, fosc = 180khz 60 40 20 0 lcd driving voltage ?fvlcd (v) 2.0 3.0 4.0 ilcd (?a) figure 54 relationship between the operation frequency and current consumption 8. each seg output voltage is within 0.15 v of the lcd voltage (vsh, gnd) when there is no load. 9. applies to the external clock input. oscillator osc1 open osc2 t rcp t fcp th tl 0.7vcc 0.5vcc 0.3vcc duty = th + tl th x 100% figure 55 external clock supply hd66763 85 10. applies to the internal oscillator operations using external oscillation resistor rf. osc1 osc2 rf since the oscillation frequency varies depending on the osc1 and osc2 pin capacitance, the wiring length to these pins should be minimized. figure 56 internal oscillation table 30 external resistance value and r-c oscillation frequency (referential data) external r-c oscillation frequency: fosc resistance (rf) vcc = 1.8 v vcc = 2.2 v vcc = 2.4 v vcc = 3.0 v vcc = 3.6 v 91 k ? 252 khz 315 khz 339 khz 389 khz 424 khz 120 k ? 216 khz 267 khz 286 khz 326 khz 353 khz 150 k ? 187 khz 228 khz 243 khz 274 khz 294 khz 200 k ? 159 khz 191 khz 202 khz 225 khz 240 khz 240 k ? 139 khz 166 khz 175 khz 193 khz 205 khz 270 k ? 129 khz 152 khz 160 khz 176 khz 186 khz 320 k ? 114 khz 133 khz 140 khz 152 khz 161 khz 360 k ? 104 khz 121 khz 126 khz 138 khz 145 khz 390 k ? 96 khz 113 khz 118 khz 128 khz 134 khz 440 k ? 90 khz 103 khz 108 khz 116 khz 122 khz load circuits ac characteristics test load circuits data bus: db15 to db0 test point 50 pf figure 57 load circuit hd66763 86 timing characteristics 68-system bus operation rs r/w* cs* e db15-0 *2 db15-0 *2 v ih v il v il v ih v il v ih v il v ih v il read data v oh1 v ol1 v oh1 v ol1 v ih v il v il v ih t ase t er t ef t cyce pw eh *1 pw el t ahe v il v il write data note 1 : pw eh is specified in the overlapped period when cs* is low and e is high. note 2 : in case of 8-bit interface mode, db15-8 are used for parallel interface. fixed unused db7-0 to the vcc or gnd level. t dswe t he t ddre t dhre figure 58 68-system bus timing 80-system bus operation rs cs* rw* rd* db15-0 *2 db15-0 *2 v ih v il v il v ih v il v ih v il v ih v il read data v oh1 v ol1 v oh1 v ol1 v ih v il v ih v ih t as t wrr t wrf t cycw, t cycr pw lw, pw lr *1 pw hw, pw hr t ah v il v il write data note 1 : pw lw and pw lr are specified in the overlapped period when cs* is low and wr* or rd* is low. note 2 : in case of 8-bit interface mode, db15-8 are used for parallel interface. fixed unused db7-0 to the vcc or gnd level. t dsw t h t ddr t dhr figure 59 80-system bus timing hd66763 87 clock synchronized serial interface operation cs* scl sdi v ih v il v il v ih v il v ih v il v ih v ih v ih v ih v il v il t scr t scf t sisu t sih t sch t scl t ch t csu t scyc v il v il end start input data input data sdo v oh1 v ol1 v oh1 v ol1 t sod t soh output data output data figure 60 clock synchronized serial interface input timing reset operation reset* reset* reset* reset* vil vil tres vih trres figure 61 reset timing hd66763 modification history revision 0.3 - first release revision 0.4 - added electrical characteristics section (preliminary) hd66763 when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all right reserved: no one is permitted to reproduce or duplicated, in any form, the whole or part of this document without hitachi's permission. 3. h itachi will not be held res ponsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachi's semiconductor products. hitachi assumes no responsib ility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party of hitachi, ltd. 6. medical applications: hitachi's products are not authorized for use in medical ap pl ic at io ns w it hout the written consent of the appropriate officer of hitachi's sales company. su ch use includes, but is not limited to use in life support systems. buyers of hitachi's products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. |
Price & Availability of HCD66763BP
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |