m5m5408afp,tp,rt-55l, -70l,-10l -55ll,-70ll,-10ll mitsubishi electric 4194304-bit (524288-word by 8-bit) cmos static ram mitsubishi lsis description the m5m5408a is a 4,194,304-bit cmos static ram organizedas 524,288-word by 8-bit. this device is fabricated usingmitsubishi's high-performance silicon-gate cmos technology.this state-of-the-art process technology, combined withinnovative circuit design techniques, yields high-density and low-power devices. the m5m5408a is suitable for memoryapplications where high reliability, large storage, simpleinterfacing and battery back-up are important design objectives. the m5m5408a is available in 32-pin plastic sop(m5m5408afp) , 32-pin plastic normal-lead-bend tsop(m5m5408atp) and 32-pin plastic reverse-lead-bend tsop(m5m5408art) packages. two types of tsop's are suitable forsurface mounting on double-sided printed circuit boards. features pin configuration (top view) outline32p2m-a (afp) 32p3y-h (atp) outline32p3y-j (art) a 18 a 16 a 14 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 dq 1 dq 2 dq 3 gnd (0v) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (5v) v cc a 15 a 17 w a 13 a 8 a 9 a 11 oe a 10 s dq 8 dq 7 dq 6 dq 5 dq 4 ?single +5v power supply ?no clocks, no refresh ?all inputs and outputs are ttl compatible. ?easy memory expansion and power down by s ?data retention supply voltage=2.0v to 5.5v ?three-state outputs: or-tie capability ?oe prevents data contention in the i/o bus ?common data i/o ?battery backup capability ?small stand-by current0.4? (typical) ?package m5m5408afp : 32 pin 525 mil sop m5m5408atp : 32 pin 400 mil tsop(ii) m5m5408art : 32 pin 400 mil tsop(ii) application small capacity memory units ic card battery operating system access power supply current power supply current type name time active stand-by (max.) (max.) (max.) m5m5408afp, tp, rt -55l 55ns 100? m5m5408afp, tp, rt -70l 70ns 30ma (vcc=5.5v*) m5m5408afp, tp, rt -10l 100ns (1mhz) m5m5408afp, tp, rt -55ll 55ns 20? m5m5408afp, tp, rt -70ll 70ns 30ma (vcc=5.5v*) m5m5408afp, tp, rt -10ll 100ns (1mhz) 0.4? (vcc=3v**) * at 70? / **at 25? pin discription a0 ..... a18: address inputs dq1..... dq8: data inputs & outputs s: chip select input w: write enable input oe: output enable input vcc: power supply gnd: ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a 18 a 16 a 14 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 dq 1 dq 2 dq 3 (0v) gnd 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v cc (5v) a 15 a 17 w a 13 a 8 a 9 a 11 oe a 10 s dq 8 dq 7 dq 6 dq 5 dq 4 m5m5408afp, tp m5m5408art
m5m5408afp,tp,rt-55l, -70l,-10l -55ll,-70ll,-10ll mitsubishi electric 4194304-bit (524288-word by 8-bit) cmos static ram mitsubishi lsis a read cycle is executed by setting w at a high level andoeat a low level while s are in an active state(s=l). when setting s at a high level, the chips are in a non-selectable mode in which both reading and writing are disabled.in this mode, the output stage is in a high-impedance state,allowing or-tie with other chips and memory expansion by s.the power supply current is reduced as low as the stand-bycurrent which is specified as icc3 or icc4, and the memorydata can be held at +2v power supply, enabling battery back-up operation during power failure or power-down operation inthe non-selected mode. function the operation mode of the m5m5408a is determined by acombination of the device control inputs s, wand oe.each mode is summarized in the truth table. a write cycle is executed whenever the low level woverlaps with the low level s. the address must be set upbefore the write cycle and must be stable during the entirecycle. the data is latched into a cell on the trailing edge of wor s, whichever occurs first, requiring the set-up and holdtime relative to these edge to be maintained. the outputenable oe directly controls the output stage. setting theoe at a high level, the output stage is in a high-impedancestate, and the data bus contention problem in the write cycleis eliminated. truth table s w dq 1 dq 2 dq 3 dq 4 v cc (5v) gnd (0v) oe dq 5 dq 6 dq 7 dq 8 block diagram 524288 words x 8 bits 512 rows x 128 columns x 64 blocks clock generator a 2 a 1 a 0 a 5 a 4 a 3 s w oe mode dq icc h x x non selection high-impedance stand-by l l x write data input active l h l read data output active l h h read high-impedance active 13 14 15 17 18 19 20 21 32 16 24 22 29 25 a 11 26 a 9 27 a 8 28 a 13 30 a 17 a 15 5 a 7 6 a 6 23 a 10 1 a 18 2 a 16 3 a 14 a 12 10 11 12 7 8 9 4 31 sense amp. data output buffer data input buffer block decoder column decoder row decoder address input buffer address input buffer address input buffer
m5m5408afp,tp,rt-55l, -70l,-10l -55ll,-70ll,-10ll mitsubishi electric 4194304-bit (524288-word by 8-bit) cmos static ram mitsubishi lsis absolute maximum ratings dc electrical characteristics (ta=0 - 70?, vcc=5v?0%, unless otherwise noted) capacitance (ta=0 - 70?, vcc=5v?0%, unless otherwise noted) symbol parameter conditions ratings unit vcc supply voltage - 0.3 ~ 7 v vi input voltage with respect to gnd - 0.3* ~ vcc + 0.3 v vo output voltage 0 ~ vcc v pd power dissipation ta=25? 700 mw topr operating temperature 0 ~ 70 ? tstg storage temperature -65 ~ 150 ? symbol parameter test conditions limits unit min. typ. max. vih high-level input voltage 2.2 vcc+0.3 v vil low-level input voltage -0.3* 0.8 v voh high-level output voltage ioh= - 1ma 2.4 v ioh= - 0.1ma vcc-0.5 v vol low-level output voltage iol = 2 ma 0.4 v ii input leakage current inputs = 0 ~ vcc ? ? io output leakage current s = vih ? ? oe= vih, dq=0 ~ vcc s 0.2 minimum icc1 active supply current (ac, mos-lvel) other inputs 0.2v or 3 vcc-0.2v cycle 50 80 ma dq = open (duty 100%) 1mhz 25 30 ma s = vil minimum icc2 active supply current (ac, ttl-level) other inputs = vih or vil cycle 60 90 ma dq = open (duty 100%) 1mhz 30 40 ma -l icc3 stand-by current s vcc - 0.2v, version 100 ? other inputs = 0 ~ vcc -ll version 1 20 ? icc4 stand-by current s = vih, other inputs=0 ~ vcc s = vih, other inputs=0 ~ vcc 3 ma symbol parameter test conditions limits unit min. typ. max. ci input capacitance vi = gnd, vi = 25mv rms, f = 1mhz 6 pf co output capacitance vo = gnd, vo = 25mv rms, f = 1mhz 8 pf * -3.0v in case of ac ( pulse width 50ns) * -3.0v in case of ac ( pulse width 50ns) note1. direction for current flowing into ic is indicated as positive value. 2. typical value is for ta=25? and vcc=5.0v 3. ci and co are random samples ,not production tested.
m5m5408afp,tp,rt-55l, -70l,-10l -55ll,-70ll,-10ll mitsubishi electric 4194304-bit (524288-word by 8-bit) cmos static ram mitsubishi lsis fig.1 output load vcc dq c l 1.8k w 990 w c l includes jig and scope capacitance (1) measurement conditions input pulse ? ih =2.4v, v il =0.6v (afp,tp,rt-70l,-10l,-70ll,-10ll) v ih =3.0v, v il =0v (afp,tp,rt-55l,-55ll) input rise and fall time 5ns output reference level v oh =v ol =1.5v for t en and t dis , transition is measured ?00mv from steady state voltage output loads show in fig. 1; c l =100pf (afp,tp,rt-70l,-10l,-70ll,-10ll) c l =30pf (afp,tp,rt-55l,-55ll) c l =5pf (for t en, t dis) ac electrical characteristics (ta=0 - 70?, vcc=5v?0%, unless otherwise noted) (2) read cycle limits symbol parameter m5m5408afp,tp,rt m5m5408afp,tp,rt m5m5408afp,tp,rt m5m5408afp,tp,rt m5m5408afp,tp,rt m5m5408afp,tp,rt unit -55l, -55ll -55l, -55ll -70l, -70ll -70l, -70ll -10l, -10ll -10l, -10ll min. max. min. max. min. max. tcw write cycle time 55 70 100 ns tw(w) write pulse width 40 50 60 ns tsu(a) address set up time 0 0 0 ns tsu(a-wh) address set up time with respect to w high 50 60 80 ns tsu(s) chip select set up time 50 60 80 ns tsu(d) data set up time 25 30 35 ns th(d) data hold time 0 0 0 ns trec(w) write recovery time 0 0 0 ns tdis(w) output disable time after w low 20 25 35 ns tdis(oe) output disable time after oe high 20 25 35 ns ten(w) output enable time after w high 5 5 5 ns ten(oe) output enable time after oe low 5 5 5 ns limits symbol parameter m5m5408afp,tp,rt m5m5408afp,tp,rt m5m5408afp,tp,rt m5m5408afp,tp,rt m5m5408afp,tp,rt m5m5408afp,tp,rt unit -55l, -55ll -55l, -55ll -70l, -70ll -70l, -70ll -10l, -10ll -10l, -10ll min. max. min. max. min. tcr read cycle time 55 70 100 ns ta(a) address access time 55 70 100 ns ta(s) chip select access time 55 70 100 ns ta(oe) output enable access time 25 35 50 ns tdis(s) output disable time after s high 20 25 35 ns tdis(oe) output disable time after oe high 20 25 35 ns ten(s) output enable time after s low 10 10 10 ns ten(oe) output enable time after oe low 5 5 5 ns tv(a) data valid time after address change 10 10 10 ns max.
m5m5408afp,tp,rt-55l, -70l,-10l -55ll,-70ll,-10ll mitsubishi electric 4194304-bit (524288-word by 8-bit) cmos static ram mitsubishi lsis (4) timing diagrams write cycle ( we control mode ) read cycle a 0 ~ a 18 dq 1 ~ dq 8 (d out ) s oe w dq 1 ~ dq 8 (d in ) a 0 ~ a 18 s oe dq 1 ~ dq 8 (d out ) t cr t a(a) t a(oe) t a(s) t en(oe) t en(s) t v(a) t dis(oe) t dis(s) t cw t en(oe) t dis(oe) t dis(w) t en(w) t su(d) t h(d) t w(w) t rec(w) t su(a) t su(s) data valid data valid ( note 4) ( note 4) ( note 4) ( note 4) ( note 4) ( note 4) t su(a-wh)
m5m5408afp,tp,rt-55l, -70l,-10l -55ll,-70ll,-10ll mitsubishi electric 4194304-bit (524288-word by 8-bit) cmos static ram mitsubishi lsis write cycle ( s control mode ) note 4: hatching indicates the state is "don't care". 5: a write occurs during the overlap of a low s and a low w. 6: if w goes low simultaneously with or prior to s, the output remains in the high-impedance state. 7: don't apply inverted phase signal externally when dq pin is in output mode. w dq 1 ~ dq 8 (d in ) a 0 ~ a 18 s t cw t su(d) t h(d) t w(w) t rec(w) t su(a) t su(s) data valid ( note 4) ( note 4) ( note 5) ( note 6)
m5m5408afp,tp,rt-55l, -70l,-10l -55ll,-70ll,-10ll mitsubishi electric 4194304-bit (524288-word by 8-bit) cmos static ram mitsubishi lsis power down characteristics (1) electrical characteristics (2) timing requirements (ta=0 - 70?, unless otherwise noted) (3) timing diagram s control mode symbol parameter test conditions limits unit min. typ. max. vcc(pd) power down supply voltage 2 v vi(s) chip select input s vcc(pd) 3 2.2v 2.2 v 2.2v 3 vcc(pd) 3 2.0v vcc(pd) v -l icc(pd) power down supply current vcc=3v, s 3 vcc-0.2v, version 50 ? other inputs = 0 ~ 3v -ll version 0.4 10* ? symbol parameter test conditions limits unit min. typ. max. tsu(pd) power down set up time 0 ms trec(pd) power down recovery time 5 ms * icc (pd) = 1? at ta=25? 4.5v 4.5v 2.2v 2.2v trec(pd) tsu(pd) vcc s s 3 vcc - 0.2v
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