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1 +features ? >400.0 mbps (200 mhz) switching rates ? + 340mv nominal differential signaling ? 3.3 v power supply ? ttl compatible inputs ? cold sparing all pins ? ultra low power cmos technology ? 3.0ns maximum, propagation delay ? 0.4ns maximum, differential skew ? radiation-hardened design; tota l dose irradiation testing to mil-std-883 method 1019 - total-dose: 300 krad(si) - latchup immune (let > 100 mev-cm 2 /mg) ? packaging options: - 16-lead flatpack (dual in-line) ? standard microcircuit drawing 5962-06201 - qml q and v compliant part introduction the ut54lvdm031lv quad bus-lvds driver is a quad cmos differential line driver designed for applications requiring ultra low power dissipation and high data rates. the device is designed to support data rates in excess of 400.0 mbps (200 mhz) utilizing low voltage differential signaling (lvds) technology. the ut54lvdm031lv accepts low voltage ttl input levels and translates them to low voltage (340mv) differential output signals. in addition, the driver supports a three-state function that may be used to disable the output stage, disabling the load current, and thus dropping the device to an ultra low idle power state. the ut54lvdm031lv and companion quad line receiver ut54lvds032lv provide new alternatives to high power pseudo-ecl devices for high speed point-to-p oint interface applications. all pins have cold spare buffers. these buffers will be high impedance when v dd is tied to v ss . standard products ut54lvdm031lv low voltage bus-lvds quad driver data sheet december 2005 www.aeroflex.com/lvds figure 1. ut54lvdm031lv bus-lvds quad driver block diagram d1 d2 d3 d4 d out1+ d out1- d out2+ d out2- d out3+ d out3- d out4+ d out4- d in1 d in2 d in4 d in3 en en
2 truth table pin description applications information the ut54lvdm031lv bus-lvds dr iver?s intended use is for both point-to-point (single termination) and multipoint (double termination) data transmissions over controlled impedance media. the transmission media may be printed-circuit board traces, backplanes, or cables. note : the ultimate rate and distance of data transfer is dependent up on the attenuation characteristics of the media, the noise coupling to the environment, and other application specifi c characteristics. the ut54lvdm031lv differential line driver is a balanced current source design. a current mo de driver, has a high output impedance and supplies a constant current for a range of loads (a voltage mode driver on the other hand supplies a constant voltage for a range of loads). current is switched through the load in one direction to produce a logic state and in the other direction to produce the other logic st ate. the current mode requires (as discussed above) that a resistiv e termination be employed to terminate the signal and to comple te the loop as shown in figure 3. ac or unterminated configura tions are not allowed. the 10ma loop current will develop a differ ential voltage of 350mv across the 35 ? termination resistor which the receiver detects with a 250mv minimum differential nois e margin neglecting resistive line losses (driven signal minu s receiver threshold (340mv - 100mv = 250mv)). the signal is centered around +1.2v (driver offset, v os ) with respect to ground as shown in figure 4. note: the steady-state voltage (v ss ) peak-to-peak swing is twice the differential voltage (v od ) and is typically 700mv. enables input output en en d in d out+ d out- l h x z z all other combinations of enable inputs l l h h h l pin no. name description 1, 7, 9, 15 d in driver input pin, ttl/cmos compatible 2, 6, 10, 14 d out+ non-inverting driver output pin, lvds levels 3, 5, 11, 13 d out- inverting driver output pin, lvds levels 4 en active high enable pin, or-ed with en 12 en active low enable pin, or-ed with en 16 v dd power supply pin, +3.3v + 0.3v 8v ss ground pin figure 2. ut54lvdm031lv pinout ut54lvdm031lv driver 16 15 14 13 12 11 10 9 v dd d in4 d out4+ d out4- en d out3- d out3+ d in3 1 d in1 2 d out1+ 3 d out1- 4 en 5 d out2- 6 d out2+ 7 d in2 8 v ss enable data input 1/4 ut54lvdm031lv 1/4 ut54lvds032lv + - data output figure 3. point-to-point application rt 35 ?
3 the current mode driver provides substantial benefits over voltage mode drivers, such as an rs-422 driver. its quiescent current remains relatively flat versus switching frequency. whereas the rs-422 voltage mode driver increases exponentially in most cases between 20 mhz - 50 mhz. this is due to the overlap current that flows between the rails of the device when the internal gates sw itch. whereas the current mode driver switches a fixed current between its output without any substantial overlap current. this is similar to some ecl and pecl devices, but without the heavy static i cc requirements of the ecl/pecl design. lvds requ ires 80% less current than similar pecl devices. ac specifi cations for the driver are a tenfold improvement over other existing rs-422 drivers. the three-state func tion allows the driver outputs to be disabled, thus obtaining an ev en lower power state when the transmission of data is not required. absolute maximum ratings 1 (referenced to v ss ) notes: 1. stresses outside the listed absolute maximum ratings may caus e permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. maximum junction temperat ure may be increased to +175 c during burn-in and life test. 3. test per mil-std-883, method 1012. recommended operating conditions d in d out- d out+ single-ended d out+ - d out- differential output v 0d 3v 0v v oh v os v ol +v od -v od 0v 0v (diff.) v ss figure 4. bus-lvds driver output note: the footprint of the ut54 lvdm031lv is the same as the industry standard quad di fferential (rs-422) driver. symbol parameter limits v dd dc supply voltage -0.3 to 4.0v v i/o voltage on any pin during operation -0.3 to (v dd + 0.3v) voltage on any pin during cold spare -.3 to 4.0v t stg storage temperature -65 to +150 c p d maximum power dissipation 1.25 w t j maximum junction temperature 2 +150 c jc thermal resistance, junction-to-case 3 10 c/w i i dc input current 10ma symbol parameter limits v dd positive supply voltage 3.0 to 3.6v t c case temperature range -55 to +125 c v in dc input voltage 0v to v dd
4 dc electrical characteristics 1, 2 (v dd = 3.3v + 0.3v; -55 c < t c < +125 c) notes: 1. current into device pins is defined as positive. current out of device pins is de fined as negative. all voltages are referen ced to ground except differential voltages. 2. output short circuit current (i os ) is specified as magnitude only, minus sign indicates direction only. only one output at a time for 1 second. 3. guaranteed by characterization. symbol parameter condition min max unit v ih high-level input voltage (ttl) 2.0 v dd v v il low-level input voltage (ttl) v ss 0.8 v v ol low-level output voltage r l = 35 ? 0.855 v v oh high-level output voltage r l = 35 ? 1.750 v i in input leakage current v in = v dd or gnd, v dd = 3.6v -10 +10 a i cs cold spare leakage current v in =3.6v, v dd =v ss -20 +20 ? v od 1 differential output voltage r l = 35 ? (figure 5) 250 400 mv ? v od 1 change in magnitude of v od for complementary output states r l = 35 ? (figure 5) 35 mv v os offset voltage r l = 35 ? , 1.055 1.550 v ? v os change in magnitude of v os for complementary output states r l = 35 ? (figure 5) 35 mv v cl 3 input clamp voltage i cl = +18ma -1.5 v i os 2, 3 output short circuit current v in = v dd , v out+ = 0v or v in = gnd, v out- = 0v 4.5 ma i oz 3 output three-state current en = 0.8v and en = 2.0 v, v out = 0v or v dd, v dd = 3.6v -10 +10 ? i ccl 3 loaded supply current, drivers enabled r l = 35 ? all channels v in = v dd or v ss (all inputs) 60.0 ma i ccz 3 loaded supply current, drivers disabled d in = v dd or v ss en = v ss , en = v dd 6.0 ma vos voh vol + 2 -------------------------- - = ?? ??
5 figure 5. driver v od and v os test circuit or equivalent circuit d d in d out- d out+ 10pf driver enabled generator 50 ? r l = 35 ? v od 10pf
6 ac switching characteristics 1, 2, 3 (v dd = +3.3v + 0.3v, t a = -55 c to +125 c) notes: 1. channel-to-channel skew is defined as the difference between the propagation delay of the channel and th e other channels in the same chip with an event on the inputs. 2. generator waveform for all tests unless otherwise specified: f = 1 mhz, z o = 50, t r < 1ns, and t f < 1ns. 3. c l includes probe and jig capacitance. 4. guaranteed by characterization 5. chip to chip skew is defined as th e difference between the minimum and maximum specified differential propagation delays. 6. may be tested at higher load capac itance and the limit interpolated from charact erization data to guarantee this parameter. symbol parameter min max unit t phld 6 differential propagati on delay high to low (figures 6 and 7) 0.5 1.8 ns t plhd 6 differential propagati on delay low to high (figures 6 and 7) 0.5 1.8 ns t skd differential skew (t phld - t plhd ) (figures 6 and 7) 0 0.4 ns t sk1 channel-to-channel skew 1 (figures 6 and 7) 00.5ns t sk2 5 chip-to-chip skew (figure 6 and 7) 1.3 ns t tlh 4 rise time (figures 6 and 7) 1.5 ns t thl 4 fall time (figures 6 and 7) 1.5 ns t phz disable time high to z (figures 8 and 9) 5.0 ns t plz disable time low to z (figures 8 and 9) 5.0 ns t pzh enable time z to high (figures 8 and 9) 7.0 ns t pzl enable time z to low (figures 8 and 9) 7.0 ns
7 d d in d out- d out+ driver enabled generator 50 ? r l = 35 ? figure 6. driver propagation delay and transition time test circuit or equivalent circuit 10pf 10pf d in d out- d out+ v diff t phld v dd 0v v oh v ol 0v v diff = d out+ - d out- 0v (differential) v dd /2 t thl 20% 80% 0v 20% 80% t tlh t plhd v dd /2 figure 7. driver propagation delay and transition time waveforms
8 d v dd v ss d in en generator 50 ? en r l =35 ? d out+ d out- figure 8. driver three-state delay te st circuit or equivalent circuit 10pf 10pf en when en = v dd en when en = v ss or d out+ when d in =v dd d out- when d in = v ss d out+ when d in = v ss d out- when d in = v dd t plz t pzl 50% 50% v ol v os v os v oh 0v v dd 0v v dd 50% 50% 50% 50% 50% t pzh t phz figure 9. driver three-state delay waveform 50%
9 notes: 1. all exposed metalized areas are gold plated over electroplated nickel per mil-prf-38535. 2. the lid is electrica lly connected to vss. 3. lead finishes are in accordance to mil-prf-38535. 4. package dimensions and symbols are similar to mil-std-1835 variation f-5a. 5. lead position and coplanarity are not measured. 6. id mark symbol is vendor option. 7. with solder, increase maximum by 0.003. figure 10. 16-pin ceramic flatpack packaging
10 ordering information ut54lvdm031lv bus-lvds quad driver: ut 54lvdm031lv - * * * * * device type: ut54lvdm031lv bus-lvds driver access time: not applicable package type: (u) = 16-lead flatpack (dual-in-line) screening: (c) = military temperature range flow (p) = prototype flow lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when or dering, then the part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3. prototype flow per aeroflex colorado spring s manufacturing flows document. tested at 25 c only. lead finish is gold only. radiation neither tested nor guaranteed. 4. military temperature range flow per aero flex colorado springs manufacturing flow s document. devices are tested at -55 c, room temp, and 125 c. radiation neither tested nor guaranteed.
11 ut54lvdm031lv quad bus-lvds driver: smd 5962 - ** * federal stock class designator: no options total dose (r) = 1e5 rad(si) (f) = 3e5 rad(si) drawing number: 5962-06201 device type 01 lvds driver 100k rad (si) 300k rad (si) class designator: (q) = qml class q (v) = qml class v case outline: (x) = 16 lead flatpack (dual-in-line) lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) 06201 ** notes: 1.lead finish (a,c, or x) must be specified. 2.if an ?x? is specified when ordering, part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3.total dose radiation must be specified when ordering. qml q and qml v not available without radiation hardening.
12 colorado toll free: 800-645-8862 fax: 719-594-8468 se and mid-atlantic tel: 321-951-4164 fax: 321-951-4254 international tel: 805-778-9229 fax: 805-778-1980 west coast tel: 949-362-2260 fax: 949-362-2266 northeast tel: 603-888-3975 fax: 603-888-4585 central tel: 719-594-8017 fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused aeroflex colorado springs, inc. reserves the right to make changes to any products and services herein at any time without notice. consult aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by aeroflex; nor does the purchase, lease, or use of a pr oduct or service from aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of aeroflex or of third parties.

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