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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD8313 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998 0.1 ghzC2.5 ghz, 70 db logarithmic detector/controller functional block diagram ++ + + + AD8313 vout vset comm pwdn gain bias band-gap reference slope control intercept control eight 8db 3.5ghz amplifier stages 8db 8db vpos inhi inlo vpos 8db 8db nine detector cells c int lp i v v v v i features wide bandwidth: 0.1 ghz to 2.5 ghz min high dynamic range: 70 db to 6 3.0 db high accuracy: 6 1.0 db over 65 db range (@ 1.9 ghz) fast response: 40 ns full-scale typical controller mode with error output scaling stable over supply and temperature wide supply range: +2.7 v to +5.5 v low power: 40 mw at 3 v power-down feature: 60 m w at 3 v complete and easy to use applications rf transmitter power amplifier setpoint control and level monitoring logarithmic amplifier for rssi measurement cellular base stations, radio link, radar product description the AD8313 is a complete multistage demodulating logarith- mic amplifier, capable of accurately converting an rf signal at its differential input to an equivalent decibel-scaled value at its dc output. the AD8313 maintains a high degree of log con- formance for signal frequencies from 0.1 ghz to 2.5 ghz and is useful over the range of 10 mhz to 3.5 ghz. the nominal input dynamic range is C65 dbm to 0 dbm (re: 50 w ), and the sensitivity can be increased by 6 db or more with a narrow band input impedance matching network or balun. application is straightforward, requiring only a single supply of 2.7 vC5.5 v and the addition of a suitable input and supply decoupling. operating on a 3 v supply, its 13.7 ma consumption (for t a = +25 c) amounts to only 41 mw. a power-down feature is provided; the input is taken high to initiate a low c urrent (20 m a) sleep mode, with a threshold at half the supply voltage. the AD8313 uses a cascade of eight amplifier/limiter cells, each having a nominal gain of 8 db and a C3 db bandwidth of 3.5 ghz, for a total midband gain of 64 db. at each amplifier output, a detector (rectifier) cell is used to convert the rf signal to baseband form; a ninth detector cell is placed directly at the input of the AD8313. the current-mode outputs of these cells are summed to generate a piecewise linear approximation to the logarithmic function, and converted to a low impedance v oltage- mode output by a transresistance stage, which also acts as a low- pass filter. when used as a log amp, the scaling is determined by a separate feedback interface (a transconductance stage) that sets the slope to approximately 18 mv/db; used as a controller, this stage accepts the setpoint input. the logarithmic intercept is posi- tioned to nearly C100 dbm, and the output runs from about 0.45 v dc at C73 dbm input to 1.75 v dc at 0 dbm input. the scale and intercept are supply and temperature stable. the AD8313 is fabricated on analog devices advanced 25 ghz silicon bipolar ic process and is available in a 8-lead m soic package. the operating temperature range is C40 c to +85 c. an evaluation board is available. input amplitude C dbm 2.0 C80 output voltage C volts dc 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 C70 C60 C50 C40 C30 C20 C10 0 frequency = 1.9ghz 5 4 3 2 1 0 C1 C2 C3 C4 C5 output error C db figure 1. typical logarithmic response and error vs. input amplitude
C2C rev. 0 AD8313Cspecifications (@ t a = +25 8 c, v s = +5.0 v 1 , r l 3 10 k v unless otherwise noted) parameter conditions min 2 typ max 2 units signal input interface specified frequency range 0.1 2.5 ghz dc common-mode voltage v pos C 0.75 v input bias currents 10 m a input impedance f rf < 100 mhz 3 900 i 1.1 w i pf 4 log (rssi) mode sinusoidal, input termination configuration shown in figure 27. 100 mhz 5 nominal conditions 3 db dynamic range 6 53.5 65 db range center C31.5 dbm 1 db dynamic range 56 db slope 17 19 21 mv/db intercept C96 C88 C80 dbm +2.7 v v s +5.5 v, C40 c t +85 c 3 db dynamic range 51 64 db range center C31 dbm 1 db dynamic range 55 db slope 16 19 22 mv/db intercept C99 C89 C75 dbm temperature sensitivity p in = C10 dbm C0.022 db/ c 900 mhz 5 nominal conditions 3 db dynamic range 60 69 db range center C32.5 dbm 1 db dynamic range 62 db slope 15.5 18 20.5 mv/db intercept C105 C93 C81 dbm +2.7 v v s +5.5 v, C40 c t +85 c 3 db dynamic range 55.5 68.5 db range center C32.75 dbm 1 db dynamic range 61 db slope 15 18 21 mv/db intercept C110 C95 C80 dbm temperature sensitivity p in = C10 dbm C0.019 db/ c 1.9 ghz 7 nominal conditions 3 db dynamic range 52 73 db range center C36.5 dbm 1 db dynamic range 62 db slope 15 17.5 20.5 mv/db intercept C115 C100 C85 dbm +2.7 v v s +5.5 v, C40 c t +85 c 3 db dynamic range 50 73 db range center 36.5 dbm 1 db dynamic range 60 db slope 14 17.5 21.5 mv/db intercept C125 C101 C78 dbm temperature sensitivity p in = C10 dbm C0.019 db/ c 2.5 ghz 7 nominal conditions 3 db dynamic range 48 66 db range center C34 dbm 1 db dynamic range 46 db slope 16 20 25 mv/db intercept C111 C92 C72 dbm +2.7 v v s +5.5 v, C40 c t +85 c 3 db dynamic range 47 68 db range center C34.5 dbm 1 db dynamic range 46 db slope 14.5 20 25 mv/db intercept C128 C92 C56 dbm temperature sensitivity p in = C10 dbm C0.040 db/ c
C3C rev. 0 AD8313 parameter conditions min 2 typ max 2 units 3.5 ghz 5 3 db dynamic range 43 db 1 db dynamic range 35 db slope 24 mv/db intercept C65 dbm control mode controller sensitivity f = 900 mhz 23 v/db low frequency gain vset to vout 8 84 db open loop corner frequency vset to vout 8 700 hz open loop slew rate f = 900 mhz 2.5 v/ m s vset delay time 150 ns vout interface current drive capability source current 400 m a sink current 10 ma minimum output voltage open loop 50 mv maximum output voltage open loop v pos C 0.1 v output noise spectral density p in = C60 dbm, f spot = 100 hz 2.0 m v/ ? hz p in = C60 dbm, f spot = 10 mhz 1.3 m v/ ? hz small signal response time p in = C60 dbm to C57 dbm, 10% to 90% 40 60 ns large signal response time p in = no signal to 0 dbm, settled to 0.5 db 110 160 ns vset interface input voltage range 0 v pos v input impedance 18k i 1 w i pf power-down interface pwdn threshold v pos /2 v power-up response time time delay following hi to lo transition until device meets full specifications. 1.8 m s pwdn input bias current pwdn = 0 v 5 m a pwdn = v s <1 m a power supply operating range +2.7 +5.5 v powered-up current 13.7 15.5 ma +4.5 v v s +5.5 v, C40 c t +85 c 18.5 ma +2.7 v v s +3.3 v, C40 c t +85 c 18.5 ma powered-down current +4.5 v v s +5.5 v, C40 c t +85 c 50 150 m a +2.7 v v s +3.3 v, C40 c t +85 c2050 m a notes 1 except where otherwise noted, performance at v s = +3.0 v is equivalent to +5.0 v operation. 2 minimum and maximum specified limits on parameters that are guaranteed but not tested are six sigma values. 3 input impedance shown over frequency range in figure 24. 4 double slashes ( i ) denote in parallel with. 5 linear regression calculation for error curve taken from C40 dbm to C10 dbm for all parameters. 6 dynamic range refers to range over which the linearity error remains within the stated bound. 7 linear regression calculation for error curve taken from C60 dbm to C5 dbm for 3 db dynamic range. all other regressions taken from C40 dbm to C10 dbm. 8 ac response shown in figure 10. specifications subject to change without notice.
AD8313 C4C rev. 0 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD8313 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy [>250 v hbm] electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings* supply voltage v s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v vout, vset, pwdn . . . . . . . . . . . . . . . . . . . . . . 0 v, vpos input power differential (re: 50 w , 5.5 v) . . . . . . . . . +25 dbm input power single-ended (re: 50 w , 5.5 v) . . . . . . . +19 dbm internal power dissipation . . . . . . . . . . . . . . . . . . . . . 200 mw q ja . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 c/w maximum junction temperature . . . . . . . . . . . . . . . . +125 c operating temperature range . . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . . C65 c to +150 c lead temperature range (soldering 60 sec) . . . . . . . . +300 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may effect device reliability. pin configuration top view (not to scale) 8 7 6 5 1 2 3 4 vpos inhi inlo vpos vout vset comm pwdn AD8313 ordering guide temperature package package model range descriptions option AD8313arm 1 C40 c to +85 c tube rm-08 2 AD8313arm-reel 13 tape and reel AD8313arm-reel7 7 tape and reel AD8313-eval evaluation board notes 1 device branded as j1a. 2 8-lead m soic. pin function descriptions pin name function 1, 4 vpos positive supply voltage (v pos ), +2.7 v to +5.5 v . 2 inhi noninverting input. this input should be ac coupled. 3 inlo inverting input. this input should be ac coupled. 5 pwdn connect pin to ground for normal operat- ing mode. connect pin to supply for power- down mode. 6 comm device common. 7 vset setpoint input for operation in controller mode. to operate in rssi mode, short vset and vout. 8 vout logarithmic/error output.
AD8313 C5C rev. 0 input amplitude C dbm 2.0 C70 v out C volts 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 C60 C50 C40 C30 C20 C10 0 10 v s = +5v input match shown in figure 27 1.9ghz 2.5ghz 900mhz 100mhz figure 2. v out vs. input amplitude input amplitude C dbm 6 C6 C70 10 C60 error C db C50 C40 C30 C20 C10 0 4 2 0 C2 C4 900mhz 100mhz 100mhz 900mhz 1.9ghz 2.5ghz 2.5ghz 1.9ghz v s = +5v input match shown in figure 27 figure 3. log conformance vs. input amplitude input amplitude C dbm 2.0 C70 v out C volts 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 C60 C50 C40 C30 C20 C10 0 10 v s = +5v input match shown in figure 27 5 4 3 2 1 0 C1 C2 C3 C4 C5 error C db C40 8 c +25 8 c +85 8 c slope and intercept normalized at +25 8 c and applied to C40 8 c and +85 8 c figure 4. v out and log conformance vs. input amplitude at 100 mhz; C40 c, +25 c and +85 c typical performance characteristicsC input amplitude C dbm 2.0 C70 v out C volts 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 C60 C50 C40 C30 C20 C10 0 10 v s = +5v input match shown in figure 27 5 4 3 2 1 0 C1 C2 C3 C4 C5 error C db +25 8 c +85 8 c C40 8 c slope and intercept normalized at +25 8 c and applied to C40 8 c and +85 8 c figure 5. v out and log conformance vs. input amplitude at 900 mhz; C40 c, +25 c and +85 c input amplitude C dbm 2.0 C70 v out C volts 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 C60 C50 C40 C30 C20 C10 0 10 v s = +5v input match shown in figure 27 5 4 3 2 1 0 C1 C2 C3 C4 C5 error C db C40 8 c +25 8 c +85 8 c slope and intercept normalized at +25 8 c and applied to C40 8 c and +85 8 c figure 6. v out and log conformance vs. input amplitude at 1.9 ghz; C40 c, +25 c and +85 c input amplitude C dbm 2.0 C70 v out C volts 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 C60 C50 C40 C30 C20 C10 0 10 v s = +5v input match shown in figure 27 5 4 3 2 1 0 C1 C2 C3 C4 C5 error C db C40 8 c +25 8 c +85 8 c slope and intercept normalized at +25 8 c and applied to C40 8 c and +85 8 c figure 7. v out and log conformance vs. input amplitude at 2.5 ghz; C40 c, +25 c and +85 c
AD8313 C6C rev. 0 frequency C mhz 22 21 16 0 2500 500 slope C mv/db 1000 1500 2000 20 19 18 17 v ps = +5v input match shown in figure 27 C40 8 c +25 8 c +85 8 c figure 8. v out slope vs. frequency; C40 c, +25 c and +85 c supply voltage C v 24 2.5 slope C mv/db 23 22 21 20 19 18 17 16 15 14 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.9ghz 2.5ghz 900mhz 100mhz specified operating range figure 9. v out slope vs. supply voltage frequency C hz v set to v out gain C db 100 1k 10k 100k 1m ref level = 92db scale: 10db/div figure 10. ac response from v set to v out frequency C mhz C110 0 2500 500 intercept C dbm 1000 1500 2000 C70 C80 C90 C100 +85 8 c C40 8 c +25 8 c v ps = +5v input match shown in figure 27 figure 11. v out intercept vs. frequency; C40 c, +25 c and +85 c supply voltage C v C70 2.5 intercept C dbm C75 C80 C85 C90 C95 C100 C105 C110 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.9ghz 2.5ghz 900mhz 100mhz specified operating range figure 12. v out intercept vs. supply voltage frequency C hz 100 10 0.1 m v/ hz 1 1k 10k 100k 1m 10m 2ghz rf input v s = +5.5v input match shown in figure 27 rf input C70dbm C60dbm C55dbm C50dbm C45dbm C40dbm C35dbm C30dbm figure 13. v out noise spectral density
AD8313 C7C rev. 0 pwdn voltage C v 0 100.00 supply current C ma 10.00 1.00 0.10 0.01 12 34 5 40 m a v pos = +5v v pos = +3v 20 m a 13.7ma figure 14. typical supply current vs. pwdn voltage ch. 1 & ch. 2: 1v/div ch. 3: 5v/div horizontal: 1 m s/div v out @ v s = +5.5v v out @ v s = +2.7v pwdn ch. 1 gnd ch. 2 gnd ch. 3 gnd figure 15. pwdn response time 0.1 m f 54.9 v 0.01 m f 0.01 m f 10 v 10 v 0.1 m f +v s +v s tek tds784c scope 8 7 6 5 1 2 3 4 vpos vout inhi inlo vpos pwdn comm vset AD8313 tek p6205 fet probe trig 0603 size surface mount components on a low leakage pc board ext trig out hp8112a pulse generator pin = 0dbm rf out hp8648b signal generator 10mhz ref output figure 16. test setup for pwdn response time ch. 1 ch. 1 gnd ch. 2 gnd ch. 2 ch. 1 & ch. 2: 200mv/div average: 50 samples v s = +5.5v v s = +2.7v horizontal: 50ns/div pulsed rf 100mhz, C45dbm figure 17. response time, no signal to C45 dbm ch. 1 & ch. 2: 500mv/div average: 50 samples horizontal: 50ns/div ch. 1 gnd ch. 2 gnd pulsed rf 100mhz, 0dbm ch. 1 ch. 2 v s = +5.5v v s = +2.7v figure 18. response time, no signal to +0 dbm 0.1 m f 54.9 v 0.01 m f 0.01 m f 10 v 10 v 0.1 m f +v s +v s tek tds784c scope 8 7 6 5 1 2 3 4 vpos vout inhi inlo vpos pwdn comm vset AD8313 tek p6205 fet probe trig out 0603 size surface mount components on a low leakage pc board ext trig hp8112a pulse generator rf out 10mhz ref output C6db rf splitter C6db hp8648b signal generator pulse modulation mode pulse mode in out trig figure 19. test setup for rssi-mode pulse response
AD8313 C8C rev. 0 circuit description the AD8313 is essentially an 8-stage logarithmic amplifier, specifically designed for use in rf measurement and power amplifier control applications at frequencies up to 2.5 ghz. a block diagram is shown in figure 20. (for a full treatment of log-amp theory and design principles, consult the ad8307 data sheet). ++ + + + AD8313 vout vset comm pwdn gain bias band-gap reference slope control intercept control eight 8db 3.5ghz amplifier stages 8db 8db vpos inhi inlo vpos 8db 8db nine detector cells c int lp i v v v v i figure 20. block diagram a fully-differential design is used, and the inputs inhi and inlo (pins 2 and 3) are internally biased to approximately 0.75 v below the supply voltage, and present a low frequency imped- ance of nominally 900 w in parallel with 1.1 pf. the noise spectral density referred to the input is 1.5 nv/ ? hz , equivalent to a voltage of 88 m v rms in a 3.5 ghz bandwidth, or a noise power of C68 dbm re: 50 w . this sets the lower limit to the dynamic range; the applications section shows how to increase the sensitivity by the use of a matching network or input trans- former. however, the low end accuracy of the AD8313 is enhanced by specially shaping the demodulation transfer characte ristic to partially compensate for errors due to internal noise. each of the eight cascaded stages has a nominal voltage gain of 8 db and a bandwidth of 3.5 ghz, and is supported by preci- sion biasing cells which determine this gain and stabilize it against supply and temperature variations. since these stages are direct-coupled and the dc gain is high, an offset-compensation loop is included. the first four of these stages, and the biasing system, are powered from pin 4, while the later stages and the output interfaces are powered from pin 1. the biasing is con- trolled by a logic interface pwdn (pin 5); this is grounded for normal operation, but may be taken high (to v s ) to disable the chip. the threshold is at v pos /2 and the biasing functions are enabled and disabled within 1.8 m s. each amplifier stage has a detector cell associated with its out- put. these nonlinear cells essentially perform an absolute-value (full-wave rectification) function on the differential voltages along this backbone, in a transconductance fashion; their out- puts are in current-mode form and are thus easily summed. a ninth detector cell is added at the input of the AD8313. since the mid-range response of each of these nine detector stages is separated by 8 db, the overall dynamic range is about 72 db (figure 21). the upper end of this range is determined by the capacity of the first detector cell, and occurs at approximately 0 dbm. the practical dynamic range is over 70 db, to the 3 db error points. however, some erosion of this range will occur at temp erature and frequency extremes. useful operation to over 3 ghz is po ssible, and the AD8313 remains serviceable at 10 mhz (see typical performance characteristics), needing only a small amount of additional ripple filtering. input amplitude C dbm 2.0 C80 v out C volts 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 C70 C60 C50 C40 C30 C20 C10 0 5 4 3 2 1 0 C1 C2 C3 C4 C5 error C db C90 intercept = C100dbm slope = 18mv/db figure 21. typical rssi response and error vs. input power at 1.9 ghz the fluctuating current output generated by the detector cells, with a fundamental component at twice the signal frequency, is filtered first by a low-pass section inside each cell, and also by the output stage. the output stage converts these currents to a voltage, v out , at pin vout (pin 8), which can swing rail-to- rail. the filter exhibits a two-pole response with a corner at approximately 12 mhz and full-scale rise time (10%C90%) of 40 ns. the residual output ripple at an input frequency of 100 mhz has an amplitude of under 1 mv. the output can drive a small resistive load: it can source currents of up to 400 m a, and sink up to 10 ma. the output is stable with any capacitive load, though settling time may be impaired. the low frequency incremental output impedance is approximately 0.2 w . in addition to its use as an rf power measurement device (that is, as a logarithmic amplifier) the AD8313 may also be used in controller applications, by breaking the feedback path from vout to the vset (pin 7), which determines the slope of the output (nominally 18 mv/db). this pin becomes the setpoint input in controller modes. in this mode, the voltage v out re- mains close to ground (typically under 50 mv) until the decibel equivalent of the voltage v set is reached at the input, when v out makes a rapid transition to a voltage close to v pos (see controller mode). the logarithmic intercept is nominally posi- tioned at C100 dbm (re: 50 w ) and this is effective in both the log amp mode and the controller mode. thus, with pins 7 and 8 connected (log amp mode) we have: v out = v slope (p in + 100 dbm) where p in is the input power, stated in dbm when the source is directly terminated in 50 w . however, the input impedance of the AD8313 is much higher than 50 w and the sensitivity of this device may be increased by about 12 db by using some type of matching network (see below), which adds a voltage gain and lowers the intercept by the same amount. this dependence on the choice of reference impedance can be avoided by restating the expression as: v out = 20 v slope log (v in / 2.2 m v) where v in is the rms value of a sinusoidal input appearing across pins 2 and 3; here, 2.2 m v corresponds to the intercept, expressed in voltage terms. (for a more thorough treatment of the effect of signal waveform and metrics on the intercept posi- tioning for a log amp, see the ad8307 data sheet).
AD8313 C9C rev. 0 with pins 7 and 8 disconnected (controller mode), the output may be stated as v out v v s when v slope (p in + 100 ) > v set v out v 0 when v slope (p in + 100 ) < v set when the input is stated in terms of the power of a sinusoidal signal across a net termination impedance of 50 w . the transi- tion zone between high and low states is very narrow, since the output stage behaves essentially as a fast integrator. the above equations may be restated as v out v v s when v slope log ( v in /2.2 m v ) > v set v out v 0 when v slope log ( v in /2.2 m v ) < v set a further use of the separate vout and vset pins is in raising the load-driving current capability by the inclusion of an ex- ternal npn emitter follower. more complete information about usage in these various modes is provided in the applications section. interfaces this section describes the signal and control interfaces and their behavior. on-chip resistances and capacitances exhibit varia- tions of up to 20%. these resistances are sometimes tempera- ture dependent and the capacitances may be voltage dep endent. power-down interface, pwdn the power-down threshold is accurat ely centered at the mid point of the supply as shown in figure 22. if pin 5 is left unconnected or tied to the supply voltage (recommended) the bias enable cur- rent is shut off, and the current drawn from the supply is pre- dominately through a nominal 300 k w chain (20 m a at 3 v). when ground ed, the bias system is turned on. the threshold le vel is accurately at v pos /2. the input bias current at the pwdn pin when operating in the device on state is approximately 5 m a for v pos = 3 v. 5 pwdn vpos 75k v 6 comm 150k v 50k v 150k v to bias enable 4 figure 22. power-down threshold circuitry signal inputs, inhi, inlo the simplest low frequency ac model for this interface consists of just a 900 w resistance r in in shunt with a 1.1 pf input ca- pacitance, c in connected across inhi and inlo. figure 23 shows these distributed in the context of a more complete sche- matic. the input bias voltage shown is for the enabled chip; when disabled, it will rise by a few hundred millivolts. if the input is coupled via capacitors, this change may cause a low- level signal transient to be introduced, having a time-constant formed by these capacitors and r in . for this reason, large- valued coupling capacitors should be well matched; this is not necessary when using the small capacitors found in many im- pedance transforming networks used at high frequencies. 1.25k v comm vpos inhi inlo vpos 0.5pf 0.5pf 0.7pf 2.5k v 2.5k v ~ 0.75v (1st detector) 250 v ~ 1.4ma 125 v 125 v 1.25k v 1.24v gain bias to 2nd stage to stages 1 thru 4 1 2 3 4 figure 23. input interface simplified schematic for high frequency use, figure 24 shows the input impedance plotted on a smith chart. this measured result of a typical de- vice includes a 191 mil 50 w trace and a 680 pf capacitor to ground from the inlo pin. 1.1pf 900 v 1.9 ghz frequency 100 mhz 900 mhz 1.9 ghz 2.5 ghz r 650 55 22 23 +j x Cj 400 Cj 135 Cj 65 Cj 43 AD8313 measured 2.5 ghz 900 mhz 100 mhz figure 24. typical input impedance logarithmic/error output, vout the rail-to-rail output interface is shown in figure 25. v out can run from within about 50 mv of ground, to within about 100 mv of the supply voltage, and is short-circuit safe to either supply. however, the sourcing load current i source is limited by that provided by the pnp transistor, to typically 400 m a. larger load currents can be provided by adding an external npn tran- sistor (see applications). the dc open-loop gain of this amplifier is high, and it may be regarded essentially as an integrator hav- ing a capacitance of 2 pf (c int ) driven by the current-mode signals generated by the summed outputs of the nine detector stages, which is scaled approximately 4.0 m a/db. comm gm stage c int lp lm 10ma max vout c l bias i source 400 m a vpos from setpoint summed detector outputs 6 8 1 figure 25. output interface circuitry thus, for a midscale rf input of about 3 mv, which is some 40 db above the minimum detector output, this current is 160 m a and the output changes by 8 v/ m s. when vout is connected to vset, the rise and fall times are approximately 40 ns (for r l 3 10 k w ). the nominal slew rate is 2.5 v/ m s. the hf compensation technique results in stable operation with a large capacitive load, c l , though the positive-going slew rate will then be limited by i source /c l to 1 v/ m s for c l = 400 pf.
AD8313 C10C rev. 0 setpoint interface, vset the setpoint interface is shown in figure 26. the voltage v set is divided by a factor of three in a resistive attenuator of total resistance 18 k w . the signal is converted to a current by the action of the op amp and the resistor r3 (1.5 k w ), which bal- ances the current generated by the summed output of the nine detector cells at the input to the previous cell. the logarithmic slope is nominally 3 4.0 m a/db 1.5 k w ? 18 mv/db. vset vpos r1 12k v comm fdbk to o/p stage 1 r2 6k v r3 1.5k v 25 m a 25 m a 8 6 lp figure 26. setpoint interface circuitry applications basic connections for log (rssi) mode figure 27 shows the AD8313 connected in its basic measure- ment mode. a power supply of +2.7 v to +5.5 v is required. the power supply to each of the vpos pins should be decoupled with a 0.1 m f, surface mount ceramic capacitor and a series resistor of 10 w . the pwdn pin is shown as grounded. the AD8313 may be disabled by a logic hi at this pin. when disabled, the chip current is reduced to about 20 m a from its normal value of 13.7 ma. the logic threshold is at v pos /2 and the enable func- tion occurs in about 1.8 m s; note, however, that further settling time is generally needed at low input levels. while the input in this case is terminated with a simple 50 w broadband resistive match, there are a wide variety of ways in which the input termi- nation can be accomplished. these are discussed in the input coupling section. vset is connected to vout to establish a feedback path that controls the overall scaling of the logarithmic amplifier. the load resistance, r l , should not be lower than 5 k w in order that the full-scale output of 1.75 v can be generated with the limited available current of 400 m a max. as stated in the absolute maximum ratings, an externally ap- plied overvoltage on the vout pin that is outside the range 0 v to v pos is sufficient to cause permanent damage to the device. if overvoltages are expected on the vpos pin, a series resistor (r prot ) should be included as shown. a 500 w resistor is suffi- cient to protect against overvoltage up to 5 v; 1000 w should be used if an overvoltage of up to 15 v is expected. since the output stage is meant to drive loads of no more than 400 m a, this resistor will not impact device performance for more high impedance drive applications (higher output current applications are discussed in the increasing output current section below). r2 10 v r l = 1m v 0.1 m f 53.6 v 680pf 680pf r1 10 v 0.1 m f +v s +v s 8 7 6 5 1 2 3 4 vpos vout inhi inlo vpos pwdn comm vset AD8313 r prot figure 27. basic connections for log (rssi) mode operating in the controller mode figure 28 shows the basic connections for operation in control- ler mode. the link between vout and vset is broken and a setpoint is applied to vset. any difference between v set and the equivalent input power to the AD8313, will drive v out either to the supply rail or close to ground. if v set is greater than the equivalent input power, v out will be driven towards ground and vice versa. v setpoint input controller output r3 10 v 0.1 m f r1 10 v 0.1 m f +v s +v s 8 7 6 5 1 2 3 4 vpos vout inhi inlo vpos pwdn comm vset AD8313 r prot figure 28. basic connections for operation in the controller mode this mode of operation is useful in applications where the out- put power of an rf power amplifier (pa) is to be controlled by an analog agc loop (figure 29). in this mode, a setpoint voltage, proportional in db to the desired output power, is ap- plied to the vset pin. a sample of the output power from the pa, via a directional coupler or other means, is fed to the input of the AD8313. setpoint control dac rfin vout vset AD8313 directional coupler power amplifier rf in envelope of transmitted signal figure 29. setpoint controller operation v out is applied to the gain control terminal of the power ampli- fier. the gain control transfer function of the power amplifier should be an inverse relationship, i.e., increasing voltage de- creases gain.
AD8313 C11C rev. 0 a positive input step on v set (indicating a demand for in- creased power from the pa) will drive v out towards ground. this should be arranged to increase the gain of the pa. the loop will settle when v out settles to a voltage that sets the input power to the AD8313 to the db equivalent of v set . input coupling the signal may be coupled to the AD8313 in a variety of ways. in all cases, there must not be a dc path from the input pins to ground. some of the possibilities include: dual input coupling capacitors, a flux-linked transformer, a printed-circuit balun, direct drive from a directional coupler, or a narrow-band imped- ance matching network. figure 30 shows a simple broadband resistive match. a termina- tion resistor of 53.6 w combines with the internal input imped- ance of the AD8313 to give an overall resistive input impedance of approximately 50 w . the termination resistor should prefer- ably be placed directly across the input pins, inhi to inlo, where it serves to lower the possible deleterious effects of dc offset voltages on the low end of the dynamic range. at low frequencies, this may not be quite as attractive, since it necessi- tates the use of larger coupling capacitors. the two 680 pf input coupling capacitors set the high-pass corner frequency of the network at 9.4 mhz. r match 53.6 v c1 680pf c2 680pf c in r in AD8313 50 v 50 v source figure 30. a simple broadband res istive input termination the high pass corner frequency can be set higher according to the equation: f c db 3 1 250 = p where: c cc cc = + 12 12 in high frequency applications, the use of a transformer, balun or matching network is advantageous. the impedance match- ing characteristics of these networks provide what is essentially a gain stage before the AD8313 that increases the device sensitiv- ity. this gain effect is further explored in the following match- ing example. figures 31 and 32 show device performance under these three input conditions at 900 mhz and 1900 mhz. while the 900 mhz case clearly shows the effect of input matching by realigning the intercept as expected, little improve- ment is seen at 1.9 ghz. clearly, if no improvement in sensitiv- ity is required, a simple 50 w termination may be the best choice for a given design based on ease of use and cost of components. input amplitude C dbm C80 C70 C60 C50 C40 C30 C20 C10 3 2 1 0 C1 C2 C3 error C db terminated dr = 66db C90 10 0 balanced matched balanced dr = 71db matched dr = 69db figure 31. comparison of terminated, matched and balanced input drive at 900 mhz input amplitude C dbm C80 C70 C60 C50 C40 C30 C20 C10 0 3 2 1 0 C1 C2 C3 error C db C90 10 terminated dr = 75db balanced balanced dr = 75db matched dr = 73db matched terminated figure 32. comparison of terminated, matched and balanced input drive at 1900 mhz a narrow-band lc matching example at 100 mhz while numerous software programs are available that allow the values of matching components to be easily calculated, a clear understanding of the calculations involved is valuable. a low frequency (100 mhz) value has been used for this exercise because of the deleterious board effects at higher frequencies. rf layout simulation software is useful when board design at higher frequencies is required. a narro w-band lc match can be implemented either as a series-inductance/shunt-capacitance or as a series-capacitance/ shunt-inductance. however, the concurrent requirement that the AD8313 i nputs, inhi and inlo, be ac-coupled, makes a series-capacitance/ shunt-inductance type match more appropri- ate (see figure 33). l match c1 c2 c in r in AD8313 50 v 50 v source figure 33. narrow-band reactive match
AD8313 C12C rev. 0 typically, the AD8313 will need to be matched to 50 w . the input impedance of the AD8313 at 100 mhz can be read from the smith chart (figure 24) and corresponds to a resistive input impedance of 900 w in parallel with a capacitance of 1.1 pf. to make the matching process simpler, the input capacitance of the AD8313, c in , can be temporarily removed from the calcula- tion by adding a virtual shunt inductor (l2), which will resonate away c in (figure 34). this inductor will be factored back into the calcula tion later. this allows the main calculation to be based on a simple resistive-to-resistive match (i.e., 50 w to 900 w ). the resonant frequency is defined by the equation w= 1 2 lc in therefore: l 2 = 1 2 w c in = 2.3 m h c match = (c1 ? c2) (c1 + c2) l match = (l 1 ? l 2 ) (l 1 + l 2 ) c1 c2 c in r in AD8313 50 v 50 v source l 1 l 2 temporary inductance figure 34. input matching example with c in and l 2 temporarily out of the picture, the focus is now on matching a 50 w source resistance to a (purely resistive) load of 900 w and calculating values for c match and l 1 . when rr l c sin match = 1 the input will look purely resistive at a frequency given by f lc o match = 1 2 1 p = 100 mhz solving for c match gives c rr f pf match sin o == 11 2 75 p . solving for l 1 gives l rr f sin o 1 2 = p = 337.6 nh because l 1 and l 2 are in parallel, they can be combined to give the final value for l match (i.e.) l ll ll match = + 12 12 = 294 nh c1 and c2 can be chosen in a number of ways. first c2 can be set to a large value such as 1000 pf, so that it appears as an rf short. c1 would then be set equal to the calculated value of c match . alternatively, c1 and c2 can each be set to twice c match so that the total series capacitance is equal to c match . by making c1 and c2 slightly unequal (i.e., select c2 to be about 10% less than c1) but keeping their series value the same, the amplitude of the signals on inhi and inlo can be equalized so that the AD8313 is driven in a more balanced manner. any one of the three options detailed above can be used as long as the combined series value of c1 and c2 (i.e., c1 c2/(c1 + c2)) is equal to c match . in all cases, the values of c match and l match must be chosen from standard values. at this point, these values need now be installed on the board and measured for performance at 100 mhz. because of board and layout parasitics, the component values from the above example had to be tuned to the final values of c match = 8.9 pf and l match = 270 nh shown in table i. assuming a lossless matching network and noting conservation of power, the impedance transformation from r s to r in (50 w to 900 w ) has an associated voltage gain given by gain r r db in s = 20 log = 12.6 db because the AD8313 input responds to voltage and not true power, the voltage gain of the matching network will increase the effective input low-end power sensitivity by this amount. thus, in this case, the dynamic range will be shifted down- wards, that is, the 12.6 db voltage gain will shift the 0 dbm to C65 dbm input range downwards to C12.6 dbm to C77.6 dbm. however, because of network losses this gain will not be fully realized in practice. reference figures 31 and 32 for an example of practical attainable voltage gains. table i shows recommended values for the inductor and capaci- tors in figure 32 for some selected rf frequencies along with the associated theoretical voltage gain. these values for a reactive match are optimal for the board layout detailed as figure 45. as previously discussed, a modification of the board layout will produce networks that may not perform as specified. at 2.5 ghz, a shunt inductor is sufficient to achieve match. consequently, c1 and c2 are set sufficiently high that they appear as rf shorts. table i. recommended values for c1, c2 and l match in figure 33 f req. c match c1 c2 l match voltage (mhz) (pf) (pf) (pf) (nh) gain (db) 100 8.9 22 15 270 12.6 9 1000 270 900 1.5 3 3 8.2 9.0 1.5 1000 8.2 1900 1.5 3 3 2.2 6.2 1.5 1000 2.2 2500 large 390 390 2.2 3.2 figure 35 shows the voltage response of the 900 mhz matching network; note the high attenuation at lower frequencies typical of a high-pass network.
AD8313 C13C rev. 0 frequency C mhz 15 50 voltage gain C db 10 5 0 C5 100 200 figure 35. voltage response of 900 mhz narrow-band matching network adjusting the log slope figure 36 shows how the log slope may be adjusted to an exact value. the idea is simple: the output at pin vout is attenuated by the variable resistor r2 working against the internal 18 k w of input resistance at the vset pin. when r2 is zero, the attenuation it introduces is zero, and thus the slope is the basic 18 mv/db (note that this value varies with frequency, see figure 8). when r2 is set to its maximum value of 10 k w , the attenuation from vout to vset is the ratio 18/(18+10), and the slope is raised to (28/18) 18 mv, or 28 mv/db. at about the midpoint, the nominal scale will be 23 mv/db. thus, a 70 db input range will change the output by 70 23 mv, or 1.6 v. 18-30mv/db r2 10k v r3 10 v 0.1 m f r1 10 v 0.1 m f +v s +v s 8 7 6 5 1 2 3 4 vpos vout inhi inlo vpos pwdn comm vset AD8313 figure 36. adjusting the log slope as already stated, the unadjusted log slope varies with frequency from 17 mv/db to 20 mv/db, as shown in figure 8. by placing a resistor between vout and vset, the slope can be adjusted to a convenient 20 mv/db as shown in figure 37. table ii shows the recommended values for this resistor r ext . also shown are values for r ext that increase the slope to approxi- mately 50 mv/db. the corresponding voltage swings for a C65 dbm to 0 dbm input range are also shown in table ii. 20mv/db r ext r3 10 v 0.1 m f r1 10 v 0.1 m f +v s +v s 8 7 6 5 1 2 3 4 vpos vout inhi inlo vpos pwdn comm vset AD8313 figure 37. adjusting the log slope to a fixed value table ii. values for r ext in figure 37 frequency r ext slope v out swing for pin mhz k v mv/db C65 dbm to 0 dbm C v 100 0.953 20 0.44 to 1.74 900 2.00 20 0.58 to 1.88 1900 2.55 20 0.70 to 2.00 2500 0 20 0.54 to 1.84 100 29.4 50 1.10 to 4.35 900 32.4 50.4 1.46 to 4.74 1900 33.2 49.8 1.74 to 4.98 2500 26.7 49.7 1.34 to 4.57 the value for r ext is calculated using the equation: r new slope original slope original slope ext = () 18 k w the value for the original slope , at a particular frequency, can be read from figure 8. the resulting output swing is calculated by simply inserting the new slope value and the intercept at that frequency (figures 8 and 11) into the general equation for the AD8313s output voltage: v out = slope (p in C intercept) increasing output current where it is necessary to drive a more substantial load, one of two methods can be used. in figure 38, a 1 k w pull-up resistor is added at the output which provides the load current necessary to drive a 1 k w load to +1.7 v for v s = 2.7 v. the pull-up resis- tor will slightly lower the intercept and the slope. as a result, the transfer function of the AD8313 will be shifted upwards (inter- cept shifts downward). r2 10 v 0.1 m f r1 10 v 0.1 m f +v s +v s 1 2 3 4 vpos vout inhi inlo vpos pwdn comm vset 8 7 6 5 AD8313 r l = 1k v 20mv/db figure 38. increasing AD8313 output current capability in figure 39, an emitter-follower is used to provide current gain, when a 100 w load can readily be driven to full-scale out- put. while a high b transistor such as the bc848blt1 (min b = 200) is recommended, a 2 k w pull-up resistor between vout and +v s can provide additional base current to the transistor. r3 10 v 0.1 m f r1 10 v 0.1 m f +v s +v s 8 7 6 5 1 2 3 4 vpos vout inhi inlo vpos pwdn comm vset AD8313 output +v s 13k v r l 100 v 10k v bc848blt1 b min = 200 figure 39. output current drive boost connection
AD8313 C14C rev. 0 in addition to providing current gain, the resistor/potentiometer combination between vset and the emitter of the transistor increases the log slope to as much as 45 mv/db, at maximum resistance. this will give an output voltage of 4 v for a 0 dbm input. if no increase in the log slope is required, vset can be connected directly to the emitter of the transistor. effect of waveform type on intercept although it is specified for input levels in dbm (db relative to 1 mw), the AD8313 fundamentally responds to voltage and not to power. a direct consequence of this characteristic is that input signals of equal rms power but differing crest factors will produce different results at the log amps output. the effect of different signal waveforms is to vary the effec- tive value of the log amps intercept upwards or downwards. graphically, this looks like a vertical shift in the log amps trans- fer function. the devices logarithmic slope, however, is in principle not affected. for example, consider the case of the AD8313 being alternately fed from a continuous wave and a single cdma channel of the same rms power. the AD8313s output voltage will differ by the equivalent of 3.55 db (64 mv) over the complete dynamic range of the device (the output for a cdma input being lower). table iii shows the correction factors that should be applied to measure the rms signal strength of a various signal types. a continuous wave input is used as a reference. to measure the rms power of a square-wave, for example, the mv equivalent of the db value given in the table (18 mv/db times 3.01 db) should be subtracted from the output voltage of the AD8313. table iii. shift in AD8313 output for signals with differing crest factors correction factor signal type (add to output reading) cw sine wave 0 db square wave or dc C3.01 db triangular wave +0.9 db gsm channel (all time slots on) + 0.55 db cdma channel +3.55 db pdc channel (all time slots on) +0.58 db gaussian noise +2.51 db evaluation board schematic and layout figure 44 shows the schematic of the evaluation board that was used to characterize the AD8313. note that uninstalled compo- nents are drawn in as dashed. this is a 3-layer board (signal, ground and power), with a duroid dielectric (rt 5880, h = 5 mil, e r = 2.2). fr4 can also be used, but microstrip dimensions must be recalculated because of the different dielectric constant and board height. the trace layout and silkscreen of the signal and power layers are shown in fig- ures 40 to 43. a detail of the pcb footprint for the m soic package and the pads for the matching components are shown in figure 45. the vacant portions of the signal and power layers are filled out with ground plane for general noise suppression. to ensure a low impedance connection between the planes, there are mul- tiple through-hole connections to the rf ground plane. while the ground planes on the power and signal planes are used as general purpose ground returns, any rf grounds related to the input matching network (e.g., c2) are returned directly to the rf internal ground plane. general operation the board should be powered by a single supply in the range, +2.7 v to +5.5 v. the power supply to each of the vpos pins is decoupled by a 10 w resistor and a 0.1 m f capacitor. the two signal inputs are ac-coupled using 680 pf high quality rf capacitors (c1, c2). a 53.6 w resistor across the differential signal inputs (inhi, inlo) combines with the internal 900 w input impedance to give a broadband input impedance of 50.6 w . this termination is not optimal from a noise perspective due to the johnson noise of the 53.6 w resistor. neither does it take account for the AD8313s reactive input impedance or of the decrease over frequency of the resistive component of the i nput impedance. however, it does allow evaluation of the AD8313 over its complete frequency range without having to design multiple matching networks. for optimum performance, a narrowband match can be imple- mented by replacing the 53.6 w resistor (labeled l/r) with an rf inductor and replacing the 680 pf capacitors with appropri- ate values. the section on input matching includes a table of recommended values for selected frequencies and explains the method of calculation. switch 1 is used to select between power-up and power-down modes. connecting the pwdn pin to ground enables normal operation of the AD8313. in the opposite position, the pwdn pin can either be driven externally (sma connector labeled ext enable) to either device state or allowed to float to a disabled device state. the evaluation board ships with the AD8313 configured to operate in rssi measurement mode, the logarithmic output appearing on the sma connector labeled vout. this mode is set by the 0 w resistor (r11), which shorts the vout and vset pins to each other. varying the logarithmic slope the slope of the AD8313 can be increased from its nominal value of 18 mv/db to a maximum of 40 mv/db by removing r11, the 0 w resistor, which shorts vset to vout. vset and vout are now connected through a 20 k w potentiometer. operating in controller mode to put the AD8313 into controller mode, r7 and r11 should be removed, breaking the link between vout and vset. the vset pin can then be driven externally via the sma connector labeled ext vset in adj. increasing output current to increase the output current of v out , set both r3 and r11 to 0 w and install potentiometer r4 (1 k w to 5 k w ).
AD8313 C15C rev. 0 figure 40. layout of signal layer figure 41. layout of power layer figure 42. signal layer silkscreen figure 43. power layer silkscreen
AD8313 C16C rev. 0 c3390C8C8/98 printed in u.s.a. 8-lead m soic package (rm-08) 8 5 4 1 0.122 (3.10) 0.114 (2.90) 0.199 (5.05) 0.187 (4.75) pin 1 0.0256 (0.65) bsc 0.122 (3.10) 0.114 (2.90) seating plane 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) 0.008 (0.20) 0.043 (1.09) 0.037 (0.94) 0.120 (3.05) 0.112 (2.84) 0.011 (0.28) 0.003 (0.08) 0.028 (0.71) 0.016 (0.41) 33 8 27 8 0.120 (3.05) 0.112 (2.84)

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