View CCD153ADC_7223664.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

fairchild imaging, inc., 1801 mccarthy blvd., milpitas, ca 95035 ? (800)325-6975 ? (408) 433-2500 features ? 512 x 1 photosite array ? 13 m x 13 m photosites on 13 m pitch ? high speed: up to 20 mhz data rate ? enhanced spectral response ? low dark signal ? high responsivity ? on-chip clock drivers ? dynamic range typical: 5000:1 ? over 1 v peak-to-peak outputs ? dark and white references contained in sample-and-held output general description the ccd153a is a 512-photoelement linear image sen- sor utilizing charge-coupled device technology. it is designed for visible and very-near-ir imaging applica- tions such as page scanning, facsimile, optical char- acter recognition, earth-resources-satellite telescopes, and other applications which require high resolution, high responsivity, high data rates, and high dynamic range. the ccd153a has been improved and is pin-for-pin compatible with the ccd153 except for the deletion of the end-of-scan waveform (eos out ). the ccd153a ccd 153a 512-element high speed linear image sensor has several new features which may be implemented at the user?s option by supplying input voltages and wave forms different than those required for standard ccd153-type operation. photoelement size is 13 m (0.51mils) x 13 m (0.51 mils) on 13 m (0.51 mils) centers. the devices are manufactured using fairchild imaging?s advanced sec- ond-generation n-channel isoplanar buried-channel technology.
fairchild imaging, inc., 1801 mccarthy blvd., milpitas, ca 95035 ? (800)325-6975 ? (408) 433-2500 2 ccd153a functional description the ccd153a consists of the following functional elements illus- trated in the block diagram and circuit diagram (fig1.). photosites: a row of 512 image sensor elements separated by a diffused channel stop and covered by a silicon dioxide surface pas- sivation layer. image photons pass through the transparent silicon creating hole-electron pairs. the photon generated electrons are accumulated in the photosites. the amount of charge accumulated in each photosite is a linear function of the incident illumination in- tensity and the integration period. the output signal will vary in an analog manner from a thermally generated background level at zero illumination to a maximum at saturation under bright illumination. photogate: the photogate structure, located at the edge of the photosites, provides a bias voltage for the photosites. transfer gate: the transfer gate structure separates the outer edge of the photogates from the analog shift registers. charge- packets generated and accumulated in the photosites are transferred into the transport analog shift registers whenever the transfer gate voltage goes ?high?. all odd-numbered charge packets are trans- ferred into the ?a? transport analog shift register: all even-numbered charge packets are transferred into the ?b? transport analog shift register. the transfer gate also controls the input of charge from v ei into the white reference cells (described below). the time inteval between successive transfer pulses determines the integration time. analog shift registers: four 273-element analog shift regis- ters transport charge towards the output end of the chip. the two inner registers, the transport registers, move the image generated charge packets serially to the two gated charge detectors and am- plifiers. the two outer shift registers, the peripheral registers, accu- mulate charge generated at the chip periphery (by photons passing through unavoidable gaps in the light shield layer, etc.) and trans- port it to charge sinks. the primary shift register clock is t . the complementary phase relationship of the secondary shift register clocks t and t , generated on-chip, provide alternate delivery of charge packets from ?a? and ?b? shift registers to their amplifiers so that the original serial sequential string of video information may be easily demutiplexed off-chip. gated charge detectors & reset gates: each transport ana- log shift register delivers charge packets to a precharged diode. the change in diode potential is linearly proportional to the amount of charge delivered in the charge packet. this potential is applied to the input gate of a mos transistor amplifier (see below), which linearly amplifies the input potential. the diode is reset to the reset drain bias voltage (v rd ) by the reset gate structure. reset occurs when both the internal reset clocks ( t on the ?a: side, t on the ?b? side) are ?high.? each side is reset just before the next charge packet is delivered from its respective transport analog shift register. output amplifiers and sample-and hold gates: each sides? gated charge integrator drives the input of a two-stage linear mos- transistor amplifier. a schematic diagram of this circuit is shown in figure 9 below. the two stages of each amplifier are separated by sample-and-hold gates. the output of the first stage is connected to the input of the second stage whenever the sample-and-hold gates is ?high?. the output of the second stage is connected to the video out pin. the sample-and-hold gates are switching mos transistors: clock- ing these gates results in a sampled-and-held output, thus eliminat- ing the reset clock feedthrough. when on-chip sample-and-hold is used, pin 2 is to be tied to pin 3 and pin 21 is to be tied to pin 22. off- chip sample-and hold pulses can be supplied through pins 2 and 22. the sample-and-hold operation can be disabled by tying pins 2 and 22 to v dd . whenever on-chip sample-and hold is not used, pins 3 and 21 should be left unconnected. clock driver circuits: two mosfet clock-driver circuits on- chip allow sample-and-held operation of the ccd153a with only two externally-supplied clocks: the square-wave primary shift register transport clock t , which determines the output data rate, and the transfer clock x , which determines the integration time. dark and white reference cells and circuitry ? at each
fairchild imaging, inc., 1801 mccarthy blvd., milpitas, ca 95035 ? (800)325-6975 ? (408) 433-2500 3 ccd153a end of the 512-photosite array there are four additional sensing ele- ments covered by opaque metallization. these ?dark reference cells? provide four charge packets (two on each side) at each end of the serial video output which indicate the typical dark (non-illumi- nated) signal level. in addition, two ?white reference cells? (one per side) are input into the serial video outputs after the last pixel (#512) and the dark reference cells. (refer to the section on the transfer gate, above) each white reference cell generates an output signal pulse approximately 80% of the amplitude of a photosite saturation (maximum) signal. these cells may be used as inputs to external dc restoration and/or automatic gain control circuits. white refer- ence amplitude is slightly dependent on exposure, especially at in- frared wavelengths definition of term charge-coupled device ? a charge-coupled device is a semi- conductor device in which finite isolated charge-packets are trans- ported from one position in the semiconductor to an adjacent posi- tion by sequential clocking of an array of gates. the charge-packets are minority carriers with respect to the semiconductor substrate. transfer clock x ? the transfer clock is the voltage waveform applied to the transfer gate to move the accumulated charge from the image sensor elements to the ccd transport shift registers. transport clock t ? the transport clock is the clock applied to the gates of the ccd transport shift registers to move the charge- packets received from the image sensor elements to the gate charge- detector/amplifiers. sample-and-hold clock ( shca, shcb ) ? the voltage wave- form applied to the sample-and-hold gates in the output amplifiers to create a continuous sampled video signal at the output. the sample-and-hold feature may be defeated by connecting sh(a+b) to v dd . isolation cell ? a site on-chip producing an element in the video output that serves as a buffer between valid video data and dark reference signals. the output from an isolation cell contains no valid information and should be ignored. dynamic range ? the saturation exposure divided by the rms temporal noise equivalent exposure. dynamic range is sometimes defined in terms of peak-to-peak noise. to compare the two defini- tions a factor of four to six is generally appropriate in that peak-to- peak noise is approximately equal to four to six times rms noise. rms noise equivalent exposure ? the exposure level that gives an output signal to the rms noise level at the output in the dark. fig. 2 test load configuration saturation exposure ? the minimum exposure level that will provide a saturation output signal. exposure is equal to the light intensity times the photosites integration time. charge transfer efficiency ? percentage of valid charge in- formation that is transferred between each successive stage of the transport registers. responsivity ? the output signal voltage per unit exposure for a specified spectral type of radiation. responsivity equals output volt- age divided by exposure. total photoresponse non-uniformity ? the difference of the response levels of the most and the least sensitive element under uniform illumination. measurement of prnu excludes first and last elements. dark signal ? the output signal in the dark caused by thermally generated electrons that is a linear function of the integration time and highly sensitive to temperature. (see accompanying photos for details of definition.) saturation output voltage ? the maximum usable signal out- put voltage. charge transfer efficiency decreases sharply when the saturation output voltage is exceeded. integration time ? the time interval between the falling edge of any two successive transfer pulses ( x ). the integration is the time allowed for the photosites to collect charge. pixel - a picture element (photosite).
fairchild imaging, inc., 1801 mccarthy blvd., milpitas, ca 95035 ? (800)325-6975 ? (408) 433-2500 ccd153a 4
fairchild imaging, inc., 1801 mccarthy blvd., milpitas, ca 95035 ? (800)325-6975 ? (408) 433-2500 5 ccd153a
fairchild imaging, inc., 1801 mccarthy blvd., milpitas, ca 95035 ? (800)325-6975 ? (408) 433-2500 6 ccd153a fig. 3 test load configuration typical performance curves
fairchild imaging, inc., 1801 mccarthy blvd., milpitas, ca 95035 ? (800)325-6975 ? (408) 433-2500 7 ccd153a fig. 4 photoresponse non-uniformity parameters (prnu)
fairchild imaging, inc., 1801 mccarthy blvd., milpitas, ca 95035 ? (800)325-6975 ? (408) 433-2500 8 ccd153a fig. 5 photoresponse non-uniformity parameters (prnu) fig. 6 dark signal parameters (ds)
fairchild imaging, inc., 1801 mccarthy blvd., milpitas, ca 95035 ? (800)325-6975 ? (408) 433-2500 9 ccd153a fig. 6 dark signal parameters (ds)
fairchild imaging, inc., 1801 mccarthy blvd., milpitas, ca 95035 ? (800)325-6975 ? (408) 433-2500 10 ccd153a fig. 7 video output timing photographs
fairchild imaging, inc., 1801 mccarthy blvd., milpitas, ca 95035 ? (800)325-6975 ? (408) 433-2500 11 ccd153a
fairchild imaging, inc., 1801 mccarthy blvd., milpitas, ca 95035 ? (800)325-6975 ? (408) 433-2500 12 ccd153a device care and operation glass may be cleaned by saturating a cotton swab in alcohol and lightly wiping the surface. rinse off the alcohol with deionized wa- ter. allow the glass to dry, preferably by blowing with filtered dry n 2 or air. it is important to note in design and applications considerations that the devices are very sensitive to thermal conditions. the dark sig- nal dc and low frequency components approximately double for ev- ery 5o c temperature increase and single-pixel dark signal non-uni- formities approximately double for every 8o c temperature increase. the devices may be cooled to achieve very long integration times and very low light level capability. order information order CCD153ADC where ?d? stands for a ceramic package and ?c? for commercial temperature range. also available are printed circuit boards that include all the neces- sary clocks, logic drivers and video amplifiers to operate the ccd153a. the boards are fully assembled and tested and require only one power supply for operation (+20v). the printed circuit board order codes are ccd153db. the ccd153a,143a and 133a can be operated in the same printed circuit board. the 24 pin ccd133a and 153a devices are to be placed at the center of the 28 pin socket on the printed circuit board.

▲Up To Search▲

Price & Availability of CCD153ADC

	To Download CCD153ADC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .