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227 hd66702 (dot matrix liquid crystal display controller/driver) description the hd66702 dot-matrix liquid crystal display controller and driver lsi displays alphanumerics, japanese kana characters, and symbols. it can be configured to drive a dot-matrix liquid crystal display under the control of a 4- or 8-bit microprocessor. since all the functions required for driving a dot-matrix liquid crystal display are internally provided on one chip, a minimal system can be interfaced with this controller/driver. a single hd66702 can display up to two 20-character lines. the low 3-v power supply of the hd66702 under development is suitable for any portable battery-driven product requiring low power dissipation. features 5 7 and 5 10 dot matrix possible 80 8-bit display ram (80 characters max.) 7,200-bit character generator rom ? 160 character fonts (5 7 dot) ? 32 character fonts (5 10 dot) 64 8-bit character generator ram ? 8 character fonts (5 7 dot) ? 4 character fonts (5 10 dot) 16-common 100-segment liquid crystal display driver programmable duty cycles ? 1/8 for one line of 5 7 dots with cursor ? 1/11 for one line of 5 10 dots with cursor ? 1/16 for two lines of 5 7 dots with cursor
hd66702 228 maximum display characters ? one line 1/8 duty cycle, 20-char. 1-line 1/11 duty cycle, 20-char. 1 -line ? two lines 1/16 duty cycle, 20-char. 2-line wide range of instruction functions ? display clear, cursor home, display on/off, cursor on/off, display character blink, cursor shift, display shift choice of power supply (v cc ): 4.5 to 5.5v (standard), 2.7 to 5.5v (low voltage) automatic reset circuit that initializes the controller/driver after power on (standard version only) independent lcd drive voltage driven off of the logic power supply (v cc ): 3.0 to 8.3v low power dissipation lqfp2020-144-pin, chip, chip wtith bump ordering information type no. package operating voltage rom font hcd66702ra00l 144-pin-chip 2.7 to 5.5v standard japanese hcd66702ra00bp 144-pin-chip with bump 2.7 to 5.5v standard japanese hcd66702ra01l 144-pin-chip 2.7 to 5.5v communication system hcd66702ra02l 144-pin-chip 2.7 to 5.5v european font hd66702ra00f fp-144a 4.5 to 5.5v standard japanese hd66702ra00fl fp-144a 2.7 to 5.5v standard japanese hd66702ra01f fp-144a 4.5 to 5.5v communication font HD66702RA02F fp-144a 4.5 to 5.5v european font
hd66702 229 lcd-ii family comparison item lcd-ii (hd44780u) hd66702 hd66710 hd66712u power supply voltage 2.7v to 5.5v 5 v 10 % (standard) 2.7 v to 5.5v (low voltage) 2.7v to 5.5v 2.7v to 5.5v liquid crystal drive voltage 3.0v to 11 v 3.0v to 8.3v 3.0v to 13.0v 2.7v to 11.0v maximum display digits per chip 8 characters 2 lines 20 characters 2 lines 16 characters 2 lines/ 8 characters 4 lines 24 characters 2 lines/ 12 characters 4 lines segment display none none 40 segments 60 segments display duty cycle 1/8, 1/11, and 1/16 1/8, 1/11, and 1/16 1/17 and 1/33 1/17 and 1/33 cgrom 9,920 bits (208 5 8 dot characters and 32 5 10 dot characters) 7,200 bits (160 5 7 dot characters and 32 5 10 dot characters) 9,600 bits (240 5 8 dot characters) 9,600 bits (240 5 8 dot characters) cgram 64 bytes 64 bytes 64 bytes 64 bytes ddram 80 bytes 80 bytes 80 bytes 80 bytes segram none none 8 bytes 16 bytes segment signals 40 100 40 60 common signals 16 16 33 34 liquid crystal drive waveform abbb bleeder resistor for lcd power supply external (adjustable) external (adjustable) external (adjustable) external (adjustable) clock source external resistor or external clock external resistor or external clock external resistor or external clock external resistor or external clock r f oscillation frequency (frame frequency) 270 khz 30% (59 to 110 hz for 1/8 and 1/16 duty cycle; 43 to 80 hz for 1/11 duty cycle) 320 khz 30% (70 to 130 hz for 1/8 and 1/16 duty cycle; 51 to 95 hz for 1/11 duty cycle) 270 khz 30% (56 to 103 hz for 1/17 duty cycle; 57 to 106 hz for 1/33 duty cycle) 270 khz 30% (56 to 103 hz for 1/17 duty cycle; 57 to 106 hz for 1/33 duty cycle) r f resistance 91 k w : 5-v operation; 75 k w : 3-v operation 68 k w : 5-v operation; 56 k w : (3-v operation) 91 k w : 5-v operation; 75 k w : 3-v operation 130 k w : 5-v operation 110 k w : 3-v operation
hd66702 230 item lcd-ii (hd44780) hd66702 hd66710 hd66712u liquid crystal voltage booster circuit none none 2-3 times step-up circuit 2-3 times step-up circuit extension driver control signal independent control signal independent control signal used in common with a driver output pin independent control signal reset function power on automatic reset power on automatic reset power on automatic reset power on automatic reset or reset input instructions lcd-ii (hd44780) fully compatible with the lcd-ii uppercompatible with the lcd-ii upper compatible with the lcd-ii number of displayed lines 1 or 2 1 or 2 1, 2, or 4 1, 2, or 4 low power mode none none available available horizontal scroll character unit character unit dot unit dot unit bus interface 4 bits/8 bits 4 bits/8 bits 4 bits/8 bits serial; 4 bits/8 bits cpu bus timing 2 mhz: 5-v operation; 1 mhz: 3-v operation 1 mhz 2 mhz: 5-v operation; 1 mhz: 3-v operation 2 mhz: 5-v operation; 1 mhz: 3-v operation package qfp-1420-80 80-pin bare chip lqfp-2020-144 144-pin bare chip qfp-1420-100 tqfp-1414-100 100-pin bare chip tcp-128 128-pin bare chip
hd66702 231 hd66702 block diagram display data ram (ddram) 80 8 bits character generator rom (cgrom) 7,200 bits character generator ram (cgram) 64 bytes instruction register (ir) timing generator common signal driver 16-bit shift register segment signal driver 100-bit latch circuit 100-bit shift register parallel/serial converter and attribute circuit lcd drive voltage selector address counter mpu inter- face input/ output buffer busy flag ext data register (dr) cursor and blink controller cpg cl1 cl2 m d rs r/w db4 to db7 e instruction decoder osc1 osc2 com1 to com16 seg1 to seg100 8 8 8 7 5 5 100 7 8 7 8 7 16 test v cc gnd v1 v2 v3 v4 v5 db0 to db3 reset circuit acl 8
hd66702 232 hd66702 pad arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 seg71 seg72 seg73 seg74 seg75 seg76 seg77 seg78 seg79 seg80 seg81 seg82 seg83 seg84 seg85 seg86 seg87 seg88 seg89 seg90 seg91 seg92 seg93 seg94 seg95 seg96 seg97 seg98 seg99 seg100 com16 com15 com14 com13 com12 com11 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 gnd osc2 osc1 v cc v cc v1 v2 v3 v4 v5 cl1 cl2 m d ext test * gnd rs r/w e db0 db1 db2 db3 db4 db5 db6 db7 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 seg56 seg57 seg58 seg59 seg60 seg61 seg62 seg63 seg64 seg65 seg66 seg67 seg68 seg69 seg70 note: * : test pins to be grounded : power supply pins : power supply pins (ground) : input pins : output pins : input/output pins chip size = 5.20 5.20 mm minimum pad pitch = 130 m pad size = 90 90 m hd66702 type code (top view)
hd66702 233 hcd66702 pad location coordinates pad no. pad name x (m) y (m) pad no. pad name x (m) y (m) 1 seg34 C2475 2350 31 seg4 C2475 C1600 2 seg33 C2475 2205 32 seg3 C2475 C1735 3 seg32 C2475 2065 33 seg2 C2475 C1870 4 seg31 C2475 1925 34 seg1 C2475 C2010 5 seg30 C2475 1790 35 gnd C2475 C2180 6 seg29 C2475 1655 36 osc2 C2475 C2325 7 seg28 C2475 1525 37 osc1 C2445 C2475 8 seg27 C2475 1395 38 v cc C2305 C2475 9 seg26 C2475 1265 39 v cc C2165 C2475 10 seg25 C2475 1135 40 v1 C2025 C2475 11 seg24 C2475 1005 41 v2 C1875 C2475 12 seg23 C2475 875 42 v3 C1745 C2475 13 seg22 C2475 745 43 v4 C1595 C2475 14 seg21 C2475 615 44 v5 C1465 C2475 15 seg20 C2475 485 45 cl1 C1335 C2475 16 seg19 C2475 355 46 cl2 C1185 C2475 17 seg18 C2475 225 47 m C1055 C2475 18 seg17 C2475 95 48 d C905 C2475 19 seg16 C2475 C35 49 ext C775 C2475 20 seg15 C2475 C165 50 test C625 C2475 21 seg14 C2475 C295 51 gnd C495 C2475 22 seg13 C2475 C425 52 rs C345 C2475 23 seg12 C2475 C555 53 r/ : C195 C2475 24 seg11 C2475 C685 54 e C45 C2475 25 seg10 C2475 C815 55 db0 85 C2475 26 seg9 C2475 C945 56 db1 235 C2475 27 seg8 C2475 C1075 57 db2 365 C2475 28 seg7 C2475 C1205 58 db3 515 C2475 29 seg6 C2475 C1335 59 db4 645 C2475 30 seg5 C2475 C1465 60 db5 795 C2475
hd66702 234 pad no. pad name x (m) y (m) pad no. pad name x (m) y (m) 61 db6 925 C2475 91 seg88 2475 95 62 db7 1075 C2475 92 seg87 2475 225 63 com1 1205 C2475 93 seg86 2475 355 64 com2 1335 C2475 94 seg85 2475 485 65 com3 1465 C2475 95 seg84 2475 615 66 com4 1595 C2475 96 seg83 2475 745 67 com5 1725 C2475 97 seg82 2475 875 68 com6 1855 C2475 98 seg81 2475 1005 69 com7 1990 C2475 99 seg80 2475 1135 70 com8 2125 C2475 100 seg79 2475 1265 71 com9 2265 C2475 101 seg78 2475 1395 72 com10 2410 C2475 102 seg77 2475 1525 73 com11 2475 C2290 103 seg76 2475 1655 74 com12 2475 C2145 104 seg75 2475 1790 75 com13 2475 C2005 105 seg74 2475 1925 76 com14 2475 C1865 106 seg73 2475 2065 77 com15 2475 C1730 107 seg72 2475 2205 78 com16 2475 C1595 108 seg71 2475 2350 79 seg100 2475 C1465 109 seg70 2320 2475 80 seg99 2475 C1335 110 seg69 2175 2475 81 seg98 2475 C1205 111 seg68 2035 2475 82 seg97 2475 C1075 112 seg67 1895 2475 83 seg96 2475 C945 113 seg66 1760 2475 84 seg95 2475 C815 114 seg65 1625 2475 85 seg94 2475 C685 115 seg64 1495 2475 86 seg93 2475 C555 116 seg63 1365 2475 87 seg92 2475 C425 117 seg62 1235 2475 88 seg91 2475 C295 118 seg61 1105 2475 89 seg90 2475 C165 119 seg60 975 2475 90 seg89 2475 C35 120 seg59 845 2475
hd66702 235 pad no. pad name x (m) y (m) pad no. pad name x (m) y (m) 121 seg58 715 2475 133 seg46 C845 2475 122 seg57 585 2475 134 seg45 C975 2475 123 seg56 455 2475 135 seg44 C1105 2475 124 seg55 325 2475 136 seg43 C1235 2475 125 seg54 195 2475 137 seg42 C1365 2475 126 seg53 65 2475 138 seg41 C1495 2475 127 seg52 C65 2475 139 seg40 C1625 2475 128 seg51 C195 2475 140 seg39 C1760 2475 129 seg50 C325 2475 141 seg38 C1895 2475 130 seg49 C455 2475 142 seg37 C2035 2475 131 seg48 C585 2475 143 seg36 C2175 2475 132 seg47 C715 2475 144 seg35 C2320 2475 notes: 1. coordinates originate from the chip center. 2. the above are preliminary specifications, and may be subject to change.
hd66702 236 hd66702 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 seg71 seg72 seg73 seg74 seg75 seg76 seg77 seg78 seg79 seg80 seg81 seg82 seg83 seg84 seg85 seg86 seg87 seg88 seg89 seg90 seg91 seg92 seg93 seg94 seg95 seg96 seg97 seg98 seg99 seg100 com16 com15 com14 com13 com12 com11 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 gnd osc2 osc1 v cc v cc v1 v2 v3 v4 v5 cl1 cl2 m d ext test gnd rs r/w e db0 db1 db2 db3 db4 db5 db6 db7 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 seg56 seg57 seg58 seg59 seg60 seg61 seg62 seg63 seg64 seg65 seg66 seg67 seg68 seg69 seg70 * note: * : test pins to be grounded : power supply pins : power supply pins (ground) : input pins : output pins : input/output pins fp-144a (top view)
hd66702 237 pin functions table 1 pin functional description signal i/o device interfaced with function rs i mpu selects registers 0: instruction register (for write) busy flag: address counter (for read) 1: data register (for write and read) r/ : i mpu selects read or write 0: write 1: read e i mpu starts data read/write db4 to db7 i/o mpu four high order bidirectional tristate data bus pins. used for data transfer between the mpu and the hd66702. db7 can be used as a busy flag. db0 to db3 i/o mpu four low order bidirectional tristate data bus pins. used for data transfer between the mpu and the hd66702. these pins are not used during 4-bit operation. cl1 o extension driver clock to latch serial data d sent to the extension driver cl2 o extension driver clock to shift serial data d m o extension driver switch signal for converting the liquid crystal drive waveform to ac d o extension driver character pattern data corresponding to each segment signal com1 to com16 o lcd common signals that are not used are changed to non- selection waveforms. com9 to com16 are non- selection waveforms at 1/8 duty factor and com12 to com16 are non-selection waveforms at 1/11 duty factor. seg1 to seg100 o lcd segment signals v1 to v5 power supply power supply for lcd drive v cc , gnd power supply v cc : +5v or +3v, gnd: 0v test i test pin, which must be grounded ext i 0: enables extension driver control signals cl1, cl2, m, and d to be output from its corresponding pins. 1: drives cl1, cl2, m, and d as tristate, lowering power dissipation. osc1, osc2 pins for connecting the registers of the internal clock oscillation. when the pin input is an external clock, it must be input to osc1.
hd66702 238 function description registers the hd66702 has two 8-bit registers, an instruction register (ir) and a data register (dr). the ir stores instruction codes, such as display clear and cursor shift, and address information for display data ram (ddram) and character generator ram (cgram). the ir can only be written from the mpu. the dr temporarily stores data to be written into ddram or cgram. data written into the dr from the mpu is auto matically written into ddram or cgram by an internal operation. the dr is also used for data storage when reading data from ddram or cgram. when address information is written into the ir, data is read and then stored into the dr from ddram or cgram by an internal operation. data transfer between the mpu is then comp leted when the mpu reads the dr. after the read, d ata in ddram or cgram at the next address is sent to the dr for the next read from the mpu. by the register selector (rs) signal, these two registers can be selected (table 2). busy flag (bf) when the busy flag is 1, the hd66702 is in the internal operation mode, and the next instruction will not be accepted. when rs = 0 and r/w = 1 (table 2), the busy flag is output to db7. the next instruction must be written after ensuring that the busy flag is 0. address counter (ac) the address counter (ac) assigns addresses to both ddram and cgram. when an address of an instruction is written into the ir, the address information is sent from the ir to the ac. selection of either ddram or cgram is also determined concurrently by the instruction. after writing into (reading from) ddram or cgram, the ac is automatically incremented by 1 (decremented by 1). the ac contents are then output to db0 to db6 when rs = 0 and r/ : = 1 (table 2). table 2 register selection rs r/ : : operation 0 0 ir write as an internal operation (display clear, etc.) 0 1 read busy flag (db7) and address counter (db0 to db6) 1 0 dr write as an internal operation (dr to ddram or cgram) 1 1 dr read as an internal operation (ddram or cgram to dr)
hd66702 239 display data ram (ddram) display data ram (ddram) stores display data represented in 8-bit character codes. its extended capacity is 80 8 bits, or 80 characters. the area in display data ram (ddram) that is not used for display can be used as general data ram. see figure 1 for the relationships between ddram addresses and positions on the liquid crystal display. the ddram address (a dd ) is set in the address counter (ac) as hexadecimal. 1-line display (n = 0) (figure 2) ? when there are fewer than 80 display characters, the display begins at the head position. for example, if using only the hd66702, 20 characters are displayed. see figure 3. when the display shift operation is performed, the ddram address shifts. see figure 3. ac6 ac5 ac4 ac3 ac2 ac1 ac0 1001110 ac (hexadecimal) example: ddram address 4e high order bits low order bits figure 1 ddram address 00 01 02 03 04 4e 4f ddram address (hexadecimal) display position (digit) 123 45 7980 . . . . . . . . . . . . . . . . . . figure 2 1-line display ddram address display position 12345 678910111213141516 17 18 19 20 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 for shift left 10 11 12 13 14 for shift right 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 4f figure 3 1-line by 20-character display example
hd66702 240 2-line display (n = 1) (figure 4) ? case 1: when the number of display characters is less than 40 2 lines, the two lines are displayed from the head. note that the first line end address and the second line start address are not consecutive. for example, when just the hd66702 is used, 20 characters 2 lines are displayed. see figure 5. when display shift operation is performed, the ddram address shifts. see figure 5. 00 01 02 03 04 26 27 ddram address (hexadecimal) display position 123 45 3940 . . . . . . . . . . . . . . . . . . 40 41 42 43 44 66 67 . . . . . . . . . . . . . . . . . . figure 4 2-line display ddram address display position 12345 678910111213141516 17 18 19 20 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 for shift left for shift right 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 14 54 27 67 figure 5 2-line by 20-character display example
hd66702 241 ? case 2: for a 28-character 2-line display, the hd66702 can be extended using one 40-output extension driver. see figure 6. when display shift operation is performed, the ddram address shifts. see figure 6. ddram address display position 1 28 23456789101112131415161718192021222324252627 00 1b 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a for shift left 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 27 40 5b 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 56 57 58 59 5a hd66702 display extension driver display 02 01 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a for shift right 5b 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 56 57 58 59 5a 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 56 57 58 59 5a 67 1b 1c 5c figure 6 2-line by 28-character display example
hd66702 242 character generator rom (cgrom) the character generator rom generates 5 7 dot or 5 10 dot character patterns from 8-bit character codes (table 5). it can generate 160 5 7 dot character patterns and 32 5 10 dot character patterns. user-defined character patterns are also available by mask-programmed rom. character generator ram (cgram) in the character generator ram, the user can rewrite character patterns by program. for 5 7 dots, eight character patterns can be written, and for 5 10 dots, four character patterns can be written. write the character codes at the addresses shown as the left column of table 5 to show the character patterns stored in cgram. see table 6 for the relationship between cgram addresses and data and display patterns. areas that are not used for display can be used as general data ram. modifying character patterns character pattern development procedure the following operations correspond to the numbers listed in figure 7: 1. determine the correspondence between character codes and character patterns. 2. create a listing indicating the correspondence between eprom addresses and data. 3. program the character patterns into the eprom. 4. send the eprom to hitachi. 5. computer processing on the eprom is performed at hitachi to create a character pattern listing, which is sent to the user. 6. if there are no problems within the character pattern listing, a trial lsi is created at hitachi and samples are sent to the user for evaluation. when it is confirmed by the user that the character patterns are correctly written, mass production of the lsi proceeds at hitachi.
hd66702 243 determine character patterns create eprom address data listing write eprom eprom ? hitachi computer processing create character pattern listing evaluate character patterns ok? art work sample evaluation ok? masking trial sample no yes no yes m/t 1 3 2 4 5 6 note: for a description of the numbers used in this figure, refer to the preceding page. user hitachi mass production start figure 7 character pattern development procedure
hd66702 244 programming character patterns this section explains the correspondence between addresses and data used to program character patterns in eprom. the hd66702 character generator rom can generate 160 5 7 dot character patterns and 32 5 10 dot character patterns for a total of 192 different character patterns. ? 5 7 dot character pattern eprom address data and character pattern data correspond with each other to form a 5 7 dot character pattern (table 3). table 3 example of correspondence between eprom address data and character pattern (5 7 dots) a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 data o4 o3 o2 o1 o0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1 0 1 0 0 1 0 eprom address character code line position fill line 8 (cursor position) with 0s 0 0 0 0 0 1 1 1 1 0 1 0 0 0 1 1 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 0 0 1 0 1 0 0 0 1 lsb notes: 1. eprom addresses a10 to a3 correspond to a character code. 2. eprom addresses a2 to a0 specify a line position of the character pattern. 3. eprom data o4 to o0 correspond to character pattern data. 4. a lit display position (black) corresponds to a 1. 5. line 8 (cursor position) of the character pattern must be blanked with 0s. 6. eprom data o5 to o7 are not used.
hd66702 245 ? 5 10 dot character pattern eprom address data and character pattern data correspond with each other to form a 5 10 dot character pattern (table 4). ? handling unused character patterns 1. eprom data outside the character pattern area: ignored by the character generator rom for display operation so 0 or 1 is arbitrary. 2. eprom data in cgram area: ignored by the character generator rom for display operation so 0 or 1 is arbitrary. 3. eprom data used when the user does not use any hd66702 character pattern: according to the user application, handled in one of the two ways listed as follows. a. when unused character patterns are not programmed: if an unused character code is written into ddram, all its dots are lit. by not programing a character pattern, all of its bits become lit. (this is due to the eprom being filled with 1s after it is erased.) b. when unused character patterns are programmed as 0s: nothing is displayed even if unused character codes are written into ddram. (this is equivalent to a space.) table 4 example of correspondence between eprom address data and character pattern (5 10 dots) a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 data o4 o3 o2 o1 o0 0 0 1 0 0 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 1 0 1 0 1 1 1 1 0 0 0 1 eprom address character code line position fill line 11 (cursor position) with 0s lsb 1 0 1 1 1 0 1 1 1 1 0 0 1 0 0 0 1 1 0 0 1 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 1 1 1 notes: 1. eprom addresses a10 to a3 correspond to a character code. set a8 and a9 of character pattern lines 9, 10, and 11 to 0s. 2. eprom addresses a2 to a0 specify a line position of the character pattern. 3. eprom data o4 to o0 correspond to character pattern data. 4. a lit display position (black) corresponds to a 1. 5. blank out line 11 (cursor position) of the character pattern with 0s. 6. eprom data o5 to o7 are not used.
hd66702 246 table 5 correspondence between character codes and character patterns (rom code: a00) xxxx0000 xxxx0001 xxxx0010 xxxx0011 xxxx0100 xxxx0101 xxxx0110 xxxx0111 xxxx1000 xxxx1001 xxxx1010 xxxx1011 xxxx1100 xxxx1101 xxxx1110 xxxx1111 0000 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111 upper 4 bits lower 4 bits cg ram (1) (2) (3) (4) (5) (6) (7) (8) (1) (2) (3) (4) (5) (6) (7) (8) note: the user can specify any pattern for character-generator ram.
hd66702 247 table 5 correspondence between character codes and character patterns (rom code: a01) xxxx0000 xxxx0001 xxxx0010 xxxx0011 xxxx0100 xxxx0101 xxxx0110 xxxx0111 xxxx1000 xxxx1001 xxxx1010 xxxx1011 xxxx1100 xxxx1101 xxxx1110 xxxx1111 0000 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111 upper 4 bits lower 4 bits cg ram (1) (2) (3) (4) (5) (6) (7) (8) (1) (2) (3) (4) (5) (6) (7) (8)
hd66702 248 table 5 correspondence between character codes and character patterns (rom code: a02) xxxx0000 xxxx0001 xxxx0010 xxxx0011 xxxx0100 xxxx0101 xxxx0110 xxxx0111 xxxx1000 xxxx1001 xxxx1010 xxxx1011 xxxx1100 xxxx1101 xxxx1110 xxxx1111 0000 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111 upper 4 bits lower 4 bits cg ram (1) (2) (3) (4) (5) (6) (7) (8) (1) (2) (3) (4) (5) (6) (7) (8)
hd66702 249 table 6 relationship between cgram addresses, character codes (ddram) and character patterns (cgram data) character codes (ddram data) cgram address character patterns (cgram data) 7 6 5 4 3 2 1 0 0 0 0 0 * 0 0 0 0 0 0 0 * 0 0 1 0 0 0 0 * 1 1 1 5 4 3 2 1 0 0 0 0 0 0 1 1 1 1 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * * * * * * * * * * * * * * * * * high low high low high low character pattern cursor position 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 0 1 0 0 1 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 1 1 0 0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 1 0 0 0 1 1 0 1 0 0 0 for 5 ? 7 dot character patterns notes: 1. character code bits 0 to 2 correspond to cgram address bits 3 to 5 (3 bits: 8 types). 2. cgram address bits 0 to 2 designate the character pattern line position. the 8th line is the cursor position and its display is formed by a logical or with the cursor. maintain the 8th line data, corresponding to the cursor display position, at 0 as the cursor display. if the 8th line data is 1, 1 bits will light up the 8th line regardless of the cursor presence. 3. character pattern row positions correspond to cgram data bits 0 to 4 (bit 4 being at the left ). since cgram data bits 5 to 7 are not used for display, they can be used for general data ram. 4. as shown tables 5 and 6, cgram character patterns are selected when character code bits 4 to 7 are all 0. however, since character code bit 3 has no effect, the r display example above can be selected by either character code 00h or 08h. 5. 1 for cgram data corresponds to display selection and 0 to non-selection. * indicates no effect.
hd66702 250 table 6 relationship between cgram addresses, character codes (ddram) and character patterns (cgram data) (cont) character codes (ddram data) cgram address character patterns (cgram data) 7 6 5 4 3 2 1 0 0 0 0 0 * 0 0 0 0 0 0 1 1 5 4 3 2 1 0 0 0 1 1 7 6 5 4 3 2 1 0 * * * * * * * * * * * * * * * * * * * * * * * * high low high low high low character pattern cursor position 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 * * * * * ** 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 * * * * * * * * * * * * * * * * for 5 ? 10 dot character patterns notes: 1. character code bits 1 and 2 correspond to cgram address bits 4 and 5 (2 bits: 4 types). 2. cgram address bits 0 to 3 designate the character pattern line position. the 11th line is the cursor position and its display is formed by a logical or with the cursor. maintain the 11th line data corresponding to the cursor display positon at 0 as the cursor display. if the 11th line data is 1, 1 bits will light up the 11th line regardless of the cursor presence. since lines 12 to 16 are not used for display, they can be used for general data ram. 3. character pattern row positions are the same as 5 7 dot character pattern positions. 4. cgram character patterns are selected when character code bits 4 to 7 are all 0. however, since character code bits 0 and 3 have no effect, the p display example above can be selected by character codes 00h, 01h, 08h, and 09h. 5. 1 for cgram data corresponds to display selection and 0 to non-selection. * indicates no effect.
hd66702 251 timing generation circuit the timing generation circuit generates timing signals for the operation of internal circuits such as ddram, cgrom and cgram. ram read timing for display and internal operation timing by mpu access are generated separately to avoid interfering with each other. therefore, when writing data to ddram, for example, there will be no undesirable interferences, such as flickering, in areas other than the display area. liquid crystal display driver circuit the liquid crystal display driver circuit consists of 16 common signal drivers and 100 segment signal drivers. when the character font and number of lines are selected by a program, the required common signal drivers automatically output drive waveforms, while the other common signal drivers continue to output non-selection waveforms. sending serial data always starts at the display data character pattern corresponding to the last address of the display data ram (ddram). since serial data is latched when the display data character pattern corresponding to the starting address enters the internal shift register, the hd66702 drives from the head display. cursor/blink control circuit the cursor/blink control circuit generates the cursor or character blinking. the cursor or the blinking will appear with the digit located at the display data ram (ddram) address set in the address counter (ac). for example (figure 8), when the address counter is 08h, the cursor position is displayed at ddram address 08h. ac6 0 ac5 0 ac4 0 ac3 1 ac2 0 ac1 0 ac0 0 1 00 2 01 3 02 4 03 5 04 6 05 7 06 8 07 9 08 10 09 11 0a 1 00 40 2 01 41 3 02 42 4 03 43 5 04 44 6 05 45 7 06 46 8 07 47 9 08 48 10 09 49 11 0a 4a ac cursor position cursor position display position ddram address (hexadecimal) display position ddram address (hexadecimal) for a 1-line display for a 2-line display note: the cursor or blinking appears when the address counter (ac) selects the character generator ram (cgram). however, the cursor and blinking become meaningless. the cursor or blinking is displayed in the meaningless position when the ac is a cgram address. figure 8 cursor/blink display example
hd66702 252 interfacing to the mpu the hd66702 can send data in either two 4-bit operations or one 8-bit operation, thus allowing interfacing with 4- or 8-bit mpus. for 4-bit interface data, only four bus lines (db4 to db7) are used for transfer. bus lines db0 to db3 are disabled. the data transfer between the hd66702 and the mpu is completed after the 4-bit data has been transferred twice. as for the order of data transfer, the four high order bits (for 8-bit operation, db4 to db7) are transferred before the four low order bits (for 8-bit operation, db0 to db3). the busy flag must be checked (one instruction) after the 4-bit data has been transferred twice. two more 4-bit operations then transfer the busy flag and address counter data. for 8-bit interface data, all eight bus lines (db0 to db7) are used. rs r/w e ir7 ir6 ir5 ir4 bf ac6 ac5 ac4 db7 db6 db5 db4 instruction register (ir) write busy flag (bf) and address counter (ac) read data register (dr) read ir3 ir2 ir1 ir0 ac3 ac2 ac1 ac0 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 figure 9 4-bit transfer example
hd66702 253 reset function initializing by internal reset circuit an internal reset circuit automatically initializes the hd66702 when the power is turned on. the following instructions are executed during the initialization. the busy flag (bf) is kept in the busy state until the initialization ends (bf = 1). the busy state lasts for 15 ms after v cc rises to 4.5v, or 40 ms after v cc rises to 2.7v. 1. display clear 2. function set: dl = 1; 8-bit interface data n = 0; 1-line display f = 0; 5 7 dot character font 3. display on/off control: d = 0; display off c = 0; cursor off b = 0; blinking off 4. entry mode set: i/d = 1; increment by 1 s = 0; no shift note: if the electrical characteristics conditions listed under the table power supply conditions using internal reset circuit are not met, the internal reset circuit will not operate normally and will fail to initialize the hd66702. for such a case, initial-ization must be performed by the mpu as explained in the section, initializing by instruction.
hd66702 254 instructions outline only the instruction register (ir) and the data register (dr) of the hd66702 can be controlled by the mpu. before starting the internal oper ation of the hd66702, control information is temporarily stored into these registers to allow interfacing with various mpus, which oper ate at different speeds, or various peripheral control devices. the internal operation of the hd66702 is determined by signals sent from the mpu. these signals, which include register s election (rs), read/write (r/ : ), and the data bus (db0 to db7), make up the hd66702 instructions (table 7). there are four categories of instructions that: designate hd66702 functions, such as display format, data length, etc. set internal ram addresses perform data transfer with internal ram perform miscellaneous functions normally, instructions that perform data transfer with internal ram are used the most. however, auto- incrementation by 1 (or auto-decrementation by 1) of internal hd66702 ram addresses after each data write can lighten the program load of the mpu. since the display shift instru ction (table 12) can perform concurrently with display data write, the user can minimize system development time with maximum programming efficiency. when an instruction is being executed for internal operation, no instruction other than the busy flag/address read instruction can be executed. because the busy flag is set to 1 while an instruction is being executed, check it to make sure it is 0 before sending another instruction from the mpu. note: be sure the hd66702 is not in the busy state (bf = 0) before sending an instruction from the mpu to the hd66702. if an instru ction is sent without checking the busy flag, the time between the first instruction and next instruction will take much longer than the instruction time itself. refer to table 7 for the list of each instruction execution time.
hd66702 255 table 7 instructions code execution time (max) (when f cp or instruction rs r/ : : db7 db6 db5 db4 db3 db2 db1 db0 description f osc is 320 khz) clear display 0 0 0 0 0 0 0 0 0 1 clears entire display and sets ddram address 0 in address counter. 1.28 ms return home 0 0 0 0 0 0 0 0 1 sets ddram address 0 in address counter. also returns display from being shifted to original position. ddram contents remain unchanged. 1.28 ms entry mode set 0 0 0 0 0 0 0 1 i/d s sets cursor move direction and specifies display shift. these operations are performed during data write and read. 31 s display on/off control 0 0 0 0 0 0 1 d c b sets entire display (d) on/off, cursor on/off (c), and blinking of cursor position character (b). 31 s cursor or display shift 0 0 0 0 0 1 s/c r/l moves cursor and shifts display without changing ddram contents. 31 s function set 0 0 0 0 1 dl n f sets interface data length (dl), number of display lines (l), and character font (f). 31 s set cgram address 0 0 0 1 acg acg acg acg acg acg sets cgram address. cgram data is sent and received after this setting. 31 s set ddram address 0 0 1 add add add add add add add sets ddram address. ddram data is sent and received after this setting. 31 s read busy flag & address 0 1 bf ac ac ac ac ac ac ac reads busy flag (bf) indicating internal operation is being performed and reads address counter contents. 0 s
hd66702 256 table 7 instructions (cont) code execution time (max) (when f cp or instruction rs r/ : : db7 db6 db5 db4 db3 db2 db1 db0 description f osc is 320 khz) write data to cg or ddram 1 0 write data writes data into ddram or cgram. 31 s t add = 4.7 s* read data from cg or ddram 1 1 read data reads data from ddram or cgram. 31 s t add = 4.7 s* i/d = 1: increment i/d = 0: decrement s = 1: accompanies display shift s/c = 1: display shift s/c = 0: cursor move r/l = 1: shift to the right r/l = 0: shift to the left dl = 1: 8 bits, dl = 0: 4 bits n = 1: 2 lines, n = 0: 1 line f = 1: 5 10 dots, f = 0: 5 7 dots bf = 1: internally operating bf = 0: instructions acceptable ddram: display data ram cgram: character generator ram acg: cgram address add: ddram address (corresponds to cursor address) ac: address counter used for both dd and cgram addresses execution time changes when frequency changes example: when f cp or f osc is 270 khz, 31 s = 37 s 320 270 note: indicates no effect. * after execution of the cgram/ddram data write or read instruction, the ram address counter is incremented or decremented by 1. the ram address counter is updated after the busy flag turns off. in figure 10, t add is the time elapsed after the busy flag turns off until the address counter is updated. busy state busy signal (db7 pin) address counter (db0 to db6 pins) t add a a + 1 note: t depends on the operation frequency t = 1.5/(f or f ) seconds add add cp osc figure 10 address counter update
hd66702 257 instruction description clear display clear display writes space code 20h (character pattern for character code 20h must be a blank pattern) into all ddram addresses. it then sets ddram address 0 into the address counter, and returns the display to its original status if it was shifted. in other words, the display disappears and the cursor or blinking goes to the left edge of the display (in the first line if 2 lines are displayed). it also sets i/d to 1 (increment mode) in entry mode. s of entry mode does not change. return home return home sets ddram address 0 into the address counter, and returns the display to its original status if it was shifted. the ddram contents do not change. the cursor or blinking go to the left edge of the display (in the first line if 2 lines are displayed). entry mode set i/d: increments (i/d = 1) or decrements (i/d = 0) the ddram address by 1 when a character code is written into or read from ddram. the cursor or blinking moves to the right when incremented by 1 and to the left when decremented by 1. the same applies to writing and reading of cgram. s: shifts the entire display either to the right (i/d = 0) or to the left (i/d = 1) when s is 1. the display does not shift if s is 0. if s is 1, it will seem as if the cursor does not move but the display does. the display does not shift when reading from ddram. also, writing into or reading out from cgram does not shift the display. display on/off control d: the display is on when d is 1 and off when d is 0. when off, the display data remains in ddram, but can be displayed instantly by setting d to 1. c: the cursor is displayed when c is 1 and not displayed when c is 0. even if the cursor disappears, the function of i/d or other specifications will not change during display data write. the cursor is displayed using 5 dots in the 8th line for 5 7 dot character font selection and in the 11th line for the 5 10 dot character font selection (figure 13).
hd66702 258 b: the character indicated by the cursor blinks when b is 1 (figure 13). the blinking is displayed as switching between all blank dots and displayed characters at a speed of 320-ms intervals when f cp or f osc is 320 khz. the cursor and blinking can be set to display simultaneously. (the blinking frequency changes according to f osc or the reciprocal of f cp . for example, when fcp is 270 khz, 320 320/270 = 379.2 ms.) cursor or display shift cursor or display shift shifts the cursor position or display to the right or left without writing or reading display data (table 8). this function is used to correct or search the display. in a 2-line display, the cursor moves to the second line when it passes the 40th digit of the first line. note that the first and second line displays will shift at the same time. when the displayed data is shifted repeatedly each line moves only horizontally. the second line display does not shift into the first line position. the address counter (ac) contents will not change if the only action performed is a display shift. function set dl: sets the interface data length. data is sent or received in 8-bit lengths (db7 to db0) when dl is 1, and in 4-bit lengths (db7 to db4) when dl is 0. when 4-bit length is selected, data must be sent or received twice. n: sets the number of display lines (table 9). f: sets the character font (table 9). note: perform the function at the head of the program before executing any instructions (except for the read busy flag and address instruction). from this point, the function set instruction cannot be executed unless the interface data length is changed. set cgram address set cgram address sets the cgram address binary aaaaaa into the address counter. data is then written to or read from the mpu for cgram.
hd66702 259 rs 0 r/w 0 db7 0 db6 0 db5 0 db4 0 db3 0 code db2 0 db1 1 db0 * note: don? care. * code rs 0 r/w 0 db7 0 db6 0 db5 0 db4 0 db3 0 code db2 1 db1 i/d db0 s rs 0 r/w 0 db7 0 db6 0 db5 0 db4 0 db3 1 code db2 d db1 c db0 b rs 0 r/w 0 db7 0 db6 0 db5 0 db4 0 db3 0 db2 0 db1 0 db0 1 return home clear display entry mode set display on/off control figure 11 rs 0 r/w 0 db7 0 db6 0 db5 0 db4 1 db3 s/c code db2 r/l db1 db0 rs 0 r/w 0 db7 0 db6 0 db5 1 db4 dl db3 n code db2 f db0 * note: don? care. * * rs 0 r/w 0 db7 0 db6 1 db5 a db4 a db3 a code db2 a db0 a db1 a highest order bit lowest order bit db1 * cursor or display shift function set set cgram address * note: don? care. * figure 12
hd66702 260 set ddram address set ddram address sets the ddram address binary aaaaaaa into the address counter. data is then written to or read from the mpu for ddram. however, when n is 0 (1-line display), aaaaaaa can be 00h to 4fh. when n is 1 (2-line display), aaaaaaa can be 00h to 27h for the first line, and 40h to 67h for the second line. read busy flag and address read busy flag and address reads the busy flag (bf) indicating that the system is now internally operating on a previously received instruction. if bf is 1, the internal operation is in progress. the next instruction will not be accepted until bf is reset to 0. check the bf status before the next write operation. at the same time, the value of the address counter in binary aaaaaaa is read out. this address counter is used by both cg and ddram addresses, and its value is determined by the previous instruction. the address contents are the same as for instructions set cgram address and set ddram address. table 8 shift function s/c r/l 0 0 shifts the cursor position to the left. (ac is decremented by one.) 0 1 shifts the cursor position to the right. (ac is incremented by one.) 1 0 shifts the entire display to the left. the cursor follows the display shift. 1 1 shifts the entire display to the right. the cursor follows the display shift. table 9 function set nf no. of display lines character font duty factor remarks 001 5 7 dots 1/8 011 5 10 dots 1/11 1*2 5 7 dots 1/16 cannot display two lines for 5 10 dot character font. note: * indicates dont care.
hd66702 261 cursor 5 7 dot character font 5 10 dot character font alternating display blink display example cursor display example figure 13 cursor and blinking rs 0 r/w 0 db7 1 db6 a db5 a db4 a db3 a code db2 a db1 a db0 a highest order bit lowest order bit rs 0 r/w 1 db7 bf db6 a db5 a db4 a db3 a code db2 a db1 a db0 a highest order bit lowest order bit set ddram address read busy flag and address figure 14
hd66702 262 write data to cg or ddram write data to cg or ddram writes 8-bit binary data dddddddd to cg or ddram. to write into cg or ddram is determined by the previous specification of the cgram or ddram address setting. after a write, the address is automatically incremented or decremented by 1 according to the entry mode. the entry mode also determines the display shift. read data from cg or ddram read data from cg or ddram reads 8-bit binary data dddddddd from cg or ddram. the previous designation determines whether cg or ddram is to be read. before entering this read instruction, either cgram or ddram address set instruction must be executed. if not executed, the first read data will be invalid. when serially executing read instructions, the next address data is normally read from the second read. the address set instructions need not be executed just before this read instruction when shifting the cursor by the cursor shift instruction (when reading out ddram). the operation of the cursor shift instruction is the same as the set ddram address instruction. after a read, the entry mode automatically increases or decreases the address by 1. however, display shift is not executed regardless of the entry mode. note: the address counter (ac) is automatically incremented or decremented by 1 after the write instructions to cgram or ddram are executed. the ram data selected by the ac cannot be read out at this time even if read instructions are executed. therefore, to correctly read data, execute either the address set instruction or cursor shift instruction (only with ddram), then just before reading the desired data, execute the read instruction from the second time the read instruction is sent. rs 1 r/w 1 db7 d db6 d db5 d db4 d db3 d code db2 d db1 d db0 d higher order bits lower order bits rs 1 r/w 0 db7 d db6 d db5 d db4 d db3 d code db2 d db1 d db0 d higher order bits lower order bits read data from cg or ddram write data to cg or ddram figure 15
hd66702 263 interfacing the hd66702 interface to mpus interfacing to an 8-bit mpu see figure 17 for an example of using a i/o port (for a single-chip microcomputer) as an interface device. in this example, a0 to a7 are connected to the data bus db0 to db7, and c0 to c2 are connected to e, r/ : , and rs, respectively. rs r/w e internal operation db7 functioning data busy busy not busy data instruction write busy flag check busy flag check busy flag check instruction write figure 16 example of busy flag check timing sequence 8 16 100 lcd c0 c1 c2 a0 to a7 rs r/w e db0 to db7 hd66702 h8/325 com1 to com16 seg1 to seg100 figure 17 8-bit mpu interface
hd66702 264 interfacing to a 4-bit mpu the hd66702 can be connected to the i/o port of a 4-bit mpu. if the i/o port has enough bits, 8-bit data can be transferred. otherwise, one data transfer must be made in two operations for 4-bit data. in this case, the timing sequence becomes somewhat complex. (see figure 18.) see figure 19 for an interface example to the hmcs43c. note that two cycles are needed for the busy flag check as well as for the data transfer. the 4-bit operation is selected by the program. rs r/w e internal operation db7 ir7 ir3 busy ac3 not busy ac3 d7 d3 instruction write busy flag check busy flag check instruction write note: ir7, ir3 are the 7th and 3rd bits of the instruction. ac3 is the 3rd bit of the address counter. * functioning figure 18 example of 4-bit data transfer timing sequence d15 d14 d13 r10 to r13 rs r/w e db4 to db7 com1 to com16 seg1 to seg100 4 100 16 lcd hmcs43c (hitachi 4-bit single-chip microcontroller) hd66702 figure 19 example of interface to hmcs43c
hd66702 265 interface to liquid crystal display character font and number of lines: the hd66702 can perform two types of displays, 5 7 dot and 5 10 dot character fonts, each with a cursor. up to two lines are displayed for 5 7 dots and one line for 5 10 dots. therefore, a total of three types of common signals are available (table 10). the number of lines and font types can be selected by the program. (see table 7, instructions.) connection to hd66702 and liquid crystal display: see figure 20 for the connection examples. table 10 common signals number of lines character font number of common signals duty factor 15 7 dots + cursor 8 1/8 15 10 dots + cursor 11 1/11 25 7 dots + cursor 16 1/16 com1 com8 seg1 seg100 com1 com11 seg1 seg100 hd66702 example of a 5 7 dot, 20-character 1-line display (1/4 bias, 1/8 duty cycle) example of a 5 10 dot, 20-character 1-line display (1/4 bias, 1/8 duty cycle) hd66702 figure 20 liquid crystal display and hd66702 connections
hd66702 266 since five segment signal lines can display one digit, one hd66702 can display up to 20 digits for a 1- line display and 40 digits for a 2-line display. the examples in figure 20 have unused common signal pins, which always output non-selection waveforms. when the liquid crystal display panel has unused extra scanning lines, connect the extra scanning lines to these common signal pins to avoid any undesirable effects due to crosstalk during the floating state (figure 21). com1 com8 seg1 seg100 hd66702 com9 com16 example of a 5 7 dot, 20-character 2-line display (1/5 bias, 1/16 duty cycle) figure 20 liquid crystal display and hd66702 connections (cont) com1 com8 seg1 seg100 hd66702 com9 5 7 dot, 20-character 1-line display (1/4 bias, 1/8 duty cycle) figure 21 using com9 to avoid crosstalk on unneeded scanning line
hd66702 267 connection of changed matrix layout: in the preceding examples, the number of lines correspond to the scanning lines. however, the following display examples (figure 22) are made possible by altering the matrix layout of the liquid crystal display panel. in either case, the only change is the layout. the display characteristics and the number of liquid crystal display characters depend on the number of common signals or on duty factor. note that the display data ram (ddram) addresses for 10 characters 2 lines and for 40 characters 1 line are the same as in figure 20. com1 com8 seg1 seg100 com9 com16 hd66702 hd66702 5 7 dot, 40-character 1-line display (1/5 bias, 1/16 duty cycle) seg1 seg50 com1 com8 seg51 seg100 5 7 dot, 10-character 2-line display (1/4 bias, 1/8 duty cycle) figure 22 changed matrix layout displays
hd66702 268 power supply for liquid crystal display drive various voltage levels must be applied to pins v1 to v5 of the hd66702 to obtain the liquid crystal display drive waveforms. the voltages must be changed according to the duty factor (table 11). vlcd is the peak value for the liquid crystal display drive waveforms, and resistance dividing provides voltages v1 to v5 (figure 23). table 11 duty factor and power supply for liquid crystal display drive duty factor 1/8, 1/11 1/16 bias power supply 1/4 1/5 v1 v cc C1/4 vlcd v cc C1/5 vlcd v2 v cc C1/2 vlcd v cc C2/5 vlcd v3 v cc C1/2 vlcd v cc C3/5 vlcd v4 v cc C3/4 vlcd v cc C4/5 vlcd v5 v cc Cvlcd v cc Cvlcd v cc v1 v4 v5 v2 v3 v cc v1 v2 v3 v4 v5 r r r r vr v cc v cc r r r r r vr vlcd vlcd 1/4 bias (1/8, 1/11 duty cycle) note: r changes depending on the size of liquid crystal panel. normally, r is, 4.7 k to 20k . 1/5 bias (1/16, duty cycle) hd66702 hd66702 v ee v ee figure 23 drive voltage supply example
hd66702 269 relationship between oscillation frequency and liquid crystal display frame frequency the liquid crystal display frame frequencies of figure 24 apply only when the oscillation frequency is 320 khz (one clock pulse of 3.125 s). 1 2 3 4 8 1 2 1 2 3 4 11 1 2 1 2 3 4 16 1 2 400 clocks 400 clocks 200 clocks 1 frame 1 frame 1 frame 1/8 duty cycle 1/11 duty cycle 1/16 duty cycle v cc v1 v2 (v3) v4 v5 v cc v1 v2 (v3) v4 v5 v cc v1 v2 v3 v4 v5 com1 com1 com1 1 frame = 3.125 s 400 8 = 10000 s = 10 ms frame frequency = = 100 hz 1 10 ms 1 frame = 3.125 s 400 11 = 13750 s = 13.75 ms frame frequency = = 72.7 hz 1 13.75 ms 1 frame = 3.125 s 200 16 = 10000 s = 10 ms frame frequency = = 100 hz 1 10 ms figure 24 frame frequency
hd66702 270 instruction and display correspondence 8-bit operation, 20-digit 1-line display with internal reset refer to table 12 for an example of an 8-bit 1-line display in 8-bit operation. the hd66702 functions must be set by the function set instruction prior to the display. since the display data ram can store data for 80 characters, as explained before, the ram can be used for displays such as for advertising when combined with the display shift operation. since the display shift operation changes only the display position with ddram contents unchanged, the first display data entered into ddram can be output when the return home operation is performed. 4-bit operation, 20-digit 1-line display with internal reset the program must set all functions prior to the 4-bit operation (table 13). when the power is turned on, 8-bit operation is automatically selected and the first write is performed as an 8-bit operation. since db0 to db3 are not connected, a rewrite is then required. however, since one operation is completed in two accesses for 4-bit operation, a rewrite is needed to set the functions (see table 13). thus, db4 to db7 of the function set instruction is written twice. 8-bit operation, 20-digit 2-line display for a 2-line display, the cursor automatically moves from the first to the second line after the 40th digit of the first line has been written. thus, if there are only 20 characters in the first line, the ddram address must be again set after the 20th character is completed. (see table 14.) note that the display shift operation is performed for the first and second lines. in the example of table 14, the display shift is performed when the cursor is on the second line. however, if the shift operation is performed when the cursor is on the first line, both the first and second lines move together. if the shift is repeated, the display of the second line will not move to the first line. the same display will only shift within its own line for the number of times the shift is repeated. note: when using the internal reset, the electrical characteristics in the power supply conditions using internal reset circuit table must be satisfied. if not, the hd66702 must be initialized by instructions. (because the internal reset does not function correctly when v cc is 3v, it must always be initialized by software.) see the section, initializing by instruction.
hd66702 271 table 12 8-bit operation, 20-digit 1-line display example with internal reset step instruction no. rs r/ : : db7 db6 db5 db4 db3 db2 db1 db0 display operation 1 power supply on (the hd66702 is initialized by the internal reset circuit) initialized. no display. 2 function set 00001100* * sets to 8-bit operation and selects 1-line display and character font. (number of display lines and character fonts cannot be changed after step #2.) 3 display on/off control 0000001110 _ turns on display and cursor. entire display is in space mode becauce of initialization. 4 entry mode set 0000000110 _ sets mode to increment the address by one and to shift the cursor to the right at the time of write to the dd/cgram. display is not shifted. 5 write data to cgram/ddram 1001001000 h_ writes h. ddram already been selected by initialization when the power was turned on. the cursor is incremented by one and shifted to the right. 6 write data to cgram/ddram 1001001001 hi_ writes i. 7 8 write data to cgram/ddram 1001001001 hitachi_ writes i. 9 entry mode set 0000000111 hitachi_ sets mode to shift display at the time of write. 10 write data to cgram/ddram 1000100000 itachi _ writes a space.
hd66702 272 table 12 8-bit operation, 20-digit 1-line display example with internal reset (cont) step instruction no. rs r/ : : db7 db6 db5 db4 db3 db2 db1 db0 display operation 11 write data to cgram/ddram 1001001101 tachi m_ writes m. 12 13 write data to cgram/ddram 1001001111 microko_ writes o. 14 cursor or display shift 00000100* * microko _ shifts only the cursor position to the left. 15 cursor or display shift 00000100* * microko _ shifts only the cursor position to the left. 16 write data to cgram/ddram 1001000011 icroco _ writes c over k. the display moves to the left. 17 cursor or display shift 00000111* * microco _ shifts the display and cursor position to the right. 18 cursor or display shift 00000101* * microco_ shifts the display and cursor position to the right. 19 write data to cgram/ddram 1001001101 icrocom_ writes m. 20 21 return home 0000000010 hitachi _ returns both display and cursor to the original position(address 0).
hd66702 273 table 13 4-bit operation, 20-digit 1-line display example with internal reset step instruction no. rs r/ : : db7 db6 db5 db4 display operation 1 power supply on (the hd66702 is initialized by the internal reset circuit) initialized. no display. 2 function set 000010 sets to 4-bit operation. in this case, operation is handled as 8 bits by initializa- tion, and only this instruction completes with one write. 3 function set 000010 0000* * sets 4-bit operation and selects1-line display and 5 7 dot character font. 4-bit operation starts from this step and resetting is necessary. (number of display lines and character fonts cannot be changed after step #3.) 4 display on/off control 000000 001110 _ turns on display and cursor. entire display is in space mode because of initialization. 5 entry mode set 000000 000110 _ sets mode to increment the address by one and to shift the cursor to the right at the time of write to the dd/cgram. display is not shifted. 6 write data to cgram/ddram 100100 101000 h_ writes h. the cursor is incremented by one and shifts to the right. note: the control is the same as for 8-bit operation beyond step #6.
hd66702 274 table 14 8-bit operation, 20-digit 2-line display example with internal reset step instruction no. rs r/ : : db7 db6 db5 db4 db3 db2 db1 db0 display operation 1 power supply on (the hd66702 is initialized by the internal reset circuit) initialized. no display. 2 function set 00001110* * sets to 8-bit operation and selects 2-line display and 5 7 dot character font. 3 display on/off control 0000001110 _ turns on display and cursor. all display is in space mode because of initialization. 4 entry mode set 0000000110 _ sets mode to increment the address by one and to shift the cursor to the right at the time of write to the dd/cgram. display is not shifted. 5 write data to cgram/ddram 1001001000 h_ writes h. ddram has already been selected by initialization when the power was turned on. the cursor is incremented by one and shifted to the right. 6 7 write data to cgram/ddram 1001001001 hitachi_ writes i. 8 set ddram address 0011000000 hitachi _ sets ram address so that the cursor is positioned at the head of the second line.
hd66702 275 table 14 8-bit operation, 20-digit 2-line display example with internal reset (cont) step instruction no. rs r/ : : db7 db6 db5 db4 db3 db2 db1 db0 display operation 9 write data to cgram/ddram 1001001101 hitachi m_ writes m. 10 11 write data to cgram/ddram 1001001111 hitachi microco_ writes o. 12 entry mode set 0000000111 hitachi microco_ sets mode to shift display at the time of write. 13 write data to cgram/ddram 1001001101 itachi icrocom_ writes m. display is shifted to the right. the first and second lines both shift at the same time. 14 15 return home 0000000010 hitachi microcom _ returns both display and cursor to the original position (address 0).
hd66702 276 initializing by instruction if the power supply conditions for correctly operating the internal reset circuit are not met, initialization by instructions becomes necessary. refer to figures 25 and 26 for the procedures on 8-bit and 4-bit initializations, respectively. power on wait for more than 15 ms after v cc rises to 4.5v wait for more than 4.1 ms wait for more than 100 s rs 0 r/w 0 db7 0 db6 0 db5 1 db4 1 db3 db2 db1 db0 **** rs 0 r/w 0 db7 0 db6 0 db5 1 db4 1 db3 db2 db1 db0 **** rs 0 r/w 0 db7 0 db6 0 db5 1 db4 1 db3 db2 db1 db0 **** rs 0 r/w 0 db7 0 db6 0 db5 1 db4 1 db3 n db2 f db1 db0 ** 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 i/d 0 1 s initialization ends bf cannot be checked before this instruction. function set (interface is 8 bits long.) bf cannot be checked before this instruction. function set (interface is 8 bits long.) bf cannot be checked before this instruction. function set (interface is 8 bits long.) bf can be checked after the following instructions. when bf is not checked, the waiting time between instructions is longer than the execution instuction time. (see table 7.) function set (interface is 8 bits long. specify the number of display lines and character font.) the number of display lines and character font cannot be changed after this point. display off display clear entry mode set wait for more than 40 ms after v cc rises to 2.7v figure 25 8-bit interface
hd66702 277 initialization ends wait for more than 15 ms after v cc rises to 4.5v wait for more than 40 ms after v cc rises to 2.7v bf cannot be checked before this instruction. function set (interface is 8 bits long.) bf cannot be checked before this instruction. function set (interface is 8 bits long.) bf cannot be checked before this instruction. function set (interface is 8 bits long.) db7 0 db6 0 db5 1 db4 1 rs 0 r/w 0 wait for more than 4.1 ms db7 0 db6 0 db5 1 db4 1 rs 0 r/w 0 wait for more than 100 s db7 0 db6 0 db5 1 db4 1 rs 0 r/w 0 db7 0 db6 0 db5 1 db4 0 rs 0 r/w 0 0 n 0 1 0 0 0 0 0 f 0 0 0 0 0 1 1 0 0 0 0 0 i/d 0 0 0 0 1 0 s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ** bf can be checked after the following instructions. when bf is not checked, the waiting time between instructions is longer than the execution instuction time. (see table 7.) function set (set interface to be 4 bits long.) interface is 8 bits in length. display off display clear entry mode set function set (interface is 4 bits long. specify the number of display lines and character font.) the number of display lines and character font cannot be changed after this point. power on figure 26 4-bit interface
hd66702 278 [low voltage version] absolute maximum ratings* item symbol unit value notes power supply voltage (1) v cc v C0.3 to +7.0 1 power supply voltage (2) v cc Cv5 v C0.3 to +8.5 2 input voltage vt v C0.3 to v cc +0.3 1 operating temperature t opr c C20 to +75 storage temperature t stg c C55 to +125 4 note: 1. the operating temperature is 75c. 2. if the lsi is used above these absolute maximum ratings, it may become permanently damaged. using the lsi within the following electrical characteristic limits is strongly recommended for normal operation. if these electrical characteristic conditions are also exceeded, the lsi will malfunction and cause poor reliability. 3. the power supply voltage is gnd = 0v. 4. keep v cc 3 v5 (low), and v cc 3 gnd (low)
hd66702 279 dc characteristics (v cc = 2.7 to 5.5v, t a = C20 to +75c* 3 ) item symbol min typ max unit test condition notes* input high voltage (1) (except osc1) vih1 0.7v cc v cc v 6, 17 input low voltage (1) (except osc1) vil1 C0.3 0.55 v 6, 17 input high voltage (2) (osc1) vih2 0.7v cc v cc v15 input low voltage (2) (osc1) vil2 0.2v cc v15 output high voltage (1) (d0Cd7) voh1 0.75v cc v Ci oh = 0.1 ma 7 output low voltage (1) (d0Cd7) vol1 0.2v cc vi ol = 0.1 ma 7 output high voltage (2) (except d0Cd7) voh2 0.8v cc v Ci oh = 0.04 ma 8 output low voltage (2) (except d0Cd7) vol2 0.2v cc vi ol = 0.04 ma 8 driver on resistance (com) r com 220 k w id = 0.05 ma (com) 13 driver on resistance (seg) r seg 230 k w id = 0.05 ma (seg) 13 input leakage current i li C1 1 a vin = 0 to v cc 9 pull-up mos current (rs, r/ : , d0Cd7) Ci p 10 50 120 a v cc = 3v power supply current i cc 0.15 0.30 ma r f oscillation, external clock v cc = 3v, f osc = 320 khz 10, 14 lcd voltage vlcd1 3.0 8.3 v v cc Cv5, 1/5 bias 16 vlcd2 3.0 8.3 v v cc Cv5, 1/4 bias 16 note: * refer to the electrical characteristics notes section following these tables.
hd66702 280 ac characteristics (v cc = 2.7 to 5.5v, t a = C20 to +75c* 3 ) clock characteristics item symbol min typ max unit test condition notes* external external clock frequency f cp 125 270 410 khz 11 clock operation external clock duty duty 45 50 55 % external clock rise time t rcp 0.2 s external clock fall time t fcp 0.2 s r f oscillation clock oscillation frequency f osc 240 320 390 khz r f = 56 k w v cc = 3v 12 note: * refer to the electrical characteristics notes section following these tables. bus timing characteristics write operation item symbol min typ max unit test condition enable cycle time t cyce 1000 ns figure 27 enable pulse width (high level) pw eh 450 enable rise/fall time t er , t ef 25 address set-up time (rs, r/ : to e) t as 40 address hold time t ah 20 data set-up time t dsw 195 data hold time t h 10 read operation item symbol min typ max unit test condition enable cycle time t cyce 1000 ns figure 28 enable pulse width (high level) pw eh 450 enable rise/fall time t er , t ef 25 address set-up time (rs, r/ : to e) t as 40 address hold time t ah 20 data delay time t ddr 350 data hold time t dhr 10
hd66702 281 interface timing characteristics with external driver item symbol min typ max unit test condition clock pulse width high level t cwh 800 ns figure 29 low level t cwl 800 clock set-up time t csu 500 data set-up time t su 300 data hold time t dh 300 m delay time t dm C1000 1000 clock rise/fall time t ct 200 power supply conditions using internal reset circuit item symbol min typ max unit test condition power supply rise time t rcc 0.1 10 ms figure 30 power supply off time t off 1 [standard voltage version] absolute maximum ratings* item symbol unit value notes power supply voltage (1) v cc v C0.3 to +7.0 1 power supply voltage (2) v cc Cv5 v C0.3 to +8.5 2 input voltage vt v C0.3 to v cc +0.3 1 operating temperature t opr c C20 to +75 storage temperature t stg c C55 to +125 4 note: * if the lsi is used above these absolute maximum ratings, it may become permanently damaged. using the lsi within the following electrical characteristic limits is strongly recommended for normal operation. if these electrical characteristic conditions are also exceeded, the lsi will malfunction and cause poor reliability. refer to the electrical characteristics notes section following these tables.
hd66702 282 dc characteristics (v cc = 5v 10%, t a = C20 to +75c* 3 ) item symbol min typ max unit test condition notes* input high voltage (1) (except osc1) vih1 2.2 v cc v 6, 17 input low voltage (1) (except osc1) vil1 C0.3 0.6 v 6, 17 input high voltage (2) (osc1) vih2 v cc C1.0 v cc v15 input low voltage (2) (osc1) vil2 1.0 v 15 output high voltage (1) (d0Cd7) voh1 2.4 v Ci oh = 0.205 ma 7 output low voltage (1) (d0Cd7) vol1 0.4 v i ol = 1.6 ma 7 output high voltage (2) (except d0Cd7) voh2 0.9 v cc v Ci oh = 0.04 ma 8 output low voltage (2) (except d0Cd7) vol2 0.1 v cc vi ol = 0.04 ma 8 driver on resistance (com) r com 220k w id = 0.05 ma (com) 13 driver on resistance (seg) r seg 230k w id = 0.05 ma (seg) 13 input leakage current i li C1 1 a vin = 0 to v cc 9 pull-up mos current (rs, r/ : , d0Cd7) Ci p 50 125 250 a v cc = 5v power supply current i cc 0.35 0.60 ma r f oscillation, external clock v cc = 5v, f osc = 320 khz 10, 14 lcd voltage vlcd1 3.0 8.3 v v cc Cv5, 1/5 bias 16 vlcd2 3.0 8.3 v v cc Cv5, 1/4 bias 16 note: * refer to the electrical characteristics notes section following these tables.
hd66702 283 ac characteristics (v cc = 5v 10%, t a = C20 to +75c* 3 ) clock characteristics item symbol min typ max unit test condition notes* external external clock frequency f cp 125 270 410 khz 11 clock external clock duty duty 45 50 55 % 11 operation external clock rise time t rcp 0.2 s 11 external clock fall time t fcp 0.2 s 11 r f oscillation clock oscillation frequency f osc 220 320 420 khz r f = 68 k w v cc = 5v 12 note: * refer to the electrical characteristics notes section following these tables. bus timing characteristics write operation item symbol min typ max unit test condition enable cycle time t cyce 1000 ns figure 27 enable pulse width (high level) pw eh 450 enable rise/fall time t er , t ef 25 address set-up time (rs, r/ : to e) t as 40 address hold time t ah 10 data set-up time t dsw 195 data hold time t h 10 read operation item symbol min typ max unit test condition enable cycle time t cyce 1000 ns figure 28 enable pulse width (high level) pw eh 450 enable rise/fall time t er , t ef 25 address set-up time (rs, r/ : to e) t as 40 address hold time t ah 10 data delay time t ddr 320 data hold time t dhr 20
hd66702 284 interface timing characteristics with external driver item symbol min typ max unit test condition clock pulse width high level t cwh 800 ns figure 29 low level t cwl 800 clock set-up time t csu 500 data set-up time t su 300 data hold time t dh 300 m delay time t dm C1000 1000 clock rise/fall time t ct 100 power supply conditions using internal reset circuit item symbol min typ max unit test condition power supply rise time t rcc 0.1 10 ms figure 30 power supply off time t off 1
hd66702 285 electrical characteristics notes 1. all voltage values are referred to gnd = 0v. 2. v cc 3 v5 must be maintained. 3. for die products, specified up to 75c. 4. for die products, specified by the die shipment specification. 5. the following four circuits are i/o pin configurations except for liquid crystal display output. v cc pmos nmos v cc v cc pmos nmos (pull up mos) pmos v cc pmos nmos v cc nmos nmos v cc pmos nmos (output circuit) (tristate) output enable data (pull-up mos) i/o pin pins: db0 ?b7 (mos with pull-up) input pin pin: e (mos without pull-up) pins: rs, r/w (mos with pull-up) output pin pins: cl1 , cl2 , m, d v cc (input circuit) pmos pmos input enable
hd66702 286 6. applies to input pins and i/o pins, excluding the osc1 pin. 7. applies to i/o pins. 8. applies to output pins. 9. current flowing through pullCup moss, excluding output drive moss. 10. input/output current is excluded. when input is at an intermediate level with cmos, the excessive current flows through the input circuit to the power supply. to avoid this from happening, the input level must be fixed high or low. 11. applies only to external clock operation. oscillator osc1 osc2 0.7 v cc 0.5 v cc 0.3 v cc th tl t rcp t rcp duty = 100% th th + tl open 12. applies only to the internal oscillator operation using oscillation resistor r f . osc1 osc2 r f r : r : f f 56 k 2% (when v cc = 3v) 68 k 2% (when v cc = 5v) w w 500 400 300 200 100 50 100 150 (68) r f (k ) w f osc (khz) v cc = 5v typ. 500 400 300 200 100 50 100 150 (56) r f (k ) w f osc (khz) v cc = 3v typ. since the oscillation frequency varies depending on the osc1 and osc2 pin capacitance, the wiring length to these pins should be minimized. max. min. max. min. 320 320
hd66702 287 13. r com is the resistance between the power supply pins (v cc , v1, v4, v5) and each common signal pin (com1 to com16). r seg is the resistance between the power supply pins (v cc , v2, v3, v5) and each segment signal pin (seg1 to seg100). 14. the following graphs show the relationship between operation frequency and current consumption. 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 100 200 300 400 500 v = 5v cc 0 100 200 300 400 500 v = 3v cc f or f (khz) f or f (khz) osc osc cp cp i (ma) cc i (ma) cc max. typ. max. typ. 15. applies to the osc1 pin. 16. each com and seg output voltage is within 0.15v of the lcd voltage (v cc , v1, v2, v3, v4, v5) when there is no load. 17. the test pin should be fixed to gnd and the ext pin should be fixed to v cc or gnd.
hd66702 288 load circuits data bus db0 to db7 for v = 5v cc test point 90 pf 11 k w v = 5v cc 2.4 k w 1s2074 diodes h for v = 3v cc test point 50 pf external driver control signal: cl1, cl2, d, m test point 30 pf
hd66702 289 timing characteristics rs r/w e db0 to db7 vih1 vil1 vih1 vil1 t as t ah vil1 vil1 t ah pw eh t ef vih1 vil1 vih1 vil1 t er t dsw h t vih1 vil1 vih1 vil1 t cyce vil1 valid data figure 27 write operation rs r/w e db0 to db7 vih1 vil1 vih1 vil1 t as t ah vih1 vih1 t ah pw eh t ef vih1 vil1 vih1 vil1 t ddr dhr t t er vil1 voh1 vol1 voh1 vol1 valid data t cyce figure 28 read operation
hd66702 290 cl1 cl2 d m voh2 voh2 vol2 t ct t cwh t cwh t csu voh2 t csu t cwl t ct t dh t su vol2 t dm voh2 vol2 vol2 figure 29 interface timing with external driver v cc 0.2v 2.7v/4.5v * 2 0.2v 0.2v t rcc t off * 1 0.1 ms t 10 ms rcc t 1 ms 3 off notes: 1. 2. 3. t compensates for the power oscillation period caused by momentary power supply oscillations. specified at 4.5v for 5-v operation, and at 2.7v for 3-v operation. when the above condition cannot be satisfied, the internal reset circuit will not operate normally. in this case, the lsi must be initialized by software. (refer to the initializing by instruction section.) off figure 30 internal power supply reset

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