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1/ 17 ? 2004 hynix semiconductor inc. all rights reserved. h18gpl11s data sheet 1. general description 2. features ? on-chip charge pump type pll clock generator ? input reference clock range : 5mhz ~ 100mhz ? clock output frequency range : 5mhz ~ 160mhz( extend to 320mhz ) ? reference divider range : 1 ~ 256 ( 8-bit programmable divider) ? feedback divider range : 3 ~ 16386 ( 14-bit programmable divider) ? 8 mode programmable loop filter ? programmable vco range and vco gain( 2-bit ) ? programmable pd gain ( 2-bit ) ? maximum power consumption : 12mw ? process : 0.18 ? cmos generic process( 1-poly, 3-metal ) ? cell size : 740 ? x 816?( with guard ring ) the h18gpl11s is a 1.8v cmos (0.18 ? 1-poly, 3-metal) analog programmable frequency synthesizer based on charged pump type pll for an on-chip appl ication using hynix standard 0.18 ? asic process. h18gpl11s has 5mhz to 320mhz output range. operating frequency and loop characteristics of pll are fully programmable. 3. block diagram and reco mmended application circuits 8 bit counter n<7:0>+1 14 bit counter m<13:0>+2 pfd charge pump lfo vco ck : external pin of chip post divider 2 p[1:0]+1 avdd icp[3:0] vc[1:0] p[1:0] external loop filter is optional if you use internal loop filter mode, lfo port doesn?t need to be connected. avdd avss 10uf 4.7nf 1.8v ground separate avdd, avss properly from digital and system power and signal vcopd vcoinitt tpdud[1:0] bpck bypass tdm analog part optional pd loop filter lfm[2:0] clfe clf2e rlfe ncb[7:0] mc[13:0] lock detector lock pd pd ref n[7:0] m[13:0] reset cnttest reset reset pd vcopd dvdd dvss
2/ 17 ? 2004 hynix semiconductor inc. all rights reserved. h18gpl11s data sheet 4. pin descriptions pin name type description dvdd power digital power supply dvss ground digital ground avdd power analog power supply avss ground analog ground asub ground guard ring ground ref input pll reference clock input signal bpck input bypass clock input signal pd input pll power down mode except vco : active high vcopd input vco power down mode : active high bypass input bypass mode : active high tdm input digital part test mode : active high reset input digital part reset signal : active high vcoinit input vco initialize signal : active high cnttest input counter toggle test : active high tpdud[1:0] input charge pump test mode( normal mode : ?00?) m[13:0] input feedback divisor is m[13:0]+2 n[7:0] input reference divisor is n[7:0]+1 p[1:0] input post divisor is 2 p[1:0]+1 vc[1:0] input vco range control vector icp[3:0] input charge pump bias current control vector
3/ 17 ? 2004 hynix semiconductor inc. all rights reserved. h18gpl11s data sheet pin name type description lfm[2:0] input loop filter mode selector lfo analog external loop filter port ck output pll output clock lock output pll lock detect signal : active high ncb[7:0] output reference divider test output mc[13:0] output feedback divider test output
4/ 17 ? 2004 hynix semiconductor inc. all rights reserved. h18gpl11s data sheet 5. function descriptions a) normal frequency mode output frequency range : 5mhz ~ 160mhz * pll control setting tdm = ?low?, bypass = ?low? at this condition, the output frequency, f(ck), is actually determined by the following equation. (1) determining output frequency h18gpl11s is ideally suited to provide th e graphics system clock signals required by video signal ad and da. fully programmable feedback and reference divider capability allow virtua lly any frequency to be generate d, not just simple multiples of reference frequency. also pd gain, vc o gain and vco range are programmable for user-define pll characteristics. h18gpl11s generates its output frequencies using charge pump pll techniques. then the output frequency is ratiometri cally related to the reference frequency. f(ck) = f(ref) (feedback divisor) . (reference divisor) . f(ck) : frequency of output, ck f(ref) : frequency of reference pin, ref feedback divisor : m[13:0] +2 reference divisor : n[7:0] +1 * f(ck) range is showed section 3). f(ref) range is restricted by l oop filter mode at section 4).
5/ 17 ? 2004 hynix semiconductor inc. all rights reserved. h18gpl11s data sheet (2) pd gain programming h18gpl11s provides various pd gain. actually pd gain is controlled internally by charge pump current. at charge pump pll, pd gain is charge pump current over 2 . h18gpl11s controls charge pump current by 4-bit resolution with the following equations. icp = . (icpb/16) (16 - icp[3:0] )[a] kpd = icp / 2 [a/rad] icpb : charge pump reference current. typically 40ua icp : charge pump current kpd : pd gain vc[1:0] f(ck) min max 00 80mhz 200mhz 01 120mhz 240mhz 10 160mhz 280mhz 11 200mhz 320mhz b) extended frequency mode * pll control setting tdm = ?low?, bypass = ?high? at this condition, the output frequency, f(ck), is actually determined by the following equation. f(ck) = f(ref) ( feedback divisor) (post divisor) . (reference divider) pre divisor : 2 p[1:0]+1 . table. f(ck) range at extended frequency range .
6/ 17 ? 2004 hynix semiconductor inc. all rights reserved. h18gpl11s data sheet (3) vco range an d gain programming h18gpl11s provides 4 different vco range s and a post divider. vco ranges are controlled by vc[1:0] and clock output frequency is divided by 2 power ( p[1:0] +1) then clock output range has 16 ranges. the ga in of vco which is the ratio of input voltage v.s. clock output frequency variation, kvcop, has 4 different values. following table shows each range by vc[1:0] and kvcop. vc[1:0] p[1:0] fck kvcop min max 00 00 40mhz 100mhz 150mhz/v 01 20mhz 50mhz 75mhz/v 10 10mhz 25mhz 37.5mhz/v 11 5mhz 12.5mhz 18.75mhz/v 01 00 60mhz 120mhz 01 30mhz 60mhz 10 15mhz 30mhz 11 7.5mhz 15mhz 10 00 80mhz 140mhz 01 40mhz 70mhz 10 20mhz 35mhz 11 10mhz 17.5mhz 11 00 100mhz 160mhz 01 50mhz 80mhz 10 25mhz 40mhz 11 12.5mhz 20mhz 150mhz/v 75mhz/v 37.5mhz/v 18.75mhz/v 150mhz/v 75mhz/v 37.5mhz/v 18.75mhz/v 150mhz/v 75mhz/v 37.5mhz/v 18.75mhz/v
7/ 17 ? 2004 hynix semiconductor inc. all rights reserved. h18gpl11s data sheet (4) programmable loop filter h18gpl11s has 7 internal loop filter mode, an d an external loop filter mode, totally 8 mode. following table shows each loop filter mode characteristics. figure 1 represents loop filter schematic. in h18gpl11s, to get sufficient stability margin and efficient loop characteristics, loop filter mode(lfm) must be selected pr operly. each lfm restricts feedback divisor and reference frequency ranges. at internal loop filter mode( lfm : 000 to 110), pd reference input frequency(f(ref)/(ref di visor)) is 150khz to 20mhz. in this mode external loop filter and lfo pin are not needed. if pd ref frequency is smaller than 150khz, the external mode ( lf m : 111) must be selected to get sufficient loop stability. however, it is recommended that pd reference input frequency is bigger than 2mhz for low jitter frequency synthesis. clf clf2 rlf lfo avdd table. loop filter device value figure 1. loop filter schematic. lfm[2:0] rlf [ohm] 000 40k clf [pf] clf2 [pf] 1437 96.4 001 24.1k 1437 96.4 010 40k 518 35.8 011 24.1k 518 35.8 100 24.1k 310 22 101 14.7k 310 22 110 8.9k 310 22 111 external loop filter zero [khz] pole [khz] 2.77 44.0 4.6 73.1 7.68 118.8 12.75 197.2 21.3 321.5 34.9 527 57.7 871
8/ 17 ? 2004 hynix semiconductor inc. all rights reserved. h18gpl11s data sheet (5) pll power down, vco power down and vco initialization h18gpl11s has pll power down mode, vc o power down mode, and vco initialize mode. pd signal is pll power down. when pd is active( active high), h18gpl11s digital circuits do not operate and the charge pump circuit is disabled. v copd signal means vco power down. when vcopd is active(active high), vco does not oscillate. vcoinit is vco initializing signal. during power-up sequence, vcoinit must be activated. to ensure the proper operati on of the h18gpl11s, the activation of vcoinit signal is required just after the deactivation of the vcopd signal. if you want use external vco, vcopd is active only. following figure 2 is a configuration of external vco mode. following equation shows relation of loop filter and pll loop characteristics. kpll = [hz/s] : pll loop gain zero1 = 1/(2 *rlf*clf) [hz] : open loop first zero kvcop*kpd*rlf m[13:0] +2 pol3 = (clf+clf2)/(2 *rlf*clf*clf2) [hz] : open loop third pole kpll is restricted by pd ref frequency, l oop filter zero1, and pole3 according to the following equation. kpll < (pd ref frequency)/6 kpll > 1.5*zero1 kpll < 0.7*pole3 typically kpll is recommended smaller than fpdref/10, kpll is lager than 2*zero1, and kpll is smaller than 0.5*pole3 to get sufficient stability margin.
9/ 17 ? 2004 hynix semiconductor inc. all rights reserved. h18gpl11s data sheet (6) bypass mode h18gpl11s has bypass mode for te st main block of chip. when bypass signal and tdm is active(active high), pll output clock is bpck . (7) digital block test mode at mass product test, h18gpl11s pr ovides digital block test. when tdm is active(active high), bpck clock is provided to the whole digital blocks in h18gpl11s and check mc[13:0] and ncb[7:0] .if cnttest is high, internal counter is toggle each bit by m, or n. h18gpl11s lfo external vco vcon vck ref ck bpck tdm ?1? ?1? vcopd figure 2. external vco conf iguration block diagram at this mode, frequency of ck is determined by section 1.a), and frequency of vck is determined by section 1.b) (8) vco block and charge pump test mode at mass product test, tpdud[1:0] enables you to access the vco control voltage directly from off-chip to get vco gain and to measure char ge pump up or down currents.
10 / 17 ? 2004 hynix semiconductor inc. all rights reserved. h18gpl11s data sheet (9) h18pl11s control modes summary table. mode settings of h18gpl11s tpdud[1:0] = ?00?, tvco[1:0] = ?00?, reset = ?0? mode pd by pass tdm vcopd vcoinit normal mode 0 0 0 0 0 description fck = fref*(m+2)/(n+1) extended mode 0 1 0 0 0 fck = fref*(m+2)*2 p+1 /(n+1) bypass mode 0 1 1 0 0 ck = ~bpck vco initialize mode 0 0 0 0 1 when power turn on, vcoinit must be activated power down mode 1 0 0 1 0 h18gpl11s is disabled at this mode external vco mode 0 0 1 1 0 using external vco digital part test 0 0 1 0 0 digital part toggle test( cnttest = 1) tpdud 01 description charge pump down current test, or vco maximum frequency test table. vco and charge pump test mode p[1:0] = ?11?, pd = ?0?, bypass = ?0?, reset = ?0?,tdm = ?0? vcopd = ?0?, vcoinit = ?0? 10 charge pump up current test, or vco minimum frequency test 00 charge pump normal mode operation 11 lfo pin is high impedance, for charge pump and loop filter leakage test
11 / 17 ? 2004 hynix semiconductor inc. all rights reserved. h18gpl11s data sheet 6. operating conditions symbol parameter min. max. unit dvdd power supply 1.6 2.0 v avdd 1.6 2.0 v dvss-avss 0 50 mv asub 0 50 mv guarding ground top operating temperature item condition min typ max unit pll dynamic current @f(vco)=100mhz 346 ma output frequency 5 - 160 mhz power on lock time when power turn on -- 10msec cycle peak to peak jitter lock state - - 500 psec symbol idd tpolock tjit 45 50 55 % output duty cycle 7. electrical characteristics lock time in lock range -- 2msec lock state, internal loop filter mode 0 100 output frequency 80 - 320 normal range extended range 40 50 60 % output duty cycle extended range tlock dtht dtn fckh fckn mhz normal range
12 / 17 ? 2004 hynix semiconductor inc. all rights reserved. h18gpl11s data sheet 8. timing diagram (1) power on and loop dynamic timing when ck is uv(un-valid) state, frequency of ck is undesirable. in this state h18gpl11s tracks valid frequency of ck . when ck is in the valid state, frequency of ck is frequency of ref multiplied by ( m[13:0] +2)/( n[9:0] +1). tpolock is a power on lock time. while pd is high, loop filter charges are held. when pd is disabled, pll tracks valid frequency fast. however, when pd remains high for a long time, loop filter charges are di scharged slowly and at last charges are completely discharged. after long pd ?s active state, the lock time of h18gpl11s, i.e. tpolock is maximized. tlock is a lock time when control data ( m[13:0] , n[9:0] ) or reference clock frequency are changed in lock range. to ensure the proper operation of the h18gpl11s, the activation of vcoinit signal is required just after the deactivation of the vcopd signal. during power-up sequence vcoinit is recommended to be activated for more than 100ns. power turn on frequency 1 frequency 2 valid uv valid uv valid uv valid data1 data2 ref ck pd, reset m[13:0] or n[7:0] tpolock < tpolock tlock tlock vcoinit lock vcopd uv figure 3. timing diagram
13 / 17 ? 2004 hynix semiconductor inc. all rights reserved. h18gpl11s data sheet (2) bypass mode tdm = ?high?, bypass = ?high? bpck ck t bp t delay bpck ck t delay : 3ns : bpck to ck delay time 9. layout guide (1) power pads guide 1) pll requires dedicated analog ( avdd, avss, asub) and digital (dvdd, dvss) power and ground pads to ensure proper operation. 2) asub ground must be connected from the analog ground pad and merged in front of the pad as can be seen in the figure 4. 3) avdd and dvdd are supplied with 1.8v and 1.8v power respectively. to isolate the analog and the digital pow er and the ground from digital pad ring, use the power cutting cells i.e. diode cells (pdo). refer to the i/o library (hgi1113tp1_typ or hgi1113tp3_typ page 9) for more information. see figure 5 for an example. 4) if you can place more pads for pll, use as many power pads as you can and use those pads with double (multiple)-bond configuration. it is required to reduce power bouncing. 5) you may insert buffers between refere nce clock input pad and pll input pin to make the rise/fall time of the clock input short.
14 / 17 ? 2004 hynix semiconductor inc. all rights reserved. h18gpl11s data sheet (2) placement & routing 1) please place pll at a corner of the ch ip and do not put noisy or high driving i/o pads near the pll. 2) please keep the routing from power pads to pll power pins as short as possible. 3) the power metal width should be larger than the width of the pll ip connection. see figure 6 for an example. 4) do not rout over the pll ip and pl ace 30um space from th e ip to the other circuitry. 5) minimize the crossing of digital core power or signal over the power lines of the pll ip. 6) figure 5 is a placement and routing ex ample of pll. in the figure analog and digital power are separated with diode cut cells. pll pvddas pvssas avdd avss asub figure 4. routing consideration for the analog ground pads
15 / 17 ? 2004 hynix semiconductor inc. all rights reserved. h18gpl11s data sheet pvssas ckin output clock buffer analog part digital part at least 300um at least 500um digital interface place quiescent i/o buffer pvddas pvssas pvddas pdo pdo pdo pdo h18gpl11s pvssas ckin output clock buffer analog part digital part at least 300um at least 500um digital interface place quiescent i/o buffer pvddas pvssas pvddas pdo pdo pdo pdo figure 5. placement and routing consideration of pll figure 6. connector width h18gpl11s w1 w2 connector metal line w2 w1 w1 w2 connector metal line w2 w1

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