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lvcmos/lvttl-to-differential 3.3v, 2.5v lvpecl translator ics85320i idt ? / ics ? 3.3v, 2.5v lvpecl translator 1 ics8532ami rev a november 13, 2006 g eneral d escription the ics85320i is a lvcmos / lvttl-to-differen- tial 3.3v, 2.5v lvpecl translator and a member of the hiperclocks? family of high performance clocks solutions from idt. the ics85320i has a single ended clock input. the single ended clock input accepts lvcmos or lvttl input levels and translates them to 3.3v or 2.5v lvpecl levels. the small outline 8-pin soic package makes this device ideal for applications where space, high performance and low power are important. f eatures ? one differential 2.5v/3.3v lvpecl output ? lvcmos/lvttl clk input ? clk accepts the following input levels: lvcmos or lvttl ? maximum output frequency: 267mhz ? part-to-part skew: 275ps (maximum) ? additive phase jitter, rms: 0.05ps (typical) ? 3.3v operating supply voltage (operating range 3.135v to 3.465v) ? 2.5v operating supply voltage (operating range 2.375v to 2.625v) ? -40c to 85c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages b lock d iagram p in a ssignment ics85320i 8-lead soic 3.90mm x 4.92mm x 1.37mm body package m package top view nc q nq nc 1 2 3 4 q nq clk hiperclocks? ic s v cc clk nc v ee 8 7 6 5
idt ? / ics ? 3.3v, 2.5v lvpecl translator 2 ics8532ami rev a november 13, 2006 ics85320i lvcmos/lvttl-to-differential 3.3v, 2.5v lvpecl translator t able 1. p in d escriptions t able 2. p in c haracteristics r e b m u ne m a ne p y tn o i t p i r c s e d 6 , 4 , 1c nd e s u n u. t c e n n o c o n 3 , 2q n , qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 5v e e r e w o p. n i p y l p p u s e v i t a g e n 7k l ct u p n ip u l l u p. t u p n i k c o l c l t t v l / s o m c v l 8v c c r e w o p. n i p y l p p u s e v i t i s o p : e t o n p u l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t s r e f e r l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k ?
idt ? / ics ? 3.3v, 2.5v lvpecl translator 3 ics8532ami rev a november 13, 2006 ics85320i lvcmos/lvttl-to-differential 3.3v, 2.5v lvpecl translator t able 3a. p ower s upply dc c haracteristics , v cc = 3.3v5% or 2.5v5%, t a = -40c to 85c t able 3b. lvcmos / lvttl dc c haracteristics , v cc = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e v i t i s o p 5 3 1 . 33 . 35 6 4 . 3v 5 7 3 . 25 . 25 2 6 . 2v i e e t n e r r u c y l p p u s r e w o p 5 2a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n ik l c2v c c 3 . 0 +v v l i e g a t l o v w o l t u p n ik l c3 . 0 -3 . 1v i h i t n e r r u c h g i h t u p n ik l cv c c v = n i v 5 6 4 . 3 =5a i l i t n e r r u c w o l t u p n ik l cv c c v = n i v 5 6 4 . 3 =0 5 1 -a t able 3d. lvpecl dc c haracteristics , v cc = 3.3v5% or 2.5v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov c c 4 . 1 -v c c 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov c c 0 . 2 -v c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p 6 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n ? v o t c c . v 2 - a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o contin uous current 50ma surge current 100ma package thermal impedance, ja 112.7c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional op- eration of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n ik l c6 . 1v c c 3 . 0 +v v l i e g a t l o v w o l t u p n ik l c3 . 0 -9 . 0v i h i t n e r r u c h g i h t u p n ik l cv c c v = n i v 5 2 6 . 2 =5a i l i t n e r r u c w o l t u p n ik l cv c c v = n i v 5 2 6 . 2 =0 5 1 -a t able 3c. lvcmos / lvttl dc c haracteristics , v cc = 2.5v5%, t a = -40c to 85c
idt ? / ics ? 3.3v, 2.5v lvpecl translator 4 ics8532ami rev a november 13, 2006 ics85320i lvcmos/lvttl-to-differential 3.3v, 2.5v lvpecl translator t able 4b. ac c haracteristics , v cc = 2.5v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 5 1 2z h m t d p 1 e t o n ; y a l e d n o i t a g a p o r p? z h m 7 6 28 . 07 . 1s n t t i j ; s m r , r e t t i j e s a h p e v i t i d d a r e f f u b n o i t c e s r e t t i j e s a h p e v i t i d d a o t r e f e r : e g n a r n o i t a r g e t n i z h m 0 2 - z h k 2 1 5 0 . 0s p t ) p p ( k s3 , 2 e t o n ; w e k s t r a p - o t - t r a p 5 7 3s p t r t , f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 20 0 7s p c d oe l c y c y t u d t u p t u o 5 45 5% v m o r f d e r u s a e m : 1 e t o n c c . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t u p n i e h t f o t n i o p 2 / d a o l l a u q e h t i w d n a s e g a t l o v y l p p u s e m a s e h t t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d e h t t a d e r u s a e m e r a s t u p t u o e h t , e c i v e d h c a e n o s t u p n i f o e p y t e m a s e h t g n i s u . s n o i t i d n o c . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 3 e t o n t able 4a. ac c haracteristics , v cc = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 7 6 2z h m t d p 1 e t o n ; y a l e d n o i t a g a p o r p? z h m 7 6 28 . 04 . 1s n t t i j ; s m r , r e t t i j e s a h p e v i t i d d a r e f f u b n o i t c e s r e t t i j e s a h p e v i t i d d a o t r e f e r : e g n a r n o i t a r g e t n i z h m 0 2 - z h k 2 1 5 0 . 0s p t ) p p ( k s3 , 2 e t o n ; w e k s t r a p - o t - t r a p 5 7 2s p t r t , f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 20 0 7s p c d oe l c y c y t u d t u p t u o 5 45 5% v m o r f d e r u s a e m : 1 e t o n c c . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t u p n i e h t f o t n i o p 2 / d a o l l a u q e h t i w d n a s e g a t l o v y l p p u s e m a s e h t t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d e h t t a d e r u s a e m e r a s t u p t u o e h t , e c i v e d h c a e n o s t u p n i f o e p y t e m a s e h t g n i s u . s n o i t i d n o c . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 3 e t o n
idt ? / ics ? 3.3v, 2.5v lvpecl translator 5 ics8532ami rev a november 13, 2006 ics85320i lvcmos/lvttl-to-differential 3.3v, 2.5v lvpecl translator a dditive p hase j itter input/output additive phase jitter @ 156.25mhz (12khz to 20mhz) = 0.05ps typical 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1m 10m 100m the spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz as with most timing specifications, phase noise measurements have issues. the primary issue relates to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device band to the power in the fundamental. when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. meets the noise floor of what is shown, but can actually be lower. the phase noise is dependant on the input source and measurement equipment. o ffset f rom c arrier f requency (h z ) ssb p hase n oise dbc/h z
idt ? / ics ? 3.3v, 2.5v lvpecl translator 6 ics8532ami rev a november 13, 2006 ics85320i lvcmos/lvttl-to-differential 3.3v, 2.5v lvpecl translator p arameter m easurement i nformation p art - to -p art s kew 2.5v c ore /2.5v o utput l oad ac t est c ircuit 3.3v c ore /3.3v o utput l oad ac t est c ircuit scope qx nqx lvpecl v ee 2v -1.3v 0.165v v cc o utput r ise /f all t ime clock outputs 20% 80% 80% 20% t r t f v sw i n g p ropagation d elay t sk(o) nqx qx nqy qy part 1 part 2 t pd clk nclk q nq o utput d uty c ycle /p ulse w idth /p eriod t pw t period t pw t period odc = x 100% q nq -0.5v 0.125v scope qx nqx lvpecl v ee 2v v cc
idt ? / ics ? 3.3v, 2.5v lvpecl translator 7 ics8532ami rev a november 13, 2006 ics85320i lvcmos/lvttl-to-differential 3.3v, 2.5v lvpecl translator a pplication i nformation v cc - 2v 50 ? 50 ? rtt z o = 50 ? z o = 50 ? fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 ? 125 ? 84 ? 84 ? z o = 50 ? z o = 50 ? fout fin the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that gen- erate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal dis- tortion. figures 1a and 1b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board design- ers simulate to guarantee compatibility across all printed circuit and clock component process variations. t ermination for lvpecl o utputs f igure 1b. lvpecl o utput t ermination f igure 1a. lvpecl o utput t ermination
idt ? / ics ? 3.3v, 2.5v lvpecl translator 8 ics8532ami rev a november 13, 2006 ics85320i lvcmos/lvttl-to-differential 3.3v, 2.5v lvpecl translator t ermination for 2.5v lvpecl o utput figure 2a and figure 2b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cc - 2v. for v cc = 2.5v, the v cc - 2v is very close to ground level. the r3 in figure 2b can be eliminated and the termination is shown in figure 2c. f igure 2b. 2.5v lvpecl d river t ermination e xample f igure 2a. 2.5v lvpecl d river t ermination e xample r2 62.5 zo = 50 ohm r1 250 + - 2.5v 2,5v lvpecl driv er r4 62.5 r3 250 zo = 50 ohm 2.5v vcc=2.5v r1 50 r3 18 zo = 50 ohm zo = 50 ohm + - 2,5v lvpecl driv er vcc=2.5v 2.5v r2 50 2,5v lvpecl driv er vcc=2.5v r1 50 r2 50 2.5v zo = 50 ohm zo = 50 ohm + - f igure 2c. 2.5v lvpecl t ermination e xample
idt ? / ics ? 3.3v, 2.5v lvpecl translator 9 ics8532ami rev a november 13, 2006 ics85320i lvcmos/lvttl-to-differential 3.3v, 2.5v lvpecl translator r1 50 (u1-8) r4 133 r6 133 optional termination r2 50 clk_in r7 82.5 zo = 50 ohm c2 0.1uf r3 50 r5 82.5 c1 10uf zo = 50 ohm vcc = 3.3v zo = 50 ohm zo = 50 ohm vcc vcc = 3.3v + - u1 85320 1 2 3 4 8 7 6 5 nc q nq nc vcc clk nc vee a pplication s chematic e xample figure 3 shows an example of ics85320i application schematic. in this example, the device is operated at v cc =3.3v. the decoupling capacitor should be located as close as possible to the power pin. for lvpecl output termination, only two terminations f igure 3. ics85320i a pplication s chematic e xample examples are shown in this schematic. for more termination approaches, please refer to the lvpecl termination application note.
idt ? / ics ? 3.3v, 2.5v lvpecl translator 10 ics8532ami rev a november 13, 2006 ics85320i lvcmos/lvttl-to-differential 3.3v, 2.5v lvpecl translator p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics85320i. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics85320i is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 25ma = 86.6mw ? power (outputs) max = 30.2mw/loaded output pair total power _max (3.465v, with all outputs switching) = 86.6mw + 30.2mw = 116.6mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3c/w per table 5 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.117w * 103.3c/w = 97.1c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). t able 5. t hermal r esistance ja for 8- pin soic, f orced c onvection ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 153.3c/w 128.5c/w 115.5c/w multi-layer pcb, jedec standard test boards 112.7c/w 103.3c/w 97.1c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
idt ? / ics ? 3.3v, 2.5v lvpecl translator 11 ics8532ami rev a november 13, 2006 ics85320i lvcmos/lvttl-to-differential 3.3v, 2.5v lvpecl translator 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 4. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cc - 2v. for logic high, v out = v oh_max = v cc_max ? 1.0v (v cc_max - v oh_max ) = 1.0v for logic low, v out = v ol_max = v cc_max ? 1.7v (v cc_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max - 2v))/r l ] * (v cc_max - v oh_max ) = [(2v - (v cc_max - v oh_max )) /r l ] * (v cc_max - v oh_max ) = [(2v - 1v)/50 ? ] * 1v = 20.0mw pd_l = [(v ol_max ? (v cc_max - 2v))/r l ] * (v cc_max - v ol_max ) = [(2v - (v cc_max - v ol_max )) /r l ] * (v cc_max - v ol_max ) = [(2v - 1.7v)/50 ? ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30.2mw f igure 4. lvpecl d river c ircuit and t ermination q1 v out v cc rl 50 v cc - 2v
idt ? / ics ? 3.3v, 2.5v lvpecl translator 12 ics8532ami rev a november 13, 2006 ics85320i lvcmos/lvttl-to-differential 3.3v, 2.5v lvpecl translator r eliability i nformation t ransistor c ount the transistor count for ics85320i is: 269 t able 6. ja vs . a ir f low t able for 8 l ead soic ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 153.3c/w 128.5c/w 115.5c/w multi-layer pcb, jedec standard test boards 112.7c/w 103.3c/w 97.1c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
idt ? / ics ? 3.3v, 2.5v lvpecl translator 13 ics8532ami rev a november 13, 2006 ics85320i lvcmos/lvttl-to-differential 3.3v, 2.5v lvpecl translator p ackage o utline - m s uffix for 8 l ead soic t able 7. p ackage d imensions reference document: jedec publication 95, ms-012 l o b m y s s r e t e m i l l i m n u m i n i mm u m i x a m n8 a5 3 . 15 7 . 1 1 a0 1 . 05 2 . 0 b3 3 . 01 5 . 0 c9 1 . 05 2 . 0 d0 8 . 40 0 . 5 e0 8 . 30 0 . 4 ec i s a b 7 2 . 1 h0 8 . 50 2 . 6 h5 2 . 00 5 . 0 l0 4 . 07 2 . 1 0 8
idt ? / ics ? 3.3v, 2.5v lvpecl translator 14 ics8532ami rev a november 13, 2006 ics85320i lvcmos/lvttl-to-differential 3.3v, 2.5v lvpecl translator while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extraordinary environmental r equirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. t able 8. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t i m a 0 2 3 5 8 s c ii m a 0 2 3 5 8c i o s d a e l 8e b u tc 5 8 o t c 0 4 - t i m a 0 2 3 5 8 s c ii m a 0 2 3 5 8c i o s d a e l 8l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - f l i m a 0 2 3 5 8 s c il i a 0 2 3 5 8c i o s " e e r f - d a e l " d a e l 8e b u tc 5 8 o t c 0 4 - t f l i m a 0 2 3 5 8 s c il i a 0 2 3 5 8c i o s " e e r f - d a e l " d a e l 8l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
idt ? / ics ? 3.3v, 2.5v lvpecl translator 15 ics8532ami rev a november 13, 2006 ics85320i lvcmos/lvttl-to-differential 3.3v, 2.5v lvpecl translator t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d a 1 4 1 . t e l l u b e e r f - d a e l d e d d a - n o i t c e s s e r u t a e f e e r f - d a e l d e d d a , d n a g n i k r a m d r a d n a t s d e t c e r r o c - e l b a t n o i t a m r o f n i g n i r e d r o . e t o n d n a , g n i k r a m , r e b m u n t r a p . t u o y a l t e e h s a t a d d e t a d p u 6 0 / 3 1 / 1 1
innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 corporate headquarters integrated device t echnology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited 321 kingston road leatherhead, surrey kt22 7tu england +44 (0) 1372 363 339 fax: +44 (0) 1372 378851 ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa ics85320i lvcmos/lvttl-to-differential 3.3v, 2.5v lvpecl translator

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