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1 4-phase interleaved boost pwm controller with light load efficiency enhancement ISL78225 the ISL78225 4-phase controller is targeted for applications where high efficiency (>95%) an d high power are required. the multiphase boost converter architecture uses interleaved timing to multiply channel ripple freque ncy and reduce input and output ripple. lower ripple results in fewer input/output capacitors and therefore lower component cost and smaller implementation area. the ISL78225 has a dedicated pin to initiate the phase dropping scheme for higher efficiency at light load by dropping phases based on the load current, so the switchin g and core losses in the converter are reduced significantly. as the lo ad increases, the dropped phase(s) are added back to accommodate he avy load transients and improve efficiency. input current is sensed continuously by measuring the voltage across a dedicated current sense resistor or inductor dcr. this current sensing provides precis ion channel-current balancing, and per-phase overcurrent protection. a separate totalizing current limit function provides ov ercurrent protection for all the phases combined. this two-stage current protection provides maximum performance and circuit reliability. ISL78225 can also provide for input voltage tracking via the vref2 pin. the comparison refere nce voltage will be the lower of the vref2 pin or the internal 2v reference. by using a resistor network between vin and vref2 pin, the output voltage can track input voltage to limit the output power during automotive cranking conditions. ISL78225 can output a clock signal for expanding operation to 8 phases, which offers high system flexibility. the threshold-sensitive enable input is available to accurately coordinate the start-up of the ISL78225 with any other voltage rail. features ? peak current mode pwm control with adjustable slope compensation ? precision resistor/dcr current sensing ? 2, 3 or 4-phase operation ? adjustable phase dropping/diode emulation/pulse skipping for high efficiency at light load ? adjustable switching frequency or external synchronization from 75khz up to 1mhz per phase ? over-temperature/overvoltage protection ?2v 1.0% internal reference ? pb-free 44-lead 10x10 ep-tqfp (rohs compliant) ? -40c to +125c operating temperature range ? aec-q100 qualified ? ts16949 compliant applications ? automotive power supplies - start/stop dc/dc converter -fuel pumps - injection system ? audio amplifier power supplies ? telecom and industrial power supplies figure 1. efficiency vs output current vs phase dropping mode efficiency output current (a) 0.73 0.78 0.83 0.88 0.93 0.98 012345678910 with phase dropping without phase dropping 16v input, 36v output synchronous boost caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. december 15, 2011 fn7909.0
ISL78225 2 fn7909.0 december 15, 2011 pin configuration ISL78225 (44 ld 10x10 ep-tqfp) top view gnd vref2 fb comp ss fs 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 slope pll_comp sync clk_out pwm_inv pwm_tri pwm1 28 27 26 25 24 23 22 21 20 19 18 dnc isen1p isen3n isen3p dnc dnc isen2n isen2p 39 38 37 36 35 34 33 32 31 30 29 44 43 42 41 40 vin_ovb vin_sen iout mode gnd vcc vin dnc dnc isen4p isen4n pgood en dmax vout_ovb vout_sen pwm3 p_com pwm2 dnc isen1n pwm4 drive_en functional pin descriptions pin # symbol description 1 fs a resistor placed from fs to ground will set the pwm switching frequency. 2 ss use this pin to set-up the desired so ft-start time. a capacitor placed from ss to ground will set up the soft-start ramp rate and in turn determine the soft-start time. 3 comp the output of the transconductance amplifier. pl ace the compensation networ k between comp and gnd for compensation loop design. 4 fb the inverting input of the transconductance amplifier. a resistor network should be placed between the fb pin and output rail to set the output voltage. 5 vref2 external reference input to the transconductance am plifier. when the vref2 pin voltage drops below 1.8v, the internal reference will be shifted from 2v to vref2. the vref2 voltage can be programmed by connecting a resistor divider network from vcc or vin. 6 gnd bias and reference ground for the ic. 7 slope this pin programs the slope of the internal slope compensation. a resistor should be connected from the slope pin to gnd. please refer to ?adjustable slope compensation? on page 19 for how to choose the resistor value. 8 pll_comp this pin serves as the compensation node for the pll. a second order passive loop filter connected between pll_comp pin and gnd compensates the pll feedback loop. 9 sync frequency synchronization pin. connecting the sync pin to an external square pulse waveform (typically 20% to 80% duty cycle) will synchronize the converter switching frequency to the fundamental frequency of the input waveform. if sync function is not used, tie the sync pi n to gnd. a 500na current sour ce is connected internally to pull-down the sync pin if it is left open. 10 clk_out this pin provides a clock signal to synchronize with another ISL78225. this provides scalability and flexibility. the rising edge signal on the clkout pin is in ph ase with the leading edge of the pwm1 signal. 11 pwm_inv this pin determines the polarity of the pwm output signal. pulling this pin to gn d will force normal operation. pulling this pin to vcc will invert th e pwm signal. this function provides the flexibility for the ISL78225 to work with different drivers.
ISL78225 3 fn7909.0 december 15, 2011 12 pwm_tri this pin enables the tri-level of the pwm output sign al. pulling this pin to gnd forces the pwm output to be traditional two level logic. pulling the pwm_tri pin to vcc will enable tri-level pwm signals, then the pwm output can be at the 2.5v tri-level condition. 13, 14, 16, 17 pwm1, pwm3, pwm2, pwm4 pulse width modulation outputs. connect these pins to the pwm input pins of the external driver ics. the number of active channels is determined by the state of pw m3, pwm4. for 2-phase operation, connect pwm3 to vcc; similarly, connect pwm4 to vcc for 3-phase operation. 15 p_com pwm compensation pin; connec t this pin through resistor to vcc. 19 drive_en driver enable output pin. this pin is connected to the enable pin of mosfet drivers. 18,20,25, 26,31,32 dnc do not connect ? these pins must be left floating. 21, 22, 23, 24, 27, 28, 29, 30 isen1n, isen1p, isen3n, isen3p, isen2n, isen2p, isen4n, isen4p the isenxp and isenxn pins are current sense inputs to in dividual differential amplif iers. the sensed current is used as a reference for current mode control and overcu rrent protection. inactive channels should have their respective isenxp pins connected to vin and isenxn pins left open. the ISL78225 utilizes external sense resistor current sensing method or inductor dcr sensing method. 33 vin connect input rail to this pin. this pin is connected to the internal linear regulator, generating the power necessary to operate the chip. it is recomm ended the dc voltage applied to the vin pin does not exceed 40v. 34 vcc this pin is the output of the internal linear regulator that supplies the bias and gate voltage for the ic. a minimum 4.7f decoupling ceramic capacitor should be connected from vcc to gnd. the controller starts to operate when the voltage on this pin exceeds the rising por threshold and shuts down when the voltage on this pin drops below the falling por threshold. this pin can be connecte d directly to a +5v supply if vin falls below 5.6v. 35 gnd bias and reference ground for the ic. 36 mode mode selection pin. pull this pin to logic high for forced pwm mode; phase dropping/adding is inactive during forced pwm mode. connecting a resistor from mode pin to gnd will initialize phase dropping mode (pdm). in pdm, a 5a fixed reference current will flow out of th e mode pin, and the phase dropping threshold can be programmed by adjusting the resistor value. 37 iout iout is the current monitor pin with an additional ocp adjustment function. an rc network needs to be placed between iout and gnd to ensure the proper operation. the vo ltage at the iout pin will be proportional to the input current. if the voltage on the iout pin is higher than 2v, ISL78225 will go into overcurrent protection mode and the chip will latch off until the en pin is toggled. 38 vin_sen the vin_sen pin is used for sensing the vin voltage. a resistor divider network is connected between this pin and boost power stage input voltage rail. when the voltage on vin_sen is greater than 2.4v , the vin_ovb pin will be pulled low to indicate an input overvoltage condition. the threshold voltage can be programmed by changing the divider ratios. 39 vin_ovb the vin_ovb pin is an open drai n indicator of an overvoltage condition at the input. when the voltage on the vin_sen pin is greater than the 2.4v threshold, the vin_ovb pin will be pulled low. 40 vout_sen the vout_sen pin is used for sensing the output volt age; a resistor divider network is connected between this pin and output voltage rail. when the voltage on vout_sen pin is greater than 2.4v, vout_ovb pin will be pulled low, indicating an output overvoltage condition. 41 vout_ovb the vout_ovb pin is an open drain indicator of an overvoltage condition at the output. when the voltage on the vout_sen pin is greater than the 2.4v threshold, the vo ut_ovb pin will be pulled low and latched, toggling vin or en will reset the latch. 42 dmax dmax pin sets the maximum duty cycle of the pwm modulator. if the dmax pin is connected to gnd, the maximum duty cycle will be set to 91.7%. floating this pin will limit the duty cycle to 75% and connecting the dmax pin to vcc will limit the duty cycle to 83.3%. 43 en this pin is a threshold-sensitive enable input for th e controller. connecting the power supply input to en pin through an appropriate resistor divider provides a mean s to synchronize power-up of the controller and the mosfet driver ics. when en pin is driven above 1.2v, th e ISL78225 is active depending on status of the internal por, and pending fault states. driving the en pin below 1.1v will clear all fault states and the ISL78225 will soft-start when re-enabled. 44 pgood this pin is used as an indication of the end of soft-start and output regulation. it is an open-drain logic output that is low impedance until the soft-start is completed. it will be pulled low again once the uv/ov/oc/ot conditions are detected. exposed pad it is recommended to solder the exposed pad to the ground plane. functional pin descriptions (continued) pin # symbol description
ISL78225 4 fn7909.0 december 15, 2011 ISL78225 block diagram ordering information part number (notes 1, 2, 3) part marking temp range (c) package tape & reel (pb-free) pkg. dwg. # ISL78225anez-t ISL78225 anez -40 to +125 44 ld ep-tqfp q44.10x10a notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL78225 . for more information on msl please see techbrief tb363 . 5v ldo vin vcc vin_ovb vin_sen 2.4v ov_in 1.2v en por soft- start logic ss drive_en s q r vout_sen 2.4v 2.4v 0.8vref fb ov_out uv pgood ov_out ov_in uv oc ot gm vref2 2v fb comp sync detect vco sync clk_out pll_comp dmax fs slope compensation slope s q r2 r1 csa isen1p isen1n pwm control pwm1 pwm_tri pwm_inv mode mode dmax dmax ot oc ov_out fault control circuits duplicate for each channel isen1 iout 2v oc_all 160a oc_ph oc_all oc_ph vout_ovb ref 2v over temp ot iout1 phase drop control adder iout1 iout4 ph3 ph4 gnd 5a zcd (for ph1 & ph2 only) 20k p _ com
ISL78225 5 fn7909.0 december 15, 2011 typical application 1: 4-phase synchronous bo ost converter with sense resistor current sensing note: please see isl78420 for an automotive qualified 100v synchronous boost driver. ISL78225 pgood en dmax vout_ovb vout_sen vin_ovb vin_sen iout mode gnd vcc vin isen4p isen4n isen2p isen2n nc isen3p isen3n isen1p isen1n nc drive_en nc pwm4 pwm2 p_com pwm3 pwm1 pwm_tri pwm_inv clk_out sync pll_comp slope gnd vref2 fb comp fs ss pwm1 pwm3 pwm2 pwm4 vcc load + + vout_sen vout_sen vin vout vcc lgate ugate phase pwm en phase 1 phase 2 phase 3 phase 4 isen4p isen4n isen2p isen2n isen3p isen3n isen1p isen1n isen2p isen2n isen3p isen3n isen4p isen4n pwm1 pwm2 pwm3 pwm4 driver en en en vcc nc nc nc
ISL78225 6 fn7909.0 december 15, 2011 typical application 2: 4-phase standard boost converter with dcr current sensing ISL78225 pgood en dmax vout_ovb vout_sen vin_ovb vin_sen iout mode gnd vcc vin isen4p isen4n isen2p isen2n nc isen3p isen3n isen1p isen1n nc drive_en pwm4 pwm2 p_com pwm3 pwm1 pwm_tri pwm_inv clk_out sync pll_comp slope gnd vref2 fb comp fs ss pwm1 pwm3 pwm2 pwm4 vcc load + + vout_sen vout_sen vin vout vcc lgate pwm en phase 1 phase 2 phase 3 phase 4 isen4p isen4n isen2p isen2n isen3p isen3n isen1p isen1n isen2p isen2n isen3p isen3n isen4p isen4n pwm1 pwm2 pwm3 pwm4 driver l dcr c r en en en nc vcc nc nc nc
ISL78225 7 fn7909.0 december 15, 2011 absolute maximum ratings supply voltage, vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd-0.3v to +45v all isen_ pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v in -5v to v in +0.3v vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd-0.3v to +6v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd-0.3v to v cc +0.3v esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . .2.5kv machine model (tested per jesd-a115-a) . . . . . . . . . . . . . . . . . . . 200v charge device model (tested per jesd22-c101c). . . . . . . . . . . . . 1.5kv latch up (tested per jesd78b, class ii, level a) . . . . . . . . . . . . . . . 100ma thermal information thermal resistance (typical) ja (c/w) jc (c/w) 44 ld ep-tqfp package (notes 4, 5) . . . . . . 28 2.5 maximum junction temperature . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp operating conditions voltage at vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.6v to +40v all isen_ pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vin-5v to vin+0.3v voltage at vcc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v 5% ambient temperature (auto) . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications operating conditions: v in = 12v, t a = -40c to +125c, unless otherwise specified. typical specifications are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +125c. parameter test conditions min (note 6) typ max (note 6) units supply input input voltage range 5.6 12 40 v input supply current (normal mode) v in = 12v, r fs = 158k (for f s = 250khz) , en = 5v 8 12 ma input supply current (shutdown mode) v in = 12v, r fs = 158k (for f s = 250khz) , en = 0v 10 a internal linear regulator ldo output voltage (vcc pin) v in > 5.6v, c l = 4.7f from vcc to gnd, i vcc < 50ma 4.75 5 5.25 v ldo current limit (vcc pin) vcc = 3v, c l = 4.7f from vcc to gnd 200 (note 7) ma power-on reset (por) and enable por threshold vcc rising 4.4 4.5 4.6 v vcc falling 4.1 4.2 4.3 v en threshold rising 1.1 1.2 1.3 v hysteresis 70 mv oscillator accuracy of switching frequency setting r fs = 158k from fs to gnd 225 250 275 khz adjustment range of switching frequency 75 1000 khz fs pin voltage 1v soft-start soft-start current c ss = 2.2nf from ss to gnd 4 5 6 a soft-start pre-bias voltage range 02 v soft-start pre-bias voltage accuracy v fb = 500mv -25 25 mv soft-start clamp voltage 3.4 v reference voltage system accuracy -40c to +125c, measure at fb pin, v ref2 > 2.5v 1.98 2 2.02 v fb pin input bias current v fb = 2v, v ref2 > 2.5v -1 1 a v ref2 pin input bias current v ref2 = 1.6v -1 1 a
ISL78225 8 fn7909.0 december 15, 2011 v ref2 external reference voltage range 0.7 1.8 v v ref2 external reference voltage accuracy -40c to +125c, measure at fb pin, v ref2 = 1.8v -1 1 % -40c to +125c, measure at fb pin, v ref2 = 0.7v -1.5 1.5 error amplifier transconductance gain 2ms output impedance 5m ? unity gain bandwidth c comp = 100pf from comp pin to gnd 11 mhz slew rate c comp = 100pf from comp pin to gnd 2.5 v/s output current capability 300 a maximum output voltage 3.5 v minimum output voltage 0.5 v pwm core duty cycle matching i isenxp = 60a, r slope = 30.1k, f s = 250khz, v comp = 2v, 4-phase, t a = +25c -6 6 % zero crossing detection (zcd) threshold for pwm1/pwm2 r sen1, 2 = 750 ? 3mv leading edge blanking (audio mode) v mode = vcc, v pwm_tri = vcc, v comp = 0.5v ts/12 (note 8) ns leading edge blanking (other mode) v mode <4v or v pwm_tri = gnd, v comp = 0.5v 130 ns slope pin voltage 385 515 650 mv isenxn bias current v isenxn = v isenxp , from v in - 1v to v in 0.3 a isenxn, isenxp common mode voltage range v in > 12v v in -5 v in v pwmx output pwmx output voltage low i pwmx = -500a 0.5 v pwmx output voltage high i pwmx = +500a 4.5 v pwmx tri-state output voltage i pwmx = 100a 2.3 2.5 2.7 v pwmx pull-down current during phase detection time (t 3 on figure 14), v pwm = 1v 50 a pwm3, pwm4 disable threshold during phase detection time (t 3 on figure 14) 3.5 v phase adding/dropping mode pull-up current v mode = 2.4v 4.2 5.1 5.6 a v iout threshold, 4-phase, drop phase 4 v mode = 1.6v 1.175 1.2 1.225 v v iout threshold, 4-phase, drop phase 3 v mode = 1.6v 0.775 0.8 0.825 v v iout threshold, 3-phase, drop phase 3 v mode = 1.8v 1.175 1.2 1.225 v v iout threshold hysteresis 40 mv phase drop disable threshold at mode pin 3.5 4v current sense and overcurrent protection peak current limit for individual channel 160 a iout current tolerance i isenxp = 60a, 4-phase 173 187 200 a maximum voltage limit at iout pin 2.0 v dmax pin dmax threshold, high 3 v dmax threshold, low 2 v dmax floating voltage during phase detection time (t 3 on figure 14) 2.5 v electrical specifications operating conditions: v in = 12v, t a = -40c to +125c, unless otherwise specified. typical specifications are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +125c. (continued) parameter test conditions min (note 6) typ max (note 6) units
ISL78225 9 fn7909.0 december 15, 2011 max duty cycle, dmax = gnd v comp = 3.5v 91.7 % max duty cycle, dmax = float v comp = 3.5v 75 % max duty cycle, dmax = vcc v comp = 3.5v 83.3 % dmax source/sink current during t 3 on figure 14 50 a dmax source/sink current after t 3 on figure 14 -1 1 a pwm_tri, pwm_inv, sync pin digital logic input leakage current en < 1v -1 1 a input pull-down current en > 2v, pin voltage = 2.1v 0.4 1.5 a logic input low 0.8 v logic input high 2 v drive_en, clk_out pin output high voltage i drive_en = 500a 4.5 v output low voltage i drive_en = -500a 0.5 v vout sense pin input leakage current -1 1 a threshold voltage 2.325 2.4 2.475 v vin sense pin input leakage current -1 1 a threshold voltage 2.325 2.4 2.475 v hysteresis 110 mv vout_ovb, vin_ovb pin leakage current v pin = high 1 a low voltage i pin = 0.5ma 0.2 v power good monitor pin pgood leakage current pgood = high 1 a pgood low voltage i pgood = 0.5ma 0.2 v overvoltage rising trip point v fb /v ref , v ref2 > 2.5v 117 120 123 % overvoltage rising hysteresis v fb /v ref , v ref2 > 2.5v 5 % undervoltage rising trip point v fb /v ref , v ref2 > 2.5v 77 80 83 % undervoltage rising hysteresis v fb /v ref , v ref2 > 2.5v 5 % over-temperature protection over-temperature trip point 160 c over-temperature re covery threshold 145 c notes: 6. parameters with min and/or max limits are 100% tested at +25c , unless otherwise noted. compliance to datasheet limits is ass ured by one or more methods: production test, characterization and/or design. 7. please refer to ldo current derating curve in ?internal 5v ldo output current limit derating curves? on page 19 for i max vs v in . 8. ts = switching period = 1/(switching frequency). electrical specifications operating conditions: v in = 12v, t a = -40c to +125c, unless otherwise specified. typical specifications are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +125c. (continued) parameter test conditions min (note 6) typ max (note 6) units
ISL78225 10 fn7909.0 december 15, 2011 typical performance curves figure 2. 10v input efficiency vs output current vs phase dropping mode figure 3. 16v input efficiency vs output current vs phase dropping mode figure 4. output voltage vs output curren t figure 5. output voltage vs input voltage figure 6. full load output ripple figure 7. full step load transient efficiency output current (a) 0.73 0.78 0.83 0.88 0.93 0.98 012345678910 with phase dropping without phase dropping 10v input, 36v output synchronous boost efficiency output current (a) 0.73 0.78 0.83 0.88 0.93 0.98 012345678910 with phase dropping without phase dropping 16v input, 36v output synchronous boost output voltage (v) output current (a) 35.5 35.6 35.7 35.8 35.9 36.0 36.1 36.2 36.3 36.4 36.5 012345678910 10v input output voltage (v) input voltage (v) 35.5 35.6 35.7 35.8 35.9 36.0 36.1 36.2 36.3 36.4 36.5 10 11 12 13 14 15 16 10a output 10v input, 36v @ 10a output 1s/div c1 = phase 1, 20v/div c4 = vout (ac-coupled), 100mv/div 10v input, 0 to 10a to 0 step load 2ms/div c1 = phase 1, 20v/div c4 = vout (ac-coupled), 100mv/div
ISL78225 11 fn7909.0 december 15, 2011 figure 8. waveforms with pwm_inv = gnd figure 9. waveforms with pwm_inv = v cc figure 10. full load waveforms figure 11. enable/disable waveforms figure 12. modulating vref2 input typical performance curves (continued) c1 = pwm1, 5v/div c2 = pwm2, 5v/div c3 = pwm3, 5v/div 1s/div c4 = clk_out, 5v/div c1 = pwm1, 5v/div c2 = pwm2, 5v/div c3 = pwm3, 5v/div 1s/div c4 = clk_out, 5v/div c1 = pwm1, 5v/div c2 = il1, 5a/div c3 = pwm3, 5v/div 1s/div c4 = pwm4, 5v/div 16v input, 36v @ 10a output c1 = en, 2v/div c2 = vcc, 5v/div c3 = pgood, 5v/div 1s/div c4 = vout, 20v/div 10v input, 36v @ 1a output c1 = vref2, 1v/div 20ms/div c4 = vout, 20v/div 10v input, 10a output
ISL78225 12 fn7909.0 december 15, 2011 operation description multiphase power conversion the technical challenges associated with producing a single-phase converter that is bo th cost-effective and thermally viable for high power applications have forced a change to the cost-saving approach of mult iphase solution. the ISL78225 controller helps reduce the comp lexity of implementation by integrating vital functions and requiring minimal output components. interleaving the switching of each channel in a multiphase converter is timed to be symmetrically out-of-phase with each of the other channels. take a 3-phase converter for example; each channel switches 1/3 cycle after the previous channel and 1/3 cycle before the following channel. as a result, the three-phase converter has a combined ripple frequency three times greater than the ripple frequency of any one phase. in addition, the peak-to-peak amplitude of the combined indu ctor current is reduced in proportion to the number of phases (equations 1 and 2). the increased ripple frequency and the lower ripple amplitude mean that the designer can use less per-channel inductance and lower total input and output capacitance for any performance specification. figure 13 illustrates the multiplicative effect on input ripple current. the three channel currents (i l1 , i l2 , and i l3 ) combine to form the ac ripple current and the dc input current. the ripple component has three times the ripple frequency of each individual channel current. each pwm pulse is triggered 1/3 of a cycle after the start of the pwm pulse of the previous phase. to understand the reduction of the ripple current amplitude in the multiphase circuit, examine th e equation repr esenting an individual channel?s peak-to-peak inductor current. in equation 1, v in and v out are the input and the output voltages respectively, l is the single-channel inductor value, and f s is the switching frequency. the input capacitors conduct the ripple component of the inductor current. in the case of multiphase converters, the capacitor current is the sum of the ripple currents from each of the individual channels. compare equation 1 to the expression for the peak-to-peak current after th e summation of n symmetrically phase-shifted inductor currents in equation 2. peak-to-peak ripple current decreases by an amount proportional to the number of channels. reducing the inductor ripple current allows the designer to use fewer or less costly input capacitors. pwm operations the timing of each channel is set by the total number of active channels. the default channel setti ng for the ISL78225 is 4, and the switching cycle is defined as the time between pwm pulse initiation signals of each channe l. the cycle time of the pulse initiation signal is the inversion of the switching frequency set by the resistor between the fs pi n and ground. the pwm signals command the mosfet drivers to turn on/off the channel mosfets. in the default 4-phase operation, the pwm2 pulse starts 1/4 of a cycle after pwm1, the pwm3 pulse starts 1/4 of a cycle after pwm2, and the pwm4 pulse starts 1/4 of a cycle after pwm3. phase selection the ISL78225 can work in 2, 3, or 4-phase configuration. connecting the pwm4 to vcc selects 3-phase operation and the pulse times are spaced in 1/3 cycle increments. connecting the pwm3 to vcc selects 2-phase operation and the pulse times are spaced in 1/2 cycle increments. unused current sense inputs must be left floating. modes of operation the different modes of operation will be determined by the voltage combinations of the mo de pin and the pwm_tri pin. if automatic phase adding/droppin g function is not needed, the mode pin should be tied to vcc (logic high). if higher light load efficiency is preferred, phase adding/dropping function could be implemented by connecting the mode pin through a resistor to gnd. a 5a reference current will flow out of the mode pin to generate corresponding v mode . v mode is used to compare with v iout to determine the phase adding/dropping level. when pwm_tri is tied to gnd (logic low), the pwm outputs will be 2-levels (i.e., 0v and 5v). when pwm_tri is pulled to vcc (logic high), apart from generati ng the 0v and 5v pwm signals, the pwm outputs can also generate 2.5v tri-level signal. the external driver can identify this tri-level signal and turn off both low side and high side ou tput signals accordingly. i pp v out v in ? () v in lf s v out -------------------------------------------- - = (eq. 1) i c pp ? () v out nv in ? () v in lf s v out -------------------------------------------------- - = (eq. 2) figure 13. pwm and inductor-current waveforms for 3-phase converter time pwm2 pwm1 il2 il1 il1 + il2 + il3 il3 pwm3
ISL78225 13 fn7909.0 december 15, 2011 the truth table regarding v mode and v pwm_tri for different modes of applications is summarized as in table 1. considerations for audio amplifier power supply application for multiphase boost converters used in audio amplifier applications, it is preferred to have the following features: 1. automatic phase dropping function is not needed because the load is fast changing. 2. in car audio amplifier applications, the switching frequency is preferred to be fixed, such that it will not interfere with fm/am band. 3. for synchronous boost, diode emulation is needed during start-up in order to prevent ne gative current dumping to the input side. 4. for synchronous boost, a maximum duty cycle limitation on the synchronous fet is preferred. based on the above mentioned ?preferred features?, for audio amplifier applications, it does not need phase dropping/adding, but it needs a tri-state pwm signal if synchronous boost structure is used. also, in order to limit the maximum duty cycle of the synchronous fet, the minimal turn on time of the active fet (low side fet for boost structure) will be changed from fixed 130ns to variable time, which is 1/12 of the switching periods. operation initialization before soft-start prior to converter initialization, pr oper conditions must exist on the enable inputs (en pin) and vcc pin. when both conditions are met, the controller begins soft-start. on ce the output voltage is within the proper window of operation, v pgood is asserted logic high. figure 14 shows the ISL78225 inte rnal circuit functions before the soft-start begins. as shown on figure 14, there ar e 5 time intervals before the soft-start is initialized. they are specified as t 1 , t 2 , t 3 , t 4 and t 5 , respectively. the descriptions for each time interval are as follows: time t 1 : the enable comparator hold s the ISL78225 in shutdown until the v en rises above 1.2v at the beginning of t 1 time period. during t 1 , v vcc will gradually increase until it reaches the internal power-on reset (por) rising threshold. then the system enters t 2 . time t 2 : during t 2 time, the device initialization occurs. the time duration for t 2 is typically from 60s to 100s. time t 3 : after the self-calibration finishes, the internal pwm detection signal will be asserted and the system enters the t 3 period. during t 3 , the ISL78225 will detect the voltage on each pwm pin to determine the active phase number. if pwm1 or pwm2 is accidentally pulled to vcc, the chip will be latched off and wait for power recycling. the time duration for t 3 is fixed to around 30s. time t 4 : when the internal pwm detection signal is released, the system enters t 4 period. during t 4 period, the ISL78225 will wait until the internal pll circuits are locked to the pre-set oscillator frequency. when pll locking is achieved, the oscillator will generate output at the clk_out pin. the time duration for t 4 is typically around 0.5ms, depending on the pll_comp pin configuration. time t 5 : after the pll locks the frequency, the system enters the t 5 period. during t 5 , the pwm outputs are held in a high-impedance state (if v pwm_tri = 1) or logic low (if v pwm_tri = 0), and the v drive_en is logic low to assure the external drivers remain off. the ISL78225 has one unique feature to pre- bias the v ss based on v fb information during this time. the duration time for t 5 is around 50s. after t 5 , the soft-start process will begin. the following section will discuss the soft-start pr ocess in detail for different applications. table 1. operation mode for different applications case mode pwm _tri external driver identify 2.5v tri-level signal? applications a 1 1 yes synchronous boost for audio amplifier power supply. no phase dropping. b analog 1 yes applications that need improving light load efficiency (automatic phase dropping + cycle-by-cycle diode emulation + pulse skipping). c 1 0 no applications that the external driver cannot identify tri-level signal; no phase dropping. d analog 0 no applications that the external driver cannot identify tri-level signal, with improved light load efficiency (e.g., 6-phase non synchronous boost with phase dropping). figure 14. circuit initialization before soft-start en 0 circuit initialization before soft- start 0 0 0 t t t t por vcc pwm_detection pwm t2 t3 t4 t1 t5 then soft- start begins
ISL78225 14 fn7909.0 december 15, 2011 soft-start process for different modes (refer to table 1) case a (v mode = vcc, v pwm_tri = vcc) figure 15 shows the pre-bias start-up pwm waveform for case a in table 1. the v pwm_tri = vcc so the pwm can output a tri-level signal, which the external drivers need to identify, and v mode = vcc to ban the automatic phase dropping function. time t 4 , t 5 : same as the t 4 , t 5 in figure 14, soft-start has not started yet. see ?operation initialization before soft-start? on page 13 for a detailed description. time t 6 : at the beginning of t 6 , the ss pin has already been pre-biased to a value very close to the v fb , so that the internal reference signal will start from the voltage close to the fb pin. this scheme will eliminate the internal delay for a non pre-biased application. the drive_en pin, which is connected to the enable pins of the external drivers, will be pulled high when first pwm toggles at the beginning of t 6; as a result external drivers will start working. the pwm signals will switch between tri-level and low. the driver will only turn on the lower mosfet accordingly, and the duty cycle will increase gradually from 0 to steady state. the synchronous mosfet (upper fet for boost converter) will never turn on during this time, so diode emulation can be achieved during the start-up and in turn prevent negative current flowing from output to input. time t 7 : soft-start finishes at the beginning of t 7 . the pwms will change to a 2-level 0v to 5v switching signal and the synchronous mosfet will be turned on. case b (v mode < 4v, v pwm_tri = vcc, light load condition) the only difference between case a and case b start-up waveforms is that at light load, case b can drop phases and have cycle-by-cycle diode emulation at pwm1 and pwm2. for case b applications, where good light load efficiency is always preferred, the isl782 25 provides three light load efficiency enhancement methods. when the load current reduces, the ISL78225 will first assert the automatic phase dropping function to reduce th e active phase number according to the load level. the minimum active phase number is two. if the load current further reduces ev en when running at two-phase operation, the ISL78225 will assert a second method by utilizing cycle-by-cycle diode emulation. during this time the ic will sense the inductor current, and when the current is approximately zero, it will turn off the synchronous mosfet. if the load current is further reduced to deep light load operation, pulse skipping function will kick in to optimize the overall efficiency. figure 15. soft-start waveform (case a) 2.5v v v 5v 0 0 0 2.5v 5v (pwm_inv = 0) 5v 0 (pwm_inv = 1) vfb vref t4 t6 t7 pwm soft-start waveform (case a) diode emulation drive_en t5 lower fet turn on diode emulation pwm note: t4, t5 period are from figure 5 synchronous operation synchronous operation
ISL78225 15 fn7909.0 december 15, 2011 case c (v pwm_tri = 0) for applications that the driver cann ot identify a tri-state pwm signal, the v pwm_tri should be connected to gnd (logic low), such that the pwm signal will only be 2 levels between 0v and 5v. then the drive_en pin can be connected to th e en pin of the external drivers. drive_en will be asserted when the pwm first toggles such that the pre-bias start-up capability can be achieved. detailed soft-start for case c is shown in figure 17. time t 4 , t 5 : same as the t 4 , t 5 in figure 14, soft-start has not started yet; see ?operation init ialization before soft-start? on page 13 for detailed description. time t 6 : at the beginning of t 6 , the pwm signal will start to switch between 0v and 5v. the driver will turn on the lower and upper mosfets accordingly, and the duty cycle for lower mosfet will increase gradually from 0 to steady state. drive_en will be pulled high when the first pwm toggles at the beginning of t 6 to enable the external drivers. soft-start ramp slew rate calculation the soft-start ramp slew rate sr ss is determined by the capacitor value c ss from ss pin to gnd. c ss can be calculated based on equation 3: figure 18 shows the relationship between c ss and sr ss . figure 16. soft-start wavefo rm (case b, light load) vfb vref t4 t6 t7 2.5v v v 5v 0 0 pwm soft-start waveform (case b, light load) diode emulation 0 drive_en t5 lower fet turn on diode emulation 2.5v 5v 5v 0 pwm note: t4, t5 period are from figure 5 (pwm_inv = 0) (pwm_inv = 1) synchronous operation with cycle-by-cycle diode emulation synchronous operation with cycle-by-cycle diode emulation figure 17. soft-start waveform (case c, light load) vfb vref t4 t6 v v 5v 0 0 soft-start waveform (case c) 0 drive_en t5 lower fet turn on 5v 5v 0 pwm (pwm_inv = 0) pwm (pwm_inv = 1) note: t4, t5 period are from figure 5 sr ss 5x10 12 ? c ss ----------------------- - v s ------ ?? ?? = (eq. 3) figure 18. soft-start capacitor vs slew rate 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 110100 c ss (nf) soft-start slew rate (v/ms)
ISL78225 16 fn7909.0 december 15, 2011 oscillator and synchronization the switching frequency is determ ined by the selection of the frequency-setting resistor, r fs , connected from the fs pin to gnd. equation 4 is provided to assist in selecting the correct resistor value. where f sw is the switching frequency of each phase. figure 19 shows the relationship between r fs and switching frequency. the maximum frequency at each pwm output is 1mhz. if the fs pin is accidentally shorted to gnd or connected to a low impedance node, the internal circ uits will detect this fault condition and fold back the switching frequency to the 75khz minimal value. the ISL78225 contains a phase lock loop (pll) circuit and has frequency synchronization capabi lity by simply connecting the sync pin to an external square pulse waveform (typically 20% to 80% duty cycle). in normal operation, the external sync frequency needs to be at least 20% faster than the internal oscillator frequency setting. the ISL78225 will synchronize its switching frequency to the fundamental frequency of the input waveform. the frequency synchronization feature will synchronize the rising edge of the pwm1 clock signal with the rising edge of the external clock signal at the sync pin. the pll is compensated with a series resistor-capacitor (rc and cc) from the pll_comp pin to gnd and a capacitor (cp) from pll_comp to gnd. typical values are rc = 6.8k ? , cc = 6.8nf, cp = 1nf. the typical lock time is around 0.5ms. the clk_out pin provides a square pulse waveform at the switching frequency. the amplitude is 5v with approximately 40% positive duty cycle, and the rising edge is synchronized with the leading edge of pwm1. current sensing the ISL78225 senses the current co ntinuously for fast response. it supports both sense resistor and inductor dcr current sensing methods. the sensed current for each active channel will be used for loop control, phase current balance, individual channel overcurrent protection and total average current protection. the internal circuitry, (shown in figures 20 and 21), represents a single channel. this circuitry is repeated for each channel, but may not be active depending on the status of the pwm3 and pwm4 pin voltage. peak current mode control is implemented by feeding back the current output of the current sense amplifier (csa) to the regulator control loop. individual channel peak current limit is implemented by comparing the cs a output current with 160a. when the peak current limit co mparator is tripped, the pwm on-pulse is terminated and the ic is latched off. sense resistor current sensing a sense resistor can be placed in series with the power inductor. as shown in figure 20, the ISL78225 acquires the channel current information by sensing the voltage signal across the sense resistor. because the voltage on both the positive input and the negative input of the current sense amplifier (csa) are forced to be equal, the voltage across r set is equivalent to the voltage drop across the r sen resistor. the resulting current into the isenxp pin is proportional to the channel current, i l . equation 5 for i sen is derived where i l is the channel current: (eq. 4) r fs 4x10 10 1 f sw --------- - 5x10 8 ? ? ?? ?? = figure 19. r fs vs switching frequency 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 r fs (k ) fs (khz) i sen i l r sen r i se t ---------------- ? = (eq. 5) figure 20. sense resistor current sensing csa isen(n)p vin i sen i sen ISL78225 internal circuits isen(n)n vout sense resistor current sensing r sen r set l
ISL78225 17 fn7909.0 december 15, 2011 inductor dcr sensing an inductor?s winding is characteri stic of a distributed resistance as measured by the dcr (direct current resistance) parameter. consider the inductor dcr as a separate lumped quantity, as shown in figure 21. the channel current i l , flowing through the inductor, will also pass through the dcr. equation 6 shows the s-domain equivalent voltage across the inductor v l . a simple r-c network across the inductor extracts the dcr voltage, as shown in figure 21. the voltage on the capacitor v c , can be shown to be proportional to the channel current i l , see equation 7. if the r-c network components ar e selected such that the rc time constant (= r*c) matche s the inductor time constant (= l/dcr), the voltage across the capacitor v c is equal to the voltage drop across the dcr, i.e ., proportional to the channel current. with the internal low-offset differential current sense amplifier, the capacitor voltage v c is replicated across the sense resistor r set . therefore, the current flow into the isenxp pin is proportional to the inductor current. equation 8 shows that the ratio of the channel current to the sensed current i sen is driven by the value of the sense resistor and the dcr of the inductor. light load efficiency enhancement schemes for switching mode power supplies, the total loss is related to both the conduction loss and the switching loss. at heavy load, the conduction loss is dominant while the switching loss will take charge at light load condition. so, if a multiphase converter is running at a fixed phase number for the entire load range, we will observe that below a certain load point, the total efficiency starts to drop heavily. the ISL78225 has automatic phase dropping, cycle-by-cycle diode emulation and pulse skipping features to enhance the light load efficiency. by observing the total input current on-the-fly and dropping the active phase numbers accordingly, the overall system can achieve optimized efficiency over the entire load range. all th e previously mentioned light load enhancement features can be disabled by simply pulling the mode pin to vcc. adjustable automatic phase dropping/adding at li ght load condition if the mode pin is connected to a resistor to gnd, and the voltage on the mode pin is lower than its disable threshold 4v, the adjustable automatic phase dr opping/adding mode will be enabled. when the ISL78225 controller works in this mode, it will automatically adjust the ac tive phase number by comparing the v mode and v iout , which represents sensed total current information. the v mode sets the overall phase dropping threshold, and the v iout is proportional to the input current, which is in turn proportional to the load current. the smaller the load current, the lower the voltage observed on the iout pin, and the ISL78225 will drop phases in operation. once the mode pin voltage is fixed, the threshold to determine how many phases are in operation is dependent on two factors: 1. the maximum configured phase number. 2. the voltage on the iout pin (v iout ). for example, if the converter is working in 4-phase operation and the mode pin is set to 1.2v, the converter will monitor the v iout and compared to 1.2v; if less than 900mv (75% of 1.2v), it will drop to 3-phase; if less than 600mv (50% of 1.2v), it will drop to 2-phase. the detailed threshold setting is shown in the ?electrical specifications? table on page 7. if pwm_tri is tied to vcc, the dropped phase will provide a 2.5v tri-level signal at its pwm output. the external driver has to identify this tri-state signal and turn off both the lower and upper switches accordingly. for better transient response during phase dropping, the ISL78225 will gradua lly reduce the duty cycle of the phase from steady state to zero, typically within 15 switching cycles. this gradual dropping scheme will help smooth the change of the pwm signal and, in turn, will help to stabilize the system when phase dropping happens. the ISL78225 also has an automatic phase adding feature similar to phase dropping, but when doing phase adding there will not be 15 switching cycles gradually adding. it will add phases instantly to take care of the increased load condition. the phase adding scheme is controlled by three factors. 1. the maximum configured phase number 2. the voltage on the iout pin (v iout ). 3. individual phase current factors 1 and 2 are similar to the phase dropping scheme. if the v iout is higher than the phase dropping threshold plus the hysteresis voltage, the dropped phase will be added back one by one instantly. the previously mentioned phase-adding method can take care of the condition that the load current increases slowly. however, if the load is increasing quickly, the ic will use a different phase adding scheme. the ISL78225 moni tors the individual channel current for all active phases. du ring phase adding, the system figure 21. inductor dcr current sensing csa isen(n)p vin i sen ISL78225 internal circuits isen(n)n vout inductor dcr current sensing dcr l c r r set il isen v l i l sl dcr + ? () ? = (eq. 6) v c s l dcr ----------- - ? 1 + ?? ?? dcr i l ? () ? src 1 + ? () ----------------------------------------------------------------- = (eq. 7) i sen i l dcr r set ------------ - ? = (eq. 8)
ISL78225 18 fn7909.0 december 15, 2011 will bring down the pre-set channel current limit to 2/3 of its original value (160a). if any of the phase?s sensed current hit the 2/3 of pre-set chan nel current limit threshold (i.e., 106.7a), all the phases will be added back instantly. after a fixed 1.5ms delay, the phase dropping circuit will be activated and the system will react to drop the phase number to the correct value. during phase adding, when either phase hits the pre-set channel current limit, there will be 200s blanking time such that per-channel ocp will not be trigge red during this blanking time. diode emulation at very light load condition when phase dropping is asserted and the minimum phase operation is 2 phases, if the load is still reducing and synchronous boost structure is used, the ISL78225 controller will enter into forced cycle-by-cycle diode emulation mode. the pwm output will be tri-stated when the inductor current falls to zero, such that the synchronous mosfet can be turned off accordingly cycle-by-cycle for forced diode emulation. this cycle-by-cycle diode emulation scheme will only be asserted when two conditions are met: 1. the pwm_tri pin voltage is logic high. 2. only two phases are running either by phase dropping or initial configuration. by utilizing the cycle-by-cycle di ode emulation scheme in this way, negative current is prevented and the system can still optimize the efficiency even at very light load conditions. pulse skipping at deep light load condition if the converter enters diode emulation mode and the load is still reducing, eventually pulse skipping will occur to increase the deep light load efficiency. adjustable slope compensation for a boost converter working in current mode control, slope compensation is needed when steady state duty cycle is larger than 50%. when slope compensation is too low, the converter can suffer from jitter or osci llation. on the other hand, over compensation of the slope will cause the reduction of the phase margin. therefore, proper design of the slope compensation is needed. the ISL78225 features adjustab le slope compensation by setting the resistor value r slope from the slope pin to gnd. this function will ease the compensation design and provide more flexibility in choosing the external components. for current mode control, typically we need the compensation slope m a to be 50% of the inductor current down ramp slope m b when the lower mosfet is off. equation 9 shows how to choose the suitable resistor value. fault monitoring and protection the ISL78225 actively monitors inpu t/output voltage and current to detect fault conditions. fault moni tors trigger protective measures to prevent damage to the load. common power-good indicator pin (pgood pin) and vin_ovb, vout_ovb pins are provided for linking to external system monitors. pgood signal the pgood pin is an open-drain lo gic output to indicate that the soft-start period is completed and the output voltage is within the specified range. this pin is pulled low during soft-start and releases high after a successful soft-start. pgood will be pulled low when a uv/ov/oc/ot fault occurs. input overvoltage detection the ISL78225 utilizes vin_sen and vin_ovb pins to deal with a high input voltage. the vin_sen pin is used for sensing the input voltage. a resistor divider network is connected between this pin and the boost power stage input voltage rail. when the voltage on vin_sen is higher than 2.4v , the open drain output vin_ovb pin will be pulled low to indicate an input overvoltage condition, the v in overvoltage sensing threshold can be programmed by changing the resistor values, and hysteresis voltage of the internal comparator is fixed to be 100mv. output undervoltage detection the undervoltage threshold is set at 80% of the internal voltage reference. when the output voltage at the fb pin is below the undervoltage threshold minus the hysteresis, pgood is pulled low. when the output voltage comes back to 80% of the reference voltage, pgood will return back to high. output overvoltage detection/protection the ISL78225 overvoltage detection circuit is active after time t 2 in figure 14 on page 13. the ov trip point is set to 120% of the internal reference level. once an overvoltage condition is detected, the pgood will be pulled low but the controller will continue to operate. the ISL78225 also provides the fl exibility for output overvoltage protection by utilizing the vout_sen and vout_ovb pins. the vout_sen pin is used for sensing the output voltage. a resistor divider network is connected be tween this pin and the boost power stage output voltage rail. when the voltage on vout_sen is higher than 2.4v, the open drain output vout_ovb will be pulled low, and the ISL78225 ic will be latched off to indicate an output overvoltage condition. the v out overvoltage sensing threshold can be programmed by changing the resistor values. overcurrent protection ISL78225 has two levels of overcu rrent protection. each phase is protected from an overcurrent co ndition by limiting its peak current, and the combined total current is protected on an average basis. for the individual channel overcurrent protection, the ISL78225 continuously compares the csa ou tput current of each channel with a 160a reference current. if any channel?s current trips the current limit comparator, th e ISL78225 will be shut down. however, during the phase adding period, the individual channel current protection function will be blanked for 200s, in order to give other phases the chance to take care of the current. the iout pin serves for both in put current monitoring and total average current ocp functions. the csa output current for each r slope 1.136x10 6 xlxr set v out v in ? () r sen () ---------------------------------------------------- () = (eq. 9)
ISL78225 19 fn7909.0 december 15, 2011 channel is scaled and summed to gether at this pin. an rc network should be connected between the iout pin and gnd, such that the ripple current si gnal can be filtered out and converted to a voltage signal to represent the averaged total input current. the relationship between total input current i in and v iout can be calculated as equation 10 (see figure 20 on page 16 for r sen and r set positions): when the v iout is higher than 2v for a consecutive 100s, the ISL78225 ic will be triggered to shut down. this provides additional safety for the voltage regulator. equation 11 can be used to calculate the value of the resistor r iout based on the desired ocp level i avg, ocp2 . the total average overcurrent protection scheme will not be asserted until the soft-start pin voltage v ss reaches its clamped value (approximately 3.5v). during the soft-start time, the system does not latch-off if per-channel or overall oc limit is reached. instead, the individual channel current will run at its pre-set peak current limit level. thermal protection the ISL78225 will be disabled if the die junction temperature reaches a nominal of +160c. it will recover when the junction temperature falls below a +15c hysteresis. the +15c hysteresis insures that the device will not be re-enabled until the junction temperature has dropped to below about +145c. internal 5v ldo output current limit derating curves ISL78225 contains an internal 5v/200ma ldo, and the input of ldo (vin pin) can go as high as 40v. based on the junction to ambient thermal resistance r ja of the package, we need to guarantee that the maximum junction temperature should be below +125c t max . figure 22 shows the relationship between maximum allowed ldo output curren t and input voltage. the curve is based on +35c/w thermal resistance r ja for the package. each curve represents different ambient temperature, t a . dedicated vref2 pin for input voltage tracking a second reference input pin, vref2, is added to the input of the transconductance amplifier. the ISL78225 internal reference will automatically change to vref2 when it is pulled below 1.8v. the vref2 pin can be connected to vi n through resistor network to implement the automatic input voltage tracking function. this function is very useful under car battery voltage cranking conditions (such as when the car is parked and the driver is listening to the stereo), where the full load power is typically not needed. in this case, the isl7822 5 can limit the output power by allowing the output voltage to trac k the input voltage. if vref2 is not used, the pin should be connected to vcc. configurations for dual ic operations for high power applications, two ISL78225 ics can be easily configured to support 8-phase oper ation. the ic that provides the clk_out signal is called master ic , and the ic that received the clk_out signal is called slave ic. note that the two pwm1 signals are synchronized and the net effect is 4-phase operation with double the output current. figure 1 shows the step-by-step setup as follows: v iout 0.75i in r sen r set ------------- - r iout = (eq. 10) r iout 2 i avg ocp2 , --------------------------- - = (eq. 11) figure 22. i ldo(max) vs v in 0 20 40 60 80 100 120 140 160 180 200 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 i l d o( m a x ) ( m a ) v in (v) t a = +25c t a = +50c t a = +75c t a = +100c master ic slave ic clk_out sync comp fb ss comp fb ss drive_en drive_en system drive_en figure 1. configurations for dual ic operation
ISL78225 20 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7909.0 december 15, 2011 for additional products, see www.intersil.com/product_tree 1. connect the clk_out pin of the master ic to the sync pin of the slave ic. 2. set the master ic?s switching frequency as desired frequency; set the slave ic?s switching frequency 20% below the master ic?s. 3. connect both ic?s comp, ss and fb pins together. 4. both ic?s drive_en pin should be anded together to provide the system?s driver enable signal. 5. since pgood, vout_ovb and vin_ovb pins are open drain structure, both ic?s pgood, vout_ovb and vin_ovb pins can be tied together and use one pull-up resistor to connect to vcc. 6. if phase dropping function is needed, tie both ic?s iout and mode pins together. products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: ISL78225 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change december 15, 2011 fn7909.0 initial release.
ISL78225 21 fn7909.0 december 15, 2011 package outline drawing q44.10x10a 44 lead thin plastic quad flatpack package with exposed pad (ep-tqfp) rev 2, 12/10 notes: bottom view detail "a" side view typical recommended land pattern top view ms-026, variation acb. 8. controlling dimension: millimeter. this outline conforms to je dec publication 95 registration be located on the lower radius or the foot. b dimension at maximum material condition. dambar cannot dambar protrusion shall be 0.08mm total in excess of the dimension b does not include dambar protrusion. allowable 6. package top dimensions are smaller than bottom dimensions and top of package will not overhang bottom of package. 1. all dimensioning and tolerancing conform to ansi y14.5-1982. 2. datum plane h located at mold parting line and coincident with lead, where lead exits plastic body at bottom of parting line. 3. datums a-b and d to be determined at centerline between leads where leads exit plastic body at datum plane h. 4. dimensions d1 and e1 do not include mold protrusion. allowable mold protrusion is 0.254mm on d1 and e1 dimensions. 9. 7. 5. these dimensions to be determined at datum plane h. 10. dimensions in ( ) are for reference only. scale: none 0.20 min. (1.00) 0.09/0.20 0.35 0.05 base metal 0.09/0.16 7 0.37 +0.08/-0.07 0.05 11/13 with lead finish 0.20 c ma-b d 0.05/0.15 r. min. 0.08 see detail "a" c 0.10 1.20 max / / 0.10 c 1.00 0.05 h gauge 0.60 0.15 0-7 0.25 0 min. 4x 0.80 c a-b d 0.20 3 a 0.20 4x 3 a-b h d 5 b 4 d 3 12.00 10.00 4 5 exposed pad 4.500.1 12.00 10.00 2 (10.00) (4.50) (0.45) typ (4.50) (1.50) typ 4.500.1 10.00 plane 11. the corners of the exposed heatspreader may appear different due to the presence of the tiebars.

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