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general description the max1530/max1531 multiple-output power-supply controllers generate all the supply rails for thin-film tran- sistor (tft) liquid-crystal display (lcd) monitors. both devices include a high-efficiency, fixed-frequency, step-down regulator. the low-cost, all n-channel, syn- chronous topology enables operation with efficiency as high as 93%. high-frequency operation allows the use of small inductors and capacitors, resulting in a com- pact solution. the max1530 includes three linear regu- lator controllers and the max1531 includes five linear regulator controllers for supplying logic and lcd bias voltages. a programmable startup sequence enables easy control of the regulators. the max1530/max1531 include soft-start functions to limit inrush current during startup. an internal step- down converter current-limit function and a versatile overcurrent shutdown protect the power supplies against fault conditions. the max1530/max1531 use a current- mode control architecture, providing fast load transient response and easy compensation. an internal linear regulator provides mosfet gate drive and can be used to power small external loads. the max1530/max1531 can operate from inputs as high as 28v and are well suited for lcd monitor and tv applications running directly from ac/dc wall adapters. both devices are available in a small (5mm x 5mm), ultra-thin (0.8mm), 32-pin qfn package and operate over the -40? to +85? temperature range. applications lcd monitors and tvs automotive lcds features 4.5v to 28v input voltage range 250khz/500khz current-mode step-down converter small inductor/capacitors no sense resistor three positive linear regulator controllers one positive and one negative additional controller (max1531) small input and output capacitors timed reset output uncommitted overcurrent protection (max1531) soft-start for all regulators programmable input undervoltage comparator programmable startup sequencing max1530/max1531 multiple-output power-supply controllers for lcd monitors ________________________________________________________________ maxim integrated products 1 ordering information reset v in v gon 25v v goff -9v v in = 12v onl2 v source 10v/500ma v gamma 9.7v v n onl5 onl4 onl3 seq vl rstin v out 3.3v/1.5a v logic 2.5v/500ma v out v l v l v p v n v in v in v p v l drv3 fbl3 fbl1 drv1 bst in dh lx dl pgnd fb comp fbl2 drv2 fbl5 drv5 drv4 fbl4 csh csl freq ilim vl en agnd max1530 minimal operating circuit 19-2866; rev 0; 5/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configuration appears at end of data sheet. part temp range pin-package max1530 etj -40 c to +85 c 32 thin qfn max1531 etj -40 c to +85 c 32 thin qfn
max1530/max1531 multiple-output power-supply controllers for lcd monitors 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (circuit of figure 1, v in = 12v, v en = v seq = 5v, t a = 0 c to +85 c , unless otherwise noted. typical values are at t a = +25 c.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in, drv1, drv2, drv3, drv4, csh, csl to agnd .....................................................-0.3v to +30v drv5 to vl .............................................................-28v to +0.3v csh to csl ..............................................................-0.3v to +6v vl to agnd ..............................................................-0.3v to +6v pgnd to agnd................................................................... 0.3v lx to bst..................................................................-6v to +0.3v bst to agnd..........................................................-0.3v to +36v dh to lx .....................................................-0.3v to (bst + 0.3v) dl to pgnd ..................................................-0.3v to (vl + 0.3v) seq, onl2, onl3, onl4, onl5, comp, ilim to agnd............................................-0.3v to (vl + 0.3v) rstin, reset, en, fb, fbl1, fbl2, fbl3, fbl4, fbl5, freq to agnd.....................................................-0.3v to +6v vl short circuit to agnd ...........................................momentary continuous power dissipation (t a = +70 c) 32-pin thin qfn (derate 21.3mw/ c above +70 c) ...1702mw operating temperature range ...........................-40 c to +85 c storage temperature range .............................-65 c to +150 c junction temperature ......................................................+150 c lead temperature (soldering, 10s) .................................+300 c parameter conditions min typ max units general operating input voltage range (note 1) 4.5 28.0 v quiescent supply current v fb = v fbl1 = v fbl2 = v fbl3 = v fbl4 = 1.5v, v fbl5 = 0 1.7 3.0 ma ic disable supply current en = agnd 200 400 a vl regulator vl output voltage 5.5v < v in < 28v, 0 < i vl < 30ma 4.75 5 5.25 v vl undervoltage lockout threshold vl rising, 3% hysteresis 3.2 3.5 3.8 v control and sequence seq, freq input logic high level 2.0 v seq, freq input logic low level 0.6 v seq, freq input leakage current -1 +1 a onl_ input threshold onl_ rising, 25mv hysteresis 1.201 1.238 1.275 v onl_ source current seq = en = vl, v onl _ = 0 to 1.24v 1.8 2.0 2.2 a onl_ input leakage current seq = en = vl, onl_ = vl -500 +500 na onl_ input discharge clamp resistance seq = 0 800 1500 3000 ? en input threshold en rising, 5% hysteresis 1.201 1.238 1.275 v en input leakage current -50 +50 na fault detection fb, fbl1, fbl2, fbl3, fbl4 undervoltage fault trip level fb, fbl1, fbl2, fbl3, fbl4 falling, 25mv hysteresis 1.081 1.114 1.147 v fbl5 undervoltage fault trip level fbl5 rising, 25mv hysteresis 300 400 500 mv
max1530/max1531 multiple-output power-supply controllers for lcd monitors _______________________________________________________________________________________ 3 electrical characteristics (continued) (circuit of figure 1, v in = 12v, v en = v seq = 5v, t a = 0 c to +85 c , unless otherwise noted. typical values are at t a = +25 c.) parameter conditions min typ max units comparator bandwidth for en, fb, fbl_ 10 khz duration to trigger fault latch for fb, fbl_ 51 64 77 ms overcurrent protection threshold (v csh - v csl ) 270 300 330 mv overcurrent sense common- mode range v csh , v csl 2.7 28.0 v csh input current v csh = 2.7v to 28v 100 a csl input current v csl = v csh = 12v -50 +50 na overcurrent sense filter rc time constant 50 s thermal protection thermal shutdown temperature rising, 15 c hysteresis 160 c reset function rstin reset trip level rstin falling, 25mv hysteresis 1.081 1.114 1.147 v rstin input leakage current v rstin = 1.5v -50 +50 na comparator bandwidth 10 khz reset timeout period 102 128 154 ms reset output low level i reset = -1ma 0.4 v reset output high leakage v reset = 5v 1 a step-down controller error amplifier fb regulation voltage 1.223 1.238 1.253 v transconductance fb to comp 70 100 140 s voltage gain fb to comp 200 v/v minimum duty cycle 15 % fb input leakage current v fb = 1.5v -50 +50 na fb input common-mode range (note 2) -0.1 +1.5 v comp output minimum voltage v fb = 1.5v 1 v comp output maximum voltage v fb = 1.175v 3 v current-sense amplifier voltage gain v in - v lx 2.75 3.5 4.0 v/v current-limit threshold (default mode) pgnd - lx, ilim = vl 190 250 310 mv current-limit threshold (adjustable mode) pgnd - lx, v ilim = 1.25v 190 250 310 mv ilim inp ut d ual m od e thr eshol d 3.0 3.5 4.00 v oscillator freq = agnd 200 250 300 switching frequency freq = vl 425 500 575 khz freq = agnd 75 80 88 maximum duty cycle freq = vl 75 80 88 % dual mode is a trademark of maxim integrated products, inc.
max1530/max1531 multiple-output power-supply controllers for lcd monitors 4 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v in = 12v, v en = v seq = 5v, t a = 0 c to +85 c , unless otherwise noted. typical values are at t a = +25 c.) parameter conditions min typ max units soft-start step size measured at fb 1.238 / 32 v freq = gnd 1024 / f osc period freq = vl 2048 / f osc s fet drivers dh, dl on-resistance 3 10 ? dh, dl output drive current sourcing or sinking, v dh or v dl = v vl / 2 0.5 a lx, bst leakage current v bst = v lx = v in = 28v 20 a linear regulator controllers positive linear regulator (lr1) fbl1 regulation voltage v drv1 = 5v, i drv1 = 100a 1.226 1.245 1.264 v fbl1 input bias current v fbl1 = 1.5v -50 +50 na fbl1 effective load regulation error (transconductance) v drv1 = 5v, i drv1 = 100a to 2ma -1.5 -2 % fbl1 line regulation error i drv1 = 100a, 5.5v < v in < 28v 5 mv drv1 sink current v fbl1 = 1.175v, v drv1 = 5v 3 10 ma drv1 off-leakage current v fbl1 = 1.5v, v drv1 = 28v 0.1 10 a fbl1 input common-mode range (note 2) -0.1 +1.5 v soft-start step size measured at fbl1 1.238 / 32 v freq = gnd 1024 / f osc soft-start period freq = vl 2048 / f osc s positive linear regulators (lr2 and lr3) fbl_ regulation voltage v drv _ = 5v, i drv _ = 100a 1.226 1.245 1.264 v fbl_ input bias current v fbl _ = 1.5v -50 +50 na fbl_ effective load regulation error (transconductance) v drv _ = 5v, i drv _ = 50a to 1ma -1.5 -2 % fbl_ line regulation error i drv _ = 100a, 5.5v < v in < 28v 5 mv drv_ sink current v fbl_ = 1.175v, v drv_ = 5v 2 4 ma drv_ off-leakage current v fbl _ = 1.5v, v drv _ = 28v 0.1 10 a fbl_ input common-mode range (note 2) -0.1 +1.5 v soft-start step size measured at fbl_ 1.238 / 32 v
max1530/max1531 multiple-output power-supply controllers for lcd monitors _______________________________________________________________________________________ 5 electrical characteristics (continued) (circuit of figure 1, v in = 12v, v en = v seq = 5v, t a = 0 c to +85 c , unless otherwise noted. typical values are at t a = +25 c.) parameter conditions min typ max units freq = gnd 1024 / f osc soft-start period freq = vl 2048 / f osc s positive linear regulator (lr4) fbl4 regulation voltage v drv4 = 5v, i drv4 = 500a 1.226 1.245 1.264 v fbl4 input bias current v fbl4 = 1.5v -50 +50 na fbl4 effective load regulation error (transconductance) v drv4 = 5v, i drv4 = 500a to 10ma -1.5 -2 % fbl4 line regulation error i drv4 = 500a, 5.5v < v in < 28v 5 mv drv4 sink current v fbl4 = 1.175v, v drv4 = 5v 10 28 ma drv4_off-leakage current v fbl4 = 1.5v, v drv4 = 28v 0.1 10 a fbl4 input common-mode range (note 2) -0.1 +1.5 v soft-start step size measured at fbl4 1.238 / 32 v freq = gnd 1024 / f osc soft-start period freq = vl 2048 / f osc s negative linear regulator (lr5) fbl5 regulation voltage v drv5 = -10v, i drv5 = 100a 100 125 150 mv fbl5 input bias current v fbl5 = 0 -50 +50 na fbl5 effective load regulation error (transconductance) v drv5 = -10v, i drv5 = 50a to 1ma -1.5 -2 % fbl5 line regulation error i drv5 = 100a, 5.5v < v in < 28v 5 mv drv5 source current v fbl5 = 200mv, v drv5 = -10v 2 9 ma drv5 off-leakage current v fbl5 = 0, v drv5 = -20v 0.1 10 a fbl5 input common-mode range (note 2) -0.1 +1.5 v soft-start step size measured at fbl5 1.238 / 32 v freq = agnd 1024 / f osc soft-start period freq = vl 2048 / f osc s electrical characteristics (circuit of figure 1, v in = 12v, v en = v seq = 5v, t a = -40? to +85? , unless otherwise noted.) (note 3) parameter conditions min typ max units general operating input voltage range (note 1) 4.5 28.0 v vl regulator vl output voltage 5.5v < v in < 28v, 0 < i vl < 30ma 4.75 5.25 v vl undervoltage lockout threshold vl rising, 3% hysteresis 3.2 3.8 v
max1530/max1531 multiple-output power-supply controllers for lcd monitors 6 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v in = 12v, v en = v seq = 5v, t a = -40 c to +85 c , unless otherwise noted.) (note 3) parameter conditions min typ max units control and sequence onl_ input threshold onl_ rising, 25mv hysteresis 1.201 1.275 v en input threshold en rising, 5% hysteresis 1.201 1.275 v fault detection fb, fbl1, fbl2, fbl3, fbl4 fault trip level fb, fbl1, fbl2, fbl3, fbl4 falling, 25mv hysteresis 1.081 1.147 v fbl5 fault trip level fbl5 rising, 25mv hysteresis 300 500 mv overcurrent protection threshold (v csh - v csl ) 270 330 mv reset function rstin reset trip level rstin falling, 25mv hysteresis 1.081 1.147 v step-down controller error amplifier fb regulation voltage 1.215 1.260 v current-limit threshold (default mode) pgnd - lx, ilim = vl 170 330 mv current-limit threshold (adjustable mode) pgnd - lx, v ilim = 1.25v 170 330 mv linear regulator controllers positive linear regulator (lr1) fbl1 regulation voltage v drv1 = 5v, i drv1 = 100a 1.220 1.270 v fbl1 input bias current v fbl1 = 1.5v -50 +50 na positive linear regulators (lr2 and lr3) fbl_ regulation voltage v drv _ = 5v, i drv _ = 100a 1.220 1.270 v fbl_ input bias current v fbl _ = 1.5v -50 +50 na positive linear regulator (lr4) fbl4 regulation voltage v drv4 = 5v, i drv4 = 500a 1.220 1.270 v fbl4 input bias current v fbl4 = 1.5v -50 +50 na negative linear regulator (lr5) fbl5 regulation voltage v drv5 = -10v, i drv5 = 100a 100 150 mv fbl5 input bias current v fbl5 = 0 -50 +50 na drv5 source current v fbl5 = 200mv, v drv5 = -10v 2 ma note 1: operating supply range is guaranteed by vl line regulation test for the range of 5.5v to 28v. between 4.5v and 5.5v, the v l regulator might be in dropout; however, the part continues to operate properly. note 2: guaranteed by design and not production tested. note 3: specifications to -40 c are guaranteed by design and not production tested.
max1530/max1531 multiple-output power-supply controllers for lcd monitors _______________________________________________________________________________________ 7 typical operating characteristics (circuit of figure 1; including r5, r6, and d2; t a = +25 c, unless otherwise noted.) step-down efficiency vs. load current max1530 toc01 load current (ma) efficiency (%) 1200 900 600 300 60 70 80 90 100 50 0 1500 v in = 12v v in = 20v f sw = 500khz step-down load regulation max1530 toc02 load current (ma) output-voltage error (%) 1200 900 600 300 -0.12 -0.08 -0.04 0 -0.16 0 1500 switching frequency vs. load current frequency (khz) 485 490 495 500 510 505 515 520 480 max1530 toc03 load current (ma) 1200 900 600 300 0 1500 step-down regulator load transient max1530 toc04 40 s/div a: load current, 1a/div b: output voltage, 200mv/div, ac-coupled c: inductor current, 1a/div a 0a b 3.3v 0a c step-down regulator switching waveform max1530 toc05 2 s/div a b c a: lx, 10v/div b: output voltage, 20 mv/div, ac-coupled c: inductor current, 1a/div 0v 3.3v 0a step-down regulator soft-start max1530 toc06 1ms/div a c a: en, 2v/div b: output voltage, 2v/div c: inductor current, 1a/div 0v 0v b 0a vl load regulation max1530 toc07 load current (ma) vl output error (%) 25 20 15 10 5 -0.4 -0.3 -0.2 -0.1 0 -0.5 030 startup sequence max1530 toc08 4ms/div a: v l , 10v/div b: v out , 5v/div c: v logic , 5v/div d: v source , 20v/div e: v gamma , 20v/div f: v goff , 20v/div g: v gon , 40v/div a b c d e f g lr1 base current vs. drv1 voltage max1530 toc09 drv1 voltage (v) base current (ma) 8 6 4 2 3 6 9 12 15 0 010 v fbl1 = 1.175v
max1530/max1531 multiple-output power-supply controllers for lcd monitors 8 _______________________________________________________________________________________ lr1 normalized load regulation max1530 toc10 load current (ma) voltage error (%) 400 300 200 100 -1.5 -1.0 -0.5 0 -2.0 0 500 lr1 normalized line regulation max1530 toc11 input voltage (v) output-voltage error (%) 5 4 3 -0.8 -0.6 -0.4 -0.2 0 0.2 -1.0 26 200ma load current lr1 load transient max1530 toc12 40 s/div a b a: lr1 output voltage, 100mv/div, ac-coupled b: lr1 load current, 500ma/div 2.5v 0ma lr2/lr3 base current vs. drv2/drv3 voltage max1530 toc13 drv2/drv3 voltage (v) base current (ma) 4 3 2 1 1 2 3 4 5 0 05 v fbl2 = v fbl3 = 1.175v lr2 normalized load regulation max1530 toc14 load current (ma) voltage error (%) 40 30 20 10 -1.2 -0.9 -0.6 -0.3 0 -1.5 050 lr2 normalized line regulation max1530 toc15 input voltage (v) output-voltage error (%) 21 17 13 -0.8 -0.6 -0.4 -0.2 0 0.2 -1.0 925 20ma load current lr3 normalized load regulation max1530 toc16 load current (ma) voltage error (%) 16 12 8 4 -1.5 -1.0 -0.5 0 -2.0 020 lr3 normalized line regulation max1530 toc17 input voltage (v) output-voltage error (%) 36 32 28 -0.8 -0.6 -0.4 -0.2 0 0.2 -1.0 24 40 20ma load current lr4 base current vs. drv voltage max1530 toc18 drv4 voltage (v) base current (ma) 8 6 4 2 5 10 15 20 25 30 0 010 v fbl4 = 1.175v typical operating characteristics (continued) (circuit of figure 1; including r5, r6, and d2; t a = +25 c, unless otherwise noted.)
max1530/max1531 multiple-output power-supply controllers for lcd monitors _______________________________________________________________________________________ 9 typical operating characteristics (continued) (circuit of figure 1; including r5, r6, and d2; t a = +25 c, unless otherwise noted.) lr4 normalized load regulation max1530 toc19 load current (ma) voltage error (%) 400 300 200 100 -0.5 -0.4 -0.3 -0.2 -0.1 0 -0.6 0 500 lr4 normalized line regulation max1530 toc20 input voltage (v) output-voltage error (%) 21 17 13 -0.8 -0.6 -0.4 -0.2 0 0.2 -1.0 925 200ma load current lr4 load transient max1530 toc21 40 s/div a b a: lr4 output voltage, 100mv/div, ac-coupled b: lr4 load current, 500ma/div 10v 0ma lr4 pulsed load transient max1530 toc22 10 s/div a b a: lr4 output voltage, 100mv/div, ac-coupled b: lr4 load current, 1a/div 10v 0a max1531 overcurrent protection (csh, csl) max1530 toc23 20 s/div a: v lx , 10v/div b: v out , 5v/div b c d a c: v reset , 5v/div d: v csh - v csl , 500mv/div lr5 base current vs. drv5 voltage max1530 toc24 drv5 voltage (v) base current (ma) 4 3 2 1 2 4 6 8 10 0 05 v fbl5 = 0v
max1530/max1531 multiple-output power-supply controllers for lcd monitors 10 ______________________________________________________________________________________ typical operating characteristics (continued) (circuit of figure 1; including r5, r6, and d2; t a = +25 c, unless otherwise noted.) pin description pin max1530 max1531 name function 1 1 drv2 gamma linear regulator (lr2) base drive. open drain of an internal n-channel mosfet. connect drv2 to the base of an external pnp pass transistor to form a positive linear regulator. (see the pass transistor selection section.) 2 2 fbl2 gamma linear regulator (lr2) feedback input. fbl2 regulates at 1.245v nominal. connect fbl2 to the center tap of a resistive voltage-divider between the lr2 output and agnd to set the output voltage. place the divider close to the fbl2 pin. 3 3 fbl3 gate-on linear regulator (lr3) feedback input. fbl3 regulates at 1.245v nominal. connect fbl3 to the center tap of a resistive voltage-divider between the lr3 output and agnd to set the output voltage. place the divider close to the fbl3 pin. 4 4 drv3 gate-on linear regulator (lr3) base drive. open drain of an internal n-channel mosfet. connect drv3 to the base of an external pnp pass transistor to form a positive linear regulator. (see the pass transistor selection section.) 5 10, 18, 19 n. c. no connection. not internally connected. 11 11 rstin adjustable reset input. reset asserts low when the monitored voltage is less than the reset trip threshold. reset goes to a high-impedance state only after the monitored voltage remains above the reset trip threshold for the duration of the reset timeout period. connect rstin to the center tap of a resistive voltage-divider between the monitored output voltage and agnd to set the reset trip threshold. the internal rstin threshold of 90% of 1.238v allows direct connection of rstin to any of the device s positive feedback pins. lr5 normalized load regulation max1530 toc25 load current (ma) voltage error (%) 40 30 20 10 -0.8 -0.6 -0.4 -0.2 0 -1.0 050 lr5 normalized line regulation max1530 toc26 input voltage (v) output-voltage error (%) -13 -17 -21 0 0.2 0.4 0.6 0.8 1.0 -0.2 -25 -9 20ma load current
max1530/max1531 multiple-output power-supply controllers for lcd monitors ______________________________________________________________________________________ 11 pin description (continued) pin max1530 max1531 name function 12 12 reset open-drain reset output. reset asserts low when the monitored voltage is less than the reset trip threshold. reset goes to a high-impedance state only after the monitored voltage remains above the reset trip threshold for the duration of the reset timeout period. reset also asserts low when vl is less than the vl undervoltage lockout threshold, en is low, or the thermal, overcurrent or undervoltage fault latches are set. 13 13 comp step-down regulator compensation input. a pole-zero pair must be added to compensate the control loop by connecting a series resistor and capacitor from comp to agnd. (see the compensation design section.) 14 14 fb step-down regulator feedback input. fb regulates at 1.238v nominal. connect fb to the center tap of a resistive voltage-divider between the step-down regulator output and agnd to set the output voltage. place the divider close to the fb pin. 15 15 ilim step-down regulator current-limit control input. connect this dual-mode input to vl to set the current-limit threshold to its default value of 250mv. the overcurrent comparator compares the voltage across the low-side n-channel mosfet with the current-limit threshold. connect ilim to the center tap of a resistive voltage-divider between vl and agnd to adjust the current-limit threshold to other values. in adjustable mode, the actual current-limit threshold is 1/5th of the voltage at ilim over a 0.25v to 3.0v range. the dual- mode threshold for switchover to the 250mv default value is approximately 3.5v. 16 16 onl2 gamma linear regulator (lr2) enable input. when en is above its enable threshold, vl is above its uvlo threshold, and onl2 is greater than the internal reference, lr2 is enabled. drive onl2 with a logic signal or, for automatic sequencing, connect a capacitor from onl2 to agnd. if seq is high, en is above its threshold, and vl is above its uvlo threshold, an internal 2a (typ) current source charges the capacitor. otherwise, an internal switch discharges the capacitor. connecting various capacitors to each onl_ pin allows the programming of the startup sequence. 17 17 onl3 gate-on linear regulator (lr3) enable input. when en is above its enable threshold, vl is above its uvlo threshold, and onl3 is greater than the internal reference, lr3 is enabled. drive onl3 with a logic signal or, for automatic sequencing, connect a capacitor from onl3 to agnd. if seq is high, en is above its threshold, and vl is above its uvlo threshold, an internal 2a (typ) current source charges the capacitor. otherwise, an internal switch discharges the capacitor. connecting various capacitors to each onl_ pin allows the programming of the startup sequence. 20 20 pgnd power ground 21 21 dl low-side gate driver output. dl drives the synchronous rectifier of the step-down regulator. dl swings from pgnd to vl. dl remains low until vl rises above the uvlo threshold. 22 22 lx step-down regulator current-sense input. the ic s current-sense amplifier inputs for current-mode control connect to in and lx. connect in and lx directly to the high-side n- channel mosfet drain and source, respectively. the low-side current-limit comparator inputs connect to lx and pgnd to sense voltage across a low-side n-channel mosfet.
max1530/max1531 multiple-output power-supply controllers for lcd monitors 12 ______________________________________________________________________________________ pin description (continued) pin max1530 max1531 name function 23 23 dh high-side gate driver output. dh drives the main switch of the step-down regulator. dh swings from lx to bst. 24 24 bst step-down regulator boostrap capacitor connection for high-side gate driver. connect a 0.1f ceramic capacitor from bst to lx. 25 25 seq sequence control input for lr2, lr3, lr4, and lr5. controls the current sources and switches that charge and discharge the capacitors connected to the onl_ pins. 26 26 freq oscillator frequency select input. connect freq to vl for 500khz operation. connect freq to agnd for 250khz operation. 27 27 in main input voltage (+4.5v to 28v). bypass in to agnd with a 1f ceramic capacitor close to the pins. in powers the vl linear regulator. connect in to the drain of the high- side mosfet (for current sense) through a 1 ? resistor. 28 28 vl internal 5v linear regulator output. connect a minimum 1f ceramic capacitor from vl to agnd. place the capacitor close to the pins. vl can supply up to 30ma for gate drive and external loads. vl remains active when en is low. 29 29 agnd analog ground 30 30 en enable input. this general-purpose on/off control input has an accurate 1.238v (typ) rising threshold with 5% hysteresis. this allows en to monitor an input voltage level or other analog parameter. if en is less than its threshold, then the main step-down and all linear regulators are turned off. vl and the internal reference remain active when en is low. the rising edge of en clears any latched faults except for a thermal fault, which is cleared only by cycling the input power. an internal filter with a 10s time constant prevents short glitches from accidentally clearing the fault latch. 31 31 fbl1 low-voltage logic linear regulator (lr1) feedback input. fbl1 regulates at 1.245v nominal. connect fbl1 to the center tap of a resistive voltage-divider between lr1 output agnd to set the output voltage. place the divider close to the fbl1 pin. lr1 starts automatically after the step-down converter soft-start ends. 32 32 drv1 low-voltage logic linear regulator (lr1) base drive. open drain of an internal n-channel mosfet. connect drv1 to the base of an external pnp pass transistor. (see the pass transistor selection section.) 5 csh overcurrent protection positive input. csh is also the supply input for the overcurrent sense block. csh and csl can be used to sense any current in the application circuit and to shut the device down in an overcurrent condition. this feature is typically used to protect the main input or the input to one of the linear regulators since they do not have their own current limits. insert an appropriate sense resistor in series with the protected input and connect csh and csl to its positive and negative terminals. the controller sets the fault latch when v csh - v csl exceeds the 300mv (typ) overcurrent threshold. an internal lowpass filter prevents large currents of short duration (less than 50s) or noise glitches from setting the latch. if the overcurrent protection is not used, connect csh and csl to vl. 6 csl overcurrent protection negative input. see csh above.
max1530/max1531 multiple-output power-supply controllers for lcd monitors ______________________________________________________________________________________ 13 pin description (continued) pin max1530 max1531 name function 7 fbl4 source drive linear regulator (lr4) feedback input. fbl4 regulates at 1.245v nominal. connect fbl4 to the center tap of a resistive voltage-divider between the lr4 output and agnd to set the output voltage. place the divider close to the fbl4 pin. 8 drv4 source drive linear regulator (lr4) base drive. open drain of an internal n-channel mosfet. connect drv4 to the base of an external pnp pass transistor to form a positive linear regulator. (see the pass transistor selection section.) 9 fbl5 gate-off linear regulator (lr5) feedback input. fbl5 regulates at 125mv nominal. connect fbl5 to the center tap of a resistive voltage-divider between the lr5 output and the internal 5v linear regulator output (vl) to set the output voltage. place the divider close to the fbl5 pin. 10 drv5 gate-off linear regulator (lr5) base drive. open drain of an internal p-channel mosfet. connect drv5 to the base of an external npn pass transistor to form a negative linear voltage regulator. (see the pass transistor selection section.) 18 onl4 source drive linear regulator (lr4) enable input. when en is above its enable threshold, vl is above its uvlo threshold, and onl4 is greater than the internal reference, lr4 is enabled. drive onl4 with a logic signal or, for automatic sequencing, connect a capacitor from onl4 to agnd. if seq is high, en is above its threshold, and vl is above its uvlo threshold, an internal 2a (typ) current source charges the capacitor. otherwise, an internal switch discharges the capacitor. connecting various capacitors to each onl_ pin allows the programming of the startup sequence. 19 onl5 gate-off linear regulator (lr5) enable input. when en is above its enable threshold, vl is above its uvlo threshold, and onl5 is greater than the internal reference, lr5 is enabled. drive onl5 with a logic signal or, for automatic sequencing, connect a capacitor from onl5 to agnd. if seq is high, en is above its threshold, and vl is above its uvlo threshold, an internal 2a (typ) current source charges the capacitor. otherwise, an internal switch discharges the capacitor. connecting various capacitors to each onl_ pin allows the programming of the startup sequence.
max1530/max1531 multiple-output power-supply controllers for lcd monitors 14 ______________________________________________________________________________________ max1531 n1-a n1-b v in = 12v vl onl2 onl3 onl4 onl5 freq seq reset en in bst dh lx dl pgnd drv1 fbl1 fb comp drv3 fbl3 ilim drv5 fbl5 fbl4 drv4 csh csl fbl2 drv2 rstin 30 28 26 25 12 16 17 18 19 1 2 6 5 8 7 9 10 15 4 3 13 14 11 31 32 20 21 22 23 27 24 29 agnd c3 4.7 f 25v r4 20.0k ? 1% d1 r5* 10 ? c1 1 f c5 0.1 f c4 1 f c10 470pf c9 10 f 6.3v c7 22 f 6.3v c23 150pf c22 2.2 f r11 100k ? r9 10k ? 1% r8 6.8k ? r10 10k ? 1% r14 121k ? 1% r15 68.1k ? 1% r16 43.2k ? 1% r17 6.8k ? r18 68.1k ? 1% r20 0.5 ? 1% r22 75k ? 1% r19 10k ? 1% r23 10.7k ? 1% c11 0.1 f c20 0.1 f c21 2.2 f c13 4.7 f 16v c12 0.47 f r29 48.7k ? 1% r28 90.9k ? 1% r25 200k ? 1% r26 10.5k ? 1% r27 6.8k ? c19 0.47 f * optional c16 0.47 f c15 0.1 f c8 0.1 f c6 0.1 f c14 0.1 f c18 0.1 f c17 0.1 f q5 q3 r24 6.8k ? r13 150k ? r12 300k ? r2 10.7k ? 1% r1 17.8k ? 1% l1 10 h r7 100k ? r3 124k ? 1% r12 1 ? r6* 10 ? d2* c2, open q6 q4 q2 q1 d3 d5 in vl vl v in v in v out 3.3v/1.5a lx lx v l 5v/30ma v logic 2.5v/500ma v goff -9v/50ma v gon 25v/20ma v gamma 9.7v/50ma v source 10v/500ma in v in d6 d4 r21 1.5k ? figure 1. max1531 standard application circuit
max1530/max1531 multiple-output power-supply controllers for lcd monitors ______________________________________________________________________________________ 15 max1530 n1-a n1-b v in = 12v vl onl2 onl3 n.c. n.c. n.c. n.c. freq seq reset en in bst dh lx dl pgnd drv1 fbl1 fb comp drv3 fbl3 ilim fbl2 drv2 rstin 30 28 26 25 12 16 17 5 6 7 8 n.c. n.c. n.c. n.c. 9 10 19 18 1 2 15 4 3 13 14 11 31 32 20 21 22 23 27 24 29 agnd c3 4.7 f 25v r4 20.0k ? 1% d1 c1 1 f c5 0.1 f c4 1 f c10 470pf c9 10 f 6.3v c7 22 f 6.3v c22 2.2 f r11 100k ? r9 10k ? 1% r8 6.8k ? r10 10k ? 1% r14 121k ? 1% r17 6.8k ? r18 68.1k ? 1% r19 10k ? 1% c11 0.1 f c20 0.1 f c12 0.47 f r22 75k ? 1% r23 10.7k ? 1% c13 4.7 f c21 2.2 f q4 r24 6.8k ? r13 150k ? r12 300k ? r2 10.7k ? 1% r1 17.8k ? 1% l1 10 h r7 100k ? r3 124k ? 1% r12 1 ? c2, open q2 q1 vl v in v out 3.3v/1.5a v l 5v/30ma v logic 2.5v/500ma v source 10v/500ma v gamma 9.7v/50ma in v in * optional r5* 10 ? r6* 10 ? d2* c23 150pf figure 2. max1530 standard application circuit
max1530/max1531 multiple-output power-supply controllers for lcd monitors 16 ______________________________________________________________________________________ standard application circuit the standard application circuit (figure 1) of the max1531 is a complete power-supply system for tft lcd monitors. the circuit generates a 3.3v/1.5a main output, a 2.5v/500ma output for the timing controller and digital sections of source/gate drive ics, a 10v/500ma source drive supply voltage, a 9.7v/50ma gamma reference, a 25v/20ma gate-on voltage, and a -10v/50ma gate-off voltage. the input voltage is 12v 10%. table 1 lists the selected components and table 2 lists the component suppliers. the standard applica- tion circuit (figure 2) of the max1530 is similar to the max1531 application circuit except that gate-on and gate-off voltages are eliminated. detailed description the max1530/max1531 power-supply controllers pro- vide logic and bias power for lcd monitors. figure 3 shows the ic functional diagram. the main step-down controller employs a current-mode pwm control method to ease compensation requirements and provide excel- lent load- and line-transient response. the use of syn- chronous rectification yields excellent efficiency. the max1530 includes three analog gain blocks to control three auxiliary positive linear regulators, and the max1531 includes five analog gain blocks to control four positive and one negative linear regulators. use the positive gain blocks to generate low-voltage rails directly from the input voltage or the main step-down converter output, or higher voltages using charge designation description c3 4.7f, 25v x7r ceramic capacitor (1210) tdk c3225x7r1e475k c7 22f, 6.3v x7r ceramic capacitor tdk c3216x7r0j226m c9 10f, 6.3v x5r ceramic capacitor tdk c2012x5r0j106m c12, c19* 0.47f, 16v x7r ceramic capacitors (0805) tdk c2012x7r1c474k c13 4.7f, 16v x7r ceramic capacitor tdk c3216x7r1c475k c21, c22 2.2f, 25v x7r ceramic capacitors (1206) tdk c3216x7r1c475m d1, d6* 100ma, 30v schottky diodes (sod523) central semiconductor cmosh-3 d2 100ma, 75v, small-signal switching diode, sot23 fairchild semiconductor mmbd4148 designation description d3*, d4*, d5* 200ma, 25v dual schottky diodes (sot23) fairchild bat54s l1 10h, 2.3a (dc) inductor sumida cdr7d28mn-100 n1 2.5a, 30v dual n-channel mosfet (6-pin super sot) fairchild fdc6561an q1, q4 3a, 60v l ow - satur ati on p n p b i p ol ar tr ansi stor s ( s o t- 223) fai r chi l d n z t660a q2, q3* 200ma, 40v pnp bipolar transistors (sot23) fairchild mmbt3906 q5*, q6* 200m a, 40v n p n b i p ol ar tr ansi stor s ( s ot23) fai r chi l d m m bt3904 table 1. selected component list supplier phone fax website central semi 516-435-1110 516-435-1824 www.centralsemi.com fairchild 888-522-5372 972-910-8036 www.fairchildsemi.com sumida 847-956-0666 847-956-0702 www.sumida.com tdk 847-803-6100 847-390-4405 www.components.tdk.com table 2. component suppliers * for max1531 only.
max1530/max1531 multiple-output power-supply controllers for lcd monitors ______________________________________________________________________________________ 17 max1531 osc ref slope clock vl timer vlok v ref sequence 0.9vref v ref 0.9vref v ref soft- start 0.9vref v ref 0.9vref v ref soft- start soft- start soft- start soft- start 400mv v ref thermal en fault logic on2 on3 on4 on5 ldo3en flt3 ldo4en flt4 flt5 flt2 flt1 ldo2en ldo5en vlok en freq en rstin reset gnd comp fb seq onl2 onl3 onl4 onl5 lr1 lr2 lr3 lr4 lr5 fbl1 drv1 drv2 drv5 drv4 drv3 fbl2 fbl5 fbl4 fbl3 ilim vl in fltm 300mv csh csl fltcs pgnd dl lx dh bst vl ss done fltm dc-dc en step-down controller comp fb ilim in lx dh dl pgnd high-side driver low-side driver seq figure 3. ic functional diagram
max1530/max1531 multiple-output power-supply controllers for lcd monitors 18 ______________________________________________________________________________________ pumps attached to the switching node or extra wind- ings coupled to the step-down converter inductor. the negative gain block (max1531) can be used in con- junction with a charge pump or coupled winding to generate the lcd gate-off voltage or other negative supplies. step-down controller the max1530/max1531 include step-down controllers that use a fixed-frequency current-mode pwm control scheme (figure 4). an internal transconductance amplifier establishes an integrated error voltage at the comp pin. the heart of the current-mode pwm con- troller is an open-loop comparator that compares an integrated voltage-feedback signal with an amplified current-sense signal plus a slope-compensation ramp. at each rising edge of the internal clock, the high-side mosfet turns on until the pwm comparator trips or the maximum duty cycle is reached. during this on-time, current ramps up through the inductor, sourcing cur- rent to the output and storing energy in a magnetic field. the current-mode feedback system regulates the peak inductor current as a function of the output volt- age error signal. since the average inductor current is nearly the same as the peak inductor current (assum- ing that the inductor value is relatively high to minimize ripple current), the circuit acts as a switch-mode transconductance amplifier. that pushes the output lc filter pole, normally found in a voltage-mode pwm, to a higher frequency. to preserve loop stability, the slope- compensation ramp is summed into the main pwm comparator. during the second half of the cycle, the high-side mos- fet turns off and the low-side n-channel mosfet turns on. now the inductor releases the stored energy as its current ramps down, providing current to the output. the output capacitor stores charge when the inductor current exceeds the load current and discharges when the inductor current is lower, smoothing the voltage across the load. under overload conditions, when the inductor current exceeds the selected current limit (see current limit circuit ), the high-side mosfet is not turned on at the rising edge of the clock and the low- side mosfet remains on to let the inductor current ramp down. under light-load conditions, the max1530/max1531 maintain a constant switching frequency to minimize cross-regulation errors in applications that use a trans- former. the low-side gate-drive waveform is the comple- ment of the high-side gate-drive waveform, which causes the inductor current to reverse under light loads. current-sense amplifier the max1530/max1531s current-sense circuit ampli- fies the current-sense voltage generated by the high- side mosfet s on-resistance. this amplified current-sense signal and the internal slope compensa- tion signal are summed together and fed into the pwm comparator s inverting input. place the high-side mos- fet near the controller, and connect in and lx to the mosfet using kelvin-sense connections to guarantee current-sense accuracy and improve stability. current-limit circuit the max1530/max1531 include two current-limit cir- cuits that use the two mosfets on-resistances as cur- rent-sensing elements (figure 4). the high-side mosfet s voltage is used with a fixed 400mv (typ) cur- rent-limit threshold during the high-side on-times. the low-side mosfet s voltage is used with an adjustable current-limit threshold during the low-side on-times. using both circuits together ensures that the current is always measured and controlled. the high-side mosfet current limit employs a peak current limit. if the voltage across the high-side mos- fet, measured from in to lx, exceeds the 400mv threshold during an on-time, the high-side mosfet turns off and the low-side mosfet turns on. the low-side mosfet current-limit circuit employs a valley current limit. if the voltage across the low-side mosfet, measured from lx to pgnd, exceeds the low-side threshold at the end of a low-side on-time, the low-side mosfet remains on and the high-side mos- fet stays off for the entire next cycle. figure 4. step-down controller block diagram slope current sense and current limit gm fltm 0.9vref soft- start v ref dc-dc en ss done current limit comp fb pgnd dl lx dh ilim r s q in clock fault comparator pwm comp q
max1530/max1531 multiple-output power-supply controllers for lcd monitors ______________________________________________________________________________________ 19 the ilim pin is a dual-mode input. when ilim is con- nected to vl, a default low-side current limit of 250mv (typ) is used. if ilim is connected to a voltage between 250mv and 3v, the low-side current limit is typically 1/5th the ilim voltage. the max1530/max1531s current limits are compara- tively inaccurate, since the maximum load current is a function of the mosfets on-resistances and the induc- tor value, as well as the accuracy of the two thresholds. however, using mosfet current sensing reduces both cost and circuit size and increases efficiency, since sense resistors are not needed. mosfet gate drivers (dh, dl) the dh and dl drivers are optimized for driving mod- erate-size high-side and low-side mosfets. adaptive dead-time circuits monitor the dl and dh drivers and prevent either fet from turning on until the other is fully off. this algorithm allows operation without shoot- through with a wide range of mosfets, minimizing delays and maintaining efficiency. when the gates are turning off, there must be low-resistance, low-induc- tance paths from the gate drivers to the mosfet gates for the adaptive dead-time circuit to work properly. otherwise, the sense circuitry in the max1530/ max1531 interpret the mosfet gate as "off" while gate charge actually remains. use short, wide traces mea- suring less than 50 squares (at least 20 mil wide if the mosfet is 1in from the device). it is advantageous to slow down the turn-on of both gate drivers if there is noise coupling between the switching regulator and the linear regulators. the noise coupling can result in excessive switching ripple on the linear regulator outputs. slowing down the turn-on of the gate drivers proves to be an effective way of reduc- ing the output ripple. take care to ensure that the turn- off times are not affected at the same time. as explained above, slowing down the turn-off times may result in shoot-through problems. in figure 1, a 10 ? resistor (r5) is inserted in series with the bst pin to slow down the turn-on of the high-side mosfet (n1-b) without affecting the turn-off. a 10 ? resistor (r6) is also inserted between dl and the gate of the low-side mos- fet (n1-a) to slow its turn-on. because the gate resis- tor would slow down the turn-off time, connect a switching diode (d2) (such as 1n4148) in parallel with the gate resistor as shown in figure 1 to prevent poten- tial shoot-through. high-side gate-drive supply (bst) a flying-capacitor bootstrap circuit generates gate- drive voltage for the high-side n-channel switch (figure 1). the capacitor c5 between bst and lx is alternately charged from the vl supply and placed parallel to the high-side mosfet s gate-source terminals. on startup, the synchronous rectifier (low-side mos- fet) forces lx to ground and charges the boost capacitor from vl through diode d1. on the second half-cycle, the switch-mode power supply turns on the high-side mosfet by closing an internal switch between bst and dh. this provides the necessary gate-to-source voltage to turn on the high-side switch, an action that boosts the 5v gate-drive signal above the input voltage. oscillator frequency selection (freq) the freq pin can be used to select the switching fre- quency of the step-down regulator. connect freq to vl for 500khz operation. connect freq to agnd for 250khz operation. the 500khz operation minimizes the size of the inductor and capacitors. the 250khz opera- tion improves efficiency by 2% to 3%. linear regulator controllers the max1530/max1531 include three positive linear regulator controllers, lr1, lr2, and lr3. these linear regulator controllers can be used with external pass transistors to regulate supplies for tft lcds. the max1531 includes an additional positive linear regula- tor controller (lr4) and a negative linear regulator con- troller (lr5). low-voltage logic regulator controller (lr1) lr1 is an analog gain block with an open-drain n- channel output. it drives an external pnp pass transis- tor with a 6.8k ? base-to-emitter resistor. its guaranteed base drive sink current is at least 3ma. the regulator including transistor q1 in figure 1 uses a 10f output capacitor and is designed to deliver 500ma at 2.5v. lr1 is typically used to generate low-voltage logic sup- plies for the timing controller and the digital sections of the tft lcd source/gate driver ics. lr1 is enabled when the soft-start of the main step- down regulator is complete. (see the startup sequence (onl_,seq) section.) each time it is enabled, the con- troller goes through a soft-start routine that ramps up its internal reference dac. (see the soft-start section.) gamma regulator controller (lr2) lr2 is an analog gain block with an open-drain n- channel output. it drives an external pnp pass transis- tor with a 6.8k ? base-to-emitter resistor. its guaranteed base drive sink current is at least 2ma. the regulator including transistor q2 in figure 1 uses a 0.47f output capacitor and is designed to deliver 50ma at 9.7v.
max1530/max1531 multiple-output power-supply controllers for lcd monitors 20 ______________________________________________________________________________________ lr2 is typically used to generate the tft lcd gamma reference voltage, which is usually 0.3v below the source drive supply voltage. lr2 is enabled when the step-down regulator is enabled and the voltage on onl2 exceeds onl2 input threshold (1.238v typ). (see the startup sequence (onl_,seq) section.) each time it is enabled, the con- troller goes through a soft-start routine that ramps up its internal reference dac. (see the soft-start section). linear regulator controller (lr3) lr3 is an analog gain block with an open-drain n- channel output. it drives an external pnp pass transis- tor with a 6.8k ? base-to-emitter resistor. its guaranteed base drive sink current is at least 2ma. the regulator, including q3 in figure 1, uses a 0.47f output capaci- tor and is designed to deliver 20ma at 25v. the regula- tor including q3 in figure 2 uses a 4.7f output capacitor and is designed to deliver 500ma at 10v. for the max1531 (figure 1), lr3 is typically used to gen- erate the tft lcd gate driver s gate-on voltage. a suffi- cient input voltage can be produced using a charge-pump circuit as shown in figure 1. note that the voltage rating of the drv3 output is 28v. if higher volt- ages are present, an external cascode npn transistor (q6) should be used with the emitter connected to drv3, the base to v in (which is the connection point of c1 and r12 in figure 1), and the collector to the base of the pnp pass transistor (figure 1). for the max1530 (figure 2), lr3 is typically used to generate the tft lcd source drive supply voltage. the input for this regulator can come directly from the input supply, be produced from an external step-up regulator, or from an extra wind- ing coupled to the main step-down regulator inductor. lr3 is enabled when the step-down regulator is enabled and the voltage on onl3 exceeds the onl3 input threshold (1.238v typ). (see the startup sequence (onl_,seq) section.) each time it is enabled, the con- troller goes through a soft-start routine that ramps up its internal reference dac. (see the soft-start section.) source drive regulator controller (lr4) (max1531 only) lr4 is an analog gain block with an open-drain n- channel output. it drives an external pnp pass transis- tor with a 1.5k ? base-to-emitter resistor. its guaranteed base drive sink current is at least 10ma. the regulator including q4 in figure 1 uses a 4.7f output capacitor and is designed to deliver 500ma at 10v. the regula- tor s fast transient response allows it to handle brief peak currents up to 2a. lr4 is typically used to generate the tft lcd source drive supply voltage. the input for this regulator can come directly from the input supply, be produced from an external step-up regulator, or from an extra winding coupled to the main step-down regulator inductor. lr4 is enabled when the step-down regulator is enabled and the voltage on onl4 exceeds the onl4 input threshold (1.238v typ). (see the startup sequence (onl_,seq) section.) each time it is enabled, the regulator goes through a soft-start routine that ramps up its internal reference dac from 0v to 1.238v (typ). (see the soft-start section.) the standard application circuit in figure 1 powers the lr4 regulator directly from the input supply and uses the max1531 s general-purpose overcurrent protection function to protect the input supply from excessive load currents. (see the overcurrent protection section.) gate-off regulator controller (lr5) (max1531 only) lr5 is an analog gain block with an open-drain p-chan- nel output. it drives an external npn pass transistor with a 6.8k ? base-to-emitter resistor. its guaranteed base drive sink current is at least 2ma. the regulator including q5 in figure 1 uses a 0.47f output capacitor and is designed to deliver 10ma at -10v. lr5 is typically used to generate the tft lcd gate dri- ver s gate-off voltage. a negative input voltage can be produced using a charge-pump circuit as shown in figure 1. use as many stages as necessary to obtain the required output voltage. lr5 is enabled when the step-down regulator is enabled and the voltage on onl5 exceeds the onl5 input threshold (1.238v typ). (see the startup sequence (onl_,seq) section.) each time it is enabled, the regulator goes through a soft-start routine that ramps down its internal reference dac from vl to 125mv (typ). (see the soft-start section.) internal 5v linear regulator (vl) all max1530/max1531 functions, except the thermal sensor, are internally powered from the on-chip, low- dropout 5v regulator. the maximum regulator input voltage (v in ) is 28v. bypass the regulator s output (vl) with at least a 1f ceramic capacitor to agnd. the v in -to-vl dropout voltage is typically 200mv, so when v in is less than 5.2v, vl is typically v in - 200mv. the internal linear regulator can source up to 30ma to sup- ply the device, power the low-side gate driver, charge the external boost capacitor, and supply small external loads. when driving particularly large mosfets, little or no regulator current may be available for external
max1530/max1531 multiple-output power-supply controllers for lcd monitors ______________________________________________________________________________________ 21 loads. for example, when switched at 500khz, large mosfets with a total of 40nc total gate charge would require 40nc 500khz, which is approximately 20ma. on/off control (en) the en pin has an accurate 1.238v (typ) rising thresh- old with 5% hysteresis. the accurate threshold allows it to be used to monitor the input voltage or other analog signals of interest. if v en voltage is less than its thresh- old, then the step-down regulator and all linear regula- tors are turned off. vl and the internal reference remain active when en is low to allow an accurate en thresh- old. a rising edge on the pin clears any latched faults except for a thermal fault, which is cleared only by cycling the input power. undervoltage lockout if vl drops below 3.4v (typ), the max1530/max1531 assume that the supply voltage is too low to make valid decisions. therefore, the undervoltage lockout (uvlo) circuitry turns off all the internal bias supplies. switching is inhibited, and the dl and dh gate drivers are forced low. after vl rises above 3.5v (typ), the fault and thermal shutdown latches are cleared and startup begins if en is above its threshold. startup sequence (onl_, seq) the max1530/max1531 are not enabled unless all four of the following conditions are met: 1) vl exceeds the uvlo threshold, 2) en is above 1.238v, 3) the fault latch is not set, and 4) the thermal shutdown latch is not set. after all four conditions are met, the step-down con- troller starts switching and enables soft-start (figure 5). after the step-down regulator soft-start is done, the low- voltage logic linear regulator controller (lr1) soft-starts. the remaining linear regulator controllers and the sequence block that can be used to control them are enabled at the same time as the step-down regulator. the seq logic input is used in combination with the onl_ pins to control the startup sequence. when seq is high and the sequence block is enabled, each onl_ pin sources 2a (typ). when the voltage on an onl_ pin reaches 1.238v (typ), its respective linear regulator controller (lr_) is enabled. when seq is low or the sequence block is not enabled, each onl_ pin is con- nected to ground through a 1.5k ? internal mosfet. the sequence block allows the user to program the startup of lr2 to lr5 in any desired sequence. if no capacitor is placed on an onl_ pin, its lr_ controller starts immediately after the sequence block is enabled and seq goes high. placing a 1.5nf capacitor on an onl_ pin provides about 1ms delay for the respective lr_ controller. placing different size capacitors on each onl_ pin allows any arbitrary startup sequence. an arbitrary startup sequence can also be created with a single capacitor (figure 6). capacitor c1, together with the 8a current (2a per onl_ pin), is chosen to provide the desired delay for the controller that starts last (onld). using 0.1f for c1 provides about 16ms figure 6. single-capacitor sequence configuration seq onl_ 0v 1.238v 5v lra lrb lrc lrd on on on on off off off off off off off off 16ms onla onlb onlc onld onla onlb onlc onld r2 75k ? r3 150k ? r1 51k ? c1 0.1 f figure 5. startup conditions onl_ current sources on sequence block enabled lr5 startup lr4 startup lr2 startup lr1 startup seq = high onl5 > 1.24v onl2 > 1.24v onl4 > 1.24v lr3 startup step-down regulator startup step-down soft-start done en > 1.24v and vl > 3.5v onl3 > 1.24v
max1530/max1531 multiple-output power-supply controllers for lcd monitors 22 ______________________________________________________________________________________ total delay. because of the 6a current flowing through r1 (51k ? ), the voltage on onlc is 0.31v greater than the voltage on onld and it crosses the 1.238v thresh- old and enables its lr_ controller about 4ms before onld s controller. similarly, the 4a current through r2 (75k ? ) and the 2a current through r3 (150k ? ) cause their lr_ controllers to each start about 4ms before the next one. any desired sequence and delay can be pro- grammed by calculating the charge rate of c1 and volt- age drops across r1 through r3. soft-start the soft-start function controls the slew rate of the out- put voltages and reduces inrush currents during start- up. each regulator (step-down, lr1 to lr5) goes through a soft-start routine after it is enabled. during soft-start, the reference voltage for each positive regu- lator gradually ramps up from 0v to the internal refer- ence in 32 steps. the reference voltage of the negative regulator ramps down from vl to 125mv in 32 steps. the total soft-start period for each regulator is 1024 clock cycles for 250khz switching frequency and 2048 clock cycles for 500khz switching frequency. reset the max1530/max1531 include an open-drain timed microprocessor supervisor function to ensure proper startup of digital circuits. the reset output asserts low whenever rstin is less than the rstin trip threshold. reset also asserts low when vl is less than the vl uvlo threshold, en is low, or the thermal, undervolt- age or overcurrent fault latches are set. reset enters the high-impedance state only after rstin remains above the trip threshold for the duration of the reset timeout period. the state of reset has no effect on other portions of the ic. the rstin threshold (1.114v typ) is designed to allow rstin to directly connect to any of the max1530/ max1531s feedback input pins, eliminating the need for an additional resistive divider. typically, rstin is connected to fb or fbl1 to monitor the supply voltage for digital logic ics, but it can be used to monitor any desired output voltage or it can even be used as a gen- eral-purpose comparator. fault protection undervoltage protection after its soft-start is done, if the output of the main step- down regulator or any of the linear-regulator outputs (lr1 to lr5) are below 90% of their normal regulation point, the max1530/max1531 activate an internal fault timer. if the fault condition remains continuously for the entire fault timer duration, the max1530/max1531 set the fault latch, shutting down all the regulator outputs. undervoltage faults do not turn off vl. once the fault condition is removed, cycling the input voltage or applying a rising edge on seq or en clears the fault latch and reactivates the device. thermal protection the thermal protection limits total power dissipation in the max1530/max1531. if the junction temperature exceeds +160 c, a thermal sensor immediately sets the thermal fault latch, shutting off all the ic s outputs including vl, allowing the device to cool down. the only way to clear the thermal fault latch is to cycle the input voltage after the device cools down by at least 15 c. overcurrent protection block (csh, csl) (max1531 only) the max1531 includes an uncommitted overcurrent protection block that can be used to measure any input or output current, using a current-sense resistor or other sense element. if the measured current exceeds the overcurrent protection threshold (300mv typ), the max1531 immediately sets the undervoltage fault latch, shutting down all the regulator outputs. overcurrent faults do not turn off vl. an internal lowpass filter pre- vents large current transients of short duration (less than 50s) from setting the latch. once the overcurrent condition is removed, cycling the input voltage clears the fault latch and reactivates the device. a rising edge on seq or en also clears the fault latch. in figure 1 s circuit, the overcurrent protection is used with the lr4 source driver regulator since that regulator is powered directly from the input supply and has no current limit of its own. the current-sense resistor is placed in series with the input supply, before the linear regulator s external pnp pass transistor. csh and csl are connected to the positive and negative sides of the sense resistor. design procedures main step-down regulator inductor selection three key inductor parameters must be specified: inductance value (l), peak current (i peak ), and dc resistance (r dc ). the following equation includes a constant, lir, which is the ratio of peak-to-peak induc- tor ripple current to dc load current. a higher lir value allows smaller inductance, but results in higher losses and higher ripple. a good compromise between size and losses is typically found at a 30% ripple current to
max1530/max1531 multiple-output power-supply controllers for lcd monitors ______________________________________________________________________________________ 23 load current ratio (lir = 0.3), which corresponds to a peak inductor current 1.15 times the dc load current: where i load(max) is the maximum dc load current, and the switching frequency f sw is 500khz when freq is tied to vl, and 250khz when freq is tied to agnd. the exact inductor value is not critical and can be adjusted to make trade-offs among size, cost, and effi- ciency. lower inductor values minimize size and cost, but they also increase the output ripple and reduce the efficiency due to higher peak currents. on the other hand, higher inductor values increase efficiency, but at some point increased resistive losses due to extra turns of wire will exceed the benefit gained from lower ac current levels. the inductor s saturation current must exceed the peak inductor current. the peak current can be calculated by: the inductor s dc resistance should be low for good efficiency. find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimen- sions. ferrite cores are often the best choice, though powdered iron is inexpensive and can work well at 250khz. shielded-core geometries help keep noise, emi, and switching waveform jitter low. mosfet selection and current-limit setting the max1530/max1531s step-down controller drives two external logic-level n-channel mosfets. since the r ds(on) of each mosfet is used as a sense resistor to provide current-sense signals to the pwm, their r ds(on) values are important considerations in compo- nent selection. the r ds(on) of the high-side mosfet (n1) provides an inductor current-sense signal for current-mode opera- tion and also provides a crude maximum current limit during the high-side on-time that prevents runaway cur- rents if the inductor saturates. the mosfet voltage is measured across the high-side mosfet from v in to lx and is limited to 400mv (typ). to ensure the desired output current with sufficient margin, choose a mosfet with r ds(on) low enough that the peak current does not generate more than 340mv across the mosfet, even when the mosfet is hot. if the mosfet s r ds(on) is not specified at a suitable temperature, use the maximum room temperature specification and add 0.5% per c for the r ds(on) increase with temperature: to ensure stable operation of the current-mode pwm, the minimum current-sense ripple signal should exceed 12mv. since this value depends on the minimum r ds(on) of the high-side mosfet, which is not typical- ly a specified parameter, a good rule of thumb is to choose the typical room temperature r ds(on) about 2 times the amount needed for this: for example, figure 1 s circuit is designed for 1.5a and uses a dual mosfet (n1) for both the high-side and low-side mosfets. its maximum r ds(on) at room tem- perature is 145m ? and an estimate of its maximum r ds(on) at our chosen maximum temperature of +85 c is 188m ? . since the inductor ripple current is 0.5a, the peak current through the mosfet is 1.75a. so the maxi- mum peak current-sense signal is 330mv, which is less than 340mv. using the typical r ds(on) of 113m ? and the ripple current of 0.5a, the current ripple signal for the pwm is 56mv, much greater than the required 24mv. the r ds(on) of the low-side mosfet (also n1) pro- vides current-limit information during the low-side on- time that inhibits a high-side on-time if the mosfet voltage is too high. the voltage is measured across the low-side mosfet from pgnd to lx and the threshold is set by ilim. to use the preset 250mv (typ) threshold, connect ilim to vl and choose a mosfet with r ds(on) low enough that the valley current does not generate more than 190mv across the mosfet, even when the mosfet is hot. if the mosfet s r ds(on) is not specified at a suitable temperature, use the maxi- mum room temperature specification and add 0.5% per c for the r ds(on) increase with temperature: if the mosfet s r ds(on) is lower than necessary, there is no need to adjust the current-limit threshold using ilim. if the mosfet s r ds(on) is too high, adjust the current-limit threshold using a resistive-divider between iii ir mv valley out ripple valley ds on hot =? < / ()_ 2 190 ir mv ripple ds on typ > ()_ 24 ir mv peak ds on hot < ()_ 340 i vvv flv ii i ripple out in out sw in peak load max ripple = ? =+ () () 2 l vvv v f i lir out in out in sw load max = ? () ()
max1530/max1531 multiple-output power-supply controllers for lcd monitors 24 ______________________________________________________________________________________ vl and agnd at ilim. the threshold is approximately 1/5th the voltage on ilim over a range of 0.25v to 3v: k is the accuracy of the current-limit threshold, which is 20% when the threshold is 250mv. for example, figure 1 s n1 mosfet has a maximum r ds(on) at room temperature of 145m ? and an esti- mate of its maximum at our chosen maximum tempera- ture of +85 c is 188m ? . since the inductor ripple current is 0.5a, the valley current through the mosfet is 1.25a. so the maximum valley current-sense signal is 235mv, which is too high to work with the 190mv mini- mum of the default current-limit threshold. adding a divider at ilim (r12 and r13) adjusts the ilim voltage to 1.7v and the current-limit threshold to 340mv, providing more than adequate margin for threshold accuracy. input capacitor the input filter capacitor reduces peak currents drawn from the power source and reduce noise and voltage ripple on the input caused by the regulator s switching. it is usually selected according to input ripple current requirements and voltage rating, rather than capaci- tance value. the input voltage and load current deter- mine the rms input ripple current (i rms ): the worst case is i rms = 0.5 i load , which occurs at v in = 2 v out . for most applications, ceramic capacitors are used because of their high ripple current and surge current capabilities. for long-term reliability, choose an input capacitor that exhibits less than +10 c temperature rise at the rms input current corresponding to the max- imum load current. output capacitor the output capacitor and its equivalent series resis- tance (esr) affect the regulator s loop stability, output ripple voltage, and transient response. the compensation design section discusses the output capacitance requirement based on the loop stability. this section deals with how to determine the output capacitance and esr needs according to the ripple voltage and load transient requirements. the output voltage ripple has two components: varia- tions in the charge stored in the output capacitor, and the voltage drop across the capacitor s esr caused by the current into and out of the capacitor: where c out is the output capacitance, and r esr is the esr of the output capacitor. in figure 1 s circuit, the inductor ripple current is 0.5a. assume the voltage-rip- ple requirement is 2% (peak-to-peak) of the 3.3v out- put, which corresponds to 66mv total peak-to-peak ripple. assuming that the esr ripple component and the capacitive ripple component each should be less than 50% of the 66mv total peak-to-peak ripple, then the esr should be less than 66m ? and the output capacitance should be more than 7.6f to meet the total ripple requirement. a 22f ceramic capacitor with esr (including pc board trace resistance) of 10m ? is selected for the standard application circuit in figure 1, which easily meets the voltage ripple requirement. the step-down regulator s output capacitance and esr also affect the voltage undershoot and overshoot when the load steps up and down abruptly. the undershoot and overshoot have three components: the voltage steps caused by esr, the voltage undershoot and overshoot due to the current-mode control s ac load regulation, and the voltage sag and soar due to the finite capacitance and inductor slew rate. the amplitude of the esr steps is a function of the load step and the esr of the output capacitor: the amplitude of the sag due to the finite output capac- itance and inductor slew rate is a function of the load step, the output capacitor value, the inductor value, the input-to-output voltage differential, and the maximum duty cycle: the amplitude of the undershoot due to the ac load regulation is a function of the high-side mosfet r ds(on) , the gain of the current-sense amplifier a vcs , the change of the slope compensation during the under- shoot ( ? sc under ), the transconductance of the error v li cv dv sag lc load out in min max out _ () () () = ? 2 2- vir esr step load esr _ = ? vv v vir v i cf ripple ripple esr ripple c ripple esr ripple esr ripple c ripple out sw =+ = = () () () () 8 ii vvv v rms load out in out in = ? () ir vk valley ds on hot ilim . ( ) ()_ max1530/max1531 multiple-output power-supply controllers for lcd monitors ______________________________________________________________________________________ 25 amplifier g m , the compensation resistor r comp , the fb regulation v fb , and the output voltage set point v out : use the following to calculate the slope compensation change during the sag: where d under is the duty cycle at the valley of the sag, which is usually 50%. the actual undershoot is always equal to or bigger than the worst of v esr_step , v sag_lc , and v under_ac . the amplitude of the soar due to the finite output capacitance and inductor slew rate is a function of the load step, the output capacitor value, the inductor value, and the output voltage: the amplitude of the overshoot due to the ac load reg- ulation is: where ? sc over is the change of the slope compensa- tion during the overshoot, given by: where d over is the duty cycle at the peak of the over- shoot, which is typically 0%. similarly, the actual overshoot is always equal to or big- ger than the worst of v esr_step , v soar_lc , and v over_ac . given the component values in the circuit of figure 1, during a 1.5a step load transient, the voltage step due to capacitor esr is negligible. the voltage sag due to finite capacitance and inductor slew rate is 81mv, and the voltage undershoot due to the ac load regulation is 170mv. the total undershoot seen in the typical operating characteristics is 170mv. the voltage soar due to finite capacitance and inductor slew rate is 155mv, and the voltage overshoot due to the ac load regulation is 167mv. the total overshoot seen the in the typical operating characteristics is 200mv. compensation design the step-down controller of the max1530/max1531 uses a peak current-mode control scheme that regu- lates the output voltage by forcing the required current through the inductor. the max1530/max1531 use the voltage across the high-side mosfet s r ds(on) to sense the inductor current. using the current-sense amplifier s output signal and the amplified feedback voltage sensed at fb, the control loop sets the peak inductor current by: where v fb = 1.238v is the fb regulation voltage, a vcs is the gain of the current-sense amplifier (3.5 typical), a vea is the dc gain of the error amplifier (2000 typ), v out(set) is the output voltage set point, and r ds(on) is the on-resistance of the high-side mosfet. the total dc loop gain (a dc ) is approximately: r le is the equivalent load resistance, given by: in the above equation, d = 1 - d, n is a factor deter- mined by the slope compensation m c and the inductor current ramp m 1 , as shown below: the slope compensation of the max1530/max1531 is 219mv/s. the inductor current ramp is a function of the input voltage, output voltage, inductance, high-side mosfet on-resistance r ds(on) , and the gain of the current-sense amplifier a vcs , and is: m vv l ra in out ds on vcs 1 () = - n m m c =+ 1 1 r v i lf ndd le out load max sw = ? ? ? ? ? ? ? ? ? ? ? ? ' () || - a vr a vra dc fb le vea out set ds on vcs = () () i vv va vra peak out out set fb vea out set ds on vcs = () () () () - ? sc mv v v d over out in over = ? ? ? ? ? ? . 437 5 - v v ar i sc vr g over ac out vcs ds on load over fb comp m _ () = + ? ? ? ? ? ? ? ? v li cv soar lc load out out _ () = ? 2 2 ? sc mv d v v under under out in = ? ? ? ? ? ? . 437 5 - v v ar i sc vr g under ac out vcs ds on load under fb comp m _ () = + ? ? ? ? ? ? ? ?
max1530/max1531 multiple-output power-supply controllers for lcd monitors 26 ______________________________________________________________________________________ current-mode control has the effect of splitting the complex pole pair of the output lc filter into a single low-frequency pole and a single high-frequency pole. the low-frequency current-mode pole depends on out- put capacitor c out and the equivalent load resistance r le , given by the following: the high-frequency current-mode pole is given by: the comp pin, which is the output of the ic s internal transconductance error amplifier, is used to stabilize the control loop. a series resistor (r11) and capacitor (c10) are connected between comp and agnd to form a pole-zero pair. another pole-zero pair can be added by connecting a feed-forward capacitor (c23) in parallel with feedback resistor r1. the compensation resistor and capacitors are selected to optimize the loop stability. the compensation capacitor (c10) creates a dominant pole at very low frequency (a few hertz). the zero formed by r11 and c10 cancels the low-frequency cur- rent-mode pole. the zero formed by r1 and c23 can- cels the high-frequency current-mode pole and introduces a preferable higher frequency pole. in appli- cations where ceramic capacitors are used, the esr zero is usually not a concern because the esr zero occurs at very high frequency. if the esr zero does not occur at a frequency at least one decade above the crossover, connect a second parallel capacitor (c2) between comp and agnd to cancel the esr zero. the component values shown in the standard application circuits (figure 1 and 2) yield stable operation and fast transient response over a broad range of input-to-out- put voltages. to design a compensation network for other compo- nents or applications, use the following procedure to achieve stable operation: 1) select the crossover frequency f crossover (bandwidth) to be 1/5th the switching frequency f sw or less: unnecessarily high bandwidth can increase noise sensitivity while providing little benefit. good tran- sient response with low amounts of output capaci- tance is achieved with a crossover frequency between 20khz and 100khz. the series compensa- tion capacitor (c10) generates a dominant pole that sets the desired crossover frequency. determine c10 using the following expression: where g m is the error amplifier s transconductance (100s typ). 2) the compensation resistor r11, together with capac- itor c10, provides a zero that is used to cancel the low-frequency current-mode pole. determine r11 using the following expression: 3) because the error amplifier has limited output cur- rent (16a typ), small values of r11 can prevent the error amplifier from providing an immediate comp voltage change required for good transient response with minimal output capacitance. if the calculated r11 value is less than 100k ? , use 100k ? and recal- culate c10 using the following formula: changing c10 also changes the crossover frequen- cy; the new crossover frequency is: the calculated crossover frequency should be less than 1/5th the switching frequency. there are two ways to lower the crossover frequency if the calculat- ed value is greater than 1/5th the switching frequen- cy: increase the high-side mosfet r ds(on ), or increase the output capacitance. increasing r ds(on) reduces the dc loop gain, which results in lower crossover frequency. increasing output capacitance reduces the frequency of the lower low-frequency current-mode pole, which also results in lower crossover frequency. the following formula gives the f ga ca crossover mdc vea = 210 c fk pole low 10 1 2 100 () ? r fc pole low 11 1 210 () c ga fa mdc crossover vea 10 2 f f crossover sw 5 f f nd pole high sw () ' = 2 f rc pole low le out () = 1 2
max1530/max1531 multiple-output power-supply controllers for lcd monitors ______________________________________________________________________________________ 27 crossover frequency as a function the mosfet r ds(on) and the output capacitance: change one or both of these circuit parameters to obtain the desired crossover. recalculate adc and repeat steps 1 to 3 after making the changes. 4) if f pole(high) is less than the crossover frequency, cancel the pole with a feed-forward zero. determine the value of c23 (feedback capacitor) using the following: c23 also forms a secondary pole with r1 and r2 given by the following: the frequency of this pole should be above the crossover frequency for loop stability. the position of this pole is related to the high-frequency current- mode pole, which is determined by the inductor cur- rent ramp signal. the inductor current ramp signal must satisfy the following condition to ensure the pole occurs above the crossover frequency: if the frequency of the secondary pole is below the crossover frequency, the frequency of the secondary pole must be moved higher, or the crossover fre- quency must be moved lower. there are two ways to increase the frequency of the secondary pole: increase the high-side mosfet r ds(on ), or reduce the step-down inductance, l. as explained before, for given input and output voltages, the current ramp sig- nal is proportional to the high-side mosfet r ds(on) , and inversely proportional to the inductance. if the pole occurs below the crossover frequency, the cur- rent feedback signal is too small. increasing r ds(on) or reducing the inductance can increase the current feedback signal. to lower the crossover frequency, use the methods described in step 3. repeat steps 1 to 4 after making the changes. 5) for most applications using tantalum or polymer capacitors, the output capacitor s esr forms a sec- ond zero that occurs either below or close to the crossover frequency. the zero must be cancelled with a pole. verify the frequency of the output capac- itor s esr zero, which is: where r esr is the esr of the output capacitor c out . if the output capacitor s esr zero does not occur well after the crossover, add the parallel compensa- tion capacitor (c2) to form another pole to cancel the esr zero. calculate the value of c2 using: applications using ceramic capacitors usually have esr zeros that occur at least one decade above the crossover. since the esr zero of ceramic capacitors has little effect on the loop stability, it does not need to be cancelled. the following is an example. in the circuit of figure 1, the input voltage is 12v, the output voltage is set to 3.3v, the maximum load current is 1.5a, the typical on- resistance of the high-side mosfet is 100m ? , and the inductor is 10h. the calculated equivalent load resis- tance is 1.67 ? . the dc loop gain is: if the chosen crossover frequency is 20khz (step 1): with a 22f output capacitor, the output pole of the step-down regulator is (step 2): calculate r11 using: r khz nf k 11 1 243 17 22 = . . ? f f khz pole out () . . = = 1 222 167 43 ? c s khz nf 10 100 4180 2 20 2000 17 . a v vm dc = . . . . 1 238 1 67 2000 33 100 35 4180 ? ? c c frc zero esr 2 10 211101 () - f cr zero esr out esr () = 1 2 m dr f m rr f d r f crossover c sw crossover 1 22 12 2 2 > + () ' ' - f rr c pole sec _ || = () 1 21223 c fr pole high 23 1 21 () f gv r av cr crossover mfb vcs out set out ds on = () () 11 2
max1530/max1531 multiple-output power-supply controllers for lcd monitors 28 ______________________________________________________________________________________ because r11 is less than 100k ? , use 100k ? for r11 and recalculate c10 as (step 3): use the standard value of 470pf for c10 and recalcu- late the crossover frequency as: since the crossover frequency is less than 1/5th the switch- ing frequency, 470pf is an acceptable value for c10. because the high-frequency pole of the current-mode control is at 64khz, the feed-forward capacitor is (step 4): use a standard value of 150pf for c23. the pole formed by c23, r1 and r2 occur at 159khz, above the 70.8khz crossover frequency. because a ceramic output capacitor is used in the cir- cuit of figure1, the esr zero occurs well above the crossover frequency, so no additional compensation capacitor (c2) is needed (step 5). output voltage selection the max1530/max1531 step-down regulator s output voltage can be adjusted by connecting a resistive volt- age-divider from the output to agnd with the center tap connected to fb (figure 1). select r2 in the 5k ? to 50k ? range. calculate r1 with the following equation: where v fb = 1.238v, and v out may vary from 1.238v to approximately 0.6 v in (v in is up to 28v). boost-supply diode a signal diode, such as the 1n4148, works well in most applications. if the input voltage goes below 6v, use a small 100ma schottky diode for slightly improved effi- ciency and dropout characteristics. do not use power diodes, such as the 1n5817 or 1n4001, since high junction capacitance can charge up vl to excessive voltages. charge pumps selecting the number of charge-pump stages for highest efficiency, always choose the lowest num- ber of charge-pump stages that meet the output requirement. the number of positive charge-pump stages is given by: where n pos is the number of positive charge-pump stages, v pos is the positive charge-pump output, v in is the input voltage of the step-down regulator, v d is the forward voltage drop of the charge-pump diode, and v dropout is the dropout margin for the linear regula- tor. use v dropout = 0.3v. the number of negative charge-pump stages is given by: where n neg is the number of negative charge-pump stages, v neg is the negative charge-pump output, v in is the input voltage of the step-down regulator, v d is the forward voltage drop of the charge-pump diode, and v dropout is the dropout margin for the linear reg- ulator. use v dropout = 0.3v. the above equations are derived based on the assumption that the first stage of the positive charge pump is connected to v in and the first stage of the negative charge pump is connected to ground. sometimes fractional stages are more desirable for bet- ter efficiency. this can be done by connecting the first stage to v out or another available supply. if the first stage of the positive charger pump is powered from the output of the step-down regulator v out , then the equa- tion becomes: if the first stage of the negative charge pump is pow- ered from the output of the step-down regulator v out , then the equation becomes: n vv v vv neg neg dropout out in d = ?+ + ? 2 n vv v vv pos pos dropout out in d = ?+ ? ? 2 n vv vv neg neg dropout in d = ?+ ? 2 n vv v vv pos pos dropout in in d = +? ? 2 rr v v out fb 12 1 = ? ? ? ? ? ? ? c khz k pf 23 1 264 178 140 = . ? f s pf khz crossover = . 100 4180 2 470 2000 70 8 c khz k pf 10 1 2 4 3 100 370 = . ?
max1530/max1531 multiple-output power-supply controllers for lcd monitors ______________________________________________________________________________________ 29 flying capacitors increasing the flying capacitor value lowers the effec- tive source impedance and increases the output cur- rent capability. increasing the capacitance indefinitely has a negligible effect on output current capability because the internal switch resistance and the diode impedance place a lower limit on the source imped- ance. a 0.1f ceramic capacitor works well in most low-current applications. the voltage rating for a given flying capacitor (cx) must exceed the following: v cx > n x v in where n is the stage number in which the flying capaci- tor appears, and v in is the input voltage of the step- down regulator. charge-pump output capacitors increasing the output capacitance or decreasing the esr reduces the charge pump output ripple voltage and the peak-to-peak transient voltage. with ceramic capacitors, the output voltage ripple is dominated by the capacitance value. use the following equation to approximate the required capacitor value: where v ripple is the peak-to-peak value of the output ripple. charge-pump rectifier diodes use low-cost silicon switching diodes with a current rat- ing equal to or greater than 2 times the average charge-pump input current. if it helps avoid an extra stage, some or all of the diodes can be replaced with schottky diodes with an equivalent current rating. linear regulator controllers output voltage selection adjust the positive linear regulator (lr1 to lr4) output voltages by connecting a resistive voltage-divider from the output to agnd with the center tap connected to fbl_ (figure 1). select the lower resistor of the divider in the 10k ? to 30k ? range. calculate the upper resistor with the following equation: where v fbl _ is 1.238v (typ). adjust the negative linear regulator (lr5) output volt- age by connecting a resistive voltage-divider from v goff to vl with the center tap connected to fbl5 (figure 1). select r29 in the 10k ? to 30k ? range. calculate r28 with the following equation: where v fbl5 = 125mv and v l = 5.0v. pass transistor selection the pass transistor must meet specifications for dc current gain (h fe ), collector-emitter saturation voltage, and power dissipation. the transistor s current gain lim- its the guaranteed maximum output current to: where i drv is the minimum guaranteed base drive cur- rent, v be is the base-emitter voltage of the pass transis- tor, and r be is the pullup resistor connected between the transistor s base and emitter. furthermore, the tran- sistor s current gain increases the linear regulator s dc loop gain (see the stability requirements section), which may destabilize the output. therefore, transistors with current gain over 300 at the maximum output cur- rent can be difficult to stabilize and are not recom- mended unless the high gain is needed to meet the load current requirements. the transistor s saturation voltage at the maximum out- put current determines the minimum input-to-output voltage differential that the linear regulator supports. also, the package s power dissipation limits the usable maximum input-to-output voltage differential. the maxi- mum power dissipation capability of the transistor s package and mounting must exceed the actual power dissipation in the device. the power dissipation equals the maximum load current (i load(max) ) times the maxi- mum input-to-output voltage differential: where v lrin(max) is the maximum input voltage of the linear regulator, and v lrout is the output voltage of the linear regulator. output voltage ripple ideally, the output voltage of a linear regulator should not contain any ripple. in the max1530/max1531, the step-down regulator s switching noise can couple to the linear regulators, creating output voltage ripple. following the pc board layout guidelines in the pc board layout and grounding section can significantly reduce noise coupling. if there is still an unacceptable pi v v load max lrin max lrout = ? () () () ii v r h load max drv be be fe () =? ? ? ? ? ? ? rr v v vv fbl goff l fbl 28 29 55 = ? ? () [] )/( rr vv upper lower out fbl = () ? [] __ /1 c i fv out load osc ripple 2
max1530/max1531 multiple-output power-supply controllers for lcd monitors 30 ______________________________________________________________________________________ amount of ripple after the pc board layout has been optimized, consider increasing output capacitance. adding more capacitance does not eliminate the ripple, but proportionally reduces the amplitude of the ripple. if increasing the output capacitance is not desirable because of space or cost concerns, then consider slowing the turn-on of the step-down dc-to-dc mosfets. slower turn-on leads to smoother lx rising and falling edges and consequently reduces the switching noise. when slowing down mosfet turn-on, ensure the turn-off time is not affected. otherwise, the adaptive dead-time circuitry may not work properly and shoot-through may occur. see the mosfet gate drivers section for details on how to slow down the turn-on of both dh and dl. stability requirements the max1530/max1531 linear-regulator controllers use an internal transconductance amplifier to drive an external pass transistor. the transconductance amplifi- er, the pass transistor, the base-emitter resistor, and the output capacitor determine loop stability. the fol- lowing applies equally to all linear regulators in the max1530 and max1531. any differences are highlight- ed where appropriate. the transconductance amplifier regulates the output voltage by controlling the pass transistor s base cur- rent. the total dc loop gain is approximately: where v t is 26mv at room temperature, i load is the output current of the linear regulator, v ref is the linear regulator s internal reference voltage, and i bias is the current through the base-to-emitter resistor (r be ). each of the linear regulator controllers is designed for a dif- ferent maximum output current so they have different output drive currents and different bias currents (i bias ). each controller s bias current can be found in the electrical characteristics . the current listed in the conditions column for the fbl_ regulation voltage specification is the individual controller s bias current. the base-to-emitter resistor for each controller should be chosen to set the correct i bias : the output capacitor and the load resistance create the dominant pole in the system. however, the internal amplifier delay, the pass transistor s input capacitance, and the stray capacitance at the feedback node create additional poles in the system, and the output capacitor s esr generates a zero. for proper operation, use the fol- lowing steps to ensure the linear regulator s stability: 1) first, calculate the dominant pole set by the linear regulator s output capacitor and the load resistor: where c lr is the output capacitance of the linear regulator and r load is the load resistance corre- sponding to the maximum load current. the unity-gain crossover of the linear regulator is: 2) the pole created by the internal amplifier delay is about 1mhz: 3) next, calculate the pole set by the transistor s input capacitance, the transistor s input resistance, and the base-to-emitter pullup resistor: transconductance of the pass transistor, and f t is the transition frequency. both parameters can be found in the transistor s data sheet. because r be is much greater than r in , the above equation can be simplified: the equation can be further simplified: f f h pole c t fe in () = f cr pole c in in in () 1 2 where c g f rr h g g is the in m t in fe m m , , === 2 f cr r pole c in be in in () (||) = 1 2 f mhz pole amp () ? 1 faf crossover v ldo pole ldo = () () f cr pole lr lr load () = 1 2 r v i be be bias = a v ih i v vlr t bias fe load ref () ? ? ? ? ? ? + ? ? ? ? ? ? 4 1
4) next, calculate the pole set by each linear regula- tor s feedback resistance and the capacitance (c fbl_ ) between fbl_ and agnd (approximately 5pf including stray capacitance): 5) next, calculate the zero caused by the output capacitor s esr: where r esr is the equivalent series resistance of c lr . 6) to ensure stability, choose c lr large enough so that the crossover occurs well before the poles and zero calculated in steps 2) to 5). the poles in steps 3) and 4) generally occur at several megahertz and using ceramic capacitors ensures the esr zero occurs at several megahertz as well. placing the crossover below 500khz is sufficient to avoid the amplifier-delay pole and generally works well, unless unusual component choices or extra capacitances move the other poles or zero below 1mhz. pc board layout and grounding careful pc board layout is important for proper opera- tion. use the following guidelines for good pc board layout: 1) place the high-power components of the step-down regulator (input capacitors, mosfets, inductor, and output capacitors) first, with any grounded connections adjacent. connect these components with short, wide traces. avoid using vias in the high-current paths. if vias are unavoidable, use many vias in parallel to reduce resistance and inductance. 2) create islands for the analog ground (agnd), power ground (pgnd), and individual linear regula- tor grounds. connect all these ground areas (islands) together at only one location, which is a via connected to the backside pad of the device. all voltage-feedback dividers should be connected to the analog ground island. the step-down regula- tor s input and output capacitors, and the charge pump components should be a wide power ground plane. the power ground plane should be connect- ed to the power ground pin (pgnd) with a wide trace. maximizing the width of the power ground traces improves efficiency, and reduces output voltage ripple and noise spikes. all other ground connections, such as the vl and in pin bypass capacitor and the linear regulator output capaci- tors, should be star-connected to the backside of the device with wide traces. make no other connec- tions between these separate ground planes. 3) place the in pin and vl pin bypass capacitors within 5mm from the ic and connect them to their respective pins with short, direct connections. 4) since both mosfets are used for current sensing, care must be taken to ensure that noise and dc errors do not corrupt the sense signals. place both mosfets close to the ic. connect pgnd to the source of the low-side mosfet with a short, wide trace. connect dl to the gate of the low-side mos- fet with a short, wide trace. ensure that the traces from dl to low-side mosfet to pgnd total no more than 50 squares. connect lx close to the connection point between the low-side and high- side mosfets with a short, wide trace. connect dh to the gate of the high-side mosfet with a short, wide trace. ensure that the traces from dh to high-side mosfet to lx total no more than 50 squares (50 squares corresponds to 20 mils wide if the total trace is 1in long). 5) place all feedback voltage-divider resistors as close to their respective feedback pins as possible. the divider s center trace should be kept short. placing the resistors far away causes their fb traces to become antennas that can pick up switching noise. care should be taken to avoid run- ning any feedback trace near lx or the switching nodes in the charge pumps. 6) minimize the length and maximize the width of the traces between the output capacitors and the load for best transient responses. 7) minimize the size of the lx node while keeping it wide and short. keep the lx node away from feed- back nodes and analog ground. use dc traces as shield if necessary. f cr esr zero lr esr _ = 1 2 f crr f crr f crr f crr and f crr pole fbl fbl pole fbl fbl pole fbl fbl pole fbl fbl pole fbl fbl () () () () () (|| ) (||) (||) (||) (||) 1 1 2 2 3 3 4 4 5 5 1 2910 1 21819 1 22526 1 22223 1 22829 = = = = = max1530/max1531 multiple-output power-supply controllers for lcd monitors ______________________________________________________________________________________ 31
max1530/max1531 multiple-output power-supply controllers for lcd monitors 32 ______________________________________________________________________________________ thin qfn 32 31 30 29 28 27 26 drv1 fbl1 en agnd vl in freq 25 seq 9 10 11 12 13 14 15 fbl5* drv5* rstin reset comp fb ilim 16 onl2 17 18 19 20 21 22 23 onl3 onl4* onl5* pgnd dl lx dh 8 7 6 5 4 3 2 drv4* * = n.c. for max1530 fbl4* csl* csh* drv3 fbl3 fbl2 max1530 max1531 1 drv2 24 bst pin configuration chip information transistor count: 5600 process: bicmos
multiple-output power-supply controllers for lcd monitors maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 33 ? 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. max1530/max1531 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) qfn thin.eps d2 (nd-1) x e e d c pin # 1 i.d. (ne-1) x e e/2 e 0.08 c 0.10 c a a1 a3 detail a 0.15 c b 0.15 c a document control no. 21-0140 package outline 16, 20, 28, 32l, qfn thin, 5x5x0.8 mm proprietary information approval title: c rev. 2 1 e2/2 e2 0.10 m c a b pin # 1 i.d. b 0.35x45 l d/2 d2/2 l c l c e e l cc l k k l l 2 2 21-0140 rev. document control no. approval proprietary information title: common dimensions exposed pad variations 1. dimensioning & tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. angles are in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 6. nd and ne refer to the number of terminals on each d and e side respectively. 7. depopulation is possible in a symmetrical fashion. 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 9. drawing conforms to jedec mo220. notes: 10. warpage shall not exceed 0.10 mm. c package outline 16, 20, 28, 32l, qfn thin, 5x5x0.8 mm

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