View MT2LG25664KHG-10_7242436.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 256k, 512k x 64 sgram sodimms micron technology, inc., reserves the right to change products or specifications without notice. gm01.p65 C rev. 2/99 ? 1999, micron technology, inc. 256k, 512k x 64 sgram sodimms obsolete sgram component key timing parameters module speed access setup hold marking grade time time time -25 7ns 6ns 2ns 1ns -10 8ns 6.5ns 2.5ns 1ns -83 10ns 9ns 3ns 1ns synchronous graphics ram sodimm features ? jedec pinout in a 144-pin, small-outline, dual in-line memory module (sodimm) ? 2mb (256k x 64) and 4mb (512k x 64) ? fully synchronous; all signals registered on positive edge of system clock ? single +3.3v 0.3v power supply ? lvttl-compatible inputs and outputs ? internal pipelined operation; column address can be changed every clock cycle ? programmable burst lengths: 1, 2, 4, 8 or full page ? block write and write-per-bit modes ? independent byte operation via dqm0-dqm7 ? auto precharge and auto refresh modes ? 17ms, 1,024-cycle refresh ? optional serial presence-detect (spd) options marking ? frequency 125 mhz -25 100 mhz -10 83 mhz -83 ? spd with spd none without spd k ? package 144-pin sodimm (gold) g pin assignment (front view) mt2lg25664(k)h, mt4lg51264(k)h for the latest full-length data sheet, please refer to the micron web site: www.micron.com/mti/msp/html/ datasheet.html note: pin symbols in parentheses are not used on these modules but may be used for other modules in this product family. they are for reference only. part numbers part number configuration options mt2lg25664hg-xx 256k x 64 spd mt2lg25664khg-xx 256k x 64 mt4lg51264hg-xx 512k x 64 spd mt4lg51264khg-xx 512k x 64 xx = frequency pin front pin back pin front pin back 1v ss 2v ss 73 nc/clk1* 74 clk0 3 dq63 4 dq62 75 v dd 76 v dd 5 dq61 6 dq60 77 rsvd 78 rsvd 7 dq59 8 dq58 79 nc (a11) 80 nc (a10) 9 dq57 10 dq56 81 ba0 (a9) 82 a8 11 v dd 12 v dd 83 a7 84 a6 13 dq55 14 dq54 85 v ss 86 v ss 15 dq53 16 dq52 87 a5 88 a4 17 dq51 18 dq50 89 a3 90 a2 19 dq49 20 dq48 91 a1 92 a0 21 v ss 22 v ss 93 v dd 94 v dd 23 dqmb7 24 dqmb6 95 dq31 96 dq30 25 dqmb5 26 dqmb4 97 dq29 98 dq28 27 v dd 28 v dd 99 dq27 100 dq26 29 dq47 30 dq46 101 dq25 102 dq24 31 dq45 32 dq44 103 v ss 104 v ss 33 dq43 34 dq42 105 dq23 106 dq22 35 dq41 36 dq40 107 dq21 108 dq20 37 v ss 38 v ss 109 dq19 110 dq18 39 dq39 40 dq38 111 dq17 112 dq16 41 dq37 42 dq36 113 v dd 114 v dd 43 dq35 44 dq34 115 dqmb3 116 dqmb2 45 dq33 46 dq32 117 dqmb1 118 dqmb0 47 v dd 48 v dd 119 v ss 120 v ss 49 rsvd 50 rsvd 121 dq15 122 dq14 51 rsvd 52 rsvd 123 dq13 124 dq12 53 rsvd 54 rsvd 125 dq11 126 dq10 55 v ss 56 v ss 127 dq9 128 dq8 57 dsf 58 rfu 129 v dd 130 v dd 59 rfu 60 rfu 131 dq7 132 dq6 61 rfu 62 sa0/nc** 133 dq5 134 dq4 63 v dd 64 v dd 135 dq3 136 dq2 65 nc/cs1#* 66 cs0# 137 dq1 138 dq0 67 ras# 68 cas# 139 v ss 140 v ss 69 we# 70 cke 141 sda/nc** 142 scl/nc** 71 v ss 72 v ss 143 v dd 144 v dd * 4mb version only ** k version only 144-pin small-outline dimm (i-7; 2mb) (i-6; 4mb) micron is a registered trademark of micron technology, inc.
2 256k, 512k x 64 sgram sodimms micron technology, inc., reserves the right to change products or specifications without notice. gm01.p65 C rev. 2/99 ? 1999, micron technology, inc. 256k, 512k x 64 sgram sodimms obsolete general description the mt2lg25664(k)h and mt4lg51264(k)h sgram modules are high-speed cmos, dynamic random-access 2mb and 4mb memories organized in a small-outline, x64 configuration. read and write accesses to the modules are burst ori- ented; accesses start at a selected location and continue for a programmed number of locations in a programmed se- quence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba selects the bank, a0-a8 select the row). then the address bits registered coincident with the read or write command are used to select the starting column location for the burst access. these modules provide for programmable read or write burst lengths of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. the modules use an internal pipelined architecture to achieve high-speed operation. this architecture is compat- ible with the 2 n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. precharging one bank while accessing the alternate bank will hide the precharge cycles and provide seamless, high-speed, random-access operation. synchronous graphics rams (sgrams) differ from syn- chronous drams (sdrams) by providing an eight- column block write function and a masked write (or write-per-bit) function to accommodate high- performance graphics applications. the block write and masked write functions may be combined with individual byte enables (dq mask or dqm pins). the cmos dynamic memory structure of these modules is designed to operate in 3.3v, low-power memory systems. an auto refresh mode is provided, along with a power-saving, power-down mode. all inputs and outputs are lvttl-compatible. (refer to the mt41lc256k32d4 sgram data sheet for additional information on sgram functionality.) resistor strapping detection three resistor straps are used to indicate the module frequency and timing. table 1 shows the settings. a logic low (i.e., 0) indicates that the strapping resistor is tied to ground (v ss ). a logic high (i.e., 1) indicates that the strapping resistor is tied to v dd . table 1 module frequency dq31 dq30 dq29 125 mhz 0 1 1 100 mhz 0 1 0 83 mhz 0 0 1 serial presence-detect operation these modules can also incorporate serial presence- detect (spd). the spd function is implemented using a 2,048-bit eeprom. this nonvolatile storage device con- tains 256 bytes. the first 128 bytes can be programmed by micron to identify the module type and various dram organizations and timing parameters. the remaining 128 bytes of storage are available for use by the customer. system read/write operations between the master (sys- tem logic) and the slave eeprom device (dimm) occur via a standard iic bus using the dimms scl (clock) and sda (data) signals, together with sa(0), which provide two unique dimm/eeprom addresses.
3 256k, 512k x 64 sgram sodimms micron technology, inc., reserves the right to change products or specifications without notice. gm01.p65 C rev. 2/99 ? 1999, micron technology, inc. 256k, 512k x 64 sgram sodimms obsolete functional block diagram mt2lg25664(k)h (2mb) 9 cas# cs0# clk0 ba0 dsf we# a0-a8 ras# dq0-dq31 9 dqmb0-dqmb3 dq32-dq63 dqmb4-dqmb7 cke u0-u1 = mt41lc256k32d4 36 36 a0 sa0 spd scl sda a1 a2 v dd v ss u0-u1 u0-u1 cke dsf cas# ras# we# cs# clk ba u0 a0?8 dq0-dq31 dqm0-dqm3 a0?8 cke dsf cas# ras# we# cs# clk ba dq0-dq31 dqm0-dqm3 u1
4 256k, 512k x 64 sgram sodimms micron technology, inc., reserves the right to change products or specifications without notice. gm01.p65 C rev. 2/99 ? 1999, micron technology, inc. 256k, 512k x 64 sgram sodimms obsolete functional block diagram mt4lg51264(k)h (4mb) u0-u3 = mt41lc256k32d4 9 cas# cs0# clk0 ba0 dsf we# cs1# a0-a8 ras# dq0-dq31 9 9 9 dqmb0-dqmb3 dq32-dq63 dqmb4-dqmb7 dq0-dq31 dqmb0-dqmb3 dq32-dq63 dqmb4-dqmb7 cke clk1 . . . 36 36 36 36 a0 spd scl sda a1 a2 v dd v ss u0-u3 u0-u3 sa0 note : all resistor values are 10 ohms unless otherwise specified. cke dsf cas# ras# we# cs# clk ba u0 a0?8 u1 a0?8 u2 a0?8 u3 a0?8 dq0-dq31 dqm0-dqm3 dq0-dq31 dqm0-dqm3 dq0-dq31 dqm0-dqm3 dq0-dq31 dqm0-dqm3 cke dsf cas# ras# we# cs# clk ba cke dsf cas# ras# we# cs# clk ba cke dsf cas# ras# we# cs# clk ba
5 256k, 512k x 64 sgram sodimms micron technology, inc., reserves the right to change products or specifications without notice. gm01.p65 C rev. 2/99 ? 1999, micron technology, inc. 256k, 512k x 64 sgram sodimms obsolete pin descriptions pin numbers symbol type description 74, 73 clk0, clk1 input clock: clk is driven by the system clock. all sgram input signals are sampled on the positive edge of clk. clk also increments the internal burst counter and controls the output registers. 70 cke input clock enable: cke activates (high) and deactivates (low) the clk signal. after both banks are precharged, deactivating the clock provides power-down mode and self refresh mode. cke is synchronous except after the device enters power-down and self refresh modes, where cke becomes asynchronous until after exiting the same mode. the input buffers, including clk, are disabled during power-down and self refresh modes, providing low standby power. cke may be tied high. 66, 65 cs0#, cs1# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands are masked when cs# is registered high. cs# provides for external bank selection on systems with multiple banks. cs# is considered part of the command code. 67-69, 57 ras#, cas# input command inputs: ras#, we#, cas# and dsf define the command being we#, dsf entered. 23-26, 115-118 dqmb0- input input/output mask: dqmb0-dqmb3 are byte-specific, nonpersistent i/o dqmb7 buffer controls. the i/o buffers are placed in a high-z state when dqmb is sampled high. input data is masked when dqmb is sampled high during a write cycle. output data is masked (two-clock latency) when dqmb is sampled high during a read cycle. dqmb0 masks dq0-dq7, dqmb1 masks dq8-dq15, dqmb2 masks dq16-dq23, and dqmb3 masks dq24-dq31. this pattern repeats for the remaining dqmbs. 81 ba0 input bank address: ba0 defines to which bank the active, read, write or precharge command is being applied. ba0 is also used to program the tenth bit of the mode and special mode registers. 82-84, 87-92 a0-a8 input address inputs: a0-a8 are sampled during the active command (row- address a0-a8) and read/write command (column-address a0-a7, with a8 defining auto precharge) to select one location out of the memory array available in the respective bank. a8 is sampled during a precharge command to determine if both banks are to be precharged (a8 high). the address inputs also provide the op-code during a load mode register or load special mode register command. 3-10, 13-20, dq0-dq63 input/ data i/o: data bus. the i/os are byte-maskable during reads and 29-36, 39-46, output writes.the dqs also serve as column/byte mask inputs during block 95-102, 105-112, writes. 121-128, 131-138 141 sda input/ serial presence-detect data. sda is a bidirectional pin used to transfer output addresses and data into and out of the presence-detect portion of the module. 142 scl input serial clock for presence-detect. scl is used to synchronize the presence-detect data transfer to and from the module. 62 sa0 input presence-detect address input. this pin is used to configure the presence-detect device.
6 256k, 512k x 64 sgram sodimms micron technology, inc., reserves the right to change products or specifications without notice. gm01.p65 C rev. 2/99 ? 1999, micron technology, inc. 256k, 512k x 64 sgram sodimms obsolete pin descriptions (continued) pin numbers symbol type description 11, 12, 27, 28, 47, v dd supply power supply: +3.3v 0.3v. 48, 63, 64, 75, 76, 93, 94, 113, 114, 129, 130,143, 144 1, 2, 21, 22, 37, v ss supply ground. 38, 55, 56, 71, 72, 85, 86, 103, 104, 119, 120, 139, 140 58-61 rfu C reserved for future use: these pins should be left unconnected. 49-54, 77, 78 rsvd C rsvd: these pins are reserved.
7 256k, 512k x 64 sgram sodimms micron technology, inc., reserves the right to change products or specifications without notice. gm01.p65 C rev. 2/99 ? 1999, micron technology, inc. 256k, 512k x 64 sgram sodimms obsolete spd acknowledge acknowledge is a software convention used to indicate successful data transfers. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data (figure 3). the spd device will always respond with an acknowl- edge after recognition of a start condition and its slave address. if both the device and a write operation have been selected, the spd device will respond with an ac- knowledge after the receipt of each subsequent eight-bit word. in the read mode the spd device will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. spd clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions (figures 1 and 2). spd start condition all commands are preceded by the start condition, which is a high-to-low transition of sda when scl is high. the spd device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. spd stop condition all communications are terminated by a stop condition, which is a low-to-high transition of sda when scl is high. the stop condition is also used to place the spd device into standby power mode. scl from master data output from transmitter data output from receiver 9 8 acknowledge figure 3 acknowledge response from receiver figure 1 data validity figure 2 definition of start and stop scl sda data stable data stable data change scl sda start bit stop bit
8 256k, 512k x 64 sgram sodimms micron technology, inc., reserves the right to change products or specifications without notice. gm01.p65 C rev. 2/99 ? 1999, micron technology, inc. 256k, 512k x 64 sgram sodimms obsolete functional block diagram mt4lg51264h (4mb) u0-u3 = mt41lc256k32d4 9 cas# cs0# clk0 ba0 dsf we# cs1# a0-a8 ras# dq0-dq31 9 9 9 dqmb0-dqmb3 dq32-dq63 dqmb4-dqmb7 dq0-dq31 dqmb0-dqmb3 dq32-dq63 dqmb4-dqmb7 cke clk1 . . . 36 36 36 36 a0 spd scl sda a1 a2 v dd v ss u0-u3 u0-u3 sa0 note : all resistor values are 10 ohms unless otherwise specified. cke dsf cas# ras# we# cs# clk ba u0 a0?8 u1 a0?8 u2 a0?8 u3 a0?8 dq0-dq31 dqm0-dqm3 dq0-dq31 dqm0-dqm3 dq0-dq31 dqm0-dqm3 dq0-dq31 dqm0-dqm3 cke dsf cas# ras# we# cs# clk ba cke dsf cas# ras# we# cs# clk ba cke dsf cas# ras# we# cs# clk ba
9 256k, 512k x 64 sgram sodimms micron technology, inc., reserves the right to change products or specifications without notice. gm01.p65 C rev. 2/99 ? 1999, micron technology, inc. 256k, 512k x 64 sgram sodimms obsolete serial presence-detect matrix byte description entry (version) symbol bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex 0 number of bytes used by micron 128 10000000 80 1 total number of spd memory bytes 256 00001000 08 2 memory type sgram 00000110 06 3 number of row addresses 9 00001001 09 4 number of column addresses 8 00001000 08 5 number of banks 1 (2mb) 00000001 01 2 (4mb) 00000010 02 6 module data width 64 01000000 40 7 module data width (continued) 0 00000000 00 8 module voltage interface levels lvttl 00000001 01 9 sgram cycle time 7 (-25) t ck 01110000 70 (cas latency = 3) 8 (-10) 10000000 80 10 (-83) 10100000 a0 10 sgram access from clk 6 (-25) t ac 01100000 60 (cas latency = 3) 6.5 (-10) 01100101 65 9 (-83) 10010000 90 11 module configuration type nonparity 00000000 00 12 refresh rate/type 15.6 m s/self 10000000 80 13 sgram width (primary sgram) 32 00100000 20 14 error checking sgram data width 0 00000000 00 15 min. clock delay from back-to-back 1 t ccd 00000001 01 random column addresses 16 burst lengths supported 1, 2, 4, 8, page 10001111 8f 17 number of banks on sgram device 2 00000010 02 18 cas latencies supported 2, 3 00000110 06 19 cs latency 0 00000001 01 20 we latency 0 00000001 01 21 sgram module attributes nonbuffered 00000000 00 22 sgram device attributes: general ce 11001110 ce 23 sgram cycle time 12 (-25) t ck 11000000 c0 (cas latency = 2) 12 (-10) 11000000 c0 15 (-83) 11110000 f0 24 sgram access from clk 6 (-25) t ac 01100000 60 (cas latency = 2) 6.5 (-10) 01100101 65 9 (-83) 10010000 90 25 sgram cycle time C t ck 00000000 00 (cas latency = 1) 26 sgram access from clk C t ac 00000000 00 (cas latency = 1) 27 minimum row precharge time ( t rp) 21 (-25) t rp 00010101 15 24 (-10) 00011000 18 30 (-83) 00011110 1e 28 minimum row active to row active 14 (-25) t rrd00001110 0e 16 (-10) 00010000 10 20 (-83) 00010100 14 note: 1. 1/0: serial data, driven to high/driven to low.
10 256k, 512k x 64 sgram sodimms micron technology, inc., reserves the right to change products or specifications without notice. gm01.p65 C rev. 2/99 ? 1999, micron technology, inc. 256k, 512k x 64 sgram sodimms obsolete serial presence-detect matrix (continued) byte description entry (version) symbol bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex 29 minimum ras# to cas# delay 20 (-25) t rcd 00010100 14 20 (-10) 00010100 14 24 (-83) 00011000 18 30 minimum ras# pulse width 49 (-25) t ras 00110001 31 56 (-10) 00111000 38 60 (-83) 00111110 3c 31 module bank density 2mb 10000000 80 32 address and command setup time 2 (-25) t as, 00100000 20 2.5 (-10) t cms 00100101 25 3 (-83) 00110000 30 33 address and command hold time 1 t ah, t cmh00010000 10 34 data input setup time 2 (-25) t ds 00100000 20 2.5 (-10) 00100101 25 3 (-83) 00110000 30 35 data input hold time 1 t dh 00010000 10 36 block write columns supported 8 00000011 03 37-61 reserved 00000000 00 62 spd revision rev. 0 00000000 00 63 checksum for bytes 0-62 2mb -25 00100001 21 2mb -10 01010001 51 2mb -83 00011111 1f 4mb -25 00100010 22 4mb -10 01010010 52 4mb -83 00100000 20 64 manufacturer's jedec id code micron 00101100 2c 65-71 manufacturer's jedec id code (cont.) 11111111 ff 72 manufacturing location 00000001 01 00000010 02 00000011 03 00000100 04 73-90 module part number (ascii) xxxxxxxx x 91 pcb revsion code a 00000001 01 b 00000010 02 c 00000011 03 d 00000100 04 92 revision code (cont.) 0 00000000 00 93 year of manufacture in bcd xxxxxxxx x 94 week of manufacture in bcd xxxxxxxx x 95-98 module serial number xxxxxxxx x 99-127 manufacture specific data (rsvd) CCCCCCCC C note: 1. 1/0: serial data, driven to high/driven to low. 2. x = variable data.
11 256k, 512k x 64 sgram sodimms micron technology, inc., reserves the right to change products or specifications without notice. gm01.p65 C rev. 2/99 ? 1999, micron technology, inc. 256k, 512k x 64 sgram sodimms obsolete absolute maximum ratings* voltage on v dd supply relative to v ss .......... -1v to +4.6v voltage on inputs or i/o pins relative to v ss ................................................ -1v to +4.6v operating temperature, t a (ambient) .......... 0 c to +70 c storage temperature (plastic) .................... -55 c to +125 c power dissipation ............................................................. 2w *stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics and operating conditions (note: 1) (v dd = +3.3v 0.3v) parameter/condition symbol min max units notes supply voltage v dd 3.0 3.6 v input high voltage: logic 1; all inputs v ih 2.0 v dd + 0.3 v 18 input low voltage: logic 0; all inputs v il -0.3 0.8 v 18 input leakage current: cs0#-cs1#, clk0-clk1, i i 1 -4 4 m a any input 0v v in v dd dqmb0-dqmb7 (all other pins not under test = 0v) all other inputs i i 2 -8 8 m a14 output leakage current: dqs are disabled; 0v v out v dd i oz -10 10 m a14 output levels: v oh 2.4 C v output high voltage (i out = -2ma) output low voltage (i out = 2ma) v ol C 0.4 v icc specifications and maximum limits (notes: 1, 8, 13) (v dd = +3.3v 0.3v) parameter/condition symbol size -25 -10 -83 units notes standby current: power-down mode; i cc 1 2mb 4 4 4 ma cke v il (max); both banks idle 4mb 8 8 8 standby current: cs# 3 v ih (min); i cc 2 2mb 130 110 100 ma 3, 4 t ck 3 t ck (min); cke 3 v ih (min); both banks idle 4mb 260 220 200 standby current: cs# 3 v ih (min); t ck 3 t ck (min); i cc 3 2mb 150 130 120 ma 3, 4 cke 3 v ih (min); both banks active after t rcd met 4mb 300 260 240 auto refresh current: i cc 4 2mb 340 280 240 ma 4 t rc = t rc (min) 4mb 680 560 480 operating current: active mode; i cc 5 2mb 360 320 290 ma 3, 4 burst = 2; read or write; t rc 3 t rc (min); one bank active 4mb 364 324 294 operating current: active mode; i cc 6 2mb 600 520 440 ma 3, 4 burst = 2; read or write; t rc 3 t rc (min); two banks active 4mb 604 524 444 operating current: burst mode; 2mb 460 400 360 full-page burst after t rcd met read or write; i cc 7 ma 3, 4 t ck 3 t ck (min); other bank idle 4mb 464 404 364 operating current: block write; i cc 8 2mb 350 320 290 ma 3, 4 t ck 3 t ck (min); t bwc 3 t bwc (min); one bank active 4mb 354 324 294 max
12 256k, 512k x 64 sgram sodimms micron technology, inc., reserves the right to change products or specifications without notice. gm01.p65 C rev. 2/99 ? 1999, micron technology, inc. 256k, 512k x 64 sgram sodimms obsolete capacitance parameter symbol 2mb 4mb units notes input capacitance: a0-a8, ba0 c i 1 12 24 pf 2 input capacitance: ras#, cas#, we#, cke, dsf c i 2 14 28 pf 2 input capacitance: cs0#, cs1#, clk0, clk1 c i 3 14 14 pf 2 input capacitance: dqmb0-dqmb7 c i 4 816pf2 input capacitance: scl, sa0 c i 5 66pf2 input/output capacitance: dq0-dq63, sda c io 918pf2 sgram component* ac electrical characteristics (notes: 6, 7, 8, 9, 10, 12, 19) listed alphabetically by symbol subscript. ac characteristics -25 -10 -83 parameter symbol min max min max min max units notes access time from clk (positive edge) t ac 6 6.5 9 ns address hold time t ah111ns address setup time t as 2 2.5 3 ns block write to precharge delay t bpl 3 3 3 t ck block write cycle time t bwc 2 2 2 t ck clk high level width t ch 3 3 3.5 ns system clock cycle time cl = 3 t ck 7 8 10 ns cl = 2 t ck 12 12 15 ns cke hold time t ckh 1 1 1 ns cke setup time t cks 2.5 2.5 3 ns clk low level width t cl 3 3 3.5 ns cs#, ras#, cas#, we#, dsf, dqm hold time t cmh 1 1 1 ns cs#, ras#, cas#, we#, dsf, dqm setup time t cms 2 2.5 3 ns data-in hold time t dh111ns data-in setup time t ds 2 2.5 3 ns data-out high-impedance time t hz 6 6.5 10 ns 11 data-out low-impedance time t lz112ns load mode register t mrd 2 2 2 t ck command to active or refresh command data-out hold time t oh 2.5 3 3 ns active to precharge command period t ras 49 120,000 56 120,000 60 120,000 ns auto refresh and active to t rc 70 80 90 ns active command period active to read, write or block write delay t rcd 20 20 24 ns refresh period (1,024 cycles) t ref 17 17 17 ms precharge command period t rp 21 24 30 ns active bank a to active bank b command period t rrd 14 16 20 ns load special mode register t sml 2 2 2 t ck command to active or refresh command transition time t t 1 30 1 30 1 30 ns write recovery time t wr222 t ck 16 12 15 15 ns 17 exit self refresh to active command t xsr 80 90 90 ns *specifications for the sgram components used on the modules. max
13 256k, 512k x 64 sgram sodimms micron technology, inc., reserves the right to change products or specifications without notice. gm01.p65 C rev. 2/99 ? 1999, micron technology, inc. 256k, 512k x 64 sgram sodimms obsolete serial presence-detect eeprom ac electrical characteristics (notes: 1) (v dd = +3.3v 0.3v) parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.3 3.5 m s time the bus must be free before a new transition can start t buf 4.7 m s data-out hold time t dh 300 ns sda and scl fall time t f 300 ns data-in hold time t hd:dat 0 m s start condition hold time t hd:sta 4 m s clock high period t high 4 m s noise suppression time constant at scl, sda inputs t i 100 ns clock low period t low 4.7 m s sda and scl rise time t r1 m s scl clock frequency t scl 100 khz data-in setup time t su:dat 250 ns start condition setup time t su:sta 4.7 m s stop condition setup time t su:sto 4.7 m s write cycle time t wrc 10 ms 15 serial presence-detect eeprom dc operating conditions (notes: 1) (v dd = +3.3v 0.3v) parameter/condition symbol min max units notes supply voltage v dd 3 3.6 v input high voltage: logic 1; all inputs v ih v dd 0.7 v dd + 0.5 v input low voltage: logic 0; all inputs v il -1 v dd 0.3 v output low voltage: i out = 3ma v ol C 0.4 v input leakage current: v in = gnd to v dd i li C10 m a output leakage current: v out = gnd to v dd i lo C10 m a standby current: i sb C30 m a scl = sda = v dd - 0.3v; all other inputs = gnd or 3.3v +10% power supply current: i cc C2ma scl clock frequency = 100 khz
14 256k, 512k x 64 sgram sodimms micron technology, inc., reserves the right to change products or specifications without notice. gm01.p65 C rev. 2/99 ? 1999, micron technology, inc. 256k, 512k x 64 sgram sodimms obsolete 11. t hz defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 12. ac timing tests have v il = 0v and v ih = 3v, with timing referenced to 1.4v crossover point. 13. i cc specifications are tested after the device is properly initialized. 14. 2mb module values will be half of those shown. 15. the spd eeprom write cycle time ( t wrc) is the time from a valid stop condition to a write sequence to the end of the eeprom internal erase/program cycle. during the write cycle, the eeprom bus interface circuit is disabled. sda remains high due to the pull-up resistor, and the eeprom does not respond to its slave address. 16. auto precharge mode. 17. precharge mode. 18. v ih overshoot: v ih (max) = v dd q + 2v for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate. v il undershoot: v il (min) = -2v for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate. 19. the clock frequency must remain constant during access or precharge states (read, write, including t wr, and precharge commands). cke may be used to reduce the data rate. notes 1. all voltages referenced to v ss . 2. this parameter is sampled. v dd = +3.3v; f = 1 mhz. 3. i cc is dependent on cycle rates. 4. i cc is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. other inputs are allowed to transition no more than once in any 30ns period and are otherwise at valid v ih or v il levels. 5. enables on-chip refresh and address counters. 6. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0 c t a 70 c) is ensured. 7. an initial pause of 100 m s is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. the two auto refresh command wake-ups should be repeated any time the t ref refresh requirement is exceeded. 8. ac characteristics assume t t = 1ns. 9. in addition to meeting the transition rate specifica- tion, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 10. outputs measured at 1.4v with equivalent load: q 50 w 1.4v 30pf
15 256k, 512k x 64 sgram sodimms micron technology, inc., reserves the right to change products or specifications without notice. gm01.p65 C rev. 2/99 ? 1999, micron technology, inc. 256k, 512k x 64 sgram sodimms obsolete scl sda in sda out t low t su:sta t hd:sta t f t high t r t buf t dh t aa t su:sto t su:dat t hd:dat undefined serial presence-detect eeprom timing parameters symbol min max units t aa 0.3 3.5 m s t buf 4.7 m s t dh 300 ns t f 300 ns t hd:dat 0 m s t hd:sta 4 m s spd eeprom symbol min max units t high 4 m s t low 4.7 m s t r1 m s t su:dat 250 ns t su:sta 4.7 m s t su:sto 4.7 m s
16 256k, 512k x 64 sgram sodimms micron technology, inc., reserves the right to change products or specifications without notice. gm01.p65 C rev. 2/99 ? 1999, micron technology, inc. 256k, 512k x 64 sgram sodimms obsolete 144-pin sodimm i-7 .115 (2.92) max .043 (1.10) .035 (0.90) pin 1 2.667 (67.75) 2.656 (67.45) .787 (20.00) typ .071 (1.80) (2x) 2.386 (60.60) .0315 (.80) typ .130 (3.30) (2x) .024 (.60) typ .079 (2.00) r (2x) pin 143 (pin 144 on backside) .157 (4.00) front view .079 (2.00) .236 (6.00) 2.504 (63.60) .100 (2.55) .059 (1.50) typ 1.156 (29.36) 1.144 (29.06) note: 1. all dimensions in inches (millimeters) max or typical where noted. min 144-pin sodimm i-6 .170 (4.32) max .043 (1.10) .035 (0.90) pin 1 2.667 (67.75) 2.656 (67.45) .071 (1.80) (2x) 2.386 (60.60) .0315 (.80) typ .130 (3.30) (2x) .024 (.60) typ .079 (2.00) r (2x) pin 143 (pin 144 on backside) front view .079 (2.00) .236 (6.00) 2.504 (63.60) .100 (2.55) .059 (1.50) typ 1.156 (29.36) 1.144 (29.06) .787 (20.00) typ .157 (4.00)

▲Up To Search▲

Price & Availability of MT2LG25664KHG-10

	To Download MT2LG25664KHG-10 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .