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? products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by micron without notice. products are only warranted by micron to meet micron?s production data sheet specifications. 128meg (x72) 184-pin registered quad-bank ddrsdram dimm dd36c128_256x72dg_c.fm - rev. c 7/03 en 1 ?2003 micron technology, inc. all rights reserved. 1gb, 2gb (x72, ecc) 184-pin registered ddr sdram dimm registered quad-rank ddr sdram dimm mt36vdds12872d ? 1gb (advance ? ), mt36vddt12872d ? 1gb, mt36vdds25672d ? 2gb (advance ? ) , mt36vddt25672d ? 2gb for the latest data sheet, please refer to the micron web site: www.micron.com/moduleds features ? 184-pin, dual in-line memory modules (dimm), organized as four module ranks fast data transfer rates: pc1600 and pc2100 utilizes 200 mt/s and 266 mt/s twindie ddr or stacked tsop ddr sdram components ecc, 1-bit error detection and correction low-profile pcb design registered inputs with one-clock delay phase-lock loop (pll) clock driver to minimize loading 1gb (128 meg x 72) and 2gb (256 meg x 72) 2.5v i/o (sstl_2 compatible) v dd = v dd q= +2.5v v ddspd = +2.3v to +3.6v commands entered on each positive ck edge dqs edge-aligned with data for reads; center- aligned with data for writes internal, pipelined double data rate (ddr) architecture; two data accesses per clock cycle bidirectional data strobe (dqs) transmitted/ received with data, i.e., source-synchronous data capture differential clock inputs (ck and ck#) four internal device banks for concurrent operation selectable burst lengths: 2, 4, or 8 auto precharge option auto refresh and self refresh modes 7.8125s maximum average periodic refresh interval serial presence detect (spd) with eeprom selectable read cas latency gold edge connectors figure 1: 184-pin low profile dimm (mo-206) note: 1. cl = device cas (read) latency; registered mode adds one clock cycle to cl due to the input register. 2. contact factory for availability. options marking package 184-pin dimm (standard) g 184-pin dimm (lead-free) y memory clock/data frequency, cas latency 1 7.5ns (133 mhz)/266 mt/s, cl = 2 -262 2 7.5ns (133 mhz)/266 mt/s, cl = 2 -26a 2 7.5ns (133 mhz)/266 mt/s, cl = 2.5 -265 2 8ns (100 mhz)/200 mt/s, cl = 2 -202 2 table 1: address table mt36vdds12872d mt36vddt12872d mt36vdds25672d mt36vddt25672d refresh count 8k 8k 8k 8k row addressing 8k (a0?a12) 8k (a0?a12) 8k (a0?a12) 8k (a0?a12) device bank addressing 4 (ba0, ba1) 4 (ba0, ba1) 4 (ba0, ba1) 4 (ba0, ba1) base device configuration 32 meg x 8 32 meg x 8 64 meg x 8 64 meg x 8 column addressing 1k (a0?a9) 1k (a0?a9) 2k (a0?a9, a11) 2k (a0?a9, a11) module rank addressing 4 (s0#-s3#) 4 (s0#-s3#) 4 (s0#-s3#) 4 (s0#-s3#)
1gb, 2gb (x72, ecc) 184-pin registered ddr sdram dimm 128meg (x72) 184-pin registered quad-bank ddrsdram dimm micron technology, inc., reserves the right to change products or specif ications without notice. dd36c128_256x72dg_c.fm - rev. c 7/03 en 2 ?2003 micron technology, inc. all rights reserved. note: all part numbers end with a two-place code (not shown), designating component and pcb revisions. consult factory for current revision codes. example: mt36vddt12872dy-265a1. table 2: part numbers and timing parameters part number module density configuration module bandwidth memoryclock/ data rate latency (cl - t rcd - t rp) mt36vdds12872dg-26a__ 1gb 128 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt36vdds12872dy-26a__ 1gb 128 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt36vdds12872dg-262__ 1gb 128 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-2-2 mt36vdds12872dy-262__ 1gb 128 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-2-2 mt36vdds12872dg-265__ 1gb 128 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 mt36vdds12872dy-265__ 1gb 128 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 mt36vdds12872dg-202__ 1gb 128 meg x 72 1.6 gb/s 10ns/200 mt/s 2-2-2 mt36vdds12872dy-202__ 1gb 128 meg x 72 1.6 gb/s 10ns/200 mt/s 2-2-2 mt36vddt12872dg-26a__ 1gb 128 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt36vddt12872dy-26a__ 1gb 128 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt36vddt12872dg-262__ 1gb 128 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-2-2 mt36vddt12872dy-262__ 1gb 128 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-2-2 mt36vddt12872dg-265__ 1gb 128 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 mt36vddt12872dy-265__ 1gb 128 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 mt36vddt12872dg-202__ 1gb 128 meg x 72 1.6 gb/s 10ns/200 mt/s 2-2-2 mt36vddt12872dy-202__ 1gb 128 meg x 72 1.6 gb/s 10ns/200 mt/s 2-2-2 mt36vdds25672dg-26a__ 2gb 256 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt36vdds25672dy-26a__ 2gb 256 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt36vdds25672dg-262__ 2gb 256 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 mt36vdds25672dy-262__ 2gb 256 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-2-2 mt36vdds25672dg-265__ 2gb 256 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-2-2 mt36vdds25672dy-265__ 2gb 256 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 mt36vdds25672dg-202__ 2gb 128 meg x 72 1.6 gb/s 10ns/200 mt/s 2-2-2 mt36vdds25672dy-202__ 2gb 128 meg x 72 1.6 gb/s 10ns/200 mt/s 2-2-2 mt36vddt25672dg-26a__ 2gb 256 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt36vddt25672dy-26a__ 2gb 256 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt36vddt25672dg-262__ 2gb 256 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-2-2 mt36vddt25672dy-262__ 2gb 256 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-2-2 mt36vddt25672dg-265__ 2gb 256 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 mt36vddt25672dg-265__ 2gb 256 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 mt36vddt25672dg-202__ 2gb 128 meg x 72 1.6 gb/s 10ns/200 mt/s 2-2-2 mt36vddt25672dy-202__ 2gb 128 meg x 72 1.6 gb/s 10ns/200 mt/s 2-2-2
1gb, 2gb (x72, ecc) 184-pin registered ddr sdram dimm 128meg (x72) 184-pin registered quad-bank ddrsdram dimm micron technology, inc., reserves the right to change products or specif ications without notice. dd36c128_256x72dg_c.fm - rev. c 7/03 en 3 ?2003 micron technology, inc. all rights reserved. figure 2: 184-pin dimm pin locations table 3: pin assignment (184-pin dimm front) pin symbol pin symbol pin symbol pin symbol 1v ref 24 dq17 47 dqs8 70 v dd 2dq0 25 dqs2 48 a0 71 s2# 3v ss 26 v ss 49 cb2 72 dq48 4 dq1 27 a9 50 v ss 73 dq49 5dqs0 28 dq18 51 cb3 74 v ss 6dq2 29 a7 52 ba1 75 dnu 7v dd 30 v dd 53 dq32 76 dnu 8dq331dq19 54 v dd 77 v dd 9nc 32 a5 55 dq33 78 dqs6 10 reset# 33 dq24 56 dqs4 79 dq50 11 v ss 34 v ss 57 dq34 80 dq51 12 dq8 35 dq25 58 v ss 81 v ss 13 dq9 36 dqs3 59 ba0 82 nc 14 dqs1 37 a4 60 dq35 83 dq56 15 v dd 38 v dd 61 dq40 84 dq57 16 dnu 39 dq26 62 v dd 85 v dd 17 dnu 40 dq27 63 we# 86 dqs7 18 v ss 41 a2 64 dq41 87 dq58 19 dq10 42 v ss 65 cas# 88 dq59 20 dq11 43 a1 66 v ss 89 v ss 21 cke0 44 cb0 67 dqs5 90 nc 22 v dd 45 cb1 68 dq42 91 sda 23 dq16 46 v dd 69 dq43 92 scl table 4: pin assignment (184-pin dimm back) pin symbol pin symbol pin symbol pin symbol 93 v ss 116 v ss 139 v ss 162 dq47 94 dq4 117 dq21 140 dqs17/dm8 163 s3# 95 dq5 118 a11 141 a10 164 v dd 96 v dd 119 dqs11/dm2 142 cb6 165 dq52 97 dqs9/dm0 120 v dd 143 v dd 166 dq53 98 dq6 121 dq22 144 cb7 167 dnu 99 dq7 122 a8 145 v ss 168 v dd 100 v ss 123 dq23 146 dq36 169 dqs15/dm6 101 nc 124 v ss 147 dq37 170 dq54 102 nc 125 a6 148 v dd 171 dq55 103 nc 126 dq28 149 dqs13/dm4 172 v dd 104 v dd 127 dq29 150 dq38 173 nc 105 dq12 128 v dd 151 dq39 174 dq60 106 dq13 129 dqs12/dm3 152 v ss 175 dq61 107 dqs10/dm1 130 a3 153 dq44 176 v ss 108 v ss 131 dq30 154 ras# 177 dqs16/dm7 109 dq14 132 v ss 155 dq45 178 dq62 110 dq15 133 dq31 156 v dd 179 dq63 111 cke1 134 cb4 157 s0# 180 v dd 112 v dd 135 cb5 158 s1# 181 sa0 113 nc 136 v dd 159 dqs14/dm5 182 sa1 114 dq20 137 ck0 160 v ss 183 sa2 115 a12 138 ck0# 161 dq46 184 v ddspd pin 1 pin 52 pin 53 pin 92 pin 93 pin 144 pin 145 pin 184 u1 u2 u3 u4 u20 u5 u6 u7 u8 u9 u22 u10 u11 u13 u14 u12 u15 u16 u17 u18 indicates a v dd or v dd q pin indicates a v ss pin front view back view low profile quad-rank u19 u21
1gb, 2gb (x72, ecc) 184-pin registered ddr sdram dimm 128meg (x72) 184-pin registered quad-bank ddrsdram dimm micron technology, inc., reserves the right to change products or specif ications without notice. dd36c128_256x72dg_c.fm - rev. c 7/03 en 4 ?2003 micron technology, inc. all rights reserved. table 5: pin descriptions pin numbers may not correlate with symbols; refer to pin assignment tables on page 3 for more information pin numbers symbol type description 1v ref input sstl_2 reference voltage. 63, 65, 154 we#, cas#, ras# input command inputs: ras#, cas#, and we# (along with s#) define the command being entered. 71, 157, 158, 163 cs0?cs4 input chip select. 137, 138 ck0, ck0# input clock: ck and ck# are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck#. output data (dqs and dqs) is referenced to the crossings of ck and ck#. 21, 111 cke0 - cke1 input clock enable: cke high activates and cke low deactivates the internal clock, input buffers and output drivers. taking cke low provides precharge power-down and self refresh operations (all device banks idle), or active power- down (row active in any device bank). cke is synchronous for power-down entry and exit, and for self refresh entry. cke is asynchronous for self refresh exit and for disabling the outputs. cke must be maintained high throughout read and write accesses. input buffers (excluding ck, ck# and cke) are disabled during power-down. input buffers (excluding cke) are disabled during self refresh. cke is an sstl_2 input but will detect an lvcmos low level after v dd is applied. 52, 59 ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an active, read, write, or precharge command is being applied. 27, 29, 32, 37, 41, 43, 48, 115, 118, 122, 125, 130, 141 a0-a12 input address inputs: provide the row address for active commands, and the column address and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective device bank. a10 sampled during a precharge command determines whether the precharge applies to one device bank (a10 low, device bank selected by ba0, ba1) or all device banks (a10 high). the address inputs also provide the op-code during a mode register set command. ba0 and ba1 define which register (mode register or extended mode register) is loaded during the load mode register command. 91 sda input/output serial presence-detect data: sda is a bidirectional pin used to transfer addresses and data into and out of the presence- detect portion of the module. 92 scl input serial clock for presence-detect: scl is used to synchronize the presence-detect data transfer to and from the module. 181, 182, 183 sa0-sa2 input presence-detect address inputs: these pins are used to configure the presence-detect device. 10 reset# input asynchronously forces all register outputs low when reset# is low. this signal can be used during power-up to ensure cke is low and sdram dqs are high-z. 44, 45, 49, 51, 134, 135, 142, 144 cb0-cb7 input/output data i/os: check bits. ecc 1-bit error detection and correction.
1gb, 2gb (x72, ecc) 184-pin registered ddr sdram dimm 128meg (x72) 184-pin registered quad-bank ddrsdram dimm micron technology, inc., reserves the right to change products or specif ications without notice. dd36c128_256x72dg_c.fm - rev. c 7/03 en 5 ?2003 micron technology, inc. all rights reserved. 5, 14, 25, 36, 47, 56, 67, 78, 86, 97, 107, 119, 129, 140, 149, 159, 169, 177 dqs0-dqs17 input/output data strobe: dqs0-dqs8, output with read data, input with write data. dqs is edge-aligned with read data, centered in write data. used to capture data. data mask: dqs9-dqs17 function as dm0-dm8 to mask write data when when high. 2, 4, 6, 8, 12, 13, 19, 20, 23, 24, 28, 31, 33, 35, 39, 40, 53, 55, 57, 60, 61, 64, 68, 69, 72, 73, 79, 80, 83, 84, 87, 88, 94, 95, 98, 99, 105, 106, 109, 110, 114, 117, 121, 123, 126, 127, 131, 133, 146, 147, 150, 151, 153, 155, 161, 162, 165, 166, 170, 171, 174, 175, 178, 179 dq0-dq63 input/ output data i/os: data bus. 7, 15, 22, 30, 38, 46, 54, 62, 70, 77, 85, 96,104, 108, 112, 120, 128, 136, 143, 148, 156, 164, 168, 172, 180 v dd supply power supply: +2.5v 0.2v. 3, 11, 18, 26, 34, 42, 50, 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176 v ss supply ground. 184 v ddspd supply serial eeprom positive power supply: +2.3v to +3.6v. 9, 82, 90, 101, 102, 103, 113, 173 nc ? no connect: these pins should be left unconnected. 16, 17, 75, 76, 167 dnu ? do not use: these pins are not connected on this module but are assigned pins on other modul es in this product family. table 5: pin descriptions pin numbers may not correlate with symbols; refer to pin assignment tables on page 3 for more information pin numbers symbol type description
1gb, 2gb (x72, ecc) 184-pin registered ddr sdram dimm 128meg (x72) 184-pin registered quad-bank ddrsdram dimm micron technology, inc., reserves the right to change products or specif ications without notice. dd36c128_256x72dg_c.fm - rev. c 7/03 en 6 ?2003 micron technology, inc. all rights reserved. figure 3: functional block diagram a0 sa0 serial pd sda a1 sa1 a2 sa2 s2# s3# ba0, ba1 a0-a12 ras# rs2#, bank 2 rs3#, bank 3 rba0, rba1: ddr sdrams ra0-ra12: ddr sdrams rras#: ddr sdrams rcas#: ddr sdrams rwe#: ddr sdrams rcke0: ddr sdrams x2 ranks (u1 b -u9 b , u10 b -u18 b ) rcke1: ddr sdrams x2 ranks (u1 t -u9 t , u10 t -u18 t ) reset# cas# we# cke0 cke1 ck ck# dq24 dq25 dq28 dq29 dq30 dq31 dq26 dq27 u15b dq dq dq dq dq dq dq dq dq16 dq17 dq20 dq21 dq22 dq23 dq18 dq19 u17b dq dq dq dq dq dq dq dq dq8 dq9 dq12 dq13 dq14 dq15 dq10 dq11 u18b dq dq dq dq dq dq dq dq dq0 dq1 dq4 dq5 dq6 dq7 dq2 dq3 u5b dq dq dq dq dq dq dq dq dq27 dq26 dq31 dq30 dq29 dq28 dq25 dq24 u4b dq dq dq dq dq dq dq dq dq19 dq18 dq23 dq22 dq21 dq20 dq17 dq16 u2b dq dq dq dq dq dq dq dq dq11 dq10 dq15 dq14 dq13 dq12 dq9 dq8 dm cs# dqs u1b dq dq dq dq dq dq dq dq dq3 dq2 dq7 dq6 dq5 dq4 dq1 dq0 dqs9/dm0 rs0# u3b dq dq dq dq dq dq dq dq r e g i s t e r s pll ddr sdram x 4 ddr sdram x 4 ddr sdram x 4 ddr sdram x 4 ddr sdram x 4 ddr sdram x 4 ddr sdram x 4 ddr sdram x 4 ddr sdram x 4 register x 2 scl u1t dq dq dq dq dq dq dq dq u2t dq dq dq dq dq dq dq dq u3t dq dq dq dq dq dq dq dq u18t dq dq dq dq dq dq dq dq rs1# dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dqs0 dqs10/dm1 dqs1 u17t dq dq dq dq dq dq dq dq dm cs# dqs dqs11/dm2 dqs2 dm cs# dqs dm cs# dqs u16b dq dq dq dq dq dq dq dq u16t dq dq dq dq dq dq dq dq dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dqs12/dm3 dqs3 u4t dq dq dq dq dq dq dq dq dm cs# dqs u15t dq dq dq dq dq dq dq dq dm cs# dqs dqs17/dm8 dqs8 u5t dq dq dq dq dq dq dq dq dm cs# dqs cb3 cb2 cb7 cb6 cb5 cb4 cb1 cb0 ck0 ck0# 120 u19, u21 u22 u20 spd v ddspd wp u14b dq dq dq dq dq dq dq dq dq59 dq58 dq63 dq62 dq61 dq60 dq57 dq56 u9b dq dq dq dq dq dq dq dq dq51 dq50 dq55 dq54 dq53 dq52 dq49 dq48 u7b dq dq dq dq dq dq dq dq dq43 dq42 dq47 dq46 dq45 dq44 dq41 dq40 dm cs# dqs u6b dq dq dq dq dq dq dq dq dq35 dq34 dq39 dq38 dq37 dq36 dq33 dq32 dqs13/dm4 rs2# u8b dq dq dq dq dq dq dq dq u6t dq dq dq dq dq dq dq dq u7t dq dq dq dq dq dq dq dq u8t dq dq dq dq dq dq dq dq rs3# dm cs# dqs dm cs# dqs dm cs# dqs dqs4 dqs14/dm5 dqs5 dqs15/dm6 dqs6 dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dqs16/dm7 dqs7 u9t dq dq dq dq dq dq dq dq dm cs# dqs u14t dq dq dq dq dq dq dq dq dm cs# dqs cb0 cb1 cb4 cb5 cb6 cb7 cb2 cb3 dq56 dq57 dq60 dq61 dq62 dq63 dq58 dq59 u10b dq dq dq dq dq dq dq dq dq48 dq49 dq52 dq53 dq54 dq55 dq50 dq51 u12b dq dq dq dq dq dq dq dq dq40 dq41 dq44 dq45 dq46 dq47 dq42 dq43 u13b dq dq dq dq dq dq dq dq dq32 dq33 dq36 dq37 dq38 dq39 dq34 dq35 u13t dq dq dq dq dq dq dq dq dm cs# dqs dm cs# dqs dm cs# dqs u12t dq dq dq dq dq dq dq dq dm cs# dqs u11b dq dq dq dq dq dq dq dq u11t dq dq dq dq dq dq dq dq dm cs# dqs dm cs# dqs dm cs# dqs u10t dq dq dq dq dq dq dq dq dm cs# dqs v ref v ss ddr sdrams ddr sdrams v dd ddr sdrams dqs9/dm0 dqs0 dqs10/dm1 dqs1 dqs11/dm2 dqs2 dqs12/dm3 dqs3 dqs17/dm8 dqs8 dqs13/dm4 dqs4 dqs14/dm5 dqs5 dqs15/dm6 dqs6 dqs16/dm7 dqs7 s0# s1# rs0#, bank 0 (u1 b -u9 b ) rs1#, bank 1 (u1 t -u9 t ) (u10 b -u18 b ) (u10 t -u18 t ) 120 note: 1. all resistor values are 22 unless otherwise specified. 2. per industry standard, micron modules utilize various component speed grades, as referenced in the module part numbering guide at www.micron.com/numberguide . mt46v32m8s2 ddr sdrams for mt36vdds12872d mt46v64m8s2 ddr sdrams for mt36vddt12872d mt46v32m8tg ddr sdrams for mt36vdds25672d mt46v64m8tg ddr sdrams for mt36vddt25672d
1gb, 2gb (x72, ecc) 184-pin registered ddr sdram dimm 128meg (x72) 184-pin registered quad-bank ddrsdram dimm micron technology, inc., reserves the right to change products or specif ications without notice. dd36c128_256x72dg_c.fm - rev. c 7/03 en 7 ?2003 micron technology, inc. all rights reserved. general description the micron mt36vdds12872d, mt36vddt12872d, mt36vdds25672d, and mt36vddt25672d are high- speed cmos, dynamic random-access, 1gb and 2gb quad-rank registered memory modules, organized in a x72 (ecc) configuration using internally configured quad-bank ddr sdram devices. these ddr sdram modules use a double data rate architecture to achieve high-speed operation. the double data rate architecture is essentially a 2 n - prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr sdram mod- ule effectively consists of a single 2 n -bit wide, one- clock-cycle data transfer at the internal dram core and two corresponding n -bit wide, one-half-clock- cycle data transfers at the i/o pins. a bidirectional data strobe (dqs) is transmitted externally, along with data, for use in data capture at the receiver. dqs is an intermittent strobe transmitted by the ddr sdram during reads and by the memory controller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. these ddr sdram modules operates from differ- ential clock inputs (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. commands (address and con- trol signals) are registered at every positive edge of ck. input data is registered on both edges of dqs, and out- put data is referenced to both edges of dqs, as well as to both edges of ck. read and write accesses to the ddr sdram mod- ules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the device bank and row to be accessed (ba0, ba1 select devices bank; a0?a12 select device row). the address bits registered coinci- dent with the read or write command are used to select the device bank and the starting device column location for the burst access. these ddr sdram modules provide for program- mable read or write burst lengths of 2, 4, or 8 loca- tions. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. the pipelined, multibank architecture of ddr sdram modules allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. an auto refresh mode is provided, along with a power-saving power-down mode. all inputs are com- patible with the jedec standard for sstl_2. all out- puts are sstl_2, class ii compatible. for more information regarding ddr sdram operation, refer to the 256mb, 512mb, ddr sdram and 512mb and 1gb twindie ddr sdram component data sheets. pll and register operation these ddr sdram modules operate in registered mode, where the control/address input signals are latched in the register on one rising clock edge and sent to the ddr sdram devices on the following ris- ing clock edge (data access is delayed by one clock). a phase-lock loop (pll) on the module is used to redrive the differential clock signals ck and ck# to the ddr sdram devices to minimize system clock loading. serial presence-detect operation these ddr sdram modules incorporate serial presence-detect (spd). the spd function is imple- mented using a 2,048-bit eeprom. this nonvolatile storage device contains 256 bytes. the first 128 bytes can be programmed by micron to identify the module type and various sdram organizations and timing parameters. the remaining 128 bytes of storage are available for use by the customer. system read/ write operations between the master (system logic) and the slave eeprom device (dimm) occur via a standard i 2 c bus using the dimm?s scl (clock) and sda (data) signals, together with sa (2:0), which pro- vide eight unique dimm/eeprom addresses. write protect (wp) is tied to ground on the module, perma- nently disabling hardware write protect. mode register definition the mode register is used to define the specific mode of operation of the ddr sdram. this definition includes the selection of a burst length, a burst type, a cas latency and an operating mode, as shown in figure 4, mode register definition diagram, on page 8. the mode register is programmed via the mode reg- ister set command (with ba0 = 0 and ba1 = 0) and will retain the stored information until it is pro- grammed again or the device loses power (except for bit a8, which is self-clearing). reprogramming the mode register will not alter the contents of the memory, provided it is performed cor- rectly. the mode register must be loaded (reloaded) when all device banks are idle and no bursts are in
1gb, 2gb (x72, ecc) 184-pin registered ddr sdram dimm 128meg (x72) 184-pin registered quad-bank ddrsdram dimm micron technology, inc., reserves the right to change products or specif ications without notice. dd36c128_256x72dg_c.fm - rev. c 7/03 en 8 ?2003 micron technology, inc. all rights reserved. progress, and the controller must wait the specified time before initiating the subsequent operation. vio- lating either of these requirements will result in unspecified operation. mode register bits a0?a2 specify the burst length, a3 specifies the type of burst (sequential or inter- leaved), a4?a6 specify the cas latency, and a7?a12 specify the operating mode. burst length read and write accesses to the ddr sdram are burst oriented, with the burst length being program- mable, as shown in figure 4, mode register definition diagram. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a1?a12 when the burst length is set to two, by a2?a12 when the burst length is set to four and by a3?a12 when the burst length is set to eight. the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. the programmed burst length applies to both read and write bursts. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is deter- mined by the burst length, the burst type and the start- ing column address, as shown in table 6, burst definition table, on page 9. read latency the read latency is the delay, in clock cycles, between the registration of a read command and the availability of the first bit of output data. the latency can be set to 2 or 2.5 clocks, as shown in figure 5, cas latency diagram. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available nominally coincident with clock edge n + m . table table 7:, cas latency (cl) table, indicates the operat- ing frequencies at which each cas latency setting can be used. reserved states should not be used as unknown operation or incompatibility with future versions may result. figure 4: mode register definition diagram m3 = 0 reserved 2 4 8 reserved reserved reserved reserved m3 = 1 reserved 2 4 8 reserved reserved reserved reserved operating mode normal operation normal operation/reset dll all other states reserved 0 1 - 0 0 - 0 0 - 0 0 - 0 0 - 0 0 - valid valid - 0 1 burst type sequential interleaved cas latency reserved reserved 2 reserved reserved reserved 2.5 reserved burst length m0 0 1 0 1 0 1 0 1 burst length cas latency bt 0* a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 m6-m0 m8 m7 operating mode a10 a12 a11 ba0 ba1 10 11 12 13 0* 14 * m14 and m13 (ba1 and ba0) must be ?0, 0? to select the base mode register (vs. the extended mode register). m9 m10 m12 m11 1gb and 2gb modules
1gb, 2gb (x72, ecc) 184-pin registered ddr sdram dimm 128meg (x72) 184-pin registered quad-bank ddrsdram dimm micron technology, inc., reserves the right to change products or specif ications without notice. dd36c128_256x72dg_c.fm - rev. c 7/03 en 9 ?2003 micron technology, inc. all rights reserved. note: 1. for a burst length of two, a1?a12 select the two-data- element block; a0 selects the first access within the block. 2. for a burst length of four, a2?a12 select the four-data- element block; a0?a1 select the first access within the block. 3. for a burst length of eight, a3?a12 select the eight- data-element block; a0?a2 select the first access within the block. 4. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. figure 5: cas latency diagram operating mode the normal operating mode is selected by issuing a mode register set command with bits a7 ? a12 each set to zero, and bits a0 ? a6 set to the desired val- ues. a dll reset is initiated by issuing a mode regis- ter set command with bits a7 and a9 ? a12 each set to zero, bit a8 set to one, and bits a0 ? a6 set to the desired values. although not required by the micron device, jedec specifications recommend when a load mode register command is issued to reset the dll, it should always be followed by a load mode regis- ter command to select normal operating mode. all other combinations of values a7 ? a12 are reserved for future use and/or test modes. test modes and reserved states should not be used because unknown operation or incompatibility with future ver- sions may result. table 6: burst definition table burst length starting column address order of accesses within a burst sequential interleaved 2 a0 0 0-1 0-1 1 1-0 1-0 4 a1 a0 00 0-1-2-3 0-1-2-3 01 1-2-3-0 1-0-3-2 10 2-3-0-1 2-3-0-1 11 3-0-1-2 3-2-1-0 8 a2 a1 a0 000 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 001 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 010 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 011 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 100 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 101 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 110 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 111 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 table 7: cas latency (cl) table registered mode will add one clock cycle to each cl speed allowable operating clock frequency (mhz) cl = 2 cl = 2.5 -262 75 f 133 75 f 133 -26a 75 f 133 75 f 133 -265 75 f 100 75 f 133 -202 75 f 100 75 f 125 ck ck# command dq dqs cl = 2 read nop nop nop read nop nop nop burst length = 4 in the cases shown shown with nominal t ac, t dqsck, and t dqsq ck ck# command dq dqs cl = 2.5 t0 t1 t2 t2n t3 t3n t0 t1 t2 t2n t3 t3n don?t care transitioning data
1gb, 2gb (x72, ecc) 184-pin registered ddr sdram dimm 128meg (x72) 184-pin registered quad-bank ddrsdram dimm micron technology, inc., reserves the right to change products or specif ications without notice. dd36c128_256x72dg_c.fm - rev. c 7/03 en 10 ?2003 micron technology, inc. all rights reserved. extended mode register the extended mode register controls functions beyond those controlled by the mode register; these additional functions are dll enable/disable and out- put drive strength. these functions are controlled via the bits shown in figure 6, extended mode register definition digram. the extended mode register is pro- grammed via the load mode register command to the mode register (with ba0 = 1 and ba1 = 0) and will retain the stored information until it is pro- grammed again or the device loses power. the enabling of the dll should always be followed by a load mode register command to the mode regis- ter (ba0/ba1 both low) to reset the dll. the extended mode register must be loaded when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. violating either of these requirements could result in unspecified oper- ation. dll enable/disable the dll must be enabled for normal operation. dll enable is required during power-up initialization and upon returning to normal operation after having disabled the dll for the purpose of debug or evalua- tion. (when the device exits self refresh mode, the dll is enabled automatically.) any time the dll is enabled, 200 clock cycles must occur before a read command can be issued. figure 6: extende d mode register definition digram note: 1. e14 and e13 (ba1 and ba0) must be ?0, 1? to select the extended mode register (vs. the base mode register). 2. the qfc# option is not supported. operating mode reserved reserved 0 ? 0 ? valid ? 0 1 dll enable disable dll 1 1 0 1 a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 9 7 654 3 8 2 1 0 e0 0 drive strength normal e1 e0 e1, operating mode a10 a11 a12 ba1 ba0 10 11 12 13 14 e3 e4 0 ? 0 ? 0 ? 0 ? 0 ? e6 e5 e7 e8 e9 0 ? 0 ? e10 e11 0 ? e12 ds 0 ? e2 2 1gb and 2gb modules
1gb, 2gb (x72, ecc) 184-pin registered ddr sdram dimm 128meg (x72) 184-pin registered quad-bank ddrsdram dimm micron technology, inc., reserves the right to change products or specif ications without notice. dd36c128_256x72dg_c.fm - rev. c 7/03 en 11 ?2003 micron technology, inc. all rights reserved. commands truth table 1 provides a general reference of avail- able commands. for a more detailed description of commands and operations, refer to the micron 256mb, 512mb, 512mb twindie, or 1gb twindie ddr sdram component data sheets. note: 1. cke is high for all commands shown except self refresh. 2. deselect and nop are functionally interchangeable. 3. ba0-ba1 provide device bank addr ess and a0-a12 provide row address. 4. ba0-ba1 provide device bank address; a0-a9 (1gb), a0?a9, a11 (2gb) provide column address; a10 high enables the auto precharge feature (nonpersistent), and a1 0 low disables the auto precharge feature. 5. applies only to read bursts with auto precharge disabled ; this command is undefined (and should not be used) for read bursts with auto precharge enabled and for write bursts. 6. a10 low: ba0-ba1 determine which device bank is precha rged. a10 high: all device banks are precharged and ba0- ba1 are ?don?t care.? 7. this command is auto refresh if cke is high, self refresh if cke is low. 8. internal refresh counter controls row addressing; all inputs and i/os are ?don?t care? except for cke. 9. ba0-ba1 select either the mode register or the extended mode register (ba0 = 0, ba1 = 0 select the mode register; ba0 = 1, ba1 = 0 select extended mode register; other combinatio ns of ba0-ba1 are reserved). a0-a12 provide the op-code to be written to the selected mode register. table 8: commands truth table note: 1 name (function) cs# ras# cas# we# addr notes deselect (nop) hxxx x 2 no operation (nop) l hhh x 2 active (select device bank and activate row) l l h h bank/row 3 read (select device bank and column, and start read burst) lhlhbank/col4 write (select device bank and column, and start write burst) l h l l bank/col 4 burst terminate lhhl x 5 precharge (deactivate row in device bank or banks) l l h l code 6 auto refresh or self refresh (enter self refresh mode) lllh x 7, 8 load mode register llllop-code9 table 9: dm operation truth table used to mask write data; provided coincident with the corresponding data. name (function) dm dq write enable l valid write inhibit hx
1gb, 2gb (x72, ecc) 184-pin registered ddr sdram dimm 128meg (x72) 184-pin registered quad-bank ddrsdram dimm micron technology, inc., reserves the right to change products or specif ications without notice. dd36c128_256x72dg_c.fm - rev. c 7/03 en 12 ?2003 micron technology, inc. all rights reserved. absolute maximum ratings stresses greater than those listed may cause perma- nent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. voltage on v dd supply relative to v ss -1v to +3.6v voltage on v dd q supply relative to v ss -1v to +3.6v voltage on v ref and inputs relative to v ss -1v to +3.6v voltage on i/o pins relative to v ss -0.5v to v dd q +0.5v operating temperature t a (ambient)0 c to +55 c storage temperature (plastic) . . . . . .-70 c to +150 c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 36w short circuit output current. . . . . . . . . . . . . . . . 50ma table 10: dc electrical characteristics and operating conditions notes: 1?5, 14; notes appear on pages 19?22; 0 c t a +70 c parameter/condition symbol min max units notes supply voltage v dd 2.3 2.7 v 32, 36 i/o supply voltage v dd q 2.3 2.7 v 32, 36,39 i/o reference voltage v ref 0.49 x v dd q 0.51 x v dd q v6, 39 i/o termination voltage (system) v tt v ref - 0.04 v ref + 0.04 v 7, 39 input high (logic 1) voltage v ih ( dc )v ref + 0.15 v dd + 0.3 v 25 input low (logic 0) voltage v il ( dc )-0.3v ref - 0.15 v 25 input leakage current (all modules) any input 0v vin vdd, vref pin 0v vin 1.35v (all other pins not under test = 0v) command/address, cas#, ras#, we#, s#, cke i i -5 5 a 48 ck, ck# -10 10 dqs, dqm -8 8 output leakage current (dqs are disabled; 0v v out v dd q dq i oz -20 20 a 48 output levels: high current (v out = v ddq -0.373v, minimum v ref , minimum v tt ) low current (v out = 0.373v, maximum v ref , maximum v tt ) i oh -16.8 ? ma 33, 34 i ol 16.8 table 11: ac input operating conditions notes: 1?5, 14; notes appear on pages 19?22; 0 c t a +70 c; v dd = v dd q = +2.5v 0.2v parameter/condition symbol min max units notes input high (logic 1) voltage v ih ( ac )v ref + 0.310 ? v 12, 25, 35 input low (logic 0) voltage v il ( ac )?v ref - 0.310 v 12, 25, 35 i/o reference voltage v ref ( ac )0.49 x v dd q 0.51 x v dd qv 6
1gb, 2gb (x72, ecc) 184-pin registered ddr sdram dimm 128meg (x72) 184-pin registered quad-bank ddrsdram dimm micron technology, inc., reserves the right to change products or specif ications without notice. dd36c128_256x72dg_c.fm - rev. c 7/03 en 13 ?2003 micron technology, inc. all rights reserved. ta bl e 1 2 : i dd specifications and co nditions (mt36vdds12872d) notes: 1?5, 8, 10, 12; ddr sdram components; notes appear on pages 19?22; 0 c t a +70 c; v dd , v dd q = +2.5v 0.2v max parameter/condition sym -262 -26a/ -265 -202 units notes operating current: one die in i dd 0 condition, one die in i dd 2 p condition. (i dd 0 condition) one device bank; active-precharge; t rc= t rc (min); t ck= t ck (min); dq, dm and dqs inputs changing once per clocke cycle; address and control inputs changing once every two clock cycles. i dd0 a tbd 1,341 tbd ma 20, 42 operating current: one die in i dd 1 condition, one die in i dd 2 p condition. (i dd 1 condition) one device bank; active-precharge; burst = 2; t rc= t rc (min); t ck= t ck (min); iout = 0ma; address and control inputs changing once per clock cycle. i dd1 a tbd 1,521 tbd ma 20, 42 precharge power-down standby current: both die in i dd 2 p condition . (i dd 2 p condition) all device banks idle; power-down mode; t ck= t ck (min); cke= low i dd2p b tbd 288 tbd ma 21, 28, 44 idle standby current: both die in i dd 2 f condition. (i dd 2 f condition) cs# = high; all device banks idle; t ck = t ck (min); ck = high; address and other control inputs changing once per clock cycle. v in = v ref for dq, dqs and dm i dd2f b tbd 2,880 tbd ma 45 active power-down standby current: both die in i dd 3 p condition. (i dd 3p condition) one device bank active; power-down mode; t ck = ck (min); cke= low i dd3p b tbd 2,160 tbd ma 21, 28, 44 active standby current: both die in i dd 3 n condition. (i dd 3 n condition) cs# = high; cke= high; one device bank active; t rc = t ras (max); t ck = t ck (min); dq, dm anddqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd3n b tbd 3,240 tbd ma 41 operating current: one die in i dd 4 r condition, one die in i dd 2 p condition. (i dd 4 r condition) burst = 2; reads; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma i dd4r a tbd 1,836 tbd ma 20, 42 operating current: one die in i dd 4 w condition, one die in i dd 2 p con- dition. (i dd 4 w condition) burst = 2; writes ; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd4w a tbd 1,971 tbd ma 20 auto refresh current: an auto refresh command is given to one die, and on the next clock cycle the second die receives an auto refresh command. t rc = t rc(min), cke = high i dd5 b tbd 8,460 tbd ma 20, 44 auto refresh distributed current: an auto refresh command given to one die and on the next clock cycle the second die recieves an auto refresh command. t rc = 7.8125s, cke = low for t rfc time. i dd5a b tbd 360 tbd ma 24, 44 self refresh current: both die are in i dd 6 condition, cke 0.2v i dd6 b tbd 288 tbd ma 9 operating current: one die in i dd 7 condition, one die in i dd 3 n condition. (i dd 7 condition) four device bank interleaving reads (bl = 4) with auto precharge, t rc = t rc (min); t ck = t ck (min); address and control inputs change only during active read or write commands. i dd7 a tbd 3,906 tbd ma 20, 43 note: a - value calculated as one module rank in this operating condition, and all other module ranks in i dd 2 p (cke low) mode. b - value calculated reflects all module ranks in this operating condition.
1gb, 2gb (x72, ecc) 184-pin registered ddr sdram dimm 128meg (x72) 184-pin registered quad-bank ddrsdram dimm micron technology, inc., reserves the right to change products or specif ications without notice. dd36c128_256x72dg_c.fm - rev. c 7/03 en 14 ?2003 micron technology, inc. all rights reserved. ta bl e 1 3 : i dd specifications and conditions (mt36vddt12872d) notes: 1?5, 8, 10, 12; ddr sdram components; notes appear on pages 19?22; 0 c t a +70 c; v dd , v dd q = +2.5v 0.2v max parameter/condition sym -262 -26a/ -265 -202 units notes operating current: one device bank; active-precharge; t rc = t rc (min); t ck = t ck (min); dq, dm and dqs inputs changing once per clock cyle; address and control inputs changing once every two clock cycles; i dd 0 a 1,233 1,053 1,188 ma 20, 42 operating current: one device bank; active-read-precharge; burst = 2; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle i dd 1 a 1,548 1,413 1,503 ma 20, 42 precharge power-down standby current: all device banks idle; power-down mode; t ck = t ck (min); cke = (low) i dd 2 p b 144 144 144 ma 21, 28, 44 idle standby current: cs# = high; all device banks idle; t ck = t ck min; cke = high; address and other control inputs changing once per clock cycle. v in = v ref for dq, dqs, and dm i dd 2 f b 1,620 1,620 1,620 ma 45 active power-down standby current: one device bank active; power-down mode; t ck = t ck (min); cke = low i dd 3 p b 900 900 1,080 ma 21, 28, 44 active standby current: cs# = high; cke = high; one device bank; active-precharge; t rc = t ras (max); t ck = t ck (min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd 3 n b 1,800 1,800 1,800 ma 41 operating current: burst = 2; reads; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma i dd 4 r a 1,458 1,458 1,683 ma 20, 42 operating current: burst = 2; writes; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd 4 w a 1,323 1,323 1,818 ma 20 auto refresh current t rc = t rfc (min) i dd 5 b 8,460 8,460 8,820 ma 20, 44 t rc = 7.81s i dd 5 a b 216 216 216 ma 24, 44 self refresh current: cke 0.2v i dd 6 b 144 144 144 ma 9 operating current: four device bank interleaving reads (bl= 4) with auto precharge with, t rc = minimum t rc allowed; t ck = t ck (min); address and control inputs change only during active read, or write commands. i dd 7 a 3,258 3,258 3,393 ma 20, 43 note: a - value calculated as one module rank in this operating condition, and all other module ranks in i dd 2 p (cke low) mode. b - value calculated reflects all module ranks in this operating condition.
1gb, 2gb (x72, ecc) 184-pin registered ddr sdram dimm 128meg (x72) 184-pin registered quad-bank ddrsdram dimm micron technology, inc., reserves the right to change products or specif ications without notice. dd36c128_256x72dg_c.fm - rev. c 7/03 en 15 ?2003 micron technology, inc. all rights reserved. ta bl e 1 4 : i dd specifications and co nditions (mt36vdds25672d) notes: 1?5, 8, 10, 12; ddr sdram components; notes appear on pages 19?22; 0 c t a +70 c; v dd , v dd q = +2.5v 0.2v max parameter/condition sym -262 -26a/ -265 -202 units notes operating current: one die in i dd 0 condition, one die in i dd 2 p condition. (i dd 0 condition) one device bank; active-precharge; t rc= t rc (min); t ck= t ck (min); dq, dm and dqs inputs changing once per clocke cycle; address and control inputs changing once every two clock cycles. i dd0 a tbd tbd tbd ma 20, 42 operating current: one die in i dd 1 condition, one die in i dd 2 p condition. (i dd 1 condition) one device bank; active-precharge; burst = 2; t rc= t rc (min); t ck= t ck (min); iout = 0ma; address and control inputs changing once per clock cycle. i dd1 a tbd tbd tbd ma 20, 42 precharge power-down standby current: both die in i dd 2 p condition . (i dd 2 p condition) all device banks idle; power-down mode; t ck= t ck (min); cke= low i dd2p b tbd tbd tbd ma 21, 28, 44 idle standby current: both die in i dd 2 f condition. (i dd 2 f condition) cs# = high; all device banks idle; t ck = t ck (min); ck = high; address and other control inputs changing once per clock cycle. v in = v ref for dq, dqs and dm i dd2f b tbd tbd tbd ma 45 active power-down standby current: both die in i dd 3 p condition. (i dd 3p condition) one device bank active; power-down mode; t ck = ck (min); cke= low i dd3p b tbd tbd tbd ma 21, 28, 44 active standby current: both die in i dd 3 n condition. (i dd 3 n condition) cs# = high; cke= high; one device bank active; t rc = t ras (max); t ck = t ck (min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd3n b tbd tbd tbd ma 41 operating current: one die in i dd 4 r condition, one die in i dd 2 p condition. (i dd 4 r condition) burst = 2; reads; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma i dd4r a tbd tbd tbd ma 20, 42 operating current: one die in i dd 4 w condition, one die in i dd 2 p con- dition. (i dd 4 w condition) burst = 2; writes; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd4w a tbd tbd tbd ma 20 auto refresh current: an auto refresh command is given to one die, and on the next clock cycle the second die receives an auto refresh command. t rc = t rc(min), cke = high i dd5 b tbd tbd tbd ma 20, 44 auto refresh distributed current: an auto refresh command given to one die and on the next clock cycle the second die recieves an auto refresh command. t rc = 7.8125s, cke = low for t rfc time. i dd5a b tbd tbd tbd ma 24, 44 self refresh current: both die are in i dd 6 condition, cke 0.2v i dd6 b tbd tbd tbd ma 9 operating current: one die in i dd 7 condition, one die in i dd 3 n condition. (i dd 7 condition) four device bank interleaving reads (bl = 4) with auto precharge, t rc = t rc (min); t ck = t ck (min); address and control inputs change only during active read or write commands. i dd7 a tbd tbd tbd ma 20, 43 note: a - value calculated as one module bank in this operating condition, and all other module ranks in i dd 2 p (cke low) mode. b - value calculated reflects all module ranks in this operating condition.
1gb, 2gb (x72, ecc) 184-pin registered ddr sdram dimm 128meg (x72) 184-pin registered quad-bank ddrsdram dimm micron technology, inc., reserves the right to change products or specif ications without notice. dd36c128_256x72dg_c.fm - rev. c 7/03 en 16 ?2003 micron technology, inc. all rights reserved. ta bl e 1 5 : i dd specifications and conditions (mt36vddt25672d) notes: 1?5, 8, 10, 12; ddr sdram components; notes appear on pages 19?22; 0 c t a +70 c; v dd , v dd q = +2.5v 0.2v max parameter/condition sym -262 -26a/ -265 -202 units notes operating current: one device bank; active-precharge; t rc = t rc (min); t ck = t ck (min); dq, dm and dqs inputs changing once per clock cyle; address and control inputs changing once every two clock cycles; i dd 0 a tbd 945 1,332 ma 20, 42 operating current: one device bank; active-read-precharge; burst = 2; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle i dd 1 a tbd 1,170 1,467 ma 20, 42 precharge power-down standby current: all device banks idle; power-down mode; t ck = t ck (min); cke = (low) i dd 2 p b tbd 180 216 ma 21, 28, 44 idle standby current: cs# = high; all device banks idle; t ck = t ck min; cke = high; address and other control inputs changing once per clock cycle. v in = v ref for dq, dqs, and dm i dd 2 f b tbd 1,440 1,260 ma 45 active power-down standby current: one device bank active; power-down mode; t ck = t ck (min); cke = low i dd 3 p b tbd 648 900 ma 21, 28, 44 active standby current: cs# = high; cke = high; one device bank; active-precharge; t rc = t ras (max); t ck = t ck (min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd 3 n b tbd 1,440 1,260 ma 41 operating current: burst = 2; reads; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma i dd 4 r a tbd 1,665 1,647 ma 20, 42 operating current: burst = 2; writes; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd 4 w a tbd 1,845 1,737 ma 20 auto refresh current t rc = t rfc (min) i dd 5 b tbd 1,845 2,997 ma 20, 44 t rc = 7.81s i dd 5 a b tbd 288 252 ma 24, 44 self refresh current: cke 0.2v i dd 6 b tbd 108 252 ma 9 operating current: four device bank interleaving reads (bl= 4) with auto precharge with, t rc = minimum t rc allowed; t ck = t ck (min); address and control inputs change only during active read, or write commands. i dd 7 a tbd 2,835 3,987 ma 20, 43 note: a - value calculated as one module rank in this operating condition, and all other module ranks in i dd 2 p (cke low) mode. b - value calculated reflects all module ranks in this operating condition.
1gb, 2gb (x72, ecc) 184-pin registered ddr sdram dimm 128meg (x72) 184-pin registered quad-bank ddrsdram dimm micron technology, inc., reserves the right to change products or specif ications without notice. dd36c128_256x72dg_c.fm - rev. c 7/03 en 17 ?2003 micron technology, inc. all rights reserved. table 16: capacitance (mt36vdds12872d and mt36vddt12872d) note: 11; notes appear on pages 19?22 parameter symbol min max input/output capacitance: dq, dqs/dm c io 16.0 20.0 input capacitance: command and address c i 1 2.5 3.5 input capacitance: s# c i 1 2.5 3.5 input capacitance: ck, ck# c i 2 ?4 input capacitance: cke c i 3 2.5 3.5 table 17: capacitance (mt36vdds25672d and mt36vddt25672d) note: 11; notes appear on pages 19?22 parameter symbol min max input/output capacitance: dq, dqs/dm c io tbd tbd input capacitance: command and address c i 1 tbd tbd input capacitance: s# c i 1 tbd tbd input capacitance: ck, ck# c i 2 tbd tbd input capacitance: cke c i 3 tbd tbd table 18: ddr sdram electrical characteristics and recommended ac operating conditions notes: 1?5, 12?15, 29; notes appear on pages 19?22; 0 c t a +70 c; v dd = v dd q = +2.5v 0.2v accharacteristics -262 -26a/-265 -202 units notes parameter sym min max min max min max access window of dqs from ck/ck# t ac -0.70 +0.70 -0.75 +0.75 -0.8 +0.75 ns ck high-level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck 26 ck low-level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck 26 clock cycle time cl = 2.5 t ck (2.5) 6137.513813ns40, 46 cl = 2 t ck (2) 7.5 13 7.5 13 10 13 ns 40, 46 dq and dm input hold time relative to dqs t dh 0.45 0.5 0.6 ns 23, 27 dq and dm input setup time relative to dqs t ds 0.45 0.5 0.6 ns 23, 27 dq and dm input pulse width (for each input) t dipw 1.75 1.75 2 ns 27 access window of dqs from ck/ck# t dqsck -0.65 +0.6 -0.75 +0.75 -0.8 +0.75 ns dqs input high pulse width t dqsh 0.35 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 0.35 t ck dqs-dq skew, dqs to last dq valid, per group, per access t dqsq 0.45 0.5 0.5 ns 22, 23 write command to first dqs latching transition t dqss 0.75 1.25 0.75 1.25 0.75 1.25 t ck dqs falling edge to ck rising - setup time t dss 0.2 0.2 0.2 t ck dqs falling edge from ck rising - hold time t dsh 0.2 0.2 0.2 t ck half clock period t hp t ch, t cl t ch, t cl t ch, t cl ns 30 data-out high-impedance window from ck/ck# t hz +0.7 +0.75 +0.75 ns 16, 37
1gb, 2gb (x72, ecc) 184-pin registered ddr sdram dimm 128meg (x72) 184-pin registered quad-bank ddrsdram dimm micron technology, inc., reserves the right to change products or specif ications without notice. dd36c128_256x72dg_c.fm - rev. c 7/03 en 18 ?2003 micron technology, inc. all rights reserved. data-out low-impedance window from ck/ck# t lz -0.7 -0.75 -0.8 ns 16,38 address and control input hold time (fast slew rate) t ih f 0.75 0.90 1.1 ns 12 address and control input setup time (fast slew rate) t is f 0.75 0.90 1.1 ns 12 address and control input hold time (slow slew rate) t ih s 0.8 1 1.1 ns 12 address and control input setup time (slow slew rate) t is s 0.8 1 1.1 ns 12 address and control in put pulse width (for each input) t ipw 2.2 2.2 2.5 ns 12 load mode register command cycle time t mrd 15 15 16 ns dq-dqs hold, dqs to first dq to go non-valid, per access t qh t hp- t qhs t hp- t qhs t hp - t qhs ns 22, 23 data hold skew factor t qhs 0.75 0.75 0.75 ns active to precharge command t ras 40 120,000 40 120,000 40 120,000 ns 31 active to read with auto precharge command t rap 15 20 20 ns active to active/auto refresh command period t rc 60 65 70 ns auto refresh command period t rfc 75 75 80 ns 44 active to read or write delay t rcd 15 20 20 ns precharge command period t rp 15 20 20 ns dqs read preamble t rpre 0.91.10.91.10.91.1ns37 dqs read postamble t rpst 0.40.60.40.60.40.6 t ck active bank a to activebank b command t rrd 15 15 15 t ck dqs write preamble t wpre 0.25 0.25 0.25 ns dqs write preamble setup time t wpres 000 t ck 18, 19 dqs write postamble t wpst 0.40.60.40.60.40.6ns17 write recovery time t wr 15 15 15 t ck internal write to read command delay t wtr 111ns data valid output window (dvw) na t qh - t dqsq t qh - t dqsq t qh - t dqsq t ck 22 refresh to refresh command interval t refc 70.3 70.3 70.3 ns 21 average periodic refresh interval t refi 7.8 7.8 7.8 s 21 terminating voltage delay to v dd t vtd 000s exit self refresh to non-read command t xsnr 75 75 80 ns exit self refresh to read command t xsrd 200 200 200 ns table 18: ddr sdram electrical characteristics and recommended ac operating conditions (continued) notes: 1?5, 12?15, 29; notes appear on pages 19?22; 0 c t a +70 c; v dd = v dd q = +2.5v 0.2v accharacteristics -262 -26a/-265 -202 units notes parameter sym min max min max min max
1gb, 2gb (x72, ecc) 184-pin registered ddr sdram dimm 128meg (x72) 184-pin registered quad-bank ddrsdram dimm micron technology, inc., reserves the right to change products or specif ications without notice. dd36c128_256x72dg_c.fm - rev. c 7/03 en 19 ?2003 micron technology, inc. all rights reserved. notes 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical ac and dc characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are guaranteed for the full voltage range specified. 3. outputs measured with equivalent load: 4. ac timing and i dd tests may use a v il -to-v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v ref (or to the crossing point for ck/ck#), and parameter speci- fications are guaranteed for the specified ac input levels under normal use conditions. the mini- mum slew rate for the input signals used to test the device is 1v/ns in the range between v il ( ac ) and v ih ( ac ). 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above [below] the dc input low [high] level). 6. v ref is expected to equal v dd q/2 of the transmit- ting device and to track variations in the dc level of the same. peak-to-peak noise (non-common mode) on v ref may not exceed 2 percent of the dc value. thus, from v dd q/2, v ref is allowed 25mv for dc error and an additional 25mv for ac noise. this measurement is to be taken at the nearest v ref by-pass capacitor. 7. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref and must track variations in the dc level of v ref . 8. i dd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time at cl = 2 for -262 and -26a; cl = 2.5 for -265 with the outputs open. 9. enables on-chip refresh and address counters. 10. i dd specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. 11. this parameter is sampled. v dd = +2.5v 0.2v, v dd q = +2.5v 0.2v, v ref = vss, f = 100 mhz, t a = 25 c, v out (dc) = v dd q/2, v out (peak to peak) = 0.2v. dm input is grouped with i/o pins, reflecting the fact that they are matched in loading. 12. command/address input slew rate = 0.5v/ns. for -262, -26a, and -265 with slew rates 1v/ns and faster, t is and t ih are reduced to 900ps. if the slew rate is less than 0.5v/ns, timing must be derated: t is has an additional 50ps per each 100mv/ns reduction in slew rate from the 500mv/ns, while t ih remains constant. if the slew rate exceeds 4.5v/ns, functionality is uncertain. 13. the ck/ck# input reference level (for timing ref- erenced to ck/ck#) is the point at which ck and ck# cross; the input reference level for s ignals other than ck/ck# is v ref . 14. inputs are not recognized as valid until v ref stabi- lizes. exception: during the period before v ref stabilizes, cke 0.3 x v dd q is recognized as low. 15. the output timing reference level, as measured at the timing reference point indicated in note 3, is v tt . 16. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (hz) or begins driving (lz). 17. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 18. this is not a device limit. the device will operate with a negative value, but system performance could be degraded due to bus turnaround. 19. it is recommended that dqs be valid (high or low) on or before the write command. the case shown (dqs going from high-z to logic low ) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss. 20. min ( t rc or t rfc) for i dd measurements is the smallest multiple of t ck that meets the minimum absolute value for the respective parameter. t ras (max) for i dd measurements is the largest multi- ple of t ck that meets the maximum absolute value for t ras. output (v out ) 50 ? v tt 30pf
1gb, 2gb (x72, ecc) 184-pin registered ddr sdram dimm 128meg (x72) 184-pin registered quad-bank ddrsdram dimm micron technology, inc., reserves the right to change products or specif ications without notice. dd36c128_256x72dg_c.fm - rev. c 7/03 en 20 ?2003 micron technology, inc. all rights reserved. 21. the refresh period 64ms. this equates to an aver- age refresh rate of 7.821s. however, an auto refresh command must be asserted at least once every 70.3s; burst refreshing or posting by the dram controller greater than eight refresh cycles is not allowed. 22. the valid data window is derived by achieving other specifications - t hp ( t ck/2), t dqsq, and t qh ( t qh = t hp - t qhs). the data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. the clock is allowed a maximum duty cycle variation of 45/55. functionality is uncer- tain when operating beyond a 45/55 ratio. figure 7, derating data valid window ( t qh - t dqsq), shows the derating curves for duty cycles ranging between 50/50 and 45/55. 23. each byte lane has a corresponding dqs. 24. this limit is actually a nominal value and does not result in a fail value. cke is high during refresh command period ( t rfc [min]) else cke is low (i.e., during standby). 25. to maintain a valid level, the transitioning edge of the input must: a. sustain a constant slew rate from the current ac level through to the target ac level, v il ( ac ) or v ih ( ac ). b.reach at least the target ac level. c. after the ac target level is reached, continue to maintain at least the target dc level, v il ( dc ) or v ih ( dc ). 26. jedec specifies ck and ck# input slew rate must be 1v/ns (2v/ns differentially). 27. dq and dm input slew rates must not deviate from dqs by more than 10 percent. if the dq/ dm/dqs slew rate is less than 0.5v/ns, timing must be derated: 50ps must be added to t ds and t dh for each 100mv/ns reduction in slew rate. if slew rate exceeds 4v/ns, functionality is uncer- tain. 28. v dd must not vary more than 4 percent if cke is not active while any bank is active. 29. the clock is allowed up to 150ps of jitter. each timing parameter is allowed to vary by the same amount. figure 7: derating data valid window ( t qh - t dqsq) 3.750 3.700 3.650 3.600 3.550 3.500 3.450 3.400 3.350 3.300 3.250 3.400 3.350 3.300 3.250 3.200 3.150 3.100 3.050 3.000 2.950 2.900 2.500 2.463 2.425 2.388 2.350 2.313 2.275 2.238 2.200 2.163 2.125 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 47/53 46.5/54.5 46/54 45.5/55.5 45/55 clock duty cycle ns -26a/-265 @ t ck = 10ns -202 @ t ck = 10ns -26a/-265 @ t ck = 7.5ns -202 @ t ck = 8ns -262 @ t ck = 7.5ns na
1gb, 2gb (x72, ecc) 184-pin registered ddr sdram dimm 128meg (x72) 184-pin registered quad-bank ddrsdram dimm micron technology, inc., reserves the right to change products or specif ications without notice. dd36c128_256x72dg_c.fm - rev. c 7/03 en 21 ?2003 micron technology, inc. all rights reserved. 30. t hp min is the lesser of t cl minimum and t ch minimum actually applied to the device ck and ck# inputs, collectively during bank active. 31. reads and writes with auto precharge are not allowed to be issued until t ras(min) can be satis- fied prior to the internal precharge command being issued. 32. any positive glitch must be less than 1/3 of the clock and not more than +400mv or 2.9v, which- ever is less. any negative glitch must be less than 1/3 of the clock cycle and not exceed either - 300mv or 2.2v, whichever is more positive. 33. normal output drive curves: a. the full variation in driver pull-down current from minimum to maximum process, temper- ature and voltage will lie within the outer bounding lines of the v-i curve of figure 8, pull-down characteristics. b. the variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure 8, pull-down characteristics. c. the full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the v-i curve of figure 9, pull-up char- acteristics. d. the variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure 9, pull-up characteristics. e. the full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between 0.71 and 1.4, for device drain-to-source voltages from 0.1v to 1.0v, and at the same voltage and temperature. f. the full variation in the ratio of the nominal pull-up to pull-down current should be unity 10 percent, for device drain-to-source voltages from 0.1v to 1.0v. 34. the voltage levels used are derived from a mini- mum v dd level and the referenced test load. in practice, the voltage levels obtained from a prop- erly terminated bus will provide significantly dif- ferent voltage values. 35. v ih overshoot: v ih (max) = v dd q + 1.5v for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. v i l undershoot: v il (min) = -1.5v for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 36. v dd and v ddq must track each other. 37. this maximum value is derived from the refer- enced test load. in practice, the values obtained in a typical terminated design may reflect up to 310ps less for t hz(max) and the last dvw. t hz(max) will prevail over t dqsck(max) + t rpst(max) condition. t lz(min) will prevail over t dqsck(min) + t rpre(max) condition. 38. or slew rates greater than 1v/ns the (lz) transition will start about 310ps earlier. 39. during initialization, v ddq , v tt , and v ref must be equal to or less than v dd + 0.3v. alternatively, v tt may be 1.35v maximum during power up, even if v dd /v ddq are 0v, provided a minimum of 42 of series resistance is used between the v tt supply and the input pin. figure 8: pull-down characteristics figure 9: pull-up characteristics 160 140 i out (ma) v out (v) nom inal low minimum nom inal high maximum 120 100 80 60 40 20 0 0.0 0.5 1.0 1.5 2.0 2.5 v out (v) 0 -20 i out (ma) n om inal low minimum nominal high m axim um -40 -60 -80 -100 -120 -140 -160 -180 -200 0.0 0.5 1.0 1.5 2.0 2.5 v dd q - v out (v)
1gb, 2gb (x72, ecc) 184-pin registered ddr sdram dimm 128meg (x72) 184-pin registered quad-bank ddrsdram dimm micron technology, inc., reserves the right to change products or specif ications without notice. dd36c128_256x72dg_c.fm - rev. c 7/03 en 22 ?2003 micron technology, inc. all rights reserved. 40. the current micron part operates below the slow- est jedec operating frequency of 83 mhz. as such, future die may not reflect this option. 41. for the -262, -26a, and -265 modules, i dd 3n is specified to be 35ma at 100 mhz. 42. random addressing changing and 50 percent of data changing at every transfer. 43. random addressing changing and 100 percent of data changing at every transfer. 44. cke must be active (high) during the entire time a refresh command is executed. that is, from the time the auto refresh command is registered, cke must be active at each rising clock edge, until t ref later. 45. i dd 2n specifies the dq, dqs, and dm to be driven to a valid high or low logic level. i dd 2q is similar to i dd 2f except i dd 2q specifies the address and control inputs to remain stable. although i dd 2f, i dd 2n, and i dd 2q are similar, i dd 2f is ?worst case.? 46. whenever the operating frequency is altered, not including jitter, the dll is required to be reset. this is followed by 200 clock cycles. 47. leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes.
1gb, 2gb (x72, ecc) 184-pin registered ddr sdram dimm 128meg (x72) 184-pin registered quad-bank ddrsdram dimm micron technology, inc., reserves the right to change products or specif ications without notice. dd36c128_256x72dg_c.fm - rev. c 7/03 en 23 ?2003 micron technology, inc. all rights reserved. note: 1. this parameter is not necessarily production tested. 2. data inputs must be low a minimum time of t act max, after reset is taken high. 3. data and clock inputs must be held at valid levels (not floating) a minimum time of t inact max, after reset# is taken low. 4. for data signal input slew rate 1 v/ns. 5. for data signal input slew rate 0.5 v/ns and < 1 v/ns. 6. ck, ck# signals input slew rates are 1 v/ns. table 19: register timing requirements and switching characteristics notes: 2?6 register parameter symbol conditions 0 c t a +70 c v dd = 2.5v 0.2v units notes min max 1:1 13-26 bit sstl clock frequency f clock 200 mhz pulse duration, ck, ck# high or low t w 2.5 differential inputs, active time (see note 1) t act 22 ns 1 differential inputs, inactive time (see note 2) t inact 22 ns 1 setup time, fast slew rate (see notes 3 and 5) t su data before ck , ck 0.75 ns setup time, slow slew rate (see notes 4 and 5) 0.9 ns hold time, fast slew rate (see notes 3 and 5) t h data after ck , ck 0.75 hold time, slow slew rate (see notes 4 and 5) 0.9 ns
1gb, 2gb (x72, ecc) 184-pin registered ddr sdram dimm 128meg (x72) 184-pin registered quad-bank ddrsdram dimm micron technology, inc., reserves the right to change products or specif ications without notice. dd36c128_256x72dg_c.fm - rev. c 7/03 en 24 ?2003 micron technology, inc. all rights reserved. note: 1. the timing and switching specifications for the pll listed above are critical for proper operation of the ddr sdram registered dimms. these are meant to be a subset of th e parameters for the specific device used on the module. detailed information for this pll is available in jedec standard jesd82. 2.the pll must be able to handle spread spectrum induced skew. 3.operating clock frequency indicates a range over which the pl l must be able to lock, but in which it is not required to meet the other timing parameters. (used for low-speed system debug.) 4.stabilization time is the time required for the integrated pl l circuit to obtain phase lock of its feedback signal to its reference signal after power up. 5.static phase offset does not include jitter. 6.period jitter and half-period jitter specifications are separate specifications that must be met independently of each other. 7.the output slew rate is determined from the ibis model: table 20: pll clock driver timing requ irements and switching characteristics note: 1 parameter symbol test conditions t a = 0?70oc v dd = 2.5v 0.2v units notes min nom max clock frequency f c 66 167 mhz 2, 3 input clock duty cycle 40% 60% stabilization time 1 0.1 ms 4 low-to high level propagation delay time t plh ck mode/ck to any output 1.5 3.5 6 ns high-to low level propagation delay time t phl ck mode/ck to any output 1.5 3.5 6 ns 5 output enable time t en ck mode/g to any y output 3ns output disable time t dis ck mode/g to any y output 3ns6 jitter (peak-to-peak) t (jitter) 66 mhz 120 ps 6 100/125/133/167 mhz 75 jitter (cycle-to-cycle) t (jitter) 66 mhz 110 ps 7 100/125/133/167 mhz 65 2, 3 phase error t (phase error) terminated with 120 /16pf -150 150 ns 4 output skew t skew(o) terminated with 120 /16pf 100 ns pulse skew t dis terminated with 120 /16pf 100 ns 5 duty cycle 66 mhz to 100 mhz 49.5% 50.5% 101 mhz to 167 mhz 49% 51% 6 output rise and fall times (20% - 80%) t r, t f load = 120 /16pf 650 800 950 ps 6 v dd /2 gnd v dd cdcv857 r=60 r=60 ? v ck v ck ?
1gb, 2gb (x72, ecc) 184-pin registered ddr sdram dimm 128meg (x72) 184-pin registered quad-bank ddrsdram dimm micron technology, inc., reserves the right to change products or specif ications without notice. dd36c128_256x72dg_c.fm - rev. c 7/03 en 25 ?2003 micron technology, inc. all rights reserved. figure 10: component case temperature vs. air flow note: 1. micron technology, inc. recommends a minimum air flow of 1 meter/second (~197 lfm) across mt36vdds12872d, mt36vddt12872d, mt36vdds25672d, and mt36vddt2 5672d modules when installed in a system. 2. the component case temperature measurements shown above were obtained experimentally. the typical system to be used for experimental purposes is a dual-processor 600 mhz work station, fully loaded, with four comparable registered memory modules. case temperatures charted represent wo rst-case component locations on modules installed in the internal slots of the system. 3. temperature versus air speed data is obtained by performing experiments with the system motherboard removed from its case and mounted in a eiffel-type low air speed wind tunn el. peripheral devices installed on the system motherboard for testing are the processor(s) and video card, all other peripheral devices are mounted outside of the wind tunnel test chamber. 4. the memory diagnostic software used for determining worst- case component temperatures is a memory diagnostic soft- ware application developed for internal use by micron technology, inc. 20 30 40 50 60 70 80 90 100 0.0 0.5 1.0 2.0 air flow (meters/sec) degrees celsius ambient temperature = 25o c t max - memory stress software t ave - 3d gaming software t ave - memory stress software minimum air flow
1gb, 2gb (x72, ecc) 184-pin registered ddr sdram dimm 128meg (x72) 184-pin registered quad-bank ddrsdram dimm micron technology, inc., reserves the right to change products or specif ications without notice. dd36c128_256x72dg_c.fm - rev. c 7/03 en 26 ?2003 micron technology, inc. all rights reserved. spd clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions (as shown in figure 11, data validity, and figure 12, defi- nition of start and stop). spd start condition all commands are preceded by the start condition, which is a high-to-low transition of sda when scl is high. the spd device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. spd stop condition all communications are terminated by a stop condi- tion, which is a low-to-high transition of sda when scl is high. the stop condition is also used to place the spd device into standby power mode. spd acknowledge acknowledge is a software convention used to indi- cate successful data transfers. the transmitting device, either master or slave, will release the bus after trans- mitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data (as shown in fig- ure 13, acknowledge response from receiver). the spd device will always respond with an acknowledge after recognition of a start condition and its slave address. if both the device and a write oper- ation have been selected, the spd device will respond with an acknowledge after the receipt of each subse- quent eight-bit word. in the read mode the spd device will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowl- edge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will termi- nate further data transmissions and await the stop condition to return to standby power mode. figure 11: data validity figure 12: definition of start and stop figure 13: acknowledge response from receiver scl sda data stable data stable data change scl sda start bit stop bit scl from master data output from transmitter data output from receiver 9 8 acknowledge
1gb, 2gb (x72, ecc) 184-pin registered ddr sdram dimm 128meg (x72) 184-pin registered quad-bank ddrsdram dimm micron technology, inc., reserves the right to change products or specif ications without notice. dd36c128_256x72dg_c.fm - rev. c 7/03 en 27 ?2003 micron technology, inc. all rights reserved. table 21: eeprom device select code most significant bit (b7) is sent first select code device type identifier chip enable rw b7 b6 b5 b4 b3 b2 b1 b0 memory area select code (two arrays) 1010sa2sa1sa0rw protection register select code 0110sa2sa1sa0rw table 22: eeprom operating modes mode rw bit wc bytes initial sequence current address read 1v ih or v il 1 start, device select, rw = ?1? random address read 0v ih or v il 1 start, device select, rw = ?0?, address 1v ih or v il 1 restart, device select, rw = ?1? sequential read 1v ih or v il 1 similar to current or random address read byte write 0v il 1 start, device select, rw = ?0? page write 0v il 16 start, device select, rw = ?0? table 23: serial presence-detect eeprom dc operating conditions all voltages referenced to v ss ; v ddspd = +2.3v to +3.6v parameter/condition symbol min max units supply voltage v ddspd 2.3 3.6 v input high voltage: logic 1; all inputs v ih v ddspd x 0.7 v ddspd + 0.5 v input low voltage: logic 0; all inputs v il -1 v ddspd x 0.3 v output low voltage: i out = 3ma v ol ?0.4v input leakage current: v in = gnd to v dd i li ?10a output leakage current: v out = gnd to v dd i lo ?10a standby current: scl = sda = v dd - 0.3v; all other inputs = v ss or v dd i sb ?30a power supply current: scl clock frequency = 100 khz i dd ?2ma
1gb, 2gb (x72, ecc) 184-pin registered ddr sdram dimm 128meg (x72) 184-pin registered quad-bank ddrsdram dimm micron technology, inc., reserves the right to change products or specif ications without notice. dd36c128_256x72dg_c.fm - rev. c 7/03 en 28 ?2003 micron technology, inc. all rights reserved. figure 14: spd eeprom timing diagram note: 1. the spd eeprom write cycle time ( t wrc) is the time from a valid stop condition of a write sequence to the end of the eeprom internal erase/program cycle. during the write cy cle, the eeprom bus interface circuit is disabled, sda remains high due to pull-up resistor, and the eeprom does not respond to its slave address. scl sda in sda out t low t su:sta t hd:sta t f t high t r t buf t dh t aa t su:sto t su:dat t hd:dat undefined table 24: serial presence-detect eeprom ac operating conditions all voltages referenced to v ss ; v ddspd = +2.3v to +3.6v parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.3 3.5 s time the bus must be free before a new transition can start t buf 4.7 s data-out hold time t dh 300 ns sda and scl fall time t f 300 ns data-in hold time t hd:dat 0s start condition hold time t hd:sta 4s clockhighperiod t high 4s noise suppression time constant at scl, sda inputs t i 100 ns clock low period t low 4.7 s sda and scl rise time t r 1s scl clock frequency t scl 100 khz data-in setup time t su:dat 250 ns start condition setup time t su:sta 4.7 s stop condition setup time t su:sto 4.7 s write cycle time t wrc 10 ms 1
1gb, 2gb (x72, ecc) 184-pin registered ddr sdram dimm 128meg (x72) 184-pin registered quad-bank ddrsdram dimm micron technology, inc., reserves the right to change products or specif ications without notice. dd36c128_256x72dg_c.fm - rev. c 7/03 en 29 ?2003 micron technology, inc. all rights reserved. table 25: serial presence-detect matrix ?1?/?0?: serial data, ?driven to high?/?driven to low?; notes at end of spd matrix byte description entry (version) mt36vdds12872d/ mt36vddt12872d mt36vdds25672d/ mt36vddt25672d 0 number of bytes used by micron 128 80 80 1 total number of spd memory bytes 256 08 08 2 memory type ddr sdram 07 07 3 number of row addresses 13 0d 0d 4 number of column addresses 10 or 11 0a 0b 5 number of module ranks 40404 6 module data width 72 48 48 7 module data width (continued) 00000 8 module voltage interface levels sstl 2.5v 04 04 9 sdram cycle time, t ck, cas latency = 2.5, (see note 1) 7ns(-262/-26a) 7.5ns (-265) 8ns (-202) 70 75 80 70 75 80 10 sdram access from clock, t ac, cas latency = 2.5 0.75ns (-262/-26a/-265) 0.8ns (-202) 75 80 75 80 11 module configuration type ecc 02 02 12 refresh rate/ type 7.81s/self 82 82 13 sdram width (primary sdram) 80808 14 error-checking sdram data width 80808 15 minimum clock delay, back-to-back random column access 10101 16 burst lengths supported 2, 4, 8 0e 0e 17 number of banks on sdram device 40404 18 cas latencies supported 2, 2.5 0c 0c 19 cs latency 00101 20 we latency 10202 21 sdram module attributes registered, pll 26 26 22 sdram device attributes: general fast/concurrent ap c0 c0 23 sdram cycle time, t ck,cas latency = 2 7.5ns (-262/-26a) 10ns (-265/-202) 75 a0 75 a0 24 sdram cycle time, t ck, cas latency = 2 7.5ns 75 75 25 sdram cycle time, t ck, cas latency = 1 ?0000 26 sdram access from ck, t ac, cas latency = 1 ?0000 27 minimum row precharge time, t rp 15ns (-262) 20ns (-26a/-265/-202) 3c 50 3c 50 28 minimum row active to row active, t rrd 15ns 3c 3c 29 minimum ras# to cas# delay, t rcd 15ns (-262) 20ns (-26a/-265/-202) 3c 50 3c 50 30 minimum ras# pulse width, t ras (see note 2) 45ns (-262/-26a/-265) 40ns (-202) 2d 28 2d 28 31 module rank density 256mb or 512mb 40 80 32 address and command setup time, t is, (see note 3) 1.0ns (-262/-26a/-265) 1.1ns (-202) a0 b0 a0 b0 33 address and command hold time, t ih (see note 3) 1.0ns (-262/-26a/-265) 1.1ns (-202) a0 b0 a0 b0
1gb, 2gb (x72, ecc) 184-pin registered ddr sdram dimm 128meg (x72) 184-pin registered quad-bank ddrsdram dimm micron technology, inc., reserves the right to change products or specif ications without notice. dd36c128_256x72dg_c.fm - rev. c 7/03 en 30 ?2003 micron technology, inc. all rights reserved. note: 1. value for -26a t ck set to 7ns (0x70) for optimum bios compatibility. actual device spec. value is 7.5ns. 2. the value of t ras for -262, -26a, and -265 modules is calculated from t rc - t rp. actual device spec. value is 40ns. 3. the jedec spd specification allows fast or slow slew rate va lues for these bytes. the worst-case (slow slew rate) value is represented here. systems requiring the fast slew rate setup and hold values are supported, provided the faster mini- mum slew rate is met. 34 data/data mask input setup time, t ds 0.5ns (-262/-26a/-265) 0.6ns (-202) 50 60 50 60 35 data/data mask input hold time, t dh 0.5ns (-262/-26a/-265) 0.6ns (-202) 50 60 50 60 36-40 reserved 00 00 41 minimum active/auto refresh time, t rc 60ns (-262) 65ns (-26a/-265) 70ns (-202) 3c 41 46 3c 41 46 42 minimum auto refresh to active/ auto refresh command period, t rfc 75ns (-262/-26a/-265) 80ns (-202) 4b 50 4b 50 43 maximum cycle time, t ck(max) 13ns 34 34 44 maximum dqs-dq skew time, t dqsq 0.5ns (-262/-26a/-265) 0.6ns (-202) 32 3c 32 3c 45 maximum read data hold skew factor, t qhs 0.75ns (-262/-26a/-265) 1.0ns (-202) 75 a0 75 a0 46 reserved 00 00 47 dimm height 01 01 48?61 reserved 00 00 62 spd revision release 1.0 10 10 63 checksum for bytes 0-62 -262 -26a -265 -202 d5 02 32 cd 16 43 73 0e 64 manufacturer?s jedec id code micron 2c 2c 65-71 manufacturer?s jedec id code (continued) ff ff 72 manufacturing location 1 - 12 01 - 0c 01 - 0c 73-90 module part number (ascii) variable data variable data 91 pcb identification code 1 - 9 01-09 01-09 92 identification code (continued) 00000 93 year of manufacture in bcd variable data variable data 94 week of manufacture in bcd variable data variable data 95-98 module serial number variable data variable data 99-127 manufacturer-specific data (rsvd) ?? table 25: serial presence-detect matrix ?1?/?0?: serial data, ?driven to high?/?driven to low?; notes at end of spd matrix byte description entry (version) mt36vdds12872d/ mt36vddt12872d mt36vdds25672d/ mt36vddt25672d
1gb, 2gb (x72, ecc) 184-pin registered ddr sdram dimm 128meg (x72) 184-pin registered quad-bank ddrsdram dimm micron technology, inc., reserves the right to change products or specif ications without notice. dd36c128_256x72dg_c.fm - rev. c 7/03 en 31 ?2003 micron technology, inc. all rights reserved. ? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.m icron.com, customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trademarks and/or service marks of micron technology, inc. all other trademarks are the property of their respective owners. figure 15: low-profile 184-pin dimm (quad rank) note: all dimensions in inches (millimet ers) or typical where noted. data sheet designation advance: this data sheet contains initial descrip- tions of products still under development. .054 (1.37) .046 (1.17) .268 (6.81) max 1.205 (30.61) 1.195 (30.35) pin 1 .700 (17.78) typ. .098 (2.50) d (2x) .091 (2.30) typ. .250 (6.35) typ. 4.750 (120.65) .050 (1.27) typ. .091 (2.30) typ. .040 (1.02) typ. .079 (2.00) r (4x) .035 (0.90) r pin 92 front view 5.256 (133.50) 5.244 (133.20) 2.55 (64.77) 1.95 (49.53) .394 (10.00) typ. u1 u2 u3 u4 u19 u20 u5 u6 u7 u8 u9 back view pin 184 pin 93 u10 u11 u12 u13 u14 u21 u22 u15 u16 u17 u18 .054 (1.37) .046 (1.17) .157 (3.99) max twindie ddr 36vdds12872d stacked tsop ddr 36vddt12872d max min

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