View SSM2212RZ_7236957.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

audio, dual-matched npn transistor ssm2212 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2010 analog devices, inc. all rights reserved. features very low voltage noise: 1 nv/hz maximum @ 100 hz excellent current gain match: 0.5% low offset voltage (v os ): 200 v maximum outstanding offset voltage drift: 0.03 v/c high gain bandwidth product: 200 mhz pin configuration c 1 1 b 1 2 e 1 3 nic 4 c 2 8 b 2 7 e 2 6 nic 5 ssm2212 nic = no internal connection 09043-001 figure 1. 8-lead soic_n general description the ssm2212 is a dual, npn-matched transistor pair that is specifically designed to meet the requirements of ultralow noise audio systems. with its extremely low input base spreading resistance (rbb' is typically 28 ) and high current gain (h fe typically exceeds 600 at i c = 1 ma), the ssm2212 can achieve outstanding signal-to- noise ratios. the high current gain results in superior performance compared to systems incorporating commercially available monolithic amplifiers. excellent matching of the current gain (h fe ) to about 0.5% and low v os of less than 10 v typical make the ssm2212 ideal for symmetrically balanced designs, which reduce high-order amplifier harmonic distortion. stability of the matching parameters is guaranteed by protection diodes across the base-emitter junction. these diodes prevent degradation of beta and matching characteristics due to reverse biasing of the base-emitter junction. the ssm2212 is also an ideal choice for accurate and reliable current biasing and mirroring circuits. furthermore, because a current mirrors accuracy degrades exponentially with mismatches of v be between transistor pairs, the low v os of the ssm2212 does not need offset trimming in most circuit applications. the ssm2212 performance and characteristics are guaranteed over the extended temperature range of ?40c to +85c.
ssm2212 rev. b | page 2 of 12 table of contents features .............................................................................................. 1 ? pin configuration............................................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? electrical characteristics............................................................. 3 ? absolute maximum ratings............................................................ 4 ? thermal resistance .......................................................................4 ? esd caution...................................................................................4 ? typical performance characteristics ..............................................5 ? applications information .................................................................8 ? fast logarithmic amplifier..........................................................8 ? outline dimensions ..........................................................................9 ? ordering guide .............................................................................9 ? revision history 7/10rev. a to rev. b changes to figure 1.......................................................................... 1 6/10rev. 0 to rev. a changes to fast logarithmic amplifier section .......................... 8 6/10revision 0: initial version
ssm2212 rev. b | page 3 of 12 specifications electrical characteristics v cb = 15 v, i o = 10 a, t a = 25c, unless otherwise specified. table 1. parameter symbol text conditions/comments min typ max unit dc and ac characteristics current gain 1 h fe i c = 1 ma 300 605 ?40c t a +85c 300 i c = 10 a 200 550 ?40c t a +85c 200 current gain match 2 h fe 10 a i c 1 ma 0.5 5 % noise voltage density 3 e n i c = 1 ma, v cb = 0 v f o = 10 hz 1.6 2 nv/hz f o = 100 hz 0.9 1 nv/hz f o = 1 khz 0.85 1 nv/hz f o = 10 khz 0.85 1 nv/hz low frequency noise (0.1 hz to 10 hz) e n p-p i c = 1 ma 0.4 v p-p offset voltage v os v cb = 0 v, i c = 1 ma 10 200 v ?40c t a +85c 220 v offset voltage change vs. v cb v os /v cb 0 v v cb v max 4 ,1 a i c 1 ma 5 10 50 v offset voltage change vs. i c v os /i c 1 a i c 1 ma 5 , v cb = 0 v 5 70 v offset voltage drift v os /t ?40c t a +85c 0.08 1 v/c ?40c t a +85c, v os trimmed to 0 v 0.03 0.3 v/c breakdown voltage bv ceo 40 v gain bandwidth product f t i c = 100 ma, v ce = 10 v 200 mhz collector-to-base leakage current i cbo v cb = v max 25 500 pa ?40c t a +85c 3 na collector-to-collector leakage current i cc v cc = v max 6 , 7 35 500 pa ?40c t a +85c 4 na collector-to-emitter leakage current i ces v ce = v max , v be = 0 v 6 , 7 35 500 pa ?40c t a +85c 4 na input bias current i b i c = 10 a 50 na ?40c t a +85c 50 na input offset current i os i c = 10 a 6.2 na ?40c t a +85c 13 na input offset current drift i os /t i c = 10 a 6 , ?40c t a +85c 40 150 pa/c collector saturation voltage v ce (sat) i c = 1 ma, i b = 100 a 0.05 0.2 v output capacitance c ob v cb = 15 v, i e = 0 a 23 pf bulk resistance r be 10 a i c 10 ma 6 0.3 1.6 collector-to-collector capacitance c cc v cc = 0 v 35 pf 1 current gain is guaranteed with collector-to-base voltage (v cb ) swept from 0 v to v max at the indicated collector currents. 2 current gain match (h fe ) is defined as follows: h fe = (100(i b )(h fe min )/i c ). 3 noise voltage density is gua ranteed, but not 100% tested. 4 this is the maximum change in v os as v cb is swept from 0 v to 40 v. 5 measured at i c = 10 a and guaranteed by design over the specified range of i c . 6 guaranteed by design. 7 i cc and i ces are verified by measurement of i cbo .
ssm2212 rev. b | page 4 of 12 absolute maximum ratings table 2. parameter rating breakdown voltage of collector-to-base voltage (bv cbo ) 40 v breakdown voltage of collector-to-emitter voltage (bv ceo ) 40 v breakdown voltage of collector-to-collector voltage (bv cc ) 40 v breakdown voltage of emitter-to-emitter voltage (bv ee ) 40 v collector current (i c ) 20 ma emitter current (i e ) 20 ma storage temperature range ?65c to +150c operating temperature range ?40c to +85c junction temperature range ?65c to +150c lead temperature (soldering, 60 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 3. thermal resistance package type ja jc unit 8-lead soic (r-8) 120 45 c/w esd caution
ssm2212 rev. b | page 5 of 12 typical performance characteristics t a = 25c, v ce = 5 v, unless otherwise specified. ch1 2.00v m4.00s a ch1 15.8v 1 ch1 4.92v p-p 0 9043-002 figure 2. low frequency nois e (0.1 hz to 10 hz), i c = 1 ma, gain = 10,000,000 1k 0.1 1 10 100 0.1 1 10 100 1k 10k 100k noise voltage density (nv/ hz) frequency (hz) i c = 1ma test i c = 10a test i c = 1a test 09043-003 figure 3. noise voltage density vs. frequency 100 0 20 40 60 80 0.001 1 0.1 0.01 total noise (nv/ hz) collector current, i c (ma) r s = 100k ? r s = 10k ? r s = 1k ? 09043-004 figure 4. total noise vs. collector current, f = 1 khz 900 800 700 600 500 400 300 200 100 0.001 1 0.1 0.01 current gain (h fe ) collector current (ma) t a = +25c t a = ?55c t a = +125c 09043-005 figure 5. current gain vs. collector current (v cb = 0 v) 900 800 700 600 500 400 300 200 0 100 ?100 ?50 0 50 100 150 current gain (h fe ) temperature (c) 1ma 1a 09043-006 figure 6. current gain vs. temperature (excludes i cbo ) 0.70 0.65 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.001 0.01 0.1 1 10 base emitter voltage, v be (v) collector current, i c (ma) v ce = 5v 09043-008 figure 7. base emitter voltage vs. collector current
ssm2212 rev. b | page 6 of 12 100 10 1 0.1 0.01 0.001 0.001 0.01 0.1 1 10 input resistance, h ie (m ? ) collector current, i c (ma) v ce = 5v 09043-009 figure 8. small signal input resistance vs. collector current 1m 0.1m 0.01m 1 0.1 0.01 0.001 1000 100 10 1 0.1 0.01 conductance, h oe (mho) collector current, i c (ma) v ce = 5v 09043-010 figure 9. small signal output conductance vs. collector current 0.01 0.1 1 10 100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 collector current, i c (ma) saturation voltage, v sat (v) t a = ?55c t a = +125c t a = +25c 09043-017 figure 10. collector current vs. saturation voltage 1000 100 10 1 0.1 0.01 25 50 75 100 125 current, i cbo (na) temperature (c) 09043-012 figure 11. collector-to-base leakage current vs. temperature 40 35 30 25 20 15 10 5 0 0 102030405 capacitance, c cb (pf) reverse bias voltage (v) 0 09043-013 figure 12. collector-to-base capacitance vs. reverse bias voltage 40 35 30 25 20 15 10 5 0 0 102030405 capacitance, c cc (pf) collector-to-substrate voltage (v) 0 09043-014 figure 13. collector-to-collector capacitance vs. collector-to-substrate voltage
ssm2212 rev. b | page 7 of 12 1000 100 10 1 0.1 0.01 25 50 75 100 125 current, i cc (na) temperature (c) 09043-015 figure 14. collector-to-collector leakage current vs. temperature 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 102030405 capacitance, c cc (pf) reverse bias voltage (v) 0 09043-016 figure 15. collector-to-collector capacitance vs. reverse bias voltage
ssm2212 rev. b | page 8 of 12 applications information fast logarithmic amplifier the circuit of figure 16 is a modification of a standard logarithmic amplifier configuration. running the ssm2212 at 2.5 ma per side (full-scale) allows for a fast response with a wide dynamic range. the circuit has a 7 decade current range and a 5 decade voltage range, and it is capable of 2.5 s settling time to 1% with a 1 v to 10 v step. the output follows the equation: in ref o v v q kt r rr v ln 2 23 + = to compensate for the temperature dependence of the kt/q term, a resistor with a positive 0.35%/c temperature coefficient is chosen for r 2 . the output is inverted with respect to the input and is nominally ?1 v/decade using the component values indicated. 1 4 3 2 8 7 5 6 ?15v 330pf r 3 7.5k ? r 2 500? r 2 = tel labs qb1e (+0.35%/c) 330pf v o +15 v r s 4k ? r 1 4k? 4k? v in (0v to 10v) v ref 10v ad8512 ssm2212 1/2 ad8512 09043-018 ?
ssm2212 rev. b | page 9 of 12 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 17. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) ordering guide model 1 temperature range package description package option SSM2212RZ ?40c to +85c 8-lead standard small outline package [soic_n] r-8 SSM2212RZ-r7 ?40c to +85c 8-lead standard small outline package [soic_n] r-8 SSM2212RZ-rl ?40c to +85c 8-lead standa rd small outline package [soic_n] r-8 1 z = rohs compliant part.
ssm2212 rev. b | page 10 of 12 notes
ssm2212 rev. b | page 11 of 12 notes
ssm2212 rev. b | page 12 of 12 notes ?2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09043-0-7/10(b)

▲Up To Search▲

Price & Availability of SSM2212RZ

	To Download SSM2212RZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .