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document no. 70-0236-05 www.psemi.com page 1 of 11 ?2007-2011 peregrine semiconductor corp. all rights reserved. figure 1. block diagram f in prescaler 10 / 11 main counter 20-bit frequency register m(8:0) a(3:0) r(5:0) 19* 20 r counter f r phase detector 6 6 13 serial control pd_u pd_d 3 msel f p f c direct control * prescaler bypass not available in direct mode ld cext product specification PE97042 features 3.5 ghz ultracmos? integer-n pll rad hard for space applications ?? low power: 45 ma typical ?? 3.5 ghz operation ?? 10/11 dual modulus prescaler ?? phase detector output ?? serial or direct hardwired mode ?? ultra-low phase noise: -216 dbc/hz ?? seu < 10 -9 errors / bit-day ?? 100 krad (si) total dose ?? easily modified to be pin compatible with the pe9704, packaged in a 44-lead cqfj (reference application note an23 at www.psemi.com) peregrine?s PE97042 is a high-performance integer-n pll capable of frequency synthesis up to 3.5 ghz. the device is designed for superior phase noise performance while providing an order of magnitude reduction in current consumption, when compared with existing commercial space plls. the PE97042 features a 10/11 dual modulus prescaler, counters, and a phase comparator as shown in figure 1 . counter values are programmable through a serial or direct hardwired mode. the PE97042 is optimized for commercial space applications. single event latch up (sel) is physically impossible and single event upset (seu) is better than 10 -9 errors per bit / day. it is manufactured on peregrine?s ultracmos? process, a patented variation of silicon-on- insulator (soi) technology on a sapphire substrate, offering excellent rf performance and intrinsic radiation tolerance. product description
product specification PE97042 page 2 of 11 ?2007-2011 peregrine semiconductor corp. all rights reserved. document no. 70-0236-05 ultracmos? rfic solutions clock, m 6 gnd r 3 r 2 r 1 r 0 v dd ld enh f r gnd gnd m 7 m 8 a 0 d mode v dd e_wr, a 1 a 2 a 3 f in f in table 1. pin descriptions figure 2. pin configurations (top view) 44-lead cqfj figure 3. package type pin no. pin name interface mode type description 1 v dd both (note 1) power supply input. input may range from 2.85 v to 3.45 v. bypassing recommended. 2 r 0 direct input r counter bit0 3 r 1 direct input r counter bit1 4 r 2 direct input r counter bit2 5 r 3 direct input r counter bit3 6 gnd both ground 7 r 4 direct input r counter bit4 8 r 5 direct input r counter bit5 (msb) 9 m 0 direct input m counter bit0 10 m 1 direct input m counter bit1 11 v dd both (note 1) power supply input. input may range from 2.85 v to 3.45 v. bypassing recommended. 12 v dd both (note 1) power supply input. input may range from 2.85 v to 3.45 v. bypassing recommended. 13 m 2 direct input m counter bit2 14 m 3 direct input m counter bit3 15 s_wr serial input frequency register load enable input. buffer ed data is transferred to the frequency register on s_wr rising edge. m 4 direct input m counter bit4 16 data serial input binary serial data input. data is entered l sb first, and is clocked serially into the 20 -bit frequency control register (e_wr ?low?) or the 8-bit enhancement register (e_wr ?high?) on the rising edge of clock. m 5 direct input m counter bit5
product specification PE97042 page 3 of 11 document no. 70-0236-05 www.psemi.com ?2007-2011 peregrine semiconductor corp. all rights reserved. table 1. pin descriptions (continued) notes 1. v dd pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level. 2. all digital input pins have 70 k ? pull-up resistors to v dd . pin no. pin name interface mode type description 17 gnd both ground 18 clock serial input clock input. data is clocked serially into either the 20-bit primary register (e_wr ?low?) or the 8-bit enhancement register (e_wr ?high?) on the rising edge of clock. m 6 direct input m counter bit6 19 m 7 direct input m counter bit7 20 m 8 direct input m counter bit8 (msb) 21 a 0 direct input a counter bit0 22 d mode both input selects direct interface mode (d mode = 1) or serial interface mode (d mode = 0) 23 v dd both (note 1) power supply input. input may range from 2.85 v to 3.45 v. bypassing recommended. 24 e_wr serial input enhancement register write enable. while e_wr is ?high?, data can be serially clocked into the enhancement register on the rising edge of clock. a 1 direct input a counter bit1. 25 a 2 direct input a counter bit2 26 a 3 direct input a counter bit3 (msb) 27 f in both input prescaler input from the vco, 3.5 ghz max frequency. a 22 pf coupling capacitor should be placed as close as possible to this pin and terminated with a 50 resistor to ground. 28 both input prescaler complementary input. a 22 pf bypass capacitor should be placed as close as possible to this pin and be connected in series with a 50 resistor to ground. 29 gnd both ground. 30 n/c no connect. 31 v dd both (note 1) power supply input. input may range from 2.85 v to 3.45 v. bypassing recommended. 32 d out serial output data out. the main counter output, r counter output, or dual modulus prescaler select (msel) can be routed to d out through enhancement register programming. 33 v dd both (note 1) power supply input. input may range from 2.85 v to 3.45 v. bypassing recommended. 34 n/c no connect. 35 gnd both ground. 36 pd_ d both output pd_ d pulses down when f p leads f c . 37 pd_ u both pd_ u pulses down when f c leads f p . 38 v dd both (note 1) power supply input. input may range from 2.85 v to 3.45 v. bypassing recommended. 39 c ext both output logical ?nand? of pd_ u and pd_ d , passed through an on-chip, 2 k ? series resistor. connecting c ext to an external capacitor will low pass filter the input to the inverting amplifier used for driving ld. 40 gnd both ground 41 gnd both ground 42 f r both input reference frequency input 43 enh both output enhancement mode. when asserted low (?0?), enhancement register bits are functional. 44 ld serial output lock detect output, the open-drain logical inversion of c ext . when the loop is locked, ld is high impedance; othe rwise ld is a logic low (?0?). f in
product specification PE97042 page 4 of 11 ?2007-2011 peregrine semiconductor corp. all rights reserved. document no. 70-0236-05 ultracmos? rfic solutions note: 1. periodically sampled, not 100% tested. tested per mil- std-883, m3015 c2 table 4. esd ratings electrostatic discharge (esd) precautions when handling this ultracmos? device, observe the same precautions that you would use with other esd-sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the specified rating. latch-up avoidance unlike conventional cmos devices, ultracmos? devices are immune to latch-up. table 5. dc characteristics: v dd = 3.3 v, -40 c < t a < 85 c, unless otherwise specified symbol parameter/conditions level units v esd esd voltage (human body mod- el) ? note 1 1000 v table 2. absolute maximum ratings table 3. operating ratings symbol parameter/conditions min max units v dd supply voltage -0.3 4.0 v v i voltage on any input -0.3 v dd + 0.3 v i i dc into any input -10 +10 ma i o dc into any output -10 +10 ma t stg storage temperature range -65 150 c symbol parameter/conditions min max units v dd supply voltage 2.85 3.45 v t a operating ambient temperature range -40 85 ? c exceeding absolute maximum ratings may cause permanent damage. operation should be restricted to the limits in the operating ranges table. operation between operating range maximum and absolute maximum for extended periods may reduce reliability. symbol parameter conditions min typ max units i dd operational supply current; v dd = 3.30 v prescaler disabled 15 ma prescaler enabled 45 50 ma digital inputs: all except f r , f in (all digital inputs have 70 k ? pull-up resistors) v ih high level input voltage v dd = 2.85-3.45 v 0.7 x v dd v v il low level input voltage v dd = 2.85-3.45 v 0.3 x v dd v i ih high level input current v ih = v dd = 3.45 v 1 a i il low level input current v il = 0, v dd = 3.45 v -70 a reference divider input: f r i ihr high level input current v ih = v dd = 3.45 v 100 a i ilr low level input current v il = 0, v dd = 3.45 v -100 a counter and phase detector outputs: f c , f p . v old output voltage low i out = 6 ma 0.4 v v ohd output voltage high i out = -3 ma v dd - 0.4 v lock detect outputs: c ext , ld v olc output voltage low, c ext i out = 100 a 0.4 v v ohc output voltage high, c ext i out = -100 a v dd - 0.4 v v olld output voltage low, ld i out = 1 ma 0.4 v
product specification PE97042 page 5 of 11 document no. 70-0236-05 www.psemi.com ?2007-2011 peregrine semiconductor corp. all rights reserved. table 6. ac characteristics: v dd = 3.3 v, -40 c < t a < 85 c, unless otherwise specified notes: 1. fclk is verified during the functional pattern test. serial programming sections of the functional pattern are clocke d at 10 mhz to verify fclk specification. 2. cmos logic levels can be used to drive the reference input. if the v dd of the cmos driver matches the v dd of pll ic, then the reference input can be dc coupled. otherwise, t he reference input should be ac coupled. 3. parameter is guaranteed through characterization only and is not tested. 4. parameters below are not tested for die sales. thes e parameters are verified during the element evaluation. symbol parameter conditions min typical max units control interface and latches (see figures 1 and 9 ) f clk clock serial data clock frequency (note 1) 10 mhz t clkh clock serial clock high time 30 ns t clkl clock serial clock low time 30 ns t dsu data set-up time after clock rising edge 10 ns t dhld data hold time after clock rising edge 10 ns t pw s_wr pulse width 30 ns t cwr clock rising edge to s_wr rising edge. 30 ns t ce clock falling edge to e_wr transition 30 ns t wrc s_wr falling edge to clock rising edge. 30 ns t ec e_wr transition to clock rising edge 30 ns t mdo msel data out delay after f in rising edge c l = 12 pf 8 ns main divider (including prescaler) 4 p fin input level range external ac coupling 275 mhz freq 3.2 ghz -5 5 dbm external ac coupling 3.2 ghz < freq 3.5 ghz 3.15 v v dd 3.45 v 0 5 dbm main divider (prescaler bypassed) 4 f in operating frequency 50 300 mhz p fin input level range external ac coupling -5 5 dbm reference divider f r operating frequency (note 3) 100 mhz p fr reference input power 2 single-ended input -2 10 dbm phase detector f c comparison frequency (note 3) 50 mhz ssb phase noise (f in = 1.9 ghz, f r = 20 mhz, f c = 20 mhz, lbw = 50 khz, v dd = 3.3 v, temp = 25 ? c ) 4 ? n phase noise 100 hz offset -89 dbc/hz ? n phase noise 1 khz offset -95 dbc/hz ? n phase noise 10 khz offset -102 dbc/hz ssb phase noise (f in = 1.9 ghz, f r = 20 mhz, f c = 20 mhz, lbw = 50 khz, v dd = 3.0 v, temp = 25 ? c ) 4 ? n phase noise 100 hz offset -87 dbc/hz ? n phase noise 1 khz offset -94 dbc/hz ? n phase noise 10 khz offset -101 dbc/hz
product specification PE97042 page 6 of 11 ?2007-2011 peregrine semiconductor corp. all rights reserved. document no. 70-0236-05 ultracmos? rfic solutions -30 -25 -20 -15 -10 -5 0 5 0 500 1000 1500 2000 2500 3000 3500 4000 frequency (mhz) rf sensitivity (dbm) 2.85v 3.15v 3.30v figure 4. rf sensitivity versus frequency (typical device at temperature = 25 c) figure 5. typical phase noise for PE97042, v dd = 3.3 v, temp = 25 c, fvco = 1.92 ghz, fcomp = 20 mhz, loop bandwidth = 50 khz
product specification PE97042 page 7 of 11 document no. 70-0236-05 www.psemi.com ?2007-2011 peregrine semiconductor corp. all rights reserved. r c l r n r p c l pd_d & pd_u v dd or n = 50 ? r p = 50 ? figure 6. equivalent input diagram: reference input figure 7. equivalent input diagram: main input figure 8. equivalent output diagram: pd_ d & pd_ u outputs r f f ref r f = 112k ? c eq = 12pf c eq r f pin 42 peregrine specification 71/0032 peregrine specification 71/0033 peregrine specification 71/0034 pin 27 pin 28 c eq r f in r f r f r f r f r f = 50k c eq = 0.8pf l bw = 3nh l bw r f = 50k ? c eq = 0.8pf l bw = 3nh l bw c eq r f l bw l bw f f in f f in 3nh 3nh l bw l bw l bw l bw pin 36 pin 37 r f = 112 k ? c eq = 12 pf r f = 50 k ? c eq = 0.8 pf l bw = 3 nh r n = 50 ? r p = 50 ?
product specification PE97042 page 8 of 11 ?2007-2011 peregrine semiconductor corp. all rights reserved. document no. 70-0236-05 ultracmos? rfic solutions functional description the PE97042 consists of a prescaler, counters, a phase detector, and control logic. the dual modulus prescaler divides the vco frequency by either 10 or 11, depending on the value of the modulus select. counters ?r? and ?m? divide the reference and prescaler output, respectively, by integer values stored in a 20-bit register. an additional counter (?a?) is used in the modulus select logic. the phase-frequency detector generates up and down frequency control signals. the control logic includes a selectable chip interface. data can be written via a serial bus or hardwired directly to the pins. there are also various operational and test modes and a lock detect output. main counter chain normal operating mode setting the pb control bit ?low? enables the 10/11 prescaler. the main counter chain then divides the rf input frequency (f in ) by an integer derived from the values in the ?m? and ?a? counters. in this mode, the output from the main counter chain (f p ) is related to the vco frequency (f in ) by the following equation: f p = f in / [10 x (m + 1) + a (1) where a ? m + 1, 1 m 511 when the loop is locked, f in is related to the reference frequency (f r ) by the following equation: f in = [10 x (m + 1) + a] x (f r / (r+1)) (2) where a ? m + 1, 1 m 511 a consequence of the upper limit on a is that f in must be greater than or equal to 90 x (f r / (r+1)) to obtain contiguous channels. the a counter can accept values as high as 15, but in typical operation it will cycle from 0 to 9 between increments in m. programming the m counter with the minimum allowed value of ?1? will result in a minimum m counter divide ratio of ?2?. prescaler bypass mode setting the enhancement register bit pb ?high? allows f in to bypass the 10/11 prescaler. in this mode, the prescaler and a counter are powered down, and the input vco frequency is divided by the m counter directly. this mode is only available when using the serial port to set the frequency control bits. the following equation relates f in to the reference frequency f r : f in = (m + 1) x (f r / (r+1)) (3) where 1 m 511 reference counter the reference counter chain divides the reference frequency f r down to the phase detector comparison frequency f c . the output frequency of the 6-bit r counter is related to the reference frequency by the following equation: f c = f r / (r + 1) (4) where 0 r 63 note that programming r with ?0? will pass the reference frequency (f r ) directly to the phase detector.
product specification PE97042 page 9 of 11 document no. 70-0236-05 www.psemi.com ?2007-2011 peregrine semiconductor corp. all rights reserved. register programming serial interface mode serial interface mode is selected by setting the d mode input ?low?. while the e_wr input is ?low?, serial data (data input), b 0 to b 19 , is clocked into a buffer register on the rising edge of clock, lsb (b 0 ) first. the contents from this buffer register are transferred into the frequency control register on the rising edge of s_wr according to the timing diagram shown in figure 9 . this data controls the counters as shown in table 7 . while the e_wr input is ?high?, serial data (data input), b 0 to b 7 , is clocked into a buffer register on the rising edge of clock, lsb (b 0 ) first. the contents from this buffer register are transferred into the enhancement register on the falling edge of e_wr according to the timing diagram shown in figure 9 . after the falling edge of e_wr, the data provides control bits as shown in table 8 . these bits are active when the enh input is ?low?. direct interface mode direct interface mode is selected by setting the d mode input ?high?. in this mode, the counter values are set directly at external pins as shown in table 7 and figure 2 . all frequency control register bits are addressable except pb (it is not possible to bypass the 10/11 dual modulus prescaler in direct mode). msb (first in) (last in) lsb table 7. frequency register programming table 8. enhancement register programming * data is clocked serially on clock rising edge while e_wr is ?low? and transferred to frequenc y register on s_wr rising edge. * program to 0 * data is clocked serially on clock rising edge while e_wr is ?low? and transferred to frequenc y register on s_wr rising edge. msb (first in) (last in) lsb interface mode enh d mode r 5 r 4 m 8 m 7 x m 6 m 5 m 4 m 3 m 2 m 1 m 0 r 3 r 2 r 1 r 0 a 3 a 2 a 1 a 0 serial* 1 0 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 9 b 10 b 11 b 12 b 13 b 14 b 15 b 16 b 17 b 18 b 19 direct 1 1 r 5 r 4 m 8 m 7 0 m 6 m 5 m 4 m 3 m 2 m 1 m 0 r 3 r 2 r 1 r 0 a 3 a 2 a 1 a 0 interface mode enh d mode reserved* reserved* fp output power down counter load msel output fc output pb serial** 0 x b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7
product specification PE97042 page 10 of 11 ?2007-2011 peregrine semiconductor corp. all rights reserved. document no. 70-0236-05 ultracmos? rfic solutions figure 9. serial interface mode timing diagram t dhld t dsu t clkh t clkl t cwr t pw t wrc t ec t ce e_wr data clock s_wr software tools for designing the active loop filter can be found at peregrine?s web site: www.psemi.com. lock detect output a lock detect signal is provided at pin ld, via the pin c ext (see figure 1 ). c ext is the logical ?nand? of pd_ u and pd_ d waveforms, driven through a series 2 k ? resistor. connecting c ext to an external shunt capacitor provides integration of this signal. the c ext signal is then sent to the ld pin through an internal inverting comparator with an open drain output. thus ld is an ?and? function of pd_ u and pd_ d . enhancement register the functions of the enhancement register bits are s hown below. all bits are active high. operation is undefined if more than one output is sent to d out . table 9. enhancement register bit functionality note: 1. program to 0 phase detector outputs the phase detector is triggered by rising edges from the main counter (f p ) and the reference counter (f c ). it has two outputs, pd_ u , and pd_ d . if the divided vco leads the divided reference in phase or frequency (f p leads f c ), pd_ d pulses ?low?. if the divided reference leads the divided vco in phase or frequency (f c leads f p ), pd_ u pulses ?low?. the width of either pulse is directly proportional to phase offset between the two input signals, f p and f c . the phase detector gain is 430 mv/radian. pd_ u and pd_ d are designed to drive an active loop filter which controls the vco tune voltage. pd_ u pulses result in an increase in vco frequency and pd_ d results in a decrease in vco frequency. bit function description bit 0 reserved 1 bit 1 reserved 1 bit 2 f p output drives the m counter output onto the d out output. bit 3 power down power down of all functions except programming interface. bit 4 counter load immediate and cont inuous load of counter programming. bit 5 msel output drives the internal dual modul us prescaler modulus select (msel) onto the d out output. bit 6 f c output drives the r counter output onto the d out output bit 7 pb allows fin to bypass the 10/11 prescaler
product specification PE97042 page 11 of 11 document no. 70-0236-05 www.psemi.com ?2007-2011 peregrine semiconductor corp. all rights reserved. figure 10. package drawing 44-lead cqfj table 10. ordering information all dimensions are in inches order code part marking description package shipping method 97042-01 PE97042 es engineering samples 44-pin cqfj 40 units / tray 97042-11 PE97042 flight units 44-pin cqfj 40 units / tray 97042-00 PE97042 ek evaluation kit 1 / box 97042-99 fa97042 die production units die 100 units / waffle pack advance information : the product is in a formative or design stage. the datasheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification: the datasheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification: the datasheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify customers of the intended changes by issuing a cnf (customer notification form). the information in this datasheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this datasheet are implie d or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or su stain life, or in any application in which the failure of the peregrine product could create a situation in wh ich personal injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, and utsi are registered trademarks and ultracmos, harp, multiswitch and dune are trademarks of peregrine semiconductor corp. sales contact and information for sales and contact information please visit www.psemi.com.

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