 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| rev.1.00 S1R72V18 data sheet
notice no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko epson. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit a nd, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of economy, trade and industry or other approval from another government agency. all other product names mentioned herein are trademarks and/or registered trademarks of their respective companies. ?seiko epson corporation 2008, all rights reserved. scope this document applies to the S1R72V18 usb 2.0 device/host controller lsi. S1R72V18 data sheet (rev. 1.00) epson i contents 1. over view............................................................................................................................................ 1 2. feat ures .................................................................................................................... ......................... 2 3. block diagram ............................................................................................................... .................... 3 4. explanati on of func tions .................................................................................................... ............. 4 4.1 power supply ................................................................................................................... ........................... 4 4.2 reset ............................................................................................................................................................ 5 4.2.1 hard rese t..................................................................................................................... .................... 5 4.2.2 soft rese t ..................................................................................................................... ..................... 5 4.3 cloc k ........................................................................................................................................................... 5 4.4 power mana ge ment..................................................................................................................................... 6 4.5 cpu-i/f ....................................................................................................................................................... 7 4.6 usb device i/f ................................................................................................................. .......................... 7 4.6.1 speed mode and transfer type......................................................................................................... 7 4.6.2 resources .......................................................................................................................................... 7 4.6.2.1 endpoint......................................................................................................................................... 7 4.6.2.2 fifo............................................................................................................................................... 8 4.6.3 data flow .......................................................................................................................................... 8 4.6.4 usb device port external circuits.............................................................................................. ..... 9 4.7 usb host i/f ................................................................................................................... .......................... 10 4.7.1 speed mode and transfer type....................................................................................................... 10 4.7.2 resources ........................................................................................................................................ 10 4.7.2.1 cha nnels ....................................................................................................................... ............... 10 4.7.2.2 fifo............................................................................................................................................. 10 4.7.3 data flow ........................................................................................................................................ 10 4.7.4 usb host port external c ircuits................................................................................................ ..... 12 4.8 fifo .......................................................................................................................................................... 12 5. terminal la y out diagrams .................................................................................................... ......... 13 6. terminal functi ons ......................................................................................................................... 14 7. electrical ch aracteristics .................................................................................................. ............. 17 ii epson S1R72V18 data sheet (rev. 1.00) 7.1 absolute maximum ratings....................................................................................................... ............... 17 7.2 recom mended operating conditions........................................................................................................ 17 7.3 dc chara cteristics............................................................................................................. ........................ 18 7.3.1 current cons umption ............................................................................................................ .......... 18 7.3.2 input c haracteristics.......................................................................................................... .............. 20 7.3.3 output c haracteristics......................................................................................................... ............ 21 7.3.4 t erminal capacitance...................................................................................................................... 22 7.4 ac chara cteristics............................................................................................................. ........................ 23 7.4.1 reset t iming ................................................................................................................... ................ 23 7.4.2 cloc k timing................................................................................................................... ................ 23 7.4.3 cpu/dma i/f a ccess timing ...................................................................................................... .. 24 7.4.3.1 specifications for cvdd = 1.65 v to 3.6 v ................................................................................ 24 7.4.3.2 specifications when limited to cvdd = 3.0 v to 3.6 v (relaxe d specifications)..................... 25 7.4.4 usb i/f timing................................................................................................................. .............. 26 8. connecti on example s ......................................................................................................... ........... 27 8.1 cpu i/f connect ion exam ple ..................................................................................................... .............. 27 8.2 usb i/f connect ion exam ple ..................................................................................................... .............. 28 9. product codes ............................................................................................................... ................. 29 10. external dime nsion diagrams ................................................................................................ ..... 30 1. overview S1R72V18 data sheet (rev. 1.00) epson 1 1. overview the S1R72V18 is a usb host/device controller lsi that supports the usb 2.0 high-speed mode. it features two host ports to function as a usb root hub. one of the ports can be used as a usb device port after setting a switch to the appropriate setting. 2. features 2 epson S1R72V18 data sheet (rev. 1.00) 2. features < 3. block diagram S1R72V18 data sheet (rev. 1.00) epson 3 3. block diagram fifo 0 cpu i/f xbel xwrl xwrh ca[9:1] cd[15:0] xrd utm 0 host sie 0 dp_0 dm_0 r1_0 vbusen_0 osc & pll test mux device sie 0 vbusflg_0 vbus_0 fifo 1 host sie 1 utm 1 dp_1 dm_1 r1_1 vbusen_1 vbusflg_1 xcs xdack_0 xint xdack_1 xdreq_0 xdreq_1 xi xo testen burnin atpgen power manager dma controller 0 dma contoroller 1 cpu i/f controller figure 3-1 overall block diagram 4. explanation of functions 4 epson S1R72V18 data sheet (rev. 1.00) 4. explanation of functions for details of the register names used in the following discussion, refer to the technical manual for this lsi. apart from usb device functions, some of the registers in this lsi have the same functions for each port. note that this is indicated only when explaining the functions for individual ports. 4.1 power supply this lsi has three power supply systems and a common gnd. the power supply systems consist of hvdd (3.3 v) for the usb i/o power supply, cvdd (3.3 v to 1.8 v) for the cpu i/f power supply, and lvdd (1.8 v) for internal circuits and test i/o. (see figure 4-1.) i o cpu -i/f fifo sie_0 mtm_0 cpu usb lvdd hvdd cvdd 1.8v to 3.3v 1.8v 3.3v test io sie_1 mtm_1 figure 4-1 S1R72V18 power supply circuit diagram the sequence of steps for turning the power supplies on and off are described below. this lsi does not allow individual power supply circuits to be held in a continuous on or off state. also, the following restrictions apply to th e sequence for turning the cvdd/hvdd i/o power supplies and lvdd internal power supply on or off. there are no restrictions on the sequence for turning the cvdd and hvdd power supplies on or off. ? in the power on sequence, the lvdd must be turned on before turning on the cvdd and hvdd. ? in the powering off sequence, the cvdd and hvdd must be turned off before turning off the lvdd. if power supply circuit characteristics or the power supply load make this sequence impossible to follow, the cvdd or hvdd must not be on for more than 1 second while the lvdd is off. 4. explanation of functions S1R72V18 data sheet (rev. 1.00) epson 5 4.2 reset this lsi includes a hard reset function using the external xreset terminal and a soft reset function using register settings. 4.2.1 hard reset start up from reset status when power is turned on, then cancel the reset after confirming power on. 4.2.2 soft reset the usb c ircuits can be reset, or internal us b analog macros can be reset individually, via software. the chipreset.allreset bit initia lizes all circuits except the cpuif_mode register, or the chipreset.resetmtm bit for each port is used to reset individual port usb analog macros. note that the usb analog m acro should be reset only when in the sleep state. 4.3 clock this lsi incorporates an internal os cillator and feedback resistor (1 m ? ) and supports clock generation with an external oscillator. the oscillator frequency can be set to 12 mhz or 24 mhz via register settings. figure 4-2 shows a typical connection configuration for an oscillation circuit. cd, cg, and rd in the oscillator circuit shown must be matched for the specific oscillator. contact the oscillator manufacturer to obtain circuit constants. xi xo cd rd cg figure 4-2 clock generation using the internal oscillator and external oscillator 4. explanation of functions 6 epson S1R72V18 data sheet (rev. 1.00) 4.4 power management this lsi includes a power management function featuring two power management states for each port, sleep and active, together with the cpu_cut power management state common for the chip. (see figure 4-3.) all function blocks are active in the active st ate, whereas only the bare minimum circuits necessary for restarting from standby mode are ac tive in sleep state. cpu_cut mode minimizes power consumption attributable to the cpu-i/f input buffer. port 0 active port 1 active active inactive cpu -i/f fifo sie_0 mtm_0 sie_1 mtm_1 osc pll60 * the cpu-i/f is only partially active in sleep state. the asynchronous access register can be accessed. ** cpu-i/f operation is suspended in cpu_cut to minimize power consumption attributable to the i/o input buffer. port 0 active port 1 sleep cpu -i/f fifo sie_0 mtm_0 sie_1 mtm_1 osc pll60 port 0 sleep port 1 active cpu -i/f fifo sie_1 mtm_1 sie_0 mtm_0 osc pll60 port 0 sleep port 1 sleep cpu -i/f * fifo sie_1 mtm_1 sie_0 mtm_0 osc pll60 port 0 cpu_cut port 1 cpu_cut cpu -i/f ** fifo sie_1 mtm_1 sie_0 mtm_0 osc pll60 figure 4-3 power management states 4. explanation of functions S1R72V18 data sheet (rev. 1.00) epson 7 4.5 cpu-i/f this lsi is connected to the cpu via a 16-bit interface. endian settings can be set as big endian or little endian in 16-bit steps. fo r big endian, registers with even addresses can be accessed above the bus (cd[15:8]), while registers with odd addresses can be accessed below the bus (cd[7:0]). for little endian, registers with even addresses can be accessed below the bus (cd[7:0]), while registers with odd addresses can be accessed above the bus (cd[15:8]). the bus mode can be set to either strobe mode for access using high/low strobe (xwrh/xwrl) or byte enable mode for access using high/low byte enable (xbeh/xbel) for writing the first or last 8 bits. endian and bus mode is set by the cpuif_mode register immediately after reset cancelling. the cpu-i/f on this lsi includes 1-ch dm a (slave) for each port (2-ch in total). the registers that can be accessed will depend on the power management state. for details, refer to the lsi technical manual. 4.6 usb device i/f this lsi supports high-speed specification usb device functions complying with the usb 2.0 (universal serial bus specification revision 2.0) standards. 4.6.1 speed mode and transfer type this lsi?s u sb device function supports hs (480 mbps) and fs (12 mbps) speed modes. the speed mode is set automatically by the sp eed negotiation performed when resetting the bus. for example, hs transfer mode is sel ected automatically by speed negotiation if connected to a usb host that supports hs speed mode. in addition, the register can be set so that fs speed mode is always selected in speed negotiations. all transfer types stipulated under the usb 2.0 standard are supported, including control transfers (endpoint 0), bulk transfers, inte rrupt transfers, and is ochronous transfers. 4.6.2 resources 4.6.2.1 endpoint this lsi?s u sb device function includes endpoint 0 and five standard endpoints. endpoint 0 supports control transfers. the standard endpoints support bulk transfers, interrupt tran sfers, and isochronous transfers. the standard endpoint numbers, maximum packet size, and transfer direction (in/out) can be set as desired. 4. explanation of functions 8 epson S1R72V18 data sheet (rev. 1.00) 4.6.2.2 fifo the lsi ports include 4.5 kb of fifo for use with usb data transfers. this forms the data transfer route with usb. the fifo capacity of each endpoint can be assigned as desired by the soft ware. for example, performance can be improved by assigning a sufficient size fifo area to the endpoints for bulk transfers. 4.6.3 data flow endpoints are assigned to usb fifo areas on a one-to-one basis, and responses are returned to usb transactions automatical ly, depending on effective usb fifo free capacity (for out transfers) or effective data quantity (for in transfers). this means the software does not need to be directly involv ed in individual transactions, allowing usb data transfers to be controlled as data flows at the usb fifo. usb fifo endpoint usb host i n t o k e n d a t a q u a n t i t y < m a x p k t s i z e n a k h a n d s h a k e i n t o k e n d a t a q u a n t i ty > = m a x p k ts i z e d a t a p a c k e t a c k h a n d s h a k e cpu w r i t e f i f o _ e m p t y f i f o _ e m p t y w r i t e i n t o k e n d a t a q u a n t i t y < m a x p k t s i z e write read in transaction (nak response) in transaction (data reply) in transaction (nak response) t r a n s f e r s e n t n a k h a n d s h a k e f i f o _ f u l l f i f o _ f u l l i n t o k e n d a t a q u a n t i t y > = m a x p k t s i z e d a t a p a c k e t a c k h a n d s h a k e in transaction (data reply) empty data figure 4-4 typical data flow (with fifo assigned for maxpktsize and in transfer) 4. explanation of functions S1R72V18 data sheet (rev. 1.00) epson 9 usb fifo endpoint usb host p i n g t o k e n f r e e q u a n t i t y > = m a x p k t s i z e a c k h a n d s h a k e o u t t o k e n cpu f i f o _ e m p t y p i n g t o k e n f r e e q u a n t i t y < m a x p k t s i z e read write ping transaction (ack response) out transaction (data receipt) ping transaction (nak response) t r a n s f e r r e c e i v e d n a k h a n d s h a k e f i f o _ f u l l f i f o _ e m p t y p i n g t o k e n f r e e q u a n t i t y > = m a x p k t s i z e ping transaction (ack response) empty data d a t a p a c k e t n y e t h a n d s h a k e r e a d a c k h a n d s h a k e note: ping transactions are performed only in high speed mode. figure 4-5 typical data flow (with fifo assigned for maxpktsize and out transfer) 4.6.4 usb device port external circuits the lsi usb port 0 has internal fs and hs device termination resistors, eliminating the need for the components normally used to adjust impedance. this allows a dp/dm line to be connected directly between the lsi terminal and the connector. note that the appropriate components must be used to ensure static electricity protection and to implement emi precautions. the vbus terminal uses a 5 v input and does not require external voltage conversion. a protection circuit is recommended, since certain commercially-available usb host and hub products may apply surge voltages exceeding vbus ratings. refer to the separately provided pcb desi gn guidelines for s1r72v series usb 2.0 hi-speed. 4. explanation of functions 10 epson S1R72V18 data sheet (rev. 1.00) 4.7 usb host i/f the lsi usb port 0 and port 1 support high-speed specification usb host functions complying with the usb 2.0 (universal serial bus specification revision 2.0) standards. 4.7.1 speed mode and transfer type this lsi?s u sb host function supports hs (480 mbps), fs (12 mbps) and ls (1.5 mbps) speed modes. the speed mode is automatically set by speed negotiations performed on resetting the bus. all transfer types stipulated in the usb 2.0 standard are supported, including control transfers, bulk transfers, interrupt tr ansfers, and isochronous transfers. 4.7.2 resources 4.7.2.1 channels in the lsi usb host functions, sets of register settings for transfers with end points on a one-to-one basis are called channels. the lsi usb host function features one dedicated channel for control transfers, one dedicated channel for bulk transfers, and four general channels that support bulk transfers, interrupt transfers, and isochronous transfers. the endpoint number, maximum packet size, and transfer direction (in/out) can be set as desired for all channels. transfers are also possible for a numbe r of endpoints exceeding the channel number using software-based time-multiplexing for the channels. 4.7.2.2 fifo each port on the lsi includes 4.5 kb of fifo for use with usb data transfers. this forms the data transfer route wi th usb. the fifo capacity for each channel can be assigned as desired by the software. for example, to improve performance, assign a fifo area of ad equate size to the endpoints for bulk transfers. 4.7.3 data flow the cha nnels are assigned to fifo areas on a one-to-one basis. transactions are sent automatically to usb, depending on the fifo effective free capacity (for in transfers) or effective data quantity (for out transfers). the software does not need to be directly involved in individual transactions, allowing usb data transfers to be controlled as data flow at the fifo. 4. explanation of functions S1R72V18 data sheet (rev. 1.00) epson 11 fifo cpu channel usb device n a k h a n d s h a k e i n t o k e n f r e e q u a n t i t y > = m a x p k t s i z e f r e e q u a n t i t y < m a x p k t s i z e t r a n s f e r r e c e i v e d f r e e q u a n t i t y > = m a x p kt s i z e f i f o _ e m p t y read write f i f o _ f u l l f i f o _ e m p t y empty data r e a d d a t a p a c k e t i n t o k e n a c k h a n d sh a k e i n t o k e n n a k h a n d s h a k e in transaction (nak response) in transaction (nak response) in transaction (data reply) figure 4-6 typical data flow (with fifo assigned for maxpktsize and in transfer) fifo channel usb device d a t a q u a n t i t y < m a x p k t s i z e d a t a q u a n t i t y > = m a x p k t s i z e cpu w r i t e f i f o _ e m p t y f i f o _ e m p t y w r i t e d a t a q u a n t i t y < m a x p k t s i z e write read t r a n s f e r s e n t f i f o _ f u l l f i f o _ f u l l d a t a q u a n t i t y > = m a x p k t s i z e o u t t o k e n d a t a p a c k e t a c k h a n d s h a k e o u t t o k e n d a t a p a c ke t a c k h a n d s h a k e empty data out transaction out transaction t r a n s f e r s e n t figure 4-7 typical data flow (with fifo assigned for maxpktsize and out transfer) 4. explanation of functions 12 epson S1R72V18 data sheet (rev. 1.00) 4.7.4 usb host port external circuits the lsi ports have internal usb host termination resistors, including an hs termination resistor, eliminating the need for the external components normally used to adjust impedance. this allows a dp/dm line to be connected between the lsi terminal and the connector. note that the appropriate components must be used to ensure static electricity protection and to implement emi precautions. an external vbus control component is required for the vbus. 4.8 fifo each port on the lsi includes 4.5 kb of usb fifo for use with usb data transfers. the usb fifo capacity for each endpoint or channel can be assigned as desired using the register settings. transfers are possible between the us b-i/f and cpu-i/f via the usb fifo. 5. terminal layout diagrams S1R72V18 data sheet (rev. 1.00) epson 13 5. terminal layout diagrams vss cd15 cd14 cd13 cd12 cd11 lvdd cd10 cd9 cd8 cd7 cd6 cvdd cd5 cd4 cd3 cd2 cd1 cd0 atpgen 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 burnin 61 40 xda c k1 lvdd 62 39 xdre q 1 v ss 63 38 xda c k0 r1 _ 1 64 37 xdre q 0 v ss 65 36 lvdd hvdd 66 35 xwrl dm _ 1 67 34 xwrh v ss 68 33 xrd dp _ 1 69 32 x cs hvdd 70 31 xint lvdd 71 30 vss v ss 72 29 c a9 hvdd 73 28 c a8 v busflg _ 74 27 c a7 v busen _ 1 75 26 c a6 v busflg _ 76 25 c vdd v busen _ 0 77 24 c a5 vss 78 23 ca4 lvdd 79 22 c a3 xi 80 21 ca2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 xo vss lvdd vss r1_0 vss hvdd dm_0 vss dp_0 hvdd vbus_0 lvdd vss lvdd cvdd xreset xbel testen ca1 figure 5-1 qfp package terminal layout diagram 1234567891011 a nc xi vss hvdd lvdd dp_1 dm_1 r1_1 lvdd vss nc a b xo lvdd vbusflg_0 vbusflg_1 vss hvdd vss vss burnin cd15 vss b c lvdd vss vbusen_0 vbusen_1 vss vss vss vss vss cd14 cd13 c d r1_0 vss vss vss vss vss vss vss vss cd12 cd11 d e dm_0 vss vss vss vss vss vss vss cd9 cd10 lvdd e f dp_0 hvdd vbus_0 vss vss vss vss vss cd6 cd7 cd8 f g lvdd vss vss vss vss vss vss vss cd4 cd5 cvdd g h vss lvdd vss vss vss vss vss vss atpgen cd2 cd3 h j cvdd xreset testen ca5 ca9 xcs xwrl vss vss cd1 cd0 j k xbel ca1 ca3 ca6 ca7 xint xwrh xdreq0 xdreq1 vss vss k l nc ca2 ca4 cvdd ca8 vss xrd lvdd xdack0 xdack1 nc l 1234567891011 top view figure 5-2 bga package terminal layout diagram 6. terminal functions 14 epson S1R72V18 data sheet (rev. 1.00) 6. terminal functions osc pin ball name i/o reset terminal type terminal description 80 a2 xi in - analog internal oscill ator circuit input (12 mhz, 24 mhz) 1 b1 xo out - analog internal oscillator circuit output test pin ball name i/o reset terminal type terminal description 19 j3 testen in - - test terminal (set to low) 41 h9 atpgen in - - test terminal (set to low) 61 b9 burnin in - - test terminal (set to low) usb port 0 pin ball name i/o reset terminal type terminal description 5 d1 r1_0 in - analog internal operation reference current setting terminal (connect 6.2 k ? 1% resistor between vss) 10 f1 dp_0 bi hi-z analog usb port 0, data line (data +) 8 e1 dm_0 bi hi-z analog usb port 0, data line (data -) 76 b3 vbusflg_0 in (pu) schmitt (pu) usb power switch fault detection signal (1: normal, 0: error) 77 c3 vbusen_0 out lo 2ma usb power switch control signal 12 f3 vbus_0 in (pd) (pd) usb device bus detection signal pd: pull down pu: pull up usb port 1 pin ball name i/o reset terminal type terminal description 64 a8 r1_1 in - analog internal operation reference current setting terminal (connect 6.2 k ? 1% resistor between vss) 69 a6 dp_1 bi hi-z analog usb port 1, data line (data +) 67 a7 dm_1 bi hi-z analog usb port 1, data line (data -) 74 b4 vbusflg_1 in (pu) schmitt (pu) usb power switch fault detection signal (1: normal, 0: error) 75 c4 vbusen_1 out lo 2ma usb power switch control signal pd: pull down pu: pull up 6. terminal functions S1R72V18 data sheet (rev. 1.00) epson 15 cpu i/f pin ball name i/o reset terminal type terminal description bus mode ? 16bit strobe mode 16bit be mode 17 j2 xreset in - - reset signal 33 l7 xrd in - - read/strobe 35 j7 xwrl (xwr) in - - writ e/strobe (lower) write/strobe 34 k7 xwrh (xbeh) in - - write/strobe (upper) high-byte enable 32 j6 xcs in - - chip select signal 31 k6 xint out high 2ma (tri-state) interrupt output signal 37 k8 xdreq0 out high 2ma port 0 dma request 38 l9 xdack0 in - - port 0 dma acknowledge 39 k9 xdreq1 out high 2ma port 1 dma request 40 l10 xdack1 in - - port 1 dma acknowledge 18 k1 xbel in - - set to high or low low-byte enable 20 k2 ca1 in - - 21 l2 ca2 in - - 22 k3 ca3 in - - 23 l3 ca4 in - - 24 j4 ca5 in - - 26 k4 ca6 in - - 27 k5 ca7 in - - 28 l5 ca8 in - - 29 j5 ca9 in - - cpu bus address 42 j11 cd0 bi hi-z 2ma 43 j10 cd1 bi hi-z 2ma 44 h10 cd2 bi hi-z 2ma 45 h11 cd3 bi hi-z 2ma 46 g9 cd4 bi hi-z 2ma 47 g10 cd5 bi hi-z 2ma 49 f9 cd6 bi hi-z 2ma 50 f10 cd7 bi hi-z 2ma 51 f11 cd8 bi hi-z 2ma 52 e9 cd9 bi hi-z 2ma 53 e10 cd10 bi hi-z 2ma 55 d11 cd11 bi hi-z 2ma 56 d10 cd12 bi hi-z 2ma 57 c11 cd13 bi hi-z 2ma 58 c10 cd14 bi hi-z 2ma 59 b10 cd15 bi hi-z 2ma cpu data bus the xint terminal can be set to 1/0 or hi-z/0 mode, depending on register settings. pd: pull down pu: pull up 6. terminal functions 16 epson S1R72V18 data sheet (rev. 1.00) power pin ball name voltage terminal description 7, 11, 66, 70, 73 f2, b6, a4 hvdd 3.3v usb i/o power supply 16, 25, 48 j1, l4, g11 cvdd 1.8 to 3.3 v cpu i/f i/o power supply 3, 13, 15, 36, 54, 62, 71, 79 c1, g1, h2, l8, e11, a9, a5, b2 lvdd 1.8v osc i/o, test i/o, and internal power supply 2, 4, 6, 9, 14, 30, 60, 63, 65, 68, 72, 78 a3, a10, b5, b7, b8, b11, c2, c5, c6, c7, c8, c9, d2, d3, d4, d5, d6, d7, d8, d9, e2, e3, e4, e5, e6, e7, e8, f4, f5, f6, f7, f8, g2, g3, g4, g5, g6, g7, g8, h1, h3, h4, h5, h6, h7, h8, j8, j9, k10, k11, l6 vss 0v gnd - a1, a11, l1, l11 n.c. 0v nc terminal (connect to gnd) 7. electrical characteristics S1R72V18 data sheet (rev. 1.00) epson 17 7. electrical characteristics 7.1 absolute maximum ratings item symbol rating units hvdd vss ? 0.3 to 4.0 v cvdd vss ? 0.3 to 4.0 v power supply voltage lvdd vss ? 0.3 to 2.5 v hvi vss ? 0.3 to hvdd + 0.5 v cvi * 1 vss ? 0.3 to cvdd + 0.5 v vvi * 2 vss ? 0.3 to 6.0 v input voltage lvi * 3 vss ? 0.3 to lvdd + 0.5 v hvo vss ? 0.3 to hvdd + 0.5 v output voltage cvo * 1 vss ? 0.3 to cvdd + 0.5 v output current/terminal iout 10 ma storage temperature tstg -65 to 150 c * 1 cpu-if * 2 vbus_0 * 3 xi, testen, atpgen, burnin 7.2 recommended operating conditions item symbol min typ max units hvdd 3.00 3.30 3.60 v cvdd 1.65 - 3.60 v power supply voltage lvdd 1.65 1.80 1.95 v hvi -0.3 - hvdd+0.3 v cvi * 1 -0.3 - cvdd+0.3 v vvi * 2 -0.3 - 6.0 v input voltage lvi * 3 -0.3 - lvdd+0.3 v ambient temperature ta -40 25 85 c * 1 cpu-i/f * 2 vbus_0 * 3 xi, testen, atpgen, burnin turn on power to the ic in the sequence shown below. lvdd (internal) hvdd, cvdd (io section) likewise, turn off power to the ic in the sequence shown below. hvdd, cvdd (io section) lvdd (internal) note: avoid leaving the hvdd or cvdd on continuously (for more than 1 second) when the lvdd is off, as doing so may affect chip reliability. 7. electrical characteristics 18 epson S1R72V18 data sheet (rev. 1.00) 7.3 dc characteristics 7.3.1 current consumption item symbol condition min typ max units power supply feed current * 1 power supply current iddh hvdd = 3.3v(typ), hvdd = 3.6v(max) - 17.3 26.0 ma iddch cvdd = 3.3v(typ), cvdd = 3.6v(max) - 2.0 6.0 ma iddcl cvdd = 1.8v(typ), cvdd = 1.95v(max) - 0.8 2.3 ma iddl lvdd = 1.8v(typ), lvdd = 1.95v(max) - 60.9 92.0 ma stationary current * 2 power supply current idds vin = hvdd,cvdd,lvdd or vss hvdd = 3.6v cvdd = 3.6v lvdd = 1.95v - - 40 a input leakage input leakage current il hvdd = 3.6v cvdd = 3.6v lvdd = 1.95v hvih = hvdd cvih = cvdd lvih = lvdd vil = vss -5 - 5 a * 1: the ?typ? values are measured when transferring da ta between two devices connected to each port of 72v18 working as usb host. * 2: stationary current with ta = 25 c and both terminals in input mode. 7. electrical characteristics S1R72V18 data sheet (rev. 1.00) epson 19 current consumption measurements for individual power management states using seiko epson operating conditions (ta = 25c) item condition min typ max units cpu_cut cpu bus operation * 1 * 2 power supply power hvdd = 3.3v cvdd = 3.3v lvdd = 1.8v - 17 - w sleep cpu bus operation * 1 * 2 power supply power hvdd = 3.3v cvdd = 3.3v lvdd = 1.8v - 212 - w active/sleep (usb ? cpu-i/f) * 3 power supply power hvdd = 3.3v cvdd = 3.3v lvdd = 1.8v - 101 - mw active/active (usb ? cpu-i/f) * 4 power supply power hvdd = 3.3v cvdd = 3.3v lvdd = 1.8v - 172 - mw * 1: when the cpu is accessing memory (e.g., sram or rom) connected to the cpu bus. * 2: excluding current consumption attributable to dp pull-up resistor inside S1R72V18 (approx. 200 a). * 3: when transferring data connected to a pc as a usb device. * 4: with both ports transferring data between a memory connected to the cpu bus and usb-hdd with usb-hdd connected with the lsi as the usb host . 7. electrical characteristics 20 epson S1R72V18 data sheet (rev. 1.00) 7.3.2 input characteristics item symbol condition min typ max units input characteristics (lvcmos) terminal names: ca[8:1], cd[15:0], xcs, xrd, xwrl, xwrh, xbel, xdack_0, xdack_1, xreset h level input voltage vih2 cvdd = 3.6v 2.2 - - v l level input voltage vil2 cvdd = 3.0v - - 0.8 v h level input voltage vih3 cvdd = 1.95v 1.27 - - v l level input voltage vil3 cvdd = 1.65v - - 0.57 v schmitt input characteristics terminal names: vbusflg_0, vbusflg_1 h level trigger voltage vt+ hvdd = 3.6v 1.4 - 2.7 v l level trigger voltage vt- hvdd = 3.0v 0.6 - 1.8 v hysteresis voltage v hvdd = 3.0v 0.3 - - v schmitt input characteristics (usb fs) terminal names: dp_0, dm_0, dp_1, dm_1 h level trigger voltage vt+(usb) hvdd = 3.6v 1.1 - 1.8 v l level trigger voltage vt-(usb) hvdd = 3.0v 1.0 - 1.5 v hysteresis voltage v(usb) hvdd = 3.0v 0.1 - - v input characteristics (usb fs differential) terminal names: dp_0 + dm_0 pair, dp_1 + dm_1 pair differential input sensitivity vds(usb) hvdd = 3.0v differential input voltage = 0.8 v to 2.5 v - - 0.2v v input characteristics (vbus) terminal name: vbus_0 h level trigger voltage vt+(vbus) hvdd = 3.6v 1.86 - 2.85 v l level trigger voltage vt-(vbus) hvdd = 3.0v 1.48 - 2.23 v hysteresis voltage v(vbus) hvdd = 3.0v 0.31 - 0.64 v input characteristics terminal name: vbus_0 pull-down resistor rpldv vih = 5.0v 110 125 150 k 7. electrical characteristics S1R72V18 data sheet (rev. 1.00) epson 21 7.3.3 output characteristics item symbol condition min typ max units output characteristics terminal names : cd[15:0], xdreq_0, xdreq_1, xint h level output voltage voh1 cvdd = 3.0v ioh = -2ma cvdd-0.4 - - v l level output voltage vol1 cvdd = 3.0v iol = 2ma - - vss+0.4 v h level output voltage voh2 cvdd = 1.65v ioh = -1ma cvdd-0.4 - - v l level output voltage vol2 cvdd = 1.65v iol = 1ma - - vss+0.4 v output characteristics terminal names:vbusen_0, vbusen_1 h level output voltage voh4 hvdd = 3.0v ioh = -2ma hvdd-0.4 - - v l level output voltage vol4 hvdd = 3.0v iol = 2ma - - vss+0.4 v output characteristics (usb fs) terminal names: dp_0, dm_0, dp_1, dm_1 h level output voltage voh(usb) hvdd=3.0v 2.8 - - v l level output voltage vol(usb) hvdd=3.6v - - 0.3 v output characteristics (usb hs) terminal names: dp_0, dm_0, dp_1, dm_1 h level output voltage vhsoh (usb) hvdd = 3.0v 360 - - mv l level output voltage vhsol (usb) hvdd = 3.6v - - 10.0 mv output characteristics term inal names: cd[15:0], xint off-state leakage current ioz cvdd = 3.6v cvoh = cvdd vol = vss -5 - 5 a 7. electrical characteristics 22 epson S1R72V18 data sheet (rev. 1.00) 7.3.4 terminal capacitance item symbol condition min typ max units terminal capacitance terminal name: all input terminals input terminal capacitance ci f = 10mhz hvdd = cvdd = lvdd = vss - - 8pf pf terminal capacitance terminal name: all output terminals output terminal capacitance co f = 10mhz hvdd = cvdd = lvdd = vss - - 8pf pf terminal capacitance terminal name: all input/ output terminals (except dp_0, dm_0, dp_1, dm_1) input/output terminal capacitance 1 cio1 f = 10mhz hvdd = cvdd = lvdd = vss - - 8pf pf terminal capacitance terminal names: dp_0, dm_0, dp_1, dm_1 input/output terminal capacitance 2 cio2 f = 10mhz hvdd = cvdd = lvdd = vss - - 8pf pf 7. electrical characteristics S1R72V18 data sheet (rev. 1.00) epson 23 7.4 ac characteristics 7.4.1 reset timing xreset treset code description min typ max units treset reset pulse width 40 - - ns 7.4.2 clock timing xi tcyc tcycl tcych code description min typ max units tcyc clock cycle (clkselect=0) 11.999 12 12.001 mhz tcyc clock cycle (clkselect=1) 23.998 24 24.002 mhz tcych tcycl clock duty 45 - 55 % 7. electrical characteristics 24 epson S1R72V18 data sheet (rev. 1.00) 7.4.3 cpu/dma i/f access timing 7.4.3.1 specifications fo r cvdd = 1.65 v to 3.6 v xdreq0/1(o) xdack0/1(i) xcs(i) xrd(i) cd(o) valid tcas ca(i) xwrh/l(i) xwr cd(i) code tcas tccs min 6 6 typ - - max - - unit ns ns tcch tcah 6 6 - - - - ns ns trbd 1 - - ns trdf - - 40 ns trdh 2 - - ns trbh - - 10 ns twds twdh - 6 - - 10 - ns ns tdrn - - 35 ns tdaa tdan 6 6 - - - - ns ns tcah tccs tcch trbd trdf trdh trbh twds twdh tdrn tdaa tdan write read tras tras 45 - - ns twas 45 - - ns twas trng twng twcy trcy trcy 80 - - ns trng 25 - - ns 80 - - ns twcy 25 - - ns twng xbeh/l(i) twbs twbh twbs twbh 6 6 - - - - ns ns write byte enable hold time (c l =30pf) item address setup time address hold time xcs setup time xcs hold time read data output start time read data confirmation time read data hold time read data output delay time write data delay acknowledge time write data hold time (after strobe negation) xdreq0/1 negate delay time xdack0/1 setup time xdack0/1 hold time read strobe assert time write strobe assert time read cycle read strobe negate time write cycle write strobe negate time write byte enable setup time twah 50 - - ns write data hold time (after strobe assertion) twah tccn tccn 15 - - ns xcs negate time (for cpuif mode only * ) * refer to ?technical manual? for details of cpuif mode settings. 7. electrical characteristics S1R72V18 data sheet (rev. 1.00) epson 25 7.4.3.2 specific ations when limited to cvdd = 3.0 v to 3.6 v (relaxed specifications) xdreq0/1(o) xdack0/1(i) xcs(i) xrd(i) cd(o) valid tcas ca(i) xwrh/l(i) xwr cd(i) code tcas tccs min 6 6 typ - - max - - unit ns ns tcch tcah 6 6 - - - - ns ns trbd 1 - - ns trdf - - 35 ns trdh 2 - - ns trbh - - 10 ns twds twdh - 6 - - 10 - ns ns tdrn - - 30 ns tdaa tdan 6 6 - - - - ns ns tcah tccs tcch trbd trdf trdh trbh twds twdh tdrn tdaa tdan write read tras tras 40 - - ns twas 40 - - ns twas trng twng twcy trcy trcy 75 - - ns trng 25 - - ns 75 - - ns twcy 25 - - ns twng xbeh/l(i) twbs twbh twbs twbh 6 6 - - - - ns ns write byte enable hold time (c l =30pf) item address setup time address hold time xcs setup time xcs hold time read data output start time read data confirmation time read data hold time read data output delay time write data delay acknowledge time write data hold time (after strobe negation) xdreq0/1 negate delay time xdack0/1 setup time xdack0/1 hold time read strobe assert time write strobe assert time read cycle read strobe negate time write cycle write strobe negate time write byte enable setup time twah 50 - - ns write data hold time (after strobe assertion) twah tccn 15 - - ns xcs negate time (for cpuif mode only * ) tccn * refer to ?technical manual? for details of cpuif mode settings. 7. electrical characteristics 26 epson S1R72V18 data sheet (rev. 1.00) 7.4.4 usb i/f timing complies with the usb 2.0 standard (universal serial bus specification revision 2.0 released on april 27, 2000). 8. connection examples S1R72V18 data sheet (rev. 1.00) epson 27 8. connection examples 8.1 cpu i/f connection example ca[8:1] xbel data[15:0] xcs xrd xwrh/xbeh xwrl/xwr xdreq_0 * 1 xdack_0 * 2 xdreq_1 * 1 xdack_1 * 2 xint address[8:1] 16-bit cpu (xwrh/xwrl) connection example data[15:0] xcs xrd xwrh xwrl xdreq0 xdack0 xdreq1 xdack1 xint * 1: open when dma is not used * 2: set to inactive level when dma is not used ca[8:1] xbel data[15:0] xcs xrd xwrh/xbeh xwrl/xwr xdreq_0 * 1 xdack_0 * 2 xdreq_1 * 1 xdack_1 * 2 xint address[8:1] 16-bit cpu (xbeh/xbel) connection example data[15:0] xcs xrd xbeh xwr xdreq0 xdack0 xdreq1 xdack1 xint xbel * 1: open when dma is not used * 2: set to inactive level when dma is not used 8. connection examples 28 epson S1R72V18 data sheet (rev. 1.00) 8.2 usb i/f connection example refer to the separately provided s1r72v series usb 2.0 hi-speed pcb design guidelines. 9. product codes S1R72V18 data sheet (rev. 1.00) epson 29 9. product codes table 9-1 product codes product code product type S1R72V18b10 **** pfbga10ux121 package S1R72V18f14 **** qfp14-80 package 10. external dimension diagrams 30 epson S1R72V18 data sheet (rev. 1.00) 10. external dimension diagrams refer to the pfbga10ux121 and qfp14-80 package drawings at the end of this document. revision history revision history revision details date rev. page (old issue) type details 07/10/12 0.79 all pages new new issue 5 revision ?the chipreset.allreset bit for each port is used to reset the lsi,? ?correction)the chipreset.allreset bit initializes all circuits except the cpuif_mode register,? 08/04/01 0.90 24 revision added the rated value in cells previously commented as ?t.b.d? 18,19 revision added the rated value in cells previously commented as ?t.b.d? 18 revision ?typ values are measured with the usb-hdd connected as the usb host and when transferring data between the ide-hdd and usb-hdd? ?the ?typ? values are measured when transferring data between two devices connected to each port of 72v18 working as usb host? 08/11/21 1.00 19 revision ?with one port transferring data between a memory connected to the cpu bus and usb-hdd with usb-hdd connected with the lsi as the usb host? ?when transferring data connected to a pc as a usb device? blank below this line international sales operations america epson electronics america, inc. 2580 orchard parkway san jose , ca 95131,usa phone: +1-800-228-3964 fax: +1-408-922-0238 europe epson europe electronics gmbh riesstrasse 15 muenchen bayern, 80992 germany phone: +49-89-14005-0 fax: +49-89-14005-110 asia epson (china) co., ltd. 7f, jinbao bldg.,no.89 jinbao st., dongcheng district, beijing 100005, china phone: +86-10-6410-6655 fax: +86-10-6410-7320 |
Price & Availability of S1R72V18
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |