View SLA6868MLF2451_7280968.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

introduction the sla6860m and sma6860m series consists of inverter power module (ipm) devices that integrate within a single, compact package: power mosfets, pre-driver ics, and fast recovery diodes. these products are especially suitable for driving the inverters of low-capacity motors, such as those used in 100 to 200 v fans or pumps for air conditioners. features and benefits include the following: ? three built-in bootstrap fast recovery diodes (frd), each with current-limiting resistor, and capable of withstanding high voltages: 600 v at 1 a ? overcurrent limiting (ocl) function, with fault signal output and shutdown input terminal; when the user- determined maximum current level is exceeded, pwm on-off cycling is initiated to effectively limit current ? built-in overcurrent protection (ocp) function; when an overcurrent condition, such as an output short circuit, is detected, the internal high-side and low-side logic ics shut down the output driver gates and issue a fault signal ? optional automatic shutdown of high-side and low-side gates if an abnormal condition occurs (overtemperature, overcurrent, undervoltage on control power supply, and so forth); enabled by connecting together the sd1 and sd2 terminals ? built-in overtemperature protection for both high-side and low-side circuits; thermal shutdown (tsd) occurs when the temperature of the logic chips exceed a user- determined value, the internal high-side and low-side logic ics shut down the output driver gates and issue a fault signal high voltage sla6860m and sma6860m series driver ics for 3-phase dc motor applications figure 1. sma6860m series packages are sips, offering compact configurations both with heatsink pad (leadforms 2171 and 2175) and without (leadforms 2451 and 2452). both horizontal mount and vertical mount are available. product information ? built-in undervoltage lockout (uvlo) protection for each control power supply, vcc1, vcc2, and vbx; when voltage falls below a set value, the gates are shut down and vcc1 and vcc2 output an alarm signal ? alarm signal (shutdown) output when protection circuits enable; high-side faults (uvlo and tsd) are signaled on the sd1 terminal, low-side faults (tsd, ocp, and uvlo) are signaled on the sd2 terminal leadform 2171 leadform 2175 leadform 2452 contents introduction 1 functional description 2 terminal descriptions 3 protection functions 8 typical applications 12 protection function timing 18 application circuit recommendations 19 electrical characteristics data 19 leadform 2451 product lineup* type mosfet rating application input voltage (vac) heat- sink sma6861m 250 v / 2 a fan motor, pump 230 ? sma6862m 500 v / 1.5 a fan motor, pump 230 ? sma6863m 500 v / 2.5 a fan motor, pump 230 ? sla6866m 250 v / 2 a fan motor, pump 230 yes sla6867m 500 v / 1.5 a fan motor, pump 230 yes sla6868m 500 v / 2.5 a fan motor, pump 230 yes *sma6861m : sla6866m, sma6862m : sla6867m, and also sma6863m : sla6868m are electrically identical respectively. 28610.14, rev. 2
2 figure 2. sla6860m/sma6860m series phase block diagram. these devices support high-side and low-side three-phase mosfet output drivers. low-side driver uvlo uvlo uvlo uvlo input logic input logic (ocp reset ) uvlo thermal shutdown sd1 vcc1 vb1 vb2 vb3 vbb u v w1 w2 ls 2 ls 1 sd2 com2 lin3 lin2 lin1 vcc 2 com1 hin3 hin2 hin1 high-side level shift driver ocl ocp and ocl rc ocp ? power mosfets incorporating fast recovery diodes (frd) provide low losses in comparison with igbt technology ? use of sip 24-pin power package, proven in other high- volume sanken product lines, with l-bend and zigzag leadforms available; l-bends formed with precautions to ensure device integrity; zigzags for stable mounting; heatsink tab option functional description the functional block diagram for one of the three device phases is shown in figure 2. high voltage power and 15 vdc are input between vbb and ls1/ls2, between vcc1 and com1, and between vcc2 and com2. the on/off signals of the power mosfets are operated by six signals: hin1, hin2, hin3, lin1, lin2, and lin3. these input signals are positive logic (the mosfet turns on at v xinx = high). the boot capacitors are con- nected between vb1 and u, vb2 and v, and vb3 and w1, as the high voltage power source. the protection functions, including overcurrent protection (enable at detected short circuit, and so forth), overtemperature protection (at abnormal ambient temperature, overload, and so forth), and undervoltage of low control power supply voltage (at instantaneous fall, and so forth) are built-in and when any of these functions is operated, it can be monitored at the correspond- ing output terminal. the current limiter (ocl) signal is provided as a control signal, and when the current flowing across the shunt resistor exceeds the typical limit value, the ocl terminal turns on. current limit- ing can be enabled by connecting this signal to the sd1 terminal (for high-side limiting) or to the sd2 terminal (for low-side limiting). allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
3 terminal descriptions a summary description of the function of the various terminals is given in the terminal list table. pin 1 for each package appears in figure 3. this section provides detailed functional descriptions of the individual pins. vbb this is the terminal for the main power supply. for supply- ing the sma6861m, v bb should be 200 vdc or lower and in other products, 400 vdc or lower. to suppress surge voltage, a snubber capacitor (0. 01 to 0.1 f) and an electrolytic capacitor should be connected to the device by traces having the shortest length practicable. if the trace lengths are long, surge voltages will be increased. it should be verified that surge voltage does not exceed the breakdown voltage of the mosfets internal to the device itself. u, v, w1, and w2 these are the output terminals connected to the motor. w1 and w2 should be connected together externally, and are used in short circuit events. ls1 and ls2 these are the source terminals for the low-side power mosfets. ls1 and ls2 should be connected together externally. when a shunt resistor is connected to this terminal, the lengths of the traces should be as short as practicable. if the trace lengths are long, malfunctions due to noise are likely to occur. vcc1 and vcc2 these are the power supply terminals of the built-in pre-driver ics. vcc1 and vcc2 should be should be connected together externally. in order to prevent malfunctions due to noise on the power supply lines, a ceramic bypass capaci- tor (0.01 to 0.1 f) should be mounted near the terminals. note: if v ccx exceeds 20 v, permanent damage may occur. it is recommended to add a zener diode (v z = 18 to 20 v) to protect against such surge voltages. the control power supply undervoltage protection circuit is inte- grated with vcc1 and vcc2. the supplied voltage should not be allowed to drop below the rated threshold voltage of vcc1 and vcc2. terminal list table number name function 1 vb1 high side bootstrap terminal (u phase) 2 vb2 high side bootstrap terminal (v phase) 3 vb3 high side bootstrap terminal (w phase) 4 vcc1 high side logic supply voltage 5 sd1 high side shutdown input and uvlo fault signal output 6 com1 high side logic gnd terminal 7 hin3 high side input terminal (w phase) 8 hin2 high side input terminal (v phase) 9 hin1 high side input terminal (u phase) 10 vbb main supply voltage 11 w1 output of w phase (connect to w2 externally) 12 v output of v phase 13 w2 output of w phase (connect to w1 externally) 14 ls2 low side emitter terminal (connect to ls1 externally) 15 rc overcurrent protection hold time adjustment input terminal 16 ls1 low side emitter terminal (connect to ls2 externally) 17 ocl output for overcurrent limiting 18 lin3 low side input terminal (w phase) 19 lin2 low side input terminal (v phase) 20 lin1 low side input terminal (u phase) 21 com2 low side gnd terminal 22 sd2 low side shutdown input and overtemperature, overcurrent, and uvlo fault signals output 23 vcc2 low side logic supply voltage 24 u output of u phase allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
4 2x exposed tie bar 1.27 0.2 0.6 16.4 0.2 24.4 0.2 ?3.2 0.15 31 0.2 gate protrusion 2x gate protrusion 9.9 0.1 12.9 0.2 16 0.2 a 1.7 0.1 4.8 0.2 r1 ref 0.5 0.1 2.45 0.1 bsc b ?3.2 0.15 31.3 0.1 4.4 ref 2.2 0.6 bsc 2.2 0.6 bsc 3 0.3 bsc 0.6 +0.2 ? 0.1 branding area exposed heatsink pad 1.27 0.7 0.6 0.6 +0.15 ? 0.05 9.5 +0.7 ? 0.5 0.5 +0.15 ? 0.05 16.4 0.2 24.4 0.2 ?3.2 0.15 31 0.2 9.9 0.2 12.9 0.2 16 0.2 a 1.7 0.1 4.8 0.2 r1 ref 4.5 ref 4.5 0.7 5 0.5 2.45 0.2 bsc b ?3.2 0.15 31.3 0.2 branding area 2x gate protrusion exposed heatsink pad 2x exposed tie bar gate protrusion figure 3(a) and (b). package outline drawings. (a) lf2171 vertical mount, (b) lf2175 horizontal mount, with heatsink pads. (b) (a) allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
5 1 31 0.2 31.3 0.2 1.27 0.5 0.6 +0.15 ? 0.05 0.5 +0.15 ? 0.05 9.5 +0.7 ? 0.5 10.2 0.2 a 4 0.2 r1 ref 4.5 ref 4.5 0.5 5 0.5 1.2 0.1 bsc gate protrusion 2x gate protrusion 2x exposed tie bar figure 3 (c) and (d). package outline drawings. (c) lf2451, l-bend horizontal mount and (d) lf2452, vertical mount; no heatsink pads. 1.27 0.1 4 0.2 10.2 0.2 r1 ref 4.4 ref 2.2 0.7 bsc 2.2 0.7 bsc 3 0.5 bsc 1.2 0.1 bsc c 0.6 +0.15 ? 0.05 0.55 +0.2 ? 0.1 0.7 +0.15 ? 0.05 a 1.27 0.6 b 31 0.2 1 31.3 0.2 gate protrusion 2x gate protrusion 2x exposed tie bar (c) (d) allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
6 com1 and com2 these are the ground terminals of the built- in logic control ics. com1 and com2 should be connected together externally. because malfunctions are likely to be caused by variations in the potential at these terminals, attention should be paid to the exter- nal connections for these terminals. connections should be made such that there are no appreciable variations in potential, such as due to fluctuations in power current levels, short wiring length, or other causes. vb1, vb2, and vb3 these are the power supply terminals for driving the high-side mosfets. as shown in figure 4, three bootstrap capacitors, cbootx, should be connected, with one each between vb1 and u, vb2 and v, and vb3 and wx. because these bootstrap circuits perform independent operations, a capaci- tor is required for each phase. at start-up, the cbootx capaci- tors should be charged. cbootx should be sufficiently charged by turning on the low-side mosfet at the beginning. one 210 series resistor and one 600 v/ 1 a bootstrap diode are built in inside the device. to determine the constants for the boot- strap circuit, the following factors should be taken into account: ? what constitutes the optimal capacitance value of the bootstrap capacitor is dependent on: the driving method (modulation method and output frequency), the switching frequency (carrier frequency), the modulation rate (duty cycle), and the gate input capacitance of the mosfets. ? consider the time interval, t off , when the low-side mosfets are not on (except when the frd conducts); the longer t off becomes, the further the capacitor voltage falls; therefore, the larger the capacity required. ? in the case of 2-phase modulation or a 120 conduction system, the time interval when the mosfets are on becomes longer. ? the relationship between t off and the recommended capacitance of a cboot capacitor is shown by the following formula (given ? v 0.5 v): c bootx ( f) t off (ms) . the validity of the result yielded by this formula should be verified using the actual product. ? the control power supply undervoltage protection circuit is integrated with vb1, vb2, and vb3. the supplied voltage should not be allowed to drop below the rated threshold voltage of these terminals. hinx and linx these are the command signal inputs for directing power to the mosfets. a pull-down resistor (20 k ) is built-in for these active high inputs, and the command signals are received at the schmidt trigger circuit for the input logic (see figure 5). the input voltage is 7 v maximum; if a higher voltage is input, the circuit may be permanently damaged. adding a series resistor figure 4. connection of bootstrap capacitor. there is a separate cboot capacitor for each of the three phases. high-side drive circuit low-side drive circuit v bb cboot charge current cbootx to motor v cc vbx u,v,w lsx vbb vcc1 vcc2 figure 5. hinx and linx terminals internal equivalent circuit 5v hin lin com 2 k k 20 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
7 (100 to 1 k ) between the external system microprocessor and this device should be considered. also, a ceramic capacitor (100 to 1000 pf) and a zener diode (v z = 5. 6 to 6. 2 v) between the xinx terminals and the corresponding comx terminal should be considered. rc when the current that is flowing across the shunt resistor is excessive and the voltage of the ls terminal exceeds 1 v typical, for 2 s or longer, the device evaluates this as an overcurrent condition and initiates the overcurrent protection (ocp) function. ocp operates as follows: 1. short-circuit the sd2 terminal (open collector). 2. turn off the low-side power mosfets completely. 3. short-circuit the rc terminal. when the power mosfets are turned off, although the voltage falls below 1 v, the gate-off operation and the short-circuiting of the sd2 terminal continue for a fixed period. this period is set by an external pull-up resistor rr and capacitor cc, connected to this terminal as shown in figure 6. the relationship between the constants of rr, cc and the duration of ocp operation, t ocp , is given in the following formula (given a pull-up voltage of 5 v): t ocp ( s) = 1.2 r r (k ) c c (nf) . the application should be designed for values of r r between 33 and 390 k , and c c between 1 and 4.7 nf. in case where r r = 360 k and c c = 4.7 nf, t ocp would be approximately 2 ms. if the pull-up resistor rr becomes disconnected (open) from the rc terminal, the ocp function will not be released. when rr is short-circuited, the opc function does not operate. in case of disconnection of the capacitor cc, the duration of ocp becomes short, to release protection operation immediately. sd2 this is the terminal for fault signal output at abnormal operation, and also a shutdown command input terminal. during ocp, low-side drive circuit ic overtemperature protection, or control power supply undervoltage protection between vcc2 and com2, the transistor of the open collector circuit is turned on (see figure 7). because the sd2 terminal also plays the role of shutdown com- mand input terminal, when it is externally short-circuited between sd2 and com2, the low-side mosfets are turned off com- pletely. a filter (3.3 s typical) is integrated into the device, for the pre- vention of malfunction due to noise. a pull-up resistor, r2, with a value of 3.3 to 10 k , should be externally connected, even if the sd2 terminal is not used. in addition, a capacitor, c2, of 0.01 f or less should be connected for eliminating noise. sd1 this is the terminal for fault signal output for high-side drive circuit ic overtemperature protection, and also a shutdown command input terminal. the transistor of the open collector circuit is turned on at the operation of overtemperature protection (see figure 8). because the sd1 terminal also plays the role of shutdown command input terminal, when it is externally short-circuited between sd1 and com1, the high-side mosfets are turned off completely. furthermore, after a short-circuit between sd1 and figure 6. rc terminal internal equivalent circuit rc com2 on during ocp ocp release comparator +5 v + ? +3.5 v rr cc 50 figure 7. sd2 terminal internal equivalent circuit sd2 com2 on during ocp to shutdown +5 v r2 c2 50 filter 3.3 s allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
8 com1 is removed, the mosfets begin again to turn on at the rising edge of the hin terminal signal. a filter (3.3 s typical) is integrated into the device, for the pre- vention of malfunction due to noise. a pull-up resistor, r1, with a value of 3.3 to 10 k , should be externally connected, even if the sd1 terminal is not used. in addition, a capacitor, c1, of 0.01 f or less should be connected for eliminating noise. ocl this is the output terminal of current limiter signal. the internal circuit composition is shown in figure 9. when the ls1 terminal voltage continuously exceeds 0.53 v typical for 2 s or longer, the transistor of the open collector circuit connected to the ocl terminal is turned on. in the case where the ocl signal is connected to the sd1 terminal and the sd2 terminal, each one of those connections should have rl and cf connected as shown in figure 10. rl and cf should be placed near the sdx terminal, which is an input terminal. the recommended constant ranges of rl and cf are: r l = 1 to 10 k c f = 0.001 to 0.01 f when the current limiter function is not used, the ocl terminal should be left floating. protection functions this section describes in detail the various device protection features provided with the sla6860m and sma6860m. undervoltage lockout (uvlo) on control power supply when the gate-driving voltages on the output mosfets become too low, the losses of the power mosfets increase, and in the worst case the circuits may be damaged. in order to prevent this, undervoltage protection circuits are built into the control power supply. the high-side driver ic monitors the voltage between vcc1 and com1, the voltage between vb1 and u, vb2 and v, and vb3 and w1. as shown in the timing chart (figure 11), when the vbx voltage exceeds the uvhh voltage (10.5 v typical), that enables the ho output (gate of mosfet) pulses on each subsequent hinx rising edge (edge operation). when the vbx voltage is below the uvhl value (10 v typical), the high-side mosfets are shut down. figure 8. sd1 terminal internal equivalent circuit sd1 com1 on in ocp to shutdown +5 v r1 c1 50 filter 3.3 s figure 10. ocl function terminal connections ocl sd1 [sd2] com1 com2 +5 v rl cf figure 9. ocl terminal internal circuit ocl ls1 com2 +5 v + ? 0.53 v rl cf 50 2 k 400 k filter 2 s (typ) allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
9 when the output of the power mosfets is shut down by uvlo operation due to falling boot voltage, the transistor on the open collector sd1 terminal does not turn on. at uvlo operation due to vcc voltage fall, however, the sd1 terminal does turn on. the high-side uvlo detection circuit and the internal equivalent circuit are shown in figure 12. as shown there, a filter is inserted to prevent line noise from affecting the control power supply voltage. when the voltage between vcc1 and com1 falls below the uvll voltage of 11 v typical, the high-side mosfets are shut down. when the power supply voltage rises above the uvlh voltage level of 11.5 v typical, that enables the ho output (gate of mosfet) pulses on each subsequent hinx rising edge (referred to as edge operation). the low-side driver ic monitors the voltage between vcc2 and com2. as shown in the low-side timing diagram (figure 13), when the voltage between vcc2 and com2 falls below the uvll voltage of 11 v typical, the low-side mosfets are shut down and the transistor of the open collector circuit connected to the sd2 terminal is turned on. when the vcc2 voltage rises above the uvlh voltage of 11.5 v typical, the shutdown of the low-side mosfets is released and the transistor of the sd2 terminal is turned off, allowing the device to operate in accordance with the command signal input on the linx pins (steady state operation). as shown in figure 14, a filter is inserted to prevent line noise from affecting the control power supply voltage, as in the high- side uvlo circuits, described above. the filter protects against the sharp fall of v bx , v cc1 , and v cc2 . however, in case of: over- voltage, filter time constants being exceeded, or only v cc1 falling while v bx voltage is sustained, malfunction or damage to the device might be caused. to protect against these faults, a ceramic capacitor (0.01 to 0.1 f) and a zener diode (v z = 18 to 22 v) should be provided near the power supply terminal. overtemperature protection (tsd) a thermal shut- down (tsd) protection circuit is built in for the sla6860m- sma6860m series. in the event of overheating, such as due to increased power consumption or an increase in the ambient temperature at the device, the power mosfets are shut down. the determination of a overtemperature condition is made by the driver circuit ics on the high side and low side, in accordance with table 1. when the operating temperature rises above 135 typical, thermal shutdown enables. when the temperature subse- quently falls below 115, thermal shutdown is released, and the device can continue operation again in accordance with the xinx signals. temperature monitoring occurs both on the high side and the low side. when tsd operates on the high side, those mosfets are turned off, and transistor of the open collector circuit to the sd1 terminal is turned on. note: because the temperatures of the power mosfets them- selves are not monitored for overtemperature condition, the internal protection function on its own may not be sufficient to prevent damage to the device due to overheating. it also should be noted that in a case where the temperature of the mosfets rise very rapidly, the overtemperature detection may lag. overcurrent protection (ocp) the sla6860m-sma6860m series has a built-in overcurrent protection circuit. if the voltage between ls1 and com2 (1.0 v or higher) continues for longer than the blanking time, t blank (2 s typical), then overcurrent protection starts operation (see figure 15). at the start of ocp operation, the transistor connected to the sd2 terminal (through a 50 resistor) turns on, and simultaneously the mosfet connected to the rc terminal (through a 50 resistor) turns on (see figure 16). the voltages of the sd2 terminal and the rc terminal fall in accordance with the time constants determined by external capac- itors c2 and cc. when the sd2 terminal voltage falls below v th (2. 1 v), a shutdown operation is performed on the mosfet gate. with the gate shut down, current decreases. as the voltage falls below the v trip level, the mosfet connected to the rc terminal turns off, in 5 s, and the rc terminal voltage rises with the time constant determined by rr and cc. when the rc terminal voltage rises to 3.5 v, the ocp reset operation starts, releasing the gate shutdown of the mosfets and turning off the transistor on the sd2 terminal, allowing the device to operate in accordance with the command signal input on the linx pins (steady state operation). table 1. overtemperature protection characteristics characteristic symbol min. typ. max. units tsd enable t dh 120 135 150 c tsd release t dl 100 115 130 c tsd hysteresis hys ? 20 ? c allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
10 + ? v ref filter to mosfet r s q ff vbx set reset figure 11. high-side mosfet output timing hin vb - hs ho uvhh uvhl vcc 1 uvll uvlh uvhh figure 12. high-side vcc1 uvlo internal equivalent circuit + ? v ref filter to mosfet gate drive circuit to sd2 output v cc2 lin figure 13. low-side mosfet output timing lin sd2 vcc 2 uvll uvlh lo uvlh figure 14. low-side vcc2 uvlo internal equivalent circuit allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
11 ls 1 v ref ocp sd2 mosfet shutdown rc filter 2 s 3.5 v r s q ff pulse expansion 5 s 50 50 ocp +5 v rr cc r2 c2 + ? + ? (1 v) +5 v figure 15. overcurrent protection circuit timing lin lo ls1 sd 2 rc ocp release 3.5 v 9 2 s v trip v th (2.9 v) (1 v) 2 s 5 s slope set by r2, c2 slope set by rc, cc figure 16. overcurrent protection circuit a. the lox signal is described, including delay imposed in accordance with the rc time constant by the input capacitance of the gate resistor and mosfet. b. waveforms when both the sd2 and the rc signals are off, and include delay due to the time constants of the internal resistor (50 ) and the external capacitors c2, cc, and rc. allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
12 typical applications this section examines typical application circuit designs using these devices, with and without output current limiting, and the timing effects that result. current limiting by pwm control this application imple- ments current limiting by connecting the ocl and sd1 pins (fig- ure 17). current limiting occurs by turning off and on the power supplied to the high side of the mosfet bridge. the timing is illustrated in figure 18. vcc 2 lin 1 vcc1 hin 1 com1 vb1 ho 3 hs3 lin 2 lin 3 sd 2 com2 lo1 lo2 lo3 m 15 v hin 2 hin 3 vb2 vb3 ho 2 ho 1 hs1 hs2 10 13 4 5 6 7 8 24 12 11 13 16 17 14 23 22 19 18 20 21 ocl 2 sd1 9 rc 15 5v 5v zd zd rs 5v cc rr r1 r2 c1 c2 csb system logic sla6860m/sma6860m high-side logic circuit low-side logic circuit figure 17. typical application. current limiting by controlling power to high-side mosfets. allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
13 lin lo ls1 sd 2 rc 3.5v v trip (1v) 2 s v ocl (0.5v) ocl , sd1 2 s (2.1v ) (2.9v ) 2 s hin enables high-side turn-on at next rising edge on hin signal enables low-side turn-on at next rising edge on lin signal ho high-side shutdown low-side shutdown 3.3 s (2.1v) 3.3 s 5 s (2.9v ) v th v th v th v th v th (2.9v) t = 50 c 2 t = 50 c c t = r l c f t = r l c f t = r 2 c 2 t = r r c c t = 50 c f figure 18. output timing effects. using typical application shown in figure 17. hin and lin must not be in phase. allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
14 current limiting using external diode this application implements current limiting by connecting the ocl and sd1 pins as in the first application example, and also inserting a diode between ocl and sd2 (figure 19). current limiting occurs by turning off and on the power supplied to the high side of the mosfet bridge, according to a fault signal on the ocl-sd2 output. the effect on timing is shown in figure 20. vcc 2 lin 1 vcc1 hin 1 com1 vb1 ho 3 hs3 lin 2 lin 3 sd2 com2 lo1 lo2 lo3 m 15 v hin 2 hin 3 vb2 vb3 ho 2 ho 1 hs1 hs2 10 13 4 5 6 7 8 24 12 11 13 16 17 14 23 22 19 18 20 21 ocl 2 sd1 9 rc 15 5v 5v zd zd rs 5v cc dt rr csb r1 r2 c1 c2 system logic sla6860m/sma6860m high-side logic circuit low-side logic circuit figure 19. typical application. current limiting by controlling power to high-side mosfets, with an external diode, dt, affecting the timing. allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
15 figure 20. output timing effects. using typical application shown in figure 19. lin lo ls1 sd 2 rc 3.5v v trip (1v) 2 s v ocl (0.5v) ocl , sd1 2 s (2.1v ) (2.9v ) 2 s hin enables high-side turn-on at next rising edge on hin signal enables low-side turn-on at next rising edge on lin signal ho high-side shutdown low-side shutdown 3.3 s (2.1v) 3.3 s 5 s v th v f (2.9v ) v th v th v th v th (2.9v) t = 50 c c t = r l c f t = r l c f t = r l c f t = r r c c t = 50 c f hin and lin must not be in phase. for the dt diode, use a diode for which v f is less than 1.2 v at 5 ma (t a = ?20c to 125c). observe the following conditions: r l = 1.0 k to 10 k , r 2 = 3.3 k to 10 k , and c f and c 2 = 0.001 f to 0.01 f allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
16 no current limiting this application does not use the device itself to limit output current. this is implemented by connecting the sd1 and sd2 pins (figure 21). the capacitors on the sd sig- nals and the pull-up resistor on sd2 are not required. the effect on timing is shown in figure 22. vcc 2 lin 1 vcc1 hin 1 com1 vb1 ho 3 hs3 lin 2 lin 3 sd 2 com2 lo1 lo2 lo3 m 15 v hin 2 hin 3 vb2 vb3 ho 2 ho 1 hs1 hs2 10 13 4 5 6 7 8 24 12 11 13 16 17 14 23 22 19 18 20 21 ocl 2 sd1 9 rc 15 r1 5v zd zd rs vrc cc rr csb system logic sla6860m/sma6860m high-side logic circuit low-side logic circuit figure 21. typical application. no output current limiting. allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
17 figure 22. output timing effects. using typical application shown in figure 21 (no current limiting). hin and lin must not be in phase. hin lin ls 1 sd 2 t blank t blank sd 1 rc slope of ,cc ocp release t p 3.5 v ocl delay v lim v trip rc ho lo 5 s allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
18 protection function timing this section provides information about the timing of fault events handled by these devices. figure 23. overtemperature protection thermal shutdown (tsd) timing. hin and lin must not be in phase. figure 24. undervoltage lockout (uvlo) protection. hin and lin must not be in phase. hin ho t jh t dh t dl lin sd 1 lo t dh t dl t jl sd 2 hin ho vbx to hsx v uvhl v uvhh lin sd 1 lo vcc sd 2 v uvll v uvlh t f t f allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
19 application circuit recommendations when designing application circuits using these devices, the fol- lowing should be taken into consideration: supply sequence the load power supply does not have to be provided in any particular sequence. however, commands should not be transmitted on the sequencing signal input terminals, hin and lin, until after the logic control power supply, vcc, has reached steady state. short circuit protection there is no built-in protection circuit against short circuits through the outputs to ground. the applica- tion circuit logic should be designed to monitor outputs to detect a short circuit condition. pin to pin distance the device packages in the sla6860m- sma6860m series have 24 pins, and a 1.27 mm pin pitch. at operating voltage levels, there may be insufficient creepage and clearance distance, and conformal coating or encapsulation of the application printed board assembly is recommended. surge protection each terminal should be protected against power surges by isolation using an external component such as a ceramic capacitor or zener diode. power surges that impinge on the device may cause critical damage to the ic as well as faulty operation. input blanking time in order to avoid a high-side to low-side short-circuit, the hin and lin signals must never be in phase. the blanking time, t blank , or dead-time, is the delay between rising edges on the hin and lin signals. it must be controlled externally by the application system logic, as it is not set inter- nally. a t blank of more than 1.5 s is recommended. electrical characteristics data the following pages contain characteristic performance data. the information shown applies to all models of the sla6860m- sma6860m series, unless otherwise specified. allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
20 i cc versus t j 0 1 2 3 4 5 6 7 -25 0 25 50 75 100 125 150 t j (c) i cc (ma) max typ min v cc = 15 v, input off i cc versus v cc 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 12 13 14 15 16 17 18 19 20 v cc (v) i cc (ma) t j =125c t j = 25c input off i boot versus t j 0 50 100 150 200 250 300 -25 0 25 50 75 100 125 150 t j (c) i boot ( a) max typ min vbx to hsx = 15 v, input off i boot versus t j 0 50 100 150 200 250 300 350 400 -25 0 25 50 75 100 125 150 t j (c) i boot ( a) max typ min vbx to hsx = 15 v, input on i boot versus v bx 0 50 100 150 200 250 12 13 14 15 16 17 18 19 20 v bx (v) i boot ( a) t j = 125c t j = 25c input off i in versus t j 0 100 200 300 400 500 600 700 -25 0 25 50 75 100 125 150 t j (c) i in ( a) i in = 5 v max typ min allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
21 0 100 200 300 400 500 600 700 -25 0 25 50 75 100 125 150 t j (c) minimum on width (ns) max typ minimum on width versus t j , high side minimum on width versus t j , low side 0 100 200 300 400 500 600 700 -25 0 25 50 75 100 125 150 max typ 0 200 400 600 800 1000 1200 0 200 400 600 800 1000 1200 input pulse width (ns) gate output pulse width (ns) high side low side typical, t j = 25c, v cc =15 v gate output pulse width versus input pulse width high-side release versus t j 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 -25 0 25 50 75 100 125 150 v uvhl (v) v ih versus t j 0.0 1.0 2.0 3.0 4.0 -25 0 25 50 75 100 125 150 t j (c) v ih (v) max min typ v il versus t j 0.0 1.0 2.0 3.0 4.0 -25 0 25 50 75 100 125 150 t j (c) v il (v) max min typ t j (c) t j (c) max min typ minimum on width (ns) allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
22 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 -25 0 25 50 75 100 125 150 t j (c) v uvhh (v) max min typ 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 -25 0 25 50 75 100 125 150 v uvll (v) max min typ 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 -25 0 25 50 75 100 125 150 v uvlh (v) max typ min uvlo filter delay (high side) versus t j high-side operation versus t j low-side operation versus t j low-side release versus t j 0 5 10 15 20 25 -25 0 25 50 75 100 125 150 uvlo filter delay ( s) max min typ uvlo filter delay (low side) versus t j 0 2 4 6 8 10 12 -25 0 25 50 75 100 125 150 uvlo filter delay ( s) max typ min v lim versus t j 0.40 0.45 0.50 0.55 0.60 -25 0 25 50 75 100 125 150 v lim (v) max min typ t j (c) t j (c) t j (c) t j (c) t j (c) allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
23 blanking time versus t j (ocp,ocl) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -25 0 25 50 75 100 125 150 t blank ( s) max typ min v trip versus t j 0.80 0.85 0.90 0.95 1.00 1.05 1.10 -25 0 25 50 75 100 125 150 t j (c) t j (c) v trip (v) max typ min 0 1.5 1.0 2.0 2.5 3.0 3.5 -25 0 25 50 75 100 125 150 v rc = 5 v, r r = 360 k ,c c = 0.0047 f max typ min pulse expansion versus t j (ocp,ocl) 0 1 2 3 4 5 6 7 8 9 -25 0 25 50 75 100 125 150 pulse expansion ( s) max typ min v sdh versus t j 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 -25 0 25 50 75 100 125 150 v sdh (v ) max typ min v sdl versus t j 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 -25 0 25 50 75 100 125 150 v sdl (v ) max typ min ocp hold time versust j hold time (ms) t j (c) t j (c) t j (c) t j (c) allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
24 0 100 200 300 400 500 600 700 -25 0 25 50 75 100 125 150 v p = 5 v, r = 1 k , c = 0.01 f max typ min sd filter versus t j saturation voltage versus t j (sd, ocl) 0 1 2 3 4 5 6 7 8 -25 0 25 50 75 100 125 150 t j (c) t j (c) sd filter ( s) v sat ( v) max min typ 0 50 100 150 200 250 300 350 400 450 500 -25 0 25 50 75 100 125 150 v rc = 5 v,r r = 330 k ,c c = 0.01 f max typ min saturation voltage versus t j (rc) t j (c) v sat ( v) allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
25 0 0.5 1.0 1.5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 r d(on) versus i d r d(on) versus i d 0 1 2 3 4 5 6 7 8 0 0.5 1.0 1.5 0 1 2 3 4 0 0.5 1.0 1.5 2.0 i d (a) i d (a) 125c 25c 75c 125c 25c 75c i sd versus v sd i sd versus v sd 0 0.5 1.0 1.5 2.0 0 0.2 0.4 0.6 0.8 1.0 v sd (v) v sd (v) i sd (a) v sd = 0 v v sd = 0 v sma6861m mosfet characteristics 0 0.5 1.0 1.5 2.0 2.5 0 0.5 1.0 1.5 v sd (v) i sd (a) i sd (a) 0 1 2 3 4 5 0 0.5 1.0 1.5 2.0 2.5 r d(on) ( )r d(on) ( )r d(on) ( ) sma6863m mosfet characteristics sma6862m mosfet characteristics r d(on) versus i d v gs =15 v v gs =15 v v gs =15 v i d (a) 125c 25c 75c 125c 25c 75c 125c 25c 75c 125c 25c 75c i sd versus v sd v sd = 0 v allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
26 copyright ? 2008-2010 allegro microsystems, inc. all performance characteristics given are typical values for circuit or system baseline design only and are at the nominal operating voltage and an ambient temperature of 25c, unless oth er wise stated. the products described herein are manufactured in ja pan by sanken electric co., ltd. for sale by allegro microsystems, inc. sanken and allegro reserve the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be re quired to per mit im- prove ments in the per for mance, reliability, or manufacturability of its prod ucts. therefore, the user is cau tioned to ve rify that the in for ma tion in this publication is current before placing any order. when using the products described herein, the ap pli ca bil i ty and suit abil i ty of such products for the intended purpose s hall be reviewed at the users responsibility. although sanken undertakes to enhance the quality and reliability of its prod ucts, the occurrence of failure and defect of sem i con duc tor products at a certain rate is in ev i ta ble. users of sanken products are requested to take, at their own risk, preventative measures including safety design of the equipme nt or systems against any possible injury, death, fires or damages to society due to device failure or malfunction. sanken products listed in this publication are designed and intended for use as components in general-purpose electronic equip ment or apparatus (home ap pli anc es, office equipment, tele com mu ni ca tion equipment, measuring equipment, etc.). their use in any applicat ion requiring radiation hardness assurance (e.g., aero space equipment) is not supported. when considering the use of sanken products in ap pli ca tions where higher reliability is re quired (transportation equipment and its control systems or equip ment, fire- or burglar-alarm systems, various safety devices, etc.), contact a company sales representative to discuss and obtain written confirmation of your spec i fi ca tions. the use of sanken products without the written consent of sanken in applications where ex treme ly high reliability is required (aerospace equip- ment, nuclear power-control stations, life-support systems, etc.) is strictly prohibited. the information in clud ed herein is believed to be accurate and reliable. ap pli ca tion and operation examples described in this pub li ca tion are given for reference only and sanken and allegro assume no re spon si bil i ty for any in fringe ment of in dus tri al property rights, intellectual property rights, or any other rights of sanken or allegro or any third party that may result from its use. the contents in this document must not be transcribed or copied without sanken?s written consent. allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
27 asia-pacific china sanken electric hong kong co., ltd. suite 1026, ocean centre canton road, tsimshatsui kowloon, hong kong tel: 852-2735-5262, fax: 852-2735-5494 sanken electric (shanghai) co., ltd. room 3202, maxdo centre xingyi road 8, changning district shanghai, china tel: 86-21-5208-1177, fax: 86-21-5208-1757 sanken electric (shanghai) co., ltd. shenzhen office room 1013, xinhua insurance building mintian road, futian district shenzhen city, guangdong, china tel: 86-755-3391-9356/9358, fax: 86-755-3391-9368 taiwan sanken electric co., ltd. room 1801, 18th floor 88 jung shiau east road, sec. 2 taipei 100, taiwan r.o.c. tel: 886-2-2356-8161, fax: 886-2-2356-8261 japan sanken electric co., ltd. overseas sales headquarters metropolitan plaza building 1-11-1 nishi-ikebukuro, toshima-ku tokyo 171-0021, japan tel: 81-3-3986-6164, fax: 81-3-3986-8637 korea sanken electric korea co., ltd. samsung life yeouido building 16f 23-10, yeouido-dong, yeongdeungpo-gu seoul 150-734, korea tel: 82-2-714-3700, fax: 82-2-3272-2145 singapore sanken electric singapore pte. ltd. 152 beach road, #10-06 the gateway east singapore 189721 tel: 65-6291-4755, fax: 65-6297-1744 europe sanken power systems (uk) limited pencoed technology park pencoed, bridgend cf35 5hy, united kingdom tel: 44-1656-869-100, fax: 44-1656-869-162 north america united states allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01606, u.s.a. tel: 1-508-853-5000, fax: 1-508-853-7895 allegro microsystems, inc. 14 hughes street, suite b105 irvine, california 92618, u.s.a. tel: 1-949-460-2003, fax: 1-949-460-7837 worldwide contacts allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com

▲Up To Search▲

Price & Availability of SLA6868MLF2451

	To Download SLA6868MLF2451 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .