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low latency pc-133 hsdram preliminary data sheet 32mb, 64mb, 128mb dimm enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 2000 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. revision 1.4 page 1 of 13 features jedec standard pc-133 sdram dimm low latency pc-133 modules (3:2:2) @ 133 mhz cas latency = 3 ras to cas delay = 2 precharge delay = 2 fast 4.6 ns clock access time overclock existing pc systems to 133 mhz ideal for low cost 133 mhz bus speed systems supports cas latency = 1, 2, 3 on-board serial presence detect (spd) unbuffered 168-pin dimm 4k refresh / 64 ms single 3.3v 0.3v power supply available on-line at http://www.pc 133memory.com description the enhanced memory systems 32mb, 64mb and 128mb low latency pc-133 hsdram dimms are the fastest unbuffered sdram dimms available. low latency (3:2:2) improves performance in high-end desktop publishing and graphics applications, particularly with uma system architectures. the fast 4.6 ns clock access time allows unbuffered dimm operation at 133 mhz for lower memory latency, and lower costs than registered dimms. the 32mb module (sm3208dt-7.5) is organized as 4mx64, the 64mb module (sm6408dt-7.5) is organized as 8mx64, and the 128mb module (sm12808dt-7.5) is organized as 16mx64. the 128mb ecc module (sm12809dt-7.5) is organized as 16mx72. each module contains a serial presence eeprom programmed by enhanced memory systems, which contains information on the module type, module organization, component speed, and other attributes relevant to the system controller. pin symbol pin symbol pin symbol pin symbol 1 vss 43 vss 85 vss 127 vss 2 dq0 44 dnu 86 dq32 128 cke0 3 dq1 45 s2# 87 dq33 129 s3# 4 dq2 46 dqmb2 88 dq34 130 dqmb6 5 dq3 47 dqmb3 89 dq35 131 dqmb7 6 vdd 48 dnu 90 vdd 132 rfu 7 dq4 49 vdd 91 dq36 133 vdd 8 dq5 50 nc 92 dq37 134 nc 9 dq6 51 nc 93 dq38 135 nc 10 dq7 52 cb2 94 dq39 136 cb6 11 dq8 53 cb3 95 dq40 137 cb7 12 vss 54 vss 96 vss 138 vss 13 dq9 55 dq16 97 dq41 139 dq48 14 dq10 56 dq17 98 dq42 140 dq49 15 dq11 57 dq18 99 dq43 141 dq50 16 dq12 58 dq19 100 dq44 142 dq51 17 dq13 59 vdd 101 dq45 143 vdd 18 vdd 60 dq20 102 vdd 144 dq52 19 dq14 61 nc 103 dq46 145 nc 20 dq15 62 nc 104 dq47 146 nc 21 cb0 63 cke1 105 cb4 147 nc 22 cb1 64 vss 106 cb5 148 vss 23 vss 65 dq21 107 vss 149 dq53 24 nc 66 dq22 108 nc 150 dq54 25 nc 67 dq23 109 nc 151 dq55 26 vdd 68 vss 110 vdd 152 vss 27 we# 69 dq24 111 cas# 153 dq56 28 dqmb0 70 dq25 112 dqmb4 154 dq57 29 dqmb1 71 dq26 113 dqmb5 155 dq58 30 s0# 72 dq27 114 s1# 156 dq59 31 dnu 73 vdd 115 ras# 157 vdd 32 vss 74 dq28 116 vss 158 dq60 33 a0 75 dq29 117 a1 159 dq61 34 a2 76 dq30 118 a3 160 dq62 35 a4 77 dq31 119 a5 161 dq63 36 a6 78 vss 120 a7 162 vss 37 a8 79 ck2 121 a9 163 ck3 38 a10/ap 80 nc 122 ba0 164 nc 39 ba1 81 wp 123 a11 165 sa0 40 vdd 82 sda 124 vdd 166 sa1 41 vdd 83 scl 125 ck1 167 sa2 42 ck0 84 vdd 126 rfu 168 vdd
low latency pc-133 hsdram 32mb, 64mb, 128mb dimm preliminary data sheet enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 2000 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. page 2 of 13 revision 1.4 pin descriptions symbol type function ck0,1,2,3 input clo cks: all sdram i nput signals are sampled on the positive edge of ck. cke0,1 input clock enables: cke activate (high) or deactivate (low) the ck signals. deactivating the clock initiates the power-down and self-refresh operations (all banks idle), or clock suspend operation. cke is synchronous until the device enters power-down and self-refresh modes where it is asynchronous until the mode is exited. s0,1,2,3# input chip select: s# enables (low) or disables (high) the command decoder. when the command decoder is disabled, new commands are ignored but previous operations continue. ras#, cas#, we# input command inputs: sampled on the rising edge of ck, these inputs define the command to be executed. ba1, ba0 input bank addresses: these inputs define to which of the 4 banks a given command is being applied. a0-a11 input address inputs: a0-a11 define the row address during the bank activate command. a0-a8 define the column address during read and write commands. a10/ap invokes the auto-precharge operation. during manual precharge commands, a10/ap low specifies a single bank precharge while a10/ap high precharges all banks. the address inputs are also used to program the mode register. dq0-dq63 input/ output data i/o: data bus inputs and outputs. for write cycles, input data is applied to these pins and must be set-up and held relative to the rising edge of clock. for read cycles, the device drives output data on these pins after the cas latency is satisfied. dqmb0-7 input data i/o mask inputs: dqmb0-7 inputs mask write data (zero latency) and acts as a synchronous output enable (2-cycle latency) for read data. cb0-7 input/ output ecc check bits v dd supply power supply: +3.3 v v ss supply ground sda input/ output serial presence-detect data: sda is a bi-directional pin used to transfer addresses and data into and data out of the presence-detect portion of the module. scl input serial clock for presence-detect: scl is used to synchronize the presence detect data transfer to and from the module sa0-2 input presence-detect address inputs: these pins are used to configure the presence detect device. wp input serial presence detect write protect: active high inhibits writes to the spd eeprom. wp must be driven low for normal read/write operations. rfu - reserved for future use: these pins should be left unconnected. dnu - do not use. nc - no connect - open pin.
low latency pc-133 hsdram preliminary data sheet 32mb, 64mb, 128mb dimm enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 2000 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. revision 1.4 page 3 of 13 32mb dimm functional block diagram C sm3208dt-7.5 s0# dqmb0 u0 dq(15:0) dqmb1 u2 dq(47:32) s2# dqmb2 u1 dq(31:16) dqmb3 u3 dq(63:48) ras# sdram u0-7 cas# sdram u0-7 we# sdram u0-7 cke0 sdram u0-7 ras# cas# we# cke0 ba0 sdram u0-7 ba0 ba1 a0-a11 vdd vss ba1 sdram u0-7 a0-a11 sdram u0-7 vdd sdram u0-7 vss sdram u0-7 note: all dq resistor values are 10 ohms all ck resistor values are 10 ohms u0-u7 are sm3603t-7.5 scl sa0-2 sda wp serial pd 47k ck0,2 sdrams 10 clock wiring ck0 ck1 ck2 ck3 2 sdram+15 pf termination 2 sdram+15 pf termination clock termination 10 10 pf ck1,3
low latency pc-133 hsdram 32mb, 64mb, 128mb dimm preliminary data sheet enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 2000 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. page 4 of 13 revision 1.4 64mb dimm functional block diagram C sm6408dt-7.5 clock wiring ck0 ck1 ck2 ck3 4 sdram+3.3 pf termination 4 sdram+3.3 pf termination clock termination 10 10 pf ck1,3 ras# sdram u0-7 cas# sdram u0-7 we# sdram u0-7 cke0 sdram u0-7 ras# cas# we# cke0 ba0 sdram u0-7 ba0 ba1 a0-a11 vdd vss ba1 sdram u0-7 a0-a11 sdram u0-7 vdd sdram u0-7 vss sdram u0-7 note: all dq resistor values are 10 ohms all ck resistor values are 10 ohms u0-u7 are sm3603t-7.5 scl sa0-2 sda wp serial pd 47k ck0,2 sdrams 10 s0# dqmb0 u0 dq(7:0) dqmb4 u4 dq(39:32) dqmb5 u5 dq(47:40) dqmb1 u1 dq(15:8) s2# dqmb2 u2 dq(23:16) dqmb6 u6 dq(55:48) dqmb7 u7 dq(63:56) dqmb3 u3 dq(31:24)
low latency pc-133 hsdram preliminary data sheet 32mb, 64mb, 128mb dimm enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 2000 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. revision 1.4 page 5 of 13 128mb dimm functional block diagram C sm12808dt-7.5 clock wiring ck0 ck1 ck2 ck3 4 sdram+3.3 pf 4 sdram+3.3 pf 4 sdram+3.3 pf 4 sdram+3.3 pf ba0 ba1 a0-a11 vdd vss ba0 sdram u0-15 ba1 sdram u0-15 a0-a11 sdram u0-15 vdd sdram u0-15 vss sdram u0-15 ras# sdram u0-15 cas# sdram u0-15 we# sdram u0-15 cke0 sdram u0-7 ras# cas# we# cke0 cke1 cke1 sdram u8-15 vdd 10k ck0-3 sdrams 10 scl sa0-2 sda wp serial pd 47k note: all dq resistor values are 10 ohms all ck resistor values are 10 ohms u0-u15 are sm3603t-7.5 s0# s1# dqmb0 u0 dq(7:0) u8 dqmb1 u1 dq(15:8) u9 u12 u4 dq(39:32) dqmb4 dqmb5 u5 dq(47:40) u13 s2# s3# dqmb2 u2 dq(23:16) u10 dqmb3 u3 dq(31:24) u11 u14 u6 dq(55:48) dqmb6 dqmb7 u7 dq(63:56) u15
low latency pc-133 hsdram 32mb, 64mb, 128mb dimm preliminary data sheet enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 2000 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. page 6 of 13 revision 1.4 128mb ecc dimm functional block diagram C sm12809dt-7.5 clock wiring ck0 ck1 ck2 ck3 5 sdram 5 sdram 4 sdram+3.3 pf 4 sdram+3.3 pf ba0 ba1 a0-a11 vdd vss ba0 sdram u0-17 ba1 sdram u0-17 a0-a11 sdram u0-17 vdd sdram u0-17 vss sdram u0-17 ras# sdram u0-17 cas# sdram u0-17 we# sdram u0-17 cke0 sdram u0-8 ras# cas# we# cke0 cke1 cke1 sdram u9-17 vdd 10k ck0-3 sdrams 10 scl sa0-2 sda wp serial pd 47k note: all dq resistor values are 10 ohms all ck resistor values are 10 ohms u0-u15 are sm3603t-7.5 s0# s1# u2 cb(7:0) u11 u14 u5 dq(39:32) dqmb4 dqmb5 u6 dq(47:40) u15 dqmb0 u0 dq(7:0) u9 dqmb1 u1 dq(15:8) u10 s2# s3# dqmb2 u3 dq(23:16) u12 dqmb3 u4 dq(31:24) u13 u16 u7 dq(55:48) dqmb6 dqmb7 u8 dq(63:56) u17 note: sdram u11 dqm input must be wired to dqmb5
low latency pc-133 hsdram preliminary data sheet 32mb, 64mb, 128mb dimm enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 2000 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. revision 1.4 page 7 of 13 electrical characteristics absolute maximum ratings description symbol value power supply voltage v dd -1v to +4.6v voltage on any pin with respect to ground v in , v out -0.5v to +4.6v operating temperature (ambient) t a 0 c to +70 c storage temperature t stg -55 c to +125 c power dissipation p d tbd dc output current (i/o pins) i out 50ma stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress ra ting only, and the functional operation of the device at these, or any other conditions above those listed in the operational sectio n of the specification, is not implied. exposure to conditions at absolute maximum ratings for extended periods may affect device reliab ility. dc operating conditions (t a = 0 c to 70 c) symbol parameter min typical max units notes v dd supply voltage 3.0 3.3 3.6 v v ih input high voltage 2.0 3.3 v dd + 0.3 v v il input low voltage -0.3 0.0 0.8 v i i(l) input leakage current - - 1 m a i o(l) output leakage current - - 1 m a v oh output high voltage (i out = -4ma) 2.4 - v dd v v ol output low voltage (i out = +4ma) 0.0 - 0.4 v capacitance (t a = 25 c, f = 1mhz, vdd = 3.3v 0.3v, not 100% tested) 32mb 64mb 128mb symbol parameter non-ecc non-ecc non-ecc ecc units c in1 input capacitance (ba1, ba0, a0-11, ras, cas) 25 38 65 71 pf c in2 input capacitance (s0 - s3) 14 21 21 24 pf c in3 input capacitance (ck0 - ck3) 26 26 26 26 pf c in4 input capacitance (cke0, cke1) 25 38 38 42 pf c in5 input capacitance (dqmb0-7) 12 12 14 14 pf c in6 input capacitance (scl, sa0-2) 12 12 12 12 pf c i/o1 i/o capacitance (sda) 12 12 12 12 pf c i/o2 i/o capacitance (dq0-63, cb0-7) 8.5 8.5 13 13 pf
low latency pc-133 hsdram 32mb, 64mb, 128mb dimm preliminary data sheet enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 2000 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. page 8 of 13 revision 1.4 ac characteristics (t a = 0 c to 70 c) 1. an initial pause of 200 m s is required after power-up, then a precharge all banks command must be given followed by a minimum of eight auto (cbr) refresh cycles before the mode register set operation can begin. 2. ac timing tests have v il = 0.8v and v ih = 2.0v with the timing referenced to the v tt = 1.4v crossover point. t setup t hold clock input output t lz t ac t oh t t vih vtt vil v tt output z 0 = 50 ohm c load = 50pf ac output load circuit v tt r t = 50 ohm 3. the transition time is measured between v ih and v il (or between v ih and v il ). 4. ac measurements assume t t = 1ns. 5. in addition to meeting the transition rate specification, the clock and cke must transition v ih and v il (or between v ih and v il ) in a monotonic manner.
low latency pc-133 hsdram preliminary data sheet 32mb, 64mb, 128mb dimm enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 2000 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. revision 1.4 page 9 of 13 ac operating conditions (t a = 0 c to 70 c) -7.5 symbol parameter min max units notes clock and clock enable parameters t ck3 clock cycle time, cl = 3 7.5 ns t ck2 clock cycle time, cl = 2 10 ns t ck1 clock cycle time, cl = 1 20 ns t ckh3 , t ckl3 clock high & low times, cl=3 2.5 - ns 1 t ckh2 , t ckl2 clock high & low times, cl=2 3.5 - ns 1 t ckh1 , t ckl1 clock high & low times, cl=1 4.5 - ns 1 t ckes clock enable set-up time 1.5 - ns t ckeh clock enable hold time 0.8 - ns t cksp cke set-up time (power down mode) 1.5 - ns t t transition time (rise and fall) - 4 ns common parameters t cs command and address set-up time 1.5 - ns t ch command and address hold time 0.8 - ns t rcd ras to cas delay time 15 - ns t rc bank cycle time 52.5 120k ns t ras bank active time 37.5 120k ns t rp precharge time 15 - ns t rrd bank to bank delay time (alt. bank) 15 - ns t ccd cas to cas delay time (same bank) 7.5 - ns t mrd mode register set to active delay 2 - clk notes: 1. assumes clock rise and fall times are equal to 1ns. if rise or fall time exceeds 1ns, other ac timing parameters must be co mpensated by an additional [(t rise +t fall )/2-1] ns.
low latency pc-133 hsdram 32mb, 64mb, 128mb dimm preliminary data sheet enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 2000 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. page 10 of 13 revision 1.4 -7.5 symbol parameter min max units notes read and write parameters t ac3 clock access time, cl = 3 - 4.6 ns 1,2 t ac2 clock access time, cl = 2 - 6.0 ns 1,2 t ac1 clock access time, cl = 1 - 15.0 ns 1,2 t oh3 data output hold time (cl=3) 2.7 - ns t oh2 data output hold time (cl=2) 3.0 - ns t oh1 data output hold time (cl=1) 3.5 - ns t lz data output to low-z time 1 - ns t hz2 data output to high-z time (cl=2, 3) - 4.6 ns 3 t hz1 data output to high-z time (cl=1) - 7.0 ns 3 t dqz dqm data output disable time 2 - clk t ds data input set-up time 1.5 - ns t dh data input hold time 0.8 - ns t dpl data input to precharge 15 - ns t dal data input to actv/refresh 30 - ns 4 t dqw data write mask latency 0 - clk refresh parameters t ref refresh period - 64 ms 5, 6 t srex self refresh exit time 2clk+t rc - ns 7 notes: 1. access time is measured at 1.4v (lvttl) at max clock rate for the cas latency specified. see ac test load. 2. access time is based on a clock rise time of 1ns. if clock rise time is longer than 1ns, then (trise/2-0.5) ns must be added to the access time. 3. referenced to the time at which the output achieves an open circuit condition. 4. tdal is equal to tdpl + trp. 5. 4096 cycles. 6. any time that the refresh period has been exceeded, a minimum of two auto- refresh (cbr) commands must be given to wake up the device. 7. self-refresh exit is a synchronous operation and begins on the 2nd positive clock edge after cke returns high. self-refresh exi t is not completed until trc is satisfied once the self-refresh exit command is registered.
low latency pc-133 hsdram preliminary data sheet 32mb, 64mb, 128mb dimm enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 2000 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. revision 1.4 page 11 of 13 serial presence detect (spd) for pc-133 dimms 32mb 64mb 128mb 32mb 64mb 128mb byte description ** hex code ** 0 number of bytes written into eeprom 128 128 128 80 80 80 1 total number of spd bytes 256 256 256 08 08 08 2 memory type sdram sdram sdram 04 04 04 3 number of row addresses 12 12 12 0c 0c 0c 4 number of column addresses 8 9 9 08 09 09 5 number of module banks 1 1 2 01 01 02 6 module data width x64 x64 x64 x72 40 40 40 48 7 module data width (cont'd) 0 0 0 00 00 00 8 voltage interface levels lvttl lvttl lvttl 01 01 01 9 cycle time at max cas latency 7.5 ns 7.5 ns 7.5 ns 75 75 75 10 sdram clock access time 5.0 ns 4.6 ns 4.6 ns 50 46 46 11 dimm config (non-parity, parity, ecc) --- non-parity --- --- ecc --- 00 00 00 02 12 refresh rate and type --- 15.625us / self --- 80 80 80 13 primary sdram width x16 x8 x8 10 08 08 14 error checking data width x64 x72 n/a n/a n/a x8 00 00 00 08 15 min. cas-to-cas delay (tccd) 1 clk 1 clk 1 clk 01 01 01 16 burst lengths supported --- 1,2,4,8,full pg --- 8f 8f 8f 17 number of banks on sdram device 4 4 4 04 04 04 18 cas latencies supported 1,2,3 1,2,3 1,2,3 07 07 07 19 cs latency 0 0 0 01 01 01 20 write latency 0 0 0 01 01 01 21 sdram module attributes --- unbuffered --- 00 00 00 22 sdram device attributes +/-10% vdd, precharge all, wr-1/rdbrst 0e 0e 0e 23 min. clock cycle time at cl=2 10 ns 10 ns 10 ns a0 a0 a0 24 clock access time at cl=2 (tac2) 6 ns 6 ns 6 ns 60 60 60 25 min. clock cycle time at cl=1 20 20 20 50 50 50 26 clock access time at cl=1 (tac1) 15 15 15 3c 3c 3c 27 min. row precharge time (trp) 15 ns 15 ns 15 ns 0f 0f 0f 28 min. row-to-row delay (trrd) 15 ns 15 ns 15 ns 0f 0f 0f 29 min. ras-to-cas delay (trcd) 15 ns 15 ns 15 ns 0f 0f 0f 30 min. ras pulse width (tras) 37.5 ns 37.5 ns 37.5 ns 26 26 26 31 density of each bank on module 32mb 64mb 64mb 08 10 10 32 cmd/addr input set-up time 1.5 ns 15 15 15 33 cmd/addr input hold time 0.8 ns 08 08 08 34 data input set-up time 1.5 ns 15 15 15 35 data input hold time 0.8 ns 08 08 08 36-61 superset information - - - 00 00 00 62 spd rev. 1.2 12 12 12 63 checksum for bytes 0-62 non-ecc ecc - - - 15 0c 0d 1f 64-71 jedec id code enhanced memory systems 7f32ffffffffffff 72 manufacturing location - - - xxxx xxxx xxxx 73-90 manufacturer's part # sm3208dt sm6408dt sm12808dt xxxx xxxx xxxx 91,92 pcb rev. code - rrrr rrrr rrrr 93,94 manufacturing date yyww code yyww yyww yyww 95-98 assembly serial # serial number ssss ssss ssss 99-125 manufacturer's specific data open 00 00 00 126 intel specification frequency 133mhz 64 64 64 127 intel specification cl and clock support - - - af af ff
low latency pc-133 hsdram 32mb, 64mb, 128mb dimm preliminary data sheet enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 2000 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. page 12 of 13 revision 1.4 revision log revision date summary of changes 1.4 5/2/00 added cas 1 data, and this revision log.
low latency pc-133 hsdram preliminary data sheet 32mb, 64mb, 128mb dimm enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 2000 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. revision 1.4 page 13 of 13 ordering information these pc-133 hsdram dimms may be purchased on-line at http://www.pc 133memory.com , which is an e-commerce function of enhanced memory systems inc., or call 1-800-568-1868. part number capacity i/o width i/o type package power supply maximum operating frequency (mhz) sm3208dt - 7.5 32 mb x64 lvttl 168 -p in dimm 3.3v 133 sm6408dt-7.5 64 mb x64 lvttl 168-pin dimm 3.3v 133 sm12808dt-7.5 128 mb x64 lvttl 168-pin dimm 3.3v 133 sm12809dt-7.5 128 mb x72 lvttl 168-pin dimm 3.3v 133 note: enhanced memory systems low latency pc-133 hsdram dimms are labeled per the intel pc sdram dimm naming convention. this convention requires identification of the bus speed, latency, clock access time, and spd revision code. the c ode for these dimm modules is pc133-322-46100.

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