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| tms320vc5441 fixed-point digital signal processor data manual literature number: sprs122d december 1999 ? revised december 2001 printed on recycled paper production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti ? s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti ? s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third ? party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? iii revision history revision date product status highlights * december 1999 product preview original a november 2000 product preview converted from data sheet to data manual format and updated characteristics data. b may 2001 product preview revised signal descriptions table and updated characteristics data c july 2001 production data revised electrical characteristics to reflect production data. d december 2001 production data updated characteristics data contents v december 1999 ? revised december 2001 sprs122d contents section page 1 tms320vc5441 features 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 introduction 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 description 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 migration from the 5421 to the 5441 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 pin assignments 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 pin assignments for the ggu package 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 pin assignments for the pgf package 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 signal descriptions 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 functional overview 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 memory 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 memory maps 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 on-chip dual-access ram (daram) 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.3 on-chip two-way shared ram 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.4 extended data memory 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.5 extended program memory 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.6 program memory 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.7 data memory 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.8 i/o memory 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.9 multicore reset signals 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.10 device bootload 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 on-chip peripherals 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 direct memory access (dma) controller 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 16-bit bidirectional host-port interface (hpi16) 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 multichannel buffered serial port (mcbsp) 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.4 hardware timer 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.5 watchdog timer 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.6 software-programmable phase-locked loop (pll) 40 . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.7 general-purpose i/o 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.8 chip subsystem id register 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.9 data memory map register 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 memory-mapped registers 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 mcbsp control registers and subaddresses 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 dma subbank addressed registers 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 interrupts 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 idle3 power-down mode 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 emulating the 5441 device 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 documentation support 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 electrical specifications 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 absolute maximum ratings 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 recommended operating conditions 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 electrical characteristics over recommended operating case temperature range (unless otherwise noted) 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contents vi december 1999 ? revised december 2001 sprs122d section page 5.4 package thermal resistance characteristics 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 timing parameter symbology 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 clock options 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.1 divide-by-two, divide-by-four, and bypass clock options ? pll disabled 57 . . . . . 5.6.2 multiply-by-n clock option ? pll enabled 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 reset, x_bio , and interrupt timings 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8 external flag (x_xf), timer (x_tout), and watchdog timer output (x_wtout ) timings 61 . . 5.9 general-purpose input/output (gpio) timing 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10 multichannel buffered serial port timing 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10.1 mcbsp0/1/2 transmit and receive timings 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10.2 mcbsp0 general-purpose i/o timing 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.11 host-port interface (hpi16) timing 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 mechanical data 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 ball grid array mechanical data 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 low-profile quad flatpack mechanical data 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figures vii december 1999 ? revised december 2001 sprs122d list of figures figure page 2 ? 1 169-ball ggu microstar bga (bottom view) 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 2 176-pin pgf low-profile quad flatpack (top view) 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 1 overall functional block diagram 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 2 typical subsystem functional block diagram 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 3 subsystem a cpu memory map 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 4 subsystem b cpu memory map 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 5 subsystem c cpu memory map 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 6 subsystem d cpu memory map 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 7 detailed memory map of local data memory relative to cpu subsystems a, b, c, and d 18 . . . . . 3 ? 8 subsystem a local dma memory map 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 9 subsystem b local dma memory map 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 10 subsystem c local dma memory map 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 11 subsystem d local dma memory map 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 12 interfacing to the hpi-16 in non-multiplexed mode 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 13 bscr register bit layout for subsystem a 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 14 xa multiplexer for hpi access 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 15 pin control register (pcr) 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 16 multichannel control register 2 for mcbspx (mcr2x) 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 17 multichannel control register 1 for mcbspx (mcr1x) 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 18 receive channel enable registers bit layout for partitions a to h 31 . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 19 transmit channel enable registers bit layout for partitions a to h 31 . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 20 sa multiplexer for mcbsp1 operation 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 21 timer control register (tcr) 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 22 timer second control register (tscr) 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 23 watchdog timer control register (wdtcr) 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 24 watchdog timer second control register (wdtscr) 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 25 watchdog operation state diagram 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 26 clock mode register (clkmd) 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 27 general-purpose i/o control register 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 28 chip subsystem id register (csidr) 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 29 data memory map register (dmmr) 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 30 bit layout of the imr and ifr registers for each subsystem 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 1 3.3-v test load circuit 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 2 external divide-by-two clock timing 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 3 external multiply-by-one clock timing 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 4 reset and x_bio timings 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 5 interrupt timing 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figures viii december 1999 ? revised december 2001 sprs122d figure page 5 ? 6 external flag (x_xf) timing 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 7 timer (x_tout) timing 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 8 watchdog timer (x_wtout ) timing 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 9 gpio timings 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 10 mcbsp0/1/2 receive timings 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 11 mcbsp0/1/2 transmit timings 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 12 mcbsp0 general-purpose i/o timings 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 13 multiplexed read timings using has 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 14 multiplexed read timings with has held high 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 15 multiplexed write timings using has 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 16 multiplexed write timings with has held high 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 17 nonmultiplexed read timings 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 18 nonmultiplexed write timings 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 19 hpi_sel1 and hpi_sel2 timing 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 1 tms320vc5441 169-ball microstar bga plastic ball grid array (ggu) package 75 . . . . . . . . . . . . . 6 ? 2 tms320vc5441 176-pin low-profile quad flatpack (pgf) package 76 . . . . . . . . . . . . . . . . . . . . . . . tables ix december 1999 ? revised december 2001 sprs122d list of tables table page 2 ? 1 pin assignments for tms320vc5441ggu (169-ball bga package) 4 . . . . . . . . . . . . . . . . . . . . . . 2 ? 2 pin assignments for tms320vc5441pgf (176-pin lqfp package) 6 . . . . . . . . . . . . . . . . . . . . . . 2 ? 3 signal descriptions 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 1 dma synchronization events 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 2 dma channel interrupt selection 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 3 hpi local/shared memory selection 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 4 hpi local/shared memory selection 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 5 bscr register bit functions for subsystem a 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 6 hpi module selection 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 7 sample rate generator clock source selection 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 8 receive channel enable registers for partitions a to h 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 9 transmit channel enable registers for partitions a to h 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 10 tcr bit description 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 11 tscr bit description 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 12 wdtcr bit description 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 13 wdtscr bit description 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 14 clock mode register (clkmd) bit functions 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 15 multiplier related to pllndiv, plldiv, and pllmul 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 16 vco truth table 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 17 vco lockup time 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 18 pll initialization at reset 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 19 general-purpose i/o control register bit functions 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 20 chip subsystem id register bit functions 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 21 data memory map register functions 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 22 processor memory-mapped registers for each dsp subsystem 45 . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 23 peripheral memory-mapped registers for each dsp subsystem 46 . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 24 mcbsp control registers and subaddresses 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 25 dma subbank addressed registers 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 26 5441 interrupt locations and priorities for each dsp subsystem 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 27 bit functions for imr and ifr registers for each dsp subsystem 51 . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 1 thermal resistance characteristics 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 2 divide-by-two, divide-by-four, and bypass clock options timing requirements 57 . . . . . . . . . . . . 5 ? 3 divide-by-two, divide-by-four, and bypass clock options switching characteristics 57 . . . . . . . . . 5 ? 4 multiply-by-n clock option timing requirements 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 5 multiply-by-n clock option switching characteristics 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 6 reset, x_bio , and interrupt timing requirements 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 7 external flag (x_xf), timer (x_tout), and watchdog timer output (x_wtout ) switching characteristics 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 8 gpio timing requirements 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 9 gpio switching characteristics 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 10 mcbsp0/1/2 transmit and receive timing requirements ? 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 11 mcbsp0/1/2 transmit and receive switching characteristics ? 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tables x december 1999 ? revised december 2001 sprs122d table page 5 ? 12 mcbsp0 general-purpose i/o timing requirements 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 13 mcbsp0 general-purpose i/o switching characteristics 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 14 hpi16 timing requirements 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 15 hpi16 switching characteristics 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . features 1 december 1999 ? revised december 2001 sprs122d 1 tms320vc5441 features 532-mips quad-core dsp consisting of four independent subsystems each core has an advanced multibus architecture with three separate 16-bit data memory buses and one program bus 40-bit arithmetic logic unit (alu) including a 40-bit barrel-shifter and two 40-bit accumulators per core each core has a 17-bit 17-bit parallel multiplier coupled to a 40-bit adder for non-pipelined single-cycle multiply/ accumulate (mac) operations each core has a compare, select, and store unit (cssu) for the add/compare selection of the viterbi operator each core has an exponent encoder to compute an exponent value of a 40-bit accumulator value in a single cycle each core has two address generators with eight auxiliary registers and two auxiliary register arithmetic units (araus) total 640k-word 16-bit dual-access on-chip ram (256k-word x 16-bit shared memory and 96k-word x 16-bit local memory per subsystem) single-instruction repeat and block-repeat operations instructions with 32-bit long word operands instructions with 2 or 3 operand reads fast return from interrupts arithmetic instructions with parallel store and parallel load conditional store instructions output control of clkout output control of timer output (tout) power consumption control with idle1, idle2, and idle3 instructions dual 1.6-v (core) and 3.3-v (i/o) power supplies for low-power, fast operations 7.5-ns single-cycle fixed-point instruction twenty-four channels of direct memory access (dma) for data transfers with no cpu loading (six channels per subsystem) twelve multichannel buffered serial ports (mcbsps), each with 128-channel selection capability (three mcbsps per subsystem) 16-bit host-port interface (hpi) software-programmable phase-locked loop (pll) provides several clocking options (requires external ttl oscillator) on-chip scan-based emulation logic, ieee standard 1149.1 (jtag) boundary- scan logic four software-programmable timers (one per subsystem) four software-programmable watchdog timers (one per subsystem) sixteen general-purpose i/os (four per subsystem) provided in 176-pin plastic low-profile quad flatpack (lqfp) package (pgf suffix) provided in 169-ball microstar bga package (ggu suffix) tms320c54x and microstar bga are trademarks of texas instruments. ? ieee standard 1149.1-1990, standard test-access port and boundary scan architecture. introduction 2 december 1999 ? revised december 2001 sprs122d 2 introduction this section describes the main features of the tms320vc5441 digital signal processor (dsp), lists the pin assignments, and describes the function of each pin. this data manual also provides a detailed description section, electrical specifications, parameter measurement information, and mechanical data about the available packaging. note: this data manual is designed to be used in conjunction with the tms320c54x ? dsp functional overview (literature number spru307). 2.1 description the tms320vc5441 fixed-point digital signal processor is a quad-core solution running at 532-mips performance. the 5441 consists of four dsp subsystems with shared program memory. each subsystem consists of one tms320c54x ? dsp core, 32k-word program/data daram, 64k-word data daram, three multichannel buffered serial ports, dma logic, one watchdog timer, one general-purpose timer, and other miscellaneous circuitry. the 5441 also contains a host-port interface (hpi) that allows the 5441 to be viewed as a memory-mapped peripheral to a host processor. each subsystem has its separate program and data spaces, allowing simultaneous accesses to program instructions and data. two read operations and one write operation can be performed in one cycle. instructions with parallel store and application-specific instructions can fully utilize this architecture. furthermore, data can be transferred between program and data spaces. such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. the 5441 includes the control mechanisms to manage interrupts, repeated operations, and function calls. in addition, the 5441 has a total of 256k words of shared program memory (128k words shared by subsystems a and b, and another 128k words shared by subsystems c and d). the 5441 is intended as a high-performance, low-cost, high-density dsp for remote data access or voice-over ip subsystems. it is designed to maintain the current modem architecture with minimal hardware and software impacts, thus maximizing reuse of existing modem technologies and development efforts. the 5441 is offered in two temperature ranges and individual part numbers are shown below. (please note that the industrial temperature device part numbers do not follow the typical numbering tradition.) commercial temperature devices (0 c to 85 c) tms320vc5441pgf532 (176-pin lqfp) tms320vc5441ggu532 (169-ball bga) industrial temperature range devices ( ? 40 c to 100 c) TMS320VC5441PGFA532 (176-pin lqfp) tms320vc5441ggua532 (169-ball bga) note: leading ? x ? in signal names identifies the subsystem; x = a, b, c, or d for subsystem a, b, c, or d, respectively. trailing ? n ? in signal names identifies the mcbsp; n = 0, 1, or 2 for mcbsp0, mcbsp1, or mcbsp2, respectively. introduction 3 december 1999 ? revised december 2001 sprs122d 2.2 migration from the 5421 to the 5441 customers who are migrating from the 5421 to the 5441 need to take into account the following differences between the two devices. ? the 5441 provides four cores in a 169-ball ball grid array (bga) and a 176-pin low-profile quad flatpack (lqfp). ? the 5441 does not have a xio interface for external memory connection. ? each subsystem includes a 32k-word daram program/data memory and a 64k-word daram data memory. ? the dma has been changed and now provides no access to external memory. ? the hpi and dma memory maps have been changed to incorporate the new 5441 memory structure. ? the 2k words of rom on the 5421 is not implemented on the 5441. ? the four mcbsp1s and four mcbsp2s have been internally multiplexed onto two sets of external pins. ? the hpi_sel1 and hpi_sel2 pins on 5441 are used to facilitate hpi module selection among the four subsystems. ? the 5441 provides four watchdog timers (one per subsystem). ? gpio0 and gpio1 pins are multiplexed with x_xf and x_bio pins, respectively. ? only the global reset (reset ) will reset the pll. 2.3 pin assignments figure 2 ? 1 illustrates the ball locations for the 169-ball ball grid array (bga) package and is used in conjunction with table 2 ? 1 to locate signal names and ball grid numbers. figure 2 ? 2 illustrates the pin locations for the 176-pin low-profile quad flatpack (lqfp); table 2 ? 2 lists each pin number and its associated pin name for this package. 2.3.1 pin assignments for the ggu package g a d b c e f h j l k m n 5 13 2 4 6 7 8 9 10111213 figure 2?1. 169-ball ggu microstar bga ? (bottom view) introduction 4 december 1999 ? revised december 2001 sprs122d table 2 ? 1. pin assignments for tms320vc5441ggu (169-ball bga package) ? ball # signal name ball # signal name ball # signal name ball # signal name a1 ha[0]/hcntl0 a2 dv dd a3 v ss a4 b_bdr0 a5 cv dd a6 v ss a7 dv dd a8 v ss a9 cv dd a10 d_bdr0 a11 v ss a12 dv dd a13 d_bfsx0 b1 ha[1]/hcntl1 b2 b_bfsx0 b3 b_bfsr0 b4 b_bdx0 b5 cv dd b6 hd[7] b7 hd[3] b8 hd[0] b9 cv dd b10 d_gpio0/d_xf b11 d_bdx0 b12 d_bfsr0 b13 ha[18] c1 v ss c2 ha[3]/b_hint c3 b_gpio1/b_bio c4 b_gpio0/b_xf c5 cv dd c6 b_bclkr0 c7 hd[4] c8 d_gpio3/d_tout c9 cv dd c10 d_bclkx0 c11 ha[17] c12 ha[15] c13 v ss d1 clkmd d2 b_nmi d3 b_rs d4 ha[4]/c_hint d5 cv dd d6 b_bclkx0 d7 hd[5] d8 d_gpio1/d_bio d9 cv dd d10 d_bclkr0 d11 d_rs d12 d_int d13 trst e1 dv dd e2 testb e3 tdi e4 b_int e5 ha[2]/a_hint e6 b_gpio3/b_tout e7 hd[6] e8 hd[1] e9 d_gpio2/d_wtout e10 testd e11 tms e12 tck e13 dv dd f1 v ssa f2 v ss f3 hcs f4 has f5 clkin f6 b_gpio2/b_wtout f7 hd[2] f8 ha[16] f9 d_nmi f10 emu1/off f11 hpi_sel2 f12 hpi_sel1 f13 v ss g1 v cca g2 cv dd g3 emu0 g4 bclkr2 g5 bclkx2 g6 hrdy g7 bdr1 g8 hmode g9 hds2 g10 c_nmi g11 reset g12 hr/w g13 cv dd h1 v ss h2 bfsr2 h3 bfsx2 h4 clkout h5 a_int h6 ha[7] h7 hd[9] h8 c_gpio1/c_bio h9 bclkx1 h10 bclkr1 h11 bfsr1 h12 bfsx1 h13 v ss j1 dv dd j2 bdr2 j3 bdx2 j4 a_rs j5 a_gpio1/a_bio j6 hd[8] j7 hd[13] j8 c_bclkr0 j9 ha[11] j10 c_int j11 c_rs j12 bdx1 j13 dv dd k1 v ss k2 a_nmi k3 tdo k4 a_gpio3/a_tout k5 cv dd k6 a_gpio2/a_wtout k7 hd[12] k8 c_bclkx0 k9 cv dd k10 ha[13] k11 ha[14] k12 testc k13 hds1 l1 ha[5]/d_hint l2 ha[6] l3 ha[8] l4 a_gpio0/a_xf l5 cv dd l6 a_bclkr0 l7 hd[11] l8 hd[15] l9 cv dd l10 c_gpio0/c_xf l11 c_gpio2/c_wtout l12 ha[12] l13 v ss m1 v ss m2 ha[9] m3 a_bfsr0 m4 a_bdr0 m5 cv dd m6 a_bclkx0 m7 hd[10] m8 hd[14] m9 cv dd m10 c_gpio3/c_tout m11 c_bdx0 m12 c_bfsr0 m13 ha[10] n1 a_bfsx0 n2 dv dd n3 v ss n4 a_bdx0 n5 cv dd n6 v ss n7 dv dd n8 v ss n9 cv dd n10 c_bdr0 n11 v ss n12 dv dd n13 c_bfsx0 ? cells highlighted in gray indicate pins that perform a multiplexed function. introduction 5 december 1999 ? revised december 2001 sprs122d 2.3.2 pin assignments for the pgf package 89 88 45 44 132 133 176 1 figure 2 ? 2. 176-pin pgf low-profile quad flatpack (top view) introduction 6 december 1999 ? revised december 2001 sprs122d table 2 ? 2. pin assignments for tms320vc5441pgf (176-pin lqfp package) ? pin no. signal name pin no. signal name pin no. signal name pin no. signal name 1 ha[0]/hcntl0 2 ha[1]/hcntl1 3 ha[2]/a_hint 4 ha[3]/b_hint 5 ha[4]/c_hint 6 v ss 7 v ss 8 b_rs 9 b_nmi 10 b_int 11 clkmd 12 tdi 13 testb 14 dv dd 15 has 16 hcs 17 v ss 18 v ssa 19 clkin 20 hrdy 21 v cca 22 cv dd 23 cv dd 24 emu0 25 bclkr2 26 bclkx2 27 v ss 28 bfsr2 29 bfsx2 30 clkout 31 dv dd 32 bdr2 33 bdx2 34 v ss 35 a_rs 36 a_nmi 37 a_int 38 tdo 39 ha[5]/d_hint 40 ha[6] 41 ha[7] 42 ha[8] 43 v ss 44 ha[9] 45 a_bfsx0 46 dv dd 47 a_gpio1/a_bio 48 a_bfsr0 49 a_gpio3/a_tout 50 v ss 51 a_gpio0/a_xf 52 a_bdr0 53 cv dd 54 a_bdx0 55 cv dd 56 cv dd 57 cv dd 58 a_gpio2/a_wtout 59 a_bclkr0 60 a_bclkx0 61 v ss 62 hd[8] 63 hd[9] 64 dv dd 65 dv dd 66 hd[10] 67 hd[11] 68 hd[12] 69 hd[13] 70 v ss 71 hd[14] 72 hd[15] 73 c_bclkx0 74 cv dd 75 cv dd 76 cv dd 77 c_bdr0 78 cv dd 79 c_gpio3/c_tout 80 c_bclkr0 81 c_gpio0/c_xf 82 v ss 83 c_bdx0 84 c_gpio1/c_bio 85 c_gpio2/c_wtout 86 dv dd 87 dv dd 88 c_bfsr0 89 c_bfsx0 90 ha[10] 91 ha[11] 92 ha[12] 93 ha[13] 94 v ss 95 ha[14] 96 testc 97 c_int 98 hds1 99 c_rs 100 bdx1 101 bdr1 102 bclkr1 103 dv dd 104 bfsr1 105 bfsx1 106 v ss 107 bclkx1 108 hmode 109 cv dd 110 hr/w 111 reset 112 c_nmi 113 hds2 114 v ss 115 hpi_sel1 116 hpi_sel2 117 emu1/off 118 dv dd 119 tck 120 tms 121 trst 122 testd 123 d_int 124 d_nmi 125 d_rs 126 v ss 127 v ss 128 ha[15] 129 ha[16] 130 ha[17] 131 ha[18] 132 d_bfsr0 133 d_bfsx0 134 dv dd 135 dv dd 136 d_gpio2/d_wtout 137 d_bdx0 138 d_bclkr0 139 v ss 140 d_bclkx0 141 d_gpio0/d_xf 142 cv dd 143 d_bdr0 144 cv dd 145 cv dd 146 cv dd 147 d_gpio1/d_bio 148 d_gpio3/d_tout 149 hd[0] 150 v ss 151 hd[1] 152 hd[2] 153 dv dd 154 hd[3] 155 hd[4] 156 hd[5] 157 hd[6] 158 v ss 159 hd[7] 160 b_bclkr0 161 b_bclkx0 162 cv dd 163 cv dd 164 cv dd 165 b_bdr0 166 cv dd 167 b_bdx0 168 b_gpio3/b_tout 169 b_gpio0/b_xf 170 v ss 171 b_bfsr0 172 b_gpio2/b_wtout 173 b_gpio1/b_bio 174 dv dd 175 dv dd 176 b_bfsx0 ? cells highlighted in gray indicate pins that perform a multiplexed function. introduction 7 december 1999 ? revised december 2001 sprs122d 2.4 signal descriptions table 2 ? 3 lists all the signals, grouped by function. see section 2.3 for the exact pin locations based on the package type. pin functions highlighted in gray are secondary (multiplexed) functions. table 2 ? 3. signal descriptions name type ? description host-port interface signals ha18 (msb) ha17 ha16 ha15 ha14 ha13 ha12 ha11 ha10 ha9 ha8 ha7 ha6 i ? hpi address pins when hpi is in nonmultiplexed mode. ha18 is used to facilitate program (shared) memory and data (local) memory selection. the pins include bus holders to reduce power dissipation caused by floating, unused pins. the bus holders also eliminate the need for external pullup resistors on unused pins. when the address bus is not being driven by the external host, the bus holders keep address pins at the last driven logic level. the address bus keepers are disabled at global reset or subsystem a reset, and can be enabled/disabled via the bha bit of the bscr register in subsystem a. secondary ha5 ha4 ha3 ha2 d_hint c_hint b_hint a_hint o/z ha1 ha0 (lsb) hcntl1 hcntl0 i hd15 (msb) hd14 hd13 hd12 hd11 hd10 hd9 hd8 hd7 hd6 hd5 hd4 hd3 hd2 hd1 hd0 (lsb) i/o/z ? parallel bidirectional data bus. these pins are the hpi data bus. the pins include bus holders to reduce power dissipation caused by floating, unused pins. the bus holders also eliminate the need for external pullup resistors on unused pins. when the data bus is not being driven by the 5441, the bus holders keep data pins at the last driven logic level. the data bus keepers are disabled at global reset or subsystem a reset, and can be enabled/disabled via the bhd bit of the bscr register in subsystem a. ? i = input, o = output, s = supply, z = high impedance ? this pin has an internal bus holder controlled by way of the bscr register in tms320c54x ? clead core of dsp subsystem a. this pin is placed in high-impedance when the emu1/off pin operates as off and when emu1/off = 0, this case is exclusively for testing and emulation purposes. ? this pin has an internal pullup resistor. # these pins are schmitt triggered inputs. || this pin is used by texas instruments for device testing and should be left unconnected. this pin has an internal pulldown resistor. note: pins highlighted in grey indicate the multiplexed function of the pin. introduction 8 december 1999 ? revised december 2001 sprs122d table 2 ? 3. signal descriptions (continued) name description type ? host-port interface signals (continued) hmode ? i hpi mode select. when this pin is low, it selects the hpi multiplexed address/data mode. the multiplexed address/data mode allows hosts with multiplexed address/data lines access to the hpi registers hpia, hpic, and hpid. host-to-dsp and dsp-to-host interrupts are supported in this mode. when hmode is high, it selects the hpi nonmultiplexed mode. hpi nonmultiplexed mode allows hosts with separate address/data buses to access the hpi address range by way of the 19-bit address bus and the hpi data (hpid) register via the 16-bit data bus. host-to-dsp and dsp-to-host interrupts are not supported in this mode. has ? # i hpi address latch enable (ale) or address strobe input. hosts with multiplexed address and data pins require has to latch the address in the hpia register. this signal is used only in hpi multiplexed address/data mode (hmode = 0). hrdy o/z hpi data ready output. the ready output informs the host when the hpi is ready for the next transfer. while driving, it is in output state and while not driving, it is in high-z state. hr/w i hpi read/write strobe. this signal is used by the host to control the direction of an hpi transfer. hds1 ? # hds1 hds2 ? # i hpi data strobes. driven by the host read and write strobes to control hpi transfers. hcs ? # i hpi chip select. must be active during hpi transfers and can remain active between concurrent transfers. primary d_hint c_hint b_hint a_hint o/z ha5 ha4 ha3 ha2 i host interrupt pins. hpi can interrupt the host by asserting this low. the host can clear this interrupt by writing a ? 1 ? to the hint bit of the hpic register. only supported in hpi multiplexed address/data mode (hmode pin low) hcntl1 hcntl0 i ha1 ha0 i hpi control pins. these pins select a host access to the hpia, hpic, and hpid registers. only supported in hpi multiplexed address/data mode (hmode pin low) hpi_sel1 hpi_sel1 hpi_sel2 i subsystem hpi module select multichannel buffered serial ports 0, 1, and 2 signals a_bclkr0 # b_bclkr0 # c_bclkr0 # d_bclkr0 # i/o/z receive clocks. x_bclkr0 serve as the serial shift clocks for the buffered serial-port receiver. input from an external clock source for clocking data into the mcbsp. when not being used as clocks, these pins can be used as general-purpose i/os by setting rioen = 1. x_bclkr0 can be configured as outputs by way of the clkrm bit in the pcr register. a_bclkx0 # b_bclkx0 # c_bclkx0 # d_bclkx0 # i/o/z transmit clocks. clock signals used to clock data from the transmit register. these pins can also be configured as inputs by setting clkxm = 0 in the pcr register. x_bclkx0 can be sampled as inputs by way of the in1 bit in the spc register. when not being used as clocks, these pins can be used as general-purpose i/os by setting xioen = 1. a_bdr0 b_bdr0 c_bdr0 d_bdr0 i buffered serial data receive (input) pins. when not being used as data-receive pins, these pins can be used as general-purpose i/os by setting rioen = 1. ? i = input, o = output, s = supply, z = high impedance ? this pin has an internal bus holder controlled by way of the bscr register in tms320c54x ? clead core of dsp subsystem a. this pin is placed in high-impedance when the emu1/off pin operates as off and when emu1/off = 0, this case is exclusively for testing and emulation purposes. ? this pin has an internal pullup resistor. # these pins are schmitt triggered inputs. || this pin is used by texas instruments for device testing and should be left unconnected. this pin has an internal pulldown resistor. note: pins highlighted in grey indicate the multiplexed function of the pin. introduction 9 december 1999 ? revised december 2001 sprs122d table 2 ? 3. signal descriptions (continued) name description type ? multichannel buffered serial ports 0, 1, and 2 signals (continued) a_bdx0 b_bdx0 c_bdx0 d_bdx0 o/z buffered serial-port transmit (output) pins. when not being used as data-transmit pins, x_bdx0 can be used as general-purpose i/os by setting xioen = 1. a_bfsr0 b_bfsr0 c_bfsr0 d_bfsr0 i/o/z frame synchronization pins for buffered serial-port input data. the x_bfsr0 pulse initiates the receive-data process over x_bdr0. when not being used as data-receive synchronization pins, these pins can be used as general-purpose i/os by setting rioen = 1. a_bfsx0 b_bfsx0 c_bfsx0 d_bfsx0 i/o/z buffered serial-port frame synchronization pins for transmitting data. the x_bfsx0 pulse initiates the transmit-data process over the x_bdx0 pin. if x_rs is asserted when x_bfsx0 is configured as output, then x_bfsx0 is turned into input mode by the reset operation. when not being used as data-transmit synchronization pins, these pins can be used as general-purpose i/os by setting xioen = 1. bclkr1 # receive clock, multiplexed mcbsp1 bclkx1 # i transmit clock, multiplexed mcbsp1 bdr1 i receive data, multiplexed mcbsp1 bdx1 o/z transmit data, multiplexed mcbsp1 bfsr1 receive frame sync, multiplexed mcbsp1 bfsx1 i transmit frame sync, multiplexed mcbsp1 bclkr2 # receive clock, multiplexed mcbsp2 bclkx2 # i transmit clock, multiplexed mcbsp2 bdr2 i receive data, multiplexed mcbsp2 bdx2 o/z transmit data, multiplexed mcbsp2 bfsr2 receive frame sync, multiplexed mcbsp2 bfsx2 i transmit frame sync, multiplexed mcbsp2 clocking signals master clock output signal. clkout cycles at the machine-cycle rate of the cpu. the internal machine cycle is bounded by the falling edges of this signal. the clkout pin can be turned off by writing a ? 1 ? to the clkout bit of the pmst register. multiplexed as shown below based on the selection bits in the gpio register clkout o/z gpio[7] gpio[6] a_clkout 0 0 (default) b_clkout || 01 c_clkout || 10 d_clkout || 11 clkin # i input clock to the device. clkin connects to a pll. clkmd # i clock mode configuration pin at reset. when clkmd = 0, bypasses pll; when clkmd = 1, clkinx2 ? i = input, o = output, s = supply, z = high impedance ? this pin has an internal bus holder controlled by way of the bscr register in tms320c54x ? clead core of dsp subsystem a. this pin is placed in high-impedance when the emu1/off pin operates as off and when emu1/off = 0, this case is exclusively for testing and emulation purposes. ? this pin has an internal pullup resistor. # these pins are schmitt triggered inputs. || this pin is used by texas instruments for device testing and should be left unconnected. this pin has an internal pulldown resistor. note: pins highlighted in grey indicate the multiplexed function of the pin. introduction 10 december 1999 ? revised december 2001 sprs122d table 2 ? 3. signal descriptions (continued) name description type ? general-purpose i/o pins a_gpio0/ a_xf subsystem a gpio0/ subsystem a external flag output b_gpio0/ b_xf subsystem b gpio0/ subsystem b external flag output these pins act according to the general-purpose i/o register. the x_xf bit must be set to ? 1 ? to drive the c_gpio0/ c_xf i/o/z subsystem c gpio0/ subsystem c external flag output x_xf bit must be set to ? 1 ? to drive the x_xf output on the pin. if x_xf=0, then these pins are general-purpose d_gpio0/ d_xf subsystem d gpio0/ subsystem d external flag output i/os. a_gpio1/ a_bio subsystem a gpio1/ subsystem a branch control input b_gpio1/ b_bio subsystem b gpio1/ subsystem b branch control input these pins act according to the general-purpose i/o register. the x_bio bit must be set to ? 1 ? to drive the c_gpio1/ c_bio i/o/z subsystem c gpio1/ subsystem c branch control input x_bio bit must be set to ? 1 ? to drive the x_bio input into the device. if x_bio =0, then these pins are general-purpose i/o pins (software- d_gpio1/ d_bio subsystem d gpio1/ subsystem d branch control input general-purpose i/os. programmable i/o signal). values can be latched (output) by writing into the gpio register. the states of gpio a_gpio2/ a_wtout subsystem a gpio2/ subsystem a watchdog timer output the gpio register. the states of gpio pins (inputs) can be determined by reading the gpio register. the gpio b_gpio2/ b_wtout subsystem b gpio2/ subsystem b watchdog timer output the watchdog enable (wden) bit in the watchdog timer register (wdtscr) is used to multiplex the direction is also programmable by way of the dirn field in the register. c_gpio2/ c_wtout i/o/z subsystem c gpio2/ subsystem c watchdog timer output (wdtscr) is used to multiplex the watchdog timer output and gpio2. if wden=0, then these pins are d_gpio2/ d_wtout subsystem d gpio2/ subsystem d watchdog timer output general-purpose i/os. a_gpio3/ a_tout subsystem a gpio3/ subsystem a timer output b_gpio3/ b_tout subsystem b gpio3/ subsystem b timer output these pins act according to the general-purpose i/o register. the x_tout bit must be set to ? 1 ? to drive c_gpio3/ c_tout i/o/z subsystem c gpio3/ subsystem c timer output x_tout bit must be set to ? 1 ? to drive the timer output on the pin. if x_tout=0, then these pins are d_gpio3/ d_tout subsystem d gpio3/ subsystem d timer output general-purpose i/os. ? i = input, o = output, s = supply, z = high impedance ? this pin has an internal bus holder controlled by way of the bscr register in tms320c54x ? clead core of dsp subsystem a. this pin is placed in high-impedance when the emu1/off pin operates as off and when emu1/off = 0, this case is exclusively for testing and emulation purposes. ? this pin has an internal pullup resistor. # these pins are schmitt triggered inputs. || this pin is used by texas instruments for device testing and should be left unconnected. this pin has an internal pulldown resistor. note: pins highlighted in grey indicate the multiplexed function of the pin. introduction 11 december 1999 ? revised december 2001 sprs122d table 2 ? 3. signal descriptions (continued) name description type ? initialization, interrupt, and reset operations a_int ? # b_int ? # c_int ? # d_int ? # i external user interrupts. a_int ? d_int are prioritized and are maskable by the interrupt mask register (imr) and the interrupt mode bit. the status of these pins can be polled and reset by way of the interrupt flag register (ifr). a_nmi ? # b_nmi ? # c_nmi ? # d_nmi ? # i nonmaskable interrupts. x_nmi is an external interrupt that cannot be masked by way of the intm bit or the imr. when x_nmi is activated, the processor traps to the appropriate vector location. a_rs # b_rs # c_rs # d_rs # i reset. x_rs causes the digital signal processor (dsp) to terminate execution and causes a reinitialization of the cpu and peripherals. when x_rs is brought to a high level, execution begins at location 0ff80h of program memory. x_rs affects various registers and status bits. reset # i global/hpi reset. this signal resets the four subsystems and the hpi. supply pins v cca dedicated power supply that powers the pll. v dd = 1.6 v cv dd dedicated power supply that powers the core cpus. cv dd = 1.6 v dv dd dedicated power supply that powers the i/o pins. dv dd = 3.3 v v ss s digital ground. dedicated ground plane for the device. v ssa analog ground. dedicated ground for the pll. v ssa can be connected to v ss if digital and analog grounds are not separated. emulation/test pins testb || testc || testd || no connection tck ? # i standard test clock. this is normally a free-running clock signal with a 50% duty cycle. changes on the test access port (tap) input signals tms and tdi are clocked into the tap controller, instruction register, or selected test-data register on the rising edge of tck. changes at the tap output signal (tdo) occur on the falling edge of tck. tdi ? i test data input. pin with an internal pullup device. tdi is clocked into the selected register (instruction or data) on a rising edge of tck. tdo o/z test data pin. the contents of the selected register is shifted out of tdo on the falling edge of tck. tdo is in high-impedance state except when the scanning of data is in progress. tms ? i test mode select. pin with internal pullup device. this serial control input is clocked into the tap controller on the rising edge of tck. trst i test reset. when high, trst gives the scan system control of the operations of the device. if trst is driven low, the device operates in its functional mode and the ieee 1149.1 signals are ignored. pin with internal pulldown device. emu0 i/o/z emulator interrupt 0 pin. when trst is driven low, emu0 must be high for the activation of the emu1/off condition. when trst is driven high, emu0 is used as an interrupt to or from the emulator system and is defined as i/o. ? i = input, o = output, s = supply, z = high impedance ? this pin has an internal bus holder controlled by way of the bscr register in tms320c54x ? clead core of dsp subsystem a. this pin is placed in high-impedance when the emu1/off pin operates as off and when emu1/off = 0, this case is exclusively for testing and emulation purposes. ? this pin has an internal pullup resistor. # these pins are schmitt triggered inputs. || this pin is used by texas instruments for device testing and should be left unconnected. this pin has an internal pulldown resistor. note: pins highlighted in grey indicate the multiplexed function of the pin. introduction 12 december 1999 ? revised december 2001 sprs122d table 2 ? 3. signal descriptions (continued) name description type ? emulation/test pins (continued) emu1/off i/o/z emulator interrupt 1 pin. when trst is driven high, emu1/off is used as an interrupt to or from the emulator system and is defined as i/o. when trst transitions from high to low, then emu1 operates as off . emu/off = 0 puts all output drivers into the high-impedance state. note that off is used exclusively for testing and emulation purposes (and not for multiprocessing applications). therefore, for the off condition, the following conditions apply: trst = 0, emu0 = 1, emu1 = 0 ? i = input, o = output, s = supply, z = high impedance ? this pin has an internal bus holder controlled by way of the bscr register in tms320c54x ? clead core of dsp subsystem a. this pin is placed in high-impedance when the emu1/off pin operates as off and when emu1/off = 0, this case is exclusively for testing and emulation purposes. ? this pin has an internal pullup resistor. # these pins are schmitt triggered inputs. || this pin is used by texas instruments for device testing and should be left unconnected. this pin has an internal pulldown resistor. note: pins highlighted in grey indicate the multiplexed function of the pin. functional overview 13 december 1999 ? revised december 2001 sprs122d 3 functional overview the functional overview in this section is based on the overall system block diagram in figure 3 ? 1 and the typical subsystem block diagram in figure 3 ? 2. gpio mcbsp0 mcbsp1 mcbsp2 dsp subsystem a dsp id: 0000 hpi xa pll shared p bus mcbsp2 mcbsp1 mcbsp0 gpio hpi dsp subsystem c dsp id: 0010 shared p bus sa1 dsp subsystem b dsp id: 0001 gpio mcbsp0 mcbsp1 mcbsp2 hpi dsp id: 0011 subsystem d dsp gpio mcbsp0 mcbsp1 mcbsp2 mcbsp1 mcbsp2 hpi sa2 figure 3 ? 1. overall functional block diagram p. c. d. e. busses and control signals p bus c bus d bus e bus tms320c54x clead (core) 64k-word data daram m bus 32k-word program/data daram m bus 3 mcbsp m bus shared p bus m bus timer dma wdtimer gpio hpi c bus d bus e bus p bus c bus d bus e bus p bus dsp subsystem hpi bus m bus 64k-word program daram figure 3 ? 2. typical subsystem functional block diagram functional overview 14 december 1999 ? revised december 2001 sprs122d 3.1 memory each 5441 dsp subsystem maintains the peripheral register memory map and interrupt location/priorities of the standard 5421. each individual subsystem cpu memory map is illustrated in figure 3 ? 3 through figure 3 ? 6. the arbitration and access for local program/data memory and local data memory is based on a 16k-word block size. the arbitration and access for all the shared memory is based on a 32k-word block size. 3.1.1 memory maps figure 3 ? 3 through figure 3 ? 6 illustrate the cpu memory maps for subsystem a through subsystem d. figure 3 ? 7 provides a detailed memory map of the local data memory relative to cpu subsystems a, b, c, and d. page 0 data memory page 1 8000h page 2 ffffh page 3 0000h mpda page 0 data memory page 1 program memory page 2 page 3 0000h 8000h ffffh : reserved program memory memory map with ovly = 1 mpda mpda mpda mpda mpab3 mpab0 mpab1 mpab2 mpab3 mpda mpab3 mpab3 mpab3 mpab0 mpab1 mpab2 memory map with ovly = 0 mda0 or mda1 mda0 or mda1 notes: a. mpda: local program/data memory in subsystem a b. mda: local data memory in subsystem a. mda is controlled by the data memory map register (dmmr). dmmr=0, mda0 is mapped in 8000h ? ffffh. dmmr=1, mda1 is mapped in 8000h ? ffffh. c. mpab: shared program memory in subsystems a and b figure 3 ? 3. subsystem a cpu memory map functional overview 15 december 1999 ? revised december 2001 sprs122d page 0 data memory page 1 program memory page 2 page 3 0000h 8000h ffffh mpdb mpdb page 0 data memory page 1 program memory page 2 page 3 mpab3 0000h 8000h ffffh mpdb ?? : reserved mpab3 mpab0 mpab1 mpab2 mpab0 mpab1 mpab2 memory map with ovly = 1 memory map with ovly = 0 mpdb mpdb mpdb mpab3 mpab3 mpab3 mdb0 or mdb1 mdb0 or mdb1 notes: a. mpdb: local program/data memory in subsystem b b. mdb: local data memory in subsystem b. mdb is controlled by the data memory map register (dmmr). dmmr=0, mdb0 is mapped in 8000h ? ffffh. dmmr=1, mdb1 is mapped in 8000h ? ffffh. c. mpab: shared program memory in subsystems a and b figure 3 ? 4. subsystem b cpu memory map functional overview 16 december 1999 ? revised december 2001 sprs122d page 0 data memory page 1 program memory page 2 page 3 0000h 8000h ffffh mpdc mpdc page 0 data memory page 1 program memory page 2 page 3 mpcd3 0000h 8000h ffffh mpdc : reserved mpcd3 mpcd0 mpcd1 mpcd2 mpcd0 mpcd1 mpcd2 memory map with ovly = 0 memory map with ovly = 1 mpdc mpdc mpdc mpcd3 mpcd3 mpcd3 mdc0 or mdc1 mdc0 or mdc1 notes: a. mpdc: local program/data memory in subsystem c b. mdc: local data memory in subsystem c. mdc is controlled by the data memory map register (dmmr). dmmr=0, mdc0 is mapped in 8000h ? ffffh. dmmr=1, mdc1 is mapped in 8000h ? ffffh. c. mpcd: shared program memory in subsystems c and d figure 3 ? 5. subsystem c cpu memory map functional overview 17 december 1999 ? revised december 2001 sprs122d page 0 data memory page 1 program memory page 2 page 3 0000h 8000h ffffh mpdd mpdd page 0 data memory page 1 program memory page 2 page 3 mpcd3 0000h 8000h ffffh mpdd ?? ?? reserved mpcd3 mpcd0 mpcd1 mpcd2 mpcd0 mpcd1 mpcd2 mpdd mpdd mpdd mpcd3 mpcd3 mpcd3 memory map with ovly = 1 memory map with ovly = 0 mdd0 or mdd1 mdd0 or mdd1 notes: a. mpdd: local program/data memory in subsystem d b. mdd: local data memory in subsystem d. mdd is controlled by the data memory map register (dmmr). dmmr=0, mdd0 is mapped in 8000h ? ffffh. dmmr=1, mdd1 is mapped in 8000h ? ffffh. c. mpcd: shared program memory in subsystems c and d figure 3 ? 6. subsystem d cpu memory map figure 3 ? 7 shows the cpu data memory map. the lower 32k-word data memory location in all pages is the overlay area. program memory has overlay area over the lower 32k words on all pages as well. the overlay areas refer to: 1. when ovly = 1, the lower 32k words of data space are mapped to the lower 32k words of all program pages in the memory map. 2. when ovly = 0, the lower 32k words of data space are mapped only to the lower 32k words of data space and the lower 32k words of program page 3 are mapped to the lower 32k words of all program pages. functional overview 18 december 1999 ? revised december 2001 sprs122d memory- mapped registers 00 0000 00 005f 00 0060 00 7fff 00 8000 00 ffff hex data memory 16k words 16k words 16k words 16k words 00 3fff 00 4000 00 bfff 00 c000 daram0 daram1 daram2 (dmmr=0) daram4 daram3 daram5 (dmmr=0) (dmmr=1) (dmmr=1) note: the upper part of data memory is controlled by the data memory map register (dmmr). 1. dmmr=0, daram2 and daram3 are mapped in 8000h ? ffffh. 2. dmmr=1, daram4 and daram5 are mapped in 8000h ? ffffh. figure 3 ? 7. detailed memory map of local data memory relative to cpu subsystems a, b, c, and d 3.1.2 on-chip dual-access ram (daram) each 5441 subsystem has 96k 16-bit words of on-chip daram (six blocks of 16k words). each of these daram blocks can be accessed twice per machine cycle. this memory is intended primarily to store data values; however, it can be used to store program as well. at reset, the daram is mapped into data memory space (ovly=0). the lower part of daram (0000h ? 8000h) can be mapped into program/data memory space by setting the ovly bit in the processor-mode status (pmst) register of the tms320c54x ? clead cpu in each dsp subsystem. 3.1.3 on-chip two-way shared ram there are 128k 16-bit words of on-chip ram (four blocks of 32k words) that are shared between subsystems a and b. there are 128k 16-bit words of on-chip ram (four blocks of 32k words) that are shared between subsystems c and d. this memory is intended to store program only. both subsystems are able to make one instruction fetch from any location in the two-way shared memory each cycle simultaneously. no subsystem cpu can write to the shared memory as only the dma can write to shared memory. if any of the cpu program fetches are requested at the same time as an m-bus transfer request, the cpu is stalled until all m bus transfers are completed. in other words, any read or write requested by the m bus (driven by dma controller or hpi) has priority over the cpus ? (a, b, c, and d) program fetches. the m-bus reads or writes always take two cycles to complete. functional overview 19 december 1999 ? revised december 2001 sprs122d 3.1.4 extended data memory the data memory space of each 5441 subsystem addresses 128k 16-bit words. there are two pages of data memory location with each page consisting of 64k words. the 5441 device uses a data memory map register (dmmr) to facilitate extended data memory access. the dmmr is a peripheral memory-mapped register. the contents of the dmmr register, once being written with an extended data number by the dsp cpu, will be associated with the address decoding for all the data memory cpu accesses. 3.1.5 extended program memory the 5441 device uses a paged extended memory scheme in program space to allow access to 256k 16-bit words. this extended program memory (each subsystem) is organized into four pages (0 ? 3), pages 0 ? 3 are two-way shared memory. each page is 64k words in length. the program counter extension register (xpc) defines the program page selection. to implement the extended program memory scheme, the 5441 device includes the following feature: ? two c54x ? instructions allow each subsystem cpu access to the on-chip program memory. ? reada ? read program memory addressed by accumulator a and store in data memory ? writa ? write data to program memory addressed by accumulator a (writes not allowed for cpus to shared program memory) 3.1.6 program memory the program memory is accessible on multiple pages, depending on the xpc value. within these pages, memory is accessible depending on the address range. ? access in the lower 32k words of each page is dependent on the state of ovly. ? ovly = 0 ? program memory is accessed from program memory page 3 for all values of xpc. ? ovly = 1 ? program memory is accessed from local data/program daram for all values of xpc. ? access in the upper 32k words of each page is dependent on the state of ovly. ? ovly = 0 ? all pages of program memory except page 3 (which is reserved) are accessible for all values of xpc. ? ovly = 1 ? all pages of program memory are accessible for all values of xpc. 3.1.7 data memory accesses on extended data spaces are dependent on the value of the data memory map register (dmmr). within the page, memory is accessible depending on the address range. ? access in the lower 32k words ? data memory is accessed from local data/program daram for all values of dmmr. ? access in the upper 32k words ? which data memory block is accessed depends on the value of dmmr. ? there are four 16k-word daram blocks for the upper addresses (8000h ? ffffh) dmmr=0: daram2 and daram3 are mapped to the upper addresses dmmr=1: daram4 and daram5 are mapped to the upper addresses 3.1.8 i/o memory the 5441 does not support i/o memory accesses. c54x is a trademark of texas instruments. functional overview 20 december 1999 ? revised december 2001 sprs122d 3.1.9 multicore reset signals the 5441 device includes five reset signals: a_rs , b_rs , c_rs , d_rs , and reset . the a_rs , b_rs , c_rs , and d_rs local reset signals function as the cpu reset signal for subsystem a, b, c, and d, respectively. the reset services as a global reset for the whole device. the global reset (reset ) is a superset of local resets a_rs , b_rs , c_rs , and d_rs . the assertion of reset triggers all the local resets; however, none of the local resets triggers the global reset. the local reset signals reset the state of the cpu registers and cpu memory-mapped peripheral registers, and upon release, initiate the reset function. the global reset, reset , resets the on-chip pll and clears the watchdog timer flag (wdflag) bit. the local reset signals are not able to reset the pll or clear the wdflag. the global reset (reset ) and local resets (x_rs ) clears the program counter extension register (xpc) to zero while the reset instruction does not affect the xpc. 3.1.10 device bootload the 5441 device supports an hpi boot sequence, which is used to download code while the dsp is in reset. the external master holds the device in reset while it loads code to the on-chip memory of each subsystem, subsystem selection is made by hpi_sel1 and hpi_sel2 signals. the host can release the 5441 from reset by using either of the following methods. ? if the x_rs (x = a, b, c, or d for subsystem a, b, c, or d, respectively) pins are held low while reset transitions from low to high, the reset of each subsystem will be controlled by the x_rs pins. when the host has finished downloading code, it can drive x_rs high to release the cores from reset. ? if the x_rs pins are held high while reset transitions from low to high, the subsystems will stay in reset until an hpi data write to address 0x2f occurs. this means the host can download code to subsystem x and then release core x from reset by writing any data to core x ? s address 0x2f via the hpi. the host can then repeat the sequence for other cores. this mode allows the host to control 5441 reset without additional hardware. 3.2 on-chip peripherals all the c54x ? devices have the same cpu structure; however, they have different on-chip peripherals connected to their cpus. the on-chip peripheral options provided are: ? dma controller ? 16-bit host-port interface i/o ports ? multichannel buffered serial ports (mcbsps) ? a hardware timer ? a hardware watchdog timer ? a software-programmable clock generator using a phase-locked loop (pll) ? general-purpose i/o 3.2.1 direct memory access (dma) controller the 5441 includes four 6-channel direct memory access (dma) controllers for performing data transfers independent of the cpu, one controller for each subsystem. the primary function of the 5441 dma controller is to provide code overlays and to manage data transfers between on-chip memory, the peripherals, and off-chip host. in the background of cpu operation, the 5441 dma allows movement of data between internal program/data memory and internal peripherals, such as the mcbsps and the hpi. each subsystem has its own independent dma with six programmable channels, which allows for six different contexts for dma operation. the hpi has a dedicated auxiliary dma channel. the remapped areas represent address aliasing for dma accesses within each subsystem. figure 3 ? 8 through figure 3 ? 11 illustrate the local dma memory map of each subsystem. functional overview 21 december 1999 ? revised december 2001 sprs122d page 0 data memory page 1 program memory page 2 page 3 0000h 8000h ffffh page 0 mpda page 1 reserved ?? ?? : remapped areas mcbsp dxr/drr mmregs only 0020h 0060h mpda mpda mpda mpda mpda mpab0 mpab1 mda0 mda1 mpab0 mpab1 ?? ?? notes: a. mpda: local program/data memory in subsystem a b. mda: local data memory in subsystem a c. mpab: two-way shared program memory in subsystems a and b figure 3 ? 8. subsystem a local dma memory map page 0 data memory page 1 program memory page 2 page 3 0000h 8000h ffffh page 0 mpdb mdb0 page 1 mdb1 ? reserved ?? ?? ?? mcbsp dxr/drr mmregs only mpdb mpdb mpdb mpdb mpdb mpab2 mpab3 : remapped areas 0020h 0060h mpab2 mpab3 notes: a. mpdb: local program/data memory in subsystem b b. mdb: local data memory in subsystem b c. mpab: two-way shared program memory in subsystems a and b figure 3 ? 9. subsystem b local dma memory map functional overview 22 december 1999 ? revised december 2001 sprs122d page 0 data memory page 1 program memory mpcd0 mpcd1 page 2 page 3 0000h 8000h ffffh page 0 mpdc mdc0 page 1 mdc1 ?? ?? reserved ?? ?? ?? ?? mcbsp dxr/drr mmregs only : remapped areas mpdc mpdc mpdc mpdc mpdc mpcd0 mpcd1 0020h 0060h notes: a. mpdc: local program/data memory in subsystem c b. mdc: local data memory in subsystem c c. mpcd: two-way shared program memory in subsystems c and d figure 3 ? 10. subsystem c local dma memory map page 0 data memory page 1 page 2 page 3 0000h 8000h ffffh page 0 mpdd mdd0 page 1 mdd1 ?? reserved ?? ?? ? mcbsp dxr/drr mmregs only mpcd2 mpcd3 mpdd mpdd mpdd mpdd mpdd 0020h 0060h mpcd2 mpcd3 : remapped areas program memory notes: a. mpdd: local program/data memory in subsystem d b. mdd: local data memory in subsystem d c. mpcd: two-way shared program memory in subsystems c and d figure 3 ? 11. subsystem d local dma memory map functional overview 23 december 1999 ? revised december 2001 sprs122d 3.2.1.1 dma controller features the 5441 dma has the following features: ? the dma operates independently of the cpu. ? the dma has six channels. the dma can keep track of the contexts of six independent block transfers. ? the dma has higher priority than the cpu. ? each channel has independently programmable priority. ? each channel ? s source and destination address registers include configurable indexing modes. the address can be held constant, postincremented, postdecremented, or adjusted by a programmable value. ? each read or write transfer can be initialized by selected events. ? the dma supports single-word (16-bit) and double-word (32-bit) transfers. ? each dma channel has independent reload registers. ? each dma channel has independent extended source/destination data page registers. ? the dma does not support i/o memory access. a 16-bit dma transfer requires four cpu clock cycles to complete ? two cycles for reads and two cycles for writes. since the dma controller shares the dma bus with the hpi module, the dma access rate is reduced when the hpi is active. 3.2.1.2 dma reload registers each dma channel has its own reload registers which are utilized when autoinitialization is enabled for the current dma channel. the reload registers include: ? source address reload register (dmgsan) ? destination address reload register (dmgdan) ? element count reload register (dmgcrn) ? frame count reload register (dmgfrn) the ? n ? in the register names refers to dma channel number: 0, 1, 2, 3, 4, and 5. in the dmprec register, bit 14 (iauto) is used to enable individual reload register for each channel. if that bit is not set, the channel 0 reload register will be loaded to all chanels (this is backward compatible). 3.2.1.3 extended source/destination data page registers (dmsrcdpn/dmdstdpn) the dma controller has the ability to perform transfers to and from the extended data memory space. the dma extended source data page register and extended destination data page register service this purpose and only the least significant seven bits are used to designate the extended data memory page. each of the dma channels will have one set of these registers for extended data memory page (other than page 0) access. data memory space transfers cannot cross 64k page boundaries. if a data page boundary is crossed during a transfer, the next transfer will wrap on to the same page. for detailed information on dma registers, see tms320c54x dsp reference set, volume 5: enhanced peripherals (literature number spru302). 3.2.1.4 dma controller synchronization events the transfers associated with each dma channel can be synchronized to one of several events. the dsyn bit field of the dma channel x sync select and frame count (dmsfcx) register selects the synchronization event for a channel. the list of possible events and the dsyn values are shown in table 3 ? 1. functional overview 24 december 1999 ? revised december 2001 sprs122d table 3 ? 1. dma synchronization events dsyn value dma synchronization event 0000b no synchronization used 0001b mcbsp0 receive event 0010b mcbsp0 transmit event 0011b mcbsp2 receive event 0100b mcbsp2 transmit event 0101b mcbsp1 receive event 0110b mcbsp1 transmit event 0111b ? 1111b reserved 3.2.1.5 dma channel interrupt selection the dma controller can generate a cpu interrupt for each of the six channels. however, channels 0, 1, 2, and 3 are multiplexed with other interrupt sources. dma channels 0 and 1 share an interrupt line with the receive and transmit portions of mcbsp2 (imr/ifr bits 6 and 7), and dma channels 2 and 3 share an interrupt line with the receive and transmit portions of mcbsp1 (imr/ifr bits 10 and 11). when the 5441 is reset, the interrupts from these four dma channels are deselected. the intsel bit field in the dma channel priority and enable control (dmprec) register can be used to select these interrupts, as shown in table 3 ? 2. table 3 ? 2. dma channel interrupt selection intsel value imr/ifr[6] imr/ifr[7] imr/ifr[10] imr/ifr[11] 00b (reset) brint2 bxint2 brint1 bxint1 01b brint2 bxint2 dmac2 dmac3 10b dmac0 dmac1 dmac2 dmac3 11b reserved 3.2.2 16-bit bidirectional host-port interface (hpi16) 3.2.2.1 hpi16 memory map the hpi16 is an enhanced 16-bit version of the c54x ? dsp 8-bit host-port interface (hpi). the hpi16 is designed to allow a 16-bit host to access the dsp on-chip memory, with the host acting as the master of the interface. each hpi subsystem memory map is identical to its corresponding dma memory map except the hpi memory map does not support accesses to any memory-mapped registers. some of the features of the hpi16 include: ? a 16-bit bidirectional data bus ? multiple data strobes and control signals to allow glueless interfacing to a variety of hosts ? multiplexed and nonmultiplexed address/data modes ? a 19-bit address bus used in nonmultiplexed mode to allow access to all on-chip (including extended address pages) memory ? a 19-bit address register used in multiplexed mode. includes address autoincrement feature for faster accesses to sequential addresses ? interface to on-chip dma module to allow access to entire on-chip memory space ? hrdy signal to hold off host accesses due to dma latency ? control register available in multiplexed mode only. accessible by either host or dsp to provide host/dsp interrupts, extended addressing, and data prefetch capability ? hpi_sel1 and hpi_sel2 pins are used to make selection among the four subsystem hpi modules. ? both the hpi data bus and address bus have bus-holder features. the bus holders can be enabled/disabled by the cpus. functional overview 25 december 1999 ? revised december 2001 sprs122d 3.2.2.2 hpi multiplexed mode in multiplexed mode, hpi16 operation is very similar to that of the standard 8-bit hpi, which is available with other c54x ? dsp products. a host with a multiplexed address/data bus can access the hpi16 data register (hpid), address register (hpia), or control register (hpic) via the hd bidirectional data bus. the host initiates the access with the strobe signals (hds1 , hds2 , hcs ) and controls the type of access with the hcntl, hr/w , and has signals. the dsp can interrupt the host via the x_hint signal, and can stall host accesses via the hrdy signal. bit 20 of the hpia register is used to make selection between program (shared) memory and data (local) memory access. table 3 ? 3 shows the memory selection via ha[20]. table 3 ? 3. hpi local/shared memory selection ha[20] memory type 0 local (data) 1 shared (program) 3.2.2.3 host/dsp interrupts in multiplexed mode, the hpi16 offers the capability for the host and dsp to interrupt each other through the hpic register. for host-to-dsp interrupts, the host must write a ? 1 ? to the dspint bit of the hpic register. this generates an interrupt to the dsp. this interrupt can also be used to wake the dsp from any of the idle 1,2, or 3 states. note that the dspint bit is always read as ? 0 ? by both the host and dsp. the dsp cannot write to this bit (see figure 3 ? 12). for dsp-to-host interrupts, the dsp must write a ? 1 ? to the hint bit of the hpic register to interrupt the host via the x_hint pin. the host acknowledges and clears this interrupt by also writing a ? 1 ? to the hint bit of the hpic register. note that writing a ? 0 ? to the hint bit by either host or dsp has no effect. functional overview 26 december 1999 ? revised december 2001 sprs122d 3.2.2.4 hpi nonmultiplexed mode in nonmultiplexed mode, a host with separate address/data buses can access the hpi16 data register (hpid) via the 16-bit hd bidirectional data bus, and the address register (hpia) via the 19-bit ha address bus. the ha[18] signal is used to make selection between program (shared) memory and data (local) memory access. table 3 ? 4 shows the memory selection via ha[18]. table 3 ? 4. hpi local/shared memory selection ha[18] memory type 0 local (data) 1 shared (program) the host initiates the access with the strobe signals (hds1 , hds2 , and hcs ) and controls the direction of the access with the hr/w signal. the hpi16 can stall host accesses via the hrdy signal. note that the hpic register is not available in nonmultiplexed mode since there are no hcntl signals available. all host accesses initiate a dma read or write access. figure 3 ? 12 shows a block diagram of the hpi16 in nonmultiplexed mode. host hpi-16 data[15:0] hd[15:0] r/w hr/w data strobes hds1 , hds2 , hcs hrdy ready hpid[15:0] ?? ?? ?? ?? ?? ?? ?? ?? ?? dma c54x cpu internal memory address[ n :0] ? ha[ n :0] ? ? n = 0 to 18 figure 3 ? 12. interfacing to the hpi-16 in non-multiplexed mode functional overview 27 december 1999 ? revised december 2001 sprs122d 3.2.2.5 hpi bus holder control both the hpi data and address buses have bus holders. by default, the bus holders are disabled after global reset or subsystem a reset. the bus holders are configured via the bhd and bha bits in the bank switching control register (bscr) located at 29h in subsystem a. figure 3 ? 13 shows the bscr bit layout for subsystem a and table 3 ? 5 describes the bit functions of bscr. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved bhd bha reserved u r/w+0 r/w+0 u legend: r = read, w = write, u = undefined figure 3 ? 13. bscr register bit layout for subsystem a table 3 ? 5. bscr register bit functions for subsystem a bit no. bit name function 15 ? 3 reserved these bits are reserved and are read as 0. 2 bhd data bus holder. bhd is cleared to 0 at reset. bhd = 0: the hpi data bus holder is disabled. bhd = 1: the hpi data bus holder is enabled. 1 bha address bus holder. bha is cleared to 0 at reset. bha = 0: the hpi address bus holder is disabled. bha = 1: the hpi address bus holder is enabled. 0 reserved this bit is reserved and is read as 0. 3.2.2.6 other hpi16 system considerations ? operation during idle ? the hpi16 can continue to operate during idle1 or idle2 by using special clock management logic that turns on relevant clocks to perform a synchronous memory access, and then turns the clocks back off to save power. the dsp cpu does not wake up from the idle mode during this process. ? downloading code during reset ? the hpi16 can download code while the dsp is in reset. the system provides a pin (reset ) that provides a way to take the hpi16 module out of reset while leaving the dsp in reset. ? emulation considerations ? the hpi16 can continue operation even when the dsp cpu is halted due to debugger breakpoints or other emulation events. ? xa multiplexer ? xa multiplexer controls the hpi data traffic from each subsystem to the device boundary. the hpi module is the slave on the hpi bus. figure 3 ? 14 shows the 5441 block diagram with xa logic. the xa basic function includes: ? making the hpi bus available for the selected subsystem hpi module according to hpi selection pins hpi_sel1/hpi_sel2. ? granting hpi path to one of the subsystems at one time ? the hpi_sel1 and hpi_sel2 pins are used to select the hpi module among the four cores. the selection is indicated in table 3 ? 6. functional overview 28 december 1999 ? revised december 2001 sprs122d dsp subsystem a dsp id: 0000 dsp subsystem b dsp id: 0001 dsp subsystem c dsp id: 0011 dsp subsystem d dsp id: 0010 hpi bus hpi bus hpi bus hpi bus hpi_sel1 hpi_sel2 xa note: xa is the muxing logic for hpi access. figure 3 ? 14. xa multiplexer for hpi access table 3 ? 6. hpi module selection hpi_sel2 hpi_sel1 selected hpi module 0 0 subsystem a 0 1 subsystem b 1 0 subsystem c 1 1 subsystem d functional overview 29 december 1999 ? revised december 2001 sprs122d 3.2.3 multichannel buffered serial port (mcbsp) the 5441 device provides high-speed, full-duplex serial ports that allow direct interface to other c54x/lc54x devices, codecs, and other devices in a system. there are twelve multichannel buffered serial ports (mcbsps) on chip (three per subsystem). the mcbsp provides: ? full-duplex communication ? double-buffer data registers, which allow a continuous data stream ? independent framing and clocking for receive and transmit in addition, the mcbsp has the following capabilities: ? direct interface to: ? t1/e1 framers ? mvip switching-compatible and st-bus compliant devices ? iom-2 compliant device ? ac97-compliant device ? serial peripheral interface (spi) ? multichannel transmit and receive of up to 128 channels ? a wide selection of data sizes, including: 8, 12, 16, 20, 24, or 32 bits ? -law and a-law companding ? programmable polarity for both frame synchronization and data clocks ? programmable internal clock and frame generation 3.2.3.1 mcbsp clock source the 5441 mcbsps allow either the receive clock pin (bclkrn) or the transmit clock pin (bclkxn) to be configured as the input clock to the sample rate generator. this enhancement is enabled through two register bits: bit 7 [the enhanced sample clock mode bit (sclkme)] of the pin control register (pcr), and bit 13 [the mcbsp sample rate generator clock mode bit (clksm)] of the sample rate generator register 2 (srgr2). sclkme is an addition to the pcr contained in the mcbsps on previous tms320c5000 ? dsp platform devices. the new bit layout of the pcr is shown in figure 3 ? 15. for a description of the remaining bits, see tms320c54x dsp reference set, volume 5: enhanced peripherals (literature number spru302). 15 14 13 12 11 10 9 8 reserved xioen rioen fsxm fsrm clkxm clkrm r,+0 rw,+0 rw,+0 rw,+0 rw,+0 rw,+0 rw,+0 76543210 sclkme clks_stat dx_stat dr_stat fsxp fsrp clkxp clkrp rw,+0 r,+0 r,+0 r,+0 rw,+0 rw,+0 rw,+0 rw,+0 legend: r = read, w = write, +0 = value at reset figure 3 ? 15. pin control register (pcr) tms320c5000 is a trademark of texas instruments. functional overview 30 december 1999 ? revised december 2001 sprs122d the selection of the sample rate generator (srg) clock input source is made by the combination of the clksm and sclkme bit values as shown in table 3 ? 7. table 3 ? 7. sample rate generator clock source selection sclkme clksm srg clock source 0 0 reserved 0 1 cpu clock 1 0 bclkrn pin 1 1 bclkxn pin when either of the bidirectional pins, bclkrn or bclkxn, is configured as the clock input, its output buffer is automatically disabled. for example, with sclkme = 1 and clksm = 0, the bclkrn pin is configured as the srg input. in this case, both the transmitter and receiver circuits can be synchronized to the srg output by setting pcr[9:8] for clkxm = 1 and clkrm = 1. however, the srg output is only driven onto the bclkxn pin because the bclkr output is automatically disabled. 3.2.3.2 multichannel selection the mcbsp supports independent selection of multiple channels for the transmitter and receiver. when multiple channels are selected, each frame represents a time-division multiplexed (tdm) data stream. in using time-division multiplexed data streams, the cpu may only need to process a few of them. thus, to save memory and bus bandwidth, multichannel selection allows independent enabling of particular channels for transmission and reception. up to a maximum of 128 channels in a bit stream can be enabled or disabled. the 5441 mcbsps have two working modes that are selected by setting the rmcme and xmcme bits in the multichannel control registers mcr1x and mcr2x, respectively (see figure 3 ? 16 and figure 3 ? 17). for a description of the remaining bits, see tms320c54x dsp reference set, volume 5: enhanced peripherals (literature number spru302). ? in the first mode, when rmcme = 0 and xmcme = 0, there are two partitions (a and b), with each containing 16 channels as shown in figure 3 ? 16 and figure 3 ? 17. this is compatible with the mcbsps used in the 5420, where only 32-channel selection is enabled (default). 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved xmc me xpbblk xpablk xcblk xmcm r,+0 rw,+0 rw,+0 rw,+0 r,+0 rw,+0 legend: r = read, w = write, +0 = value at reset; x = mcbsp 0,1, or 2 figure 3 ? 16. multichannel control register 2 for mcbspx (mcr2x) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved rmc me rpbblk rpablk rcblk rmcm r,+0 rw,+0 rw,+0 rw,+0 r,+0 rw,+0 legend: r = read, w = write, +0 = value at reset; x = mcbsp 0,1, or 2 figure 3 ? 17. multichannel control register 1 for mcbspx (mcr1x) functional overview 31 december 1999 ? revised december 2001 sprs122d ? in the second mode, with rmcme = 1 and xmcme = 1, the mcbsps have 128-channel selection capability. twelve registers (rcercx ? rcerhx and xcercx ? xcerhx) are used to enable the 128-channel selection. the subaddresses of the registers are shown in table 3 ? 24. these registers, functionally equivalent to the rcera0 ? rcerb1 and xcera0 ? xcerb1 registers, are used to enable/disable the transmit and receive of additional channel partitions (c,d,e,f,g, and h) in the 128-channel stream. for example, xcerh1 is the transmit enable for channel partition h (channels 112 to 127) of mcbsp1 for each dsp subsystem. see figure 3 ? 18, table 3 ? 8, figure 3 ? 19, and table 3 ? 9 for bit layouts and functions of the receive and transmit registers. 15 14 13 12 11 10 9 8 rceryz15 rceryz14 rceryz13 rceryz12 rceryz11 rceryz10 rceryz9 rceryz8 rw,+0 rw,+0 rw,+0 rw,+0 rw,+0 rw,+0 rw,+0 rw,+0 76543210 rceryz7 rceryz6 rceryz5 rcery4 rceryz3 rceryz2 rceryz1 rceryz0 rw,+0 rw,+0 rw,+0 rw,+0 rw,+0 rw,+0 rw,+0 rw,+0 legend: r = read, w = write, +0 = value at reset; y = partition a,b,c,d,e,f,g, or h; z = mcbsp 0,1, or 2 figure 3 ? 18. receive channel enable registers bit layout for partitions a to h table 3 ? 8. receive channel enable registers for partitions a to h bit name function 15 ? 0 rceryz[15:0] receive channel enable register rceryz n =0 disables reception of n th channel in partition y. rceryz n =1 enables reception of n th channel in partition y. note: y = partition a,b,c,d,e,f,g, or h; z = mcbsp 0,1, or 2; n = bit 15 ? 0 15 14 13 12 11 10 9 8 xceryz15 xceryz14 xceryz13 xceryz12 xceryz11 xceryz10 xceryz9 xceryz8 rw,+0 rw,+0 rw,+0 rw,+0 rw,+0 rw,+0 rw,+0 rw,+0 76543210 xceryz7 xceryz6 xceryz5 xcery4 xceryz3 xceryz2 xceryz1 xceryz0 rw,+0 rw,+0 rw,+0 rw,+0 rw,+0 rw,+0 rw,+0 rw,+0 legend: r = read, w = write, +0 = value at reset; y = partition a,b,c,d,e,f,g, or h; z = mcbsp 0,1, or 2 figure 3 ? 19. transmit channel enable registers bit layout for partitions a to h table 3 ? 9. transmit channel enable registers for partitions a to h bit name function 15 ? 0 xceryz[15:0] transmit channel enable register xceryz n =0 disables transmit of n th channel in partition y. xceryz n =1 enables transmit of n th channel in partition y. legend: y = partition a,b,c,d,e,f,g, or h; z = mcbsp 0,1, or 2; n = bit 15 ? 0 functional overview 32 december 1999 ? revised december 2001 sprs122d the mcbsp is fully static and operates at arbitrarily low clock frequencies. for the maximum mcbsp multichannel operating frequency, see section 5.10 of this data manual. 3.2.3.3 mcbsp1 and mcbsp2 the four mcbsp1s from each subsystem share the same external signal pins. the four mcbsp2s from each subsystem share the same set of external signal pins. they can only operate in either of the following modes: ? multichannel mode (x_bclkr, x_bclkx, x_bfsr, and x_bfsx are external and the mcbsps share tdm stream with no single time slot assigned to more than one mcbsp) ? standard serial port mode (x_bclkr, x_bclkx, x_bfsr, and x_bfsx are external and only one mcbsp is enabled at one time). for mcbsp1 and mcbsp2, no other mode is supported. 3.2.3.4 sa multiplexer the sa1 and sa2 multiplexers provide multiplexing for the four mcbsp1s and the four mcbsp2s from each subsystem and present the data path to the device boundary. all the same functional pins from the four mcbsp1s are multiplexed together by sa1 and connect to the device external pins. all the same functional pins from the four mcbsp2s are multiplexed together by sa2 and connect to the device external pins. the functional pins are: data receive (bdrn), data transmit (bdxn), receive frame sync (bfsrn), transmit frame sync (bfsxn), receive shift clock (bclkrn), and transmit shift clock (bclkxn). when mcbsp operates in multichannel mode, software shall ensure that the same channel (time slot) not be assigned by more than one subsystem. if more than one subsystem enables the same transmit time slot, the results are undefined. figure 3 ? 20 shows 5441 block diagram with sa1 logic; sa2 logic is identical. dsp subsystem a dsp id: 0000 mcbsp1 mcbsp1 dsp id: 0001 dsp subsystem b mcbsp1 dsp id: 0010 dsp subsystem c mcbsp1 dsp subsystem d dsp id: 0011 sa1 bclkr1 bclkx1 bfsr1 bfsx1 bdr1 bdx1 note: sa is the mux/arbitration logic for mcbsp1 operation. figure 3 ? 20. sa multiplexer for mcbsp1 operation functional overview 33 december 1999 ? revised december 2001 sprs122d 3.2.4 hardware timer each 5441 subsystem has one independent software programmable timer. the memory-mapped registers control the operation of the timer. the timer resolution is the clock rate of the cpu. the timer output shares the pin with gpio3 and is controlled by gpio register bit 15. the timer supports a 32-bit dynamic range. the timer consists of a programmable 16-bit main counter and a programmable prescalar. the main counter is driven by the prescalar, which decrements by one at every cpu clock. once the prescalar reaches zero, the 16-bit counter decrements by one. when the 16-bit counter decrements to zero, a maskable interrupt (tint) is generated and the timer output pin (tout) asserts an active-high pulse (2h ? 2 ns, h=0.5 clock cycle). the timer output pulse is driven on gpio3 when the tout bit is set to high in the gpio register. when the timer is configured in continuous mode, the timer counter and prescalar will be reloaded accordingly after the timer counter exhausts. the timer can be stopped, restarted, reset, or disabled via the bits of the timer control register. there are four 16-bit registers associated with the timer. ? timer counter register (tim) ? timer period register (prd) ? timer control register (tcr) ? timer second control register (tscr) 3.2.4.1 tim register this register is loaded with the period register (prd) value and decrements once the prd value is loaded. 3.2.4.2 prd register this register is used to reload the timer counter register (tim). 3.2.4.3 tcr register this register provides the control and status information. tcr bit fields are shown in figure 3 ? 21 and described in table 3 ? 10. 151413121110987 6 5 43210 reserved soft free psc trb tss tddr r/w+0 r/w+0 r/w+0 r/w+0 r/w+0 r/w+0 legend: r = read, w = write, +0 = value at reset figure 3 ? 21. timer control register (tcr) functional overview 34 december 1999 ? revised december 2001 sprs122d table 3 ? 10. tcr bit description bit no. bit name function 15 ? 12 reserved register bit is reserved. read 0, write has no effect. 11 soft used in conjunction with the free bit to determine the state of the timer when a breakpoint is encountered in the hll debugger. when free = 0 and soft = 0 the timer stops immediately. when free = 0 and soft = 1, the timer stops when the counter decrements to 0. 10 free used in conjunction with the soft bit to determine the state of the timer when a breakpoint is encountered in the hll debugger. when free = 0, the soft bit selects the timer mode. when free = 1, the timer runs free regardless of the soft bit. 9 ? 6 psc timer prescalar counter, used only when premd = 0 (in tscr register) and the prescaler is in direct mode. 5 trb timer reload. when trb is set, tim is loaded with the value in the prd register and the psc field is loaded with the value in the tddr field (when prescalar is in direct mode). trb is always read a 0. 4 tss timer stop status. stops or starts the timer at reset. tss is cleared and the timer starts timing. 0 = timer is started 1 = timer is stopped 3 ? 0 tddr timer prescalar. case 1: when premd = 0, tddr is a 4-bit reload prescalar. when psc decrements to 0, psc is loaded with the contents of tddr. case 2: when premd = 1,tddr is an indirect prescalar, the contents in tddr is used to specify the timer prescalar. tddr[3:0] prescalar 0000 0001h 0001 0003h 0010 0007h 0011 000fh 0100 001fh 0101 003fh 0110 007fh 0111 00ffh 1000 01ffh 1001 03ffh 1010 07ffh 1011 0fffh 1100 1fffh 1101 3fffh 1110 7fffh 1111 ffffh functional overview 35 december 1999 ? revised december 2001 sprs122d 3.2.4.4 tscr register this 16-bit register contains bits to set prescalar mode. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved premd reserved r/w+0 legend: r = read, w = write, +0 = value at reset figure 3 ? 22. timer second control register (tscr) table 3 ? 11. tscr bit description bit no. bit name function 15 ? 13 reserved register bit is reserved. read 0, write has no effect. 12 premd prescalar mode select bit. 0 = direct mode, tddr is a 4-bit reload prescalar (default value after reset). 1 = indirect mode, tddr is used to select individual prescalar value. 11 ? 0 reserved register bit is reserved. read 0, write has no effect. out of reset, the tim and prd registers are set to a maximum value of ffffh, the premd bit (tscr[12]) is set to 0, the tddr field (tcr[3:0]) is cleared to 0, and the timer is started. 3.2.5 watchdog timer each subsystem contains a watchdog timer. the purpose of the watchdog timer is to prevent the system from lock in case the software becomes trapped in loops with no controlled exit. the watchdog timer has a ? watchdog output ? pin associated with it. this watchdog output pin is shared with the x_gpio2/x_wtout pin; once the watchdog timer is enabled, this pin is automatically configured as x_wtout . the watchdog timer requires a special service sequence to be executed periodically. without this periodic servicing, the watchdog timer counter reaches zero and times out. consequently, an active-low pulse will be asserted on the ? watchdog output ? pin and an internal maskable interrupt will be triggered. the watchdog output (x_wtout ) pin can be gluelessly external-connected to the local hardware reset or nmi (nonmaskable interrupt). this allows maximum flexibility in utilizing the watchdog as required by the particular application. the watchdog timer is a prescaled 16-bit counter that supports up to a 32-bit dynamic range. out of reset, the watchdog is disabled in order to allow as much time as needed for code to be loaded into the 5441 on-chip memory via the hpi. prior to being enabled, the watchdog counter will, in fact, still count down from its initial default value using the default prescalar value. when the counter reaches zero, a watchdog time-out event will occur in that a wd interrupt (wdtint) request will be sent to the core, and the wdflag will be set. however, since all maskable interrupts are disabled by default at reset, the wdtint will not be serviced by the core. additionally, the watchdog pin (x_wtout ) is disconnected from the watchdog time-out event, so no pulse will be generated on this pin. after this time-out, the counter and prescalar will be reloaded automatically and the watchdog will continue to count, time out, reload, etc. after code-download, the watchdog can be enabled to connect the x_wtout pin to the time-out event. to enable the watchdog, certain sequence shall be followed as shown in figure 3 ? 25. once the watchdog is enabled, it cannot be disabled by software. it can be disabled by watchdog time-out, local hardware reset, or global hardware reset. a special key sequence is provided to prevent the watchdog from being accidentally serviced while the software is trapped in a dead loop or in some other software failures. functional overview 36 december 1999 ? revised december 2001 sprs122d 3.2.5.1 watchdog timer registers there are four 16-bit registers associated with the watchdog timer. ? wd timer counter register (wdtim) ? wd timer period register (wdprd) ? wd timer control register (wdtcr) ? wd timer second control register (wdtscr) 3.2.5.2 wdtim register this register contains the 16-bit watchdog counter value. it is decremented once every watchdog clock cycle. 3.2.5.3 wdprd register this register is used to reload the wd timer counter register (wdtim). 3.2.5.4 wdtcr register this register provides the control and status information. wdtcr bit fields are as shown in figure 3 ? 23 and are described in table 3 ? 12. 151413121110987 6 5 43210 reserved soft free psc reserved tddr r/w+0 r/w+0 r r/w+1111 legend: r = read, w = write, +0 = value at reset figure 3 ? 23. watchdog timer control register (wdtcr) functional overview 37 december 1999 ? revised december 2001 sprs122d table 3 ? 12. wdtcr bit description bit no. bit name function 15 ? 12 reserved register bit is reserved. read 0, write has no effect. 11 soft used in conjunction with the free bit to determine the state of the timer when a breakpoint is encountered in the hll debugger. when free = 0 and soft = 0 the timer stops immediately. when free = 0 and soft = 1, the timer stops when the counter decrements to 0. 10 free used in conjunction with the soft bit to determine the state of the timer when a breakpoint is encountered in the hll debugger. when free = 0, the soft bit selects the timer mode. when free = 1, the timer runs free regardless of the soft bit. 9 ? 6 psc timer prescalar counter, used only when premd = 0 (in wdtscr register) and the prescaler is in direct mode. 5 ? 4 reserved register bit is reserved. read 0, write has no effect. 3 ? 0 tddr timer prescalar. case 1: when premd = 0, tddr is a 4-bit reload prescalar. when psc decrements to 0, psc is loaded with the contents of tddr. case 2: when premd = 1,tddr is an indirect prescalar, the contents in tddr is used to specify the timer prescalar. tddr[3:0] prescalar 0000 0001h 0001 0003h 0010 0007h 0011 000fh 0100 001fh 0101 003fh 0110 007fh 0111 00ffh 1000 01ffh 1001 03ffh 1010 07ffh 1011 0fffh 1100 1fffh 1101 3fffh 1110 7fffh 1111 ffffh (default) 3.2.5.5 wdtscr register this 16-bit register contains bits to indicate watchdog flag, to enable watchdog, to set prescalar mode as well as to provide the 12-bit wdkey for watchdog service. wdtscr bit fields are shown in figure 3 ? 24 and are described in table 3 ? 13. functional overview 38 december 1999 ? revised december 2001 sprs122d 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wdflag wden reserved premd wdkey r/w+0 r/w+0 r/w+1 r/w+0 legend: r = read, w = write, +0 = value at reset figure 3 ? 24. watchdog timer second control register (wdtscr) table 3 ? 13. wdtscr bit description bit no. bit name function 15 wdflag watchdog flag bit. this bit can be cleared by enabling the watchdog timer, by device global reset, and by being written with ? 1 ? . it is set by a watchdog time-out. 0 = no watchdog time-out occurred 1 = watchdog time-out occurred 14 wden watchdog timer enable bit. 0 = watchdog disable. default value after device reset. watchdog output pin is disconnected to the watchdog time-out event, counter starts to run. 1 = watchdog enable. once enabled, the watchdog output pin is connected to the watchdog time-out event, and can be disabled by watchdog time-out or reset. 13 reserved register bit is reserved. read 0, write has no effect. 12 premd prescalar mode select bit. 0 = direct mode, tddr is 4-bit reload prescalar. 1 = indirect mode, tddr is used to select individual prescalar value (default value after local or global hardware reset). 11 ? 0 wdkey 12-bit watchdog reset key, only the sequence of a 5c6h followed by an a7eh services the watchdog. the watchdog has to be serviced periodically with the sequence of 5c6h followed by a7eh, written to wdkey before the watchdog timer times out. both 5c6h and a7eh are allowed to be written to wdkey. only the sequence of 5c6h followed by a7eh, to wdkey services the watchdog. any other writes to wdkey will trigger the watchdog time-out immediately, and consequently: ? the watchdog output pin will generate an active-low pulse (6h ns, h=0.5 clock cycle) ? the wdflag bit in wdtscr will be set to 1 ? the internal maskable wd interrupt (wd_tint) will be triggered read from wdtscr register will not cause time-out. when the watchdog is in time-out state, the watchdog is disabled and wden is cleared. the watchdog output pin (x_wtout ) is disconnected to the watchdog time-out event. finally, the timer is reloaded and continues to run. out of reset, the watchdog is disabled, and reads and writes to the watchdog registers are allowed. once 5c6h is written to wdkey in the wdtscr register from the initial state, the watchdog enters the preactive state. the next write to the wdtscr register should be completed with a ? 1 ? written to wden and a7eh written to wdkey. this causes the watchdog timer to enter the active state. once the watchdog is enabled, it cannot be disabled by software. any writes to the wdtscr register from the active or service states that do not write 5c6h or a7eh to wdkey will result in an immediate watchdog time-out. writing the sequence of 5c6h and a7eh to wdkey causes the watchdog timer to transition between the active and service states. the transition from the service state to the active state results in the timer register reload that is necessary to keep the watchdog timer from timing out. each time the watchdog is serviced by the sequence, the watchdog timer counter and prescalar will automatically be reloaded. functional overview 39 december 1999 ? revised december 2001 sprs122d the registers wdtim, wdprd, wdtcr, and the premd bit in wdtscr must be configured before the watchdog enters the active state. by default, wdtim =ffffh, wdprd = ffffh, premd = 1, tddr = 1111b. writing a ? 1 ? to wden and configuring the premd bit must be done at the same time that a7eh is written to wdkey in watchdog pre-active state. 3.2.5.6 watchdog state diagram figure 3 ? 25 shows the watchdog operation state diagram. initial state (watchdog disabled) (wdtim=ffffh) (wdprd=ffffh) (tddr=1111b) (premd=1) power up/ reset (hardware) not 5c6h to wdkey 5c6h to wdkey pre-active state 5c6h to wdkey a7eh to wdkey a7eh to wdkey with ? 1 ? to wden (reload timer, clear wdflag, enable output pin) active state (waiting for 5c6h) not a7eh or 5c6h to wdkey not 5c6h or a7eh to wdkey output pin asserted wdflag set wd int triggered timeout! output pin asserted wdflag set wd int triggered timeout state (watchdog disabled) (output pin disconnected) 5c6h to wdkey a7eh to wdkey (register reload) service state (waiting for a7eh) 5c6h to wdkey timeout! wdflag set wd int triggered output pin asserted wd int triggered to wdkey output pin asserted wdflag set not a7eh or 5c6h figure 3 ? 25. watchdog operation state diagram as shown in figure 3 ? 25, the watchdog is disabled before it enters the active state. even though disabled, the wd interrupt (wd_tint) may be triggered periodically although the watchdog output pin (x_wtout ) will not be asserted. the interrupt may be utilized to: ? indicate that watchdog is not in active state ? allow the watchdog timer to act as a general-purpose time counter if the watchdog functionality is not needed. 3.2.5.7 watchdog register write protection once the watchdog is enabled, writes to registers wdtim, wdprd, and wdtcr will have no effect. writes to the wdflag, wden, and premd bits in register wdtscr will have no effect. however, writing an incorrect key (not 5c6h or a7eh) to wdkey will result in an immediate time-out. functional overview 40 december 1999 ? revised december 2001 sprs122d 3.2.6 software-programmable phase-locked loop (pll) the clock generator provides clocks to the 5441 device, and consists of a phase-locked loop (pll) circuit. the clock generator requires a reference clock input, which must be provided by using an external clock source. the reference clock input is then divided by two (div mode) to generate clocks for the 5441 device. alternately, the pll circuit can be used (pll mode) to generate the device clock by multiplying the reference clock frequency by a scale factor, allowing use of a clock source with a lower frequency than that of the cpu. the pll is an adaptive circuit that, once synchronized, locks onto and tracks an input clock signal. when the pll is initially started, it enters a transitional mode during which the pll acquires lock with the input signal. once the pll is locked, it continues to track and maintain synchronization with the input signal. then, other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the 5441 device. only subsystem a controls the pll. subsystems b, c, and d cannot access the pll registers. the software-programmable pll features a high level of flexibility, and includes a clock scaler that provides various clock multiplier ratios, capability to directly enable and disable the pll, and a pll lock timer that can be used to delay switching to pll clocking mode of the device until lock is achieved. devices that have a built-in software-programmable pll can be configured in one of two clock modes: ? pll mode. the input clock (clkin) is multiplied by 1 of 31 possible ratios. these ratios are achieved using the pll circuitry. ? div (divider) mode. the input clock is divided by 2 or 4. note that when div mode is used, the pll can be completely disabled in order to minimize power dissipation. the software-programmable pll is controlled using the 16-bit memory-mapped (address 0058h) clock mode register (clkmd). the clkmd register is used to define the clock configuration of the pll clock module. figure 3 ? 26 shows the bit layout of the clock mode register and table 3 ? 14 describes the bit functions. 15 12 11 10 3 2 1 0 pllmul ? plldiv ? pllcount ? pllon/off ? pllndiv status r/w r/w r/w r/w r/w r/w ? when in div mode (pllstatus is low), pllmul, plldiv, pllcount, and pllon/off are don ? t cares, and their contents are indeterminate. legend: r = read, w = write figure 3 ? 26. clock mode register (clkmd) functional overview 41 december 1999 ? revised december 2001 sprs122d table 3 ? 14. clock mode register (clkmd) bit functions bit no. bit name function 15 ? 12 pllmul ? pll multiplier. pllmul defines the frequency multiplier in conjunction with plldiv and pllndiv. see table 3 ? 15. pll divider. plldiv defines the frequency multiplier in conjunction with pllmul and pllndiv. see t able 3 ? 15. 11 plldiv ? plldiv = 0 means that an integer multiply factor is used 11 plldiv plldiv = 1 means that a noninteger multiply factor is used 10 ? 3 pllcount ? pll counter value. pllcount specifies the number of input clock cycles (in increments of16 cycles) for the pll lock timer to count before the pll begins clocking the processor after the pll is started. the pll counter is a down-counter, which is driven by the input clock divided by 16; therefore, for every 16 input clocks, the pll counter decrements by one. the pll counter can be used to ensure that the processor is not clocked until the pll is locked, so that only valid clock signals are sent to the device. 2 pllon/off ? pll on/off. pllon/off enables or disables the pll part of the clock generator in conjunction with the pllndiv bit (see table 3 ? 16). note that pllon/off and pllndiv can both force the pll to run; when pllon/off is high, the pll runs independently of the state of pllndiv. 1 pllndiv pllndiv configures pll mode when high or div mode when low. pllndiv defines the frequency multiplier in conjunction with plldiv and pllmul. see table 3 ? 15. indicates the pll mode. 0 status status = 0 indicates div mode 0 status status = 1 indicates pll mode ? when in div mode (pllstatus is low), pllmul, plldiv, pllcount, and pllon/off are don ? t cares, and their contents are indeterminate. table 3 ? 15. multiplier related to pllndiv, plldiv, and pllmul pllndiv plldiv pllmul multiplier ? 0 x 0 ? 14 0.5 0 x 15 0.25 1 0 0 ? 14 pllmul + 1 1 0 15 bypass (multiply by 1) 1 1 0 or even (pllmul + 1)/2 1 1 odd pllmul/4 ? clkout = clkin * multiplier table 3 ? 16. vco truth table pllon/off pllndiv vco state 0 0 off 1 0 on 0 1 on 1 1 on 3.2.6.1 pll clock programmable timer during the lockup period, the pll should not be used to clock the 5441. the pllcount programmable lock timer provides a convenient method of automatically delaying clocking of the device by the pll until lock is achieved. the pll lock timer is a counter, loaded from the pllcount field in the clkmd register, that decrements from its preset value to 0. the timer can be preset to any value from 0 to 255, and its input clock is clkin divided by 16. the resulting lockup delay can therefore be set from 0 to 255 16 clkin cycles. functional overview 42 december 1999 ? revised december 2001 sprs122d the lock timer is activated when the operating mode of the clock generator is switched from div to pll. during the lockup period, the clock generator continues to operate in div mode; after the pll lock timer decrements to zero, the pll begins clocking the 5441. accordingly, the value loaded into pllcount is chosen based on the following formula: pllcount lockup time 16 t clkin where t clkin is the input reference clock period and lockup time is the required vco lockup time, as shown in table 3 ? 17. table 3 ? 17. vco lockup time clkout frequency (mhz) lockup time ( s) ? 5 23 10 17 20 16 40 19 60 24 80 29 100 35 135 45 ? approximate values 3.2.6.2 clkmd register initialization at reset the clock mode pin (clkmd) is used to initialize the pll to a known value at reset. the clkmd pin is sampled when the reset signal is low. only global reset (reset ) will reset the pll. subsystem a local reset (a_rs ) has no effect on the pll. table 3 ? 18. pll initialization at reset clkmd pin pll mode 0 bypass 1 clkinx2 3.2.7 general-purpose i/o the 5441 has 16 general-purpose i/o pins. these pins are: a_gpio0, a_gpio1, a_gpio2, a_gpio3 b_gpio0, b_gpio1, b_gpio2, b_gpio3 c_gpio0, c_gpio1, c_gpio2, c_gpio3 d_gpio0, d_gpio1, d_gpio2, d_gpio3 four bits of general-purpose i/o are available to each core. each gpio pin can be individually selected as either an input or an output through the gpio register. the x_xf, x_bio , and timer output are selectable on gpio pins 0, 1, and 3 through the gpio register also. each output driver has an independent three-state control. all nonreserved gpio register bits are readable and writeable. the gpio register bits will be set to 0 when the core is in reset, which will configure all gpio as inputs. gpio data and control bits are accessible through a memory-mapped register at 3ch with the format shown in figure 3 ? 27 and the bit functions described in table 3 ? 19. functional overview 43 december 1999 ? revised december 2001 sprs122d 151413121110987 6 5 43210 tout rsvd x_bio x_xf gpio dir3 gpio dir2 gpio dir1 gpio dir0 clk out1 clk out0 reserved gpio dat3 gpio dat2 gpio dat1 gpio dat0 r/w+0 r/w+0 r/w+0 r/w+0 r/w+0 r/w+0 r/w+0 r/w+0 r/w+0 r/w+0 r/w+0 r/w+0 r/w+0 legend: r = read, w = write, +0 = value at reset figure 3 ? 27. general-purpose i/o control register table 3 ? 19. general-purpose i/o control register bit functions bit no. bit name bit value function 0 timer output disable. uses gpio3 as general-purpose i/o. 15 tout 1 timer output enable. overrides dir3. timer output is driven on gpio3 and readable in dat3. 14 reserved x register bit is reserved. read 0, write has no effect. 0 branch control input disable. uses gpio1 as general-purpose i/o. 13 x_bio 1 branch control input enable. overrides dir1. the x_bio output is driven on gpio1 and readable in dat0. 0 external flag output disable. uses gpio0 as general-purpose i/o. 12 x_xf 1 external flag output enable. overrides dir0. the x_xf output is driven on gpio0 and readable in dat1. gpio 0 gpion pin is used as an input. 11 ? 8 gpio dirn ? 1 gpion pin is used as an output. 7 ? 6 clkout clkout muxing selection bits. clkout1[7] clkout0[6] a_clkout 0 0 (default) b_clkout 0 1 c_clkout 1 0 d_clkout 1 1 5 ? 4 reserved x register bit is reserved. read 0, write has no effect. gpio 0 gpion is driven with a 0 (dirn = 1). gpion is read as 0 (dirn = 0). 3 ? 0 gpio datn ? 1 gpion is driven with a 1 (dirn = 1). gpion is read as 1 (dirn = 0). ? n = 3, 2, 1, or 0 the timer output (tout) bit is used to multiplex the output of the timer and gpio3. the x_xf bit is used to multiplex the output of the external flag, and the x_bio bit is used to multiplex the input of the branch control. the watchdog enable (wden) bit in the watchdog timer second control register (wdtscr) is used to multiplex the watchdog timer output and gpio2. all gpio pins are programmable as an input or output by the direction bit (gpiodirn). data is either driven or read from the data bit field (gpiodatn). gpiodir3 has no effect when tout = 1. functional overview 44 december 1999 ? revised december 2001 sprs122d 3.2.8 chip subsystem id register the chip subsystem id register (csidr) is a read-only memory-mapped register located at 3eh within each dsp subsystem. this register contains two elements for electrically readable device identification. the chip id bits identify the type of c54x ? device (41h for 5441). the subsysid contains a unique subsystem identifier. figure 3 ? 28 shows the csidr and table 3 ? 20 describes its bit functions. 151413121110987 6 5 43210 chip id reserved subsysid r r legend: r = read figure 3 ? 28. chip subsystem id register (csidr) table 3 ? 20. chip subsystem id register bit functions bit no. bit field name function 15 ? 8 chip id 54x device type. contains 41h for 5441. 7 ? 4 reserved 3 ? 0 subsysid identifier for dsp subsystem: a = 00b, b = 01b, c = 10b, and d = 11b 3.2.9 data memory map register to access the extended data memory, the dsp cpu need to configure the data memory map register (dmmr), which is used to point to extended data memory. the content of dmmr register is used to select the extended data for all cpu data memory accesses. figure 3 ? 29 shows the dmmr and table 3 ? 21 describes its bit functions. 151413121110987 6 5 4321 0 reserved extended data r/w+0 legend: r = read, w = write figure 3 ? 29. data memory map register (dmmr) table 3 ? 21. data memory map register functions bit no. bit field name function 15 ? 1 reserved extended data memory for cpu access: 0 extended data extended_data = 0b, daram2 and daram3 are mapped in. extended_data = 1b, daram4 and daram5 are mapped in. functional overview 45 december 1999 ? revised december 2001 sprs122d 3.3 memory-mapped registers the 5441 has 27 processor memory-mapped registers, which are mapped in data memory space addresses 0h to 1fh as shown in table 3 ? 22. each device also has a set of memory-mapped registers associated with the peripherals as shown in table 3 ? 23. table 3 ? 22. processor memory-mapped registers for each dsp subsystem address name dec hex description imr 0 0 interrupt mask register ifr 1 1 interrupt flag register ? 2 ? 5 2 ? 5 reserved for testing st0 6 6 status register 0 st1 7 7 status register 1 al 8 8 accumulator a low word (15 ? 0) ah 9 9 accumulator a high word (31 ? 16) ag 10 a accumulator a guard bits (39 ? 32) bl 11 b accumulator b low word (15 ? 0) bh 12 c accumulator b high word (31 ? 16) bg 13 d accumulator b guard bits (39 ? 32) treg 14 e temporary register trn 15 f transition register ar0 16 10 auxiliary register 0 ar1 17 11 auxiliary register 1 ar2 18 12 auxiliary register 2 ar3 19 13 auxiliary register 3 ar4 20 14 auxiliary register 4 ar5 21 15 auxiliary register 5 ar6 22 16 auxiliary register 6 ar7 23 17 auxiliary register 7 sp 24 18 stack pointer bk 25 19 circular buffer size register brc 26 1a block-repeat counter rsa 27 1b block-repeat start address rea 28 1c block-repeat end address pmst 29 1d processor mode status register xpc 30 1e extended program counter ? 31 1f reserved functional overview 46 december 1999 ? revised december 2001 sprs122d table 3 ? 23. peripheral memory-mapped registers for each dsp subsystem name address (hex) description drr20 20 mcbsp 0 data receive register 2 drr10 21 mcbsp 0 data receive register 1 dxr20 22 mcbsp 0 data transmit register 2 dxr10 23 mcbsp 0 data transmit register 1 tim 24 timer register prd 25 timer period register tcr 26 timer control register tscr 27 timer second control register ? 28 reserved bscr 29 bank-switching control register ? 2a ? 2b reserved hpic 2c hpi control register (hmode=0 only) ? 2d ? 2f reserved drr22 30 mcbsp 2 data receive register 2 drr12 31 mcbsp 2 data receive register 1 dxr22 32 mcbsp 2 data transmit register 2 dxr12 33 mcbsp 2 data transmit register 1 spsa2 34 mcbsp 2 subbank address register ? spsd2 35 mcbsp 2 subbank data register ? ? 36 ? 37 reserved spsa0 38 mcbsp 0 subbank address register ? spsd0 39 mcbsp 0 subbank data register ? ? 3a ? 3b reserved gpio 3c general-purpose i/o register ? 3d reserved csidr 3e chip subsystem id register ? 3f reserved drr21 40 mcbsp 1 data receive register 2 drr11 41 mcbsp 1 data receive register 1 dxr21 42 mcbsp 1 data transmit register 2 dxr11 43 mcbsp 1 data transmit register 1 ? 44 ? 47 reserved spsa1 48 mcbsp 1 subbank address register ? spsd1 49 mcbsp 1 subbank data register ? ? 4a ? 4b reserved tim 4c watchdog timer register prd 4d watchdog timer period register tcr 4e watchdog timer control register wdtscr 4f watchdog timer second control register dmmr 50 data memory map register ? 51 ? 53 reserved dmprec 54 dma priority and enable control register dmsa 55 dma subbank address register ? dmsdi 56 dma subbank data register with autoincrement ? ? see table 3 ? 24 for a detailed description of the mcbsp control registers and their subaddresses. ? see table 3 ? 25 for a detailed description of the dma subbank addressed registers. functional overview 47 december 1999 ? revised december 2001 sprs122d table 3 ? 23. peripheral memory-mapped registers for each dsp subsystem (continued) name description address (hex) dmsdn 57 dma subbank data register ? clkmd 58 clock mode register (clkmd), subsystem a only (reserved in subsystems b, c, and d) ? 59 ? 5f reserved ? see table 3 ? 24 for a detailed description of the mcbsp control registers and their subaddresses. ? see table 3 ? 25 for a detailed description of the dma subbank addressed registers. 3.4 mcbsp control registers and subaddresses the control registers for the multichannel buffered serial port (mcbsp) are accessed using the subbank addressing scheme. this allows a set or subbank of registers to be accessed through a single memory location. the mcbsp subbank address register (spsax) is used as a pointer to select a particular register within the subbank. the mcbsp data register (spsdx) is used to access (read or write) the selected register. table 3 ? 24 shows the mcbsp control registers and their corresponding subaddresses. table 3 ? 24. mcbsp control registers and subaddresses mcbsp0 mcbsp1 mcbsp2 sub- name address name address name address sub- address description spcr10 39h spcr11 49h spcr12 35h 00h serial port control register 1 spcr20 39h spcr21 49h spcr22 35h 01h serial port control register 2 rcr10 39h rcr11 49h rcr12 35h 02h receive control register 1 rcr20 39h rcr21 49h rcr22 35h 03h receive control register 2 xcr10 39h xcr11 49h xcr12 35h 04h transmit control register 1 xcr20 39h xcr21 49h xcr22 35h 05h transmit control register 2 srgr10 39h srgr11 49h srgr12 35h 06h sample rate generator register 1 srgr20 39h srgr21 49h srgr22 35h 07h sample rate generator register 2 mcr10 39h mcr11 49h mcr12 35h 08h multichannel register 1 mcr20 39h mcr21 49h mcr22 35h 09h multichannel register 2 rcera0 39h rcera1 49h rcera2 35h 0ah receive channel enable register partition a rcerb0 39h rcerb1 49h rcerb2 35h 0bh receive channel enable register partition b xcera0 39h xcera1 49h xcera2 35h 0ch transmit channel enable register partition a xcerb0 39h xcerb1 49h xcerb2 35h 0dh transmit channel enable register partition b pcr0 39h pcr1 49h pcr2 35h 0eh pin control register rcerc0 39h rcerc1 49h rcerc2 35h 010h receive channel enable register partition c rcerd0 39h rcerd1 49h rcerd2 35h 011h receive channel enable register partition d xcerc0 39h xcerc1 49h xcerc2 35h 012h transmit channel enable register partition c xcerd0 39h xcerd1 49h xcerd2 35h 013h transmit channel enable register partition d rcere0 39h rcere1 49h rcere2 35h 014h receive channel enable register partition e rcerf0 39h rcerf1 49h rcerf2 35h 015h receive channel enable register partition f xcere0 39h xcere1 49h xcere2 35h 016h transmit channel enable register partition e xcerf0 39h xcerf1 49h xcerf2 35h 017h transmit channel enable register partition f rcerg0 39h rcerg1 49h rcerg2 35h 018h receive channel enable register partition g rcerh0 39h rcerh1 49h rcerh2 35h 019h receive channel enable register partition h xcerg0 39h xcerg1 49h xcerg2 35h 01ah transmit channel enable register partition g xcerh0 39h xcerh1 49h xcerh2 35h 01bh transmit channel enable register partition h functional overview 48 december 1999 ? revised december 2001 sprs122d 3.5 dma subbank addressed registers the direct memory access (dma) controller has several control registers associated with it. the main control register (dmprec) is a standard memory-mapped register. however, the other registers are accessed using the subbank addressing scheme. this allows a set or subbank of registers to be accessed through a single memory location. the dma subbank address (dmsa) register is used as a pointer to select a particular register within the subbank, while the dma subbank data (dmsdn) register or the dma subbank data register with autoincrement (dmsdi) is used to access (read or write) the selected register. when the dmsdi register is used to access the subbank, the subbank address is automatically postincremented so that a subsequent access affects the next register within the subbank. this autoincrement feature is intended for ef ficient, successive accesses to several control registers. if the autoincrement feature is not required, the dmsdn register should be used to access the subbank. table 3 ? 25 shows the dma controller subbank addressed registers and their corresponding subaddresses. table 3 ? 25. dma subbank addressed registers name address sub- address description dmsrc0 56h/57h 00h dma channel 0 source address register dmdst0 56h/57h 01h dma channel 0 destination address register dmctr0 56h/57h 02h dma channel 0 element count register dmsfc0 56h/57h 03h dma channel 0 sync select and frame count register dmmcr0 56h/57h 04h dma channel 0 transfer mode control register dmsrc1 56h/57h 05h dma channel 1 source address register dmdst1 56h/57h 06h dma channel 1 destination address register dmctr1 56h/57h 07h dma channel 1 element count register dmsfc1 56h/57h 08h dma channel 1 sync select and frame count register dmmcr1 56h/57h 09h dma channel 1 transfer mode control register dmsrc2 56h/57h 0ah dma channel 2 source address register dmdst2 56h/57h 0bh dma channel 2 destination address register dmctr2 56h/57h 0ch dma channel 2 element count register dmsfc2 56h/57h 0dh dma channel 2 sync select and frame count register dmmcr2 56h/57h 0eh dma channel 2 transfer mode control register dmsrc3 56h/57h 0fh dma channel 3 source address register dmdst3 56h/57h 10h dma channel 3 destination address register dmctr3 56h/57h 11h dma channel 3 element count register dmsfc3 56h/57h 12h dma channel 3 sync select and frame count register dmmcr3 56h/57h 13h dma channel 3 transfer mode control register dmsrc4 56h/57h 14h dma channel 4 source address register dmdst4 56h/57h 15h dma channel 4 destination address register dmctr4 56h/57h 16h dma channel 4 element count register dmsfc4 56h/57h 17h dma channel 4 sync select and frame count register dmmcr4 56h/57h 18h dma channel 4 transfer mode control register dmsrc5 56h/57h 19h dma channel 5 source address register dmdst5 56h/57h 1ah dma channel 5 destination address register dmctr5 56h/57h 1bh dma channel 5 element count register dmsfc5 56h/57h 1ch dma channel 5 sync select and frame count register dmmcr5 56h/57h 1dh dma channel 5 transfer mode control register dmsrcp 56h/57h 1eh dma source program page address (common channel) functional overview 49 december 1999 ? revised december 2001 sprs122d table 3 ? 25. dma subbank addressed registers (continued) name description sub- address address dmdstp 56h/57h 1fh dma destination program page address (common channel) dmidx0 56h/57h 20h dma element index address register 0 dmidx1 56h/57h 21h dma element index address register 1 dmfri0 56h/57h 22h dma frame index register 0 dmfri1 56h/57h 23h dma frame index register 1 dmgsa0 56h/57h 24h dma channel 0 global source address reload register dmgda0 56h/57h 25h dma channel 0 global destination address reload register dmgcr0 56h/57h 26h dma channel 0 global count reload register dmgfr0 56h/57h 27h dma channel 0 global frame count reload register ? 56h/57h 28h reserved ? 56h/57h 29h reserved dmgsa1 56h/57h 2ah dma channel 1 global source address reload register dmgda1 56h/57h 2bh dma channel 1 global destination address reload register dmgcr1 56h/57h 2ch dma channel 1 global count reload register dmgfr1 56h/57h 2dh dma channel 1 global frame count reload register dmgsa2 56h/57h 2eh dma channel 2 global source address reload register dmgda2 56h/57h 2fh dma channel 2 global destination address reload register dmgcr2 56h/57h 30h dma channel 2 global count reload register dmgfr2 56h/57h 31h dma channel 2 global frame count reload register dmgsa3 56h/57h 32h dma channel 3 global source address reload register dmgda3 56h/57h 33h dma channel 3 global destination address reload register dmgcr3 56h/57h 34h dma channel 3 global count reload register dmgfr3 56h/57h 35h dma channel 3 global frame count reload register dmgsa4 56h/57h 36h dma channel 4 global source address reload register dmgda4 56h/57h 37h dma channel 4 global destination address reload register dmgcr4 56h/57h 38h dma channel 4 global count reload register dmgfr4 56h/57h 39h dma channel 4 global frame count reload register dmgsa5 56h/57h 3ah dma channel 5 global source address reload register dmgda5 56h/57h 3bh dma channel 5 global destination address reload register dmgcr5 56h/57h 3ch dma channel 5 global count reload register dmgfr5 56h/57h 3dh dma channel 5 global frame count reload register dmsrcdp0 56h/57h 3eh dma channel 0 extended source data page register dmdstdp0 56h/57h 3fh dma channel 0 extended destination data page register dmsrcdp1 56h/57h 40h dma channel 1 extended source data page register dmdstdp1 56h/57h 41h dma channel 1 extended destination data page register dmsrcdp2 56h/57h 42h dma channel 2 extended source data page register dmdstdp2 56h/57h 43h dma channel 2 extended destination data page register dmsrcdp3 56h/57h 44h dma channel 3 extended source data page register dmdstdp3 56h/57h 45h dma channel 3 extended destination data page register dmsrcdp4 56h/57h 46h dma channel 4 extended source data page register dmdstdp4 56h/57h 47h dma channel 4 extended destination data page register functional overview 50 december 1999 ? revised december 2001 sprs122d table 3 ? 25. dma subbank addressed registers (continued) name description sub- address address dmsrcdp5 56h/57h 48h dma channel 5 extended source data page register dmdstdp5 56h/57h 49h dma channel 5 extended destination data page register 3.6 interrupts vector-relative locations and priorities for all internal and external interrupts are shown in table 3 ? 26. table 3 ? 26. 5441 interrupt locations and priorities for each dsp subsystem location name decimal hex priority function rs , sintr 0 00 1 reset (hardware and software reset) nmi , sint16 4 04 2 nonmaskable interrupt sint17 8 08 ? software interrupt #17 sint18 12 0c ? software interrupt #18 sint19 16 10 ? software interrupt #19 sint20 20 14 ? software interrupt #20 sint21 24 18 ? software interrupt #21 sint22 28 1c ? software interrupt #22 sint23 32 20 ? software interrupt #23 sint24 36 24 ? software interrupt #24 sint25 40 28 ? software interrupt #25 sint26 44 2c ? software interrupt #26 sint27 48 30 ? software interrupt #27 sint28 52 34 ? software interrupt #28 sint29 56 38 ? software interrupt #29 sint30 60 3c ? software interrupt #30 int , sint0 64 40 3 external user interrupt wdtint, sint1 68 44 4 watchdog timer interrupt int2 , sint2 72 48 5 software interrupt #2 tint, sint3 76 4c 6 external timer interrupt brint0, sint4 80 50 7 bsp #0 receive interrupt bxint0, sint5 84 54 8 bsp #0 transmit interrupt brint2, dmac0 88 58 9 bsp #2 receive interrupt or dma channel 0 bxint2, dmac1 92 5c 10 bsp #2 receive interrupt or dma channel 1 int3 , sint8 96 60 11 software interrupt #8 hpint, sint9 100 64 12 hpi interrupt (from dspint in hpic) brint1, dmac2 104 68 13 bsp #1 receive interrupt or dma channel 2 bxint1, dmac3 108 6c 14 bsp #1 transmit interrupt or dma channel 3 dmac4, sint12 112 70 15 dma channel 4 dmac5, sint13 116 74 16 dma channel 5 ? 120 ? 127 78 ? 7f ? reserved functional overview 51 december 1999 ? revised december 2001 sprs122d figure 3 ? 30 shows the bit layout of the imr and the ifr. table 3 ? 27 describes the bit functions. 15 14 13 12 11 10 9 8 reserved dmac5 dmac4 xint1 or dmac3 rint1 or dmac2 hpint reserved r/w r/w r/w r/w r/w 76543210 xint2 or dmac1 rint2 or dmac0 xint0 rint0 tint reserved wdtint int r/w r/w r/w r/w r/w r/w r/w legend: r = read, w = write figure 3 ? 30. bit layout of the imr and ifr registers for each subsystem table 3 ? 27. bit functions for imr and ifr registers for each dsp subsystem bit no. bit name bit value function 15 ? 14 reserved x register bit is reserved. 0 ifr/imr: dma channel 5 has no interrupt pending/is disabled (masked). 13 dmac5 1 ifr/imr: dma channel 5 has an interrupt pending/is enabled. 0 ifr/imr: dma channel 4 has no interrupt pending/is disabled (masked). 12 dmac4 1 ifr/imr: dma channel 4 has an interrupt pending/is enabled. 0 ifr/imr: mcbsp_1 has no transmit interrupt pending/is disabled (masked). xint1 1 ifr/imr: mcbsp_1 has a transmit interrupt pending/is enabled. 11 0 ifr/imr: dma channel 3 has no interrupt pending/is disabled (masked). dmac3 1 ifr/imr: dma channel 3 has an interrupt pending/is enabled. 0 ifr/imr: mcbsp_1 has no receive interrupt pending/is disabled (masked). rint1 1 ifr/imr: mcbsp_1 has a receive interrupt pending/is enabled. 10 0 ifr/imr: dma channel 2 has no interrupt pending/is disabled (masked). dmac2 1 ifr/imr: dma channel 2 has an interrupt pending/is enabled. 0 ifr/imr: host-port interface has no dspint interrupt pending/is disabled (masked). 9 hpint 1 ifr/imr: host-port interface has an dspint interrupt pending/is enabled. 8 reserved x register bit is reserved. 0 ifr/imr: mcbsp_2 has no transmit interrupt pending/is disabled (masked). xint2 1 ifr/imr: mcbsp_2 has a transmit interrupt pending/is enabled. 7 0 ifr/imr: dma channel 1 has no interrupt pending/is disabled (masked). dmac1 1 ifr/imr: dma channel 1 has an interrupt pending/is enabled. 0 ifr/imr: mcbsp_2 has no receive interrupt pending/is disabled (masked). rint2 1 ifr/imr: mcbsp_2 has a receive interrupt pending/is enabled. 6 0 ifr/imr: dma channel 0 has no interrupt pending/is disabled (masked). dmac0 1 ifr/imr: dma channel 0 has an interrupt pending/is enabled. 0 ifr/imr: mcbsp_0 has no receive interrupt pending/is disabled (masked). 5 xint0 1 ifr/imr: mcbsp_0 has a receive interrupt pending/is enabled. 0 ifr/imr: mcbsp_0 has no receive interrupt pending/is disabled (masked). 4 rint0 1 ifr/imr: mcbsp_0 has a receive interrupt pending/is enabled. functional overview 52 december 1999 ? revised december 2001 sprs122d table 3 ? 27. bit functions for imr and ifr registers for each dsp subsystem (continued) bit no. function bit value bit name 0 ifr/imr: timer has no interrupt pending/is disabled (masked). 3 tint 1 ifr/imr: timer has an interrupt pending/is enabled. 2 reserved x register bit is reserved. 0 ifr/imr: watchdog interrupt has no interrupt pending/is disabled (masked). 1 wdtint 1 ifr/imr: watchdog interrupt has an interrupt pending/is enabled. 0 ifr/imr: ext user interrupt pin 0 has no interrupt pending/is disabled (masked). 0 int 1 ifr/imr: ext user interrupt pin 0 has an interrupt pending/is enabled. 3.7 idle3 power-down mode the idle1 and idle2 power-down modes operate as described in the tms320c54x dsp reference set, volume 1: cpu and peripherals (literature number spru131). the idle3 mode is special in that the clocking circuitry is shut off to conserve power. the 5441 cannot enter an idle3 mode unless all the subsystems execute an idle3 instruction. the power-reduced benefits of idle3 cannot be realized until all the subsystems enter the idle3 state and the internal clocks are automatically shut off. the order in which subsystems enter idle3 does not matter. 3.8 emulating the 5441 device the 5441 is a single device, but actually consists of four independent subboundary systems that contain register/status information used by the emulator tools. code composer studio ? has a setup wizard called ? code composer setup. ? the setup wizard prompts the user for the i/o address of the xdssio card and the number of processors in the system. the board.dat file is then created and placed in the correct directory automatically. the board.dat file contents would look something like this: ? cpu_d ? ti320c5xx ? cpu_c ? ti320c5xx ? cpu_b ? ti320c5xx ? cpu_a ? ti320c5xx the subsystems are serially connected together internally. emulation information is serially transmitted into the device using tdi. the device responds with serial scan information transmitted out the tdo pin. code composer studio is a trademark of texas instruments. documentation support 53 december 1999 ? revised december 2001 sprs122d 4 documentation support extensive documentation supports all tms320 ? dsp family of devices from product announcement through applications development. the following types of documentation are available to support the design and use of the c5000 ? platform of dsps: ? tms320c5000 ? dsp family functional overview (literature number spru307) ? device-specific data sheets ? complete user guides ? development-support tools ? hardware and software application reports the five-volume tms320c54x dsp reference set (literature number spru210) consists of: ? volume 1: cpu and peripherals (literature number spru131) ? volume 2: mnemonic instruction set (literature number spru172) ? volume 3: algebraic instruction set (literature number spru179) ? volume 4: applications guide (literature number spru173) ? volume 5: enhanced peripherals (literature number spru302) the reference set describes in detail the tms320c54x ? dsp products currently available and the hardware and software applications, including algorithms, for fixed-point tms320 ? dsp devices. a series of dsp textbooks is published by prentice-hall and john wiley & sons to support digital signal processing research and education. the tms320 ? dsp newsletter, details on signal processing , is published quarterly and distributed to update tms320 ? dsp customers on product information. information regarding texas instruments (ti) dsp products is also available on the worldwide web at http://www.ti.com uniform resource locator (url). electrical specifications 54 december 1999 ? revised december 2001 sprs122d 5 electrical specifications this section provides the absolute maximum ratings and the recommended operating conditions for the tms320vc5441 dsp. leading ? x ? in signal names identifies the subsystem; x = a, b, c, or d for subsystem a, b, c, or d, respectively. trailing ? n ? in signal names identifies the mcbsp; n = 0, 1, or 2 for mcbsp0, mcbsp1, or mcbsp2, respectively. 5.1 absolute maximum ratings the list of absolute maximum ratings are specified over operating case temperature. stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under section 5.2 is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. all voltage values are with respect to v ss . figure 5 ? 1 provides the test load circuit values for a 3.3-v device. supply voltage i/o range, dv dd ? 0.3 v to 4.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply voltage core range, cv dd ? 0.3 v to 2.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply voltage analog pll, v cca ? 0.3 v to 2.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i ? 0.5 v to dv dd + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range, v o ? 0.5 v to dv dd + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating case temperature range, t c (commercial) 0 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t c (industrial) ? 40 c to 100 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range t stg ? 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 recommended operating conditions min nom max unit dv dd device supply voltage, i/o ? 3 3.3 3.6 v cv dd device supply voltage, core ? 1.55 1.6 1.65 v v cca device supply voltage, pll 1.55 1.6 1.65 v v ss supply voltage, gnd 0 v v ih high-level input voltage, i/o schmitt triggered inputs dv dd = 3.3 0.3 v 0.7dv dd dv dd + 0.3 v v ih high-level input voltage, i/o all other inputs 2 dv dd + 0.3 v v il low-level input voltage, i/o schmitt triggered inputs dv dd = 3.3 0.3 v 0 0.3dv dd v v il low-level input voltage, i/o all other inputs 0 0.8 v i oh high-level output current ? 1 ma i ol low-level output current 1.5 ma operating case temperature, commercial 0 85 ? 40 100 c ? texas instrument dsps do not require specific power sequencing between the core supply and the i/o supply. however, systems sho uld be designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper opera ting voltage. excessive exposure to these conditions can adversely affect the long-term reliability of the devices. system-level concerns suc h as bus contention may require supply sequencing to be implemented. in this case, the core supply should be powered up at the same time as or prior to the i/o buffers, and then powered down after the i/o buffers. electrical specifications 55 december 1999 ? revised december 2001 sprs122d 5.3 electrical characteristics over recommended operating case temperature range (unless otherwise noted) parameter test conditions min typ ? max unit v oh high-level output voltage ? v dd = 3.3 0.3 v, i oh = max 2.4 v v ol low-level output voltage ? i ol = max 0.4 v i iz input current in high impedance v dd = max, v o = v ss to v dd ? 10 10 a trst with internal pulldown ? 10 300 input current see pin descriptions with internal pullups ? 300 10 i i (v i = v ss to v dd ) d[15:0], ha[18:0] bus holders enabled, v dd = max || ? 230 230 a all other input-only pins ? 10 10 i ddc supply current, all four core cpus cv dd = 1.6 v, f x = 133 mhz , t c = 25 c 200 ? ma i ddp supply current, pins dv dd = 3.3 v, f clock = 133 mhz ? , t c = 25 c # 40 ma i dda supply current, pll 3 ma idle2 pll n mode, 20 mhz input 7 ma i ddc supply current, standby idle3 pll x n mode, 20 mhz input 1 ma c i input capacitance 5 pf c o output capacitance 5 pf ? all values are typical unless otherwise specified. ? all input and output voltage levels except x_rs , x_int , x_nmi , clkin, x_bclkx0, x_bclkr0, bclkx2, bclkr2, has , hcs , hds1 , hds2 , and reset are lvttl-compatible. clock mode: pll 1 with external source ? this value is based on 50% usage of mac and 50% usage of nop instructions. actual operating current varies with the program being ex ecuted. # this value was obtained using the following conditions: hpi in multiplexed mode with address autoincrement, hpi read, clkoff = 0, fu ll-duplex operation of all 12 mcbsps at a rate of 10 million bits per second each, and 15-pf loads on all outputs. for more details on ho w this calculation is performed, refer to the calculation of tms320lc54x power dissipation application report (literature number spra164). || v il(min) v i v il(max) or v ih(min) v i v ih(max) tester pin electronics v load i ol c t i oh output under test 50 ? where: i ol = 1.5 ma (all outputs) i oh = 300 a (all outputs) v load = 1.6 v c t = 20 pf typical load circuit capacitance figure 5 ? 1. 3.3-v test load circuit electrical specifications 56 december 1999 ? revised december 2001 sprs122d 5.4 package thermal resistance characteristics table 5 ? 1 provides the thermal resistance characteristics for the recommended package types used on the tms320vc5441 dsp. table 5 ? 1. thermal resistance characteristics parameter ggu package pgf package unit r ja 38 56 c/w r jc 5 5 c/w 5.5 timing parameter symbology timing parameter symbols used in the timing requirements and switching characteristics tables are created in accordance with jedec standard 100. to shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: lowercase subscripts and their meanings: letters and symbols and their meanings: a access time h high c cycle time (period) l low d delay time v valid dis disable time z high impedance en enable time f fall time h hold time r rise time su setup time t transition time v valid time w pulse duration (width) x unknown, changing, or don ? t care level electrical specifications 57 december 1999 ? revised december 2001 sprs122d 5.6 clock options the frequency of the reference clock provided at the clkin pin can be divided by a factor of two or four to generate the internal machine cycle. the selection of the clock mode is described in section 3.2.6. 5.6.1 divide-by-two, divide-by-four, and bypass clock options ? pll disabled the frequency of the reference clock provided at the clkin pin can be divided by a factor of two or four to generate the internal machine cycle. the selection of the clock mode is described in section 3.2.6. table 5 ? 2 and table 5 ? 3 assume testing over recommended operating conditions and h = 0.5t c(co) (see figure 5 ? 2). table 5 ? 2. divide-by-two, divide-by-four, and bypass clock options timing requirements min max unit t c(ci) cycle time, clkin 20 ? ns t f(ci) fall time, clkin 6 ns t r(ci) rise time, clkin 6 ns t w(cil) pulse duration, clkin low 5 ns t w(cih) pulse duration, clkin high 5 ns ? this device utilizes a fully static design and therefore can operate with t c(ci) approaching . the device is characterized at frequencies approaching 0 hz. table 5 ? 3. divide-by-two, divide-by-four, and bypass clock options switching characteristics parameter min typ max unit t c(co) cycle time, clkout 7.5 2t c(ci) ? ns t c(co) cycle time, clkout ? bypass mode 7.5 2t c(ci) ? ns t d(cih-co) delay time, clkin high to clkout high/low 2 7 11 ns t f(co) fall time, clkout 1 ns t r(co) rise time, clkout 1 ns t w(col) pulse duration, clkout low h ? 2 h ? 1 h ns t w(coh) pulse duration, clkout high h ? 2 h ? 1 h ns ? this device utilizes a fully static design and therefore can operate with t c(ci) approaching . the device is characterized at frequencies approaching 0 hz. t r(co) t f(co) clkout clkin t w(col) t d(cih-co) t f(ci) t r(ci) t c(co) t c(ci) t w(coh) t w(cih) t w(cil) figure 5 ? 2. external divide-by-two clock timing electrical specifications 58 december 1999 ? revised december 2001 sprs122d 5.6.2 multiply-by-n clock option ? pll enabled the frequency of the reference clock provided at the clkin pin can be multiplied by a factor of n to generate the internal machine cycle. the selection of the clock mode and the value of n is described in section 3.2.6. table 5 ? 4 and table 5 ? 5 assume testing over recommended operating conditions and h = 0.5t c(co) (see figure 5 ? 3). table 5 ? 4. multiply-by-n clock option timing requirements min max unit integer pll multiplier n (n = 1 ? 15) ? 20 ? 200 t c(ci) cycle time, clkin pll multiplier n = x.5 ? 20 ? 100 ns t c(ci) cycle time, clkin pll multiplier n = x.25, x.75 ? 20 ? 50 ns t f(ci) fall time, clkin 6 ns t r(ci) rise time, clkin 6 ns t w(cil) pulse duration, clkin low 5 ns t w(cih) pulse duration, clkin high 5 ns ? n = multiplication factor ? the multiplication factor and minimum clkin cycle time should be chosen such that the resulting clkout cycle time is within the specified range (t c(co) ) table 5 ? 5. multiply-by-n clock option switching characteristics parameter min typ max unit t c(co) cycle time, clkout 7.5 t c(ci) /n ? ns t d(ci-co) delay time, clkin high/low to clkout high/low 2 7 11 ns t f(co) fall time, clkout 1.5 ns t r(co) rise time, clkout 1.5 ns t w(col) pulse duration, clkout low h ? 2 h ? 1 h ns t w(coh) pulse duration, clkout high h ? 2 h ? 1 h ns t p transitory phase, pll lock up time 45 s ? n = multiplication factor t c(co) t c(ci) t w(coh) t f(co) t r(co) t f(ci) clkin clkout t d(ci-co) t w(col) t r(ci) tp unstable t w(cih) t w(cil) figure 5 ? 3. external multiply-by-one clock timing electrical specifications 59 december 1999 ? revised december 2001 sprs122d 5.7 reset, x_bio , and interrupt timings table 5 ? 6 assumes testing over recommended operating conditions and h = 0.5t c(co) (see figure 5 ? 4 and figure 5 ? 5). table 5 ? 6. reset, x_bio , and interrupt timing requirements min max unit t h(rs) hold time, x_rs after clkout low 0 ns t h(bio) hold time, x_bio after clkout low 0 ns t h(int) hold time, x_int , x_nmi , after clkout low ? 0 ns t w(rsl) pulse duration, x_rs low ? 4h+4 ns t w(bio)a pulse duration, x_bio low, asynchronous ? 5h ns t w(inth)a pulse duration, x_int , x_nmi high (asynchronous) ? 4h ns t w(intl)a pulse duration, x_int , x_nmi low (asynchronous) ? 4h ns t w(intl)wkp pulse duration, x_int , x_nmi low for idle2/idle3 wakeup ? 6 ns t su(rs) setup time, x_rs before clkin low 4 ns t su(bio) setup time, x_bio before clkout low 7 10 ns t su(int) setup time, x_int , x_nmi , x_rs before clkout low 7 10 ns ? the external interrupts (x_int , x_nmi ) are synchronized to the core cpu by way of a two flip-flop synchronizer, which samples these inputs with consecutive falling edges of clkout. the input to the interrupt pins is required to represent a 1-0-0 sequence at the timing that is corres ponding to a three-clkout sampling sequence. ? if the pll mode is selected, then at power-on sequence, or at wakeup from idle3, x_rs must be held low for at least 50 s to ensure synchronization and lock-in of the pll. x_rs can cause a change in clock frequency, changing the value of h (see section 3.2.6). x_bio clkout x_rs, x_nmi , x_int clkin t h(bio) t h(rs) t su(int) t w(bio)a t su(bio) t w(rsl) t su(rs) figure 5 ? 4. reset and x_bio timings electrical specifications 60 december 1999 ? revised december 2001 sprs122d x_int , x_nmi clkout t h(int) t su(int) t su(int) t w(intl)a t w(inth)a figure 5 ? 5. interrupt timing electrical specifications 61 december 1999 ? revised december 2001 sprs122d 5.8 external flag (x_xf), timer (x_tout), and watchdog timer output (x_wtout ) timings table 5 ? 7 assumes testing over recommended operating conditions and h = 0.5t c(co) (see figure 5 ? 6, figure 5 ? 7, and figure 5 ? 8). table 5 ? 7. external flag (x_xf), timer (x_tout), and watchdog timer output (x_wtout ) switching characteristics parameter min max unit delay time, clkout low to x_xf high ? 1 4 t d(xf) delay time, clkout low to x_xf low ? 1 4 ns t d(touth) delay time, clkout low to x_tout high ? 1 4 ns t d(toutl) delay time, clkout low to x_tout low ? 1 4 ns t w(tout) pulse duration, x_tout 2h ? 8 2h ns t d(wtouth) delay time, clkout low to x_wtout high ? 1 4 ns t d(wtoutl) delay time, clkout low to x_wtout low ? 1 4 ns t w(wtout) pulse duration, x_wtout 2h ? 8 ns x_xf clkout t d(xf) figure 5 ? 6. external flag (x_xf) timing x_tout clkout t w(tout) t d(toutl) t d(touth) figure 5 ? 7. timer (x_tout) timing x_wtout clkout t w(wtout) t d(wtoutl) t d(wtouth) figure 5 ? 8. watchdog timer (x_wtout ) timing electrical specifications 62 december 1999 ? revised december 2001 sprs122d 5.9 general-purpose input/output (gpio) timing table 5 ? 8 and table 5 ? 9 assume testing over recommended operating conditions (see figure 5 ? 9). table 5 ? 8. gpio timing requirements min max unit t su(gpio-coh) setup time, x_gpion input valid before clkout high, x_gpion configured as general-purpose input. 7 ns t h(gpio-coh) hold time, x_gpion input valid after clkout high, x_gpion configured as general-purpose input. 0 ns table 5 ? 9. gpio switching characteristics parameter min max unit t d(coh-gpio) delay time, clkout high to x_gpion output change. x_gpion configured as general-purpose output. 0 6 ns x_gpion input mode clkout t h(gpio-coh) x_gpion output mode t su(gpio-coh) t d(coh-gpio) figure 5 ? 9. gpio timings electrical specifications 63 december 1999 ? revised december 2001 sprs122d 5.10 multichannel buffered serial port timing 5.10.1 mcbsp0/1/2 transmit and receive timings the serial port timings that are referenced to clkout are actually related to the internal cpu clock frequency. these timings are not affected by the value of the divfct bit field in the bscr register (see section 3.2.2.5 of this data manual for details on the bscr register). any references to clkout in these timing parameters refer to the clkout timings when no divide factor is selected (divfct=00b). table 5 ? 10 and table 5 ? 11 assume testing over recommended operating conditions and h = 0.5t c(co) (see figure 5 ? 10 and figure 5 ? 11). table 5 ? 10. mcbsp0/1/2 t ransmit and receive timing requirements ? min max unit t c(bckrx) cycle time, x_bclkr/x bclkr/x ext 50 ns t w(bckrx) pulse duration, x_bclkr/x low or x_bclkr/x high bclkr/x ext 24 ns t h(bckrl-bfrh) hold time, external x_bfsr high after x_bclkr low bclkr ext 7.5 ns t h(bckrl-bdrv) hold time, x_bdr valid after x_bclkr low bclkr ext 7.5 ns t h(bckxl-bfxh) hold time, external x_bfsx high after x_bclkx low bclkx ext 7.5 ns t su(bfrh-bckrl) setup time, external x_bfsr high before x_bclkr low bclkr ext 7.5 ns t su(bdrv-bckrl) setup time, x_bdr valid before x_bclkr low bclkr ext 7.5 ns t su(bfxh-bckxl) setup time, external x_bfsx high before x_bclkx low bclkx ext 7.5 ns t r(bckrx) rise time, x_bclkr/x bclkr/x ext 6 ns t f(bckrx) fall time, x_bclkr/x bclkr/x ext 6 ns ? polarity bits clkrp = clkxp = fsrp = fsxp = 0. if the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. electrical specifications 64 december 1999 ? revised december 2001 sprs122d table 5 ? 11. mcbsp0/1/2 t ransmit and receive switching characteristics ? parameter min max unit t d(bckxh-bfxv) delay time, x_bclkx high to internal x_bfsx valid bclkx ext 2 15 ns t dis(bckxh-bdxhz) disable time, x_bclkx high to x_bdx high impedance following last data bit bclkx ext 1 18 ns delay time, x_bclkx high to x_bdx valid. this applies to all bits except the first bit transmitted. bclkx ext 4 20 t d(bckxh-bdxv) delay time, x_bclkx high to x_bdx valid. dxena = 0 bclkx ext 16 ns only applies to first bit transmitted when in data delay 1 or 2 (xdatdly=01b or 10b) modes dxena = 1 bclkx ext 4h+19 enable time, x_bclkx high to x_bdx driven. dxena = 0 bclkx ext 2 t en(bckxh-bdx) only applies to first bit transmitted when in data delay 1 or 2 (xdatdly=01b or 10b) modes dxena = 1 bclkx ext 4h+2 ns delay time, x_bfsx high to x_bdx valid. dxena = 0 bfsx ext 17 t d(bfxh-bdxv) only applies to first bit transmitted when in data delay 0 (xdatdly=00b) mode. dxena = 1 bfsx ext 4h+15 ns enable time, x_bfsx high to x_bdx driven. dxena = 0 bfsx ext 1 t en(bfxh-bdx) only applies to first bit transmitted when in data delay 0 (xdatdly=00b) mode dxena = 1 bfsx ext 4h+5 ns ? polarity bits clkrp = clkxp = fsrp = fsxp = 0. if the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ? t=bclkrx period = (1 + clkgdv) * 2h c=bclkrx low pulse width = t/2 when clkgdv is odd or zero and = (clkgdv/2) * 2h when clkgdv is even d=bclkrx high pulse width = t/2 when clkgdv is odd or zero and = (clkgdv/2 + 1) * 2h when clkgdv is even see the tms320c54x dsp reference set, volume 5: enhanced peripherals (literature number spru302) for a description of the dx enable (dxena) and data delay features of the mcbsp. electrical specifications 65 december 1999 ? revised december 2001 sprs122d (n ? 2) bit (n ? 1) (n ? 3) (n ? 2) bit (n ? 1) (n ? 4) (n ? 3) (n ? 2) bit (n ? 1) t h(bckrl ? bdrv) t su(bdrv ? bckrl) t h(bckrl ? bdrv) t su(bdrv ? bckrl) t su(bdrv ? bckrl) t h(bckrl ? bdrv) t h(bckrl ? bfrh) t su(bfrh ? bckrl) t d(bckrh ? bfrv) t d(bckrh ? bfrv) t r(bckrx) t r(bckrx) t w(bckrxl) t c(bckrx) t w(bckrxh) (rdatdly=10b) x_bdr (rdatdly=01b) x_bdr (rdatdly=00b) x_bdr x_bfsr (ext) x_bfsr (int) x_bclkr figure 5 ? 10. mcbsp0/1/2 receive timings t en(bckxh ? bdx) t d(bckxh ? bdxv) t d(bckxh ? bdxv) t en(bckxh ? bdx) t dis(bckxh ? bdxhz) t d(bckxh ? bdxv) t d(bfxh ? bdxv) t en(bfxh ? bdx) (xdatdly=10b) x_bdx (xdatdly=01b) x_bdx (xdatdly=00b) x_bdx (n ? 2) bit (n ? 1) bit 0 (n ? 4) bit (n ? 1) (n ? 3) (n ? 2) bit 0 (n ? 3) (n ? 2) bit (n ? 1) bit 0 t h(bckxl ? bfxh) t f(bckrx) t r(bckrx) t w(bckrxl) t c(bckrx) t w(bckrxh) x_bfsx (ext) x_bfsx (int) x_bclkx t d(bckxh ? bfxv) t d(bckxh ? bfxv) t su(bfxh ? bckxl) figure 5 ? 11. mcbsp0/1/2 transmit timings electrical specifications 66 december 1999 ? revised december 2001 sprs122d 5.10.2 mcbsp0 general-purpose i/o timing table 5 ? 12 and table 5 ? 13 assume testing over recommended operating conditions (see figure 5 ? 12). table 5 ? 12. mcbsp0 general-purpose i/o timing requirements min max unit t su(bgpio-coh) setup time, bgpiox input mode before clkout high ? 7 ns t h(coh-bgpio) hold time, bgpiox input mode after clkout high ? 0 ns ? bgpiox refers to x_bclkr, x_bfsr, x_bdr, x_bclkx, or x_bfsx when configured as a general-purpose input. table 5 ? 13. mcbsp0 general-purpose i/o switching characteristics parameter min max unit t d(coh-bgpio) delay time, clkout high to bgpiox output mode ? ? 8 8 ns ? bgpiox refers to x_bclkr, x_bfsr, x_bclkx, x_bfsx, or x_bdx when configured as a general-purpose output. t su(bgpio-coh) t h(coh-bgpio) t d(coh-bgpio) clkout bgpiox input mode ? bgpiox output mode ? ? bgpiox refers to x_bclkr, x_bfsr, x_bdr, x_bclkx, or x_bfsx when configured as a general-purpose input. ? bgpiox refers to x_bclkr, x_bfsr, x_bclkx, x_bfsx, or x_bdx when configured as a general-purpose output. figure 5 ? 12. mcbsp0 general-purpose i/o timings electrical specifications 67 december 1999 ? revised december 2001 sprs122d 5.11 host-port interface (hpi16) timing table 5 ? 14 and table 5 ? 15 assume testing over recommended operating conditions and h = 0.5t c(co) (see figure 5 ? 13 through figure 5 ? 19). in the following tables, ds refers to the logical or of hcs , hds1 , and hds2 , and hd refers to any of the hpi data bus pins (hd0, hd1, hd2, etc.). table 5 ? 14. hpi16 timing requirements min max unit t su(hbv-dsl) setup time, had valid before ds falling edge ?? 4 ns t h(dsl-hbv) hold time, had valid after ds falling edge ?? 4 ns t su(hbv-hsl) setup time, had valid before has falling edge ? 4 ns t h(hsl-hbv) hold time, had valid after has falling edge ? 4 ns t su(hav-dsh) setup time, address valid before ds rising edge (nonmultiplexed write) ? 5 ns t su(hav-dsl) setup time, address valid before ds falling edge (nonmultiplexed read) ? ? (4h + 5) ns t h(dsh-hav) hold time, address valid after ds rising edge (nonmultiplexed mode) ? 2 ns t su(hsl-dsl) setup time, has low before ds falling edge ? 4 ns t h(hsl-dsl) hold time, has low after ds falling edge ? 2 ns t w(dsl) pulse duration, ds low ? 23 ns t w(dsh) pulse duration, ds high ? 8 ns nonmultiplexed or multiplexed mode (no increment) memory accesses (or reads 10h + 20 (no increment) memory accesses (or writes to the fetch bit) with no dma activity. writes 10h + 10 ns cycle time, ds rising edge to next ds nonmultiplexed or multiplexed mode (no increment) memory accesses (or reads 16h + 20 cycle time, ds rising edge to next ds rising edge ? (no increment) memory accesses (or writes to the fetch bit) with 16-bit dma activity. writes 16h + 10 ns nonmultiplexed or multiplexed mode (no increment) memory accesses (or reads 24h + 20 (no increment) memory accesses (or writes to the fetch bit) with 32-bit dma activity. writes 24h + 10 ns t c(dsh-dsh) cycle time, ds rising edge to next ds multiplexed (autoincrement) memory accesses (or writes to the fetch bit) with no dma activity. 10h + 10 ns rising edge ? (in autoincrement mode, write multiplexed (autoincrement) memory accesses (or writes to the fetch bit) with 16-bit dma activity. 16h + 10 ns timings are the same as read timings.) multiplexed (autoincrement) memory accesses (or writes to the fetch bit) with 32-bit dma activity. 24h + 10 ns cycle time, ds rising edge to next ds rising edge for writes to dspint and x_hint 8h ns cycle time, ds rising edge to next ds rising edge for hpic reads, hpic xadd bit writes, and address register reads and writes 40 ns t su(hdv-dsh)w setup time, hd valid before ds rising edge ? 4 ns t h(dsh-hdv)w hold time, hd valid after ds rising edge, write ? 2 ns t su(selv-dsl) setup time, hpi_sel1/sel2 valid before ds falling edge ? 4 ns t h(dsh-selv) hold time, hpi_sel1/sel2 valid after ds rising edge ? 1 ns ? had stands for hcntl0, hcntl1, and hr/w . ? ds refers to either hcs or hds , whichever is controlling the transfer. refer to the tms320c54x dsp reference set, volume 5: enhanced peripherals (literature number spru302) for information regarding logical operation of the hpi16. these timings are shown assuming that hd s is the signal controlling the transfer. electrical specifications 68 december 1999 ? revised december 2001 sprs122d table 5 ? 15. hpi16 switching characteristics parameter min max unit t d(dsl-hdd) delay time, ds low to hd driven ? 3 20 ns case 1a: memory accesses initiated immediately following a write when dmac is active in 16-bit mode and t w(dsh) was < 18h 32h+20 ? t w(dsh) ns case 1b: memory accesses initiated by an autoincrement when dmac is active in 16-bit mode and t w(dsh) was < 18h 16h+20 ? t w(dsh) ns case 1c: memory accesses not initiated by an autoincrement (or not immediately following a write) when dmac is active in 16-bit mode 16h+20 case 1d: memory accesses initiated by an autoincrement when dmac is active in 16-bit mode and t w(dsh) was 18h 20 ns case 1e: memory accesses initiated immediately following a write when dmac is active in 16-bit mode and t w(dsh) was < 26h 48h+20 ? t w(dsh) ns delay time, ds case 1f: memory access initiated by an autoincrement when dmac is active in 32-bit mode and t w(dsh) was < 26h 24h+20 ? t w(dsh) t d(dsl-hdv1) delay time, ds low to hd valid for first word of case 1g: memory access not initiated by an autoincrement (or not immediately following a write) when dmac is active in 32-bit mode 24h+20 ns an hpi read case 1h: memory access initiated by an autoincrement when dmac is active in 32-bit mode and t w(dsh) was 26h 20 case 2a: memory accesses initiated immediately following a write when dmac is active in 16-bit mode and t w(dsh) was < 10h 20h+20 ? t w(dsh) ns case 2b: memory accesses initiated by an autoincrement when dmac is inactive and t w(dsh) was < 10h 10h+20 ? t w(dsh) case 2c: memory accesses not initiated by an autoincrement (or not immediately following a write) when dmac is inactive 10h+20 ns case 2d: memory accesses initiated by an autoincrement when dmac is inactive and t w(dsh) was 10h 20 ns case 3: hpic/hpia reads 20 t d(dsl-hdv2) multiplexed reads with autoincrement. prefetch completed. 3 20 ns delay time, ds memory accesses (or writes to the fetch bit) when no dma is active 10h+5 t delay time, ds high to hrdy high ? memory accesses (or writes to the fetch bit) with one or more 16-bit dma channels active 16h+5 ns t d(dsh-hyh) (writes and autoincrement memory accesses (or writes to the fetch bit) with one or more 32-bit dma channels active 24h+5 reads) writes to dspint and x_hint ? 4h + 5 t v(hyh-hdv) valid time, hd valid after hrdy high 6 ns t h(dsh-hdv)r hold time, hd valid after ds rising edge, read ? 0 10 ns t d(dsl-hyl) delay time, ds low to hrdy low ? 18 ns t d(dsh-hyl) delay time, ds high to hrdy low ? 18 ns t d(hsl-hyl) delay time, has low to hrdy low, read 18 ns ? ds refers to either hcs or hds , whichever is controlling the transfer. refer to the tms320c54x dsp reference set, volume 5: enhanced peripherals (literature number spru302) for information regarding logical operation of the hpi16. these timings are shown assuming that hds is the signal controlling the transfer. ? hrdy does not go low for other register accesses. electrical specifications 69 december 1999 ? revised december 2001 sprs122d pf data data 1 01 01 hrdy ? hd[15:0] hcntl[1:0] hr/w hds has hcs t c(dsh ? dsh) t w(dsh) t w(dsl) t d(dsl ? hdv2) t d(dsh ? hyh) ? t h(dsh ? hdv)r t v(hyh ? hdv) t h(hsl ? hbv) t su(hbv ? hsl) t su(hsl ? dsl) t h(hsl ? dsl) t d(dsh ? hyl) ? t d(dsl ? hdv1) t d(hsl ? hyl) t d(dsl ? hdd) ? hrdy goes low at these times only after autoincrement reads. ? while hcs is not selected, hrdy is in high-z state. figure 5 ? 13. multiplexed read timings using has electrical specifications 70 december 1999 ? revised december 2001 sprs122d pf data 01 01 t h(dsl ? hbv) t su(hbv ? dsl) hrdy ? hd[15:0] hcntl[1:0] hr/w hds hcs t c(dsh ? dsh) t w(dsh) t w(dsl) t d(dsl ? hdv2) t d(dsh ? hyh) ? t d(dsl ? hyl) t h(dsh ? hdv)r t v(hyh ? hdv) t d(dsl ? hdv1) t d(dsl ? hdd) t d(dsh ? hyl) ? data 1 ? hrdy goes low at these times only after autoincrement reads. ? while hcs is not selected, hrdy is in high-z state. figure 5 ? 14. multiplexed read timings with has held high electrical specifications 71 december 1999 ? revised december 2001 sprs122d t d(dsh ? hyl) t h(dsh ? hdv)w t su(hdv ? dsh)w t w(dsl) t w(dsh) t c(dsh ? dsh) t su(hsl ? dsl) data 2 data 1 hd[15:0] 01 01 hrdy ? hds hcntl[1:0] hr/w has hcs t h(hsl ? hbv) t su(hbv ? hsl) t d(dsh ? hyh) t h(hsl ? dsl) ? while hcs is not selected, hrdy is in high-z state. figure 5 ? 15. multiplexed write timings using has electrical specifications 72 december 1999 ? revised december 2001 sprs122d t d(dsh ? hyl) t h(dsh ? hdv)w t su(hdv ? dsh)w t w(dsl) t h(dsl ? hbv) t su(hbv ? dsl) t c(dsh ? dsh) t w(dsh) data 2 data 1 hd[15:0] 01 01 hrdy ? hcntl[1:0] hr/w hds hcs t d(dsh ? hyh) ? while hcs is not selected, hrdy is in high-z state. figure 5 ? 16. multiplexed write timings with has held high electrical specifications 73 december 1999 ? revised december 2001 sprs122d t c(dsh ? dsh) t w(dsh) t su(hbv ? dsl) t w(dsl) t h(dsl ? hbv) t su(hav ? dsl) t h(dsh ? hdv)r t v(hyh ? hdv) t d(dsl ? hyl) hcs hds hr/w ha[18:0] hd[15:0] hrdy ? valid address data valid address t su(hbv ? dsl) t h(dsl ? hbv) t d(dsl ? hdv1) data t d(dsl ? hdv1) t v(hyh ? hdv) t h(dsh ? hdv)r t d(dsl ? hyl) t h(dsh ? hav) t d(dsl ? hdd) t d(dsl ? hdd) ? while hcs is not selected, hrdy is in high-z state. figure 5 ? 17. nonmultiplexed read timings electrical specifications 74 december 1999 ? revised december 2001 sprs122d hrdy ? hd[15:0] ha[18:0] hr/w hds hcs data valid data valid t h(dsh ? hdv)w t su(hdv ? dsh)w valid address valid address t h(dsh ? hav) t h(dsl ? hbv) t w(dsl) t su(hbv ? dsl) t w(dsh) t c(dsh ? dsh) t d(dsh ? hyh) t d(dsh ? hyl) t su(hav ? dsh) t h(dsl ? hbv) t su(hbv ? dsl) t h(dsh ? hdv)w t su(hdv ? dsh)w ? while hcs is not selected, hrdy is in high-z state. figure 5 ? 18. nonmultiplexed write timings hds hpi_sel1 hcs t h(dsh ? selv1) t su(selv1 ? dsl) hpi_sel2 t h(dsh ? selv2) t su(selv2 ? dsl) figure 5 ? 19. hpi_sel1 and hpi_sel2 timing mechanical data 75 december 1999 ? revised december 2001 sprs122d 6 mechanical data 6.1 ball grid array mechanical data ggu (s-pbga-n169) plastic ball grid array 0,80 0,10 m 0,08 0,80 4073221-3/b 08/00 0,12 0,08 0,85 0,95 12,10 11,90 sq 1,40 max 0,45 0,55 0,45 0,35 seating plane 9,60 typ g a d b c e f h j l k m n 5 13 2 4 678910111213 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. microstar bga ? configuration figure 6 ? 1. tms320vc5441 169-ball microstar bga ? plastic ball grid array (ggu) package microstar bga is a trademark of texas instruments. mechanical data 76 december 1999 ? revised december 2001 sprs122d 6.2 low-profile quad flatpack mechanical data pgf (s-pqfp-g176) plastic quad flatpack 0,13 nom 89 0,17 0,27 88 45 0,45 0,25 0,75 44 seating plane 0,05 min 4040134/b 11/96 gage plane 132 133 176 sq 24,20 sq 25,80 26,20 23,80 21,50 sq 1 1,45 1,35 1,60 max m 0,08 0,50 0,08 0 ? 7 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026 figure 6 ? 2. tms320vc5441 176-pin low-profile quad flatpack (pgf) package |
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