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c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 a n p e c r e s e r v e s t h e r i g h t t o m a k e c h a n g e s t o i m p r o v e r e l i a b i l i t y o r m a n u f a c t u r a b i l i t y w i t h o u t n o t i c e , a n d a d v i s e c u s t o m e r s t o o b t a i n t h e l a t e s t v e r s i o n o f r e l e v a n t i n f o r m a t i o n t o v e r i f y b e f o r e p l a c i n g o r d e r s . s y n c h r o n o u s s i n g l e p w m c o n t r o l l e r w i t h m u l t i f o r m s u p p l y v o l t a g e a p w 8 7 2 7 / l f e a t u r e s g e n e r a l d e s c r i p t i o n a p p l i c a t i o n s n o t e b o o k t a b l e p c h a n d - h e l d p o r t a b l e a i o p c w i d e i n p u t d c / d c r e g u l a t o r s t h e a p w 8 7 2 7 i s a s i n g l e - p h a s e , c o n s t a n t o n - t i m e , s y n - c h r o n o u s p w m c o n t r o l l e r , w h i c h d r i v e s n - c h a n n e l m o s f e t s . t h e a p w 8 7 2 7 s t e p s d o w n h i g h v o l t a g e t o g e n e r a t e l o w - v o l t a g e c h i p s e t , r a m s u p p l i e s i n n o t e b o o k c o m p u t e r s o r m o t h e r b o a r d a p p l i c a t i o n s . t h e a p w 8 7 2 7 p r o v i d e s e x c e l l e n t t r a n s i e n t r e s p o n s e a n d a c c u r a t e d c v o l t a g e o u t p u t i n e i t h e r p f m o r p w m m o d e . i n p u l s e f r e q u e n c y m o d e ( p f m ) , t h e a p w 8 7 2 7 p r o v i d e s v e r y h i g h e f f i c i e n c y o v e r l i g h t t o h e a v y l o a d s w i t h l o a d i n g - m o d u l a t e d s w i t c h i n g f r e q u e n c i e s . i n p w m m o d e , t h e c o n - v e r t e r w o r k s n e a r l y a t c o n s t a n t f r e q u e n c y f o r l o w - n o i s e r e q u i r e m e n t s . t h e u n i q u e u l t r a s o n i c m o d e m a i n t a i n s t h e s w i t c h i n g f r e q u e n c y a b o v e 3 7 k h z , w h i c h e l i m i n a t e s n o i s e i n a u d i o a p p l i c a t i o n . t h e a p w 8 7 2 7 i s e q u i p p e d w i t h a c c u r a t e p o s i t i v e c u r r e n t l i m i t , o u t p u t u n d e r - v o l t a g e , a n d o u t p u t o v e r - v o l t a g e p r o t e c t i o n s , p e r f e c t f o r m u l t i f o r m a p p l i c a t i o n s . t h e p o w e r - o n - r e s e t f u n c t i o n m o n i t o r s t h e v o l t a g e o n v c c t o p r e - v e n t w r o n g o p e r a t i o n d u r i n g p o w e r - o n . t h e a p w 8 7 2 7 h a s a n i n t e r n a l 2 m s d i g i t a l s o f t s t a r t t h a t r a m p s u p t h e o u t p u t v o l t a g e w i t h p r o g r a m m a b l e s l e w r a t e t o r e d u c e t h e s t a r t - u p c u r r e n t . t h e e n a b l e f u n c t i o n c a n l e t u s e r e a s y t o a p p l y a p w 8 7 2 7 . t h e a p w 8 7 2 7 i s a v a i l a b l e i n 1 0 p i n t d f n 3 x 3 p a c k a g e r e s p e c t i v e l y . adjustable output voltage from +0.8v to +5.0v - 0.8v reference voltage - + 0.6% accuracy operates from an input battery voltage range of +4v to +25v multiform purpose input voltage collocation - -v cc =5v / v in =8~19v for nb application - v cc =5~12v / v in =5~12v for table pc application power-on-reset monitoring on v cc pin excellent line and load transient responses ultrasonic operation eliminated audio noise pfm mode for increased light load efficiency 300khz constant pwm switching frequency integrated mosfet drivers integrated bootstrap forward p-ch mosfet integrated soft-start function power good monitoring 70% under-voltage protection 125% over-voltage protection adjustable current-limit protection - using sense low-side mosfet?s r ds(on) over-temperature protection tdfn-10 3x3 package lead free and green devices available (rohs compliant) s i m p l i f i e d a p p l i c a t i o n c i r c u i t v out l q 1 q 2 en apw 8727 v in pok 4 . 5 ~ 13 . 2 v phase ugate lgate / ocset vcc 4 ~ 25 v
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 a p w 8 7 2 7 / l o r d e r i n g a n d m a r k i n g i n f o r m a t i o n n o t e : a n p e c l e a d - f r e e p r o d u c t s c o n t a i n m o l d i n g c o m p o u n d s / d i e a t t a c h m a t e r i a l s a n d 1 0 0 % m a t t e t i n p l a t e t e r m i n a t i o n f i n i s h ; w h i c h a r e f u l l y c o m p l i a n t w i t h r o h s . a n p e c l e a d - f r e e p r o d u c t s m e e t o r e x c e e d t h e l e a d - f r e e r e q u i r e m e n t s o f i p c / j e d e c j - s t d - 0 2 0 d f o r m s l c l a s s i f i c a t i o n a t l e a d - f r e e p e a k r e f l o w t e m p e r a t u r e . a n p e c d e f i n e s ? g r e e n ? t o m e a n l e a d - f r e e ( r o h s c o m p l i a n t ) a n d h a l o g e n f r e e ( b r o r c l d o e s n o t e x c e e d 9 0 0 p p m b y w e i g h t i n h o m o g e n e o u s m a t e r i a l a n d t o t a l o f b r a n d c l d o e s n o t e x c e e d 1 5 0 0 p p m b y w e i g h t ) . p i n c o n f i g u r a t i o n = gnd and thermal pad ( connected to gnd plane for better heat dissipation ) lgate / ocset 4 6 vcc 7 en 8 fb 9 vsense 10 pok apw 8727 tdfn - 10 3 x 3 ( top view ) boot 1 phase 2 ugate 3 gnd 5 lgate / ocset 4 6 vcc 7 en 8 fb 9 nc 10 pok apw 8727 l tdfn - 10 3 x 3 ( top view ) boot 1 phase 2 ugate 3 gnd 5 a b s o l u t e m a x i m u m r a t i n g s ( n o t e 1 ) symbol parameter rating unit v cc vcc supply voltage (vcc to gnd) - 0.3 ~ 16 v v boot - gnd boot supply voltage (boot to gnd) - 0.3 ~ 44 v v boot boot supply voltage (boot to phase) - 0.3 ~ 16 v v pok pok supply voltage ( pok to gnd ) - 0.3 ~ 16 v all other pins (en, vsense and fb to gnd) - 0.3~7 v apw 8727 / l handling code temperature range . package code assembly meterial package code temperature range i : - 40 to 85 o c handling code assembly meterial g : halogen and lead free device qb : tdfn 3 x 3 - 10 tr : tape & reel apw 8727 xxxxx xxxxx - date code apw 8727 qb : apw 8727 l xxxxx xxxxx - date code qb : apw 8727 l
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 3 a p w 8 7 2 7 / l a b s o l u t e m a x i m u m r a t i n g s ( c o n t . ) ( n o t e 1 ) note1: stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom- mended operating conditions" is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. t h e r m a l c h a r a c t e r i s t i c s symbol parameter typical value unit q ja thermal resistance - junction to ambient (note 2) tdfn3x3 - 10 55 c/w note 2: q ja is measured with the component mounted on a high effective thermal conductivity test board in free air.the exposed pad of package is soldered directly on the pcb. symbol parameter range unit v in converter input voltage 4 ~ 25 v v cc vcc supply voltage 4.5 ~ 13.2 v v out converter output voltage 0.8~5 v i out converter output current 0 ~ 20 a t a ambient temperature - 40 ~ 85 o c t j junction temperature - 40 ~ 125 o c r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s ( n o t e 3 ) n o t e 3 : r e f e r t o t h e a p p l i c a t i o n c i r c u i t f o r f u r t h e r i n f o r m a t i o n . symbol parameter rating unit ugate voltage (ugate to phase) < 2 0ns pulse width > 2 0ns pulse width - 3 ~ v boot + 3 - 0.3 ~ v boot +0.3 v lgate voltage (lgate to gnd) < 2 0ns pulse width > 2 0ns pulse width - 5 ~ v cc + 5 - 0.3 ~ v cc +0.3 v v phase phase voltage (phase to gnd) < 2 0ns pulse width > 2 0ns pulse width - 5 ~ 3 5 - 0.3 ~ 2 8 v t j maximum junction temperature 150 o c t stg storage temperature - 65 ~ 150 o c t sdr maximum soldering temperature, 10 seconds 260 o c
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 4 a p w 8 7 2 7 / l e l e c t r i c a l c h a r a c t e r i s t i c s apw8727 symbal parameter test condition min. typ. max. unit reference v oltage reference voltage - 0.8 - v t a = 25 o c - 0.6 - +0.6 % v ref regulation accuracy t a = - 40 o c ~ 85 o c, line / load transient - 1.0 - +1.0 % i fb fb input bias current fb=0.8v - - 1 m a supply current i vcc vcc input bias current vcc current, en=5v, v fb =0.9v, phase=0.5v - 2 3 ma i vcc_shd n vcc shutdown current en =gnd , vcc=5v - 15.3 20 m a sw itching frequency and duty t on pwm on time v in =12v, v out =1v 222 278 333 ns t off (min) minimum off time v fb =0.75v, v phase = - 0.1v 300 400 500 ns minimum ultrasonic skip operating frequency 25 37 - khz power on timing ocp threshold setting time when se t the max. value - 950 - m s t ss internal s oft s tart t ime v out =0% to v out regulation (95%) - 2 - ms gate driver 5v ug source current vcc=5v, boot - ug=5v - 1.5 - a 5v ug sink resistance vcc=5v, ug - phase=1v - 1.4 - w 5v lg source current vcc=5v, vcc - lg=5v - 1.5 - a 5v l g si nk resistance vcc=5v, lg - gnd=1v - 1.0 - w ug to lg dead time ug falling to lg rising at vcc=5v - 40 - ns ug falling to lg rising at vcc=12v - 20 - ns lg to ug dead time lg falling to ug rising at vcc=5v - 40 - ns lg falling to ug rising at vcc=12 v - 20 - ns bootstrap switch v f bootstrap forward voltage v vcc ? v boot - gnd , i f = 10ma - 0.2 0.4 v i r reverse leakage v boot - gnd = 30v, v phase = 25v, v vcc = 5v - - 0.5 m a these specifications apply for t a = -40 o c to +85 o c, unless otherwise stated. all typical specifications t a = +25 o c, v cc = 12v
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 5 a p w 8 7 2 7 / l e l e c t r i c a l c h a r a c t e r i s t i c s ( c o n t . ) apw8727 symbal parameter test condition min. typ. max. unit vcc por threshold v vcc_thr ris ing vcc por threshold voltage 4.25 4.35 4.45 v vcc por hysteresis - 300 - mv control inputs shutdown - - 0.85 en threshold enable 1.3 - - v en le akage en = 5 v - 0.1 1.0 m a power - ok indicator pok in from lower (pok goes high) 87 90 93 % pok out from normal falling (pok goes low) 65 70 75 % v pok pok threshold pok out from normal rising (pok goes low) 120 125 130 % i pok p ok leakage current v pok =5v - 0.1 1 m a p ok s ink current v pok =0.5v 5 15 - ma pok enable delay time v out from 0% to pok high - 2.5 - ms current sense i ocset i ocset ocp threshold i ocset sourc ing 9.5 10 10.5 m a t ci ocset i ocset t emperature c oefficient on t he b asis of 25c 2780 ppm/ o c v r ocset m aximum current l imit t hreshold r ocset open - 640 - mv zero c rossing c omparator o ffset v gnd - phase voltage - 3 0 3 mv protection v uv uvp threshold 65 70 75 % uvp debounce time - 30 - s uvp enable delay v out from 0% to uvp enable - 2.5 - ms v ovr ovp rising threshold v fb rising, lg fully turn on 120 125 130 % ovp propagation delay v fb rising - 2 - m s t otr otp rising threshold (note 4) - 150 - o c otp hyste r esis (note 4) - 25 - o c these specifications apply for t a = -40 o c to +85 o c, unless otherwise stated. all typical specifications t a = +25 o c, v cc = 12v n o t e 4 : g u a r a n t e e d b y d e s i g n .
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 6 a p w 8 7 2 7 / l t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s 0 5 10 15 20 25 30 150 200 250 300 350 400 converter input voltage , v in ( v ) s w i t c h i n g f r e q u e n c y , f s w ( k h z ) switching frequency vs . converter input voltage 0 . 001 0 . 01 0 . 1 1 10 100 0 50 100 150 200 250 300 350 switching frequency vs . converter output current s w i t c h i n g f r e q u e n c y , f s w ( k h z ) converter output current , i out ( a ) 3 6 9 12 15 18 21 24 1 . 030 1 . 040 1 . 050 1 . 060 1 . 070 1 . 080 load = 0 a load = 2 a converter output voltage vs . converter input voltage c o n v e r t e r o u t p u t v o l t a g e , v o u t ( v ) converter input voltage , v in ( v ) 0 . 79 0 . 795 0 . 8 0 . 805 0 . 81 - 20 0 20 40 60 80 100 r e f e r e n c e v o l t a g e ( v ) junction temperature ( ) o c reference voltage vs . junction temperature v cc = 12 v 120 s w i t c h i n g f r e q u e n c y ( k h z ) 250 260 270 280 290 300 310 320 330 340 350 switching frequency vs . junction temperature - 20 0 20 40 60 80 100 120 junction temperature ( o c ) 0 3 6 9 12 15 18 21 24 1 . 048 1 . 050 1 . 052 1 . 054 1 . 056 1 . 058 1 . 060 1 . 062 converter output voltage vs . converter output current c o n v e r t e r o u t p u t v o l t a g e , v o u t ( v ) converter output current , i out ( a ) vin = 12 v vin = 19 v
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 7 a p w 8 7 2 7 / l t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s 1 10 60 65 e f f i c i e n c y ( % ) 85 90 80 95 75 70 0 . 1 100 . 00 converter output current , i out ( a ) efficiency vs load current v out = 1 . 05 v h - side : sm 4370 x 1 l - side : sm 4373 x 1 vin = 19 v vin = 12 v
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 8 a p w 8 7 2 7 / l o p e r a t i n g w a v e f o r m s r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t . t h e t e s t c o n d i t i o n i s v i n = 1 9 v , t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d . ch 1 : v in , 10 v / div ch 2 : v out , 500 mv / div time : 2 ms / div power on 1 3 2 ch 3 : v phase , 10 v / div v in v out v phase ch 2 : v out , 500 mv / div ch 3 : v phase , 10 v / div time : 20 ms / div ch 1 : v in , 10 v / div power off 1 3 2 v in v out v phase r load = 20 [ enable ch 1 : v en , 5 v / div ch 2 : v out , 500 mv / div time : 1 ms / div ch 3 : v phase , 10 v / div v en v out v phase 1 3 2 shutdown ch 1 : v en , 50 v / div ch 2 : v out , 500 mv / div time : 1 ms / div ch 3 : v phase , 10 v / div v en v out v phase 1 3 2 r load = 20 [
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 9 a p w 8 7 2 7 / l o p e r a t i n g w a v e f o r m s r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t . t h e t e s t c o n d i t i o n i s v i n = 1 9 v , t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d . over - current protection 1 4 rocset = 7 . 5 k rds ( low - side )= 4 . 6 m [ ch 1 : v out , 10 v / div ch 3 : v lgate 10 v / div ch 3 : v ugate 20 v / div time : 2 ms / div 2 v out v lgate i l ch 3 : i l , 10 a / div 3 v ugate under - voltage protection 1 2 v sense v pok ch 1 : v sense , 500 mv / div ch 3 : v lgate 5 v / div ch 3 : v ugate 20 v / div time : 10 us / div ch 3 : v pok , 5 v / div 3 4 v lgate v ugate power ok v pok v out ch 1 : v out , 500 mv / div ch 2 : v pok , 5 v / div time : 20 ms / div 1 2 load transient i out v out 1 2 ch 1 : v out , 50 mv / div ch 2 : i out , 5 a / div time : 200 us / div
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 0 a p w 8 7 2 7 / l p i n d e s c r i p t i o n pin no. apw8727 apw8727l name function 1 1 boot supply input for t he ug ate driver a nd a n i nternal l evel - shift c ircuit. connect to an external capacitor to create a boosted voltage suitable to drive a logic - level n - channel mosfet. 2 2 phase junction p oint of t he h igh - side mosfet source, o utput f ilter i nductor a nd t he l ow - side mosfet drain. connect this pin to the source of the high - side mosfet. phase serves as the lower supply rail for the u g high - side gate driver. 3 3 ugate output of t he h igh - side m osfet d river. connect this pin to gate of the high - side mosfet. 4 4 lgate/ocset output of t he l ow - side mosfet d river a nd current - limit setting input. connect this pin to gate of the low - side mosfet. there is an internal source current 10 m a through a resis tor from lgate/ocset pin to gnd before power on. this action is used to monitor the voltage drop across the drain and source of the low - side mo sfet for current limit. 5 5 gnd signal g round for t he ic 6 6 vcc supply v oltage i nput p in for c ontrol c ircuitry . connect +5v~+12v from the vcc pin to the gnd. decoupling at least 1f of a mlcc capacitor from the vcc pin to the gnd. 7 7 en enable/shutdown pin . when en=1, enable t he pwm c ontroller , en=0, shutdown t he pwm c ontrolle r. when the en is floating, it will pull up to high logic automatically. 8 8 fb output v oltage f eedback p in. t his pin is connected to the resistive divider in remote side that set the desired output voltage. in apw8727l, the p ok , uvp, and ovp circuits detect this signal to report output vol tage status. 9 - vsense output voltage sense pin. it is used to sense the output voltage. the vsense pin is the input of over - voltage , under - voltage and pok detecting comparator. c onnect a resistor diver from output to gnd to set the ovp and uvp threshold s. vsense should not be left floating. - 9 nc no connect 10 10 pok power good output. po k i s a n o pen d rain o utput used to in dicate the status of the output voltage. connect the pok in to +5v~+12v through a pull - high resistor. exposed pad exposed pad gnd signal g round for t he ic
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 1 a p w 8 7 2 7 / l b l o c k d i a g r a m error comparator ov uv 70 % v ref 125 % v ref v ref por vcc en digital soft start p w m s i g n a l c o n t r o l l e r v cc boot ugate phase lgate thermal shutdown pok fault latch logic on - time generator v ref x 70 % v ref x 125 % z c phase v cc sample and hold v rocset to lgate 10 m a current limit v rocset sense low - side vsense / fb fb boot boot ok signal to sample and hold boot voltage sense circuit phase vin ok signal to sample and hold vin voltage sense circuit por por gnd
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 2 a p w 8 7 2 7 / l t y p i c a l a p p l i c a t i o n c i r c u i t c i r c u i t 1 c i r c u i t 2 phase vsense gnd vcc lgate / ocset apw 8727 ( tdfn 3 * 3 - 10 ) c in 10 m f x 3 l 1 1 . 0 h v in = 5 v ~ 19 v ugate vcc supply 5 v ~ 12 v boot 6 7 5 4 2 3 1 r vcc 2 r 2 c vcc 1 m f q 1 sm 4370 q 2 sm 4373 c boot 0 . 1 m f r ocset fb 8 pok 10 r pok 100 k w en enable signal 9 v out = 1 . 05 v on off 5 v / 12 v pull - high source c out 1 330 m f c out 2 330 m f r top 10 k w r top 10 k w r gnd 32 k w r gnd 32 k w phase nc gnd vcc lgate / ocset apw 8727 l ( tdfn 3 x 3 - 10 ) c in 10 f x 3 l 1 1 . 0 m h v in = 5 v ~ 19 v ugate vcc supply 5 v ~ 12 v boot 6 7 5 4 2 3 1 r vcc 2 r 2 c vcc 1 m f q 1 sm 4370 q 2 sm 4373 c boot 0 . 1 m f r ocset fb 8 pok 10 r pok 100 k w en enable signal 9 v out = 1 . 05 v on off 5 v / 12 v pull - high source c out 1 330 m f c out 2 330 m f r top 10 k w r gnd 32 k w
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 3 a p w 8 7 2 7 / l f u n c t i o n d e s c r i p t i o n constant-on-time pwm controller with input feed-for- ward the constant-on-time control architecture is a pseudofixed frequency with input voltage feed-forward. this architec- ture relies on the output filter capacitor?s effective series resistance (esr) to act as a current-sense resistor, so the output ripple voltage provides the pwm ramp signal. in pfm operation, the high-side switch on-time controlled by the on-time generator is determined solely by a oneshot whose pulse width is inversely proportional to input volt- age and directly proportional to output voltage. in pwm operation, the high-side switch on-time is determined by a switching frequency control circuit in the on-time gen- erator block. t h e s w i t c h i n g f r e q u e n c y c o n t r o l c i r c u i t s e n s e s t h e s w i t c h - i n g f r e q u e n c y o f t h e h i g h - s i d e s w i t c h a n d k e e p s r e g u l a t - i n g i t a t a c o n s t a n t f r e q u e n c y i n p w m m o d e . t h e d e s i g n i m p r o v e s t h e f r e q u e n c y v a r i a t i o n a n d i s m o r e o u t s t a n d - i n g t h a n a c o n v e n t i o n a l c o n s t a n t - o n - t i m e c o n t r o l l e r , w h i c h h a s l a r g e s w i t c h i n g f r e q u e n c y v a r i a t i o n o v e r i n p u t v o l t a g e , o u t p u t c u r r e n t , a n d t e m p e r a t u r e . b o t h i n p f m a n d p w m , t h e o n - t i m e g e n e r a t o r , w h i c h s e n s e s i n p u t v o l t a g e o n p h a s e p i n , p r o v i d e s v e r y f a s t o n - t i m e r e s p o n s e t o i n p u t l i n e t r a n s i e n t s . a n o t h e r o n e - s h o t s e t s a m i n i m u m o f f - t i m e ( 4 0 0 n s , t y p i c a l ) . t h e o n - t i m e o n e - s h o t i s t r i g g e r e d i f t h e e r r o r c o m - p a r a t o r i s h i g h , t h e l o w - s i d e s w i t c h c u r r e n t i s b e l o w t h e c u r r e n t - l i m i t t h r e s h o l d , a n d t h e m i n i m u m o f f - t i m e o n e s h o t h a s t i m e d o u t . pulse-frequency modulation (pfm) in pfm mode, an automatic switchover to pulse-fre- quency modulation (pfm) takes place at light loads. this switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current zero crossing. this mechanism causes the threshold between pfm and pwm operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the critical conduction point). the on-time of pfm is given by: w h e r e f s w i s t h e n o m i n a l s w i t c h i n g f r e q u e n c y o f t h e c o n - v e r t e r i n p w m m o d e . t h e l o a d c u r r e n t a t h a n d o f f f r o m p f m t o p w m m o d e i s g i v e n b y : v v f 1 t in out sw pfm - on = in out sw out in pfm - on out in pwm) to load(pfm v v x f 1 2l v v t l v v 2 1 i - = - = power-on-reset a power-on-reset (por) function is designed to prevent wrong logic controls when the vcc voltage is low. the por function continually monitors the bias supply volt- age on the vcc pin if at least one of the enable pins is set high. when the rising vcc voltage reaches the rising vcc por threshold (4.35v, typical), the por signal goes high and the chip initiates soft-start operations. there is a hysteresis to por voltage threshold ( a b o u t 3 0 0 m v t y p i c a l ) . when vcc voltage drops lower than 4.05v (typical), the por disables the chip. en pin control when v en is above the en high threshold (1.3v, minimum), the converter is enabled. when v en is below the en low threshold (0.85v, maximum), the chip is in the shutdown and only low leakage current is taken from vcc. when en pin is in float state, it will pull up high logic automatically. d i g i t a l s o f t - s t a r t t h e a p w 8 7 2 7 i n t e g r a t e s d i g i t a l s o f t - s t a r t c i r c u i t s t o r a m p u p t h e o u t p u t v o l t a g e o f t h e c o n v e r t e r t o t h e p r o g r a m m e d r e g u l a t i o n s e t p o i n t a t a p r e d i c t a b l e s l e w r a t e . t h e s l e w r a t e o f o u t p u t v o l t a g e i s i n t e r n a l l y c o n t r o l l e d t o l i m i t t h e i n r u s h c u r r e n t t h r o u g h t h e o u t p u t c a p a c i t o r s d u r i n g s o f t - s t a r t p r o c e s s . t h e f i g u r e 1 s h o w s s o f t - s t a r t s e q u e n c e . w h e n t h e e n p i n i s p u l l e d a b o v e t h e r i s i n g e n t h r e s h o l d v o l t a g e , t h e d e v i c e i n i t i a t e s a s o f t - s t a r t p r o c e s s t o r a m p u p t h e o u t p u t v o l t a g e . t h e s o f t - s t a r t i n t e r v a l i s 2 m s ( t y p i c a l ) a n d i n d e p e n d e n t o f t h e u g a t e s w i t c h i n g f r e q u e n c y .
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 4 a p w 8 7 2 7 / l f u n c t i o n d e s c r i p t i o n ( c o n t . ) f i g u r e 1 . s o f t - s t a r t s e q u e n c e during soft-start stage before the pgood pin is ready, the under-voltage protection is prohibited. the over-volt- age and current-limit protection functions are enabled. if the output capacitor has residue voltage before start-up, both low-side and high-side mosfets are in off-state until the internal digital soft-start voltage equals to the v fb voltage. this will ensure that the output voltage starts from its existing voltage level. power ok indicator the apw8727 features an open-drain pok pin to indi- cate output regulation status. in normal operation, when the output voltage rises 90% of its target value, the pok goes high. when the output voltage outruns 70% or 125% of the target voltage, pok signal will be pulled low immediately. in apw8727l, since the fb pin is used for both feedback and monitoring purposes, the output voltage deviation can be coupled directly to the fb pin by the capacitor in parallel with the voltage divider as shown in the typical applications. in order to prevent false pok from dropping, capacitors need to parallel at the output to confine the voltage deviation with severe load step transient. under-voltage protection (uvp) in the operational process, if a short-circuit occurs, the output voltage will drop quickly. when load current is big- ger than current-limit threshold value, the output voltage will fall out of the required regulation range. the under- voltage protection circuit continually monitors the vsense voltage after soft-start is completed. if a load step is strong enough to pull the output voltage lower than the under- voltage threshold, the under-voltage threshold is 70% of the nominal output voltage, the internal uvp delay counter starts to count. after 30 m s debounce time, the device turns off both high-side and low-side mosefet with latched. toggling enable pin to low or recycling vcc, will clear the latch and bring the chip back to operation. in apw8727l, the fb pin is also used for monitoring this function. o v e r - v o l t a g e p r o t e c t i o n ( o v p ) the over-voltage function monitors the output voltage by vsense pin. when the vsense voltage increases over 125% of the reference voltage due to the high-side mosfet failure or for other reasons, the over-voltage pro- tection comparator designed with a 2 m s noise filter will force the low-side mosfet gate driver fully turn on and latch high. this action actively pulls down the output voltage. this ovp scheme only clamps the voltage overshoot and does not invert the output voltage when otherwise acti- vated with a continuously high output from low-side mosfet driver. it?s a common problem for ovp schemes with a latch. once an over-voltage fault condition is set, it can only be reset by toggling en, vcc power-on-reset signal. in apw8727l, the fb pin is also used for monitor- ing this function. en v cc pok v v out t power ready detection & ocp setting soft start time = 2 ms pok enable delay time = 2 . 5 ms
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 5 a p w 8 7 2 7 / l f u n c t i o n d e s c r i p t i o n ( c o n t . ) over-temperature protection (otp) when the junction temperature increases above the ris- ing threshold temperature t otr , the ic will enter the over- temperature protection state that suspends the pwm, which forces the ugate and lgate gate drivers output low. the thermal sensor allows the converters to start a start-up process and regulate the output voltage again after the junction temperature cools by 25 o c. the otp is designed with a 25 o c hysteresis to lower the average t j during continuous thermal overload conditions, which in- creases lifetime of the apw8727. t h e o n - t i m e c o n t r o l a n d p w m s w i t c h i n g f r e q u e n c y t h e a p w 8 7 2 7 d o e s n o t u s e a c l o c k s i g n a l t o p r o d u c e p w m . t h e d e v i c e u s e s t h e c o n s t a n t - o n - t i m e c o n t r o l a r - c h i t e c t u r e t o p r o d u c e p s e u d o - f i x e d f r e q u e n c y w i t h i n p u t v o l t a g e f e e d - f o r w a r d . t h e o n - t i m e p u l s e w i d t h i s p r o p o r - t i o n a l t o o u t p u t v o l t a g e v o u t a n d i n v e r s e s p r o p o r t i o n a l t o i n p u t v o l t a g e v i n . when v in is 12v, v out is 1v, the switch- ing frequency is 300khz at pwm operation. apw8727 doesn?t have vin pin to calculate on-time pulse width. therefore, monitoring v phase voltage as input volt- age to calculate on-time when the high-side mosfet is turned on. o v e r - c u r r e n t p r o t e c t i o n o f t h e p w m c o n v e r t e r the over-current function protects the switching converter against over-current or short-circuit conditions. the con- troller senses the inductor current by detecting the drain- to-source voltage which is the product of the inductor?s current and the on-resistance of the low-side mosfet during it?s on-state. this method enhances the converter?s efficiency and reduces cost by eliminating a current sens- ing resistor required. a r e s i s t o r ( r o c s e t ) , c o n n e c t e d f r o m t h e l g a t e / o c s e t t o g n d , p r o g r a m s t h e o v e r - c u r r e n t t r i p l e v e l . b e f o r e t h e i c i n i t i a t e s a s o f t - s t a r t p r o c e s s , a n i n t e r n a l c u r r e n t s o u r c e , i o c s e t ( 1 0 m a t y p i c a l ) , f l o w i n g t h r o u g h t h e r o c s e t d e v e l o p s a v o l t a g e ( v r o c s e t ) a c r o s s t h e r o c s e t . t h e d e v i c e h o l d s v r o c s e t a n d s t o p s t h e c u r r e n t s o u r c e i o c s e t d u r i n g n o r m a l o p e r a t i o n . w h e n t h e v o l t a g e a c r o s s t h e l o w - s i d e m o s f e t e x c e e d s t h e v r o c set , the apw8727 shuts off the converter and then initiates a new soft-start process. after 4 over- current events are counted, the device turns off both high- side and low-side mosfets and the converter?s output is latched to be floating. the apw8727 has an internal ocp voltage, v ocp_max , and the value is 0.64v (typical). when the r ocset x i ocset ex- ceed 0.64v or the r ocset is floating or not connected, the v rocset will be the default value 0.64v. the over current threshold would be 0.64v across low-side mosfet. the threshold of the valley inductor current-limit is therefore given by: ) side low ( r r i i ) on ( ds ocset ocset limit - = for the over-current is never occurred in the normal oper- ating load range, the variation of all parameters in the above equation should be considered: - the r ds(on) of low-side mosfet is varied by tempera- ture and gate to source voltage. users should deter- mine the maximum r ds(on) by using the manufacturer?s datasheet. - the minimum i ocset (9.5 m a) and minimum r ocset should be used in the above equation. - note that the i limit is the current flow through the low- side mosfet; i limit must be greater than peak inductor current which is output current add the half of inductor ripple current. 2 i i i ) max ( out limit d + > where d i = output inductor ripple current - the overshoot and transient peak current also should be considered.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 6 a p w 8 7 2 7 / l a p p l i c a t i o n i n f o r m a t i o n where 0.8 is the reference voltage, r top is the resistor connected from converter?s output to fb, and r gnd is the resistor connected from fb to gnd. suggested r gnd is in the range from 1k to 20k w . to prevent stray pickup, locate resistors r top and r gnd close to apw8727. o u t p u t i n d u c t o r s e l e c t i o n t h e d u t y c y c l e ( d ) o f a b u c k c o n v e r t e r i s t h e f u n c t i o n o f t h e i n p u t v o l t a g e a n d o u t p u t v o l t a g e . o n c e a n o u t p u t v o l t a g e i s f i x e d , i t c a n b e w r i t t e n a s : in out v v d = in out sw out in ripple v v l f v - v i = o u t p u t c a p a c i t o r s e l e c t i o n the inductor value (l) determines the inductor ripple current, i ripple , and affects the load transient reponse. higher inductor value reduces the inductor?s ripple cur- rent and induces lower output ripple voltage. the ripple current and ripple voltage can be approximated by: esr ripple esr sw out ripple out c r i v f 8c i v = d = d o u t p u t v o l t a g e s e t t i n g the output voltage is adjustable from 0.8v to 5v with a resistor-divider connected with fb, gnd, and converter?s output. using 1% or better resistors for the resistor-di- vider is recommended. the output voltage is determined by: w h e r e f s w i s t h e s w i t c h i n g f r e q u e n c y o f t h e r e g u l a t o r . a l t h o u g h t h e i n d u c t o r v a l u e a n d f r e q u e n c y a r e i n c r e a s e d a n d t h e r i p p l e c u r r e n t a n d v o l t a g e a r e r e d u c e d , a t r a d e o f f e x i s t s b e t w e e n t h e i n d u c t o r ? s r i p p l e c u r r e n t a n d t h e r e g u - l a t o r l o a d t r a n s i e n t r e s p o n s e t i m e . a smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. increasing the switching frequency (f sw ) also reduces the ripple current and voltage, but it will increase the switching loss of the mosfets and the power dissipa- tion of the converter. the maximum ripple current occurs at the maximum input voltage. a good starting point is to choose the ripple current to be approximately 30% of the maximum output current. once the inductance value has been chosen, selecting an inductor which is capable of carrying the required peak current without going into saturation. in some types of inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it saturates. this results in a larger output ripple voltage. besides, the inductor needs to have low dcr to reduce the loss of efficiency. o u tp ut voltage ripple and the transient volta ge devia- tion are factors which have to be taken into con sider- ation when selecting an output capacitor. higher capaci- tor value and lower esr reduce the out put ripple and the load transient drop. therefore, selecting high per- formance low esr capacitors is recommended for switching regulator applications. in addition to h igh frequency noise related to mosfet turn-on and turn - o ff, the output voltage ripple includes the capaci tance voltage drop d v cout and esr voltage drop d v esr caused by the ac peak-to-peak inductor?s current. t h e s e t w o v o l t a g e s c a n b e r e p r e s e n t e d b y : these two components constitute a large portion of the total output voltage ripple. in some applications, multiple capacitors have to be paralleled to achieve the desired esr value. if the output of the converter has to support another load with high pulsating current, more capaci- tors are needed in order to reduce the equivalent esr and suppress the voltage ripple to a tolerable level. a small decoupling capacitor (1 m f) in parallel for bypass- ing the noise is also recommended, and the voltage rat- ing of the output capacitors are also must be considered. to support a load transient that is faster than the switch- ing frequency, more capacitors are needed for reducing the voltage excursion during load step change. another aspect of the capacitor selection is that the total ac cur- rent going through the capacitors has to be less than the rated rms current specified on the capacitors in order to prevent the capacitor from over-heating. ? ? ? ? ? + = gnd top out r r 1 0.8 v i n p u t c a p a c i t o r s e l e c t i o n t h e i n p u t c a p a c i t o r i s c h o s e n b a s e d o n t h e v o l t a g e r a t i n g a n d t h e r m s c u r r e n t r a t i n g . f o r r e l i a b l e o p e r a t i o n , s e l e c t - i n g t h e c a p a c i t o r v o l t a g e r a t i n g t o b e a t l e a s t 1 . 3 t i m e s
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 7 a p w 8 7 2 7 / l a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) i n p u t c a p a c i t o r s e l e c t i o n ( c o n t . ) m o s f e t s e l e c t i o n t h e a p p l i c a t i o n f o r a n o t e b o o k b a t t e r y w i t h a m a x i m u m v o l t a g e o f 2 4 v , a t l e a s t a m i n i m u m 3 0 v m o s f e t s s h o u l d b e u s e d . t h e d e s i g n h a s t o t r a d e o f f t h e g a t e c h a r g e w i t h t h e r ds(on) o f t h e m o s f e t : t h e s e l e c t i o n o f t h e n - c h a n n e l p o w e r m o s f e t s a r e d e t e r m i n e d b y t h e r ds(on) , r e v e r s i n g t r a n s f e r c a p a c i - t a n c e ( c r s s ) a n d m a x i m u m o u t p u t c u r r e n t r e q u i r e m e n t . t h e l o s s e s i n t h e m o s f e t s h a v e t w o c o m p o n e n t s : c o n d u c t i o n l o s s a n d t r a n s i t i o n l o s s . f o r t h e h i g h - s i d e a n d l o w - s i d e m o s f e t s , t h e l o s s e s a r e a p p r o x i m a t e l y g i v e n b y t h e f o l l o w i n g e q u a t i o n s : p high-side = i out 2 (1+ tc)(r ds(on) )d + (0.5)( i out )(v in )( t sw )f s w p low-side = i out 2 (1+ tc)(r ds(on) )(1-d) l a y o u t c o n s i d e r a t i o n i n a n y h i g h s w i t c h i n g f r e q u e n c y c o n v e r t e r , a c o r r e c t l a y o u t i s i m p o r t a n t t o e n s u r e p r o p e r o p e r a t i o n o f t h e r e g u l a t o r . w i t h p o w e r d e v i c e s s w i t c h i n g a t h i g h e r f r e q u e n c y , t h e r e s u l t i n g c u r r e n t t r a n s i e n t w i l l c a u s e v o l t a g e s p i k e a c r o s s t h e i n t e r c o n n e c t i n g i m p e d a n c e a n d p a r a s i t i c c i r c u i t e l e m e n t s . a s a n e x a m p l e , c o n s i d e r t h e t u r n - o f f t r a n s i t i o n o f t h e p w m m o s f e t . b e f o r e t u r n - o f f c o n d i t i o n , t h e m o s f e t i s c a r r y i n g t h e f u l l l o a d c u r r e n t . d u r i n g t u r n - o f f , c u r r e n t s t o p s f l o w i n g i n t h e m o s f e t a n d i s f r e e w h e e l i n g b y t h e l o w s i d e m o s f e t a n d p a r a s i t i c d i o d e . a n y p a r a s i t i c i n d u c t a n c e o f t h e c i r c u i t g e n e r a t e s a l a r g e v o l t a g e s p i k e d u r i n g t h e s w i t c h i n g i n t e r v a l . i n g e n e r a l , u s i n g s h o r t a n d w i d e p r i n t e d c i r c u i t t r a c e s s h o u l d m i n i m i z e i n t e r c o n n e c t - i n g i m p e d a n c e s a n d t h e m a g n i t u d e o f v o l t a g e s p i k e . b e s i d e s , s i g n a l a n d p o w e r g r o u n d s a r e t o b e k e p t s e p a - r a t i n g a n d f i n a l l y c o m b i n e d u s i n g g r o u n d p l a n e c o n s t r u c - t i o n o r s i n g l e p o i n t g r o u n d i n g . t h e b e s t t i e - p o i n t b e t w e e n the signal ground and the power ground is at the nega- tive side of the output capacitor on each channel, where there is less noise. noisy traces beneath the ic are not recommended. below is a checklist for your layout: f o r t h e l o w - s i d e m o s f e t , b e f o r e i t i s t u r n e d o n , t h e b o d y d i o d e h a s b e e n c o n d u c t i n g . t h e l o w - s i d e m o s f e t d r i v e r w i l l n o t c h a r g e t h e m i l l e r c a p a c i t o r o f t h i s m o s f e t . i n t h e t u r n i n g o f f p r o c e s s o f t h e l o w - s i d e m o s f e t , t h e l o a d c u r r e n t w i l l s h i f t t o t h e b o d y d i o d e f i r s t . t h e h i g h d v / d t o f t h e p h a s e n o d e v o l t a g e w i l l c h a r g e t h e m i l l e r c a p a c i - t o r t h r o u g h t h e l o w - s i d e m o s f e t d r i v e r s i n k i n g c u r r e n t p a t h . t h i s r e s u l t s i n m u c h l e s s s w i t c h i n g l o s s o f t h e l o w - s i d e m o s f e t s . t h e d u t y c y c l e i s o f t e n v e r y s m a l l i n h i g h b a t t e r y v o l t a g e a p p l i c a t i o n s , a n d t h e l o w - s i d e m o s f e t w i l l c o n d u c t m o s t o f t h e s w i t c h i n g c y c l e ; t h e r e f o r e , when using smaller r ds(on) of the low-side mosfet, the con- verter can reduce power loss. t h e g a t e c h a r g e f o r t h i s m o s f e t i s u s u a l l y t h e s e c o n d a r y c o n s i d e r a t i o n . t h e h i g h - s i d e m o s f e t d o e s n o t h a v e t h i s z e r o v o l t a g e s w i t c h - i n g c o n d i t i o n ; i n a d d i t i o n , b e c a u s e i t c o n d u c t s f o r l e s s t i m e c o m p a r e d t o t h e l o w - s i d e m o s f e t , t h e s w i t c h i n g l o s s t e n d s t o b e d o m i n a n t . p r i o r i t y s h o u l d b e g i v e n t o t h e m o s f e t s w i t h l e s s g a t e c h a r g e , s o t h a t b o t h t h e g a t e d r i v e r l o s s a n d s w i t c h i n g l o s s w i l l b e m i n i m i z e d . where i out is the load current tc is the temperature dependency of r ds(on) f sw is the switching frequency t sw is the switching interval d is the duty cycle note that both mosfets have conduction losses while the high- side mosfet includes an additional transi tion loss. t he switching interval , t sw , is the function of the reverse transfer capacitance c rss . the (1+tc) term is a factor in the temperature dependency of the r ds(on) and can be extracted from the ?r ds(on) vs. temperature? curve of the power mosfet. h i g h e r t h a n t h e m a x i m u m i n p u t v o l t a g e . t h e m a x i m u m r m s c u r r e n t r a t i n g r e q u i r e m e n t i s a p p r o x i m a t e l y i o u t / 2 , w h e r e i o u t i s t h e l o a d c u r r e n t . d u r i n g p o w e r - u p , t h e i n p u t c a p a c i t o r s h a v e t o h a n d l e g r e a t a m o u n t o f s u r g e c u r r e n t . f o r l o w - d u t y n o t e b o o k a p p l i a c t i o n s , c e r a m i c c a p a c i t o r i s r e c o m m e n d e d . t h e c a p a c i t o r s m u s t b e c o n n e c t e d b e - t w e e n t h e d r a i n o f h i g h - s i d e m o s f e t a n d t h e s o u r c e o f l o w - s i d e m o s f e t w i t h v e r y l o w - i m p e a d a n c e p c b l a y o u t . k e e p t h e s w i t c h i n g n o d e s ( u g a t e , l g a t e , b o o t , a n d p h a s e ) a w a y f r o m s e n s i t i v e s m a l l s i g n a l n o d e s s i n c e t h e s e n o d e s a r e f a s t m o v i n g s i g n a l s . t h e r e f o r e , k e e p t r a c e s t o t h e s e n o d e s a s s h o r t a s p o s s i b l e a n d t h e r e s h o u l d b e n o o t h e r w e a k s i g n a l t r a c e s i n p a r a l l e l w i t h t h e s e s t r a c e s o n a n y l a y e r .
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 8 a p w 8 7 2 7 / l a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) l a y o u t c o n s i d e r a t i o n ( c o n t . ) t h e s i g n a l s g o i n g t h r o u g h t h e s e s t r a c e s h a v e b o t h h i g h d v / d t a n d h i g h d i / d t w i t h h i g h p e a k c h a r g i n g a n d d i s c h a r g i n g c u r r e n t . t h e t r a c e s f r o m t h e g a t e d r i v e r s t o t h e m o s f e t s ( u g a t e a n d l g a t e ) s h o u l d b e s h o r t a n d w i d e . p l a c e t h e s o u r c e o f t h e h i g h - s i d e m o s f e t a n d t h e d r a i n o f t h e l o w - s i d e m o s f e t a s c l o s e a s p o s s i b l e . m i n i m i z i n g t h e i m p e d a n c e w i t h w i d e l a y o u t p l a n e b e - t w e e n t h e t w o p a d s r e d u c e s t h e v o l t a g e b o u n c e o f t h e n o d e . i n a d d i t i o n , t h e l a r g e l a y o u t p l a n e b e t w e e n t h e d r a i n o f t h e m o s f e t s ( v i n a n d p h a s e n o d e s ) c a n g e t b e t t e r h e a t s i n k i n g . the gnd is the current sensing circuit reference ground and also the power ground of the lgate low- side mosfet. on the other hand, the gnd trace should be a separate trace and independently go to the source of the low-side mosfet. besides, the cur- rent sense resistor should be close to ocset pin to avoid parasitic capacitor effect and noise coupling. d e c o u p l i n g c a p a c i t o r s , t h e r e s i s t o r - d i v i d e r , a n d b o o t c a p a c i t o r s h o u l d b e c l o s e t o t h e i r p i n s . ( f o r e x a m p l e , p l a c e t h e d e c o u p l i n g c e r a m i c c a p a c i t o r c l o s e t o t h e d r a i n o f t h e h i g h - s i d e m o s f e t a s c l o s e a s p o s s i b l e . ) t h e i n p u t b u l k c a p a c i t o r s s h o u l d b e c l o s e t o t h e d r a i n o f t h e h i g h - s i d e m o s f e t , a n d t h e o u t p u t b u l k c a p a c i - t o r s s h o u l d b e c l o s e t o t h e l o a d s . t h e i n p u t c a p a c i - t o r ? s g r o u n d s h o u l d b e c l o s e t o t h e g r o u n d s o f t h e o u t p u t c a p a c i t o r s a n d l o w - s i d e m o s f e t . locate the resistor-divider close to the fb pin to mini- mize the high impedance trace. in addition, fb pin traces can?t be close to the switching signal traces (ugate, lgate, boot, and phase). 0 . 3 0 mm 1 . 75 mm ground plane for thermalpad thermalvia diameter 12 mil x 5 0 . 27 5 mm 0 . 75 mm 0 . 50 mm tdfn 3 x 3 - 10 2 . 7 0 m m
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 9 a p w 8 7 2 7 / l p a c k a g e i n f o r m a t i o n t d f n 3 x 3 - 1 0 note : 1. followed from jedec mo-229 veed-5. aaa c nx a3 a1 b a k l e e 2 pin 1 corner d2 pin 1 e d s y m b o l min. max. 0.80 0.00 0.18 0.30 2.20 2.70 0.05 1.40 a a1 b d d2 e e2 e l millimeters a3 0.20 ref tdfn3x3-10 0.30 0.50 1.75 0.008 ref min. max. inches 0.031 0.000 0.007 0.012 0.087 0.106 0.055 0.012 0.020 0.70 0.069 0.028 0.002 0.50 bsc 0.016 bsc 0.20 0.008 k 2.90 3.10 0.114 0.122 2.90 3.10 0.114 0.122 0.08 0.003 aaa
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 0 a p w 8 7 2 7 / l application a h t1 c d d w e1 f 330.0 ? 2.00 50 min. 12.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 12.0 ? 0.30 1.75 ? 0.10 5.5 ? 0.05 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 tdfn3x3 - 10 4.0 ? 0.10 8.0 ? 0.10 2.0 ? 0.05 1.5+0.10 - 0.00 1.5 min. 0.6+0.00 - 0.40 3.30 ? 0.20 3.30 ? 0.20 1.30 ? 0.20 (mm) c a r r i e r t a p e & r e e l d i m e n s i o n s a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1 h t1 a d d e v i c e s p e r u n i t package type unit quantity tdfn3x3 - 10 tape & reel 3000
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 1 a p w 8 7 2 7 / l t a p i n g d i r e c t i o n i n f o r m a t i o n t d f n 3 x 3 - 1 0 user direction of feed c l a s s i f i c a t i o n p r o f i l e
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 2 a p w 8 7 2 7 / l c l a s s i f i c a t i o n r e f l o w p r o f i l e s profile feature sn - pb eutectic assembly pb - free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) ( t s ) 100 c 150 c 60 - 120 seconds 150 c 200 c 60 - 1 2 0 seconds average ramp - up rate (t smax to t p ) 3 c/second ma x. 3 c/second max. liquidous temperature ( t l ) time at l iquidous (t l ) 183 c 60 - 150 seconds 217 c 60 - 150 seconds peak package body temperature (t p ) * see classification temp in table 1 see classification temp in table 2 time (t p ) ** within 5 c of the spe cified c lassification t emperature ( t c ) 2 0 ** seconds 3 0 ** seconds average r amp - down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to p eak t emperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. table 2. pb - free process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350 - 2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm ? 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c table 1. snpb eutectic process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 22 0 c 3 2.5 mm 220 c 220 c test item method description solderability jesd - 22, b102 5 sec, 245 c holt jesd - 22, a108 1000 hrs, bias @ t j =125 c pct jesd - 22, a102 168 hrs, 100 % rh, 2atm , 121 c tct jesd - 22, a104 500 cycles, - 65 c~150 c hbm mil - std - 883 - 3015.7 vhbm ? 2kv mm jesd - 22, a1 15 vmm ? 200v latch - up jesd 78 10ms, 1 tr ? 100ma r e l i a b i l i t y t e s t p r o g r a m
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a p r . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 3 a p w 8 7 2 7 / l c u s t o m e r s e r v i c e a n p e c e l e c t r o n i c s c o r p . head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 t a i p e i b r a n c h : 2 f , n o . 1 1 , l a n e 2 1 8 , s e c 2 j h o n g s i n g r d . , s i n d i a n c i t y , t a i p e i c o u n t y 2 3 1 4 6 , t a i w a n t e l : 8 8 6 - 2 - 2 9 1 0 - 3 8 3 8 f a x : 8 8 6 - 2 - 2 9 1 7 - 3 8 3 8

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