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document no. e0300e20 (ver. 2.0) date published december 2002 (k) japan url: http:// www.elpida.com ? elpida memory, inc. 2002 preliminary data sheet 256m bits ddr mobile ram edk2516cbbh (16m words 16 bits) description the edk2516cb is a 256m bits ddr mobile ram organized as 4,194,304 words 16 bits 4 banks. the ddr mobile ram achieved low power consumption and high-speed data transfer using the 2bits prefetch- pipeline architecture. command and address inputs are synchronized with the positive edge of the clock. data inputs and outputs are synchronized with both edges of dqs(data strobe). dll is not implemented. this product is packaged in 60-ball fbga. features ? low voltage power supply ? vdd: 1.8v 0.15v ? vddq: 1.8v 0.15v ? wide temperature range ( ? 25 c to 85 c) ? programmable partial self refresh ? programmable driver strength ? programmable temperature compensated self refresh ? deep power down mode ? small package (60-ball fbga) ? fbga package is lead free solder (sn-ag-cu) ? data rate: 200mbps/io(max) ? doule data rate architecture: two data transfers per one clock cycle ? bi-directional, data strobe (dqs) is transmitted /received with data, to be used in capturing data at the receiver. ? 1.8v lvcmos interface ? command and address signals refer to a positive clock edge ? quad internal banks controlled by ba0 and ba1 ? data mask (dm) for write data ? wrap sequence = sequential/ interleave ? programmable burst length (bl) = 2, 4, 8 ? automatic precharge and controlled precharge ? auto refresh and self refresh ? 8,192 refresh cycles/64ms (7.8 s maximum average periodic refresh interval) ? burst termination by burst stop command and precharge command pin configurations /xxx indicates active low si gnal. a b c d e f g h j 123 789 (top view) k vss dq15 vssq vddq dq0 vdd dq14 dq13 vddq vssq dq2 dq1 dq12 dq11 vssq vddq dq4 dq3 dq10 dq9 vddq vssq dq6 dq5 dq8 vssq vddq ldqs dq7 udqs nc udm vdd ldm nc vss clk cke /cas /ras /we /clk a12 a11 a9 ba0 ba1 /cs a8 a7 a6 a0 a1 a10 vss a5 a4 a3 a2 vdd a0 to a12 ba0, ba1 dq0 to dq15 udqs, ldqs /cs /ras /cas /we udm, ldm ck /ck cke vdd vss vddq vssq nc address input bank select address data-input/output input and output data strobe chip select row address strobe command column address strobe command write enable write data mask clock input differential clock input clock enable power for internal circuit ground for internal circuit power for dq circuit ground for dq circuit no connection 60-ball fbga
edk2516cbbh preliminary data sheet e0300e20 (ver. 2.0) 2 ordering information part number organization (words bits) internal banks clock frequency mhz (max.) /cas latency package edk2516cbbh-15-e edk2516cbbh-10-e 16m 16 4 66 100 2 3 60-ball fbga part number lead free elpida memory density / bank 25: 256m /4 banks bit organization 16: x16 voltage, interface c: vdd = 1.8v, vddq = 1.8v, lvcmos die rev. package bh: fbga speed 10: 100mhz/cl3 15: 66mhz/cl2 product code k: ddr mobile ram type d: monolithic device e d k 25 16 c b bh - 10 - e
edk2516cbbh preliminary data sheet e0300e20 (ver. 2.0) 3 contents description .................................................................................................................... ................................ 1 features ....................................................................................................................... ................................. 1 pin configurations ............................................................................................................. ............................ 1 ordering information ........................................................................................................... .......................... 3 electrical specifications...................................................................................................... ........................... 5 block diagram .................................................................................................................. ........................... 11 pin function ................................................................................................................... ............................. 12 command operation .............................................................................................................. ..................... 14 simplified state diagram....................................................................................................... ...................... 21 operation of the ddr mobile ram ................................................................................................ ............. 22 initialization................................................................................................................. ................................. 22 timing waveforms ............................................................................................................... ....................... 26 package drawing ................................................................................................................ ........................ 27 recommended soldering conditions............................................................................................... ........... 28
edk2516cbbh preliminary data sheet e0300e20 (ver. 2.0) 4 electrical specifications ? all voltages are referenced to vss (gnd). ? after power up, wait more than 200 s and then, execute power on sequence and cbr (auto) refresh before proper device operation is achieved. absolute maximum ratings parameter symbol rating unit note voltage on any pin relative to vss vt C1.0 to +2.6 v supply voltage relative to vss vdd C1.0 to +2.6 v short circuit output current ios 50 ma power dissipation pd 1.0 w operating temperature ta -25 to +85 c storage temperature tstg C55 to +125 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended dc operating conditions (ta = -25 to 85 c) parameter symbol min typ max unit notes supply voltage vdd, vddq 1.65 1.8 1.95 v 1 vss, vssq 0 0 0 v input high voltage vih (dc) 0.8 vddq vddq + 0.3 v 2 input low voltage vil (dc) C0.3 0.3 v 3 input voltage level, ck and /ck inputs vin (dc) C0.3 vddq + 0.3 v input differential cross point voltage, ck and /ck inputs vix (dc) 0.5 vddq ? 0.2v 0.5 vddq 0.5 vddq + 0.2v v input differential voltage, ck and /ck inputs vid (dc) 1.0 vddq + 0.6 v notes: 1. vddq must be lower than or equal to vdd. 2. vih is allowed to exceed vdd up to 2.6v for the period shorter than or equal to 5ns. 3. vil is allowed to outreach below vss down to C1.0v for the period shorter than or equal to 5ns.
edk2516cbbh preliminary data sheet e0300e20 (ver. 2.0) 5 dc characteristics 1 (ta = C25 to +85 c, vdd, vddq = 1.8v 0.15v, vss, vssq = 0v) parameter grade -10 -15 /cas latency symbol max. max. unit test condition notes operating current (cl = 2) idd1 45 ma 1 (cl = 3) idd1 45 ma burst length = 1 trc trc min., io = 0ma, one bank active standby current in power down idd2p tbd tbd ma cke vil max., tck = 15ns standby current in power down (input signal stable) idd2ps tbd tbd ma cke vil max., tck = standby current in non power down idd2n 3.0 3.0 ma cke vih min., tck = 15ns, /cs vih min., input signals are changed one time during 30ns. standby current in non power down (input signal stable) idd2ns 2.0 2.0 ma cke vih min., tck = , input signals are stable. active standby current in power down idd3p tbd tbd ma cke vil max., tck = 15ns active standby current in power down (input signal stable) idd3ps tbd tbd ma cke vil max., tck = active standby current in non power down idd3n tbd tbd ma cke vih min., tck = 15 ns, /cs vih min., input signals are changed one time during 30ns. active standby current in non power down (input signal stable) idd3ns tbd tbd ma cke vih min., tck = , input signals are stable. burst operating current (cl = 2) idd4 30 ma tck tck min., iout = 0ma, all banks active 2 (cl = 3) idd4 45 ma refresh current (cl = 2) idd5 50 50 ma trc trc min. 3 self refresh current pasr="000" (full) idd6 150 150 a tcsr="00" (ts* 4 70c) pasr="001" (2bk) tbd tbd a cke 0.2v pasr="010" (1bk) tbd tbd a pasr="101" (1/2 bk) tbd tbd a pasr="110" (1/4 bk) tbd tbd a pasr="000" (full) idd6 100 100 a tcsr="01" (ts* 4 45c) pasr="001" (2bk) tbd tbd a cke 0.2v pasr="010" (1bk) tbd tbd a pasr="101" (1/2 bk) tbd tbd a pasr="110" (1/4 bk) tbd tbd a pasr="000" (full) idd6 250 250 a tcsr="11" (ts* 4 85c) pasr="001" (2bk) tbd tbd a cke 0.2v pasr="010" (1bk) tbd tbd a pasr="101" (1/2 bk) tbd tbd a pasr="110" (1/4 bk) tbd tbd a standby current in deep power down mode idd7 10 10 a cke 0.2v
edk2516cbbh preliminary data sheet e0300e20 (ver. 2.0) 6 notes: 1. idd1 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, idd1 is measured condition that addresses are changed only one time during tck (min.). 2. idd4 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, idd4 is measured condition that addresses are changed only one time during tck (min.). 3. idd5 is measured on condition that addresses are changed only one time during tck (min.). 4. ts is surface temperature. dc characteristics 2 (ta = -25 to +85 c, vdd, vddq = 1.8v 0.15v, vss, vssq = 0v) parameter symbol min. max. unit test condition notes input leakage current ili C1.0 1.0 a 0 vin vddq output leakage current ilo C1.5 1.5 a 0 vout vddq, dq = disable output high voltage voh vddq C 0.2 v ioh = ? 0.1ma output low voltage vol 0.2 v iol = 0.1 ma pin capacitance (ta = +25c, vdd, vddq = 2.5v 0.2v) parameter symbol pins min. typ max. unit notes input capacitance ci1 ck, /ck 2.0 3.0 pf 1 ci2 all other input pins 2.0 3.0 pf 1 data input/output capacitance ci/o dq, dm, dqs 4.0 5 pf 1, 2, notes: 1. these parameters are measured on conditions: f = 100mhz, vout = vddq/2, ? vout = 0.2v, ta = +25 c. 2. dout circuits are disabled.
edk2516cbbh preliminary data sheet e0300e20 (ver. 2.0) 7 ac characteristics (ta = -25 to +85 c, vdd, vddq = 1.8v 0.15v, vss, vssq = 0v) -10 -15 parameter symbol min. max. min. max unit notes clock cycle time (cl =2) tck 15 ns (cl =3) tck 10 ns ck high-level width tch 0.45 0.55 0.45 0.55 tck ck low-level width tcl 0.45 0.55 0.45 0.55 tck dq output access time from ck, /ck tac 2.0 7.0 2.0 9.0 ns 2 dqs output access time from ck, /ck tdqsck 2.0 7.0 2.0 9.0 ns 2 dq-out high-impedance time from ck, /ck thz 2.0 7.0 2.0 9.0 ns 5 dq-out low-impedance time from ck, /ck tlz 2.0 7.0 2.0 9.0 ns 6 dqs-out high-impedance time from ck, /ck tdqshz 2.0 7.0 2.0 9.0 ns 5 dqs-out low-impedance time from ck, /ck tdqslz 2.0 7.0 2.0 9.0 ns 6 dqs to dq skew tdqsq 0.75 1.0 ns 3 dout valid window tdv 3.0 4.0 4 dq and dm input setup time tds 1.0 1.5 ns 3 dq and dm input hold time tdh 1.0 1.5 ns 3 write preamble setup time twpres 0 0 ns write preamble twpre 0.25 0.25 tck write postamble twpst 0.4 0.6 0.4 0.6 tck 7 write command to first dqs latching transition tdqss 0.75 1.25 0.75 1.25 tck dqs falling edge to ck setup time tdss 0.2 0.2 tck dqs falling edge hold time from ck tdsh 0.2 0.2 tck dqs input high pulse width tdqsh 0.35 0.35 tck dqs input low pulse width tdqsl 0.35 0.35 tck address and control input setup time tis 1.5 2.0 ns 3 address and control input hold time tih 1.5 2.0 ns 3 mode register set command cycle time tmrd 2 2 tck active to precharge command period tras 60 120000 60 120000 ns active to active/auto refresh command period trc 90 90 ns auto refresh to active/auto refresh command period trfc 110 110 ns active to read/write delay trcd 30 30 ns precharge to active command period trp 30 30 ns active to active command period trrd 20 20 ns write recovery time twr 20 30 ns self refresh exit period tsrex 120 120 ns average periodic refresh interval tref 7.8 7.8 s
edk2516cbbh preliminary data sheet e0300e20 (ver. 2.0) 8 notes: 1. on all ac measurements, we assume the test conditions shown in the next page. full driver strength is assumed for the output load seen in test conditions, that is both a6 and a5 of emrs is set to be l. 2. this parameter defines the signal transition delay from the cross point of ck and /ck. the signal transition is defined to occur when the signal level crossing vref. 3. the timing reference level is vref. 4. output valid window is defined to be the period between two successive transition of data out signals. the signal transition is defined to occur when the signal level crossing vref. 5. thz, tdqshz is defined as dout transition delay from low-z to high-z at the end of read burst operation. the timing reference is cross point of ck and /ck. this parameter is not referred to a specific dout voltage level, but specify when the device output stops driving. 6. tlz, tdqslz is defined as dout transition delay from high-z to low-z at the beginning of read operation. this parameter is not referred to a specific dout voltage level, but specify when the device output begins driving. 7. the transition from low-z to high-z is defined to occur when the device output stops driving. a specific reference voltage to judge this transition is not given. test conditions parameter symbol value unit input reference voltage vref 0.9 v input high voltage vih (ac) 1.6 v input low voltage vil (ac) 0.2 v input differential voltage, ck and /ck inputs vid (ac) 1.4 v input differential cross point voltage, ck and /ck inputs vix (ac) 0.9 v input signal slew rate slew 1 v/ns test condition (wave form and timing reference) output load q1 q2 ck /ck vref ( =0.9v ) td q lz tac dqout (dqsout) vref ( =0.9v ) vix tck tch tcl vih ( =1.6v ) vil ( =0.2v ) t t ) v - (v rate slew il ih = z0 = 50 ? cl = 30 pf
edk2516cbbh preliminary data sheet e0300e20 (ver. 2.0) 9 timing parameter measured in clock cycle number of clock cycle tck 10ns 15ns parameter symbol min. max. min. max. write to pre-charge command delay (same bank) twpd 3 + bl/2 3 + bl/2 read to pre-charge command delay (same bank) trpd bl/2 bl/2 write to read command delay (to input all data) twrd 2 + bl/2 2 + bl/2 burst stop command to write command delay (cl = 2) tbstw 2 (cl = 3) tbstw 3 burst stop command to dq high-z (cl = 2) tbstz 2 (cl = 3) tbstz 3 read command to write command delay (to output all data) (cl = 2) trwd 2 + bl/2 (cl = 3) trwd 3 + bl/2 pre-charge command to high-z (cl = 2) thzp 2 (cl = 3) thzp 3 write command to data in latency twcd 1 1 write recovery twr 2 2 dm to data in latency tdmd 0 0 mode register set command cycle time tmrd 2 2 self refresh exit to non-column command tsnr 12 8 auto refersh period trfc 11 8 power down entry tpden 1 1 power down exit to command input tpdex 1 1
edk2516cbbh preliminary data sheet e0300e20 (ver. 2.0) 10 block diagram a0 to a12, ba0, ba1 /cs /ras /cas /we command decoder input & output buffer latch circuit data control circuit column decoder row decoder memory cell array bank 0 sense amp. bank 1 bank 2 bank 3 control logic column address buffer and burst counter row address buffer and refresh counter mode register clock generator dq ck /ck cke dqs dm dll ck, /ck
edk2516cbbh preliminary data sheet e0300e20 (ver. 2.0) 11 pin function ck, /ck (input pins) the ck and the /ck are the master clock inputs. all inputs except dms, dqss and dqs are referred to the cross point of the ck rising edge and the /ck falling edge. when a read operation, dqss and dqs are referred to the cross point of the ck and the /ck. when a write operation, dms and dqs are referred to the cross point of the dqs and the vref level. dqss for write operation are referred to the cross point of the ck and the /ck. ck is the master clock input to this pin. the other input signals are referred at ck rising edge. /cs (input pin) when /cs is low, commands and data can be input. when /cs is high, all inputs are ignored. however, internal operations (bank active, burst operations, etc.) are held. /ras, /cas, and /we (input pins) these pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. see "command operation". a0 toa12 (input pins) row address (ax0 to ax12) is determined by the a0 to the a12 level at the cross point of the ck rising edge and the /ck falling edge in a bank active command cycle. column address (see address pins table) is loaded via the a0 to the a8 at the cross point of the ck rising edge and the /ck falling edge in a read or a write command cycle. this column address becomes the starting address of a burst operation. [address pins table] address (a0 to a12) part number row address column address edk2516cbbh ax0 to ax12 ay0 to ay8 a10 (ap) (input pin) a10 defines the precharge mode when a precharge command, a read command or a write command is issued. if a10 = high when a precharge command is issued, all banks are precharged. if a10 = low when a precharge command is issued, only the bank that is selected by ba1/ba0 is precharged. if a10 = high when read or write command, auto-precharge function is enabled. while a10 = low, auto-precharge function is disabled. ba0 and ba1 (input pins) ba0, ba1 are bank select signals (ba). the memory array is divided into bank 0, bank 1, bank 2 and bank 3. (see bank select signal table) [bank select signal table] ba0 ba1 bank 0 l l bank 1 h l bank 2 l h bank 3 h h remark: h: vih. l: vil.
edk2516cbbh preliminary data sheet e0300e20 (ver. 2.0) 12 cke (input pin) this pin determines whether or not the next ck is valid. if cke is high, the next ck rising edge is valid. if cke is low. cke controls power down and self-refresh. the power down and the self-refresh commands are entered when the cke is driven low and exited when it resumes to high. cke must be maintained high throughout read or write access. the cke level must be kept for 1 ck cycle at least, that is, if cke changes at the cross point of the ck rising edge and the /ck falling edge with proper setup time tis, by the next ck rising edge cke level must be kept with proper hold time tih. dq0 todq15 (input/output pins) data is input to and output from these pins. udqs, ldqs (input and output pin): dqs provides the read data strobes (as output) and the write data strobes (as input). ldqs is the strobe signals specific for the lower dq signls (dq0-dq7). udqs is the strobe signals specific for the upper dq signls (dq8-dq15). udm, ldm (input pin) dm are the reference signals of the data input mask function. dms are sampled at the cross point of dqs and vref. ldm controls the lower dq signals (dq0-dq7). udm controls the upper dq signals (dq7-dq15). vdd, vss, vddq, vssq (power supply) vdd and vss are power supply pins for internal circuits. vddq and vssq are power supply pins for the output buffers.
edk2516cbbh preliminary data sheet e0300e20 (ver. 2.0) 13 command operation command truth table ddr mobile ram recognize the following commands specified by the /cs, /ras, /cas, /we and address pins. all other combinations than those in the table below are illegal. cke command symbol n C 1 n /cs /ras /cas /we ba1 ba0 ap address ignore command desl h h h no operation nop h h l h h h burst stop in read command bst h h l h h l column address and read command read h h l h l h v v l v read with auto-precharge reada h h l h l h v v h v column address and write command writ h h l h l l v v l v write with auto-precharge writa h h l h l l v v h v row address strobe and bank active act h h l l h h v v v v precharge select bank pre h h l l h l v v l precharge all bank pall h h l l h l h refresh ref h h l l l h self h l l l l h mode register set mrs h h l l l l l l l v emrs h h l l l l l h l v remark: h: vih. l: vil. : vih or vil v: valid address input note: the cke level must be kept for 1 ck cycle at least. ignore command [desl] when /cs is high at the cross point of the ck rising edge and the vref level, every input are neglected and internal status is held. no operation [nop] as long as this command is input at the cross point of the ck rising edge and the vref level, address and data input are neglected and internal status is held. burst stop in read operation [bst] this command stops a burst read operation, which is not applicable for a burst write operation. column address strobe and read command [read] this command starts a read operation. the start address of the burst read is determined by the column address (see address pins table in pin function) and the bank select address. after the completion of the read operation, the output buffer becomes high-z. read with auto-precharge [reada] this command starts a read operation. after completion of the read operation, precharge is automatically executed. column address strobe and write command [writ] this command starts a write operation. the start address of the burst write is determined by the column address (see address pins table in pin function) and the bank select address. write with auto-precharge [writa] this command starts a write operation. after completion of the write operation, precharge is automatically executed.
edk2516cbbh preliminary data sheet e0300e20 (ver. 2.0) 14 row address strobe and bank activate [act] this command activates the bank that is selected by ba0, ba1 and determines the row address (ax0 to ax12). (see bank select signal table) precharge selected bank [pre] this command starts precharge operation for the bank selected by ba0, ba1. (see bank select signal table) [bank select signal table] ba0 ba1 bank 0 l l bank 1 h l bank 2 l h bank 3 h h remark: h: vih. l: vil. precharge all banks [pall] this command starts a precharge operation for all banks. refresh [ref/self] this command starts a refresh operation. there are two types of refresh operation, one is auto-refresh, and another is self-refresh. for details, refer to the cke truth table section. mode register set/extended mode register set [mrs/emrs] the ddr mobile ram has the two mode registers, the mode register and the extended mode register, to defines how it works. the both mode registers are set through the address pins (the a0 to the a12, ba0 to ba1) in the mode register set cycle. for details, refer to "mode register and extended mode register set".
edk2516cbbh preliminary data sheet e0300e20 (ver. 2.0) 15 function truth table the following tables show the operations that are performed when each command is issued in each state of the ddr mobile sdram. function truth table (1) current state /cs /ras /cas /we address command operation next state precharging* 1 h desl nop ldle l h h h nop nop ldle l h h l bst illegal* 11 l h l h ba, ca, a10 read/reada illegal* 11 l h l l ba, ca, a10 writ/writa illegal* 11 l l h h ba, ra act illegal* 11 l l h l ba, a10 pre, pall nop ldle l l l illegal idle* 2 h desl nop ldle l h h h nop nop ldle l h h l bst illegal* 11 l h l h ba, ca, a10 read/reada illegal* 11 l h l l ba, ca, a10 writ/writa illegal* 11 l l h h ba, ra act activating active l l h l ba, a10 pre, pall nop ldle l l l h ref, self refresh/ self refresh* 12 ldle/ self refresh l l l l mode mrs mode register set* 12 ldle refresh (auto-refresh)* 3 h desl nop ldle l h h h nop nop ldle h h h l bst illegal l h l illegal l l illegal
edk2516cbbh preliminary data sheet e0300e20 (ver. 2.0) 16 function truth table (2) current state /cs /ras /cas /we address command operation next state activating* 4 h desl nop active l h h h nop nop active l h h l bst illegal* 11 l h l h ba, ca, a10 read/reada illegal* 11 l h l l ba, ca, a10 writ/writa illegal* 11 l l h h ba, ra act illegal* 11 l l h l ba, a10 pre, pall illegal* 11 l l l illegal active* 5 h desl nop active l h h h nop nop active l h h l bst illegal active l h l h ba, ca, a10 read/reada starting read operation read/reada l h l l ba, ca, a10 writ/writa starting write operation write recovering/ precharging l l h h ba, ra act illegal* 11 l l h l ba, a10 pre, pall pre-charge idle l l l illegal read* 6 h desl nop active l h h h nop nop active l h h l bst bst active l h l h ba, ca, a10 read/reada interrupting burst read operation to start new read active l h l l ba, ca, a10 writ/writa illegal* 13 l l h h ba, ra act illegal* 11 l l h l ba, a10 pre, pall interrupting burst read operation to start pre-charge precharging l l l illegal
edk2516cbbh preliminary data sheet e0300e20 (ver. 2.0) 17 function truth table (3) current state /cs /ras /cas /we address command operation next state read with auto-pre- charge* 7 h desl nop precharging l h h h nop nop precharging l h h l bst illegal l h l h ba, ca, a10 read/reada illegal l h l l ba, ca, a10 writ/writa illegal l l h h ba, ra act illegal* 11 l l h l ba, a10 pre, pall illegal* 11 l l l illegal write* 8 h desl nop write recovering l h h h nop nop write recovering l h h l bst illegal l h l h ba, ca, a10 read/reada interrupting burst write operation to start read operation. read/reada l h l l ba, ca, a10 writ/writa interrupting burst write operation to start new write operation. write/writea l l h h ba, ra act illegal* 11 l l h l ba, a10 pre, pall interrupting write operation to start pre- charge. idle l l l illegal write recovering* 9 h desl nop active l h h h nop nop active l h h l bst illegal l h l h ba, ca, a10 read/reada starting read operation. read/reada l h l l ba, ca, a10 writ/writa starting new write operation. write/writea l l h h ba, ra act illegal* 11 l l h l ba, a10 pre/pall illegal* 11 l l l illegal
edk2516cbbh preliminary data sheet e0300e20 (ver. 2.0) 18 function truth table (4) current state /cs /ras /cas /we address command operation next state write with auto- pre-charge* 10 h desl nop precharging l h h h nop nop precharging l h h l bst illegal l h l h ba, ca, a10 read/reada illegal l h l l ba, ca, a10 writ/writ a illegal l l h h ba, ra act illegal* 11 l l h l ba, a10 pre, pall illegal* 11 l l l illegal remark: h: vih. l: vil. : vih or vil notes: 1. the ddr mobile ram is in "precharging" state for trp after precharge command is issued. 2. the ddr mobile ram reaches "idle" state trp after precharge command is issued. 3. the ddr mobile ram is in "refresh" state for trc after auto-refresh command is issued. 4. the ddr mobile ram is in "activating" state for trcd after act command is issued. 5. the ddr mobile ram is in "active" state after "activating" is completed. 6. the ddr mobile ram is in "read" state until burst data have been output and dq output circuits are turned off. 7. the ddr mobile ram is in "read with auto-precharge" from reada command until burst data has been output and dq output circuits are turned off. 8. the ddr mobile ram is in "write" state from writ command to the last burst data are input. 9. the ddr mobile ram is in "write recovering" for twr after the last data are input. 10. the ddr miobile ram is in "write with auto-precharge" until twr after the last data has been input. 11. this command may be issued for other banks, depending on the state of the banks. 12. all banks must be in "idle". 13. before executing a write command to stop the preceding burst read operation, bst command must be issued.
edk2516cbbh preliminary data sheet e0300e20 (ver. 2.0) 19 cke truth table cke current state command n C 1 n /cs /ras /cas /we address notes idle auto-refresh command (ref) h h l l l h 2 idle self-refresh entry (self) h l l l l h 2 h l l h h h idle power down entry (pden) h l h idle deep power down entry(dpwde) h l l h h l l h l h h h self refresh self refresh exit (selfx) l h h l h l h h h power down power down exit (pdex) l h h deep power down power down exit (dpdex) l h notes: 1. h : vih . l : vil : vih or vil . 2. all the banks must be in idle before executing this command. 3. the cke level must be kept for 1 clk cycle at least. auto-refresh command [ref] this command executes auto-refresh. the banks and the row addresses to be refreshed are internally determined by the internal refresh controller. the average refresh cycle is 7.8 s. the output buffer becomes high-z after auto- refresh start. precharge has been completed automatically after the auto-refresh. the act or mrs command can be issued trfc after the last auto-refresh command. self-refresh entry [self] this command starts self-refresh. the self-refresh operation continues as long as cke is held low. during the self- refresh operation, all row addresses are repeated refreshing by the internal refresh controller. a self-refresh is terminated by a self-refresh exit command. power down mode entry [pden] tpden (= 1 cycle) after the cycle when [pden] is issued. the ddr mobile ram enters into power-down mode. in power down mode, power consumption is suppressed by deactivating the input initial circuit. power down mode continues while cke is held low. no internal refresh operation occurs during the power down mode. [pden] do not disable dll. deep power down entry [dpden] after the command execution, deep power down mode continues while cke remains low. before executing deep power down, all banks must be precharged or in idle state. self-refresh exit [selfx] this command is executed to exit from self-refresh mode. trc + 3tck after [selfx], non-read commands can be executed power down exit [pdex] the ddr mobile sdram can exit from power down mode tpdex (1 cycle min.) after the cycle when [pdex] is issued. deep power down exit [dpdex] cke goes high in the deep power down mode, the ddr mobile ram exits the deep power down mode.
edk2516cbbh preliminary data sheet e0300e20 (ver. 2.0) 20 simplified state diagram 7* 7* j qr j[ [r qr [ =]; =]; j[rijrt j[rijrt q7; z[] [?C 7* 7* ]?C ]?Cr xh z [ ] z [ ] 7=[riqt [ [ q7;x> ] [ j h q j h j z[] [qh [qhq [x; [x;q j[ [ qr zrr [ r h j h hjh hjhr
edk2516cbbh preliminary data sheet e0300e20 (ver. 2.0) 21 operation of the ddr mobile ram initialization the synchronous dram is initialized in the power-on sequence according to the following. (1) to stabilize internal circuits, when power is applied, a 200 s or longer pause must precede any signal toggling. (2) after the pause, all banks must be precharged using the precharge command (the precharge all banks command is convenient). (3) once the precharge is completed and the minimum trp is satisfied, two or more auto refresh must be performed. (4) both the mode register and the extended mode register must be programmed. after the mode register set cycle or the extended mode register set cycle, trsc (2 clk minimum) pause must be satisfied. remarks: 1 the sequence of auto refresh, mode register programming and extended mode register programming above may be transposed. 2 cke and dqm must be held high until the precharge command is issued to ensure data-bus high-z. mode register and extended mode register set there are two mode registers, the mode register and the extended mode register so as to define the operating mode. parameters are set to both through the a0 to the a12 and ba0, ba1 pins by the mode register set command [mrs] or the extended mode register set command [emrs]. the mode register and the extended mode register are set by inputting signal via the a0 to the a12 and ba0, ba1 during mode register set cycles. ba0 and ba1 determine which one of the mode register or the extended mode register are set. prior to a read or a write operation, the m ode register must be set. remind that no other parameters are shown in the table bellow are allowed to input to the registers. mode register the mode register has three fields; options : a12 through a7 /cas latency : a6 through a4 wrap type : a3 burst length : a2 through a0 following mode register programming, no command can be issued before at least 2 clk have elapsed. /cas latency set /cas latency as follows. part number /cas latency edk2516cbbh-10-e edk2516cbbh-15-e 3 2 burst length burst length is the number of words that will be output or input in a read or write cycle. after a read burst is completed, the output bus will become high-z. the burst length is programmable as 2, 4, 8. wrap type (burst sequence) the wrap type specifies the order in which the burst data will be addressed. this order is programmable as either sequential or interleave. the method chosen will depend on the type of cpu in the system. some microprocessor cache systems are optimized for sequential addressing and others for interleaved addressing. burst length sequence shows the addressing sequence for each burst length using them. both sequences support bursts of 2, 4 and 8.
edk2516cbbh preliminary data sheet e0300e20 (ver. 2.0) 22 extended mode register the extended mode register has four fields; options : a12 through a7 drive strength : a6 through a5 temperature compensated self refresh : a4 through a3 partial array self refresh : a2 through a0 following extended mode register programming, no command can be issued before at least 2 clk have elapsed. drive strength by setting specific parameter on a6 and a5, driving capability of data output drivers is selected. temperature compensated self refresh a4 and a3 bit of emrs control the internal self refresh timer and self refresh current. partial array self refresh memory array size to be refreshed during self refresh operation is programmable in order to reduce power. data outside the defined area will not be retained during self refresh.
edk2516cbbh preliminary data sheet e0300e20 (ver. 2.0) 23 mode register definition wt = 1 r 2 4 8 r r r r bl wt 0 0 0 0 0 mode register set wt = 0 r 2 4 8 r r r r bits2-0 000 001 010 011 100 101 110 111 burst length sequential interleave 0 1 wrap type a0 a1 a2 a3 a4 a5 a7 a6 a8 a9 a10 a11 0 0 remark r : reserved ltmode pasr tcsr ds 0 0 0 0 extended mode register set refresh array all banks bank a & bank b (ba1=0) bank a (ba0=ba1=0) r r 1/2 of bank a (ra11=0) 1/4 of bank a (ra11=ra10=0) r bits2-0 000 001 010 011 100 101 110 111 partial array self refresh max temperature 70 c 45 c 15 c 85 c bits4-3 00 01 10 11 temprature compensated self refresh drive strength ba1 ba0 1 0 /cas latency r r 2 3 r r r r bits6-4 000 001 010 011 100 101 110 111 latency mode a12 0 a0 a1 a2 a3 a4 a5 a7 a6 a8 a9 a10 a11 ba1 ba0 0 strength normal 1/2 strength 1/4 strength 1/8 strength bits6-5 00 01 10 11 a12 0
edk2516cbbh preliminary data sheet e0300e20 (ver. 2.0) 24 burst operation the burst type (bt) and the first three bits of the column address determine the order of a data out. a2 a1 a0 addressing(decimal) 00 0 00 1 01 0 01 1 11 1 interleave sequence 10 0 11 0 10 1 starting ad. 0, 1, 2, 3, 4, 5, 6, 7, 1, 2, 3, 4, 5, 6, 7, 2, 3, 4, 5, 6, 7, 3, 4, 5, 6, 7, 4, 5, 6, 7, 5, 6, 7, 6, 7, 7, 0, 0, 1, 0, 1, 2, 0, 1, 2, 3, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 6, 0, 1, 2, 3, 4, 5, 6, 7, 1, 0, 3, 2, 5, 4, 7, 2, 3, 0, 1, 6, 7, 3, 2, 1, 0, 7, 4, 5, 6, 7, 5, 4, 7, 6, 7, 7, 6, 4, 5, 6, 5, 4, 0, 1, 2, 3, 6, 1, 0, 3, 2, 4, 5, 2, 3, 0, 1, 6, 5, 4, 3, 2, 1, 0, burst length = 8 a1 a0 addressing(decimal) 00 01 10 11 interleave sequence starting ad. 0, 1, 2, 3, 1, 2, 3, 0, 2, 3, 0, 1, 3, 0, 1, 2, 0, 1, 2, 3, 1, 0, 3, 2, 2, 3, 0, 1, 3, 2, 1, 0, burst length = 4 a0 addressing(decimal) 0 1 interleave sequence starting ad. 0, 1, 1, 0, 0, 1, 1, 0, burst length = 2
edk2516cbbh preliminary data sheet e0300e20 (ver. 2.0) 25 timing waveforms command and addresses input timing definition ck /ck vref command (/ras, /cas, /we, /cs) address tis tis tih tih vref read timing definition(1) read timing definition(2) write timing definition /ck ck dqs dm vref vref vref dq (din) tds tdh tdqss twpre twpres tds tdh tdipw tdipw tdipw tck tdsh tdss tdss tdqsl tdqsh twpst dqout ck /ck dqsout tdqsq tdqsq tdv hi-z hi-z hi-z hi-z tac(min) tac(max) tdqsck dq ck /ck hi-z dqs hi-z hi-z hi-z command read tdqslz(min) tdqslz(max) tlz(max) tlz(min) thz, tdqshz(min) thz, tdqshz(max)
edk2516cbbh preliminary data sheet e0300e20 (ver. 2.0) 26 package drawing 60-ball fbga solder ball: lead free (sn-ag-cu) 0.8 0.8 8 2 1 13.0 9.0 7 j h g f e d c b a 3 9 0.45 1.2 max ( detail: tbd) k unit : mm
edk2516cbbh preliminary data sheet e0300e20 (ver. 2.0) 27 recommended soldering conditions please consult with our sales offices for soldering conditions of the edk2516cbbh. type of surface mount device edk2516cbbh: 60-ball fbga < lead free (sn-ag-cu) >
edk2516cbbh preliminary data sheet e0300e20 (ver. 2.0) 28 notes for cmos devices 1 precaution against esd for mos devices exposing the mos devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the mos devices operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. mos devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. mos devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor mos devices on it. 2 handling of unused input pins for cmos devices no connection for cmos devices input pins can be a cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. the unused pins must be handled in accordance with the related specifications. 3 status before initialization of mos devices power-on does not necessarily define initial status of mos devices. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the mos devices with reset function have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. mos devices are not initialized until the reset signal is received. reset operation must be executed immediately after power-on for mos devices having reset function. cme0107
edk2516cbbh preliminary data sheet e0300e20 (ver. 2.0) 29 m01e0107 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of elpida memory, inc. elpida memory, inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of elpida memory, inc. or third parties by or arising from the use of the products or information listed in this document. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of elpida memory, inc. or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. elpida memory, inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [product applications] elpida memory, inc. makes every attempt to ensure that its products are of high quality and reliability. however, users are instructed to contact elpida memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [product usage] design your application so that the product is used within the ranges and conditions guaranteed by elpida memory, inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. elpida memory, inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating elpida memory, inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the elpida memory, inc. product. [usage environment] this product is not designed to be resistant to electromagnetic waves or radiation. this product must be used in a non-condensing environment. if you export the products or technology described in this document that are controlled by the foreign exchange and foreign trade law of japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of japan. also, if you export products/technology controlled by u.s. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. if these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. the information in this document is subject to change without notice. before using this document, confirm that this is the late st version.

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