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256m gddr sdram k4d551638f-tc - 1 - rev 2.1 (apr. 2005) 256mbit gddr sdram revision 2.1 april 2005 samsung electronics reserves the right to change products or specification without notice. information in this document is provid ed in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about sams ung products, contact your nearest samsung office. 2. samsung products are not intended for us e in life support, critical care, m edical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any government al procurement to which special terms or provisions may apply.
256m gddr sdram k4d551638f-tc - 2 - rev 2.1 (apr. 2005) revision history revision 2.1(april 29, 2005) ? mofidied cke input functional description on page 5. ? added k4d551638f-tc60 from the data sheet. revision 2.0(march 24, 2005) ? removed k4d551638f-tc60 from the data sheet. ? typo corrected. revision 1.9(february 24, 2005) ? typo corrected. revision 1.8 (august 30, 2004) ? dc spec defined for -tc33/36/40 revision 1.7 (june 15, 2004) ? changed vdd/vddq of k4d551638f-tc33 from 2.8v + 0.1v to 2.8v(min)/2.95v(max) ? spec for -tc33/36/40 still in target revision 1.6 (march 31, 2004) ? ac changes : refer to the ac characteristics of page 13 and 14. revision 1.5 (march 18, 2004) ? added k4d551638f-tc33 in the data sheet. ? target spec defined for -tc33 revision 1.4 (february 27, 2004) ? added k4d551638f-tc36/40 in the data sheet. ? target spec defined for -tc36/40 revision 1.3 (december 5, 2003) ? changed vdd/vddq of k4d551638f-tc50 from 2.5v + 5% to 2.6v + 0.1v revision 1.2 (november 11, 2003) ? "wrtie-interrupted by read function" is supported revision 1.1 (october 13, 2003) ? defined icc7 value revision 1.0 (october 10, 2003) ? defined dc spec ? changed part number of 16mx16 gddr f-die from k4d561638f-tc to k4d551638f-tc. revision 0.1 (october 2, 2003) - target spec ? added lead free package part number in the data sheet. ? removed k4d561638f-tc40 from the data sheet.
256m gddr sdram k4d551638f-tc - 3 - rev 2.1 (apr. 2005) the k4d551638f is 268,435,456 bits of hyper synchronous da ta rate dynamic ram organized as 4 x 4,194,304 words by 16 bits, fabricated with samsung ? s high performance cmos technology. sync hronous features with data strobe allow extremely high performance up to 1.1gb/ s/chip. i/o transactions are possible on both edges of the clock cycle. range of operating frequencies, programmable burst length and programma ble latencies allow the device to be useful for a variety of high performance memo ry system applications. general description features for 4m x 16bit x 4 bank gddr sdram 4m x 16bit x 4 banks graphic double data rate synchronous dram with bi-directional da ta strobe and dll ? 2.6v + 0.1v power supply for device operation ? 2.6v + 0.1v power supply for i/o interface ? sstl_2 compatible inputs/outputs ? 4 banks operation ? mrs cycle with address key programs -. read latency 3 (clock) -. burst length (2, 4 and 8) -. burst type (sequential & interleave) ? all inputs except data & dm are sampled at the positive going edge of the system clock ? differential clock input ? no write-interrupted by read function ? 2 dqs?s ( 1dqs / byte ) ? data i/o transactions on both edges of data strobe ? dll aligns dq and dqs transitions with clock transition ? edge aligned data & data strobe output ? center aligned data & data strobe input ? dm for write masking only ? auto & self refresh ? 64ms refresh period (8k cycle) ? 66pin tsop-ii ? maximum clock frequency up to 300mhz ? maximum data rate up to 600mbps/pin ordering information 1. k4d551638f-lc is the lead free package part number. 2. for the k4d551638f-tc60, vdd & vddq = 2.5v + 5% 3. for the k4d551638f-tc36, vdd & vddq = 2.8v + 0.1v 4. for the k4d551638f-tc33, vdd & vddq = 2.8v ~ 2.95v part no. max freq. max data rate interface vdd & vddq package k4d551638f-tc33 300mhz 600mbps/pin sstl_2 2.8v ~ 2.95v 66pin tsop-ii k4d551638f-tc36 275mhz 550mbps/pin 2.8v+ 0.1v k4d551638f-tc40 250mhz 500mbps/pin 2.6v+ 0.1v k4d551638f-tc50 200mhz 400mbps/pin k4d551638f-tc60* 166mhz 333mbps/pin 2.5v+ 0.125v
256m gddr sdram k4d551638f-tc - 4 - rev 2.1 (apr. 2005) pin configuration (top view) pin description ck,ck differential clock input ba 0 , ba 1 bank select address cke clock enable a 0 ~a 12 address input cs chip select dq 0 ~ dq 15 data input/output ras row address strobe v dd power cas column address strobe v ss ground we write enable v ddq power for dq ? s l(u)dqs data strobe v ssq ground for dq ? s l(u)dm data mask nc no connection rfu reserved for future use vref reference voltage 1 66 pin tsop(ii) (400mil x 875mil) 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13 27 26 25 24 23 22 21 54 53 52 51 50 49 48 47 46 45 44 43 35 36 37 38 39 40 41 42 55 56 57 58 59 60 34 (0.65 mm pin pitch) 33 32 31 30 29 28 61 62 63 64 65 66 v dd dq 0 v ddq dq 1 dq 2 v ssq dq 3 dq 4 v ddq dq 5 dq 6 v ssq ba 0 cs ras cas we ldm v ddq dq 7 v dd a 3 a 2 a 1 a 0 ap/a 10 ba 1 nc ldqs nc nc nc v dd v ss dq 15 v ssq dq 14 dq 13 v ddq dq 12 dq 11 v ssq dq 10 dq 9 v ddq a 11 cke ck udm v ref v ssq dq 8 v ss a 4 a 5 a 6 a 7 a 8 a 9 nc udqs nc v ss ck nc a 12
256m gddr sdram k4d551638f-tc - 5 - rev 2.1 (apr. 2005) input/output functional description *1 : the timing reference point for the different ial clocking is the cross point of ck and ck. for any applications us ing the single ended clocking, apply v ref to ck pin. sym- type function ck, ck *1 input the differential system clock input. all of the inputs are sampled on the risi ng edge of the clock except dq?s and dm?s that are sampled on both edges of the dqs. cke input activates the ck signal when high and deactivates the ck signal when low. by deactivating the clock, cke low indicate s the power down mode or self refresh mode.cke is synchronous for power down entry and exit, and for self refresh entry. cke is asynchronous for self refres h exit, and for output disable. cke must be maintained high through read and write accesses. input buffers, excluding ck, ck and cke are disbled during power down. input buffers, excluding cke are dis- abled during self refresh. cke is an sst l_2 input, but will detect a lvcmos low level after vdd is applied upon 1st power up. after vref has become stable during the power on and intialization sequence, it must be maintained for proper opera- tion of the cke receiver. for proper self refresh entry and exit, vref must be main- tained to this input. cs input cs enables the command decoder when lo w and disabled the command decoder when high. when the command decoder is disabled, new commands are ignored but previous oper ations continue. ras input latches row addresses on the positiv e going edge of the ck with ras low. enables row access & precharge. cas input latches column addresses on the positive going edge of the ck with cas low. enables column access. we input enables write operation and row precharge. latches data in starting from cas , we active. ldqs,udqs input/output data input and output are synchronized with both edge of dqs. for the x16, ldqs corresponds to the data on dq0-dq7 ; udqs corresponds to the data on dq8-dq15. ldm,udm input data in mask. data in is ma sked by dm latency=0 when dm is high in burst write. for the x16, ldm corresponds to the data on dq0-dq7 ; udm correspons to the data on dq8-dq15. dq0 ~ dq15 input/output data inputs/outputs are multiplexed on the same pins. ba0, ba1 input selects which bank is to be active. a0 ~ a12 input row/column addresses are multiplexed on the same pins. row addresses : ra0 ~ ra12, column addresses : ca0 ~ ca8. vdd/vss power supply power and ground for the input buffers and core logic. vddq/vssq power supply isolated power supply and ground for the output buffers to provide improved noise immunity. vref power supply reference voltage for inputs, used for sstl interface. nc/rfu no connection/ reserved for future use this pin is recommended to be le ft "no connection" on the device
256m gddr sdram k4d551638f-tc - 6 - rev 2.1 (apr. 2005) block diagram (4mbit x 16i/o x 4 bank) bank select timing register address register refresh counter row buffer row decoder col. buffer data input register serial to parallel 4mx16 4mx16 4mx16 4mx16 sense amp 2-bit prefetch output buffer i/o control column decoder latency & burst length programming register strobe gen. ck,ck addr lcke ck,ck cke cs ras cas we ldm ldmi ck,ck lcas lras lcbr lwe lwcbr lras lcbr ck, ck 32 16 16 lwe ldmi x16 dqi data strobe intput buffer dll udm
256m gddr sdram k4d551638f-tc - 7 - rev 2.1 (apr. 2005) ? power-up sequence ddr sdrams must be powered up and initialized in a predefined manner to prevent undefined operations. 1. apply power and keep cke at low state (all other inputs may be undefined) - apply vdd before vddq . - apply vddq before vref & vtt 2. start clock and maintain stable condition for minimum 200us. 3. the minimum of 200us after stable power and clock(ck,ck ), apply nop and take cke to be high . 4. issue precharge command for all banks of the device. 5. issue a emrs command to enable dll *1 6. issue a mrs command to reset dll. the additional 200 clock cycles are required to lock the dll. * 1,2 7. issue precharge command for all banks of the device. 8. issue at least 2 or more auto-refresh commands. 9. issue a mode register set command with a8 to low to initialize the mode register. *1 the additional 200cycles of clock input is required to lock the dll after ena bling dll. *2 sequence of 6&7 is regardless of the order. functional description power up & initialization sequence command 0 12345678910111213141516171819 trp 2 clock min. precharge all banks 2nd auto refresh mode register set any command t rfc 1st auto refresh t rfc emrs mrs 2 clock min. dll reset precharge all banks t rp inputs must be stable for 200us ~ ~ 200 clock min. 2 clock min. ck,ck * when the operating frequency is change d, dll reset should be required again. after dll reset again, the mini mum 200 cycles of clock input is needed to lock the dll.
256m gddr sdram k4d551638f-tc - 8 - rev 2.1 (apr. 2005) the mode register stores the data for controlling the vari ous operating modes of ddr sdram. it programs cas latency, addressing mode, burst length, test mode, dll reset and vari ous vendor specific options to make ddr sdram useful for variety of different applications. the default value of the mode register is not defined, therefore the mode register must be written after emrs setting for proper operation. th e mode register is written by asserting low on cs , ras , cas and we (the ddr sdram should be in active mode with cke already high prior to writing into the mode register). the state of address pins a 0 ~ a 12 and ba 0 , ba 1 in the same cycle as cs , ras , cas and we going low is written in the mode register. minimum two clock cycles are requested to complete the write o peration in the mode register. the mode register contents can be changed using the same command and clock cycle requirements du ring operation as long as all banks are in the idle state. the mode register is divided into various fi elds depending on functionality. the burst length uses a 0 ~ a 2 , addressing mode uses a 3 , cas latency(read latency from column address) uses a 4 ~ a 6 . a 7 is used for test mode. a 8 is used for dll reset. a 7, a 8 , ba 0 and ba 1 must be set to low for normal mrs operation. refer to the table for specific codes for various burst length, addre ssing modes and cas latencies. mode register set(mrs) mode register cas latency a 6 a 5 a 4 latency 000 reserved 001 reserved 010 reserved 011 3 100 reserved 101 reserved 110 reserved 111 reserved burst length a 2 a 1 a 0 burst type sequential interleave 0 0 0 reserve reserve 001 2 2 010 4 4 011 8 8 1 0 0 reserve reserve 1 0 1 reserve reserve 1 1 0 reserve reserve 1 1 1 reserve reserve burst type a 3 type 0 sequential 1 interleave * rfu(reserved for future use) should stay "0" during mrs cycle. mrs cycle command *1 : mrs can be issued only at all banks precharge state. *2 : minimum t rp is required to issue mrs command. 0 ck, ck precharge nop nop mrs nop nop 2 01 5 34 8 67 any nop all banks command t rp t mrd =2 t ck ba 1 ba 0 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 ba 0 a n ~ a 0 0mrs 1emrs dll a 8 dll reset 0no 1yes test mode a 7 mode 0 normal 1test nop address bus rfu 0 rfu dll tm cas latency bt burst length
256m gddr sdram k4d551638f-tc - 9 - rev 2.1 (apr. 2005) the extended mode register stores the data for enabling or disabling dll and selecting output driver strength. the default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling dll. the extended mode register is written by assert- ing low on cs , ras , cas , we and high on ba0(the ddr sdram should be in all bank precharge with cke already high prior to writing into the extended mode register). the state of address pins a0, a2 ~ a5, a7 ~ a12 and ba1 in the same cycle as cs , ras , cas and we going low are written in the extended mode register. a1 and a6 are used for setting driver strength to norm al, weak or matched impedance. two clock cycles are required to complete the write operation in the extended mode register. the mode register contents can be changed using the same command and clock cycle require ments during operation as long as all banks are in the idle state. a0 is used for dll enable or disable. "high" on ba0 is used for emrs. all the other address pins except a0,a1,a6 and ba0 must be set to low for proper emrs operation. refer to the table for specific codes. a 0 dll enable 0 enable 1 disable ba 0 a n ~ a 0 0mrs 1emrs extended mode register set(emrs) address bus extended *1 : rfu(reserved for future use) should stay "0" during emrs cycle. a 6 a 1 output driver impedence control 00 full 100% 01 weak 60% 10 matched 30% 11 n/a do not use ba 1 ba 0 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 mode register rfu 1 rfu d.i.c rfu d.i.c dll
256m gddr sdram k4d551638f-tc - 10 - rev 2.1 (apr. 2005) permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restri cted to recommended operating condition. exposure to higher than recommended voltage for extended per iods of time could affect device reliability. note : power & dc operating conditions(sstl_2 in/out) recommended operating conditions(voltage referenced to v ss =0v, t a =0 to 65 c) parameter symbol min typ max unit note device supply voltage v dd 2.5 2.6 2.7 v 1, 7 output supply voltage v ddq 2.5 2.6 2.7 v 1 reference voltage v ref 0.49*v ddq - 0.51*v ddq v2 termination voltage vtt v ref -0.04 v ref v ref +0.04 v 3 input logic high voltage v ih(dc) v ref +0.15 - v ddq +0.30 v 4 input logic low voltage v il(dc) -0.30 - v ref -0.15 v 5 output logic high voltage v oh vtt+0.76 - - v i oh =-15.2ma output logic low voltage v ol - - vtt-0.76 v i ol =+15.2ma input leakage current i il -5 - 5 ua 6 output leakage current i ol -5 - 5 ua 6 absolute maximum ratings parameter symbol value unit voltage on any pin relative to vss v in , v out -0.5 ~ 3.6 v voltage on v dd supply relative to vss v dd -1.0 ~ 3.6 v voltage on v ddq supply relative to vss v ddq -0.5 ~ 3.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 2.0 w short circuit current i os 50 ma 1. under all conditions v ddq must be less than or equal to v dd . 2. v ref is expected to equal 0.50*v ddq of the transmitting device and to track variations in the dc level of the same. peak to peak noise on the v ref may not exceed + 2% of the dc value. thus, from 0.50*v ddq , v ref is allowed + 25mv for dc error and an additional + 25mv for ac noise. 3. v tt of the transmitting device must track v ref of the receiving device. 4. v ih (max.)= v ddq +1.5v for a pulse width and it can not be greater than 1/3 of the cycle rate. 5. v il (mim.)= -1.5v for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. for any pin under test input of 0v < v in < v dd is acceptable. for all other pins that are not under test v in =0v. 7. for the k4d551638f-tc60 , vdd & vddq =2.5v + 5%, for the k4d551638f-tc36 , vdd & vddq =2.8v + 0.1v and for the k4d551638f-t c33 , vdd & vddq = 2.8v ~ 2.95v note :
256m gddr sdram k4d551638f-tc - 11 - rev 2.1 (apr. 2005) 1. v id is the magnitude of the diff erence between the input level on ck and the input level on ck 2. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track va riations in the dc level of the same note : ac input operating conditions recommended operating conditions(voltage referenced to v ss =0v, v dd =2.6v+ 0.1v, v ddq =2.6v+ 0.1v ,t a =0 to 65 c) parameter symbol min typ max unit note input high (logic 1) voltage; dq v ih v ref +0.35 - - v input low (logic 0) voltage; dq v il --v ref -0.35 v clock input differential voltage; ck and ck v id 0.7 - v ddq +0.6 v 1 clock input crossing point voltage; ck and ck v ix 0.5*v ddq -0.2 - 0.5*v ddq +0.2 v 2 dc characteristics note : 1. measured with outputs open. 2. refresh period is 64ms parameter symbol test condition version unit note -33 -36 -40 -50 -60 operating current (one bank active) i cc1 burst lenth=2 t rc t rc (min) i ol =0ma, t cc = t cc (min) 210 205 165 150 125 ma 1 precharge standby current in power-down mode i cc2 p cke v il (max), t cc = t cc (min) 66543ma precharge standby current in non power-down mode i cc2 n cke v ih (min), cs v ih (min), t cc = t cc (min) 50 45 37 25 20 ma active standby current power-down mode i cc3 p cke v il (max), t cc = t cc (min) 70 65 60 55 35 ma active standby current in in non power-down mode i cc3 n cke vih(min), cs vih(min), t cc = t cc (min) 100 95 80 75 56 ma operating current (burst mode) i cc4 t rc t rfc (min) t rc t rfc (min) page burst, all banks activated. 405 400 320 250 200 ma refresh current i cc5 t rc t rfc (min) 275 270 220 200 180 ma 2 self refresh current i cc6 cke 0.2v 44433ma operating current (4bank interleaving) i cc7 burst length=4 , t rc t rfc (min) i ol =0ma, t cc = t cc (min) 520 515 410 380 350 ma recommended operating conditions unless otherwise noted, t a =0 to 65 c)
256m gddr sdram k4d551638f-tc - 12 - rev 2.1 (apr. 2005) r t =50 ? output c load =30pf (fig. 1) output load circuit z0=50 ? v ref =0.5*v ddq v tt =0.5*v ddq decoupling capacitance guide line recommended decoupling capacitance added to power line at board. parameter symbol value unit decoupling capacitance between v dd and v ss c dc1 0.1 + 0.01 uf decoupling capacitance between v ddq and v ssq c dc2 0.1 + 0.01 uf 1. v dd and v ddq pins are separated each other. all v dd pins are connected in chip. all v ddq pins are connected in chip. 2. v ss and v ssq pins are separated each other all v ss pins are connected in chip. all v ssq pins are connected in chip. note : ac operating test conditions (v dd =2.6v 0.1v, t a = 0 to 65 c) parameter value unit note input reference voltage for ck(for single ended) 0.50*v ddq v ck and ck signal maximum peak swing 1.5 v ck signal minimum slew rate 1.0 v/ns input levels(v ih /v il )v ref +0.35/v ref -0.35 v input timing measurement reference level v ref v output timing measurement reference level v tt v output load condition see fig.1 capacitance (v dd =2.6v, t a = 25 c, f=1mhz) parameter symbol min max unit input capacitance( ck, ck )c in1 1.0 5.0 pf input capacitance(a 0 ~a 12 , ba 0 ~ba 1 )c in2 1.0 4.0 pf input capacitance ( cke, cs , ras ,cas , we ) c in3 1.0 4.0 pf data & dqs input/output capacitance(dq 0 ~dq 15 )c out 1.0 6.5 pf input capacitance(dm0 ~ dm3) c in4 1.0 6.5 pf
256m gddr sdram k4d551638f-tc - 13 - rev 2.1 (apr. 2005) ac characteristics parameter symbol -33 -36 -40 -50 -60 unit note min max min max min max min max min max ck cycle time cl=3 tck 3.3 10 3.6 10 4.0 10 5.0 10 6.0 12 ns ck high level width tch 0.45 0.55 0.4 5 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck ck low level width tcl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck dqs out access time from ck tdqsck -0.6 0.6 -0.6 0.6 -0.6 0.6 -0.55 0.55 -0.6 0.6 ns output access time from ck tac -0.6 0.6 -0.6 0.6 -0.6 0.6 -0.65 0.65 -0.7 0.7 ns data strobe edge to dout edge tdqsq - 0.35 - 0.4 - 0.4 - 0.4 - 0.45 ns 1 read preamble trpre 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck ck to valid dqs-in tdqss 0.85 1.15 0 .85 1.15 0.85 1.15 0.72 1.28 0.75 1.25 tck dqs-in setup time twpres0-0-0-0-0-ns dqs-in hold time twpreh 0.35 - 0.35 - 0.35 - 0.25 - 0.25 - tck dqs write postamble twpst 0.4 0 .60.40.60.40.60.40.60.40.6tck dqs-in high level width tdqsh 0.4 0.6 0.4 0.6 0.4 0.6 0.35 - 0.35 - tck dqs-in low level width tdqsl 0.4 0.6 0.4 0.6 0.4 0.6 0.35 - 0.35 - tck address and control input setup tis 0.9 - 0.9 - 0.9 - 0.6 - 0.8 - ns address and control input hold tih 0.9 - 0.9 - 0.9 - 0.6 - 0.8 - ns dq and dm setup time to dqs tds 0.35 - 0.4 - 0.4 - 0.4 - 0.45 - ns dq and dm hold time to dqs tdh 0.35 - 0.4 - 0.4 - 0.4 - 0.45 - ns clock half period thp tclmin or tchmin - tclmin or tchmin - tclmin or tchmin - tclmin or tchmin - tclmin or tchmin -ns1 data output hold time from dqs tqh thp- 0.35 - thp-0.4 - thp-0.4 - thp-0.5 - thp- 0.55 -ns1 note 1 : - the jedec ddr specification currently defi nes the output data valid window(tdv) as t he time period when the data strobe and all data associated with that data strobe are coincidentally valid. - the previously used definition of tdv(=0.35tck) ar tificially penalizes system ti ming budgets by assuming the worst case output vaild window even then the clock duty cycl e applied to the device is better than 45/55% - a new ac timing term, tqh wh ich stands for data output hold time from dqs is difined to account for clo ck duty cycle variation and replaces tdv - tqhmin = thp-x where . thp=minimum half clock period for any given cycle and is defined by clock high or clock low time(tch,tcl) . x=a frequency dependent timing allowance account for tdqsqmax
256m gddr sdram k4d551638f-tc - 14 - rev 2.1 (apr. 2005) ac characteristics (i) note : 1. for normal write operation, even numbers of din are to be written inside dram parameter symbol -33 -36 -40 -50 -60 unit note min max min max min max min max min max row cycle time trc 15 - 15 - 13 - 12 - 10 - tck refresh row cycle time trfc 17 - 17 - 15 - 14 - 12 - tck row active time tras 10 100k 10 100k 9 100k 8 100k 7 100k tck ras to cas delay for read trcdrd 5 - 5 - 4 - 4 - 3 - tck ras to cas delay for write trcdwr 3 - 3 - 2 - 2 - 2 - tck row precharge time trp 5 - 5 - 4 - 4 - 3 - tck row active to row active trrd 3 - 3 - 3 - 2 - 2 - tck last data in to row precharge @nor- mal precharge twr 3-3-3-3-3-tck1 last data in to row precharge @auto precharge twr_a3-3-3-3-3-tck1 last data in to read command tcdlr 3 - 2 - 2 - 2 - 1 - tck 1 col. address to col. address tccd 1 - 1 - 1 - 1 - 1 - tck mode register set cycle time tmrd 2 - 2 - 2 - 2 - 2 - tck auto precharge write recovery + pre- charge tdal 8-8-7-7-6-tck exit self refresh to read command txsr 200 - 200 - 200 - 200 - 200 - tck power down exit time tpdex 3tck +tis - 3tck +tis - 3tck +tis - 1tck +tis - 1tck +tis -ns refresh interval time tref 7.8 - 7.8 - 7.8 - 7.8 - 7.8 - us ac characteristics (ii) k4d551638f-tc33 frequency cas latency trc trfc tras trcdrd trcdwr trp trrd tdal unit 300mhz ( 3.3ns ) 3 15 17 10 5 3 5 3 8 tck k4d551638f-tc36 frequency cas latency trc trfc tras trcdrd trcdwr trp trrd tdal unit 275mhz ( 3.6ns ) 3 15 17 10 5 3 5 3 8 tck k4d551638f-tc40 frequency cas latency trc trfc tras trcdrd trcdwr trp trrd tdal unit 250mhz ( 4.0ns ) 3 13 15 9 4 2 4 3 7 tck 200mhz ( 5.0ns ) 3 12 14 8 4 2 4 3 7 tck k4d551638f-tc50 frequency cas latency trc trfc tras trcdrd trcdwr trp trrd tdal unit 200mhz ( 5.0ns ) 3 12 14 8 4 2 4 3 7 tck k4d551638f-tc60 frequency cas latency trc trfc tras trcdrd trcdwr trp trrd tdal unit 166mhz ( 6.0ns ) 3 10 12 7 3 2 3 2 6 tck (unit : number of clock)
256m gddr sdram k4d551638f-tc - 15 - rev 2.1 (apr. 2005) write interrupted by a read & dm a burst write can be interrupted by a read command of any bank. the dq ? s must be in the high impedance state at least one clock cycle before the interrupting read data app ear on the outputs to avoid data contention. when the read command is registered, any resi dual data from the burst write cycle must be masked by dm. the delay from the last data to read command (tcdlr) is required to avoid the data conten tion dram inside. data that are presented on the dq pins before the read command is initiated will actually be writ ten to the memory. read command interrupting write can not be issued at the next clock edge of that of write command. command < burst length=8, cas latency=3 > nop write nop nop read nop nop nop nop dqs dq s din 0 din 1 din 2 din 3 din 4 din 5 dout 0 dout 1 din 6 din 7 t cdlr cas latency=3 t dqssmax dqs dq s t cdlr cas latency=3 t dqssmin din 7 din 0 din 1 din 2 din 3 din 4 din 5 din 6 dm dout 0 dout 1 2 0 1 5 3 4 8 6 7 t wpres* 5 t wpres* 5 ck ck the following function established how a read command may interrupt a write burst and which input data is not written into the memory. 1. for read commands interru pting a write burst, the minimum write to read command delay is 2 clock cycles. the case where the write to read delay is 1 cl ock cycle is disallowed 2. for read commands interrupting a write burst, the dm pin must be used to mask the input data words whcich imme- diately precede the interrupting read operation and the in put data word which immediately follows the interrupting read operation 3. for all cases of a read interrupting a write, the dq and dqs buses must be released by the driving chip (i.e., the memory controller) in time to allow the buses to turn around before the gddr drives them during a read operation. 4. if input write data is masked by the read co mmand, the dqs input is ignored by the gddr. * this function is on ly supported in 200/166mhz.
256m gddr sdram k4d551638f-tc - 16 - rev 2.1 (apr. 2005) package dimensions (66pin tsop-ii) units : millimeters 0.30 0.08 0.65typ (0.71) 22.22 0.10 0.125 (0.80) 10.16 0.10 0 ~8 #1 #33 #66 #34 (1.50) (1.50) 0.65 0.08 1.00 0.10 1.20max (0.50) (0.50) (10.76) 11.76 0.20 (10 ) (10 ) +0.075 -0.035 (0.80) 0.10 max 0.075 max [] 0.05 min (10 ) (10 ) ( r 0 . 1 5 ) 0.210 0.05 0.665 0.05 ( r 0 . 15 ) ( 4 ) ( r 0 . 2 5 ) ( r 0.25) 0.45~0.75 0.25typ note 1. ( ) is reference 2. [ ] is ass ? y out quality

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