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5-573 fast and ls ttl data four-bit up/down counter with three-state outputs the sn54 / 74ls569a is designed as programmable up/down bcd and binary counters respectively. these devices have 3-state outputs for use in bus organized systems. with the exception of output enable (oe ) and asynchronous clear (aclr ), all functions occur on the positive edge of the clock pulse (cp). when the load input is low , the outputs will be programmed by the parallel data inputs (a, b, c, d) on the next clock edge. enabling of the counters occurs only when cep and cet are low and load is high. direction of the count is controlled by the up-down input (u/d ), high counts up and low counts down. high-speed counting and cascading is implement - ed by internal look-ahead carry logic and an active low ripple carry output (rco ). on the ls569a, the rco is low at binary 15 during up-count and during down-count it is also low at binary 0. during normal cascading operation rco connected to the succeeding block at cet is the only requisite. when counting and when rco is low , the clocked carry output (cco) provides a high-low -high pulse for a duration equal to the low time of the clock pulse. t wo active low reset lines are provided, a master reset asynchronous clear (aclr ) and a synchronous clear (sclr ). when in a high state, the output control (oe ) input forces the counter output into a high impedance state and when low, the counter outputs are enabled. ? esd > 3500 volts connection diagram (top view)

note: pin 1 is marked for orientation. guaranteed operating ranges symbol parameter min typ max unit v cc supply voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 v t a operating ambient temperature range 54 74 55 0 25 25 125 70 c i oh output current e high except rco , cco 54 74 1.0 2.6 ma i oh output current e high rco , cco 54, 74 0.44 ma i ol output current e low except rco , cco 54 74 12 24 ma i ol output current e low, rco, cco 54 74 4.0 8.0 ma sn54/74ls569a four-bit up/ down counter with three-state outputs low power schottky ordering information sn54lsxxxj ceramic sn74lsxxxn plastic sn74lsxxxdw soic 20 1 j suffix ceramic case 732-03 20 1 n suffix plastic case 738-03 20 1 dw suffix soic case 751d-03
5-574 fast and ls ttl data sn54/74ls569a function table inputs outputs cp d c b a load cet cep u/d aclr sclr oe rco cco y d y c y b y a x x x x h l l h h h l a/r a/r (q t cp) + 1 count up x x x x h l l l h h l a/r a/r (q t cp) 1 count down x x x x h h x x h h l h h nc nc nc nc count inhibit x x x x h l h x h h l a/r h nc nc nc nc count inhibit w x x x x x l l h h h l l h h h h overflow x x x x x l h h h h l l h h h h h overflow x x x x x h x h h h l h h h h h h overflow inhibit x x x x x l l l h h l l l l l l underflow x x x x x l h l h h l l h l l l l underflow x x x x x h x l h h l h h l l l l underflow inhibit l h l h l x x x h h l h h l h l h load example x x x x x h x h h l l h h l l l l clear (synchronous) x x x x x l l l h l l l l l l l clear (synchronous) x x x x x l h l h l l l h l l l l clear (synchronous) x x x x x h x l h l l h h l l l l clear (synchronous) x x x x x x x x h l x l h h l l l l asynchronous clear x x x x x l l l l x l l l l l l asynchronous clear x x x x x x l h l l x l l h l l l l asynchronous clear x x x x x x h x l l x l h h l l l l asynchronous clear x x x x x x x x x x x h x x hi-z output disabled (q t e cp) = output state prior to clock edge a/r = assumes required output state; x = don't care nc = no change high except during overflow and underflow logic diagram

5-575 fast and ls ttl data sn54/74ls569a definition of functional terms a, b, c, d the four programmable data inputs. cep count enable parallel. can be used to enable and inhibit counting in high speed cascaded operation. cep must be low to count. cet count enable t rickle. enables the ripple carry output for cascaded operation. must be low to count. cp clock pulse. all synchronous functions occur on the low -to-high transition of the clock. load enables parallel load of counter outputs from data inputs on the next clock edge. must be high to count. u/d up/down count control. high counts up and low counts down. aclr asynchronous clear . master reset of counters to zero when aclr is low , independent of the clock. sclr synchronous clear of counters to zero on the next clock edge when sclr is low. oe a high on the output control sets the four counter outputs in the high impedance, and a low, enables the output. y a , y b , y c , y d the four counter outputs. rco ripple carry output. output will be low on the maximum count on up-count. upon down-count, rco is low at 0000. cco clock carry output. while counting and rco is low , cco will follow the clock high-low-high transition. note: actual current flow direction shown

low-power schottky input/output current interface conditions
5-576 fast and ls ttl data sn54/74ls569a dc characteristics over operating temperature range (unless otherwise specified) symbol parameter limits unit test conditions symbol parameter min typ max unit test conditions v ih input high voltage 2.0 v guaranteed input high voltage for all inputs v il input low voltage 54 0.7 v guaranteed input low voltage for all inputs v il input low voltage 74 0.8 v guaranteed input low voltage for all inputs v ik input clamp diode voltage 0.65 1.5 v v cc = min, i in = 18 ma v oh output high voltage ya yd 54 2.4 3.4 v v cc = min, i oh = max, v in = v ih or v il per truth table v oh output high voltage ya yd 74 2.4 3.1 v v cc = min, i oh = max, v in = v ih or v il per truth table v oh rco , cco 54 2.5 3.5 v v cc = min, i oh = max, v in = v ih or v il per truth table rco , cco 74 2.7 3.5 v v ol output low voltage 54, 74 0.25 0.4 v i ol = i ol max v cc = v cc min, v in = v il or v ih per truth table v ol output low voltage 74 0.35 0.5 v i ol = i ol max v in = v il or v ih per truth table i ozh output off current high 20 m a v cc = max, v o = 2.7 v i ozl output off current low 20 m a v cc = max, v o = 0.4 v i ih input high current 20 m a v cc = max, v in = 2.7 v i ih input high current 0.1 ma v cc = max, v in = 7.0 v i il input low current others 0.4 ma v cc = max, v in = 0.4 v i il input low current cet 0.8 ma v cc = max, v in = 0.4 v i os short circuit current (note 1) rco , cco 20 100 ma v cc = max i os short circuit current (note 1) others 30 130 ma v cc = max i cc power supply current, 3-state 43 ma v cc = max note 1: not more than one output should be shorted at a time, nor for more than 1 second. ac characteristics (t a = 25 c) symbol parameter limits unit test conditions symbol parameter min typ max unit test conditions
5-577 fast and ls ttl data f max maximum toggle frequency 35 mhz v cc = 5.0 v c l = 45 pf r l = 667 w t plh t phl propagation delay clock to q 15 20 ns v cc = 5.0 v c l = 45 pf r l = 667 w t plh t phl propagation delay cet to rco 14 15 ns v cc = 5.0 v c l = 45 pf r l = 667 w t plh t phl propagation delay u/d to rco 20 24 ns v cc = 5.0 v c l = 45 pf r l = 667 w t plh t phl propagation delay clock to rco 20 25 ns v cc = 5.0 v c l = 45 pf r l = 667 w t plh t phl propagation delay cet to cco 16 28 ns v cc = 5.0 v c l = 45 pf r l = 667 w t plh t phl propagation delay cep to cco 16 26 ns t plh t phl propagation delay clock to cco 15 17 ns t plh t phl propagation delay aclr to q 22 32 ns t pzh t pzl output enable time 15 20 ns t phz t plz output disable time 20 27 ns c l = 5.0 pf
5-578 fast and ls ttl data sn54/74ls569a ac setup requirements (t a = 25 c, v cc = 5.0 v) symbol parameter limits unit test conditions symbol parameter min typ max unit test conditions t w clock pulse width (low) 20 ns v cc = 5.0 v t s setup time, a, b, c, d 20 ns v cc = 5.0 v t s setup time, sclr 20 ns v cc = 5.0 v t s setup time, load 25 ns v cc = 5.0 v t s setup time, u/d 30 ns v cc = 5.0 v t s setup time, cet , cep 20 ns t h hold time, any inputs 0 ns t rec aclr 15 ns microprogrammable dual-event 8-bit counters

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5-580 fast and ls ttl data symbol sw1 sw2 t pzh open closed t pzl closed open t plz closed closed t phz closed closed motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages. at ypicalo parameters can and do vary in dif ferent applications. all operating parameters, including at ypicalso must be validated for each customer application by customer ' s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur . should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af firmative action employer . literature distribution centers: usa: motorola literature distribution; p .o. box 20912; phoenix, arizona 85036. europe: motorola ltd.; european literature centre; 88 t anners drive, blakelands, milton keynes, mk14 5bp , england. jap an: nippon motorola ltd.; 4-32-1, nishi-gotanda, shinagawa-ku, t okyo 141, japan. asia p acific: motorola semiconductors h.k. ltd.; silicon harbour center , no. 2 dai king street, t ai po industrial estate, t ai po, n.t., hong kong. ?

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