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s1d17508 epson 8-1 1. description s1d17508 is a 160 output segment (column) lcd driver suitable for driving of colored stn dot-matrix lcd panels of a larger capacity, for use in combination with s1d17043. contributing to making clearer lcd picture quality, this ic employs the high speed enable chain method and is slim-chip configuration which is more advantageous for miniaturization of the lcd panel. s1d17508 is also capable of low-voltage and high-speed logic operations and fits to a wide range of applications. 2. features ? number of lcd drive output segments: 160 ? low voltage operation: 2.7v min. ? high duty drive: 1/500 (an example) ? wide lcd drive voltage range: + 8 to + 42v (v dd = 3 to 5.5v) ? high speed and low power consumption data transfer is possible by adoption of the 8-bit bus enable chain method: shift clock frequencies: 18.0 mhz (5v 10%) 10.0 mhz (2.7v) ? slim-chip configuration ? non-bias display off function ? pin-selection of the output shift direction is available ? offset bias regulation of lcd power for respective v ddh and gnd levels is possible ? logic operation power supply: 2.7 to 5.5v ? shipped status: chip S1D17508D00B * tcp s1d17508t **** ? this ic is not radiation resistant
s1d17508 8-2 epson v ddhl v 0l v 2l v 3l v 5l v ddhr v 0r v 2r v 3r v 5r fr dspof lp v gnd d0 to d7 xscl eio1 shl eio2 o1 o160 cc lcd driver 160 bot level shifter : 160 bit latch : 160 bit data resister : 160 bit bidirectional shift resister 3. block diagram
s1d17508 epson 8-3 4. pin description pin name i/o description numbers of pins o1 to o160 o lcd driving segment (column) output. 160 the output varies at the falling edge of lp. d0 to d7 i display data input terminals 8 xscl i for input of the shift clock signals of the display data 1 (falling edge trigger) lp i for input of the latch pulse signals of the display data 1 (falling edge trigger) eio1 i/o enable i/o. 2 eio2 setting to i or o is determined by the shl input level. the output is reset by the lp input and when 160 bit equivalent data are received, it falls to low automatically. shl i shift direction selection and eio terminal i/o control signal input. 1 when data are input to terminals (d 0 , d 1 .....d 7 ) in the order of (a 0 , a 1 .....a 6 and a 7 ), (b 0 .....b 6 and b 7 ) .....(t 0 , t 1 .....t 6 and t 7 ), the relations between the data and segment outputs become as follows: fr i for input of alternating current lcd drive signals. 1 v cc , gnd power logic operation power supply: gnd: 0v 2 supply v cc : +3.3, +5v v ddhl , v ddhr lcd drive power supply v ddh gnd: 0v v ddh :14 to 42v 10 v 0l ,v 0r "v 0 v ddh 3 v 0 3 v 2 3 7/9v 0 v 2l , v 2r power "v 2 2/9 v 0 3 v 3 3 v 5 3 v ss v 3l , v 3r supply "v 3 v 5l , v 5r "v 5 dspof i for forced bias fixed input. 1 low level output is forcefully made to v 5 level. * when using this function, combined use with s1d17003 is not applicable. total 187 output eio shl o1 o2 o3 o158 o159 o160 eio1 eio2 low a7 a6 a5 ... t2 t1 t0 input output high t0 t1 t2 ... a5 a6 a7 output input (note) the relations between the data and segment outputs are determined independent from the number of the shift clocks.
s1d17508 8-4 epson data bus voltage dspof signals fr outputs of the driver high high v 0 high low v 5 low high v 2 low v 3 low C C v 5 5. function of each block 5-1 enable shift resister the enable shift register is a bidirectional shift register of which the shift direction is being selected by the shl input and the shift register output is used to store data bus signals into the data register. when the enable signal is in disabled state, the internal clock signal and the data bus are fixed to low, thus going into a power saving mode. when using multiple number of segment drivers, make cascade connection of eio terminals of respective drivers to connect the eio terminal of the top driver to gnd. (refer to clause 10. connection examples) since the enable control circuit automatically senses completion of receiving 160 bit equivalent data to transfer the enable signal automatically, control signal of a separate control lsi is not needed. 5-2 data register this register works to make series or parallel conversion of data bus signals according to the enable shift register output. consequently, the relations between the serial display data and segment outputs are determined independent from the number of the shift clock inputs. 5-3 latch it takes in the content of the data register at the falling edge trigger to transfer the output to the level shifter. 5-4 level shifter this is a level interface circuit to convert the voltage level of signals from the logic operation level to lcd drive level. 5-5 lcd driver it outputs the lcd driving voltage. given below are the relations between data bus signals, alternating current signal fr levels and segment output voltages.
s1d17508 epson 8-5 5-6 timing diagram timing diagram in case of 1/240 duty (an example) lp latch data fr 240 1 2 3 4 239 240 1 2 3 239 240 1 lp xscl d0 to d7 eio eio eio n 20 1 2 3 20 1 2 3 20 1 2 3 20 1 [ 1 to n stands for the cascade numbers of the driver. * when making high speed data transfer, it becomes necessary to secure a longer xscl cycle when determining the lp pulse insertion timing in order to maintain the specified value of lp ? xscl (t lh ). lp latch data fr dspof v 0 v 2 v 3 v 5 h h h ll l h l l h l h h h l h l l
s1d17508 8-6 epson 6. absolute maximum ratings items codes ratings units supply voltage (1) v cc C0.3 to +7.0 v supply voltage (2) v ddh C0.3 to +45.0 v supply voltage (3) v 0 , v 2 , v 3 , v 5 C0.3 to v ddh + 0.3 v input voltage v i C0.3 to v cc + 0.3 v output voltage v o C0.3 to v cc + 0.3 v eio output current i 01 20 ma working temperature topr C30 to +85 c storage temperature 1 tstg1 C65 to +150 c storage temperature 2 tstg2 C55 to +100 c (note 1) all the voltage ratings are based on gnd = 0v. (note 2) the storage temperature 1 is applicable to independent chips and the storage temperature 2 is applicable to the tcp modular state. (note 3) v 0 , v 2 , v 3 and v 5 should always be in the order of v ddh 3 v 0 3 v 2 3 v 3 3 v 5 3 gnd. (note 4) if the logic operation power goes into a floating state or if v cc drops to 2.6v or below while the lcd driving power is being applied, the lsi may be damaged. therefore, keep from occurrence of the aforementioned status. specifically, pay close attention to the power supply sequence at times of turning the system power on and off. 42v 5v v cc gnd v ddh v 0 v 2 v 3 v 5 gnd
s1d17508 epson 8-7 unless otherwise specified, gnd = 0v, v cc = +5.0 v 10%, ta = C30 to 85 c applicable item symbol condition min. typ. max. unit pin supply voltage (1) v cc v cc 2.7 5.5 v recommended operating v 0 v 0l ,v ddhl 14.0 40.0 v voltage operating voltage v 0 function only v 0r ,v ddhl 8.0 42.0 v supply voltage (2) v 2 recommended value v 2l , v 2r 7/9 v 0 v 0 v supply voltage (3) v 3 recommended value v 3l , v 3r gnd 2/9 v 0 v high level input voltage v ih eio1,eio2,fr 0.8v cc v v dd = 2.7 to 5.5v d0 to d7,xscl low level input voltage v il shl,lp, dspof 0.2v cc v high level output voltage v oh v cc= i oh = C0.6ma v cc C0.4 v 2.7 to eio1, eio2 low level output voltage v ol 5.5v i ol = 0.6ma 0.4 v input leak current i li gnd v in v cc d0 to d7,lp,fr 2.0 m a xscl, shl dspof i/o leak current i li/o gnd v in v cc eio1, eio2 5.0 m a rest current i gnd v 0 = 14.0 to 42.0v gnd 25 m a v ih = v cc , v il =gnd output resistance s s v on v 0 =+36.0v, 1/24 o1 to o160 0.85 2.6 r seg =0.5v k w recom- mended v 0 =+26.0v, 1/20 0.90 2.6 condition in-chip deviation of output s s r seg s s v on =0.5v o1 to o160 90 w resistance v 0 = +36.0v, 1/24 mean working current v cc = +5.0v, v ih = v cc consumption (1) v il = gnd, f xscl = 5.38mhz f lp = 33.6khz, f fr = 70hz 0.5 1.1 ma i cc input data: checkered indication, v cc no-load v cc = +3.0v other conditions are the same as 0.2 0.6 those when v cc = 5v. mean working current i o v 0 = +30.0v consumption (2) v cc = +5.0v, v 3 = +4.0v v 2 = +26.0v, v 5 = +0.0v v0l, v0r 0.15 0.9 ma other conditions are the same as those in the i dd column. input terminal capacity c i freq. = 1 mhz d0 to d7, lp, 8 pf ta = 25 c fr, xscl, shl, independent chips dspof i/o terminal capacity c i/o eio1, eio2 15 pf 7. electrical characteristics 7-1 dc characteristics
s1d17508 8-8 epson working voltage range v cc - v 0 the v 0 voltage should be set up within the v cc - v 0 working voltage range given below. 50 42 40 30 20 10 0 28 2.0 3.0 4.0 5.0 6.0 2.7 v cc (v) v 0 (v) working voltage range
s1d17508 epson 8-9 7-2 ac characteristics input timing characteristics fr lp xscl do to d7 eio 1,2 (in) t df t r t wlh t lh t c t wch t wcl t sue t dh t ds t ld v cc = 5.0v 10%, ta = C30 to 85 c notes : *1 the t wlh specifies the time when the lp is at high and, at the same time, when xscl is at low, when lp is being input while the xscl is at low. * 2 the t wlh (its definition is same as *1) when lp rises while xscl is at high. * 3 high speed operation of the shift clocks (xscl) should only be made under a condition of t r + t f (t c - t wcl - t wch ). * 4 when making high speed data transfer using continuous shift clocks, t r + t f of the lp signals should be upto (t c + t wch - t ld - t wlh - t lh ) at the maximum. items symbol conditions min. max. units xscl cycle tc t r , t f 11ns *3 62 ns xscl high level pulse duration t wch 20 ns xscl low level pulse duration t wcl 20 ns data setup time t ds 10 ns data hold time t dh 10 ns xscl ? lp rise time t ld C5 ns lp ? xscl fall time t lh 30 ns lp high level pulse duration t wlh *1 40 ns *2 35 ns fr delay allowance t df C300 +300 ns eio setup time t sue 30 ns input signal variation time t r, t f *4 50 ns items symbol conditions min. max. units xscl cycle tc t r , t f 15ns *3 100 ns xscl high level pulse duration t wch 35 ns xscl low level pulse duration t wcl 35 ns data setup time t ds 15 ns data hold time t dh 10 ns xscl ? lp rise time t ld C10 ns lp ? xscl fall time t lh 60 ns lp high level pulse duration t wlh *1 75 ns *2 65 ns fr delay allowance t df C300 +300 ns eio setup time t sue 40 ns input signal variation time t r, t f *4 50 ns v cc = 2.7v to 4.5v, ta = C30 to 85 c
s1d17508 8-10 epson output timing characteristics fr lp xscl eio 1,2 (out) seg t er t dcl t frsd t lsd items symbol conditions min. max. units eio reset time t er cl = 15 pf 120 ns eio output delay time t dcl (eio) 55 ns lp ? seg output delay time t lsd cl = 100 pf 200 ns fr ? seg output delay time t frsd (o n) 400 ns v cc = +5.0v 10%, v 0 = +14.0 to +42.0v items symbol conditions min. max. units eio reset time t er cl = 15 pf 240 ns eio output delay time t dcl (eio) 85 ns lp ? seg output delay time t lsd cl = 100 pf 400 ns fr ? seg output delay time t frsd (o n) 800 ns v cc = +2.7v to 4.5v, v 0 = +14.0 to +28.0v
s1d17508 epson 8-11 8. lcd driving power supply 8-1 setting up respective voltage levels when setting up respective voltage levels for lcd drive, it is the best way to resistively divide the potential between v 0 - gnd to drive the lcd by means of voltage follower using an operation amplifier. in consideration of the case of using an operation amplifier, the lcd driving minimum potential level v 5 and gnd are separated and independent terminals are used. however, since the efficacy of the lcd driving output driver deteriorates when the potential of v 5 goes up beyond the gnd potential to enlarge the potential difference, always keep the potential difference of v 5 - v ss at 0v to 2.5v. when a resistance exists in series in the power supply line of v 0 (gnd), io at signal changes causes voltage drop at v 0 (gnd) of the supply terminals of the lsi disabling it to maintain the relations of the lcd with intermediate potentials of (v ddh 3 v 0 3 v 2 3 v 3 3 v 5 3 gnd), thus leading to breakdown or destruction of the lsi. when using a protective resistor, do not fail to stabilize the voltage using an appropriate capacitance. 8-2 precautions when turning the power on and off since the lcd drive voltage of these lsis is comparatively high, if a high voltage of 30v or more is applied to the lcd drive circuit with the logic operation power made floating or with the v cc lowered to 2.6v or less, or when lcd drive signals are output before applied voltage to the lcd drive circuits is stabilized, excess current flows through to possibly lead to breakdown or to destroy the lsi. it is therefore suggested to maintain the potential of the lcd drive output to v 5 level until the lcd drive circuit voltage is stabilized, using the display off function ( dspof ). maintain the following sequences when turning the power on and off: when turning the power on: turn on the logic operation power ? turn on the lcd drive power or turn them on simultaneously. when turning the power off: turn off the lcd drive power ? turn off the logic operation power or turn them off simultaneously. for protection against excess current, insert a quick melting fuse in series in the lcd drive power line. when using a protective resistor, select the optimum resistance value depending on the capacitance of the lcd cells.
s1d17508 8-12 epson 9. a connection example block diagram of a large-plane lcd ydu yscl dspof shl (ydl) fr lp xscl shl dl0 to 7 dio1 sel dio2 dio1 sel dio2 di3 dio1 sel dio2 s1d17403 s1d17403 s1d17403 160 160 160 160 s1d17508 s1d17508 s1d17508 s1d17508 eio1 eio2 eio1 eio2 eio1 eio2 eio1 eio2 640 480 dot (1/240 duty) 1/480 duty 80 80 80 80 80 80 r r r r r + + + + v 0 v 1 v 2 v 3 v 4 v 5
s1d17508 epson 8-13 10. s1d17508t * tcp pin arrangement example for reference remark: this drawing is not meant to determine the contour of the tcp. v 5l v 3l v 2l v 0l v ddhl gnd nc shl nc spof fr lp xlcl eio1 eio2 v cc d7 d6 d5 d4 d3 d2 d1 d0 v 0r v 2r v ddhr v 3r v 5r o1 o2 o3 o4 o157 o158 o159 o160
s1d17508 8-14 epson 11. dimensional outline drawing for reference s1d17508t00a * unit: mm
s1d17508 epson 8-15 for reference s1d17508t00b * unit: mm
s1d17508 8-16 epson unit: mm for reference s1d17508t00g *

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