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first release features ? built using the advantages and compatibility of cmos and ixys hdmos tm processes ? latch-up protected over entire operating range ? high peak output current: 14a peak ? wide operating range: 4.5v to 30v ? - 55c to +125c extended operating temperature ? high capacitive load drive capability: 15nf in <30ns ? matched rise and fall times ? low propagation delay time ? low output impedance ? low supply current ? two drivers in single chip applications ? driving mosfets and igbts ? motor controls ? line drivers ? pulse generators ? local power on/off switch ? switch mode power supplies (smps) ? dc to dc converters ? pulse transformer driver ? class d switching amplifiers ? power charge pumps general description the ixdi514 and ixdn514 are high speed high current gate drivers specifically designed to drive the largest ixys mosfets & igbts to their minimum switching time and maximum parctical frequency limits. the ixdi514 and ixdn514 can source and sink 14 amps of peak current while producing voltage rise and fall times of less than 30ns. the inputs of the drivers are compatible with ttl or cmos and are virtually immune to latch up over the entire operating range! patented* design innovations eliminate cross conduction and current "shoot-through". improved speed and drive capabilities are further enhanced by very quick & matched rise and fall times. the ixdi514 is configured as a inverting gate driver, and the ixdn514 is configured as a non-inverting gate driver. the ixdi514 and ixdn514 are each available in the 8-pin p- dip (pi) package, the 8-pin soic (sia) package, and the 6-lead dfn (d1) package, (which occupies less than 65% of the board area of the 8-pin soic). *united states patent 6,917,227 ordering information part number description package type packing style pack qty configuration ixdi514pi 14a low side gate driver i.c. 8-pin pdip tube 50 ixdi514sia 14a low side gate driver i.c. 8-pin soic tube 94 ixdi514siat/r 14a low side gate driver i.c. 8-pin soic 13? tape and reel 2500 ixdi514d1 14a low side gate driver i.c. 6-lead dfn 2? x 2? waffle pack 56 ixdi514d1t/r 14a low side gate driver i.c. 6-lead dfn 13? tape and reel 2500 inverting IXDN514PI 14a low side gate driver i.c. 8-pin pdip tube 50 ixdn514sia 14a low side gate driver i.c. 8-pin soic tube 94 ixdn514siat/r 14a low side gate driver i.c. 8-pin soic 13? tape and reel 2500 ixdn514d1 14a low side gate driver i.c. 6-lead dfn 2? x 2? waffle pack 56 ixdn514d1t/r 14a low side gate driver i.c. 6-lead dfn 13? tape and reel 2500 non-inverting ds99672(01/07) note: all parts are lead-free and rohs compliant copyright ? 2006 ixys corporation all rights reserved 14 ampere low-side ultrafast mosfet drivers ixdi514 / ixdn514 preliminary technical information
2 copyright ? 2006 ixys corporation all rights reserved ixdi514 / ixdn514 figure 2 - ixdn514 14a non-inverting gate driver functional block diagram figure 1 - ixdi514 inverting 14a gate driver functional block diagram * united states patent 6,917,227 n p out vcc in anti-cross conduction circuit * gnd gnd vcc * n p out vcc in anti-cross conduction circuit * gnd gnd vcc
3 ixdi514 / ixdn514 unless otherwise noted, 4.5v v cc 30v . all voltage measurements with respect to gnd. ixd_514 configured as described in test conditions . electrical characteristics @ t a = 25 o c (3) s y mbol parameter test conditions min t y p max units v ih high input voltage 4.5v v cc 18v 2.5 v v il low input voltage 4.5v v cc 18v 1.0 v v in input voltage range -5 v cc + 0.3 v i in input current 0v v in v cc -10 10 a v oh high output voltage v cc - 0.025 v v ol low output voltage 0.025 v r oh output resistance @ output high i out = 10ma, v cc = 18v 600 1000 m ? r ol output resistance @ output low i out = 10ma, v cc = 18v 600 1000 m ? i peak peak output current v cc is 18v 14 a i dc continuous output current limited by package power dissipation 4 a t r rise time c l =15nf vcc=18v 23 25 40 ns t f fall time c l =15nf vcc=18v 21 22 50 ns t ondly on-time propagation delay c l =15nf vcc=18v 29 30 30 ns t offdly off-time propagation delay c l =15nf vcc=18v 29 31 50 ns v cc power supply voltage 4.5 18 30 v i cc power supply current v in = 3.5v v in = 0v v in = + v cc 1 0 3 10 10 ma a a absolute maximum ratings (1) operating ratings (2) parameter value supply voltage 35 v all other pins -0.3 v to v cc + 0.3v junction temperature 150 c storage temperature -65 c to 150 c lead temperature (10 sec) 300 c parameter value operating supply voltage 4.5v to 30v operating temperature range -55 c to 125 c (4) ixys reserves the right to change limits, test conditions, and dimensions. package thermal resistance * 8-pin pdip (pi) j-a (typ) 125 c/w 8-pin soic (sia) j-a (typ) 200 c/w 6-lead dfn (d1) j-a (typ) 125-200 c/w 6-lead dfn (d1) j-c (max) 1.5 c/w 6-lead dfn (d1) j-s (typ) 5.8 c/w
4 copyright ? 2006 ixys corporation all rights reserved ixdi514 / ixdn514 notes: 1. operating the device beyond the parameters listed as ?absolute maximum ratings? may cause permanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2. the device is not intended to be operated outside of the operating ratings. 3. electrical characteristics provided are associated with the stated test conditions. 4. typical values are presented in order to communicate how the device is expected to perform, but not necessarily to highlight any specific performance limits within which the device is guaranteed to function. unless otherwise noted, 4.5v v cc 30v , tj < 150 o c all voltage measurements with respect to gnd. ixd_502 configured as described in test conditions . all specifications are for one channel. electrical characteristics @ temperatures over -55 o c to 125 o c (3) symbol parameter test conditions min typ max units v ih high input voltage 4.5v v cc 18v 2.7 v v il low input voltage 4.5v v cc 18v 0.8 v v in input voltage range -5 v cc + 0.3 v i in input current 0v v in v cc -10 10 a v oh high output voltage v cc - 0.025 v v ol low output voltage 0.025 v r oh output resistance @ output high v cc = 18v 1.25 ? r ol output resistance @ output low v cc = 18v 1.25 ? i dc continuous output current 1 a t r rise time c l =10,000pf vcc=18v 23 100 ns t f fall time c l =10,000pf vcc=18v 30 100 ns t ondly on-time propagation delay c l =10,000pf vcc=18v 20 60 ns t offdly off-time propagation delay c l =10,000pf vcc=18v 40 60 ns v cc power supply voltage 4.5 18 30 v i cc power supply current v in = 3.5v v in = 0v v in = + v cc 1 0 3 10 10 ma a a (4)
5 ixdi514 / ixdn514 pin description caution: follow proper esd procedures when handling and assembling this component. * the following notes are meant to define the conditions for the j-a , j-c and j-s values: 1) the j-a (typ) is defined as junction to ambient. the j-a of the standard single die 8-lead pdip and 8-lead soic are dominated by the resistance of the package, and the ixd_5xx are typical. the values for these packages are natural convection values with verti cal boards and the values would be lower with natural convection. for the 6-lead dfn package, the j-a value supposes the dfn package is soldered on a pcb. the j-a (typ) is 200 c/w with no special provisions on the pcb, but because the center pad provides a low thermal resistance to the die, it is easy to reduce the j-a by adding connected copper pads or traces on the pcb. these can reduce the j-a (typ) to 125 c/w easily, and potentially even lower. the j-a for dfn on pcb without heatsink or thermal management will vary significantly with size, construction, layout, materials, etc. this typical range tells the user what he is likely to get if he does no thermal managem ent. 2) j-c (max) is defined as juction to case, where case is the large pad on the back of the dfn package. the j-c values are generally not published for the pdip and soic packages. the j-c for the dfn packages are important to show the low thermal resistance from junction to the die attach pad on the back of the dfn, -- and a guardband has been added to be safe. 3) the j-s (typ) is defined as junction to heatsink, where the dfn package is soldered to a thermal substrate that is mounted on a heatsi nk. the value must be typical because there are a variety of thermal substrates. this value was calculated based on easily availab le ims in the u.s. or europe, and not a premium japanese ims. a 4 mil dialectric with a thermal conductivity of 2.2w/mc was assumed. the re sult was given as typical, and indicates what a user would expect on a typical ims substrate, and shows the potential low thermal resist ance for the dfn package. symbol function description vcc supply voltage positive power-supply voltage input. this pin provides power to the entire chip. the range for this voltage is from 4.5v to 30v. in input input signal-ttl or cmos compatible. out output driver output. for application purposes, this pin is connected, through a resistor, to gate of a mosfet/igbt. gnd ground the system ground pin. internally connected to all circuitry, this pin provides ground reference for the entire chip. this pin should be connected to a low noise analog ground plane for optimum performance. figure 3 - characteristics test diagram 0v 5.0v 0v vcc ixdi414 ixdn414 0v vcc a gilent 1147a current probe 15nf 10uf 25v ixd_514 ixdi514 ixdn514 2500 pf
6 copyright ? 2006 ixys corporation all rights reserved ixdi514 / ixdn514 ixys reserves the right to change limits, test conditions, and dimensions. figure 4 - timing diagrams inverting (ixdi514) timing diagram 0v 5v 90% 10% 2.5v input vcc 0v 10% 90% output pw min t f t offdly t r t ondly non-inverting (ixdn514) timing diagram input output 5v 90% 2.5v 10% 0v 0 v vcc 90% 10% t ondly t offdly t r t f pw min
7 ixdi514 / ixdn514 typical performance characteristics max / min input vs. case temperature v cc =18v c l =15nf temperature ( o c) -60 -40 -20 0 20 40 60 80 100 max / min input (v) 1.6 1.8 2.2 2.4 2.6 2.8 3.2 2.0 3.0 maximum input low minimum input high fall time vs. load capacitance load capacitance (pf) 0k 5k 10k 15k 20k fall time (ns) 0 10 20 30 40 18v 8v 10v 12v 14v 16v rise time vs. load capacitance load capacitance (pf) 0k 5k 10k 15k 20k rise time (ns) 0 10 20 30 40 50 18v 8v 10v 12v 14v 16v rise and fall times vs. case temperature c l = 15 nf, v cc = 18v tem p erature ( c ) -40-200 20406080100120 time (ns) 0 5 10 15 20 25 30 35 40 t f t r rise time vs. supply voltage supply voltage (v) 8 1012141618 rise time (ns) 0 10 20 30 40 cl=15,000 pf 7,500 pf 3,600 pf fall time vs. supply voltage supply voltage (v) 8 1012141618 fall time (ns) 0 10 20 30 40 cl=15,000 pf 7,500 pf 3,600 pf fig. 5 fig. 6 fig. 7 fig. 8 fig. 9 fig. 10
8 copyright ? 2006 ixys corporation all rights reserved ixdi514 / ixdn514 supply current vs. load capacitance vcc=8v load capacitance (pf) 1k 10k 100k supply current (ma) 1 10 100 1000 50 khz 100 khz 500 khz 1 mhz 2 mhz supply current vs. load capacitance vcc=12v load capacitance (pf) 1k 10k 100k supply current (ma) 1 10 100 1000 50 khz 100 khz 500 khz 1 mhz 2 mhz supply current vs. frequency vcc=8v frequency (khz) 10 100 1000 10000 supply current (ma) 0.1 1 10 100 1000 2000 pf cl= 30 nf 5000 pf 15 nf supply current vs. frequency vcc=18v frequency (khz) 10 100 1000 10000 supply current (ma) 0.1 1 10 100 1000 2000 pf cl= 30 nf 5000 pf 15 nf supply current vs. frequency vcc=12v frequency (khz) 10 100 1000 10000 supply current (ma) 0.1 1 10 100 1000 2000 pf cl = 30 nf 5000 pf 15 nf supply current vs. load capacitance vcc=18v load capacitance (pf) 1k 10k 100k supply current (ma) 1 10 100 1000 50 khz 100 khz 500 khz 1 mhz 2 mhz fig. 13 fig. 11 fig. 12 fig. 14 fig. 16 fig. 15
9 ixdi514 / ixdn514 propagation delay vs. input voltage c l =15nf v cc =15v input voltage (v) 24681012 propagation delay (ns) 0 10 20 30 40 50 t ondly t offdly propagation delay vs. supply voltage c l =15nf v in =5v@1khz supply voltage (v) 8 1012141618 propagation delay (ns) 0 10 20 30 40 50 t ondly t offdly p channel output current vs. case temperature v cc =18v c l =.1uf temperature ( o c) -40 -20 0 20 40 60 80 100 p channel output current (a) 12 13 14 15 16 n channel output current vs. case temperature v cc =18v c l =.1uf temperature ( o c) -40 -20 0 20 40 60 80 100 n channel output current (a) 14 15 16 17 quiescent supply current vs. case temperature v cc =18v v in =5v@1khz tem p erature ( o c ) -40-200 20406080 quiescent supply current (ma) 0.50 0.52 0.54 0.56 0.58 0.60 propagation delay vs. case temperature c l = 2500pf, v cc = 18v tem p erature ( c ) -40 -20 0 20 40 60 80 100 120 time (ns) 10 15 20 25 30 35 40 45 50 t offdly t ondly fig. 18 fig. 20 fig. 22 fig. 17 fig. 19 fig. 21
10 copyright ? 2006 ixys corporation all rights reserved ixdi514 / ixdn514 low-state output resistance vs. supply voltage supply voltage (v) 10 15 20 25 low-state output resistance (ohms) 0.2 0.4 0.6 0.8 0.0 1.0 8 high state output resistance vs. supply voltage supply voltage (v) 10 15 20 25 high state output resistance (ohm) 0.2 0.4 0.6 0.8 0.0 1.0 8 v cc vs. p channel output current c l =.1uf v in =0-5v@1khz vcc 10 15 20 25 p channel output current (a) -24 -22 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 8 vcc vs. n channel output current c l =.1uf v in =0-5v@1khz vcc 10 15 20 25 n channel output current (a) 0 2 4 6 8 10 12 14 16 18 20 22 24 8 enable threshold vs. supply voltage supply voltage (v) 8 101214161820222426 enable threshold (v) 0 2 4 6 8 10 12 14 fig. 23 fig. 24 fig. 25 fig. 26 fig. 27
11 ixdi514 / ixdn514 pin configurations when designing a circuit to drive a high speed mosfet utilizing the ixd_514, it is very important to observe certain design criteria in order to optimize performance of the driver. particular attention needs to be paid to supply bypassing , grounding , and minimizing the output lead inductance . say, for example, we are using the ixd_514 to charge a 5000pf capacitive load from 0 to 25 volts in 25ns . using the formula: i= ? v c / ? t, where ? v=25v c=5000pf & ? t=25ns, we can determine that to charge 5000pf to 25 volts in 25ns will take a constant current of 5a. (in reality, the charging current won?t be constant, and will peak somewhere around 8a). supply bypassing in order for our design to turn the load on properly, the ixd_514 must be able to draw this 5a of current from the power supply in the 25ns. this means that there must be very low impedance between the driver and the power supply. the most common method of achieving this low impedance is to bypass the power supply at the driver with a capacitance value that is an order of magnitude larger than the load capacitance. usually, this would be achieved by placing two different types of bypassing capacitors, with complementary impedance curves, very close to the driver itself. (these capacitors should be carefully selected and should have low inductance, low resistance and high-pulse current-service ratings). lead lengths may radiate at high frequency due to inductance, so care should be taken to keep the lengths of the leads between these bypass capacitors and the ixd_514 to an absolute minimum. grounding in order for the design to turn the load off properly, the ixd_514 must be able to drain this 5a of current into an adequate grounding system. there are three paths for returning current that need to be considered: path #1 is between the ixd_514 and its load. path #2 is between the ixd_514 and its power supply. path #3 is between the ixd_514 and whatever logic is driving it. all three of these paths should be as low in resistance and inductance as possible, and thus as short as practical. in addition, every effort should be made to keep these three ground paths distinctly separate. otherwise, the returning ground current from the load may develop a voltage that would have a detrimental effect on the logic line driving the ixd_514. output lead inductance of equal importance to supply bypassing and grounding are issues related to the output lead inductance. every effort should be made to keep the leads between the driver and its load as short and wide as possible. if the driver must be placed farther than 2? (5mm) from the load, then the output leads should be treated as transmission lines. in this case, a twisted- pair should be considered, and the return line of each twisted pair should be placed as close as possible to the ground pin of the driver, and connected directly to the ground terminal of the load. supply bypassing, grounding practices and output lead inductance note: solder tabs on bottoms of dfn packages are grounded 8 pin dip (pi) 8 pin soic (sia) vcc in nc gnd vcc out out 1 2 3 4 8 7 6 5 i x d i 5 1 4 gnd 8 pin dip (pi) 8 pin soic (sia) vcc in nc gnd vcc out out 1 2 3 4 8 7 6 5 i x d n 5 1 4 gnd 6 lead dfn (d1) (bottom view) in n/c gnd vcc gnd out 1 2 3 6 5 4 i x d n 5 1 4 6 lead dfn (d1) (bottom view) in n/c gnd vcc gnd out 1 2 3 6 5 4 i x d i 5 1 4
12 copyright ? 2006 ixys corporation all rights reserved ixdi514 / ixdn514 ixys semiconductor gmbh edisonstrasse15 ; d-68623; lampertheim tel: +49-6206-503-0; fax: +49-6206-503627 e-mail: marcom@ixys.de ixys corporation 3540 bassett st; santa clara, ca 95054 tel: 408-982-0700; fax: 408-496-0670 e-mail: sales@ixys.net www.ixys.com h e e a a1 b d d c l h x 45 h h l e e b c m n m n e1 e ea l eb e d d1 c b3 b2 b a2 0.018 [0.47] 0 . 0 2 0 [ 0 . 5 1 ] 0 . 0 1 9 [ 0 . 4 9 ] 0 . 0 3 9 [ 1 . 0 0 ] 0 . 1 5 7 0 . 0 0 5 [ 3 . 9 9 0 . 1 3 ] 0.1970.005 [5.000.13] 0 . 1 2 0 [ 3 . 0 5 ] 0.100 [2.54] 0.137 [3.48] s0.002^0.000; o s0.05^0.00;o [] 0.035 [0.90] preliminary technical information the product presented herein is under development. the technical specifications offered are derived from data gathered during objective characterizations of preliminary engineering lots; but also may yet contain some information supplied during a pre-production design evaluation. ixys reserves the right to change limits, test conditions, and dimensions without notice.

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